opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_VexR (int, int);
  92 static void OP_VexW (int, int);
  93 static void OP_Rounding (int, int);
  94 static void OP_REG_VexI4 (int, int);
  95 static void OP_VexI4 (int, int);
  96 static void PCLMUL_Fixup (int, int);
  97 static void VPCMP_Fixup (int, int);
  98 static void VPCOM_Fixup (int, int);
  99 static void OP_0f07 (int, int);
 100 static void OP_Monitor (int, int);
 101 static void OP_Mwait (int, int);
 102 static void NOP_Fixup1 (int, int);
 103 static void NOP_Fixup2 (int, int);
 104 static void OP_3DNowSuffix (int, int);
 105 static void CMP_Fixup (int, int);
 106 static void BadOp (void);
 107 static void REP_Fixup (int, int);
 108 static void SEP_Fixup (int, int);
 109 static void BND_Fixup (int, int);
 110 static void NOTRACK_Fixup (int, int);
 111 static void HLE_Fixup1 (int, int);
 112 static void HLE_Fixup2 (int, int);
 113 static void HLE_Fixup3 (int, int);
 114 static void CMPXCHG8B_Fixup (int, int);
 115 static void XMM_Fixup (int, int);
 116 static void FXSAVE_Fixup (int, int);
 117
 118 static void MOVSXD_Fixup (int, int);
 119
 120 static void OP_Mask (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   OPCODES_SIGJMP_BUF bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* Mark parts used in the REX prefix.  When we are testing for
 148    empty prefix (for 8bit register REX extension), just mask it
 149    out.  Otherwise test for REX bit is excuse for existence of REX
 150    only in case value is nonzero.  */
 151 #define USED_REX(value)                                 \
 152   {                                                     \
 153     if (value)                                          \
 154       {                                                 \
 155         if ((rex & value))                              \
 156           rex_used |= (value) | REX_OPCODE;             \
 157       }                                                 \
 158     else                                                \
 159       rex_used |= REX_OPCODE;                           \
 160   }
 161
 162 /* Flags for prefixes which we somehow handled when printing the
 163    current instruction.  */
 164 static int used_prefixes;
 165
 166 /* Flags stored in PREFIXES.  */
 167 #define PREFIX_REPZ 1
 168 #define PREFIX_REPNZ 2
 169 #define PREFIX_LOCK 4
 170 #define PREFIX_CS 8
 171 #define PREFIX_SS 0x10
 172 #define PREFIX_DS 0x20
 173 #define PREFIX_ES 0x40
 174 #define PREFIX_FS 0x80
 175 #define PREFIX_GS 0x100
 176 #define PREFIX_DATA 0x200
 177 #define PREFIX_ADDR 0x400
 178 #define PREFIX_FWAIT 0x800
 179
 180 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 181    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 182    on error.  */
 183 #define FETCH_DATA(info, addr) \
 184   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 185    ? 1 : fetch_data ((info), (addr)))
 186
 187 static int
 188 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 189 {
 190   int status;
 191   struct dis_private *priv = (struct dis_private *) info->private_data;
 192   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 193
 194   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 195     status = (*info->read_memory_func) (start,
 196                                         priv->max_fetched,
 197                                         addr - priv->max_fetched,
 198                                         info);
 199   else
 200     status = -1;
 201   if (status != 0)
 202     {
 203       /* If we did manage to read at least one byte, then
 204          print_insn_i386 will do something sensible.  Otherwise, print
 205          an error.  We do that here because this is where we know
 206          STATUS.  */
 207       if (priv->max_fetched == priv->the_buffer)
 208         (*info->memory_error_func) (status, start, info);
 209       OPCODES_SIGLONGJMP (priv->bailout, 1);
 210     }
 211   else
 212     priv->max_fetched = addr;
 213   return 1;
 214 }
 215
 216 /* Possible values for prefix requirement.  */
 217 #define PREFIX_IGNORED_SHIFT    16
 218 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 219 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 222 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 223
 224 /* Opcode prefixes.  */
 225 #define PREFIX_OPCODE           (PREFIX_REPZ \
 226                                  | PREFIX_REPNZ \
 227                                  | PREFIX_DATA)
 228
 229 /* Prefixes ignored.  */
 230 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 231                                  | PREFIX_IGNORED_REPNZ \
 232                                  | PREFIX_IGNORED_DATA)
 233
 234 #define XX { NULL, 0 }
 235 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 236
 237 #define Eb { OP_E, b_mode }
 238 #define Ebnd { OP_E, bnd_mode }
 239 #define EbS { OP_E, b_swap_mode }
 240 #define EbndS { OP_E, bnd_swap_mode }
 241 #define Ev { OP_E, v_mode }
 242 #define Eva { OP_E, va_mode }
 243 #define Ev_bnd { OP_E, v_bnd_mode }
 244 #define EvS { OP_E, v_swap_mode }
 245 #define Ed { OP_E, d_mode }
 246 #define Edq { OP_E, dq_mode }
 247 #define Edqw { OP_E, dqw_mode }
 248 #define Edqb { OP_E, dqb_mode }
 249 #define Edb { OP_E, db_mode }
 250 #define Edw { OP_E, dw_mode }
 251 #define Edqd { OP_E, dqd_mode }
 252 #define Eq { OP_E, q_mode }
 253 #define indirEv { OP_indirE, indir_v_mode }
 254 #define indirEp { OP_indirE, f_mode }
 255 #define stackEv { OP_E, stack_v_mode }
 256 #define Em { OP_E, m_mode }
 257 #define Ew { OP_E, w_mode }
 258 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 259 #define Ma { OP_M, a_mode }
 260 #define Mb { OP_M, b_mode }
 261 #define Md { OP_M, d_mode }
 262 #define Mo { OP_M, o_mode }
 263 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 264 #define Mq { OP_M, q_mode }
 265 #define Mv { OP_M, v_mode }
 266 #define Mv_bnd { OP_M, v_bndmk_mode }
 267 #define Mx { OP_M, x_mode }
 268 #define Mxmm { OP_M, xmm_mode }
 269 #define Gb { OP_G, b_mode }
 270 #define Gbnd { OP_G, bnd_mode }
 271 #define Gv { OP_G, v_mode }
 272 #define Gd { OP_G, d_mode }
 273 #define Gdq { OP_G, dq_mode }
 274 #define Gm { OP_G, m_mode }
 275 #define Gva { OP_G, va_mode }
 276 #define Gw { OP_G, w_mode }
 277 #define Rd { OP_R, d_mode }
 278 #define Rdq { OP_R, dq_mode }
 279 #define Rm { OP_R, m_mode }
 280 #define Ib { OP_I, b_mode }
 281 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 282 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 283 #define Iv { OP_I, v_mode }
 284 #define sIv { OP_sI, v_mode }
 285 #define Iv64 { OP_I64, v_mode }
 286 #define Id { OP_I, d_mode }
 287 #define Iw { OP_I, w_mode }
 288 #define I1 { OP_I, const_1_mode }
 289 #define Jb { OP_J, b_mode }
 290 #define Jv { OP_J, v_mode }
 291 #define Jdqw { OP_J, dqw_mode }
 292 #define Cm { OP_C, m_mode }
 293 #define Dm { OP_D, m_mode }
 294 #define Td { OP_T, d_mode }
 295 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 296
 297 #define RMeAX { OP_REG, eAX_reg }
 298 #define RMeBX { OP_REG, eBX_reg }
 299 #define RMeCX { OP_REG, eCX_reg }
 300 #define RMeDX { OP_REG, eDX_reg }
 301 #define RMeSP { OP_REG, eSP_reg }
 302 #define RMeBP { OP_REG, eBP_reg }
 303 #define RMeSI { OP_REG, eSI_reg }
 304 #define RMeDI { OP_REG, eDI_reg }
 305 #define RMrAX { OP_REG, rAX_reg }
 306 #define RMrBX { OP_REG, rBX_reg }
 307 #define RMrCX { OP_REG, rCX_reg }
 308 #define RMrDX { OP_REG, rDX_reg }
 309 #define RMrSP { OP_REG, rSP_reg }
 310 #define RMrBP { OP_REG, rBP_reg }
 311 #define RMrSI { OP_REG, rSI_reg }
 312 #define RMrDI { OP_REG, rDI_reg }
 313 #define RMAL { OP_REG, al_reg }
 314 #define RMCL { OP_REG, cl_reg }
 315 #define RMDL { OP_REG, dl_reg }
 316 #define RMBL { OP_REG, bl_reg }
 317 #define RMAH { OP_REG, ah_reg }
 318 #define RMCH { OP_REG, ch_reg }
 319 #define RMDH { OP_REG, dh_reg }
 320 #define RMBH { OP_REG, bh_reg }
 321 #define RMAX { OP_REG, ax_reg }
 322 #define RMDX { OP_REG, dx_reg }
 323
 324 #define eAX { OP_IMREG, eAX_reg }
 325 #define AL { OP_IMREG, al_reg }
 326 #define CL { OP_IMREG, cl_reg }
 327 #define zAX { OP_IMREG, z_mode_ax_reg }
 328 #define indirDX { OP_IMREG, indir_dx_reg }
 329
 330 #define Sw { OP_SEG, w_mode }
 331 #define Sv { OP_SEG, v_mode }
 332 #define Ap { OP_DIR, 0 }
 333 #define Ob { OP_OFF64, b_mode }
 334 #define Ov { OP_OFF64, v_mode }
 335 #define Xb { OP_DSreg, eSI_reg }
 336 #define Xv { OP_DSreg, eSI_reg }
 337 #define Xz { OP_DSreg, eSI_reg }
 338 #define Yb { OP_ESreg, eDI_reg }
 339 #define Yv { OP_ESreg, eDI_reg }
 340 #define DSBX { OP_DSreg, eBX_reg }
 341
 342 #define es { OP_REG, es_reg }
 343 #define ss { OP_REG, ss_reg }
 344 #define cs { OP_REG, cs_reg }
 345 #define ds { OP_REG, ds_reg }
 346 #define fs { OP_REG, fs_reg }
 347 #define gs { OP_REG, gs_reg }
 348
 349 #define MX { OP_MMX, 0 }
 350 #define XM { OP_XMM, 0 }
 351 #define XMScalar { OP_XMM, scalar_mode }
 352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 353 #define XMM { OP_XMM, xmm_mode }
 354 #define TMM { OP_XMM, tmm_mode }
 355 #define XMxmmq { OP_XMM, xmmq_mode }
 356 #define EM { OP_EM, v_mode }
 357 #define EMS { OP_EM, v_swap_mode }
 358 #define EMd { OP_EM, d_mode }
 359 #define EMx { OP_EM, x_mode }
 360 #define EXbwUnit { OP_EX, bw_unit_mode }
 361 #define EXw { OP_EX, w_mode }
 362 #define EXd { OP_EX, d_mode }
 363 #define EXdS { OP_EX, d_swap_mode }
 364 #define EXq { OP_EX, q_mode }
 365 #define EXqS { OP_EX, q_swap_mode }
 366 #define EXx { OP_EX, x_mode }
 367 #define EXxS { OP_EX, x_swap_mode }
 368 #define EXxmm { OP_EX, xmm_mode }
 369 #define EXymm { OP_EX, ymm_mode }
 370 #define EXtmm { OP_EX, tmm_mode }
 371 #define EXxmmq { OP_EX, xmmq_mode }
 372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 375 #define EXxmm_md { OP_EX, xmm_md_mode }
 376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 377 #define EXxmmdw { OP_EX, xmmdw_mode }
 378 #define EXxmmqd { OP_EX, xmmqd_mode }
 379 #define EXymmq { OP_EX, ymmq_mode }
 380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 383 #define MS { OP_MS, v_mode }
 384 #define XS { OP_XS, v_mode }
 385 #define EMCq { OP_EMC, q_mode }
 386 #define MXC { OP_MXC, 0 }
 387 #define OPSUF { OP_3DNowSuffix, 0 }
 388 #define SEP { SEP_Fixup, 0 }
 389 #define CMP { CMP_Fixup, 0 }
 390 #define XMM0 { XMM_Fixup, 0 }
 391 #define FXSAVE { FXSAVE_Fixup, 0 }
 392
 393 #define Vex { OP_VEX, vex_mode }
 394 #define VexW { OP_VexW, vex_mode }
 395 #define VexScalar { OP_VEX, vex_scalar_mode }
 396 #define VexScalarR { OP_VexR, vex_scalar_mode }
 397 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 398 #define VexGdq { OP_VEX, dq_mode }
 399 #define VexTmm { OP_VEX, tmm_mode }
 400 #define XMVexI4 { OP_REG_VexI4, x_mode }
 401 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 402 #define VexI4 { OP_VexI4, 0 }
 403 #define PCLMUL { PCLMUL_Fixup, 0 }
 404 #define VPCMP { VPCMP_Fixup, 0 }
 405 #define VPCOM { VPCOM_Fixup, 0 }
 406
 407 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 408 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 409 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 410
 411 #define XMask { OP_Mask, mask_mode }
 412 #define MaskG { OP_G, mask_mode }
 413 #define MaskE { OP_E, mask_mode }
 414 #define MaskBDE { OP_E, mask_bd_mode }
 415 #define MaskR { OP_R, mask_mode }
 416 #define MaskVex { OP_VEX, mask_mode }
 417
 418 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 419 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 420 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 421 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 422
 423 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 424
 425 /* Used handle "rep" prefix for string instructions.  */
 426 #define Xbr { REP_Fixup, eSI_reg }
 427 #define Xvr { REP_Fixup, eSI_reg }
 428 #define Ybr { REP_Fixup, eDI_reg }
 429 #define Yvr { REP_Fixup, eDI_reg }
 430 #define Yzr { REP_Fixup, eDI_reg }
 431 #define indirDXr { REP_Fixup, indir_dx_reg }
 432 #define ALr { REP_Fixup, al_reg }
 433 #define eAXr { REP_Fixup, eAX_reg }
 434
 435 /* Used handle HLE prefix for lockable instructions.  */
 436 #define Ebh1 { HLE_Fixup1, b_mode }
 437 #define Evh1 { HLE_Fixup1, v_mode }
 438 #define Ebh2 { HLE_Fixup2, b_mode }
 439 #define Evh2 { HLE_Fixup2, v_mode }
 440 #define Ebh3 { HLE_Fixup3, b_mode }
 441 #define Evh3 { HLE_Fixup3, v_mode }
 442
 443 #define BND { BND_Fixup, 0 }
 444 #define NOTRACK { NOTRACK_Fixup, 0 }
 445
 446 #define cond_jump_flag { NULL, cond_jump_mode }
 447 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 448
 449 /* bits in sizeflag */
 450 #define SUFFIX_ALWAYS 4
 451 #define AFLAG 2
 452 #define DFLAG 1
 453
 454 enum
 455 {
 456   /* byte operand */
 457   b_mode = 1,
 458   /* byte operand with operand swapped */
 459   b_swap_mode,
 460   /* byte operand, sign extend like 'T' suffix */
 461   b_T_mode,
 462   /* operand size depends on prefixes */
 463   v_mode,
 464   /* operand size depends on prefixes with operand swapped */
 465   v_swap_mode,
 466   /* operand size depends on address prefix */
 467   va_mode,
 468   /* word operand */
 469   w_mode,
 470   /* double word operand  */
 471   d_mode,
 472   /* double word operand with operand swapped */
 473   d_swap_mode,
 474   /* quad word operand */
 475   q_mode,
 476   /* quad word operand with operand swapped */
 477   q_swap_mode,
 478   /* ten-byte operand */
 479   t_mode,
 480   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 481      broadcast enabled.  */
 482   x_mode,
 483   /* Similar to x_mode, but with different EVEX mem shifts.  */
 484   evex_x_gscat_mode,
 485   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 486   bw_unit_mode,
 487   /* Similar to x_mode, but with disabled broadcast.  */
 488   evex_x_nobcst_mode,
 489   /* Similar to x_mode, but with operands swapped and disabled broadcast
 490      in EVEX.  */
 491   x_swap_mode,
 492   /* 16-byte XMM operand */
 493   xmm_mode,
 494   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 495      memory operand (depending on vector length).  Broadcast isn't
 496      allowed.  */
 497   xmmq_mode,
 498   /* Same as xmmq_mode, but broadcast is allowed.  */
 499   evex_half_bcst_xmmq_mode,
 500   /* XMM register or byte memory operand */
 501   xmm_mb_mode,
 502   /* XMM register or word memory operand */
 503   xmm_mw_mode,
 504   /* XMM register or double word memory operand */
 505   xmm_md_mode,
 506   /* XMM register or quad word memory operand */
 507   xmm_mq_mode,
 508   /* 16-byte XMM, word, double word or quad word operand.  */
 509   xmmdw_mode,
 510   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 511   xmmqd_mode,
 512   /* 32-byte YMM operand */
 513   ymm_mode,
 514   /* quad word, ymmword or zmmword memory operand.  */
 515   ymmq_mode,
 516   /* 32-byte YMM or 16-byte word operand */
 517   ymmxmm_mode,
 518   /* TMM operand */
 519   tmm_mode,
 520   /* d_mode in 32bit, q_mode in 64bit mode.  */
 521   m_mode,
 522   /* pair of v_mode operands */
 523   a_mode,
 524   cond_jump_mode,
 525   loop_jcxz_mode,
 526   movsxd_mode,
 527   v_bnd_mode,
 528   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 529   v_bndmk_mode,
 530   /* operand size depends on REX prefixes.  */
 531   dq_mode,
 532   /* registers like dq_mode, memory like w_mode, displacements like
 533      v_mode without considering Intel64 ISA.  */
 534   dqw_mode,
 535   /* bounds operand */
 536   bnd_mode,
 537   /* bounds operand with operand swapped */
 538   bnd_swap_mode,
 539   /* 4- or 6-byte pointer operand */
 540   f_mode,
 541   const_1_mode,
 542   /* v_mode for indirect branch opcodes.  */
 543   indir_v_mode,
 544   /* v_mode for stack-related opcodes.  */
 545   stack_v_mode,
 546   /* non-quad operand size depends on prefixes */
 547   z_mode,
 548   /* 16-byte operand */
 549   o_mode,
 550   /* registers like dq_mode, memory like b_mode.  */
 551   dqb_mode,
 552   /* registers like d_mode, memory like b_mode.  */
 553   db_mode,
 554   /* registers like d_mode, memory like w_mode.  */
 555   dw_mode,
 556   /* registers like dq_mode, memory like d_mode.  */
 557   dqd_mode,
 558   /* normal vex mode */
 559   vex_mode,
 560
 561   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 562   vex_vsib_d_w_dq_mode,
 563   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 564   vex_vsib_d_w_d_mode,
 565   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 566   vex_vsib_q_w_dq_mode,
 567   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 568   vex_vsib_q_w_d_mode,
 569   /* mandatory non-vector SIB.  */
 570   vex_sibmem_mode,
 571
 572   /* scalar, ignore vector length.  */
 573   scalar_mode,
 574   /* like vex_mode, ignore vector length.  */
 575   vex_scalar_mode,
 576   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 577   vex_scalar_w_dq_mode,
 578
 579   /* Static rounding.  */
 580   evex_rounding_mode,
 581   /* Static rounding, 64-bit mode only.  */
 582   evex_rounding_64_mode,
 583   /* Supress all exceptions.  */
 584   evex_sae_mode,
 585
 586   /* Mask register operand.  */
 587   mask_mode,
 588   /* Mask register operand.  */
 589   mask_bd_mode,
 590
 591   es_reg,
 592   cs_reg,
 593   ss_reg,
 594   ds_reg,
 595   fs_reg,
 596   gs_reg,
 597
 598   eAX_reg,
 599   eCX_reg,
 600   eDX_reg,
 601   eBX_reg,
 602   eSP_reg,
 603   eBP_reg,
 604   eSI_reg,
 605   eDI_reg,
 606
 607   al_reg,
 608   cl_reg,
 609   dl_reg,
 610   bl_reg,
 611   ah_reg,
 612   ch_reg,
 613   dh_reg,
 614   bh_reg,
 615
 616   ax_reg,
 617   cx_reg,
 618   dx_reg,
 619   bx_reg,
 620   sp_reg,
 621   bp_reg,
 622   si_reg,
 623   di_reg,
 624
 625   rAX_reg,
 626   rCX_reg,
 627   rDX_reg,
 628   rBX_reg,
 629   rSP_reg,
 630   rBP_reg,
 631   rSI_reg,
 632   rDI_reg,
 633
 634   z_mode_ax_reg,
 635   indir_dx_reg
 636 };
 637
 638 enum
 639 {
 640   FLOATCODE = 1,
 641   USE_REG_TABLE,
 642   USE_MOD_TABLE,
 643   USE_RM_TABLE,
 644   USE_PREFIX_TABLE,
 645   USE_X86_64_TABLE,
 646   USE_3BYTE_TABLE,
 647   USE_XOP_8F_TABLE,
 648   USE_VEX_C4_TABLE,
 649   USE_VEX_C5_TABLE,
 650   USE_VEX_LEN_TABLE,
 651   USE_VEX_W_TABLE,
 652   USE_EVEX_TABLE,
 653   USE_EVEX_LEN_TABLE
 654 };
 655
 656 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 657
 658 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 659 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 660 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 661 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 662 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 663 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 664 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 665 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 666 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 667 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 668 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 669 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 670 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 671 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 672 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 673 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 674
 675 enum
 676 {
 677   REG_80 = 0,
 678   REG_81,
 679   REG_83,
 680   REG_8F,
 681   REG_C0,
 682   REG_C1,
 683   REG_C6,
 684   REG_C7,
 685   REG_D0,
 686   REG_D1,
 687   REG_D2,
 688   REG_D3,
 689   REG_F6,
 690   REG_F7,
 691   REG_FE,
 692   REG_FF,
 693   REG_0F00,
 694   REG_0F01,
 695   REG_0F0D,
 696   REG_0F18,
 697   REG_0F1C_P_0_MOD_0,
 698   REG_0F1E_P_1_MOD_3,
 699   REG_0F71,
 700   REG_0F72,
 701   REG_0F73,
 702   REG_0FA6,
 703   REG_0FA7,
 704   REG_0FAE,
 705   REG_0FBA,
 706   REG_0FC7,
 707   REG_VEX_0F71,
 708   REG_VEX_0F72,
 709   REG_VEX_0F73,
 710   REG_VEX_0FAE,
 711   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 712   REG_VEX_0F38F3,
 713
 714   REG_0FXOP_09_01_L_0,
 715   REG_0FXOP_09_02_L_0,
 716   REG_0FXOP_09_12_M_1_L_0,
 717   REG_0FXOP_0A_12_L_0,
 718
 719   REG_EVEX_0F71,
 720   REG_EVEX_0F72,
 721   REG_EVEX_0F73,
 722   REG_EVEX_0F38C6,
 723   REG_EVEX_0F38C7
 724 };
 725
 726 enum
 727 {
 728   MOD_8D = 0,
 729   MOD_C6_REG_7,
 730   MOD_C7_REG_7,
 731   MOD_FF_REG_3,
 732   MOD_FF_REG_5,
 733   MOD_0F01_REG_0,
 734   MOD_0F01_REG_1,
 735   MOD_0F01_REG_2,
 736   MOD_0F01_REG_3,
 737   MOD_0F01_REG_5,
 738   MOD_0F01_REG_7,
 739   MOD_0F12_PREFIX_0,
 740   MOD_0F12_PREFIX_2,
 741   MOD_0F13,
 742   MOD_0F16_PREFIX_0,
 743   MOD_0F16_PREFIX_2,
 744   MOD_0F17,
 745   MOD_0F18_REG_0,
 746   MOD_0F18_REG_1,
 747   MOD_0F18_REG_2,
 748   MOD_0F18_REG_3,
 749   MOD_0F18_REG_4,
 750   MOD_0F18_REG_5,
 751   MOD_0F18_REG_6,
 752   MOD_0F18_REG_7,
 753   MOD_0F1A_PREFIX_0,
 754   MOD_0F1B_PREFIX_0,
 755   MOD_0F1B_PREFIX_1,
 756   MOD_0F1C_PREFIX_0,
 757   MOD_0F1E_PREFIX_1,
 758   MOD_0F24,
 759   MOD_0F26,
 760   MOD_0F2B_PREFIX_0,
 761   MOD_0F2B_PREFIX_1,
 762   MOD_0F2B_PREFIX_2,
 763   MOD_0F2B_PREFIX_3,
 764   MOD_0F50,
 765   MOD_0F71_REG_2,
 766   MOD_0F71_REG_4,
 767   MOD_0F71_REG_6,
 768   MOD_0F72_REG_2,
 769   MOD_0F72_REG_4,
 770   MOD_0F72_REG_6,
 771   MOD_0F73_REG_2,
 772   MOD_0F73_REG_3,
 773   MOD_0F73_REG_6,
 774   MOD_0F73_REG_7,
 775   MOD_0FAE_REG_0,
 776   MOD_0FAE_REG_1,
 777   MOD_0FAE_REG_2,
 778   MOD_0FAE_REG_3,
 779   MOD_0FAE_REG_4,
 780   MOD_0FAE_REG_5,
 781   MOD_0FAE_REG_6,
 782   MOD_0FAE_REG_7,
 783   MOD_0FB2,
 784   MOD_0FB4,
 785   MOD_0FB5,
 786   MOD_0FC3,
 787   MOD_0FC7_REG_3,
 788   MOD_0FC7_REG_4,
 789   MOD_0FC7_REG_5,
 790   MOD_0FC7_REG_6,
 791   MOD_0FC7_REG_7,
 792   MOD_0FD7,
 793   MOD_0FE7_PREFIX_2,
 794   MOD_0FF0_PREFIX_3,
 795   MOD_0F382A_PREFIX_2,
 796   MOD_VEX_0F3849_X86_64_P_0_W_0,
 797   MOD_VEX_0F3849_X86_64_P_2_W_0,
 798   MOD_VEX_0F3849_X86_64_P_3_W_0,
 799   MOD_VEX_0F384B_X86_64_P_1_W_0,
 800   MOD_VEX_0F384B_X86_64_P_2_W_0,
 801   MOD_VEX_0F384B_X86_64_P_3_W_0,
 802   MOD_VEX_0F385C_X86_64_P_1_W_0,
 803   MOD_VEX_0F385E_X86_64_P_0_W_0,
 804   MOD_VEX_0F385E_X86_64_P_1_W_0,
 805   MOD_VEX_0F385E_X86_64_P_2_W_0,
 806   MOD_VEX_0F385E_X86_64_P_3_W_0,
 807   MOD_0F38F5_PREFIX_2,
 808   MOD_0F38F6_PREFIX_0,
 809   MOD_0F38F8_PREFIX_1,
 810   MOD_0F38F8_PREFIX_2,
 811   MOD_0F38F8_PREFIX_3,
 812   MOD_0F38F9_PREFIX_0,
 813   MOD_62_32BIT,
 814   MOD_C4_32BIT,
 815   MOD_C5_32BIT,
 816   MOD_VEX_0F12_PREFIX_0,
 817   MOD_VEX_0F12_PREFIX_2,
 818   MOD_VEX_0F13,
 819   MOD_VEX_0F16_PREFIX_0,
 820   MOD_VEX_0F16_PREFIX_2,
 821   MOD_VEX_0F17,
 822   MOD_VEX_0F2B,
 823   MOD_VEX_W_0_0F41_P_0_LEN_1,
 824   MOD_VEX_W_1_0F41_P_0_LEN_1,
 825   MOD_VEX_W_0_0F41_P_2_LEN_1,
 826   MOD_VEX_W_1_0F41_P_2_LEN_1,
 827   MOD_VEX_W_0_0F42_P_0_LEN_1,
 828   MOD_VEX_W_1_0F42_P_0_LEN_1,
 829   MOD_VEX_W_0_0F42_P_2_LEN_1,
 830   MOD_VEX_W_1_0F42_P_2_LEN_1,
 831   MOD_VEX_W_0_0F44_P_0_LEN_1,
 832   MOD_VEX_W_1_0F44_P_0_LEN_1,
 833   MOD_VEX_W_0_0F44_P_2_LEN_1,
 834   MOD_VEX_W_1_0F44_P_2_LEN_1,
 835   MOD_VEX_W_0_0F45_P_0_LEN_1,
 836   MOD_VEX_W_1_0F45_P_0_LEN_1,
 837   MOD_VEX_W_0_0F45_P_2_LEN_1,
 838   MOD_VEX_W_1_0F45_P_2_LEN_1,
 839   MOD_VEX_W_0_0F46_P_0_LEN_1,
 840   MOD_VEX_W_1_0F46_P_0_LEN_1,
 841   MOD_VEX_W_0_0F46_P_2_LEN_1,
 842   MOD_VEX_W_1_0F46_P_2_LEN_1,
 843   MOD_VEX_W_0_0F47_P_0_LEN_1,
 844   MOD_VEX_W_1_0F47_P_0_LEN_1,
 845   MOD_VEX_W_0_0F47_P_2_LEN_1,
 846   MOD_VEX_W_1_0F47_P_2_LEN_1,
 847   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 848   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 849   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 850   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 851   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 852   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 853   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 854   MOD_VEX_0F50,
 855   MOD_VEX_0F71_REG_2,
 856   MOD_VEX_0F71_REG_4,
 857   MOD_VEX_0F71_REG_6,
 858   MOD_VEX_0F72_REG_2,
 859   MOD_VEX_0F72_REG_4,
 860   MOD_VEX_0F72_REG_6,
 861   MOD_VEX_0F73_REG_2,
 862   MOD_VEX_0F73_REG_3,
 863   MOD_VEX_0F73_REG_6,
 864   MOD_VEX_0F73_REG_7,
 865   MOD_VEX_W_0_0F91_P_0_LEN_0,
 866   MOD_VEX_W_1_0F91_P_0_LEN_0,
 867   MOD_VEX_W_0_0F91_P_2_LEN_0,
 868   MOD_VEX_W_1_0F91_P_2_LEN_0,
 869   MOD_VEX_W_0_0F92_P_0_LEN_0,
 870   MOD_VEX_W_0_0F92_P_2_LEN_0,
 871   MOD_VEX_0F92_P_3_LEN_0,
 872   MOD_VEX_W_0_0F93_P_0_LEN_0,
 873   MOD_VEX_W_0_0F93_P_2_LEN_0,
 874   MOD_VEX_0F93_P_3_LEN_0,
 875   MOD_VEX_W_0_0F98_P_0_LEN_0,
 876   MOD_VEX_W_1_0F98_P_0_LEN_0,
 877   MOD_VEX_W_0_0F98_P_2_LEN_0,
 878   MOD_VEX_W_1_0F98_P_2_LEN_0,
 879   MOD_VEX_W_0_0F99_P_0_LEN_0,
 880   MOD_VEX_W_1_0F99_P_0_LEN_0,
 881   MOD_VEX_W_0_0F99_P_2_LEN_0,
 882   MOD_VEX_W_1_0F99_P_2_LEN_0,
 883   MOD_VEX_0FAE_REG_2,
 884   MOD_VEX_0FAE_REG_3,
 885   MOD_VEX_0FD7_PREFIX_2,
 886   MOD_VEX_0FE7_PREFIX_2,
 887   MOD_VEX_0FF0_PREFIX_3,
 888   MOD_VEX_0F381A_PREFIX_2,
 889   MOD_VEX_0F382A_PREFIX_2,
 890   MOD_VEX_0F382C_PREFIX_2,
 891   MOD_VEX_0F382D_PREFIX_2,
 892   MOD_VEX_0F382E_PREFIX_2,
 893   MOD_VEX_0F382F_PREFIX_2,
 894   MOD_VEX_0F385A_PREFIX_2,
 895   MOD_VEX_0F388C_PREFIX_2,
 896   MOD_VEX_0F388E_PREFIX_2,
 897   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 898   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 899   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 900   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 901   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 902   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 903   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 904   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 905
 906   MOD_VEX_0FXOP_09_12,
 907
 908   MOD_EVEX_0F12_PREFIX_0,
 909   MOD_EVEX_0F12_PREFIX_2,
 910   MOD_EVEX_0F13,
 911   MOD_EVEX_0F16_PREFIX_0,
 912   MOD_EVEX_0F16_PREFIX_2,
 913   MOD_EVEX_0F17,
 914   MOD_EVEX_0F2B,
 915   MOD_EVEX_0F381A_P_2_W_0,
 916   MOD_EVEX_0F381A_P_2_W_1,
 917   MOD_EVEX_0F381B_P_2_W_0,
 918   MOD_EVEX_0F381B_P_2_W_1,
 919   MOD_EVEX_0F385A_P_2_W_0,
 920   MOD_EVEX_0F385A_P_2_W_1,
 921   MOD_EVEX_0F385B_P_2_W_0,
 922   MOD_EVEX_0F385B_P_2_W_1,
 923   MOD_EVEX_0F38C6_REG_1,
 924   MOD_EVEX_0F38C6_REG_2,
 925   MOD_EVEX_0F38C6_REG_5,
 926   MOD_EVEX_0F38C6_REG_6,
 927   MOD_EVEX_0F38C7_REG_1,
 928   MOD_EVEX_0F38C7_REG_2,
 929   MOD_EVEX_0F38C7_REG_5,
 930   MOD_EVEX_0F38C7_REG_6
 931 };
 932
 933 enum
 934 {
 935   RM_C6_REG_7 = 0,
 936   RM_C7_REG_7,
 937   RM_0F01_REG_0,
 938   RM_0F01_REG_1,
 939   RM_0F01_REG_2,
 940   RM_0F01_REG_3,
 941   RM_0F01_REG_5_MOD_3,
 942   RM_0F01_REG_7_MOD_3,
 943   RM_0F1E_P_1_MOD_3_REG_7,
 944   RM_0FAE_REG_6_MOD_3_P_0,
 945   RM_0FAE_REG_7_MOD_3,
 946   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 947 };
 948
 949 enum
 950 {
 951   PREFIX_90 = 0,
 952   PREFIX_0F01_REG_3_RM_1,
 953   PREFIX_0F01_REG_5_MOD_0,
 954   PREFIX_0F01_REG_5_MOD_3_RM_0,
 955   PREFIX_0F01_REG_5_MOD_3_RM_1,
 956   PREFIX_0F01_REG_5_MOD_3_RM_2,
 957   PREFIX_0F01_REG_7_MOD_3_RM_2,
 958   PREFIX_0F01_REG_7_MOD_3_RM_3,
 959   PREFIX_0F09,
 960   PREFIX_0F10,
 961   PREFIX_0F11,
 962   PREFIX_0F12,
 963   PREFIX_0F16,
 964   PREFIX_0F1A,
 965   PREFIX_0F1B,
 966   PREFIX_0F1C,
 967   PREFIX_0F1E,
 968   PREFIX_0F2A,
 969   PREFIX_0F2B,
 970   PREFIX_0F2C,
 971   PREFIX_0F2D,
 972   PREFIX_0F2E,
 973   PREFIX_0F2F,
 974   PREFIX_0F51,
 975   PREFIX_0F52,
 976   PREFIX_0F53,
 977   PREFIX_0F58,
 978   PREFIX_0F59,
 979   PREFIX_0F5A,
 980   PREFIX_0F5B,
 981   PREFIX_0F5C,
 982   PREFIX_0F5D,
 983   PREFIX_0F5E,
 984   PREFIX_0F5F,
 985   PREFIX_0F60,
 986   PREFIX_0F61,
 987   PREFIX_0F62,
 988   PREFIX_0F6C,
 989   PREFIX_0F6D,
 990   PREFIX_0F6F,
 991   PREFIX_0F70,
 992   PREFIX_0F73_REG_3,
 993   PREFIX_0F73_REG_7,
 994   PREFIX_0F78,
 995   PREFIX_0F79,
 996   PREFIX_0F7C,
 997   PREFIX_0F7D,
 998   PREFIX_0F7E,
 999   PREFIX_0F7F,
1000   PREFIX_0FAE_REG_0_MOD_3,
1001   PREFIX_0FAE_REG_1_MOD_3,
1002   PREFIX_0FAE_REG_2_MOD_3,
1003   PREFIX_0FAE_REG_3_MOD_3,
1004   PREFIX_0FAE_REG_4_MOD_0,
1005   PREFIX_0FAE_REG_4_MOD_3,
1006   PREFIX_0FAE_REG_5_MOD_0,
1007   PREFIX_0FAE_REG_5_MOD_3,
1008   PREFIX_0FAE_REG_6_MOD_0,
1009   PREFIX_0FAE_REG_6_MOD_3,
1010   PREFIX_0FAE_REG_7_MOD_0,
1011   PREFIX_0FB8,
1012   PREFIX_0FBC,
1013   PREFIX_0FBD,
1014   PREFIX_0FC2,
1015   PREFIX_0FC3_MOD_0,
1016   PREFIX_0FC7_REG_6_MOD_0,
1017   PREFIX_0FC7_REG_6_MOD_3,
1018   PREFIX_0FC7_REG_7_MOD_3,
1019   PREFIX_0FD0,
1020   PREFIX_0FD6,
1021   PREFIX_0FE6,
1022   PREFIX_0FE7,
1023   PREFIX_0FF0,
1024   PREFIX_0FF7,
1025   PREFIX_0F3810,
1026   PREFIX_0F3814,
1027   PREFIX_0F3815,
1028   PREFIX_0F3817,
1029   PREFIX_0F3820,
1030   PREFIX_0F3821,
1031   PREFIX_0F3822,
1032   PREFIX_0F3823,
1033   PREFIX_0F3824,
1034   PREFIX_0F3825,
1035   PREFIX_0F3828,
1036   PREFIX_0F3829,
1037   PREFIX_0F382A,
1038   PREFIX_0F382B,
1039   PREFIX_0F3830,
1040   PREFIX_0F3831,
1041   PREFIX_0F3832,
1042   PREFIX_0F3833,
1043   PREFIX_0F3834,
1044   PREFIX_0F3835,
1045   PREFIX_0F3837,
1046   PREFIX_0F3838,
1047   PREFIX_0F3839,
1048   PREFIX_0F383A,
1049   PREFIX_0F383B,
1050   PREFIX_0F383C,
1051   PREFIX_0F383D,
1052   PREFIX_0F383E,
1053   PREFIX_0F383F,
1054   PREFIX_0F3840,
1055   PREFIX_0F3841,
1056   PREFIX_0F3880,
1057   PREFIX_0F3881,
1058   PREFIX_0F3882,
1059   PREFIX_0F38C8,
1060   PREFIX_0F38C9,
1061   PREFIX_0F38CA,
1062   PREFIX_0F38CB,
1063   PREFIX_0F38CC,
1064   PREFIX_0F38CD,
1065   PREFIX_0F38CF,
1066   PREFIX_0F38DB,
1067   PREFIX_0F38DC,
1068   PREFIX_0F38DD,
1069   PREFIX_0F38DE,
1070   PREFIX_0F38DF,
1071   PREFIX_0F38F0,
1072   PREFIX_0F38F1,
1073   PREFIX_0F38F5,
1074   PREFIX_0F38F6,
1075   PREFIX_0F38F8,
1076   PREFIX_0F38F9,
1077   PREFIX_0F3A08,
1078   PREFIX_0F3A09,
1079   PREFIX_0F3A0A,
1080   PREFIX_0F3A0B,
1081   PREFIX_0F3A0C,
1082   PREFIX_0F3A0D,
1083   PREFIX_0F3A0E,
1084   PREFIX_0F3A14,
1085   PREFIX_0F3A15,
1086   PREFIX_0F3A16,
1087   PREFIX_0F3A17,
1088   PREFIX_0F3A20,
1089   PREFIX_0F3A21,
1090   PREFIX_0F3A22,
1091   PREFIX_0F3A40,
1092   PREFIX_0F3A41,
1093   PREFIX_0F3A42,
1094   PREFIX_0F3A44,
1095   PREFIX_0F3A60,
1096   PREFIX_0F3A61,
1097   PREFIX_0F3A62,
1098   PREFIX_0F3A63,
1099   PREFIX_0F3ACC,
1100   PREFIX_0F3ACE,
1101   PREFIX_0F3ACF,
1102   PREFIX_0F3ADF,
1103   PREFIX_VEX_0F10,
1104   PREFIX_VEX_0F11,
1105   PREFIX_VEX_0F12,
1106   PREFIX_VEX_0F16,
1107   PREFIX_VEX_0F2A,
1108   PREFIX_VEX_0F2C,
1109   PREFIX_VEX_0F2D,
1110   PREFIX_VEX_0F2E,
1111   PREFIX_VEX_0F2F,
1112   PREFIX_VEX_0F41,
1113   PREFIX_VEX_0F42,
1114   PREFIX_VEX_0F44,
1115   PREFIX_VEX_0F45,
1116   PREFIX_VEX_0F46,
1117   PREFIX_VEX_0F47,
1118   PREFIX_VEX_0F4A,
1119   PREFIX_VEX_0F4B,
1120   PREFIX_VEX_0F51,
1121   PREFIX_VEX_0F52,
1122   PREFIX_VEX_0F53,
1123   PREFIX_VEX_0F58,
1124   PREFIX_VEX_0F59,
1125   PREFIX_VEX_0F5A,
1126   PREFIX_VEX_0F5B,
1127   PREFIX_VEX_0F5C,
1128   PREFIX_VEX_0F5D,
1129   PREFIX_VEX_0F5E,
1130   PREFIX_VEX_0F5F,
1131   PREFIX_VEX_0F60,
1132   PREFIX_VEX_0F61,
1133   PREFIX_VEX_0F62,
1134   PREFIX_VEX_0F63,
1135   PREFIX_VEX_0F64,
1136   PREFIX_VEX_0F65,
1137   PREFIX_VEX_0F66,
1138   PREFIX_VEX_0F67,
1139   PREFIX_VEX_0F68,
1140   PREFIX_VEX_0F69,
1141   PREFIX_VEX_0F6A,
1142   PREFIX_VEX_0F6B,
1143   PREFIX_VEX_0F6C,
1144   PREFIX_VEX_0F6D,
1145   PREFIX_VEX_0F6E,
1146   PREFIX_VEX_0F6F,
1147   PREFIX_VEX_0F70,
1148   PREFIX_VEX_0F71_REG_2,
1149   PREFIX_VEX_0F71_REG_4,
1150   PREFIX_VEX_0F71_REG_6,
1151   PREFIX_VEX_0F72_REG_2,
1152   PREFIX_VEX_0F72_REG_4,
1153   PREFIX_VEX_0F72_REG_6,
1154   PREFIX_VEX_0F73_REG_2,
1155   PREFIX_VEX_0F73_REG_3,
1156   PREFIX_VEX_0F73_REG_6,
1157   PREFIX_VEX_0F73_REG_7,
1158   PREFIX_VEX_0F74,
1159   PREFIX_VEX_0F75,
1160   PREFIX_VEX_0F76,
1161   PREFIX_VEX_0F77,
1162   PREFIX_VEX_0F7C,
1163   PREFIX_VEX_0F7D,
1164   PREFIX_VEX_0F7E,
1165   PREFIX_VEX_0F7F,
1166   PREFIX_VEX_0F90,
1167   PREFIX_VEX_0F91,
1168   PREFIX_VEX_0F92,
1169   PREFIX_VEX_0F93,
1170   PREFIX_VEX_0F98,
1171   PREFIX_VEX_0F99,
1172   PREFIX_VEX_0FC2,
1173   PREFIX_VEX_0FC4,
1174   PREFIX_VEX_0FC5,
1175   PREFIX_VEX_0FD0,
1176   PREFIX_VEX_0FD1,
1177   PREFIX_VEX_0FD2,
1178   PREFIX_VEX_0FD3,
1179   PREFIX_VEX_0FD4,
1180   PREFIX_VEX_0FD5,
1181   PREFIX_VEX_0FD6,
1182   PREFIX_VEX_0FD7,
1183   PREFIX_VEX_0FD8,
1184   PREFIX_VEX_0FD9,
1185   PREFIX_VEX_0FDA,
1186   PREFIX_VEX_0FDB,
1187   PREFIX_VEX_0FDC,
1188   PREFIX_VEX_0FDD,
1189   PREFIX_VEX_0FDE,
1190   PREFIX_VEX_0FDF,
1191   PREFIX_VEX_0FE0,
1192   PREFIX_VEX_0FE1,
1193   PREFIX_VEX_0FE2,
1194   PREFIX_VEX_0FE3,
1195   PREFIX_VEX_0FE4,
1196   PREFIX_VEX_0FE5,
1197   PREFIX_VEX_0FE6,
1198   PREFIX_VEX_0FE7,
1199   PREFIX_VEX_0FE8,
1200   PREFIX_VEX_0FE9,
1201   PREFIX_VEX_0FEA,
1202   PREFIX_VEX_0FEB,
1203   PREFIX_VEX_0FEC,
1204   PREFIX_VEX_0FED,
1205   PREFIX_VEX_0FEE,
1206   PREFIX_VEX_0FEF,
1207   PREFIX_VEX_0FF0,
1208   PREFIX_VEX_0FF1,
1209   PREFIX_VEX_0FF2,
1210   PREFIX_VEX_0FF3,
1211   PREFIX_VEX_0FF4,
1212   PREFIX_VEX_0FF5,
1213   PREFIX_VEX_0FF6,
1214   PREFIX_VEX_0FF7,
1215   PREFIX_VEX_0FF8,
1216   PREFIX_VEX_0FF9,
1217   PREFIX_VEX_0FFA,
1218   PREFIX_VEX_0FFB,
1219   PREFIX_VEX_0FFC,
1220   PREFIX_VEX_0FFD,
1221   PREFIX_VEX_0FFE,
1222   PREFIX_VEX_0F3800,
1223   PREFIX_VEX_0F3801,
1224   PREFIX_VEX_0F3802,
1225   PREFIX_VEX_0F3803,
1226   PREFIX_VEX_0F3804,
1227   PREFIX_VEX_0F3805,
1228   PREFIX_VEX_0F3806,
1229   PREFIX_VEX_0F3807,
1230   PREFIX_VEX_0F3808,
1231   PREFIX_VEX_0F3809,
1232   PREFIX_VEX_0F380A,
1233   PREFIX_VEX_0F380B,
1234   PREFIX_VEX_0F380C,
1235   PREFIX_VEX_0F380D,
1236   PREFIX_VEX_0F380E,
1237   PREFIX_VEX_0F380F,
1238   PREFIX_VEX_0F3813,
1239   PREFIX_VEX_0F3816,
1240   PREFIX_VEX_0F3817,
1241   PREFIX_VEX_0F3818,
1242   PREFIX_VEX_0F3819,
1243   PREFIX_VEX_0F381A,
1244   PREFIX_VEX_0F381C,
1245   PREFIX_VEX_0F381D,
1246   PREFIX_VEX_0F381E,
1247   PREFIX_VEX_0F3820,
1248   PREFIX_VEX_0F3821,
1249   PREFIX_VEX_0F3822,
1250   PREFIX_VEX_0F3823,
1251   PREFIX_VEX_0F3824,
1252   PREFIX_VEX_0F3825,
1253   PREFIX_VEX_0F3828,
1254   PREFIX_VEX_0F3829,
1255   PREFIX_VEX_0F382A,
1256   PREFIX_VEX_0F382B,
1257   PREFIX_VEX_0F382C,
1258   PREFIX_VEX_0F382D,
1259   PREFIX_VEX_0F382E,
1260   PREFIX_VEX_0F382F,
1261   PREFIX_VEX_0F3830,
1262   PREFIX_VEX_0F3831,
1263   PREFIX_VEX_0F3832,
1264   PREFIX_VEX_0F3833,
1265   PREFIX_VEX_0F3834,
1266   PREFIX_VEX_0F3835,
1267   PREFIX_VEX_0F3836,
1268   PREFIX_VEX_0F3837,
1269   PREFIX_VEX_0F3838,
1270   PREFIX_VEX_0F3839,
1271   PREFIX_VEX_0F383A,
1272   PREFIX_VEX_0F383B,
1273   PREFIX_VEX_0F383C,
1274   PREFIX_VEX_0F383D,
1275   PREFIX_VEX_0F383E,
1276   PREFIX_VEX_0F383F,
1277   PREFIX_VEX_0F3840,
1278   PREFIX_VEX_0F3841,
1279   PREFIX_VEX_0F3845,
1280   PREFIX_VEX_0F3846,
1281   PREFIX_VEX_0F3847,
1282   PREFIX_VEX_0F3849_X86_64,
1283   PREFIX_VEX_0F384B_X86_64,
1284   PREFIX_VEX_0F3858,
1285   PREFIX_VEX_0F3859,
1286   PREFIX_VEX_0F385A,
1287   PREFIX_VEX_0F385C_X86_64,
1288   PREFIX_VEX_0F385E_X86_64,
1289   PREFIX_VEX_0F3878,
1290   PREFIX_VEX_0F3879,
1291   PREFIX_VEX_0F388C,
1292   PREFIX_VEX_0F388E,
1293   PREFIX_VEX_0F3890,
1294   PREFIX_VEX_0F3891,
1295   PREFIX_VEX_0F3892,
1296   PREFIX_VEX_0F3893,
1297   PREFIX_VEX_0F3896,
1298   PREFIX_VEX_0F3897,
1299   PREFIX_VEX_0F3898,
1300   PREFIX_VEX_0F3899,
1301   PREFIX_VEX_0F389A,
1302   PREFIX_VEX_0F389B,
1303   PREFIX_VEX_0F389C,
1304   PREFIX_VEX_0F389D,
1305   PREFIX_VEX_0F389E,
1306   PREFIX_VEX_0F389F,
1307   PREFIX_VEX_0F38A6,
1308   PREFIX_VEX_0F38A7,
1309   PREFIX_VEX_0F38A8,
1310   PREFIX_VEX_0F38A9,
1311   PREFIX_VEX_0F38AA,
1312   PREFIX_VEX_0F38AB,
1313   PREFIX_VEX_0F38AC,
1314   PREFIX_VEX_0F38AD,
1315   PREFIX_VEX_0F38AE,
1316   PREFIX_VEX_0F38AF,
1317   PREFIX_VEX_0F38B6,
1318   PREFIX_VEX_0F38B7,
1319   PREFIX_VEX_0F38B8,
1320   PREFIX_VEX_0F38B9,
1321   PREFIX_VEX_0F38BA,
1322   PREFIX_VEX_0F38BB,
1323   PREFIX_VEX_0F38BC,
1324   PREFIX_VEX_0F38BD,
1325   PREFIX_VEX_0F38BE,
1326   PREFIX_VEX_0F38BF,
1327   PREFIX_VEX_0F38CF,
1328   PREFIX_VEX_0F38DB,
1329   PREFIX_VEX_0F38DC,
1330   PREFIX_VEX_0F38DD,
1331   PREFIX_VEX_0F38DE,
1332   PREFIX_VEX_0F38DF,
1333   PREFIX_VEX_0F38F2,
1334   PREFIX_VEX_0F38F3_REG_1,
1335   PREFIX_VEX_0F38F3_REG_2,
1336   PREFIX_VEX_0F38F3_REG_3,
1337   PREFIX_VEX_0F38F5,
1338   PREFIX_VEX_0F38F6,
1339   PREFIX_VEX_0F38F7,
1340   PREFIX_VEX_0F3A00,
1341   PREFIX_VEX_0F3A01,
1342   PREFIX_VEX_0F3A02,
1343   PREFIX_VEX_0F3A04,
1344   PREFIX_VEX_0F3A05,
1345   PREFIX_VEX_0F3A06,
1346   PREFIX_VEX_0F3A08,
1347   PREFIX_VEX_0F3A09,
1348   PREFIX_VEX_0F3A0A,
1349   PREFIX_VEX_0F3A0B,
1350   PREFIX_VEX_0F3A0C,
1351   PREFIX_VEX_0F3A0D,
1352   PREFIX_VEX_0F3A0E,
1353   PREFIX_VEX_0F3A0F,
1354   PREFIX_VEX_0F3A14,
1355   PREFIX_VEX_0F3A15,
1356   PREFIX_VEX_0F3A16,
1357   PREFIX_VEX_0F3A17,
1358   PREFIX_VEX_0F3A18,
1359   PREFIX_VEX_0F3A19,
1360   PREFIX_VEX_0F3A1D,
1361   PREFIX_VEX_0F3A20,
1362   PREFIX_VEX_0F3A21,
1363   PREFIX_VEX_0F3A22,
1364   PREFIX_VEX_0F3A30,
1365   PREFIX_VEX_0F3A31,
1366   PREFIX_VEX_0F3A32,
1367   PREFIX_VEX_0F3A33,
1368   PREFIX_VEX_0F3A38,
1369   PREFIX_VEX_0F3A39,
1370   PREFIX_VEX_0F3A40,
1371   PREFIX_VEX_0F3A41,
1372   PREFIX_VEX_0F3A42,
1373   PREFIX_VEX_0F3A44,
1374   PREFIX_VEX_0F3A46,
1375   PREFIX_VEX_0F3A48,
1376   PREFIX_VEX_0F3A49,
1377   PREFIX_VEX_0F3A4A,
1378   PREFIX_VEX_0F3A4B,
1379   PREFIX_VEX_0F3A4C,
1380   PREFIX_VEX_0F3A5C,
1381   PREFIX_VEX_0F3A5D,
1382   PREFIX_VEX_0F3A5E,
1383   PREFIX_VEX_0F3A5F,
1384   PREFIX_VEX_0F3A60,
1385   PREFIX_VEX_0F3A61,
1386   PREFIX_VEX_0F3A62,
1387   PREFIX_VEX_0F3A63,
1388   PREFIX_VEX_0F3A68,
1389   PREFIX_VEX_0F3A69,
1390   PREFIX_VEX_0F3A6A,
1391   PREFIX_VEX_0F3A6B,
1392   PREFIX_VEX_0F3A6C,
1393   PREFIX_VEX_0F3A6D,
1394   PREFIX_VEX_0F3A6E,
1395   PREFIX_VEX_0F3A6F,
1396   PREFIX_VEX_0F3A78,
1397   PREFIX_VEX_0F3A79,
1398   PREFIX_VEX_0F3A7A,
1399   PREFIX_VEX_0F3A7B,
1400   PREFIX_VEX_0F3A7C,
1401   PREFIX_VEX_0F3A7D,
1402   PREFIX_VEX_0F3A7E,
1403   PREFIX_VEX_0F3A7F,
1404   PREFIX_VEX_0F3ACE,
1405   PREFIX_VEX_0F3ACF,
1406   PREFIX_VEX_0F3ADF,
1407   PREFIX_VEX_0F3AF0,
1408
1409   PREFIX_EVEX_0F10,
1410   PREFIX_EVEX_0F11,
1411   PREFIX_EVEX_0F12,
1412   PREFIX_EVEX_0F16,
1413   PREFIX_EVEX_0F2A,
1414   PREFIX_EVEX_0F2C,
1415   PREFIX_EVEX_0F2D,
1416   PREFIX_EVEX_0F2E,
1417   PREFIX_EVEX_0F2F,
1418   PREFIX_EVEX_0F51,
1419   PREFIX_EVEX_0F58,
1420   PREFIX_EVEX_0F59,
1421   PREFIX_EVEX_0F5A,
1422   PREFIX_EVEX_0F5B,
1423   PREFIX_EVEX_0F5C,
1424   PREFIX_EVEX_0F5D,
1425   PREFIX_EVEX_0F5E,
1426   PREFIX_EVEX_0F5F,
1427   PREFIX_EVEX_0F64,
1428   PREFIX_EVEX_0F65,
1429   PREFIX_EVEX_0F66,
1430   PREFIX_EVEX_0F6E,
1431   PREFIX_EVEX_0F6F,
1432   PREFIX_EVEX_0F70,
1433   PREFIX_EVEX_0F71_REG_2,
1434   PREFIX_EVEX_0F71_REG_4,
1435   PREFIX_EVEX_0F71_REG_6,
1436   PREFIX_EVEX_0F72_REG_0,
1437   PREFIX_EVEX_0F72_REG_1,
1438   PREFIX_EVEX_0F72_REG_2,
1439   PREFIX_EVEX_0F72_REG_4,
1440   PREFIX_EVEX_0F72_REG_6,
1441   PREFIX_EVEX_0F73_REG_2,
1442   PREFIX_EVEX_0F73_REG_3,
1443   PREFIX_EVEX_0F73_REG_6,
1444   PREFIX_EVEX_0F73_REG_7,
1445   PREFIX_EVEX_0F74,
1446   PREFIX_EVEX_0F75,
1447   PREFIX_EVEX_0F76,
1448   PREFIX_EVEX_0F78,
1449   PREFIX_EVEX_0F79,
1450   PREFIX_EVEX_0F7A,
1451   PREFIX_EVEX_0F7B,
1452   PREFIX_EVEX_0F7E,
1453   PREFIX_EVEX_0F7F,
1454   PREFIX_EVEX_0FC2,
1455   PREFIX_EVEX_0FC4,
1456   PREFIX_EVEX_0FC5,
1457   PREFIX_EVEX_0FD6,
1458   PREFIX_EVEX_0FDB,
1459   PREFIX_EVEX_0FDF,
1460   PREFIX_EVEX_0FE2,
1461   PREFIX_EVEX_0FE6,
1462   PREFIX_EVEX_0FE7,
1463   PREFIX_EVEX_0FEB,
1464   PREFIX_EVEX_0FEF,
1465   PREFIX_EVEX_0F380D,
1466   PREFIX_EVEX_0F3810,
1467   PREFIX_EVEX_0F3811,
1468   PREFIX_EVEX_0F3812,
1469   PREFIX_EVEX_0F3813,
1470   PREFIX_EVEX_0F3814,
1471   PREFIX_EVEX_0F3815,
1472   PREFIX_EVEX_0F3816,
1473   PREFIX_EVEX_0F3819,
1474   PREFIX_EVEX_0F381A,
1475   PREFIX_EVEX_0F381B,
1476   PREFIX_EVEX_0F381E,
1477   PREFIX_EVEX_0F381F,
1478   PREFIX_EVEX_0F3820,
1479   PREFIX_EVEX_0F3821,
1480   PREFIX_EVEX_0F3822,
1481   PREFIX_EVEX_0F3823,
1482   PREFIX_EVEX_0F3824,
1483   PREFIX_EVEX_0F3825,
1484   PREFIX_EVEX_0F3826,
1485   PREFIX_EVEX_0F3827,
1486   PREFIX_EVEX_0F3828,
1487   PREFIX_EVEX_0F3829,
1488   PREFIX_EVEX_0F382A,
1489   PREFIX_EVEX_0F382C,
1490   PREFIX_EVEX_0F382D,
1491   PREFIX_EVEX_0F3830,
1492   PREFIX_EVEX_0F3831,
1493   PREFIX_EVEX_0F3832,
1494   PREFIX_EVEX_0F3833,
1495   PREFIX_EVEX_0F3834,
1496   PREFIX_EVEX_0F3835,
1497   PREFIX_EVEX_0F3836,
1498   PREFIX_EVEX_0F3837,
1499   PREFIX_EVEX_0F3838,
1500   PREFIX_EVEX_0F3839,
1501   PREFIX_EVEX_0F383A,
1502   PREFIX_EVEX_0F383B,
1503   PREFIX_EVEX_0F383D,
1504   PREFIX_EVEX_0F383F,
1505   PREFIX_EVEX_0F3840,
1506   PREFIX_EVEX_0F3842,
1507   PREFIX_EVEX_0F3843,
1508   PREFIX_EVEX_0F3844,
1509   PREFIX_EVEX_0F3845,
1510   PREFIX_EVEX_0F3846,
1511   PREFIX_EVEX_0F3847,
1512   PREFIX_EVEX_0F384C,
1513   PREFIX_EVEX_0F384D,
1514   PREFIX_EVEX_0F384E,
1515   PREFIX_EVEX_0F384F,
1516   PREFIX_EVEX_0F3850,
1517   PREFIX_EVEX_0F3851,
1518   PREFIX_EVEX_0F3852,
1519   PREFIX_EVEX_0F3853,
1520   PREFIX_EVEX_0F3854,
1521   PREFIX_EVEX_0F3855,
1522   PREFIX_EVEX_0F3859,
1523   PREFIX_EVEX_0F385A,
1524   PREFIX_EVEX_0F385B,
1525   PREFIX_EVEX_0F3862,
1526   PREFIX_EVEX_0F3863,
1527   PREFIX_EVEX_0F3864,
1528   PREFIX_EVEX_0F3865,
1529   PREFIX_EVEX_0F3866,
1530   PREFIX_EVEX_0F3868,
1531   PREFIX_EVEX_0F3870,
1532   PREFIX_EVEX_0F3871,
1533   PREFIX_EVEX_0F3872,
1534   PREFIX_EVEX_0F3873,
1535   PREFIX_EVEX_0F3875,
1536   PREFIX_EVEX_0F3876,
1537   PREFIX_EVEX_0F3877,
1538   PREFIX_EVEX_0F387A,
1539   PREFIX_EVEX_0F387B,
1540   PREFIX_EVEX_0F387C,
1541   PREFIX_EVEX_0F387D,
1542   PREFIX_EVEX_0F387E,
1543   PREFIX_EVEX_0F387F,
1544   PREFIX_EVEX_0F3883,
1545   PREFIX_EVEX_0F3888,
1546   PREFIX_EVEX_0F3889,
1547   PREFIX_EVEX_0F388A,
1548   PREFIX_EVEX_0F388B,
1549   PREFIX_EVEX_0F388D,
1550   PREFIX_EVEX_0F388F,
1551   PREFIX_EVEX_0F3890,
1552   PREFIX_EVEX_0F3891,
1553   PREFIX_EVEX_0F3892,
1554   PREFIX_EVEX_0F3893,
1555   PREFIX_EVEX_0F389A,
1556   PREFIX_EVEX_0F389B,
1557   PREFIX_EVEX_0F38A0,
1558   PREFIX_EVEX_0F38A1,
1559   PREFIX_EVEX_0F38A2,
1560   PREFIX_EVEX_0F38A3,
1561   PREFIX_EVEX_0F38AA,
1562   PREFIX_EVEX_0F38AB,
1563   PREFIX_EVEX_0F38B4,
1564   PREFIX_EVEX_0F38B5,
1565   PREFIX_EVEX_0F38C4,
1566   PREFIX_EVEX_0F38C6_REG_1,
1567   PREFIX_EVEX_0F38C6_REG_2,
1568   PREFIX_EVEX_0F38C6_REG_5,
1569   PREFIX_EVEX_0F38C6_REG_6,
1570   PREFIX_EVEX_0F38C7_REG_1,
1571   PREFIX_EVEX_0F38C7_REG_2,
1572   PREFIX_EVEX_0F38C7_REG_5,
1573   PREFIX_EVEX_0F38C7_REG_6,
1574   PREFIX_EVEX_0F38C8,
1575   PREFIX_EVEX_0F38CA,
1576   PREFIX_EVEX_0F38CB,
1577   PREFIX_EVEX_0F38CC,
1578   PREFIX_EVEX_0F38CD,
1579
1580   PREFIX_EVEX_0F3A00,
1581   PREFIX_EVEX_0F3A01,
1582   PREFIX_EVEX_0F3A03,
1583   PREFIX_EVEX_0F3A05,
1584   PREFIX_EVEX_0F3A08,
1585   PREFIX_EVEX_0F3A09,
1586   PREFIX_EVEX_0F3A0A,
1587   PREFIX_EVEX_0F3A0B,
1588   PREFIX_EVEX_0F3A14,
1589   PREFIX_EVEX_0F3A15,
1590   PREFIX_EVEX_0F3A16,
1591   PREFIX_EVEX_0F3A17,
1592   PREFIX_EVEX_0F3A18,
1593   PREFIX_EVEX_0F3A19,
1594   PREFIX_EVEX_0F3A1A,
1595   PREFIX_EVEX_0F3A1B,
1596   PREFIX_EVEX_0F3A1E,
1597   PREFIX_EVEX_0F3A1F,
1598   PREFIX_EVEX_0F3A20,
1599   PREFIX_EVEX_0F3A21,
1600   PREFIX_EVEX_0F3A22,
1601   PREFIX_EVEX_0F3A23,
1602   PREFIX_EVEX_0F3A25,
1603   PREFIX_EVEX_0F3A26,
1604   PREFIX_EVEX_0F3A27,
1605   PREFIX_EVEX_0F3A38,
1606   PREFIX_EVEX_0F3A39,
1607   PREFIX_EVEX_0F3A3A,
1608   PREFIX_EVEX_0F3A3B,
1609   PREFIX_EVEX_0F3A3E,
1610   PREFIX_EVEX_0F3A3F,
1611   PREFIX_EVEX_0F3A42,
1612   PREFIX_EVEX_0F3A43,
1613   PREFIX_EVEX_0F3A50,
1614   PREFIX_EVEX_0F3A51,
1615   PREFIX_EVEX_0F3A54,
1616   PREFIX_EVEX_0F3A55,
1617   PREFIX_EVEX_0F3A56,
1618   PREFIX_EVEX_0F3A57,
1619   PREFIX_EVEX_0F3A66,
1620   PREFIX_EVEX_0F3A67,
1621   PREFIX_EVEX_0F3A70,
1622   PREFIX_EVEX_0F3A71,
1623   PREFIX_EVEX_0F3A72,
1624   PREFIX_EVEX_0F3A73,
1625 };
1626
1627 enum
1628 {
1629   X86_64_06 = 0,
1630   X86_64_07,
1631   X86_64_0E,
1632   X86_64_16,
1633   X86_64_17,
1634   X86_64_1E,
1635   X86_64_1F,
1636   X86_64_27,
1637   X86_64_2F,
1638   X86_64_37,
1639   X86_64_3F,
1640   X86_64_60,
1641   X86_64_61,
1642   X86_64_62,
1643   X86_64_63,
1644   X86_64_6D,
1645   X86_64_6F,
1646   X86_64_82,
1647   X86_64_9A,
1648   X86_64_C2,
1649   X86_64_C3,
1650   X86_64_C4,
1651   X86_64_C5,
1652   X86_64_CE,
1653   X86_64_D4,
1654   X86_64_D5,
1655   X86_64_E8,
1656   X86_64_E9,
1657   X86_64_EA,
1658   X86_64_0F01_REG_0,
1659   X86_64_0F01_REG_1,
1660   X86_64_0F01_REG_2,
1661   X86_64_0F01_REG_3,
1662   X86_64_VEX_0F3849,
1663   X86_64_VEX_0F384B,
1664   X86_64_VEX_0F385C,
1665   X86_64_VEX_0F385E
1666 };
1667
1668 enum
1669 {
1670   THREE_BYTE_0F38 = 0,
1671   THREE_BYTE_0F3A
1672 };
1673
1674 enum
1675 {
1676   XOP_08 = 0,
1677   XOP_09,
1678   XOP_0A
1679 };
1680
1681 enum
1682 {
1683   VEX_0F = 0,
1684   VEX_0F38,
1685   VEX_0F3A
1686 };
1687
1688 enum
1689 {
1690   EVEX_0F = 0,
1691   EVEX_0F38,
1692   EVEX_0F3A
1693 };
1694
1695 enum
1696 {
1697   VEX_LEN_0F12_P_0_M_0 = 0,
1698   VEX_LEN_0F12_P_0_M_1,
1699 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1700   VEX_LEN_0F13_M_0,
1701   VEX_LEN_0F16_P_0_M_0,
1702   VEX_LEN_0F16_P_0_M_1,
1703 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1704   VEX_LEN_0F17_M_0,
1705   VEX_LEN_0F41_P_0,
1706   VEX_LEN_0F41_P_2,
1707   VEX_LEN_0F42_P_0,
1708   VEX_LEN_0F42_P_2,
1709   VEX_LEN_0F44_P_0,
1710   VEX_LEN_0F44_P_2,
1711   VEX_LEN_0F45_P_0,
1712   VEX_LEN_0F45_P_2,
1713   VEX_LEN_0F46_P_0,
1714   VEX_LEN_0F46_P_2,
1715   VEX_LEN_0F47_P_0,
1716   VEX_LEN_0F47_P_2,
1717   VEX_LEN_0F4A_P_0,
1718   VEX_LEN_0F4A_P_2,
1719   VEX_LEN_0F4B_P_0,
1720   VEX_LEN_0F4B_P_2,
1721   VEX_LEN_0F6E_P_2,
1722   VEX_LEN_0F77_P_0,
1723   VEX_LEN_0F7E_P_1,
1724   VEX_LEN_0F7E_P_2,
1725   VEX_LEN_0F90_P_0,
1726   VEX_LEN_0F90_P_2,
1727   VEX_LEN_0F91_P_0,
1728   VEX_LEN_0F91_P_2,
1729   VEX_LEN_0F92_P_0,
1730   VEX_LEN_0F92_P_2,
1731   VEX_LEN_0F92_P_3,
1732   VEX_LEN_0F93_P_0,
1733   VEX_LEN_0F93_P_2,
1734   VEX_LEN_0F93_P_3,
1735   VEX_LEN_0F98_P_0,
1736   VEX_LEN_0F98_P_2,
1737   VEX_LEN_0F99_P_0,
1738   VEX_LEN_0F99_P_2,
1739   VEX_LEN_0FAE_R_2_M_0,
1740   VEX_LEN_0FAE_R_3_M_0,
1741   VEX_LEN_0FC4_P_2,
1742   VEX_LEN_0FC5_P_2,
1743   VEX_LEN_0FD6_P_2,
1744   VEX_LEN_0FF7_P_2,
1745   VEX_LEN_0F3816_P_2,
1746   VEX_LEN_0F3819_P_2,
1747   VEX_LEN_0F381A_P_2_M_0,
1748   VEX_LEN_0F3836_P_2,
1749   VEX_LEN_0F3841_P_2,
1750   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1751   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1752   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1753   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1754   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1755   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1756   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1757   VEX_LEN_0F385A_P_2_M_0,
1758   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1759   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1760   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1761   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1762   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1763   VEX_LEN_0F38DB_P_2,
1764   VEX_LEN_0F38F2_P_0,
1765   VEX_LEN_0F38F3_R_1_P_0,
1766   VEX_LEN_0F38F3_R_2_P_0,
1767   VEX_LEN_0F38F3_R_3_P_0,
1768   VEX_LEN_0F38F5_P_0,
1769   VEX_LEN_0F38F5_P_1,
1770   VEX_LEN_0F38F5_P_3,
1771   VEX_LEN_0F38F6_P_3,
1772   VEX_LEN_0F38F7_P_0,
1773   VEX_LEN_0F38F7_P_1,
1774   VEX_LEN_0F38F7_P_2,
1775   VEX_LEN_0F38F7_P_3,
1776   VEX_LEN_0F3A00_P_2,
1777   VEX_LEN_0F3A01_P_2,
1778   VEX_LEN_0F3A06_P_2,
1779   VEX_LEN_0F3A14_P_2,
1780   VEX_LEN_0F3A15_P_2,
1781   VEX_LEN_0F3A16_P_2,
1782   VEX_LEN_0F3A17_P_2,
1783   VEX_LEN_0F3A18_P_2,
1784   VEX_LEN_0F3A19_P_2,
1785   VEX_LEN_0F3A20_P_2,
1786   VEX_LEN_0F3A21_P_2,
1787   VEX_LEN_0F3A22_P_2,
1788   VEX_LEN_0F3A30_P_2,
1789   VEX_LEN_0F3A31_P_2,
1790   VEX_LEN_0F3A32_P_2,
1791   VEX_LEN_0F3A33_P_2,
1792   VEX_LEN_0F3A38_P_2,
1793   VEX_LEN_0F3A39_P_2,
1794   VEX_LEN_0F3A41_P_2,
1795   VEX_LEN_0F3A46_P_2,
1796   VEX_LEN_0F3A60_P_2,
1797   VEX_LEN_0F3A61_P_2,
1798   VEX_LEN_0F3A62_P_2,
1799   VEX_LEN_0F3A63_P_2,
1800   VEX_LEN_0F3ADF_P_2,
1801   VEX_LEN_0F3AF0_P_3,
1802   VEX_LEN_0FXOP_08_85,
1803   VEX_LEN_0FXOP_08_86,
1804   VEX_LEN_0FXOP_08_87,
1805   VEX_LEN_0FXOP_08_8E,
1806   VEX_LEN_0FXOP_08_8F,
1807   VEX_LEN_0FXOP_08_95,
1808   VEX_LEN_0FXOP_08_96,
1809   VEX_LEN_0FXOP_08_97,
1810   VEX_LEN_0FXOP_08_9E,
1811   VEX_LEN_0FXOP_08_9F,
1812   VEX_LEN_0FXOP_08_A3,
1813   VEX_LEN_0FXOP_08_A6,
1814   VEX_LEN_0FXOP_08_B6,
1815   VEX_LEN_0FXOP_08_C0,
1816   VEX_LEN_0FXOP_08_C1,
1817   VEX_LEN_0FXOP_08_C2,
1818   VEX_LEN_0FXOP_08_C3,
1819   VEX_LEN_0FXOP_08_CC,
1820   VEX_LEN_0FXOP_08_CD,
1821   VEX_LEN_0FXOP_08_CE,
1822   VEX_LEN_0FXOP_08_CF,
1823   VEX_LEN_0FXOP_08_EC,
1824   VEX_LEN_0FXOP_08_ED,
1825   VEX_LEN_0FXOP_08_EE,
1826   VEX_LEN_0FXOP_08_EF,
1827   VEX_LEN_0FXOP_09_01,
1828   VEX_LEN_0FXOP_09_02,
1829   VEX_LEN_0FXOP_09_12_M_1,
1830   VEX_LEN_0FXOP_09_82_W_0,
1831   VEX_LEN_0FXOP_09_83_W_0,
1832   VEX_LEN_0FXOP_09_90,
1833   VEX_LEN_0FXOP_09_91,
1834   VEX_LEN_0FXOP_09_92,
1835   VEX_LEN_0FXOP_09_93,
1836   VEX_LEN_0FXOP_09_94,
1837   VEX_LEN_0FXOP_09_95,
1838   VEX_LEN_0FXOP_09_96,
1839   VEX_LEN_0FXOP_09_97,
1840   VEX_LEN_0FXOP_09_98,
1841   VEX_LEN_0FXOP_09_99,
1842   VEX_LEN_0FXOP_09_9A,
1843   VEX_LEN_0FXOP_09_9B,
1844   VEX_LEN_0FXOP_09_C1,
1845   VEX_LEN_0FXOP_09_C2,
1846   VEX_LEN_0FXOP_09_C3,
1847   VEX_LEN_0FXOP_09_C6,
1848   VEX_LEN_0FXOP_09_C7,
1849   VEX_LEN_0FXOP_09_CB,
1850   VEX_LEN_0FXOP_09_D1,
1851   VEX_LEN_0FXOP_09_D2,
1852   VEX_LEN_0FXOP_09_D3,
1853   VEX_LEN_0FXOP_09_D6,
1854   VEX_LEN_0FXOP_09_D7,
1855   VEX_LEN_0FXOP_09_DB,
1856   VEX_LEN_0FXOP_09_E1,
1857   VEX_LEN_0FXOP_09_E2,
1858   VEX_LEN_0FXOP_09_E3,
1859   VEX_LEN_0FXOP_0A_12,
1860 };
1861
1862 enum
1863 {
1864   EVEX_LEN_0F6E_P_2 = 0,
1865   EVEX_LEN_0F7E_P_1,
1866   EVEX_LEN_0F7E_P_2,
1867   EVEX_LEN_0FC4_P_2,
1868   EVEX_LEN_0FC5_P_2,
1869   EVEX_LEN_0FD6_P_2,
1870   EVEX_LEN_0F3816_P_2,
1871   EVEX_LEN_0F3819_P_2_W_0,
1872   EVEX_LEN_0F3819_P_2_W_1,
1873   EVEX_LEN_0F381A_P_2_W_0_M_0,
1874   EVEX_LEN_0F381A_P_2_W_1_M_0,
1875   EVEX_LEN_0F381B_P_2_W_0_M_0,
1876   EVEX_LEN_0F381B_P_2_W_1_M_0,
1877   EVEX_LEN_0F3836_P_2,
1878   EVEX_LEN_0F385A_P_2_W_0_M_0,
1879   EVEX_LEN_0F385A_P_2_W_1_M_0,
1880   EVEX_LEN_0F385B_P_2_W_0_M_0,
1881   EVEX_LEN_0F385B_P_2_W_1_M_0,
1882   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1883   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1884   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1885   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1886   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1887   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1888   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1889   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1890   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1891   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1892   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1893   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1894   EVEX_LEN_0F3A00_P_2_W_1,
1895   EVEX_LEN_0F3A01_P_2_W_1,
1896   EVEX_LEN_0F3A14_P_2,
1897   EVEX_LEN_0F3A15_P_2,
1898   EVEX_LEN_0F3A16_P_2,
1899   EVEX_LEN_0F3A17_P_2,
1900   EVEX_LEN_0F3A18_P_2_W_0,
1901   EVEX_LEN_0F3A18_P_2_W_1,
1902   EVEX_LEN_0F3A19_P_2_W_0,
1903   EVEX_LEN_0F3A19_P_2_W_1,
1904   EVEX_LEN_0F3A1A_P_2_W_0,
1905   EVEX_LEN_0F3A1A_P_2_W_1,
1906   EVEX_LEN_0F3A1B_P_2_W_0,
1907   EVEX_LEN_0F3A1B_P_2_W_1,
1908   EVEX_LEN_0F3A20_P_2,
1909   EVEX_LEN_0F3A21_P_2_W_0,
1910   EVEX_LEN_0F3A22_P_2,
1911   EVEX_LEN_0F3A23_P_2_W_0,
1912   EVEX_LEN_0F3A23_P_2_W_1,
1913   EVEX_LEN_0F3A38_P_2_W_0,
1914   EVEX_LEN_0F3A38_P_2_W_1,
1915   EVEX_LEN_0F3A39_P_2_W_0,
1916   EVEX_LEN_0F3A39_P_2_W_1,
1917   EVEX_LEN_0F3A3A_P_2_W_0,
1918   EVEX_LEN_0F3A3A_P_2_W_1,
1919   EVEX_LEN_0F3A3B_P_2_W_0,
1920   EVEX_LEN_0F3A3B_P_2_W_1,
1921   EVEX_LEN_0F3A43_P_2_W_0,
1922   EVEX_LEN_0F3A43_P_2_W_1
1923 };
1924
1925 enum
1926 {
1927   VEX_W_0F41_P_0_LEN_1 = 0,
1928   VEX_W_0F41_P_2_LEN_1,
1929   VEX_W_0F42_P_0_LEN_1,
1930   VEX_W_0F42_P_2_LEN_1,
1931   VEX_W_0F44_P_0_LEN_0,
1932   VEX_W_0F44_P_2_LEN_0,
1933   VEX_W_0F45_P_0_LEN_1,
1934   VEX_W_0F45_P_2_LEN_1,
1935   VEX_W_0F46_P_0_LEN_1,
1936   VEX_W_0F46_P_2_LEN_1,
1937   VEX_W_0F47_P_0_LEN_1,
1938   VEX_W_0F47_P_2_LEN_1,
1939   VEX_W_0F4A_P_0_LEN_1,
1940   VEX_W_0F4A_P_2_LEN_1,
1941   VEX_W_0F4B_P_0_LEN_1,
1942   VEX_W_0F4B_P_2_LEN_1,
1943   VEX_W_0F90_P_0_LEN_0,
1944   VEX_W_0F90_P_2_LEN_0,
1945   VEX_W_0F91_P_0_LEN_0,
1946   VEX_W_0F91_P_2_LEN_0,
1947   VEX_W_0F92_P_0_LEN_0,
1948   VEX_W_0F92_P_2_LEN_0,
1949   VEX_W_0F93_P_0_LEN_0,
1950   VEX_W_0F93_P_2_LEN_0,
1951   VEX_W_0F98_P_0_LEN_0,
1952   VEX_W_0F98_P_2_LEN_0,
1953   VEX_W_0F99_P_0_LEN_0,
1954   VEX_W_0F99_P_2_LEN_0,
1955   VEX_W_0F380C_P_2,
1956   VEX_W_0F380D_P_2,
1957   VEX_W_0F380E_P_2,
1958   VEX_W_0F380F_P_2,
1959   VEX_W_0F3813_P_2,
1960   VEX_W_0F3816_P_2,
1961   VEX_W_0F3818_P_2,
1962   VEX_W_0F3819_P_2,
1963   VEX_W_0F381A_P_2_M_0_L_0,
1964   VEX_W_0F382C_P_2_M_0,
1965   VEX_W_0F382D_P_2_M_0,
1966   VEX_W_0F382E_P_2_M_0,
1967   VEX_W_0F382F_P_2_M_0,
1968   VEX_W_0F3836_P_2,
1969   VEX_W_0F3846_P_2,
1970   VEX_W_0F3849_X86_64_P_0,
1971   VEX_W_0F3849_X86_64_P_2,
1972   VEX_W_0F3849_X86_64_P_3,
1973   VEX_W_0F384B_X86_64_P_1,
1974   VEX_W_0F384B_X86_64_P_2,
1975   VEX_W_0F384B_X86_64_P_3,
1976   VEX_W_0F3858_P_2,
1977   VEX_W_0F3859_P_2,
1978   VEX_W_0F385A_P_2_M_0_L_0,
1979   VEX_W_0F385C_X86_64_P_1,
1980   VEX_W_0F385E_X86_64_P_0,
1981   VEX_W_0F385E_X86_64_P_1,
1982   VEX_W_0F385E_X86_64_P_2,
1983   VEX_W_0F385E_X86_64_P_3,
1984   VEX_W_0F3878_P_2,
1985   VEX_W_0F3879_P_2,
1986   VEX_W_0F38CF_P_2,
1987   VEX_W_0F3A00_P_2,
1988   VEX_W_0F3A01_P_2,
1989   VEX_W_0F3A02_P_2,
1990   VEX_W_0F3A04_P_2,
1991   VEX_W_0F3A05_P_2,
1992   VEX_W_0F3A06_P_2_L_0,
1993   VEX_W_0F3A18_P_2_L_0,
1994   VEX_W_0F3A19_P_2_L_0,
1995   VEX_W_0F3A1D_P_2,
1996   VEX_W_0F3A30_P_2_LEN_0,
1997   VEX_W_0F3A31_P_2_LEN_0,
1998   VEX_W_0F3A32_P_2_LEN_0,
1999   VEX_W_0F3A33_P_2_LEN_0,
2000   VEX_W_0F3A38_P_2_L_0,
2001   VEX_W_0F3A39_P_2_L_0,
2002   VEX_W_0F3A46_P_2_L_0,
2003   VEX_W_0F3A4A_P_2,
2004   VEX_W_0F3A4B_P_2,
2005   VEX_W_0F3A4C_P_2,
2006   VEX_W_0F3ACE_P_2,
2007   VEX_W_0F3ACF_P_2,
2008
2009   VEX_W_0FXOP_08_85_L_0,
2010   VEX_W_0FXOP_08_86_L_0,
2011   VEX_W_0FXOP_08_87_L_0,
2012   VEX_W_0FXOP_08_8E_L_0,
2013   VEX_W_0FXOP_08_8F_L_0,
2014   VEX_W_0FXOP_08_95_L_0,
2015   VEX_W_0FXOP_08_96_L_0,
2016   VEX_W_0FXOP_08_97_L_0,
2017   VEX_W_0FXOP_08_9E_L_0,
2018   VEX_W_0FXOP_08_9F_L_0,
2019   VEX_W_0FXOP_08_A6_L_0,
2020   VEX_W_0FXOP_08_B6_L_0,
2021   VEX_W_0FXOP_08_C0_L_0,
2022   VEX_W_0FXOP_08_C1_L_0,
2023   VEX_W_0FXOP_08_C2_L_0,
2024   VEX_W_0FXOP_08_C3_L_0,
2025   VEX_W_0FXOP_08_CC_L_0,
2026   VEX_W_0FXOP_08_CD_L_0,
2027   VEX_W_0FXOP_08_CE_L_0,
2028   VEX_W_0FXOP_08_CF_L_0,
2029   VEX_W_0FXOP_08_EC_L_0,
2030   VEX_W_0FXOP_08_ED_L_0,
2031   VEX_W_0FXOP_08_EE_L_0,
2032   VEX_W_0FXOP_08_EF_L_0,
2033
2034   VEX_W_0FXOP_09_80,
2035   VEX_W_0FXOP_09_81,
2036   VEX_W_0FXOP_09_82,
2037   VEX_W_0FXOP_09_83,
2038   VEX_W_0FXOP_09_C1_L_0,
2039   VEX_W_0FXOP_09_C2_L_0,
2040   VEX_W_0FXOP_09_C3_L_0,
2041   VEX_W_0FXOP_09_C6_L_0,
2042   VEX_W_0FXOP_09_C7_L_0,
2043   VEX_W_0FXOP_09_CB_L_0,
2044   VEX_W_0FXOP_09_D1_L_0,
2045   VEX_W_0FXOP_09_D2_L_0,
2046   VEX_W_0FXOP_09_D3_L_0,
2047   VEX_W_0FXOP_09_D6_L_0,
2048   VEX_W_0FXOP_09_D7_L_0,
2049   VEX_W_0FXOP_09_DB_L_0,
2050   VEX_W_0FXOP_09_E1_L_0,
2051   VEX_W_0FXOP_09_E2_L_0,
2052   VEX_W_0FXOP_09_E3_L_0,
2053
2054   EVEX_W_0F10_P_1,
2055   EVEX_W_0F10_P_3,
2056   EVEX_W_0F11_P_1,
2057   EVEX_W_0F11_P_3,
2058   EVEX_W_0F12_P_0_M_1,
2059   EVEX_W_0F12_P_1,
2060   EVEX_W_0F12_P_3,
2061   EVEX_W_0F16_P_0_M_1,
2062   EVEX_W_0F16_P_1,
2063   EVEX_W_0F2A_P_3,
2064   EVEX_W_0F51_P_1,
2065   EVEX_W_0F51_P_3,
2066   EVEX_W_0F58_P_1,
2067   EVEX_W_0F58_P_3,
2068   EVEX_W_0F59_P_1,
2069   EVEX_W_0F59_P_3,
2070   EVEX_W_0F5A_P_0,
2071   EVEX_W_0F5A_P_1,
2072   EVEX_W_0F5A_P_2,
2073   EVEX_W_0F5A_P_3,
2074   EVEX_W_0F5B_P_0,
2075   EVEX_W_0F5B_P_1,
2076   EVEX_W_0F5B_P_2,
2077   EVEX_W_0F5C_P_1,
2078   EVEX_W_0F5C_P_3,
2079   EVEX_W_0F5D_P_1,
2080   EVEX_W_0F5D_P_3,
2081   EVEX_W_0F5E_P_1,
2082   EVEX_W_0F5E_P_3,
2083   EVEX_W_0F5F_P_1,
2084   EVEX_W_0F5F_P_3,
2085   EVEX_W_0F62,
2086   EVEX_W_0F66_P_2,
2087   EVEX_W_0F6A,
2088   EVEX_W_0F6B,
2089   EVEX_W_0F6C,
2090   EVEX_W_0F6D,
2091   EVEX_W_0F6F_P_1,
2092   EVEX_W_0F6F_P_2,
2093   EVEX_W_0F6F_P_3,
2094   EVEX_W_0F70_P_2,
2095   EVEX_W_0F72_R_2_P_2,
2096   EVEX_W_0F72_R_6_P_2,
2097   EVEX_W_0F73_R_2_P_2,
2098   EVEX_W_0F73_R_6_P_2,
2099   EVEX_W_0F76_P_2,
2100   EVEX_W_0F78_P_0,
2101   EVEX_W_0F78_P_2,
2102   EVEX_W_0F79_P_0,
2103   EVEX_W_0F79_P_2,
2104   EVEX_W_0F7A_P_1,
2105   EVEX_W_0F7A_P_2,
2106   EVEX_W_0F7A_P_3,
2107   EVEX_W_0F7B_P_2,
2108   EVEX_W_0F7B_P_3,
2109   EVEX_W_0F7E_P_1,
2110   EVEX_W_0F7F_P_1,
2111   EVEX_W_0F7F_P_2,
2112   EVEX_W_0F7F_P_3,
2113   EVEX_W_0FC2_P_1,
2114   EVEX_W_0FC2_P_3,
2115   EVEX_W_0FD2,
2116   EVEX_W_0FD3,
2117   EVEX_W_0FD4,
2118   EVEX_W_0FD6_P_2,
2119   EVEX_W_0FE6_P_1,
2120   EVEX_W_0FE6_P_2,
2121   EVEX_W_0FE6_P_3,
2122   EVEX_W_0FE7_P_2,
2123   EVEX_W_0FF2,
2124   EVEX_W_0FF3,
2125   EVEX_W_0FF4,
2126   EVEX_W_0FFA,
2127   EVEX_W_0FFB,
2128   EVEX_W_0FFE,
2129   EVEX_W_0F380D_P_2,
2130   EVEX_W_0F3810_P_1,
2131   EVEX_W_0F3810_P_2,
2132   EVEX_W_0F3811_P_1,
2133   EVEX_W_0F3811_P_2,
2134   EVEX_W_0F3812_P_1,
2135   EVEX_W_0F3812_P_2,
2136   EVEX_W_0F3813_P_1,
2137   EVEX_W_0F3813_P_2,
2138   EVEX_W_0F3814_P_1,
2139   EVEX_W_0F3815_P_1,
2140   EVEX_W_0F3819_P_2,
2141   EVEX_W_0F381A_P_2,
2142   EVEX_W_0F381B_P_2,
2143   EVEX_W_0F381E_P_2,
2144   EVEX_W_0F381F_P_2,
2145   EVEX_W_0F3820_P_1,
2146   EVEX_W_0F3821_P_1,
2147   EVEX_W_0F3822_P_1,
2148   EVEX_W_0F3823_P_1,
2149   EVEX_W_0F3824_P_1,
2150   EVEX_W_0F3825_P_1,
2151   EVEX_W_0F3825_P_2,
2152   EVEX_W_0F3828_P_2,
2153   EVEX_W_0F3829_P_2,
2154   EVEX_W_0F382A_P_1,
2155   EVEX_W_0F382A_P_2,
2156   EVEX_W_0F382B,
2157   EVEX_W_0F3830_P_1,
2158   EVEX_W_0F3831_P_1,
2159   EVEX_W_0F3832_P_1,
2160   EVEX_W_0F3833_P_1,
2161   EVEX_W_0F3834_P_1,
2162   EVEX_W_0F3835_P_1,
2163   EVEX_W_0F3835_P_2,
2164   EVEX_W_0F3837_P_2,
2165   EVEX_W_0F383A_P_1,
2166   EVEX_W_0F3852_P_1,
2167   EVEX_W_0F3859_P_2,
2168   EVEX_W_0F385A_P_2,
2169   EVEX_W_0F385B_P_2,
2170   EVEX_W_0F3870_P_2,
2171   EVEX_W_0F3872_P_1,
2172   EVEX_W_0F3872_P_2,
2173   EVEX_W_0F3872_P_3,
2174   EVEX_W_0F387A_P_2,
2175   EVEX_W_0F387B_P_2,
2176   EVEX_W_0F3883_P_2,
2177   EVEX_W_0F3891_P_2,
2178   EVEX_W_0F3893_P_2,
2179   EVEX_W_0F38A1_P_2,
2180   EVEX_W_0F38A3_P_2,
2181   EVEX_W_0F38C7_R_1_P_2,
2182   EVEX_W_0F38C7_R_2_P_2,
2183   EVEX_W_0F38C7_R_5_P_2,
2184   EVEX_W_0F38C7_R_6_P_2,
2185
2186   EVEX_W_0F3A00_P_2,
2187   EVEX_W_0F3A01_P_2,
2188   EVEX_W_0F3A05_P_2,
2189   EVEX_W_0F3A08_P_2,
2190   EVEX_W_0F3A09_P_2,
2191   EVEX_W_0F3A0A_P_2,
2192   EVEX_W_0F3A0B_P_2,
2193   EVEX_W_0F3A18_P_2,
2194   EVEX_W_0F3A19_P_2,
2195   EVEX_W_0F3A1A_P_2,
2196   EVEX_W_0F3A1B_P_2,
2197   EVEX_W_0F3A21_P_2,
2198   EVEX_W_0F3A23_P_2,
2199   EVEX_W_0F3A38_P_2,
2200   EVEX_W_0F3A39_P_2,
2201   EVEX_W_0F3A3A_P_2,
2202   EVEX_W_0F3A3B_P_2,
2203   EVEX_W_0F3A42_P_2,
2204   EVEX_W_0F3A43_P_2,
2205   EVEX_W_0F3A70_P_2,
2206   EVEX_W_0F3A72_P_2,
2207 };
2208
2209 typedef void (*op_rtn) (int bytemode, int sizeflag);
2210
2211 struct dis386 {
2212   const char *name;
2213   struct
2214     {
2215       op_rtn rtn;
2216       int bytemode;
2217     } op[MAX_OPERANDS];
2218   unsigned int prefix_requirement;
2219 };
2220
2221 /* Upper case letters in the instruction names here are macros.
2222    'A' => print 'b' if no register operands or suffix_always is true
2223    'B' => print 'b' if suffix_always is true
2224    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2225           size prefix
2226    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2227           suffix_always is true
2228    'E' => print 'e' if 32-bit form of jcxz
2229    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2230    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2231    'H' => print ",pt" or ",pn" branch hint
2232    'I' unused.
2233    'J' unused.
2234    'K' => print 'd' or 'q' if rex prefix is present.
2235    'L' => print 'l' if suffix_always is true
2236    'M' => print 'r' if intel_mnemonic is false.
2237    'N' => print 'n' if instruction has no wait "prefix"
2238    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2239    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2240           or suffix_always is true.  print 'q' if rex prefix is present.
2241    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2242           is true
2243    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2244    'S' => print 'w', 'l' or 'q' if suffix_always is true
2245    'T' => print 'q' in 64bit mode if instruction has no operand size
2246           prefix and behave as 'P' otherwise
2247    'U' => print 'q' in 64bit mode if instruction has no operand size
2248           prefix and behave as 'Q' otherwise
2249    'V' => print 'q' in 64bit mode if instruction has no operand size
2250           prefix and behave as 'S' otherwise
2251    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2252    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2253    'Y' unused.
2254    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2255    '!' => change condition from true to false or from false to true.
2256    '%' => add 1 upper case letter to the macro.
2257    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2258           prefix or suffix_always is true (lcall/ljmp).
2259    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2260           on operand size prefix.
2261    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2262           has no operand size prefix for AMD64 ISA, behave as 'P'
2263           otherwise
2264
2265    2 upper case letter macros:
2266    "XY" => print 'x' or 'y' if suffix_always is true or no register
2267            operands and no broadcast.
2268    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2269            register operands and no broadcast.
2270    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2271    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
2272            being false, or no operand at all in 64bit mode, or if suffix_always
2273            is true.
2274    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2275    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2276    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2277    "DQ" => print 'd' or 'q' depending on the VEX.W bit
2278    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2279    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2280            an operand size prefix, or suffix_always is true.  print
2281            'q' if rex prefix is present.
2282
2283    Many of the above letters print nothing in Intel mode.  See "putop"
2284    for the details.
2285
2286    Braces '{' and '}', and vertical bars '|', indicate alternative
2287    mnemonic strings for AT&T and Intel.  */
2288
2289 static const struct dis386 dis386[] = {
2290   /* 00 */
2291   { "addB",             { Ebh1, Gb }, 0 },
2292   { "addS",             { Evh1, Gv }, 0 },
2293   { "addB",             { Gb, EbS }, 0 },
2294   { "addS",             { Gv, EvS }, 0 },
2295   { "addB",             { AL, Ib }, 0 },
2296   { "addS",             { eAX, Iv }, 0 },
2297   { X86_64_TABLE (X86_64_06) },
2298   { X86_64_TABLE (X86_64_07) },
2299   /* 08 */
2300   { "orB",              { Ebh1, Gb }, 0 },
2301   { "orS",              { Evh1, Gv }, 0 },
2302   { "orB",              { Gb, EbS }, 0 },
2303   { "orS",              { Gv, EvS }, 0 },
2304   { "orB",              { AL, Ib }, 0 },
2305   { "orS",              { eAX, Iv }, 0 },
2306   { X86_64_TABLE (X86_64_0E) },
2307   { Bad_Opcode },       /* 0x0f extended opcode escape */
2308   /* 10 */
2309   { "adcB",             { Ebh1, Gb }, 0 },
2310   { "adcS",             { Evh1, Gv }, 0 },
2311   { "adcB",             { Gb, EbS }, 0 },
2312   { "adcS",             { Gv, EvS }, 0 },
2313   { "adcB",             { AL, Ib }, 0 },
2314   { "adcS",             { eAX, Iv }, 0 },
2315   { X86_64_TABLE (X86_64_16) },
2316   { X86_64_TABLE (X86_64_17) },
2317   /* 18 */
2318   { "sbbB",             { Ebh1, Gb }, 0 },
2319   { "sbbS",             { Evh1, Gv }, 0 },
2320   { "sbbB",             { Gb, EbS }, 0 },
2321   { "sbbS",             { Gv, EvS }, 0 },
2322   { "sbbB",             { AL, Ib }, 0 },
2323   { "sbbS",             { eAX, Iv }, 0 },
2324   { X86_64_TABLE (X86_64_1E) },
2325   { X86_64_TABLE (X86_64_1F) },
2326   /* 20 */
2327   { "andB",             { Ebh1, Gb }, 0 },
2328   { "andS",             { Evh1, Gv }, 0 },
2329   { "andB",             { Gb, EbS }, 0 },
2330   { "andS",             { Gv, EvS }, 0 },
2331   { "andB",             { AL, Ib }, 0 },
2332   { "andS",             { eAX, Iv }, 0 },
2333   { Bad_Opcode },       /* SEG ES prefix */
2334   { X86_64_TABLE (X86_64_27) },
2335   /* 28 */
2336   { "subB",             { Ebh1, Gb }, 0 },
2337   { "subS",             { Evh1, Gv }, 0 },
2338   { "subB",             { Gb, EbS }, 0 },
2339   { "subS",             { Gv, EvS }, 0 },
2340   { "subB",             { AL, Ib }, 0 },
2341   { "subS",             { eAX, Iv }, 0 },
2342   { Bad_Opcode },       /* SEG CS prefix */
2343   { X86_64_TABLE (X86_64_2F) },
2344   /* 30 */
2345   { "xorB",             { Ebh1, Gb }, 0 },
2346   { "xorS",             { Evh1, Gv }, 0 },
2347   { "xorB",             { Gb, EbS }, 0 },
2348   { "xorS",             { Gv, EvS }, 0 },
2349   { "xorB",             { AL, Ib }, 0 },
2350   { "xorS",             { eAX, Iv }, 0 },
2351   { Bad_Opcode },       /* SEG SS prefix */
2352   { X86_64_TABLE (X86_64_37) },
2353   /* 38 */
2354   { "cmpB",             { Eb, Gb }, 0 },
2355   { "cmpS",             { Ev, Gv }, 0 },
2356   { "cmpB",             { Gb, EbS }, 0 },
2357   { "cmpS",             { Gv, EvS }, 0 },
2358   { "cmpB",             { AL, Ib }, 0 },
2359   { "cmpS",             { eAX, Iv }, 0 },
2360   { Bad_Opcode },       /* SEG DS prefix */
2361   { X86_64_TABLE (X86_64_3F) },
2362   /* 40 */
2363   { "inc{S|}",          { RMeAX }, 0 },
2364   { "inc{S|}",          { RMeCX }, 0 },
2365   { "inc{S|}",          { RMeDX }, 0 },
2366   { "inc{S|}",          { RMeBX }, 0 },
2367   { "inc{S|}",          { RMeSP }, 0 },
2368   { "inc{S|}",          { RMeBP }, 0 },
2369   { "inc{S|}",          { RMeSI }, 0 },
2370   { "inc{S|}",          { RMeDI }, 0 },
2371   /* 48 */
2372   { "dec{S|}",          { RMeAX }, 0 },
2373   { "dec{S|}",          { RMeCX }, 0 },
2374   { "dec{S|}",          { RMeDX }, 0 },
2375   { "dec{S|}",          { RMeBX }, 0 },
2376   { "dec{S|}",          { RMeSP }, 0 },
2377   { "dec{S|}",          { RMeBP }, 0 },
2378   { "dec{S|}",          { RMeSI }, 0 },
2379   { "dec{S|}",          { RMeDI }, 0 },
2380   /* 50 */
2381   { "pushV",            { RMrAX }, 0 },
2382   { "pushV",            { RMrCX }, 0 },
2383   { "pushV",            { RMrDX }, 0 },
2384   { "pushV",            { RMrBX }, 0 },
2385   { "pushV",            { RMrSP }, 0 },
2386   { "pushV",            { RMrBP }, 0 },
2387   { "pushV",            { RMrSI }, 0 },
2388   { "pushV",            { RMrDI }, 0 },
2389   /* 58 */
2390   { "popV",             { RMrAX }, 0 },
2391   { "popV",             { RMrCX }, 0 },
2392   { "popV",             { RMrDX }, 0 },
2393   { "popV",             { RMrBX }, 0 },
2394   { "popV",             { RMrSP }, 0 },
2395   { "popV",             { RMrBP }, 0 },
2396   { "popV",             { RMrSI }, 0 },
2397   { "popV",             { RMrDI }, 0 },
2398   /* 60 */
2399   { X86_64_TABLE (X86_64_60) },
2400   { X86_64_TABLE (X86_64_61) },
2401   { X86_64_TABLE (X86_64_62) },
2402   { X86_64_TABLE (X86_64_63) },
2403   { Bad_Opcode },       /* seg fs */
2404   { Bad_Opcode },       /* seg gs */
2405   { Bad_Opcode },       /* op size prefix */
2406   { Bad_Opcode },       /* adr size prefix */
2407   /* 68 */
2408   { "pushT",            { sIv }, 0 },
2409   { "imulS",            { Gv, Ev, Iv }, 0 },
2410   { "pushT",            { sIbT }, 0 },
2411   { "imulS",            { Gv, Ev, sIb }, 0 },
2412   { "ins{b|}",          { Ybr, indirDX }, 0 },
2413   { X86_64_TABLE (X86_64_6D) },
2414   { "outs{b|}",         { indirDXr, Xb }, 0 },
2415   { X86_64_TABLE (X86_64_6F) },
2416   /* 70 */
2417   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2418   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2419   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2420   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2421   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2422   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2423   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2424   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2425   /* 78 */
2426   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2427   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2428   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2429   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2430   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2431   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2432   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2433   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2434   /* 80 */
2435   { REG_TABLE (REG_80) },
2436   { REG_TABLE (REG_81) },
2437   { X86_64_TABLE (X86_64_82) },
2438   { REG_TABLE (REG_83) },
2439   { "testB",            { Eb, Gb }, 0 },
2440   { "testS",            { Ev, Gv }, 0 },
2441   { "xchgB",            { Ebh2, Gb }, 0 },
2442   { "xchgS",            { Evh2, Gv }, 0 },
2443   /* 88 */
2444   { "movB",             { Ebh3, Gb }, 0 },
2445   { "movS",             { Evh3, Gv }, 0 },
2446   { "movB",             { Gb, EbS }, 0 },
2447   { "movS",             { Gv, EvS }, 0 },
2448   { "movD",             { Sv, Sw }, 0 },
2449   { MOD_TABLE (MOD_8D) },
2450   { "movD",             { Sw, Sv }, 0 },
2451   { REG_TABLE (REG_8F) },
2452   /* 90 */
2453   { PREFIX_TABLE (PREFIX_90) },
2454   { "xchgS",            { RMeCX, eAX }, 0 },
2455   { "xchgS",            { RMeDX, eAX }, 0 },
2456   { "xchgS",            { RMeBX, eAX }, 0 },
2457   { "xchgS",            { RMeSP, eAX }, 0 },
2458   { "xchgS",            { RMeBP, eAX }, 0 },
2459   { "xchgS",            { RMeSI, eAX }, 0 },
2460   { "xchgS",            { RMeDI, eAX }, 0 },
2461   /* 98 */
2462   { "cW{t|}R",          { XX }, 0 },
2463   { "cR{t|}O",          { XX }, 0 },
2464   { X86_64_TABLE (X86_64_9A) },
2465   { Bad_Opcode },       /* fwait */
2466   { "pushfT",           { XX }, 0 },
2467   { "popfT",            { XX }, 0 },
2468   { "sahf",             { XX }, 0 },
2469   { "lahf",             { XX }, 0 },
2470   /* a0 */
2471   { "mov%LB",           { AL, Ob }, 0 },
2472   { "mov%LS",           { eAX, Ov }, 0 },
2473   { "mov%LB",           { Ob, AL }, 0 },
2474   { "mov%LS",           { Ov, eAX }, 0 },
2475   { "movs{b|}",         { Ybr, Xb }, 0 },
2476   { "movs{R|}",         { Yvr, Xv }, 0 },
2477   { "cmps{b|}",         { Xb, Yb }, 0 },
2478   { "cmps{R|}",         { Xv, Yv }, 0 },
2479   /* a8 */
2480   { "testB",            { AL, Ib }, 0 },
2481   { "testS",            { eAX, Iv }, 0 },
2482   { "stosB",            { Ybr, AL }, 0 },
2483   { "stosS",            { Yvr, eAX }, 0 },
2484   { "lodsB",            { ALr, Xb }, 0 },
2485   { "lodsS",            { eAXr, Xv }, 0 },
2486   { "scasB",            { AL, Yb }, 0 },
2487   { "scasS",            { eAX, Yv }, 0 },
2488   /* b0 */
2489   { "movB",             { RMAL, Ib }, 0 },
2490   { "movB",             { RMCL, Ib }, 0 },
2491   { "movB",             { RMDL, Ib }, 0 },
2492   { "movB",             { RMBL, Ib }, 0 },
2493   { "movB",             { RMAH, Ib }, 0 },
2494   { "movB",             { RMCH, Ib }, 0 },
2495   { "movB",             { RMDH, Ib }, 0 },
2496   { "movB",             { RMBH, Ib }, 0 },
2497   /* b8 */
2498   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2499   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2500   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2501   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2502   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2503   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2504   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2505   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2506   /* c0 */
2507   { REG_TABLE (REG_C0) },
2508   { REG_TABLE (REG_C1) },
2509   { X86_64_TABLE (X86_64_C2) },
2510   { X86_64_TABLE (X86_64_C3) },
2511   { X86_64_TABLE (X86_64_C4) },
2512   { X86_64_TABLE (X86_64_C5) },
2513   { REG_TABLE (REG_C6) },
2514   { REG_TABLE (REG_C7) },
2515   /* c8 */
2516   { "enterT",           { Iw, Ib }, 0 },
2517   { "leaveT",           { XX }, 0 },
2518   { "{l|}ret{|f}P",     { Iw }, 0 },
2519   { "{l|}ret{|f}P",     { XX }, 0 },
2520   { "int3",             { XX }, 0 },
2521   { "int",              { Ib }, 0 },
2522   { X86_64_TABLE (X86_64_CE) },
2523   { "iret%LP",          { XX }, 0 },
2524   /* d0 */
2525   { REG_TABLE (REG_D0) },
2526   { REG_TABLE (REG_D1) },
2527   { REG_TABLE (REG_D2) },
2528   { REG_TABLE (REG_D3) },
2529   { X86_64_TABLE (X86_64_D4) },
2530   { X86_64_TABLE (X86_64_D5) },
2531   { Bad_Opcode },
2532   { "xlat",             { DSBX }, 0 },
2533   /* d8 */
2534   { FLOAT },
2535   { FLOAT },
2536   { FLOAT },
2537   { FLOAT },
2538   { FLOAT },
2539   { FLOAT },
2540   { FLOAT },
2541   { FLOAT },
2542   /* e0 */
2543   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2544   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2545   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2546   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2547   { "inB",              { AL, Ib }, 0 },
2548   { "inG",              { zAX, Ib }, 0 },
2549   { "outB",             { Ib, AL }, 0 },
2550   { "outG",             { Ib, zAX }, 0 },
2551   /* e8 */
2552   { X86_64_TABLE (X86_64_E8) },
2553   { X86_64_TABLE (X86_64_E9) },
2554   { X86_64_TABLE (X86_64_EA) },
2555   { "jmp",              { Jb, BND }, 0 },
2556   { "inB",              { AL, indirDX }, 0 },
2557   { "inG",              { zAX, indirDX }, 0 },
2558   { "outB",             { indirDX, AL }, 0 },
2559   { "outG",             { indirDX, zAX }, 0 },
2560   /* f0 */
2561   { Bad_Opcode },       /* lock prefix */
2562   { "icebp",            { XX }, 0 },
2563   { Bad_Opcode },       /* repne */
2564   { Bad_Opcode },       /* repz */
2565   { "hlt",              { XX }, 0 },
2566   { "cmc",              { XX }, 0 },
2567   { REG_TABLE (REG_F6) },
2568   { REG_TABLE (REG_F7) },
2569   /* f8 */
2570   { "clc",              { XX }, 0 },
2571   { "stc",              { XX }, 0 },
2572   { "cli",              { XX }, 0 },
2573   { "sti",              { XX }, 0 },
2574   { "cld",              { XX }, 0 },
2575   { "std",              { XX }, 0 },
2576   { REG_TABLE (REG_FE) },
2577   { REG_TABLE (REG_FF) },
2578 };
2579
2580 static const struct dis386 dis386_twobyte[] = {
2581   /* 00 */
2582   { REG_TABLE (REG_0F00 ) },
2583   { REG_TABLE (REG_0F01 ) },
2584   { "larS",             { Gv, Ew }, 0 },
2585   { "lslS",             { Gv, Ew }, 0 },
2586   { Bad_Opcode },
2587   { "syscall",          { XX }, 0 },
2588   { "clts",             { XX }, 0 },
2589   { "sysret%LQ",                { XX }, 0 },
2590   /* 08 */
2591   { "invd",             { XX }, 0 },
2592   { PREFIX_TABLE (PREFIX_0F09) },
2593   { Bad_Opcode },
2594   { "ud2",              { XX }, 0 },
2595   { Bad_Opcode },
2596   { REG_TABLE (REG_0F0D) },
2597   { "femms",            { XX }, 0 },
2598   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2599   /* 10 */
2600   { PREFIX_TABLE (PREFIX_0F10) },
2601   { PREFIX_TABLE (PREFIX_0F11) },
2602   { PREFIX_TABLE (PREFIX_0F12) },
2603   { MOD_TABLE (MOD_0F13) },
2604   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2605   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2606   { PREFIX_TABLE (PREFIX_0F16) },
2607   { MOD_TABLE (MOD_0F17) },
2608   /* 18 */
2609   { REG_TABLE (REG_0F18) },
2610   { "nopQ",             { Ev }, 0 },
2611   { PREFIX_TABLE (PREFIX_0F1A) },
2612   { PREFIX_TABLE (PREFIX_0F1B) },
2613   { PREFIX_TABLE (PREFIX_0F1C) },
2614   { "nopQ",             { Ev }, 0 },
2615   { PREFIX_TABLE (PREFIX_0F1E) },
2616   { "nopQ",             { Ev }, 0 },
2617   /* 20 */
2618   { "movZ",             { Rm, Cm }, 0 },
2619   { "movZ",             { Rm, Dm }, 0 },
2620   { "movZ",             { Cm, Rm }, 0 },
2621   { "movZ",             { Dm, Rm }, 0 },
2622   { MOD_TABLE (MOD_0F24) },
2623   { Bad_Opcode },
2624   { MOD_TABLE (MOD_0F26) },
2625   { Bad_Opcode },
2626   /* 28 */
2627   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2628   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2629   { PREFIX_TABLE (PREFIX_0F2A) },
2630   { PREFIX_TABLE (PREFIX_0F2B) },
2631   { PREFIX_TABLE (PREFIX_0F2C) },
2632   { PREFIX_TABLE (PREFIX_0F2D) },
2633   { PREFIX_TABLE (PREFIX_0F2E) },
2634   { PREFIX_TABLE (PREFIX_0F2F) },
2635   /* 30 */
2636   { "wrmsr",            { XX }, 0 },
2637   { "rdtsc",            { XX }, 0 },
2638   { "rdmsr",            { XX }, 0 },
2639   { "rdpmc",            { XX }, 0 },
2640   { "sysenter",         { SEP }, 0 },
2641   { "sysexit",          { SEP }, 0 },
2642   { Bad_Opcode },
2643   { "getsec",           { XX }, 0 },
2644   /* 38 */
2645   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2646   { Bad_Opcode },
2647   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2648   { Bad_Opcode },
2649   { Bad_Opcode },
2650   { Bad_Opcode },
2651   { Bad_Opcode },
2652   { Bad_Opcode },
2653   /* 40 */
2654   { "cmovoS",           { Gv, Ev }, 0 },
2655   { "cmovnoS",          { Gv, Ev }, 0 },
2656   { "cmovbS",           { Gv, Ev }, 0 },
2657   { "cmovaeS",          { Gv, Ev }, 0 },
2658   { "cmoveS",           { Gv, Ev }, 0 },
2659   { "cmovneS",          { Gv, Ev }, 0 },
2660   { "cmovbeS",          { Gv, Ev }, 0 },
2661   { "cmovaS",           { Gv, Ev }, 0 },
2662   /* 48 */
2663   { "cmovsS",           { Gv, Ev }, 0 },
2664   { "cmovnsS",          { Gv, Ev }, 0 },
2665   { "cmovpS",           { Gv, Ev }, 0 },
2666   { "cmovnpS",          { Gv, Ev }, 0 },
2667   { "cmovlS",           { Gv, Ev }, 0 },
2668   { "cmovgeS",          { Gv, Ev }, 0 },
2669   { "cmovleS",          { Gv, Ev }, 0 },
2670   { "cmovgS",           { Gv, Ev }, 0 },
2671   /* 50 */
2672   { MOD_TABLE (MOD_0F50) },
2673   { PREFIX_TABLE (PREFIX_0F51) },
2674   { PREFIX_TABLE (PREFIX_0F52) },
2675   { PREFIX_TABLE (PREFIX_0F53) },
2676   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2677   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2678   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2679   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2680   /* 58 */
2681   { PREFIX_TABLE (PREFIX_0F58) },
2682   { PREFIX_TABLE (PREFIX_0F59) },
2683   { PREFIX_TABLE (PREFIX_0F5A) },
2684   { PREFIX_TABLE (PREFIX_0F5B) },
2685   { PREFIX_TABLE (PREFIX_0F5C) },
2686   { PREFIX_TABLE (PREFIX_0F5D) },
2687   { PREFIX_TABLE (PREFIX_0F5E) },
2688   { PREFIX_TABLE (PREFIX_0F5F) },
2689   /* 60 */
2690   { PREFIX_TABLE (PREFIX_0F60) },
2691   { PREFIX_TABLE (PREFIX_0F61) },
2692   { PREFIX_TABLE (PREFIX_0F62) },
2693   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2694   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2695   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2696   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2697   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2698   /* 68 */
2699   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2700   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2701   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2702   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2703   { PREFIX_TABLE (PREFIX_0F6C) },
2704   { PREFIX_TABLE (PREFIX_0F6D) },
2705   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2706   { PREFIX_TABLE (PREFIX_0F6F) },
2707   /* 70 */
2708   { PREFIX_TABLE (PREFIX_0F70) },
2709   { REG_TABLE (REG_0F71) },
2710   { REG_TABLE (REG_0F72) },
2711   { REG_TABLE (REG_0F73) },
2712   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2713   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2714   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2715   { "emms",             { XX }, PREFIX_OPCODE },
2716   /* 78 */
2717   { PREFIX_TABLE (PREFIX_0F78) },
2718   { PREFIX_TABLE (PREFIX_0F79) },
2719   { Bad_Opcode },
2720   { Bad_Opcode },
2721   { PREFIX_TABLE (PREFIX_0F7C) },
2722   { PREFIX_TABLE (PREFIX_0F7D) },
2723   { PREFIX_TABLE (PREFIX_0F7E) },
2724   { PREFIX_TABLE (PREFIX_0F7F) },
2725   /* 80 */
2726   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2727   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2728   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2729   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2730   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2731   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2732   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2733   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2734   /* 88 */
2735   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2736   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2737   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2738   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2739   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2740   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2741   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2742   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2743   /* 90 */
2744   { "seto",             { Eb }, 0 },
2745   { "setno",            { Eb }, 0 },
2746   { "setb",             { Eb }, 0 },
2747   { "setae",            { Eb }, 0 },
2748   { "sete",             { Eb }, 0 },
2749   { "setne",            { Eb }, 0 },
2750   { "setbe",            { Eb }, 0 },
2751   { "seta",             { Eb }, 0 },
2752   /* 98 */
2753   { "sets",             { Eb }, 0 },
2754   { "setns",            { Eb }, 0 },
2755   { "setp",             { Eb }, 0 },
2756   { "setnp",            { Eb }, 0 },
2757   { "setl",             { Eb }, 0 },
2758   { "setge",            { Eb }, 0 },
2759   { "setle",            { Eb }, 0 },
2760   { "setg",             { Eb }, 0 },
2761   /* a0 */
2762   { "pushT",            { fs }, 0 },
2763   { "popT",             { fs }, 0 },
2764   { "cpuid",            { XX }, 0 },
2765   { "btS",              { Ev, Gv }, 0 },
2766   { "shldS",            { Ev, Gv, Ib }, 0 },
2767   { "shldS",            { Ev, Gv, CL }, 0 },
2768   { REG_TABLE (REG_0FA6) },
2769   { REG_TABLE (REG_0FA7) },
2770   /* a8 */
2771   { "pushT",            { gs }, 0 },
2772   { "popT",             { gs }, 0 },
2773   { "rsm",              { XX }, 0 },
2774   { "btsS",             { Evh1, Gv }, 0 },
2775   { "shrdS",            { Ev, Gv, Ib }, 0 },
2776   { "shrdS",            { Ev, Gv, CL }, 0 },
2777   { REG_TABLE (REG_0FAE) },
2778   { "imulS",            { Gv, Ev }, 0 },
2779   /* b0 */
2780   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2781   { "cmpxchgS",         { Evh1, Gv }, 0 },
2782   { MOD_TABLE (MOD_0FB2) },
2783   { "btrS",             { Evh1, Gv }, 0 },
2784   { MOD_TABLE (MOD_0FB4) },
2785   { MOD_TABLE (MOD_0FB5) },
2786   { "movz{bR|x}",       { Gv, Eb }, 0 },
2787   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2788   /* b8 */
2789   { PREFIX_TABLE (PREFIX_0FB8) },
2790   { "ud1S",             { Gv, Ev }, 0 },
2791   { REG_TABLE (REG_0FBA) },
2792   { "btcS",             { Evh1, Gv }, 0 },
2793   { PREFIX_TABLE (PREFIX_0FBC) },
2794   { PREFIX_TABLE (PREFIX_0FBD) },
2795   { "movs{bR|x}",       { Gv, Eb }, 0 },
2796   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2797   /* c0 */
2798   { "xaddB",            { Ebh1, Gb }, 0 },
2799   { "xaddS",            { Evh1, Gv }, 0 },
2800   { PREFIX_TABLE (PREFIX_0FC2) },
2801   { MOD_TABLE (MOD_0FC3) },
2802   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2803   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2804   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2805   { REG_TABLE (REG_0FC7) },
2806   /* c8 */
2807   { "bswap",            { RMeAX }, 0 },
2808   { "bswap",            { RMeCX }, 0 },
2809   { "bswap",            { RMeDX }, 0 },
2810   { "bswap",            { RMeBX }, 0 },
2811   { "bswap",            { RMeSP }, 0 },
2812   { "bswap",            { RMeBP }, 0 },
2813   { "bswap",            { RMeSI }, 0 },
2814   { "bswap",            { RMeDI }, 0 },
2815   /* d0 */
2816   { PREFIX_TABLE (PREFIX_0FD0) },
2817   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2818   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2819   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2820   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2821   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2822   { PREFIX_TABLE (PREFIX_0FD6) },
2823   { MOD_TABLE (MOD_0FD7) },
2824   /* d8 */
2825   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2826   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2827   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2828   { "pand",             { MX, EM }, PREFIX_OPCODE },
2829   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2830   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2831   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2832   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2833   /* e0 */
2834   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2835   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2836   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2837   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2838   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2839   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2840   { PREFIX_TABLE (PREFIX_0FE6) },
2841   { PREFIX_TABLE (PREFIX_0FE7) },
2842   /* e8 */
2843   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2844   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2845   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2846   { "por",              { MX, EM }, PREFIX_OPCODE },
2847   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2848   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2849   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2850   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2851   /* f0 */
2852   { PREFIX_TABLE (PREFIX_0FF0) },
2853   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2854   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2855   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2856   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2857   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2858   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2859   { PREFIX_TABLE (PREFIX_0FF7) },
2860   /* f8 */
2861   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2862   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2863   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2864   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2865   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2866   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2867   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2868   { "ud0S",             { Gv, Ev }, 0 },
2869 };
2870
2871 static const unsigned char onebyte_has_modrm[256] = {
2872   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2873   /*       -------------------------------        */
2874   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2875   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2876   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2877   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2878   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2879   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2880   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2881   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2882   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2883   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2884   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2885   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2886   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2887   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2888   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2889   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2890   /*       -------------------------------        */
2891   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2892 };
2893
2894 static const unsigned char twobyte_has_modrm[256] = {
2895   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2896   /*       -------------------------------        */
2897   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2898   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2899   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2900   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2901   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2902   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2903   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2904   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2905   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2906   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2907   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2908   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2909   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2910   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2911   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2912   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2913   /*       -------------------------------        */
2914   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2915 };
2916
2917 static char obuf[100];
2918 static char *obufp;
2919 static char *mnemonicendp;
2920 static char scratchbuf[100];
2921 static unsigned char *start_codep;
2922 static unsigned char *insn_codep;
2923 static unsigned char *codep;
2924 static unsigned char *end_codep;
2925 static int last_lock_prefix;
2926 static int last_repz_prefix;
2927 static int last_repnz_prefix;
2928 static int last_data_prefix;
2929 static int last_addr_prefix;
2930 static int last_rex_prefix;
2931 static int last_seg_prefix;
2932 static int fwait_prefix;
2933 /* The active segment register prefix.  */
2934 static int active_seg_prefix;
2935 #define MAX_CODE_LENGTH 15
2936 /* We can up to 14 prefixes since the maximum instruction length is
2937    15bytes.  */
2938 static int all_prefixes[MAX_CODE_LENGTH - 1];
2939 static disassemble_info *the_info;
2940 static struct
2941   {
2942     int mod;
2943     int reg;
2944     int rm;
2945   }
2946 modrm;
2947 static unsigned char need_modrm;
2948 static struct
2949   {
2950     int scale;
2951     int index;
2952     int base;
2953   }
2954 sib;
2955 static struct
2956   {
2957     int register_specifier;
2958     int length;
2959     int prefix;
2960     int w;
2961     int evex;
2962     int r;
2963     int v;
2964     int mask_register_specifier;
2965     int zeroing;
2966     int ll;
2967     int b;
2968   }
2969 vex;
2970 static unsigned char need_vex;
2971
2972 struct op
2973   {
2974     const char *name;
2975     unsigned int len;
2976   };
2977
2978 /* If we are accessing mod/rm/reg without need_modrm set, then the
2979    values are stale.  Hitting this abort likely indicates that you
2980    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2981 #define MODRM_CHECK  if (!need_modrm) abort ()
2982
2983 static const char **names64;
2984 static const char **names32;
2985 static const char **names16;
2986 static const char **names8;
2987 static const char **names8rex;
2988 static const char **names_seg;
2989 static const char *index64;
2990 static const char *index32;
2991 static const char **index16;
2992 static const char **names_bnd;
2993
2994 static const char *intel_names64[] = {
2995   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2996   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2997 };
2998 static const char *intel_names32[] = {
2999   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3000   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3001 };
3002 static const char *intel_names16[] = {
3003   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3004   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3005 };
3006 static const char *intel_names8[] = {
3007   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3008 };
3009 static const char *intel_names8rex[] = {
3010   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3011   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3012 };
3013 static const char *intel_names_seg[] = {
3014   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3015 };
3016 static const char *intel_index64 = "riz";
3017 static const char *intel_index32 = "eiz";
3018 static const char *intel_index16[] = {
3019   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3020 };
3021
3022 static const char *att_names64[] = {
3023   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3024   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3025 };
3026 static const char *att_names32[] = {
3027   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3028   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3029 };
3030 static const char *att_names16[] = {
3031   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3032   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3033 };
3034 static const char *att_names8[] = {
3035   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3036 };
3037 static const char *att_names8rex[] = {
3038   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3039   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3040 };
3041 static const char *att_names_seg[] = {
3042   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3043 };
3044 static const char *att_index64 = "%riz";
3045 static const char *att_index32 = "%eiz";
3046 static const char *att_index16[] = {
3047   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3048 };
3049
3050 static const char **names_mm;
3051 static const char *intel_names_mm[] = {
3052   "mm0", "mm1", "mm2", "mm3",
3053   "mm4", "mm5", "mm6", "mm7"
3054 };
3055 static const char *att_names_mm[] = {
3056   "%mm0", "%mm1", "%mm2", "%mm3",
3057   "%mm4", "%mm5", "%mm6", "%mm7"
3058 };
3059
3060 static const char *intel_names_bnd[] = {
3061   "bnd0", "bnd1", "bnd2", "bnd3"
3062 };
3063
3064 static const char *att_names_bnd[] = {
3065   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3066 };
3067
3068 static const char **names_xmm;
3069 static const char *intel_names_xmm[] = {
3070   "xmm0", "xmm1", "xmm2", "xmm3",
3071   "xmm4", "xmm5", "xmm6", "xmm7",
3072   "xmm8", "xmm9", "xmm10", "xmm11",
3073   "xmm12", "xmm13", "xmm14", "xmm15",
3074   "xmm16", "xmm17", "xmm18", "xmm19",
3075   "xmm20", "xmm21", "xmm22", "xmm23",
3076   "xmm24", "xmm25", "xmm26", "xmm27",
3077   "xmm28", "xmm29", "xmm30", "xmm31"
3078 };
3079 static const char *att_names_xmm[] = {
3080   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3081   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3082   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3083   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3084   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3085   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3086   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3087   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3088 };
3089
3090 static const char **names_ymm;
3091 static const char *intel_names_ymm[] = {
3092   "ymm0", "ymm1", "ymm2", "ymm3",
3093   "ymm4", "ymm5", "ymm6", "ymm7",
3094   "ymm8", "ymm9", "ymm10", "ymm11",
3095   "ymm12", "ymm13", "ymm14", "ymm15",
3096   "ymm16", "ymm17", "ymm18", "ymm19",
3097   "ymm20", "ymm21", "ymm22", "ymm23",
3098   "ymm24", "ymm25", "ymm26", "ymm27",
3099   "ymm28", "ymm29", "ymm30", "ymm31"
3100 };
3101 static const char *att_names_ymm[] = {
3102   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3103   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3104   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3105   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3106   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3107   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3108   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3109   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3110 };
3111
3112 static const char **names_zmm;
3113 static const char *intel_names_zmm[] = {
3114   "zmm0", "zmm1", "zmm2", "zmm3",
3115   "zmm4", "zmm5", "zmm6", "zmm7",
3116   "zmm8", "zmm9", "zmm10", "zmm11",
3117   "zmm12", "zmm13", "zmm14", "zmm15",
3118   "zmm16", "zmm17", "zmm18", "zmm19",
3119   "zmm20", "zmm21", "zmm22", "zmm23",
3120   "zmm24", "zmm25", "zmm26", "zmm27",
3121   "zmm28", "zmm29", "zmm30", "zmm31"
3122 };
3123 static const char *att_names_zmm[] = {
3124   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3125   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3126   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3127   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3128   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3129   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3130   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3131   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3132 };
3133
3134 static const char **names_tmm;
3135 static const char *intel_names_tmm[] = {
3136   "tmm0", "tmm1", "tmm2", "tmm3",
3137   "tmm4", "tmm5", "tmm6", "tmm7"
3138 };
3139 static const char *att_names_tmm[] = {
3140   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
3141   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
3142 };
3143
3144 static const char **names_mask;
3145 static const char *intel_names_mask[] = {
3146   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3147 };
3148 static const char *att_names_mask[] = {
3149   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3150 };
3151
3152 static const char *names_rounding[] =
3153 {
3154   "{rn-sae}",
3155   "{rd-sae}",
3156   "{ru-sae}",
3157   "{rz-sae}"
3158 };
3159
3160 static const struct dis386 reg_table[][8] = {
3161   /* REG_80 */
3162   {
3163     { "addA",   { Ebh1, Ib }, 0 },
3164     { "orA",    { Ebh1, Ib }, 0 },
3165     { "adcA",   { Ebh1, Ib }, 0 },
3166     { "sbbA",   { Ebh1, Ib }, 0 },
3167     { "andA",   { Ebh1, Ib }, 0 },
3168     { "subA",   { Ebh1, Ib }, 0 },
3169     { "xorA",   { Ebh1, Ib }, 0 },
3170     { "cmpA",   { Eb, Ib }, 0 },
3171   },
3172   /* REG_81 */
3173   {
3174     { "addQ",   { Evh1, Iv }, 0 },
3175     { "orQ",    { Evh1, Iv }, 0 },
3176     { "adcQ",   { Evh1, Iv }, 0 },
3177     { "sbbQ",   { Evh1, Iv }, 0 },
3178     { "andQ",   { Evh1, Iv }, 0 },
3179     { "subQ",   { Evh1, Iv }, 0 },
3180     { "xorQ",   { Evh1, Iv }, 0 },
3181     { "cmpQ",   { Ev, Iv }, 0 },
3182   },
3183   /* REG_83 */
3184   {
3185     { "addQ",   { Evh1, sIb }, 0 },
3186     { "orQ",    { Evh1, sIb }, 0 },
3187     { "adcQ",   { Evh1, sIb }, 0 },
3188     { "sbbQ",   { Evh1, sIb }, 0 },
3189     { "andQ",   { Evh1, sIb }, 0 },
3190     { "subQ",   { Evh1, sIb }, 0 },
3191     { "xorQ",   { Evh1, sIb }, 0 },
3192     { "cmpQ",   { Ev, sIb }, 0 },
3193   },
3194   /* REG_8F */
3195   {
3196     { "popU",   { stackEv }, 0 },
3197     { XOP_8F_TABLE (XOP_09) },
3198     { Bad_Opcode },
3199     { Bad_Opcode },
3200     { Bad_Opcode },
3201     { XOP_8F_TABLE (XOP_09) },
3202   },
3203   /* REG_C0 */
3204   {
3205     { "rolA",   { Eb, Ib }, 0 },
3206     { "rorA",   { Eb, Ib }, 0 },
3207     { "rclA",   { Eb, Ib }, 0 },
3208     { "rcrA",   { Eb, Ib }, 0 },
3209     { "shlA",   { Eb, Ib }, 0 },
3210     { "shrA",   { Eb, Ib }, 0 },
3211     { "shlA",   { Eb, Ib }, 0 },
3212     { "sarA",   { Eb, Ib }, 0 },
3213   },
3214   /* REG_C1 */
3215   {
3216     { "rolQ",   { Ev, Ib }, 0 },
3217     { "rorQ",   { Ev, Ib }, 0 },
3218     { "rclQ",   { Ev, Ib }, 0 },
3219     { "rcrQ",   { Ev, Ib }, 0 },
3220     { "shlQ",   { Ev, Ib }, 0 },
3221     { "shrQ",   { Ev, Ib }, 0 },
3222     { "shlQ",   { Ev, Ib }, 0 },
3223     { "sarQ",   { Ev, Ib }, 0 },
3224   },
3225   /* REG_C6 */
3226   {
3227     { "movA",   { Ebh3, Ib }, 0 },
3228     { Bad_Opcode },
3229     { Bad_Opcode },
3230     { Bad_Opcode },
3231     { Bad_Opcode },
3232     { Bad_Opcode },
3233     { Bad_Opcode },
3234     { MOD_TABLE (MOD_C6_REG_7) },
3235   },
3236   /* REG_C7 */
3237   {
3238     { "movQ",   { Evh3, Iv }, 0 },
3239     { Bad_Opcode },
3240     { Bad_Opcode },
3241     { Bad_Opcode },
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { Bad_Opcode },
3245     { MOD_TABLE (MOD_C7_REG_7) },
3246   },
3247   /* REG_D0 */
3248   {
3249     { "rolA",   { Eb, I1 }, 0 },
3250     { "rorA",   { Eb, I1 }, 0 },
3251     { "rclA",   { Eb, I1 }, 0 },
3252     { "rcrA",   { Eb, I1 }, 0 },
3253     { "shlA",   { Eb, I1 }, 0 },
3254     { "shrA",   { Eb, I1 }, 0 },
3255     { "shlA",   { Eb, I1 }, 0 },
3256     { "sarA",   { Eb, I1 }, 0 },
3257   },
3258   /* REG_D1 */
3259   {
3260     { "rolQ",   { Ev, I1 }, 0 },
3261     { "rorQ",   { Ev, I1 }, 0 },
3262     { "rclQ",   { Ev, I1 }, 0 },
3263     { "rcrQ",   { Ev, I1 }, 0 },
3264     { "shlQ",   { Ev, I1 }, 0 },
3265     { "shrQ",   { Ev, I1 }, 0 },
3266     { "shlQ",   { Ev, I1 }, 0 },
3267     { "sarQ",   { Ev, I1 }, 0 },
3268   },
3269   /* REG_D2 */
3270   {
3271     { "rolA",   { Eb, CL }, 0 },
3272     { "rorA",   { Eb, CL }, 0 },
3273     { "rclA",   { Eb, CL }, 0 },
3274     { "rcrA",   { Eb, CL }, 0 },
3275     { "shlA",   { Eb, CL }, 0 },
3276     { "shrA",   { Eb, CL }, 0 },
3277     { "shlA",   { Eb, CL }, 0 },
3278     { "sarA",   { Eb, CL }, 0 },
3279   },
3280   /* REG_D3 */
3281   {
3282     { "rolQ",   { Ev, CL }, 0 },
3283     { "rorQ",   { Ev, CL }, 0 },
3284     { "rclQ",   { Ev, CL }, 0 },
3285     { "rcrQ",   { Ev, CL }, 0 },
3286     { "shlQ",   { Ev, CL }, 0 },
3287     { "shrQ",   { Ev, CL }, 0 },
3288     { "shlQ",   { Ev, CL }, 0 },
3289     { "sarQ",   { Ev, CL }, 0 },
3290   },
3291   /* REG_F6 */
3292   {
3293     { "testA",  { Eb, Ib }, 0 },
3294     { "testA",  { Eb, Ib }, 0 },
3295     { "notA",   { Ebh1 }, 0 },
3296     { "negA",   { Ebh1 }, 0 },
3297     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3298     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3299     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3300     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3301   },
3302   /* REG_F7 */
3303   {
3304     { "testQ",  { Ev, Iv }, 0 },
3305     { "testQ",  { Ev, Iv }, 0 },
3306     { "notQ",   { Evh1 }, 0 },
3307     { "negQ",   { Evh1 }, 0 },
3308     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3309     { "imulQ",  { Ev }, 0 },
3310     { "divQ",   { Ev }, 0 },
3311     { "idivQ",  { Ev }, 0 },
3312   },
3313   /* REG_FE */
3314   {
3315     { "incA",   { Ebh1 }, 0 },
3316     { "decA",   { Ebh1 }, 0 },
3317   },
3318   /* REG_FF */
3319   {
3320     { "incQ",   { Evh1 }, 0 },
3321     { "decQ",   { Evh1 }, 0 },
3322     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3323     { MOD_TABLE (MOD_FF_REG_3) },
3324     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3325     { MOD_TABLE (MOD_FF_REG_5) },
3326     { "pushU",  { stackEv }, 0 },
3327     { Bad_Opcode },
3328   },
3329   /* REG_0F00 */
3330   {
3331     { "sldtD",  { Sv }, 0 },
3332     { "strD",   { Sv }, 0 },
3333     { "lldt",   { Ew }, 0 },
3334     { "ltr",    { Ew }, 0 },
3335     { "verr",   { Ew }, 0 },
3336     { "verw",   { Ew }, 0 },
3337     { Bad_Opcode },
3338     { Bad_Opcode },
3339   },
3340   /* REG_0F01 */
3341   {
3342     { MOD_TABLE (MOD_0F01_REG_0) },
3343     { MOD_TABLE (MOD_0F01_REG_1) },
3344     { MOD_TABLE (MOD_0F01_REG_2) },
3345     { MOD_TABLE (MOD_0F01_REG_3) },
3346     { "smswD",  { Sv }, 0 },
3347     { MOD_TABLE (MOD_0F01_REG_5) },
3348     { "lmsw",   { Ew }, 0 },
3349     { MOD_TABLE (MOD_0F01_REG_7) },
3350   },
3351   /* REG_0F0D */
3352   {
3353     { "prefetch",       { Mb }, 0 },
3354     { "prefetchw",      { Mb }, 0 },
3355     { "prefetchwt1",    { Mb }, 0 },
3356     { "prefetch",       { Mb }, 0 },
3357     { "prefetch",       { Mb }, 0 },
3358     { "prefetch",       { Mb }, 0 },
3359     { "prefetch",       { Mb }, 0 },
3360     { "prefetch",       { Mb }, 0 },
3361   },
3362   /* REG_0F18 */
3363   {
3364     { MOD_TABLE (MOD_0F18_REG_0) },
3365     { MOD_TABLE (MOD_0F18_REG_1) },
3366     { MOD_TABLE (MOD_0F18_REG_2) },
3367     { MOD_TABLE (MOD_0F18_REG_3) },
3368     { MOD_TABLE (MOD_0F18_REG_4) },
3369     { MOD_TABLE (MOD_0F18_REG_5) },
3370     { MOD_TABLE (MOD_0F18_REG_6) },
3371     { MOD_TABLE (MOD_0F18_REG_7) },
3372   },
3373   /* REG_0F1C_P_0_MOD_0 */
3374   {
3375     { "cldemote",       { Mb }, 0 },
3376     { "nopQ",           { Ev }, 0 },
3377     { "nopQ",           { Ev }, 0 },
3378     { "nopQ",           { Ev }, 0 },
3379     { "nopQ",           { Ev }, 0 },
3380     { "nopQ",           { Ev }, 0 },
3381     { "nopQ",           { Ev }, 0 },
3382     { "nopQ",           { Ev }, 0 },
3383   },
3384   /* REG_0F1E_P_1_MOD_3 */
3385   {
3386     { "nopQ",           { Ev }, 0 },
3387     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3388     { "nopQ",           { Ev }, 0 },
3389     { "nopQ",           { Ev }, 0 },
3390     { "nopQ",           { Ev }, 0 },
3391     { "nopQ",           { Ev }, 0 },
3392     { "nopQ",           { Ev }, 0 },
3393     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3394   },
3395   /* REG_0F71 */
3396   {
3397     { Bad_Opcode },
3398     { Bad_Opcode },
3399     { MOD_TABLE (MOD_0F71_REG_2) },
3400     { Bad_Opcode },
3401     { MOD_TABLE (MOD_0F71_REG_4) },
3402     { Bad_Opcode },
3403     { MOD_TABLE (MOD_0F71_REG_6) },
3404   },
3405   /* REG_0F72 */
3406   {
3407     { Bad_Opcode },
3408     { Bad_Opcode },
3409     { MOD_TABLE (MOD_0F72_REG_2) },
3410     { Bad_Opcode },
3411     { MOD_TABLE (MOD_0F72_REG_4) },
3412     { Bad_Opcode },
3413     { MOD_TABLE (MOD_0F72_REG_6) },
3414   },
3415   /* REG_0F73 */
3416   {
3417     { Bad_Opcode },
3418     { Bad_Opcode },
3419     { MOD_TABLE (MOD_0F73_REG_2) },
3420     { MOD_TABLE (MOD_0F73_REG_3) },
3421     { Bad_Opcode },
3422     { Bad_Opcode },
3423     { MOD_TABLE (MOD_0F73_REG_6) },
3424     { MOD_TABLE (MOD_0F73_REG_7) },
3425   },
3426   /* REG_0FA6 */
3427   {
3428     { "montmul",        { { OP_0f07, 0 } }, 0 },
3429     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3430     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3431   },
3432   /* REG_0FA7 */
3433   {
3434     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3435     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3436     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3437     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3438     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3439     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3440   },
3441   /* REG_0FAE */
3442   {
3443     { MOD_TABLE (MOD_0FAE_REG_0) },
3444     { MOD_TABLE (MOD_0FAE_REG_1) },
3445     { MOD_TABLE (MOD_0FAE_REG_2) },
3446     { MOD_TABLE (MOD_0FAE_REG_3) },
3447     { MOD_TABLE (MOD_0FAE_REG_4) },
3448     { MOD_TABLE (MOD_0FAE_REG_5) },
3449     { MOD_TABLE (MOD_0FAE_REG_6) },
3450     { MOD_TABLE (MOD_0FAE_REG_7) },
3451   },
3452   /* REG_0FBA */
3453   {
3454     { Bad_Opcode },
3455     { Bad_Opcode },
3456     { Bad_Opcode },
3457     { Bad_Opcode },
3458     { "btQ",    { Ev, Ib }, 0 },
3459     { "btsQ",   { Evh1, Ib }, 0 },
3460     { "btrQ",   { Evh1, Ib }, 0 },
3461     { "btcQ",   { Evh1, Ib }, 0 },
3462   },
3463   /* REG_0FC7 */
3464   {
3465     { Bad_Opcode },
3466     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3467     { Bad_Opcode },
3468     { MOD_TABLE (MOD_0FC7_REG_3) },
3469     { MOD_TABLE (MOD_0FC7_REG_4) },
3470     { MOD_TABLE (MOD_0FC7_REG_5) },
3471     { MOD_TABLE (MOD_0FC7_REG_6) },
3472     { MOD_TABLE (MOD_0FC7_REG_7) },
3473   },
3474   /* REG_VEX_0F71 */
3475   {
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3479     { Bad_Opcode },
3480     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3481     { Bad_Opcode },
3482     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3483   },
3484   /* REG_VEX_0F72 */
3485   {
3486     { Bad_Opcode },
3487     { Bad_Opcode },
3488     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3489     { Bad_Opcode },
3490     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3491     { Bad_Opcode },
3492     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3493   },
3494   /* REG_VEX_0F73 */
3495   {
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3499     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3503     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3504   },
3505   /* REG_VEX_0FAE */
3506   {
3507     { Bad_Opcode },
3508     { Bad_Opcode },
3509     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3510     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3511   },
3512   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3513   {
3514     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3515   },
3516   /* REG_VEX_0F38F3 */
3517   {
3518     { Bad_Opcode },
3519     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3520     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3521     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3522   },
3523   /* REG_0FXOP_09_01_L_0 */
3524   {
3525     { Bad_Opcode },
3526     { "blcfill",        { VexGdq, Edq }, 0 },
3527     { "blsfill",        { VexGdq, Edq }, 0 },
3528     { "blcs",   { VexGdq, Edq }, 0 },
3529     { "tzmsk",  { VexGdq, Edq }, 0 },
3530     { "blcic",  { VexGdq, Edq }, 0 },
3531     { "blsic",  { VexGdq, Edq }, 0 },
3532     { "t1mskc", { VexGdq, Edq }, 0 },
3533   },
3534   /* REG_0FXOP_09_02_L_0 */
3535   {
3536     { Bad_Opcode },
3537     { "blcmsk", { VexGdq, Edq }, 0 },
3538     { Bad_Opcode },
3539     { Bad_Opcode },
3540     { Bad_Opcode },
3541     { Bad_Opcode },
3542     { "blci",   { VexGdq, Edq }, 0 },
3543   },
3544   /* REG_0FXOP_09_12_M_1_L_0 */
3545   {
3546     { "llwpcb", { Edq }, 0 },
3547     { "slwpcb", { Edq }, 0 },
3548   },
3549   /* REG_0FXOP_0A_12_L_0 */
3550   {
3551     { "lwpins", { VexGdq, Ed, Id }, 0 },
3552     { "lwpval", { VexGdq, Ed, Id }, 0 },
3553   },
3554
3555 #include "i386-dis-evex-reg.h"
3556 };
3557
3558 static const struct dis386 prefix_table[][4] = {
3559   /* PREFIX_90 */
3560   {
3561     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3562     { "pause", { XX }, 0 },
3563     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3564     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3565   },
3566
3567   /* PREFIX_0F01_REG_3_RM_1 */
3568   {
3569     { "vmmcall",        { Skip_MODRM }, 0 },
3570     { "vmgexit",        { Skip_MODRM }, 0 },
3571     { Bad_Opcode },
3572     { "vmgexit",        { Skip_MODRM }, 0 },
3573   },
3574
3575   /* PREFIX_0F01_REG_5_MOD_0 */
3576   {
3577     { Bad_Opcode },
3578     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3579   },
3580
3581   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3582   {
3583     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3584     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3585     { Bad_Opcode },
3586     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3587   },
3588
3589   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3590   {
3591     { Bad_Opcode },
3592     { Bad_Opcode },
3593     { Bad_Opcode },
3594     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3595   },
3596
3597   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3598   {
3599     { Bad_Opcode },
3600     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3601   },
3602
3603   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3604   {
3605     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3606     { "mcommit",        { Skip_MODRM }, 0 },
3607   },
3608
3609   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3610   {
3611     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3612   },
3613
3614   /* PREFIX_0F09 */
3615   {
3616     { "wbinvd",   { XX }, 0 },
3617     { "wbnoinvd", { XX }, 0 },
3618   },
3619
3620   /* PREFIX_0F10 */
3621   {
3622     { "movups", { XM, EXx }, PREFIX_OPCODE },
3623     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3624     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3625     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3626   },
3627
3628   /* PREFIX_0F11 */
3629   {
3630     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3631     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3632     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3633     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3634   },
3635
3636   /* PREFIX_0F12 */
3637   {
3638     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3639     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3640     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3641     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3642   },
3643
3644   /* PREFIX_0F16 */
3645   {
3646     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3647     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3648     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3649   },
3650
3651   /* PREFIX_0F1A */
3652   {
3653     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3654     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3655     { "bndmov", { Gbnd, Ebnd }, 0 },
3656     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3657   },
3658
3659   /* PREFIX_0F1B */
3660   {
3661     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3662     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3663     { "bndmov", { EbndS, Gbnd }, 0 },
3664     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3665   },
3666
3667   /* PREFIX_0F1C */
3668   {
3669     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3670     { "nopQ",   { Ev }, PREFIX_OPCODE },
3671     { "nopQ",   { Ev }, PREFIX_OPCODE },
3672     { "nopQ",   { Ev }, PREFIX_OPCODE },
3673   },
3674
3675   /* PREFIX_0F1E */
3676   {
3677     { "nopQ",   { Ev }, PREFIX_OPCODE },
3678     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3679     { "nopQ",   { Ev }, PREFIX_OPCODE },
3680     { "nopQ",   { Ev }, PREFIX_OPCODE },
3681   },
3682
3683   /* PREFIX_0F2A */
3684   {
3685     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3686     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3687     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3688     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3689   },
3690
3691   /* PREFIX_0F2B */
3692   {
3693     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3694     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3695     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3696     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3697   },
3698
3699   /* PREFIX_0F2C */
3700   {
3701     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3702     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3703     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3704     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3705   },
3706
3707   /* PREFIX_0F2D */
3708   {
3709     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3710     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3711     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3712     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3713   },
3714
3715   /* PREFIX_0F2E */
3716   {
3717     { "ucomiss",{ XM, EXd }, 0 },
3718     { Bad_Opcode },
3719     { "ucomisd",{ XM, EXq }, 0 },
3720   },
3721
3722   /* PREFIX_0F2F */
3723   {
3724     { "comiss", { XM, EXd }, 0 },
3725     { Bad_Opcode },
3726     { "comisd", { XM, EXq }, 0 },
3727   },
3728
3729   /* PREFIX_0F51 */
3730   {
3731     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3732     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3733     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3734     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3735   },
3736
3737   /* PREFIX_0F52 */
3738   {
3739     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3740     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3741   },
3742
3743   /* PREFIX_0F53 */
3744   {
3745     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3746     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3747   },
3748
3749   /* PREFIX_0F58 */
3750   {
3751     { "addps", { XM, EXx }, PREFIX_OPCODE },
3752     { "addss", { XM, EXd }, PREFIX_OPCODE },
3753     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3754     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3755   },
3756
3757   /* PREFIX_0F59 */
3758   {
3759     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3760     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3761     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3762     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3763   },
3764
3765   /* PREFIX_0F5A */
3766   {
3767     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3768     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3769     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3770     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3771   },
3772
3773   /* PREFIX_0F5B */
3774   {
3775     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3776     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3777     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3778   },
3779
3780   /* PREFIX_0F5C */
3781   {
3782     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3783     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3784     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3785     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3786   },
3787
3788   /* PREFIX_0F5D */
3789   {
3790     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3791     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3792     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3793     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3794   },
3795
3796   /* PREFIX_0F5E */
3797   {
3798     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3799     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3800     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3801     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3802   },
3803
3804   /* PREFIX_0F5F */
3805   {
3806     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3807     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3808     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3809     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3810   },
3811
3812   /* PREFIX_0F60 */
3813   {
3814     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3815     { Bad_Opcode },
3816     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3817   },
3818
3819   /* PREFIX_0F61 */
3820   {
3821     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3822     { Bad_Opcode },
3823     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3824   },
3825
3826   /* PREFIX_0F62 */
3827   {
3828     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3829     { Bad_Opcode },
3830     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3831   },
3832
3833   /* PREFIX_0F6C */
3834   {
3835     { Bad_Opcode },
3836     { Bad_Opcode },
3837     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3838   },
3839
3840   /* PREFIX_0F6D */
3841   {
3842     { Bad_Opcode },
3843     { Bad_Opcode },
3844     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3845   },
3846
3847   /* PREFIX_0F6F */
3848   {
3849     { "movq",   { MX, EM }, PREFIX_OPCODE },
3850     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3851     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3852   },
3853
3854   /* PREFIX_0F70 */
3855   {
3856     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3857     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3858     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3859     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3860   },
3861
3862   /* PREFIX_0F73_REG_3 */
3863   {
3864     { Bad_Opcode },
3865     { Bad_Opcode },
3866     { "psrldq", { XS, Ib }, 0 },
3867   },
3868
3869   /* PREFIX_0F73_REG_7 */
3870   {
3871     { Bad_Opcode },
3872     { Bad_Opcode },
3873     { "pslldq", { XS, Ib }, 0 },
3874   },
3875
3876   /* PREFIX_0F78 */
3877   {
3878     {"vmread",  { Em, Gm }, 0 },
3879     { Bad_Opcode },
3880     {"extrq",   { XS, Ib, Ib }, 0 },
3881     {"insertq", { XM, XS, Ib, Ib }, 0 },
3882   },
3883
3884   /* PREFIX_0F79 */
3885   {
3886     {"vmwrite", { Gm, Em }, 0 },
3887     { Bad_Opcode },
3888     {"extrq",   { XM, XS }, 0 },
3889     {"insertq", { XM, XS }, 0 },
3890   },
3891
3892   /* PREFIX_0F7C */
3893   {
3894     { Bad_Opcode },
3895     { Bad_Opcode },
3896     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3897     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3898   },
3899
3900   /* PREFIX_0F7D */
3901   {
3902     { Bad_Opcode },
3903     { Bad_Opcode },
3904     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3905     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3906   },
3907
3908   /* PREFIX_0F7E */
3909   {
3910     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3911     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3912     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3913   },
3914
3915   /* PREFIX_0F7F */
3916   {
3917     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3918     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3919     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3920   },
3921
3922   /* PREFIX_0FAE_REG_0_MOD_3 */
3923   {
3924     { Bad_Opcode },
3925     { "rdfsbase", { Ev }, 0 },
3926   },
3927
3928   /* PREFIX_0FAE_REG_1_MOD_3 */
3929   {
3930     { Bad_Opcode },
3931     { "rdgsbase", { Ev }, 0 },
3932   },
3933
3934   /* PREFIX_0FAE_REG_2_MOD_3 */
3935   {
3936     { Bad_Opcode },
3937     { "wrfsbase", { Ev }, 0 },
3938   },
3939
3940   /* PREFIX_0FAE_REG_3_MOD_3 */
3941   {
3942     { Bad_Opcode },
3943     { "wrgsbase", { Ev }, 0 },
3944   },
3945
3946   /* PREFIX_0FAE_REG_4_MOD_0 */
3947   {
3948     { "xsave",  { FXSAVE }, 0 },
3949     { "ptwrite{%LQ|}", { Edq }, 0 },
3950   },
3951
3952   /* PREFIX_0FAE_REG_4_MOD_3 */
3953   {
3954     { Bad_Opcode },
3955     { "ptwrite{%LQ|}", { Edq }, 0 },
3956   },
3957
3958   /* PREFIX_0FAE_REG_5_MOD_0 */
3959   {
3960     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3961   },
3962
3963   /* PREFIX_0FAE_REG_5_MOD_3 */
3964   {
3965     { "lfence",         { Skip_MODRM }, 0 },
3966     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3967   },
3968
3969   /* PREFIX_0FAE_REG_6_MOD_0 */
3970   {
3971     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3972     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3973     { "clwb",   { Mb }, PREFIX_OPCODE },
3974   },
3975
3976   /* PREFIX_0FAE_REG_6_MOD_3 */
3977   {
3978     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3979     { "umonitor",       { Eva }, PREFIX_OPCODE },
3980     { "tpause", { Edq }, PREFIX_OPCODE },
3981     { "umwait", { Edq }, PREFIX_OPCODE },
3982   },
3983
3984   /* PREFIX_0FAE_REG_7_MOD_0 */
3985   {
3986     { "clflush",        { Mb }, 0 },
3987     { Bad_Opcode },
3988     { "clflushopt",     { Mb }, 0 },
3989   },
3990
3991   /* PREFIX_0FB8 */
3992   {
3993     { Bad_Opcode },
3994     { "popcntS", { Gv, Ev }, 0 },
3995   },
3996
3997   /* PREFIX_0FBC */
3998   {
3999     { "bsfS",   { Gv, Ev }, 0 },
4000     { "tzcntS", { Gv, Ev }, 0 },
4001     { "bsfS",   { Gv, Ev }, 0 },
4002   },
4003
4004   /* PREFIX_0FBD */
4005   {
4006     { "bsrS",   { Gv, Ev }, 0 },
4007     { "lzcntS", { Gv, Ev }, 0 },
4008     { "bsrS",   { Gv, Ev }, 0 },
4009   },
4010
4011   /* PREFIX_0FC2 */
4012   {
4013     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4014     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4015     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4016     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4017   },
4018
4019   /* PREFIX_0FC3_MOD_0 */
4020   {
4021     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4022   },
4023
4024   /* PREFIX_0FC7_REG_6_MOD_0 */
4025   {
4026     { "vmptrld",{ Mq }, 0 },
4027     { "vmxon",  { Mq }, 0 },
4028     { "vmclear",{ Mq }, 0 },
4029   },
4030
4031   /* PREFIX_0FC7_REG_6_MOD_3 */
4032   {
4033     { "rdrand", { Ev }, 0 },
4034     { Bad_Opcode },
4035     { "rdrand", { Ev }, 0 }
4036   },
4037
4038   /* PREFIX_0FC7_REG_7_MOD_3 */
4039   {
4040     { "rdseed", { Ev }, 0 },
4041     { "rdpid",  { Em }, 0 },
4042     { "rdseed", { Ev }, 0 },
4043   },
4044
4045   /* PREFIX_0FD0 */
4046   {
4047     { Bad_Opcode },
4048     { Bad_Opcode },
4049     { "addsubpd", { XM, EXx }, 0 },
4050     { "addsubps", { XM, EXx }, 0 },
4051   },
4052
4053   /* PREFIX_0FD6 */
4054   {
4055     { Bad_Opcode },
4056     { "movq2dq",{ XM, MS }, 0 },
4057     { "movq",   { EXqS, XM }, 0 },
4058     { "movdq2q",{ MX, XS }, 0 },
4059   },
4060
4061   /* PREFIX_0FE6 */
4062   {
4063     { Bad_Opcode },
4064     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4065     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4066     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4067   },
4068
4069   /* PREFIX_0FE7 */
4070   {
4071     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4072     { Bad_Opcode },
4073     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4074   },
4075
4076   /* PREFIX_0FF0 */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { Bad_Opcode },
4081     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4082   },
4083
4084   /* PREFIX_0FF7 */
4085   {
4086     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4087     { Bad_Opcode },
4088     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4089   },
4090
4091   /* PREFIX_0F3810 */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4096   },
4097
4098   /* PREFIX_0F3814 */
4099   {
4100     { Bad_Opcode },
4101     { Bad_Opcode },
4102     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4103   },
4104
4105   /* PREFIX_0F3815 */
4106   {
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4110   },
4111
4112   /* PREFIX_0F3817 */
4113   {
4114     { Bad_Opcode },
4115     { Bad_Opcode },
4116     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4117   },
4118
4119   /* PREFIX_0F3820 */
4120   {
4121     { Bad_Opcode },
4122     { Bad_Opcode },
4123     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4124   },
4125
4126   /* PREFIX_0F3821 */
4127   {
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4131   },
4132
4133   /* PREFIX_0F3822 */
4134   {
4135     { Bad_Opcode },
4136     { Bad_Opcode },
4137     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4138   },
4139
4140   /* PREFIX_0F3823 */
4141   {
4142     { Bad_Opcode },
4143     { Bad_Opcode },
4144     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4145   },
4146
4147   /* PREFIX_0F3824 */
4148   {
4149     { Bad_Opcode },
4150     { Bad_Opcode },
4151     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4152   },
4153
4154   /* PREFIX_0F3825 */
4155   {
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4159   },
4160
4161   /* PREFIX_0F3828 */
4162   {
4163     { Bad_Opcode },
4164     { Bad_Opcode },
4165     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4166   },
4167
4168   /* PREFIX_0F3829 */
4169   {
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4173   },
4174
4175   /* PREFIX_0F382A */
4176   {
4177     { Bad_Opcode },
4178     { Bad_Opcode },
4179     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4180   },
4181
4182   /* PREFIX_0F382B */
4183   {
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4187   },
4188
4189   /* PREFIX_0F3830 */
4190   {
4191     { Bad_Opcode },
4192     { Bad_Opcode },
4193     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4194   },
4195
4196   /* PREFIX_0F3831 */
4197   {
4198     { Bad_Opcode },
4199     { Bad_Opcode },
4200     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4201   },
4202
4203   /* PREFIX_0F3832 */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4208   },
4209
4210   /* PREFIX_0F3833 */
4211   {
4212     { Bad_Opcode },
4213     { Bad_Opcode },
4214     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4215   },
4216
4217   /* PREFIX_0F3834 */
4218   {
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4222   },
4223
4224   /* PREFIX_0F3835 */
4225   {
4226     { Bad_Opcode },
4227     { Bad_Opcode },
4228     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4229   },
4230
4231   /* PREFIX_0F3837 */
4232   {
4233     { Bad_Opcode },
4234     { Bad_Opcode },
4235     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_0F3838 */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4243   },
4244
4245   /* PREFIX_0F3839 */
4246   {
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4250   },
4251
4252   /* PREFIX_0F383A */
4253   {
4254     { Bad_Opcode },
4255     { Bad_Opcode },
4256     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4257   },
4258
4259   /* PREFIX_0F383B */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4264   },
4265
4266   /* PREFIX_0F383C */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4271   },
4272
4273   /* PREFIX_0F383D */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4278   },
4279
4280   /* PREFIX_0F383E */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4285   },
4286
4287   /* PREFIX_0F383F */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4292   },
4293
4294   /* PREFIX_0F3840 */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4299   },
4300
4301   /* PREFIX_0F3841 */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F3880 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F3881 */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4320   },
4321
4322   /* PREFIX_0F3882 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4327   },
4328
4329   /* PREFIX_0F38C8 */
4330   {
4331     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4332   },
4333
4334   /* PREFIX_0F38C9 */
4335   {
4336     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4337   },
4338
4339   /* PREFIX_0F38CA */
4340   {
4341     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F38CB */
4345   {
4346     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4347   },
4348
4349   /* PREFIX_0F38CC */
4350   {
4351     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F38CD */
4355   {
4356     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4357   },
4358
4359   /* PREFIX_0F38CF */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F38DB */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F38DC */
4374   {
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F38DD */
4381   {
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F38DE */
4388   {
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F38DF */
4395   {
4396     { Bad_Opcode },
4397     { Bad_Opcode },
4398     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4399   },
4400
4401   /* PREFIX_0F38F0 */
4402   {
4403     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
4404     { Bad_Opcode },
4405     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
4406     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F38F1 */
4410   {
4411     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
4412     { Bad_Opcode },
4413     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
4414     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F38F5 */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4422   },
4423
4424   /* PREFIX_0F38F6 */
4425   {
4426     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4427     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4428     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4429     { Bad_Opcode },
4430   },
4431
4432   /* PREFIX_0F38F8 */
4433   {
4434     { Bad_Opcode },
4435     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4436     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4437     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4438   },
4439
4440   /* PREFIX_0F38F9 */
4441   {
4442     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4443   },
4444
4445   /* PREFIX_0F3A08 */
4446   {
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F3A09 */
4453   {
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4457   },
4458
4459   /* PREFIX_0F3A0A */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F3A0B */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F3A0C */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F3A0D */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F3A0E */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F3A14 */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F3A15 */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3A16 */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3A17 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F3A20 */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F3A21 */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4534   },
4535
4536   /* PREFIX_0F3A22 */
4537   {
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4541   },
4542
4543   /* PREFIX_0F3A40 */
4544   {
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4548   },
4549
4550   /* PREFIX_0F3A41 */
4551   {
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4555   },
4556
4557   /* PREFIX_0F3A42 */
4558   {
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4562   },
4563
4564   /* PREFIX_0F3A44 */
4565   {
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4569   },
4570
4571   /* PREFIX_0F3A60 */
4572   {
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
4576   },
4577
4578   /* PREFIX_0F3A61 */
4579   {
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
4583   },
4584
4585   /* PREFIX_0F3A62 */
4586   {
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4590   },
4591
4592   /* PREFIX_0F3A63 */
4593   {
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4597   },
4598
4599   /* PREFIX_0F3ACC */
4600   {
4601     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4602   },
4603
4604   /* PREFIX_0F3ACE */
4605   {
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4609   },
4610
4611   /* PREFIX_0F3ACF */
4612   {
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4616   },
4617
4618   /* PREFIX_0F3ADF */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4623   },
4624
4625   /* PREFIX_VEX_0F10 */
4626   {
4627     { "vmovups",        { XM, EXx }, 0 },
4628     { "vmovss",         { XMScalar, VexScalarR, EXxmm_md }, 0 },
4629     { "vmovupd",        { XM, EXx }, 0 },
4630     { "vmovsd",         { XMScalar, VexScalarR, EXxmm_mq }, 0 },
4631   },
4632
4633   /* PREFIX_VEX_0F11 */
4634   {
4635     { "vmovups",        { EXxS, XM }, 0 },
4636     { "vmovss",         { EXdS, VexScalarR, XMScalar }, 0 },
4637     { "vmovupd",        { EXxS, XM }, 0 },
4638     { "vmovsd",         { EXqS, VexScalarR, XMScalar }, 0 },
4639   },
4640
4641   /* PREFIX_VEX_0F12 */
4642   {
4643     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4644     { "vmovsldup",      { XM, EXx }, 0 },
4645     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4646     { "vmovddup",       { XM, EXymmq }, 0 },
4647   },
4648
4649   /* PREFIX_VEX_0F16 */
4650   {
4651     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4652     { "vmovshdup",      { XM, EXx }, 0 },
4653     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4654   },
4655
4656   /* PREFIX_VEX_0F2A */
4657   {
4658     { Bad_Opcode },
4659     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
4660     { Bad_Opcode },
4661     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
4662   },
4663
4664   /* PREFIX_VEX_0F2C */
4665   {
4666     { Bad_Opcode },
4667     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4668     { Bad_Opcode },
4669     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4670   },
4671
4672   /* PREFIX_VEX_0F2D */
4673   {
4674     { Bad_Opcode },
4675     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4676     { Bad_Opcode },
4677     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4678   },
4679
4680   /* PREFIX_VEX_0F2E */
4681   {
4682     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4683     { Bad_Opcode },
4684     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4685   },
4686
4687   /* PREFIX_VEX_0F2F */
4688   {
4689     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4690     { Bad_Opcode },
4691     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4692   },
4693
4694   /* PREFIX_VEX_0F41 */
4695   {
4696     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4697     { Bad_Opcode },
4698     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4699   },
4700
4701   /* PREFIX_VEX_0F42 */
4702   {
4703     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4704     { Bad_Opcode },
4705     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4706   },
4707
4708   /* PREFIX_VEX_0F44 */
4709   {
4710     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4711     { Bad_Opcode },
4712     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4713   },
4714
4715   /* PREFIX_VEX_0F45 */
4716   {
4717     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4718     { Bad_Opcode },
4719     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4720   },
4721
4722   /* PREFIX_VEX_0F46 */
4723   {
4724     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4725     { Bad_Opcode },
4726     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4727   },
4728
4729   /* PREFIX_VEX_0F47 */
4730   {
4731     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4732     { Bad_Opcode },
4733     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4734   },
4735
4736   /* PREFIX_VEX_0F4A */
4737   {
4738     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4739     { Bad_Opcode },
4740     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4741   },
4742
4743   /* PREFIX_VEX_0F4B */
4744   {
4745     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4746     { Bad_Opcode },
4747     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4748   },
4749
4750   /* PREFIX_VEX_0F51 */
4751   {
4752     { "vsqrtps",        { XM, EXx }, 0 },
4753     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4754     { "vsqrtpd",        { XM, EXx }, 0 },
4755     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4756   },
4757
4758   /* PREFIX_VEX_0F52 */
4759   {
4760     { "vrsqrtps",       { XM, EXx }, 0 },
4761     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4762   },
4763
4764   /* PREFIX_VEX_0F53 */
4765   {
4766     { "vrcpps",         { XM, EXx }, 0 },
4767     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4768   },
4769
4770   /* PREFIX_VEX_0F58 */
4771   {
4772     { "vaddps",         { XM, Vex, EXx }, 0 },
4773     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4774     { "vaddpd",         { XM, Vex, EXx }, 0 },
4775     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4776   },
4777
4778   /* PREFIX_VEX_0F59 */
4779   {
4780     { "vmulps",         { XM, Vex, EXx }, 0 },
4781     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4782     { "vmulpd",         { XM, Vex, EXx }, 0 },
4783     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4784   },
4785
4786   /* PREFIX_VEX_0F5A */
4787   {
4788     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4789     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4790     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4791     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4792   },
4793
4794   /* PREFIX_VEX_0F5B */
4795   {
4796     { "vcvtdq2ps",      { XM, EXx }, 0 },
4797     { "vcvttps2dq",     { XM, EXx }, 0 },
4798     { "vcvtps2dq",      { XM, EXx }, 0 },
4799   },
4800
4801   /* PREFIX_VEX_0F5C */
4802   {
4803     { "vsubps",         { XM, Vex, EXx }, 0 },
4804     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4805     { "vsubpd",         { XM, Vex, EXx }, 0 },
4806     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4807   },
4808
4809   /* PREFIX_VEX_0F5D */
4810   {
4811     { "vminps",         { XM, Vex, EXx }, 0 },
4812     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4813     { "vminpd",         { XM, Vex, EXx }, 0 },
4814     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4815   },
4816
4817   /* PREFIX_VEX_0F5E */
4818   {
4819     { "vdivps",         { XM, Vex, EXx }, 0 },
4820     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4821     { "vdivpd",         { XM, Vex, EXx }, 0 },
4822     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4823   },
4824
4825   /* PREFIX_VEX_0F5F */
4826   {
4827     { "vmaxps",         { XM, Vex, EXx }, 0 },
4828     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4829     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4830     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4831   },
4832
4833   /* PREFIX_VEX_0F60 */
4834   {
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4838   },
4839
4840   /* PREFIX_VEX_0F61 */
4841   {
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4845   },
4846
4847   /* PREFIX_VEX_0F62 */
4848   {
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4852   },
4853
4854   /* PREFIX_VEX_0F63 */
4855   {
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4859   },
4860
4861   /* PREFIX_VEX_0F64 */
4862   {
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4866   },
4867
4868   /* PREFIX_VEX_0F65 */
4869   {
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4873   },
4874
4875   /* PREFIX_VEX_0F66 */
4876   {
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4880   },
4881
4882   /* PREFIX_VEX_0F67 */
4883   {
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4887   },
4888
4889   /* PREFIX_VEX_0F68 */
4890   {
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4894   },
4895
4896   /* PREFIX_VEX_0F69 */
4897   {
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4901   },
4902
4903   /* PREFIX_VEX_0F6A */
4904   {
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4908   },
4909
4910   /* PREFIX_VEX_0F6B */
4911   {
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4915   },
4916
4917   /* PREFIX_VEX_0F6C */
4918   {
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4922   },
4923
4924   /* PREFIX_VEX_0F6D */
4925   {
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4929   },
4930
4931   /* PREFIX_VEX_0F6E */
4932   {
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4936   },
4937
4938   /* PREFIX_VEX_0F6F */
4939   {
4940     { Bad_Opcode },
4941     { "vmovdqu",        { XM, EXx }, 0 },
4942     { "vmovdqa",        { XM, EXx }, 0 },
4943   },
4944
4945   /* PREFIX_VEX_0F70 */
4946   {
4947     { Bad_Opcode },
4948     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4949     { "vpshufd",        { XM, EXx, Ib }, 0 },
4950     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4951   },
4952
4953   /* PREFIX_VEX_0F71_REG_2 */
4954   {
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4958   },
4959
4960   /* PREFIX_VEX_0F71_REG_4 */
4961   {
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { "vpsraw",         { Vex, XS, Ib }, 0 },
4965   },
4966
4967   /* PREFIX_VEX_0F71_REG_6 */
4968   {
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { "vpsllw",         { Vex, XS, Ib }, 0 },
4972   },
4973
4974   /* PREFIX_VEX_0F72_REG_2 */
4975   {
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { "vpsrld",         { Vex, XS, Ib }, 0 },
4979   },
4980
4981   /* PREFIX_VEX_0F72_REG_4 */
4982   {
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { "vpsrad",         { Vex, XS, Ib }, 0 },
4986   },
4987
4988   /* PREFIX_VEX_0F72_REG_6 */
4989   {
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { "vpslld",         { Vex, XS, Ib }, 0 },
4993   },
4994
4995   /* PREFIX_VEX_0F73_REG_2 */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5000   },
5001
5002   /* PREFIX_VEX_0F73_REG_3 */
5003   {
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5007   },
5008
5009   /* PREFIX_VEX_0F73_REG_6 */
5010   {
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { "vpsllq",         { Vex, XS, Ib }, 0 },
5014   },
5015
5016   /* PREFIX_VEX_0F73_REG_7 */
5017   {
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { "vpslldq",        { Vex, XS, Ib }, 0 },
5021   },
5022
5023   /* PREFIX_VEX_0F74 */
5024   {
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5028   },
5029
5030   /* PREFIX_VEX_0F75 */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5035   },
5036
5037   /* PREFIX_VEX_0F76 */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5042   },
5043
5044   /* PREFIX_VEX_0F77 */
5045   {
5046     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5047   },
5048
5049   /* PREFIX_VEX_0F7C */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5054     { "vhaddps",        { XM, Vex, EXx }, 0 },
5055   },
5056
5057   /* PREFIX_VEX_0F7D */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5062     { "vhsubps",        { XM, Vex, EXx }, 0 },
5063   },
5064
5065   /* PREFIX_VEX_0F7E */
5066   {
5067     { Bad_Opcode },
5068     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5069     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5070   },
5071
5072   /* PREFIX_VEX_0F7F */
5073   {
5074     { Bad_Opcode },
5075     { "vmovdqu",        { EXxS, XM }, 0 },
5076     { "vmovdqa",        { EXxS, XM }, 0 },
5077   },
5078
5079   /* PREFIX_VEX_0F90 */
5080   {
5081     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5082     { Bad_Opcode },
5083     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0F91 */
5087   {
5088     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5089     { Bad_Opcode },
5090     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5091   },
5092
5093   /* PREFIX_VEX_0F92 */
5094   {
5095     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5096     { Bad_Opcode },
5097     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5098     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5099   },
5100
5101   /* PREFIX_VEX_0F93 */
5102   {
5103     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5104     { Bad_Opcode },
5105     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5106     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5107   },
5108
5109   /* PREFIX_VEX_0F98 */
5110   {
5111     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5112     { Bad_Opcode },
5113     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5114   },
5115
5116   /* PREFIX_VEX_0F99 */
5117   {
5118     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5119     { Bad_Opcode },
5120     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5121   },
5122
5123   /* PREFIX_VEX_0FC2 */
5124   {
5125     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
5126     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
5127     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
5128     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
5129   },
5130
5131   /* PREFIX_VEX_0FC4 */
5132   {
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_0FC5 */
5139   {
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_0FD0 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5150     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5151   },
5152
5153   /* PREFIX_VEX_0FD1 */
5154   {
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5158   },
5159
5160   /* PREFIX_VEX_0FD2 */
5161   {
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5165   },
5166
5167   /* PREFIX_VEX_0FD3 */
5168   {
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5172   },
5173
5174   /* PREFIX_VEX_0FD4 */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { "vpaddq",         { XM, Vex, EXx }, 0 },
5179   },
5180
5181   /* PREFIX_VEX_0FD5 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { "vpmullw",        { XM, Vex, EXx }, 0 },
5186   },
5187
5188   /* PREFIX_VEX_0FD6 */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5193   },
5194
5195   /* PREFIX_VEX_0FD7 */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5200   },
5201
5202   /* PREFIX_VEX_0FD8 */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5207   },
5208
5209   /* PREFIX_VEX_0FD9 */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5214   },
5215
5216   /* PREFIX_VEX_0FDA */
5217   {
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { "vpminub",        { XM, Vex, EXx }, 0 },
5221   },
5222
5223   /* PREFIX_VEX_0FDB */
5224   {
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { "vpand",          { XM, Vex, EXx }, 0 },
5228   },
5229
5230   /* PREFIX_VEX_0FDC */
5231   {
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5235   },
5236
5237   /* PREFIX_VEX_0FDD */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5242   },
5243
5244   /* PREFIX_VEX_0FDE */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5249   },
5250
5251   /* PREFIX_VEX_0FDF */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { "vpandn",         { XM, Vex, EXx }, 0 },
5256   },
5257
5258   /* PREFIX_VEX_0FE0 */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { "vpavgb",         { XM, Vex, EXx }, 0 },
5263   },
5264
5265   /* PREFIX_VEX_0FE1 */
5266   {
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5270   },
5271
5272   /* PREFIX_VEX_0FE2 */
5273   {
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5277   },
5278
5279   /* PREFIX_VEX_0FE3 */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { "vpavgw",         { XM, Vex, EXx }, 0 },
5284   },
5285
5286   /* PREFIX_VEX_0FE4 */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5291   },
5292
5293   /* PREFIX_VEX_0FE5 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5298   },
5299
5300   /* PREFIX_VEX_0FE6 */
5301   {
5302     { Bad_Opcode },
5303     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5304     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5305     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5306   },
5307
5308   /* PREFIX_VEX_0FE7 */
5309   {
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5313   },
5314
5315   /* PREFIX_VEX_0FE8 */
5316   {
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5320   },
5321
5322   /* PREFIX_VEX_0FE9 */
5323   {
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5327   },
5328
5329   /* PREFIX_VEX_0FEA */
5330   {
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { "vpminsw",        { XM, Vex, EXx }, 0 },
5334   },
5335
5336   /* PREFIX_VEX_0FEB */
5337   {
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { "vpor",           { XM, Vex, EXx }, 0 },
5341   },
5342
5343   /* PREFIX_VEX_0FEC */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5348   },
5349
5350   /* PREFIX_VEX_0FED */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5355   },
5356
5357   /* PREFIX_VEX_0FEE */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5362   },
5363
5364   /* PREFIX_VEX_0FEF */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { "vpxor",          { XM, Vex, EXx }, 0 },
5369   },
5370
5371   /* PREFIX_VEX_0FF0 */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5377   },
5378
5379   /* PREFIX_VEX_0FF1 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5384   },
5385
5386   /* PREFIX_VEX_0FF2 */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5391   },
5392
5393   /* PREFIX_VEX_0FF3 */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5398   },
5399
5400   /* PREFIX_VEX_0FF4 */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5405   },
5406
5407   /* PREFIX_VEX_0FF5 */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5412   },
5413
5414   /* PREFIX_VEX_0FF6 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5419   },
5420
5421   /* PREFIX_VEX_0FF7 */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5426   },
5427
5428   /* PREFIX_VEX_0FF8 */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { "vpsubb",         { XM, Vex, EXx }, 0 },
5433   },
5434
5435   /* PREFIX_VEX_0FF9 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { "vpsubw",         { XM, Vex, EXx }, 0 },
5440   },
5441
5442   /* PREFIX_VEX_0FFA */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { "vpsubd",         { XM, Vex, EXx }, 0 },
5447   },
5448
5449   /* PREFIX_VEX_0FFB */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { "vpsubq",         { XM, Vex, EXx }, 0 },
5454   },
5455
5456   /* PREFIX_VEX_0FFC */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { "vpaddb",         { XM, Vex, EXx }, 0 },
5461   },
5462
5463   /* PREFIX_VEX_0FFD */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { "vpaddw",         { XM, Vex, EXx }, 0 },
5468   },
5469
5470   /* PREFIX_VEX_0FFE */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { "vpaddd",         { XM, Vex, EXx }, 0 },
5475   },
5476
5477   /* PREFIX_VEX_0F3800 */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { "vpshufb",        { XM, Vex, EXx }, 0 },
5482   },
5483
5484   /* PREFIX_VEX_0F3801 */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { "vphaddw",        { XM, Vex, EXx }, 0 },
5489   },
5490
5491   /* PREFIX_VEX_0F3802 */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { "vphaddd",        { XM, Vex, EXx }, 0 },
5496   },
5497
5498   /* PREFIX_VEX_0F3803 */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5503   },
5504
5505   /* PREFIX_VEX_0F3804 */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5510   },
5511
5512   /* PREFIX_VEX_0F3805 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { "vphsubw",        { XM, Vex, EXx }, 0 },
5517   },
5518
5519   /* PREFIX_VEX_0F3806 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { "vphsubd",        { XM, Vex, EXx }, 0 },
5524   },
5525
5526   /* PREFIX_VEX_0F3807 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5531   },
5532
5533   /* PREFIX_VEX_0F3808 */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { "vpsignb",        { XM, Vex, EXx }, 0 },
5538   },
5539
5540   /* PREFIX_VEX_0F3809 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { "vpsignw",        { XM, Vex, EXx }, 0 },
5545   },
5546
5547   /* PREFIX_VEX_0F380A */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { "vpsignd",        { XM, Vex, EXx }, 0 },
5552   },
5553
5554   /* PREFIX_VEX_0F380B */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5559   },
5560
5561   /* PREFIX_VEX_0F380C */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5566   },
5567
5568   /* PREFIX_VEX_0F380D */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5573   },
5574
5575   /* PREFIX_VEX_0F380E */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5580   },
5581
5582   /* PREFIX_VEX_0F380F */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0F3813 */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5594   },
5595
5596   /* PREFIX_VEX_0F3816 */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0F3817 */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { "vptest",         { XM, EXx }, 0 },
5608   },
5609
5610   /* PREFIX_VEX_0F3818 */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5615   },
5616
5617   /* PREFIX_VEX_0F3819 */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5622   },
5623
5624   /* PREFIX_VEX_0F381A */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5629   },
5630
5631   /* PREFIX_VEX_0F381C */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { "vpabsb",         { XM, EXx }, 0 },
5636   },
5637
5638   /* PREFIX_VEX_0F381D */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { "vpabsw",         { XM, EXx }, 0 },
5643   },
5644
5645   /* PREFIX_VEX_0F381E */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { "vpabsd",         { XM, EXx }, 0 },
5650   },
5651
5652   /* PREFIX_VEX_0F3820 */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5657   },
5658
5659   /* PREFIX_VEX_0F3821 */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5664   },
5665
5666   /* PREFIX_VEX_0F3822 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5671   },
5672
5673   /* PREFIX_VEX_0F3823 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5678   },
5679
5680   /* PREFIX_VEX_0F3824 */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5685   },
5686
5687   /* PREFIX_VEX_0F3825 */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5692   },
5693
5694   /* PREFIX_VEX_0F3828 */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5699   },
5700
5701   /* PREFIX_VEX_0F3829 */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5706   },
5707
5708   /* PREFIX_VEX_0F382A */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5713   },
5714
5715   /* PREFIX_VEX_0F382B */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5720   },
5721
5722   /* PREFIX_VEX_0F382C */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5727   },
5728
5729   /* PREFIX_VEX_0F382D */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5734   },
5735
5736   /* PREFIX_VEX_0F382E */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5741   },
5742
5743   /* PREFIX_VEX_0F382F */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5748   },
5749
5750   /* PREFIX_VEX_0F3830 */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5755   },
5756
5757   /* PREFIX_VEX_0F3831 */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5762   },
5763
5764   /* PREFIX_VEX_0F3832 */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5769   },
5770
5771   /* PREFIX_VEX_0F3833 */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5776   },
5777
5778   /* PREFIX_VEX_0F3834 */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5783   },
5784
5785   /* PREFIX_VEX_0F3835 */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5790   },
5791
5792   /* PREFIX_VEX_0F3836 */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5797   },
5798
5799   /* PREFIX_VEX_0F3837 */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5804   },
5805
5806   /* PREFIX_VEX_0F3838 */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { "vpminsb",        { XM, Vex, EXx }, 0 },
5811   },
5812
5813   /* PREFIX_VEX_0F3839 */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { "vpminsd",        { XM, Vex, EXx }, 0 },
5818   },
5819
5820   /* PREFIX_VEX_0F383A */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { "vpminuw",        { XM, Vex, EXx }, 0 },
5825   },
5826
5827   /* PREFIX_VEX_0F383B */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { "vpminud",        { XM, Vex, EXx }, 0 },
5832   },
5833
5834   /* PREFIX_VEX_0F383C */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5839   },
5840
5841   /* PREFIX_VEX_0F383D */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5846   },
5847
5848   /* PREFIX_VEX_0F383E */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5853   },
5854
5855   /* PREFIX_VEX_0F383F */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5860   },
5861
5862   /* PREFIX_VEX_0F3840 */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { "vpmulld",        { XM, Vex, EXx }, 0 },
5867   },
5868
5869   /* PREFIX_VEX_0F3841 */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5874   },
5875
5876   /* PREFIX_VEX_0F3845 */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { "vpsrlv%DQ", { XM, Vex, EXx }, 0 },
5881   },
5882
5883   /* PREFIX_VEX_0F3846 */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5888   },
5889
5890   /* PREFIX_VEX_0F3847 */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { "vpsllv%DQ", { XM, Vex, EXx }, 0 },
5895   },
5896
5897   /* PREFIX_VEX_0F3849_X86_64 */
5898   {
5899     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
5900     { Bad_Opcode },
5901     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
5902     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
5903   },
5904
5905   /* PREFIX_VEX_0F384B_X86_64 */
5906   {
5907     { Bad_Opcode },
5908     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
5909     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
5910     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
5911   },
5912
5913   /* PREFIX_VEX_0F3858 */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F3859 */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F385A */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F385C_X86_64 */
5935   {
5936     { Bad_Opcode },
5937     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
5938     { Bad_Opcode },
5939   },
5940
5941   /* PREFIX_VEX_0F385E_X86_64 */
5942   {
5943     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
5944     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
5945     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
5946     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
5947   },
5948
5949   /* PREFIX_VEX_0F3878 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F3879 */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5961   },
5962
5963   /* PREFIX_VEX_0F388C */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5968   },
5969
5970   /* PREFIX_VEX_0F388E */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5975   },
5976
5977   /* PREFIX_VEX_0F3890 */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, 0 },
5982   },
5983
5984   /* PREFIX_VEX_0F3891 */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5989   },
5990
5991   /* PREFIX_VEX_0F3892 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5996   },
5997
5998   /* PREFIX_VEX_0F3893 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6003   },
6004
6005   /* PREFIX_VEX_0F3896 */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6010   },
6011
6012   /* PREFIX_VEX_0F3897 */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6017   },
6018
6019   /* PREFIX_VEX_0F3898 */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F3899 */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6031   },
6032
6033   /* PREFIX_VEX_0F389A */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F389B */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F389C */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F389D */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6059   },
6060
6061   /* PREFIX_VEX_0F389E */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F389F */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F38A6 */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6080     { Bad_Opcode },
6081   },
6082
6083   /* PREFIX_VEX_0F38A7 */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F38A8 */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6095   },
6096
6097   /* PREFIX_VEX_0F38A9 */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6102   },
6103
6104   /* PREFIX_VEX_0F38AA */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38AB */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38AC */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38AD */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38AE */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6137   },
6138
6139   /* PREFIX_VEX_0F38AF */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6144   },
6145
6146   /* PREFIX_VEX_0F38B6 */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6151   },
6152
6153   /* PREFIX_VEX_0F38B7 */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6158   },
6159
6160   /* PREFIX_VEX_0F38B8 */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6165   },
6166
6167   /* PREFIX_VEX_0F38B9 */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6172   },
6173
6174   /* PREFIX_VEX_0F38BA */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6179   },
6180
6181   /* PREFIX_VEX_0F38BB */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38BC */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6193   },
6194
6195   /* PREFIX_VEX_0F38BD */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6200   },
6201
6202   /* PREFIX_VEX_0F38BE */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F38BF */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F38CF */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6221   },
6222
6223   /* PREFIX_VEX_0F38DB */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6228   },
6229
6230   /* PREFIX_VEX_0F38DC */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vaesenc",        { XM, Vex, EXx }, 0 },
6235   },
6236
6237   /* PREFIX_VEX_0F38DD */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6242   },
6243
6244   /* PREFIX_VEX_0F38DE */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vaesdec",        { XM, Vex, EXx }, 0 },
6249   },
6250
6251   /* PREFIX_VEX_0F38DF */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6256   },
6257
6258   /* PREFIX_VEX_0F38F2 */
6259   {
6260     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6261   },
6262
6263   /* PREFIX_VEX_0F38F3_REG_1 */
6264   {
6265     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6266   },
6267
6268   /* PREFIX_VEX_0F38F3_REG_2 */
6269   {
6270     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6271   },
6272
6273   /* PREFIX_VEX_0F38F3_REG_3 */
6274   {
6275     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6276   },
6277
6278   /* PREFIX_VEX_0F38F5 */
6279   {
6280     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6281     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6282     { Bad_Opcode },
6283     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6284   },
6285
6286   /* PREFIX_VEX_0F38F6 */
6287   {
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6292   },
6293
6294   /* PREFIX_VEX_0F38F7 */
6295   {
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6297     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6299     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A00 */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6307   },
6308
6309   /* PREFIX_VEX_0F3A01 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A02 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A04 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A05 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A06 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6342   },
6343
6344   /* PREFIX_VEX_0F3A08 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { "vroundps",       { XM, EXx, Ib }, 0 },
6349   },
6350
6351   /* PREFIX_VEX_0F3A09 */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { "vroundpd",       { XM, EXx, Ib }, 0 },
6356   },
6357
6358   /* PREFIX_VEX_0F3A0A */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F3A0B */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F3A0C */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F3A0D */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6384   },
6385
6386   /* PREFIX_VEX_0F3A0E */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6391   },
6392
6393   /* PREFIX_VEX_0F3A0F */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6398   },
6399
6400   /* PREFIX_VEX_0F3A14 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6405   },
6406
6407   /* PREFIX_VEX_0F3A15 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6412   },
6413
6414   /* PREFIX_VEX_0F3A16 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A17 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A18 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A19 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A1D */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A20 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A21 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A22 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A30 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A31 */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A32 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A33 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6496   },
6497
6498   /* PREFIX_VEX_0F3A38 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6503   },
6504
6505   /* PREFIX_VEX_0F3A39 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6510   },
6511
6512   /* PREFIX_VEX_0F3A40 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6517   },
6518
6519   /* PREFIX_VEX_0F3A41 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6524   },
6525
6526   /* PREFIX_VEX_0F3A42 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6531   },
6532
6533   /* PREFIX_VEX_0F3A44 */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6538   },
6539
6540   /* PREFIX_VEX_0F3A46 */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6545   },
6546
6547   /* PREFIX_VEX_0F3A48 */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6552   },
6553
6554   /* PREFIX_VEX_0F3A49 */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6559   },
6560
6561   /* PREFIX_VEX_0F3A4A */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6566   },
6567
6568   /* PREFIX_VEX_0F3A4B */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6573   },
6574
6575   /* PREFIX_VEX_0F3A4C */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6580   },
6581
6582   /* PREFIX_VEX_0F3A5C */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6587   },
6588
6589   /* PREFIX_VEX_0F3A5D */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6594   },
6595
6596   /* PREFIX_VEX_0F3A5E */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6601   },
6602
6603   /* PREFIX_VEX_0F3A5F */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6608   },
6609
6610   /* PREFIX_VEX_0F3A60 */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6615     { Bad_Opcode },
6616   },
6617
6618   /* PREFIX_VEX_0F3A61 */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6623   },
6624
6625   /* PREFIX_VEX_0F3A62 */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6630   },
6631
6632   /* PREFIX_VEX_0F3A63 */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6637   },
6638
6639   /* PREFIX_VEX_0F3A68 */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6644   },
6645
6646   /* PREFIX_VEX_0F3A69 */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6651   },
6652
6653   /* PREFIX_VEX_0F3A6A */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6658   },
6659
6660   /* PREFIX_VEX_0F3A6B */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6665   },
6666
6667   /* PREFIX_VEX_0F3A6C */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6672   },
6673
6674   /* PREFIX_VEX_0F3A6D */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6679   },
6680
6681   /* PREFIX_VEX_0F3A6E */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6686   },
6687
6688   /* PREFIX_VEX_0F3A6F */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6693   },
6694
6695   /* PREFIX_VEX_0F3A78 */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6700   },
6701
6702   /* PREFIX_VEX_0F3A79 */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6707   },
6708
6709   /* PREFIX_VEX_0F3A7A */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6714   },
6715
6716   /* PREFIX_VEX_0F3A7B */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6721   },
6722
6723   /* PREFIX_VEX_0F3A7C */
6724   {
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6728     { Bad_Opcode },
6729   },
6730
6731   /* PREFIX_VEX_0F3A7D */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6736   },
6737
6738   /* PREFIX_VEX_0F3A7E */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6743   },
6744
6745   /* PREFIX_VEX_0F3A7F */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6750   },
6751
6752   /* PREFIX_VEX_0F3ACE */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6757   },
6758
6759   /* PREFIX_VEX_0F3ACF */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6764   },
6765
6766   /* PREFIX_VEX_0F3ADF */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6771   },
6772
6773   /* PREFIX_VEX_0F3AF0 */
6774   {
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6779   },
6780
6781 #include "i386-dis-evex-prefix.h"
6782 };
6783
6784 static const struct dis386 x86_64_table[][2] = {
6785   /* X86_64_06 */
6786   {
6787     { "pushP", { es }, 0 },
6788   },
6789
6790   /* X86_64_07 */
6791   {
6792     { "popP", { es }, 0 },
6793   },
6794
6795   /* X86_64_0E */
6796   {
6797     { "pushP", { cs }, 0 },
6798   },
6799
6800   /* X86_64_16 */
6801   {
6802     { "pushP", { ss }, 0 },
6803   },
6804
6805   /* X86_64_17 */
6806   {
6807     { "popP", { ss }, 0 },
6808   },
6809
6810   /* X86_64_1E */
6811   {
6812     { "pushP", { ds }, 0 },
6813   },
6814
6815   /* X86_64_1F */
6816   {
6817     { "popP", { ds }, 0 },
6818   },
6819
6820   /* X86_64_27 */
6821   {
6822     { "daa", { XX }, 0 },
6823   },
6824
6825   /* X86_64_2F */
6826   {
6827     { "das", { XX }, 0 },
6828   },
6829
6830   /* X86_64_37 */
6831   {
6832     { "aaa", { XX }, 0 },
6833   },
6834
6835   /* X86_64_3F */
6836   {
6837     { "aas", { XX }, 0 },
6838   },
6839
6840   /* X86_64_60 */
6841   {
6842     { "pushaP", { XX }, 0 },
6843   },
6844
6845   /* X86_64_61 */
6846   {
6847     { "popaP", { XX }, 0 },
6848   },
6849
6850   /* X86_64_62 */
6851   {
6852     { MOD_TABLE (MOD_62_32BIT) },
6853     { EVEX_TABLE (EVEX_0F) },
6854   },
6855
6856   /* X86_64_63 */
6857   {
6858     { "arpl", { Ew, Gw }, 0 },
6859     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6860   },
6861
6862   /* X86_64_6D */
6863   {
6864     { "ins{R|}", { Yzr, indirDX }, 0 },
6865     { "ins{G|}", { Yzr, indirDX }, 0 },
6866   },
6867
6868   /* X86_64_6F */
6869   {
6870     { "outs{R|}", { indirDXr, Xz }, 0 },
6871     { "outs{G|}", { indirDXr, Xz }, 0 },
6872   },
6873
6874   /* X86_64_82 */
6875   {
6876     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6877     { REG_TABLE (REG_80) },
6878   },
6879
6880   /* X86_64_9A */
6881   {
6882     { "{l|}call{T|}", { Ap }, 0 },
6883   },
6884
6885   /* X86_64_C2 */
6886   {
6887     { "retP",           { Iw, BND }, 0 },
6888     { "ret@",           { Iw, BND }, 0 },
6889   },
6890
6891   /* X86_64_C3 */
6892   {
6893     { "retP",           { BND }, 0 },
6894     { "ret@",           { BND }, 0 },
6895   },
6896
6897   /* X86_64_C4 */
6898   {
6899     { MOD_TABLE (MOD_C4_32BIT) },
6900     { VEX_C4_TABLE (VEX_0F) },
6901   },
6902
6903   /* X86_64_C5 */
6904   {
6905     { MOD_TABLE (MOD_C5_32BIT) },
6906     { VEX_C5_TABLE (VEX_0F) },
6907   },
6908
6909   /* X86_64_CE */
6910   {
6911     { "into", { XX }, 0 },
6912   },
6913
6914   /* X86_64_D4 */
6915   {
6916     { "aam", { Ib }, 0 },
6917   },
6918
6919   /* X86_64_D5 */
6920   {
6921     { "aad", { Ib }, 0 },
6922   },
6923
6924   /* X86_64_E8 */
6925   {
6926     { "callP",          { Jv, BND }, 0 },
6927     { "call@",          { Jv, BND }, 0 }
6928   },
6929
6930   /* X86_64_E9 */
6931   {
6932     { "jmpP",           { Jv, BND }, 0 },
6933     { "jmp@",           { Jv, BND }, 0 }
6934   },
6935
6936   /* X86_64_EA */
6937   {
6938     { "{l|}jmp{T|}", { Ap }, 0 },
6939   },
6940
6941   /* X86_64_0F01_REG_0 */
6942   {
6943     { "sgdt{Q|Q}", { M }, 0 },
6944     { "sgdt", { M }, 0 },
6945   },
6946
6947   /* X86_64_0F01_REG_1 */
6948   {
6949     { "sidt{Q|Q}", { M }, 0 },
6950     { "sidt", { M }, 0 },
6951   },
6952
6953   /* X86_64_0F01_REG_2 */
6954   {
6955     { "lgdt{Q|Q}", { M }, 0 },
6956     { "lgdt", { M }, 0 },
6957   },
6958
6959   /* X86_64_0F01_REG_3 */
6960   {
6961     { "lidt{Q|Q}", { M }, 0 },
6962     { "lidt", { M }, 0 },
6963   },
6964
6965   /* X86_64_VEX_0F3849 */
6966   {
6967     { Bad_Opcode },
6968     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
6969   },
6970
6971   /* X86_64_VEX_0F384B */
6972   {
6973     { Bad_Opcode },
6974     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
6975   },
6976
6977   /* X86_64_VEX_0F385C */
6978   {
6979     { Bad_Opcode },
6980     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
6981   },
6982
6983   /* X86_64_VEX_0F385E */
6984   {
6985     { Bad_Opcode },
6986     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
6987   },
6988 };
6989
6990 static const struct dis386 three_byte_table[][256] = {
6991
6992   /* THREE_BYTE_0F38 */
6993   {
6994     /* 00 */
6995     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6996     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6997     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6998     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6999     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7000     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7001     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7002     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7003     /* 08 */
7004     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7005     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7006     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7007     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     /* 10 */
7013     { PREFIX_TABLE (PREFIX_0F3810) },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { PREFIX_TABLE (PREFIX_0F3814) },
7018     { PREFIX_TABLE (PREFIX_0F3815) },
7019     { Bad_Opcode },
7020     { PREFIX_TABLE (PREFIX_0F3817) },
7021     /* 18 */
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7027     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7028     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7029     { Bad_Opcode },
7030     /* 20 */
7031     { PREFIX_TABLE (PREFIX_0F3820) },
7032     { PREFIX_TABLE (PREFIX_0F3821) },
7033     { PREFIX_TABLE (PREFIX_0F3822) },
7034     { PREFIX_TABLE (PREFIX_0F3823) },
7035     { PREFIX_TABLE (PREFIX_0F3824) },
7036     { PREFIX_TABLE (PREFIX_0F3825) },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     /* 28 */
7040     { PREFIX_TABLE (PREFIX_0F3828) },
7041     { PREFIX_TABLE (PREFIX_0F3829) },
7042     { PREFIX_TABLE (PREFIX_0F382A) },
7043     { PREFIX_TABLE (PREFIX_0F382B) },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     /* 30 */
7049     { PREFIX_TABLE (PREFIX_0F3830) },
7050     { PREFIX_TABLE (PREFIX_0F3831) },
7051     { PREFIX_TABLE (PREFIX_0F3832) },
7052     { PREFIX_TABLE (PREFIX_0F3833) },
7053     { PREFIX_TABLE (PREFIX_0F3834) },
7054     { PREFIX_TABLE (PREFIX_0F3835) },
7055     { Bad_Opcode },
7056     { PREFIX_TABLE (PREFIX_0F3837) },
7057     /* 38 */
7058     { PREFIX_TABLE (PREFIX_0F3838) },
7059     { PREFIX_TABLE (PREFIX_0F3839) },
7060     { PREFIX_TABLE (PREFIX_0F383A) },
7061     { PREFIX_TABLE (PREFIX_0F383B) },
7062     { PREFIX_TABLE (PREFIX_0F383C) },
7063     { PREFIX_TABLE (PREFIX_0F383D) },
7064     { PREFIX_TABLE (PREFIX_0F383E) },
7065     { PREFIX_TABLE (PREFIX_0F383F) },
7066     /* 40 */
7067     { PREFIX_TABLE (PREFIX_0F3840) },
7068     { PREFIX_TABLE (PREFIX_0F3841) },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     /* 48 */
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     /* 50 */
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     /* 58 */
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     /* 60 */
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     /* 68 */
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     /* 70 */
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     /* 78 */
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     /* 80 */
7139     { PREFIX_TABLE (PREFIX_0F3880) },
7140     { PREFIX_TABLE (PREFIX_0F3881) },
7141     { PREFIX_TABLE (PREFIX_0F3882) },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     /* 88 */
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     /* 90 */
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     /* 98 */
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     /* a0 */
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     /* a8 */
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     /* b0 */
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     /* b8 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     /* c0 */
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     /* c8 */
7220     { PREFIX_TABLE (PREFIX_0F38C8) },
7221     { PREFIX_TABLE (PREFIX_0F38C9) },
7222     { PREFIX_TABLE (PREFIX_0F38CA) },
7223     { PREFIX_TABLE (PREFIX_0F38CB) },
7224     { PREFIX_TABLE (PREFIX_0F38CC) },
7225     { PREFIX_TABLE (PREFIX_0F38CD) },
7226     { Bad_Opcode },
7227     { PREFIX_TABLE (PREFIX_0F38CF) },
7228     /* d0 */
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     /* d8 */
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { PREFIX_TABLE (PREFIX_0F38DB) },
7242     { PREFIX_TABLE (PREFIX_0F38DC) },
7243     { PREFIX_TABLE (PREFIX_0F38DD) },
7244     { PREFIX_TABLE (PREFIX_0F38DE) },
7245     { PREFIX_TABLE (PREFIX_0F38DF) },
7246     /* e0 */
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     /* e8 */
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     /* f0 */
7265     { PREFIX_TABLE (PREFIX_0F38F0) },
7266     { PREFIX_TABLE (PREFIX_0F38F1) },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { PREFIX_TABLE (PREFIX_0F38F5) },
7271     { PREFIX_TABLE (PREFIX_0F38F6) },
7272     { Bad_Opcode },
7273     /* f8 */
7274     { PREFIX_TABLE (PREFIX_0F38F8) },
7275     { PREFIX_TABLE (PREFIX_0F38F9) },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282   },
7283   /* THREE_BYTE_0F3A */
7284   {
7285     /* 00 */
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     /* 08 */
7295     { PREFIX_TABLE (PREFIX_0F3A08) },
7296     { PREFIX_TABLE (PREFIX_0F3A09) },
7297     { PREFIX_TABLE (PREFIX_0F3A0A) },
7298     { PREFIX_TABLE (PREFIX_0F3A0B) },
7299     { PREFIX_TABLE (PREFIX_0F3A0C) },
7300     { PREFIX_TABLE (PREFIX_0F3A0D) },
7301     { PREFIX_TABLE (PREFIX_0F3A0E) },
7302     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7303     /* 10 */
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { PREFIX_TABLE (PREFIX_0F3A14) },
7309     { PREFIX_TABLE (PREFIX_0F3A15) },
7310     { PREFIX_TABLE (PREFIX_0F3A16) },
7311     { PREFIX_TABLE (PREFIX_0F3A17) },
7312     /* 18 */
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     /* 20 */
7322     { PREFIX_TABLE (PREFIX_0F3A20) },
7323     { PREFIX_TABLE (PREFIX_0F3A21) },
7324     { PREFIX_TABLE (PREFIX_0F3A22) },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     /* 28 */
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     /* 30 */
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     /* 38 */
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     /* 40 */
7358     { PREFIX_TABLE (PREFIX_0F3A40) },
7359     { PREFIX_TABLE (PREFIX_0F3A41) },
7360     { PREFIX_TABLE (PREFIX_0F3A42) },
7361     { Bad_Opcode },
7362     { PREFIX_TABLE (PREFIX_0F3A44) },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     /* 48 */
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     /* 50 */
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     /* 58 */
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     /* 60 */
7394     { PREFIX_TABLE (PREFIX_0F3A60) },
7395     { PREFIX_TABLE (PREFIX_0F3A61) },
7396     { PREFIX_TABLE (PREFIX_0F3A62) },
7397     { PREFIX_TABLE (PREFIX_0F3A63) },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     /* 68 */
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     /* 70 */
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     /* 78 */
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     /* 80 */
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     /* 88 */
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     /* 90 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     /* 98 */
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     /* a0 */
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     /* a8 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     /* b0 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     /* b8 */
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     /* c0 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* c8 */
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { PREFIX_TABLE (PREFIX_0F3ACC) },
7516     { Bad_Opcode },
7517     { PREFIX_TABLE (PREFIX_0F3ACE) },
7518     { PREFIX_TABLE (PREFIX_0F3ACF) },
7519     /* d0 */
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     /* d8 */
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { PREFIX_TABLE (PREFIX_0F3ADF) },
7537     /* e0 */
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     /* e8 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* f0 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* f8 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573   },
7574 };
7575
7576 static const struct dis386 xop_table[][256] = {
7577   /* XOP_08 */
7578   {
7579     /* 00 */
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     /* 08 */
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     /* 10 */
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     /* 18 */
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     /* 20 */
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     /* 28 */
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     /* 30 */
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     /* 38 */
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     /* 40 */
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     /* 48 */
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     /* 50 */
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     /* 58 */
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     /* 60 */
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     /* 68 */
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     /* 70 */
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     /* 78 */
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     /* 80 */
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
7730     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
7731     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
7732     /* 88 */
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
7740     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
7741     /* 90 */
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
7748     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
7749     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
7750     /* 98 */
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
7758     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
7759     /* a0 */
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
7763     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
7767     { Bad_Opcode },
7768     /* a8 */
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     /* b0 */
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
7785     { Bad_Opcode },
7786     /* b8 */
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     /* c0 */
7796     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
7797     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
7798     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
7799     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     /* c8 */
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7810     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7811     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7812     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7813     /* d0 */
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     /* d8 */
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     /* e0 */
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     /* e8 */
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7846     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7847     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7848     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7849     /* f0 */
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     /* f8 */
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867   },
7868   /* XOP_09 */
7869   {
7870     /* 00 */
7871     { Bad_Opcode },
7872     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
7873     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     /* 08 */
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     /* 10 */
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     /* 18 */
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     /* 20 */
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     /* 28 */
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     /* 30 */
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     /* 38 */
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     /* 40 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     /* 48 */
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     /* 50 */
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* 58 */
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     /* 60 */
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     /* 68 */
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     /* 70 */
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     /* 78 */
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     /* 80 */
8015     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
8016     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
8017     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
8018     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     /* 88 */
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     /* 90 */
8033     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
8034     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
8035     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
8036     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
8037     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
8038     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
8039     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
8040     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
8041     /* 98 */
8042     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
8043     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
8044     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
8045     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     /* a0 */
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     /* a8 */
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     /* b0 */
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     /* b8 */
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     /* c0 */
8087     { Bad_Opcode },
8088     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
8089     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
8090     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
8094     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
8095     /* c8 */
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     /* d0 */
8105     { Bad_Opcode },
8106     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
8107     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
8108     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
8112     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
8113     /* d8 */
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     /* e0 */
8123     { Bad_Opcode },
8124     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
8125     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
8126     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     /* e8 */
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     /* f0 */
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     /* f8 */
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158   },
8159   /* XOP_0A */
8160   {
8161     /* 00 */
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     /* 08 */
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     /* 10 */
8180     { "bextrS", { Gdq, Edq, Id }, 0 },
8181     { Bad_Opcode },
8182     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     /* 18 */
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     /* 20 */
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     /* 28 */
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     /* 30 */
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     /* 38 */
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     /* 40 */
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     /* 48 */
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     /* 50 */
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     /* 58 */
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     /* 60 */
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     /* 68 */
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     /* 70 */
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     /* 78 */
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     /* 80 */
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     /* 88 */
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* 90 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* 98 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* a0 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* a8 */
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     /* b0 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* b8 */
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     /* c0 */
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     /* c8 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* d0 */
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     /* d8 */
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     /* e0 */
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     /* e8 */
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     /* f0 */
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     /* f8 */
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449   },
8450 };
8451
8452 static const struct dis386 vex_table[][256] = {
8453   /* VEX_0F */
8454   {
8455     /* 00 */
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     /* 08 */
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     /* 10 */
8474     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8475     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8476     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8477     { MOD_TABLE (MOD_VEX_0F13) },
8478     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8479     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8480     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8481     { MOD_TABLE (MOD_VEX_0F17) },
8482     /* 18 */
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     /* 20 */
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     /* 28 */
8501     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8502     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8503     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8504     { MOD_TABLE (MOD_VEX_0F2B) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8506     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8509     /* 30 */
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     /* 38 */
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     /* 40 */
8528     { Bad_Opcode },
8529     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8531     { Bad_Opcode },
8532     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8536     /* 48 */
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     /* 50 */
8546     { MOD_TABLE (MOD_VEX_0F50) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8550     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8551     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8552     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8553     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8554     /* 58 */
8555     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8560     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8563     /* 60 */
8564     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8572     /* 68 */
8573     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8581     /* 70 */
8582     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8583     { REG_TABLE (REG_VEX_0F71) },
8584     { REG_TABLE (REG_VEX_0F72) },
8585     { REG_TABLE (REG_VEX_0F73) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8589     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8590     /* 78 */
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8599     /* 80 */
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     /* 88 */
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     /* 90 */
8618     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     /* 98 */
8627     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     /* a0 */
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     /* a8 */
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { REG_TABLE (REG_VEX_0FAE) },
8652     { Bad_Opcode },
8653     /* b0 */
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     /* b8 */
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     /* c0 */
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8675     { Bad_Opcode },
8676     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8678     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8679     { Bad_Opcode },
8680     /* c8 */
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     /* d0 */
8690     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8698     /* d8 */
8699     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8707     /* e0 */
8708     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8716     /* e8 */
8717     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8721     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8722     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8723     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8724     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8725     /* f0 */
8726     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8727     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8728     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8729     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8730     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8731     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8732     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8733     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8734     /* f8 */
8735     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8736     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8738     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8739     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8740     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8741     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8742     { Bad_Opcode },
8743   },
8744   /* VEX_0F38 */
8745   {
8746     /* 00 */
8747     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8755     /* 08 */
8756     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8764     /* 10 */
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8773     /* 18 */
8774     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8777     { Bad_Opcode },
8778     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8781     { Bad_Opcode },
8782     /* 20 */
8783     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     /* 28 */
8792     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8800     /* 30 */
8801     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8809     /* 38 */
8810     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8818     /* 40 */
8819     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8827     /* 48 */
8828     { Bad_Opcode },
8829     { X86_64_TABLE (X86_64_VEX_0F3849) },
8830     { Bad_Opcode },
8831     { X86_64_TABLE (X86_64_VEX_0F384B) },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     /* 50 */
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     /* 58 */
8846     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8849     { Bad_Opcode },
8850     { X86_64_TABLE (X86_64_VEX_0F385C) },
8851     { Bad_Opcode },
8852     { X86_64_TABLE (X86_64_VEX_0F385E) },
8853     { Bad_Opcode },
8854     /* 60 */
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     /* 68 */
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     /* 70 */
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     /* 78 */
8882     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     /* 80 */
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     /* 88 */
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8905     { Bad_Opcode },
8906     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8907     { Bad_Opcode },
8908     /* 90 */
8909     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8917     /* 98 */
8918     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8926     /* a0 */
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8935     /* a8 */
8936     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8944     /* b0 */
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8953     /* b8 */
8954     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8962     /* c0 */
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     /* c8 */
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8980     /* d0 */
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     /* d8 */
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8998     /* e0 */
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     /* e8 */
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     /* f0 */
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9020     { REG_TABLE (REG_VEX_0F38F3) },
9021     { Bad_Opcode },
9022     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9025     /* f8 */
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034   },
9035   /* VEX_0F3A */
9036   {
9037     /* 00 */
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9041     { Bad_Opcode },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9045     { Bad_Opcode },
9046     /* 08 */
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9055     /* 10 */
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9064     /* 18 */
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     /* 20 */
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     /* 28 */
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     /* 30 */
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     /* 38 */
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     /* 40 */
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9113     { Bad_Opcode },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9115     { Bad_Opcode },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9117     { Bad_Opcode },
9118     /* 48 */
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     /* 50 */
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     /* 58 */
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9144     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9145     /* 60 */
9146     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     /* 68 */
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9161     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9162     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9163     /* 70 */
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     /* 78 */
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9177     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9180     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9181     /* 80 */
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     /* 88 */
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     /* 90 */
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     /* 98 */
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     /* a0 */
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     /* a8 */
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     /* b0 */
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     /* b8 */
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     /* c0 */
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     /* c8 */
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9270     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9271     /* d0 */
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     /* d8 */
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9289     /* e0 */
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     /* e8 */
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     /* f0 */
9308     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     /* f8 */
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325   },
9326 };
9327
9328 #include "i386-dis-evex.h"
9329
9330 static const struct dis386 vex_len_table[][2] = {
9331   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9332   {
9333     { "vmovlpX",        { XM, Vex, EXq }, 0 },
9334   },
9335
9336   /* VEX_LEN_0F12_P_0_M_1 */
9337   {
9338     { "vmovhlps",       { XM, Vex, EXq }, 0 },
9339   },
9340
9341   /* VEX_LEN_0F13_M_0 */
9342   {
9343     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9344   },
9345
9346   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9347   {
9348     { "vmovhpX",        { XM, Vex, EXq }, 0 },
9349   },
9350
9351   /* VEX_LEN_0F16_P_0_M_1 */
9352   {
9353     { "vmovlhps",       { XM, Vex, EXq }, 0 },
9354   },
9355
9356   /* VEX_LEN_0F17_M_0 */
9357   {
9358     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9359   },
9360
9361   /* VEX_LEN_0F41_P_0 */
9362   {
9363     { Bad_Opcode },
9364     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9365   },
9366   /* VEX_LEN_0F41_P_2 */
9367   {
9368     { Bad_Opcode },
9369     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9370   },
9371   /* VEX_LEN_0F42_P_0 */
9372   {
9373     { Bad_Opcode },
9374     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9375   },
9376   /* VEX_LEN_0F42_P_2 */
9377   {
9378     { Bad_Opcode },
9379     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9380   },
9381   /* VEX_LEN_0F44_P_0 */
9382   {
9383     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9384   },
9385   /* VEX_LEN_0F44_P_2 */
9386   {
9387     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9388   },
9389   /* VEX_LEN_0F45_P_0 */
9390   {
9391     { Bad_Opcode },
9392     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9393   },
9394   /* VEX_LEN_0F45_P_2 */
9395   {
9396     { Bad_Opcode },
9397     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9398   },
9399   /* VEX_LEN_0F46_P_0 */
9400   {
9401     { Bad_Opcode },
9402     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9403   },
9404   /* VEX_LEN_0F46_P_2 */
9405   {
9406     { Bad_Opcode },
9407     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9408   },
9409   /* VEX_LEN_0F47_P_0 */
9410   {
9411     { Bad_Opcode },
9412     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9413   },
9414   /* VEX_LEN_0F47_P_2 */
9415   {
9416     { Bad_Opcode },
9417     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9418   },
9419   /* VEX_LEN_0F4A_P_0 */
9420   {
9421     { Bad_Opcode },
9422     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9423   },
9424   /* VEX_LEN_0F4A_P_2 */
9425   {
9426     { Bad_Opcode },
9427     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9428   },
9429   /* VEX_LEN_0F4B_P_0 */
9430   {
9431     { Bad_Opcode },
9432     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9433   },
9434   /* VEX_LEN_0F4B_P_2 */
9435   {
9436     { Bad_Opcode },
9437     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9438   },
9439
9440   /* VEX_LEN_0F6E_P_2 */
9441   {
9442     { "vmovK",          { XMScalar, Edq }, 0 },
9443   },
9444
9445   /* VEX_LEN_0F77_P_1 */
9446   {
9447     { "vzeroupper",     { XX }, 0 },
9448     { "vzeroall",       { XX }, 0 },
9449   },
9450
9451   /* VEX_LEN_0F7E_P_1 */
9452   {
9453     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9454   },
9455
9456   /* VEX_LEN_0F7E_P_2 */
9457   {
9458     { "vmovK",          { Edq, XMScalar }, 0 },
9459   },
9460
9461   /* VEX_LEN_0F90_P_0 */
9462   {
9463     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9464   },
9465
9466   /* VEX_LEN_0F90_P_2 */
9467   {
9468     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9469   },
9470
9471   /* VEX_LEN_0F91_P_0 */
9472   {
9473     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9474   },
9475
9476   /* VEX_LEN_0F91_P_2 */
9477   {
9478     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9479   },
9480
9481   /* VEX_LEN_0F92_P_0 */
9482   {
9483     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9484   },
9485
9486   /* VEX_LEN_0F92_P_2 */
9487   {
9488     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9489   },
9490
9491   /* VEX_LEN_0F92_P_3 */
9492   {
9493     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9494   },
9495
9496   /* VEX_LEN_0F93_P_0 */
9497   {
9498     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9499   },
9500
9501   /* VEX_LEN_0F93_P_2 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9504   },
9505
9506   /* VEX_LEN_0F93_P_3 */
9507   {
9508     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9509   },
9510
9511   /* VEX_LEN_0F98_P_0 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9514   },
9515
9516   /* VEX_LEN_0F98_P_2 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9519   },
9520
9521   /* VEX_LEN_0F99_P_0 */
9522   {
9523     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9524   },
9525
9526   /* VEX_LEN_0F99_P_2 */
9527   {
9528     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9529   },
9530
9531   /* VEX_LEN_0FAE_R_2_M_0 */
9532   {
9533     { "vldmxcsr",       { Md }, 0 },
9534   },
9535
9536   /* VEX_LEN_0FAE_R_3_M_0 */
9537   {
9538     { "vstmxcsr",       { Md }, 0 },
9539   },
9540
9541   /* VEX_LEN_0FC4_P_2 */
9542   {
9543     { "vpinsrw",        { XM, Vex, Edqw, Ib }, 0 },
9544   },
9545
9546   /* VEX_LEN_0FC5_P_2 */
9547   {
9548     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9549   },
9550
9551   /* VEX_LEN_0FD6_P_2 */
9552   {
9553     { "vmovq",          { EXqS, XMScalar }, 0 },
9554   },
9555
9556   /* VEX_LEN_0FF7_P_2 */
9557   {
9558     { "vmaskmovdqu",    { XM, XS }, 0 },
9559   },
9560
9561   /* VEX_LEN_0F3816_P_2 */
9562   {
9563     { Bad_Opcode },
9564     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9565   },
9566
9567   /* VEX_LEN_0F3819_P_2 */
9568   {
9569     { Bad_Opcode },
9570     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9571   },
9572
9573   /* VEX_LEN_0F381A_P_2_M_0 */
9574   {
9575     { Bad_Opcode },
9576     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0_L_0) },
9577   },
9578
9579   /* VEX_LEN_0F3836_P_2 */
9580   {
9581     { Bad_Opcode },
9582     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9583   },
9584
9585   /* VEX_LEN_0F3841_P_2 */
9586   {
9587     { "vphminposuw",    { XM, EXx }, 0 },
9588   },
9589
9590    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
9591   {
9592     { "ldtilecfg", { M }, 0 },
9593   },
9594
9595   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
9596   {
9597     { "tilerelease", { Skip_MODRM }, 0 },
9598   },
9599
9600   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
9601   {
9602     { "sttilecfg", { M }, 0 },
9603   },
9604
9605   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
9606   {
9607     { "tilezero", { TMM, Skip_MODRM }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
9611   {
9612     { "tilestored", { MVexSIBMEM, TMM }, 0 },
9613   },
9614   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
9615   {
9616     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
9617   },
9618
9619   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
9620   {
9621     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
9622   },
9623
9624   /* VEX_LEN_0F385A_P_2_M_0 */
9625   {
9626     { Bad_Opcode },
9627     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0_L_0) },
9628   },
9629
9630   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
9631   {
9632     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
9633   },
9634
9635   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
9636   {
9637     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
9638   },
9639
9640   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
9641   {
9642     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
9643   },
9644
9645   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
9646   {
9647     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
9648   },
9649
9650   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
9651   {
9652     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
9653   },
9654
9655   /* VEX_LEN_0F38DB_P_2 */
9656   {
9657     { "vaesimc",        { XM, EXx }, 0 },
9658   },
9659
9660   /* VEX_LEN_0F38F2_P_0 */
9661   {
9662     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9663   },
9664
9665   /* VEX_LEN_0F38F3_R_1_P_0 */
9666   {
9667     { "blsrS",          { VexGdq, Edq }, 0 },
9668   },
9669
9670   /* VEX_LEN_0F38F3_R_2_P_0 */
9671   {
9672     { "blsmskS",        { VexGdq, Edq }, 0 },
9673   },
9674
9675   /* VEX_LEN_0F38F3_R_3_P_0 */
9676   {
9677     { "blsiS",          { VexGdq, Edq }, 0 },
9678   },
9679
9680   /* VEX_LEN_0F38F5_P_0 */
9681   {
9682     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9683   },
9684
9685   /* VEX_LEN_0F38F5_P_1 */
9686   {
9687     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9688   },
9689
9690   /* VEX_LEN_0F38F5_P_3 */
9691   {
9692     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9693   },
9694
9695   /* VEX_LEN_0F38F6_P_3 */
9696   {
9697     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9698   },
9699
9700   /* VEX_LEN_0F38F7_P_0 */
9701   {
9702     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9703   },
9704
9705   /* VEX_LEN_0F38F7_P_1 */
9706   {
9707     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9708   },
9709
9710   /* VEX_LEN_0F38F7_P_2 */
9711   {
9712     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9713   },
9714
9715   /* VEX_LEN_0F38F7_P_3 */
9716   {
9717     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9718   },
9719
9720   /* VEX_LEN_0F3A00_P_2 */
9721   {
9722     { Bad_Opcode },
9723     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9724   },
9725
9726   /* VEX_LEN_0F3A01_P_2 */
9727   {
9728     { Bad_Opcode },
9729     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9730   },
9731
9732   /* VEX_LEN_0F3A06_P_2 */
9733   {
9734     { Bad_Opcode },
9735     { VEX_W_TABLE (VEX_W_0F3A06_P_2_L_0) },
9736   },
9737
9738   /* VEX_LEN_0F3A14_P_2 */
9739   {
9740     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9741   },
9742
9743   /* VEX_LEN_0F3A15_P_2 */
9744   {
9745     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9746   },
9747
9748   /* VEX_LEN_0F3A16_P_2  */
9749   {
9750     { "vpextrK",        { Edq, XM, Ib }, 0 },
9751   },
9752
9753   /* VEX_LEN_0F3A17_P_2 */
9754   {
9755     { "vextractps",     { Edqd, XM, Ib }, 0 },
9756   },
9757
9758   /* VEX_LEN_0F3A18_P_2 */
9759   {
9760     { Bad_Opcode },
9761     { VEX_W_TABLE (VEX_W_0F3A18_P_2_L_0) },
9762   },
9763
9764   /* VEX_LEN_0F3A19_P_2 */
9765   {
9766     { Bad_Opcode },
9767     { VEX_W_TABLE (VEX_W_0F3A19_P_2_L_0) },
9768   },
9769
9770   /* VEX_LEN_0F3A20_P_2 */
9771   {
9772     { "vpinsrb",        { XM, Vex, Edqb, Ib }, 0 },
9773   },
9774
9775   /* VEX_LEN_0F3A21_P_2 */
9776   {
9777     { "vinsertps",      { XM, Vex, EXd, Ib }, 0 },
9778   },
9779
9780   /* VEX_LEN_0F3A22_P_2 */
9781   {
9782     { "vpinsrK",        { XM, Vex, Edq, Ib }, 0 },
9783   },
9784
9785   /* VEX_LEN_0F3A30_P_2 */
9786   {
9787     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9788   },
9789
9790   /* VEX_LEN_0F3A31_P_2 */
9791   {
9792     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9793   },
9794
9795   /* VEX_LEN_0F3A32_P_2 */
9796   {
9797     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9798   },
9799
9800   /* VEX_LEN_0F3A33_P_2 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9803   },
9804
9805   /* VEX_LEN_0F3A38_P_2 */
9806   {
9807     { Bad_Opcode },
9808     { VEX_W_TABLE (VEX_W_0F3A38_P_2_L_0) },
9809   },
9810
9811   /* VEX_LEN_0F3A39_P_2 */
9812   {
9813     { Bad_Opcode },
9814     { VEX_W_TABLE (VEX_W_0F3A39_P_2_L_0) },
9815   },
9816
9817   /* VEX_LEN_0F3A41_P_2 */
9818   {
9819     { "vdppd",          { XM, Vex, EXx, Ib }, 0 },
9820   },
9821
9822   /* VEX_LEN_0F3A46_P_2 */
9823   {
9824     { Bad_Opcode },
9825     { VEX_W_TABLE (VEX_W_0F3A46_P_2_L_0) },
9826   },
9827
9828   /* VEX_LEN_0F3A60_P_2 */
9829   {
9830     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, 0 },
9831   },
9832
9833   /* VEX_LEN_0F3A61_P_2 */
9834   {
9835     { "vpcmpestri!%LQ", { XM, EXx, Ib }, 0 },
9836   },
9837
9838   /* VEX_LEN_0F3A62_P_2 */
9839   {
9840     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9841   },
9842
9843   /* VEX_LEN_0F3A63_P_2 */
9844   {
9845     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9846   },
9847
9848   /* VEX_LEN_0F3ADF_P_2 */
9849   {
9850     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9851   },
9852
9853   /* VEX_LEN_0F3AF0_P_3 */
9854   {
9855     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9856   },
9857
9858   /* VEX_LEN_0FXOP_08_85 */
9859   {
9860     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
9861   },
9862
9863   /* VEX_LEN_0FXOP_08_86 */
9864   {
9865     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
9866   },
9867
9868   /* VEX_LEN_0FXOP_08_87 */
9869   {
9870     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
9871   },
9872
9873   /* VEX_LEN_0FXOP_08_8E */
9874   {
9875     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
9876   },
9877
9878   /* VEX_LEN_0FXOP_08_8F */
9879   {
9880     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
9881   },
9882
9883   /* VEX_LEN_0FXOP_08_95 */
9884   {
9885     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
9886   },
9887
9888   /* VEX_LEN_0FXOP_08_96 */
9889   {
9890     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
9891   },
9892
9893   /* VEX_LEN_0FXOP_08_97 */
9894   {
9895     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
9896   },
9897
9898   /* VEX_LEN_0FXOP_08_9E */
9899   {
9900     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
9901   },
9902
9903   /* VEX_LEN_0FXOP_08_9F */
9904   {
9905     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
9906   },
9907
9908   /* VEX_LEN_0FXOP_08_A3 */
9909   {
9910     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
9911   },
9912
9913   /* VEX_LEN_0FXOP_08_A6 */
9914   {
9915     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
9916   },
9917
9918   /* VEX_LEN_0FXOP_08_B6 */
9919   {
9920     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
9921   },
9922
9923   /* VEX_LEN_0FXOP_08_C0 */
9924   {
9925     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
9926   },
9927
9928   /* VEX_LEN_0FXOP_08_C1 */
9929   {
9930     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
9931   },
9932
9933   /* VEX_LEN_0FXOP_08_C2 */
9934   {
9935     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
9936   },
9937
9938   /* VEX_LEN_0FXOP_08_C3 */
9939   {
9940     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
9941   },
9942
9943   /* VEX_LEN_0FXOP_08_CC */
9944   {
9945     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
9946   },
9947
9948   /* VEX_LEN_0FXOP_08_CD */
9949   {
9950     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
9951   },
9952
9953   /* VEX_LEN_0FXOP_08_CE */
9954   {
9955     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
9956   },
9957
9958   /* VEX_LEN_0FXOP_08_CF */
9959   {
9960     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
9961   },
9962
9963   /* VEX_LEN_0FXOP_08_EC */
9964   {
9965     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
9966   },
9967
9968   /* VEX_LEN_0FXOP_08_ED */
9969   {
9970     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
9971   },
9972
9973   /* VEX_LEN_0FXOP_08_EE */
9974   {
9975     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
9976   },
9977
9978   /* VEX_LEN_0FXOP_08_EF */
9979   {
9980     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
9981   },
9982
9983   /* VEX_LEN_0FXOP_09_01 */
9984   {
9985     { REG_TABLE (REG_0FXOP_09_01_L_0) },
9986   },
9987
9988   /* VEX_LEN_0FXOP_09_02 */
9989   {
9990     { REG_TABLE (REG_0FXOP_09_02_L_0) },
9991   },
9992
9993   /* VEX_LEN_0FXOP_09_12_M_1 */
9994   {
9995     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
9996   },
9997
9998   /* VEX_LEN_0FXOP_09_82_W_0 */
9999   {
10000     { "vfrczss",        { XM, EXd }, 0 },
10001   },
10002
10003   /* VEX_LEN_0FXOP_09_83_W_0 */
10004   {
10005     { "vfrczsd",        { XM, EXq }, 0 },
10006   },
10007
10008   /* VEX_LEN_0FXOP_09_90 */
10009   {
10010     { "vprotb",         { XM, EXx, VexW }, 0 },
10011   },
10012
10013   /* VEX_LEN_0FXOP_09_91 */
10014   {
10015     { "vprotw",         { XM, EXx, VexW }, 0 },
10016   },
10017
10018   /* VEX_LEN_0FXOP_09_92 */
10019   {
10020     { "vprotd",         { XM, EXx, VexW }, 0 },
10021   },
10022
10023   /* VEX_LEN_0FXOP_09_93 */
10024   {
10025     { "vprotq",         { XM, EXx, VexW }, 0 },
10026   },
10027
10028   /* VEX_LEN_0FXOP_09_94 */
10029   {
10030     { "vpshlb",         { XM, EXx, VexW }, 0 },
10031   },
10032
10033   /* VEX_LEN_0FXOP_09_95 */
10034   {
10035     { "vpshlw",         { XM, EXx, VexW }, 0 },
10036   },
10037
10038   /* VEX_LEN_0FXOP_09_96 */
10039   {
10040     { "vpshld",         { XM, EXx, VexW }, 0 },
10041   },
10042
10043   /* VEX_LEN_0FXOP_09_97 */
10044   {
10045     { "vpshlq",         { XM, EXx, VexW }, 0 },
10046   },
10047
10048   /* VEX_LEN_0FXOP_09_98 */
10049   {
10050     { "vpshab",         { XM, EXx, VexW }, 0 },
10051   },
10052
10053   /* VEX_LEN_0FXOP_09_99 */
10054   {
10055     { "vpshaw",         { XM, EXx, VexW }, 0 },
10056   },
10057
10058   /* VEX_LEN_0FXOP_09_9A */
10059   {
10060     { "vpshad",         { XM, EXx, VexW }, 0 },
10061   },
10062
10063   /* VEX_LEN_0FXOP_09_9B */
10064   {
10065     { "vpshaq",         { XM, EXx, VexW }, 0 },
10066   },
10067
10068   /* VEX_LEN_0FXOP_09_C1 */
10069   {
10070     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
10071   },
10072
10073   /* VEX_LEN_0FXOP_09_C2 */
10074   {
10075     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
10076   },
10077
10078   /* VEX_LEN_0FXOP_09_C3 */
10079   {
10080     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
10081   },
10082
10083   /* VEX_LEN_0FXOP_09_C6 */
10084   {
10085     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
10086   },
10087
10088   /* VEX_LEN_0FXOP_09_C7 */
10089   {
10090     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
10091   },
10092
10093   /* VEX_LEN_0FXOP_09_CB */
10094   {
10095     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
10096   },
10097
10098   /* VEX_LEN_0FXOP_09_D1 */
10099   {
10100     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
10101   },
10102
10103   /* VEX_LEN_0FXOP_09_D2 */
10104   {
10105     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
10106   },
10107
10108   /* VEX_LEN_0FXOP_09_D3 */
10109   {
10110     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
10111   },
10112
10113   /* VEX_LEN_0FXOP_09_D6 */
10114   {
10115     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
10116   },
10117
10118   /* VEX_LEN_0FXOP_09_D7 */
10119   {
10120     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
10121   },
10122
10123   /* VEX_LEN_0FXOP_09_DB */
10124   {
10125     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
10126   },
10127
10128   /* VEX_LEN_0FXOP_09_E1 */
10129   {
10130     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
10131   },
10132
10133   /* VEX_LEN_0FXOP_09_E2 */
10134   {
10135     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
10136   },
10137
10138   /* VEX_LEN_0FXOP_09_E3 */
10139   {
10140     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
10141   },
10142
10143   /* VEX_LEN_0FXOP_0A_12 */
10144   {
10145     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
10146   },
10147 };
10148
10149 #include "i386-dis-evex-len.h"
10150
10151 static const struct dis386 vex_w_table[][2] = {
10152   {
10153     /* VEX_W_0F41_P_0_LEN_1 */
10154     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10155     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10156   },
10157   {
10158     /* VEX_W_0F41_P_2_LEN_1 */
10159     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10160     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10161   },
10162   {
10163     /* VEX_W_0F42_P_0_LEN_1 */
10164     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10165     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10166   },
10167   {
10168     /* VEX_W_0F42_P_2_LEN_1 */
10169     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10170     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10171   },
10172   {
10173     /* VEX_W_0F44_P_0_LEN_0 */
10174     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10175     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10176   },
10177   {
10178     /* VEX_W_0F44_P_2_LEN_0 */
10179     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10180     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10181   },
10182   {
10183     /* VEX_W_0F45_P_0_LEN_1 */
10184     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10185     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10186   },
10187   {
10188     /* VEX_W_0F45_P_2_LEN_1 */
10189     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10190     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10191   },
10192   {
10193     /* VEX_W_0F46_P_0_LEN_1 */
10194     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10195     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10196   },
10197   {
10198     /* VEX_W_0F46_P_2_LEN_1 */
10199     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10200     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10201   },
10202   {
10203     /* VEX_W_0F47_P_0_LEN_1 */
10204     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10205     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10206   },
10207   {
10208     /* VEX_W_0F47_P_2_LEN_1 */
10209     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10210     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10211   },
10212   {
10213     /* VEX_W_0F4A_P_0_LEN_1 */
10214     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10215     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10216   },
10217   {
10218     /* VEX_W_0F4A_P_2_LEN_1 */
10219     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10220     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10221   },
10222   {
10223     /* VEX_W_0F4B_P_0_LEN_1 */
10224     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10225     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10226   },
10227   {
10228     /* VEX_W_0F4B_P_2_LEN_1 */
10229     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10230   },
10231   {
10232     /* VEX_W_0F90_P_0_LEN_0 */
10233     { "kmovw",          { MaskG, MaskE }, 0 },
10234     { "kmovq",          { MaskG, MaskE }, 0 },
10235   },
10236   {
10237     /* VEX_W_0F90_P_2_LEN_0 */
10238     { "kmovb",          { MaskG, MaskBDE }, 0 },
10239     { "kmovd",          { MaskG, MaskBDE }, 0 },
10240   },
10241   {
10242     /* VEX_W_0F91_P_0_LEN_0 */
10243     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10244     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10245   },
10246   {
10247     /* VEX_W_0F91_P_2_LEN_0 */
10248     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10249     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10250   },
10251   {
10252     /* VEX_W_0F92_P_0_LEN_0 */
10253     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10254   },
10255   {
10256     /* VEX_W_0F92_P_2_LEN_0 */
10257     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10258   },
10259   {
10260     /* VEX_W_0F93_P_0_LEN_0 */
10261     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10262   },
10263   {
10264     /* VEX_W_0F93_P_2_LEN_0 */
10265     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10266   },
10267   {
10268     /* VEX_W_0F98_P_0_LEN_0 */
10269     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10270     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10271   },
10272   {
10273     /* VEX_W_0F98_P_2_LEN_0 */
10274     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10275     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10276   },
10277   {
10278     /* VEX_W_0F99_P_0_LEN_0 */
10279     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10280     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10281   },
10282   {
10283     /* VEX_W_0F99_P_2_LEN_0 */
10284     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10285     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10286   },
10287   {
10288     /* VEX_W_0F380C_P_2  */
10289     { "vpermilps",      { XM, Vex, EXx }, 0 },
10290   },
10291   {
10292     /* VEX_W_0F380D_P_2  */
10293     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10294   },
10295   {
10296     /* VEX_W_0F380E_P_2  */
10297     { "vtestps",        { XM, EXx }, 0 },
10298   },
10299   {
10300     /* VEX_W_0F380F_P_2  */
10301     { "vtestpd",        { XM, EXx }, 0 },
10302   },
10303   {
10304     /* VEX_W_0F3813_P_2 */
10305     { "vcvtph2ps", { XM, EXxmmq }, 0 },
10306   },
10307   {
10308     /* VEX_W_0F3816_P_2  */
10309     { "vpermps",        { XM, Vex, EXx }, 0 },
10310   },
10311   {
10312     /* VEX_W_0F3818_P_2 */
10313     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10314   },
10315   {
10316     /* VEX_W_0F3819_P_2 */
10317     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10318   },
10319   {
10320     /* VEX_W_0F381A_P_2_M_0_L_0 */
10321     { "vbroadcastf128", { XM, Mxmm }, 0 },
10322   },
10323   {
10324     /* VEX_W_0F382C_P_2_M_0 */
10325     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10326   },
10327   {
10328     /* VEX_W_0F382D_P_2_M_0 */
10329     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10330   },
10331   {
10332     /* VEX_W_0F382E_P_2_M_0 */
10333     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10334   },
10335   {
10336     /* VEX_W_0F382F_P_2_M_0 */
10337     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10338   },
10339   {
10340     /* VEX_W_0F3836_P_2  */
10341     { "vpermd",         { XM, Vex, EXx }, 0 },
10342   },
10343   {
10344     /* VEX_W_0F3846_P_2 */
10345     { "vpsravd",        { XM, Vex, EXx }, 0 },
10346   },
10347   {
10348     /* VEX_W_0F3849_X86_64_P_0 */
10349     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
10350   },
10351   {
10352     /* VEX_W_0F3849_X86_64_P_2 */
10353     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
10354   },
10355   {
10356     /* VEX_W_0F3849_X86_64_P_3 */
10357     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
10358   },
10359   {
10360     /* VEX_W_0F384B_X86_64_P_1 */
10361     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
10362   },
10363   {
10364     /* VEX_W_0F384B_X86_64_P_2 */
10365     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
10366   },
10367   {
10368     /* VEX_W_0F384B_X86_64_P_3 */
10369     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
10370   },
10371   {
10372     /* VEX_W_0F3858_P_2 */
10373     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10374   },
10375   {
10376     /* VEX_W_0F3859_P_2 */
10377     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10378   },
10379   {
10380     /* VEX_W_0F385A_P_2_M_0_L_0 */
10381     { "vbroadcasti128", { XM, Mxmm }, 0 },
10382   },
10383   {
10384     /* VEX_W_0F385C_X86_64_P_1 */
10385     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
10386   },
10387   {
10388     /* VEX_W_0F385E_X86_64_P_0 */
10389     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
10390   },
10391   {
10392     /* VEX_W_0F385E_X86_64_P_1 */
10393     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
10394   },
10395   {
10396     /* VEX_W_0F385E_X86_64_P_2 */
10397     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
10398   },
10399   {
10400     /* VEX_W_0F385E_X86_64_P_3 */
10401     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
10402   },
10403   {
10404     /* VEX_W_0F3878_P_2 */
10405     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10406   },
10407   {
10408     /* VEX_W_0F3879_P_2 */
10409     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10410   },
10411   {
10412     /* VEX_W_0F38CF_P_2 */
10413     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10414   },
10415   {
10416     /* VEX_W_0F3A00_P_2 */
10417     { Bad_Opcode },
10418     { "vpermq",         { XM, EXx, Ib }, 0 },
10419   },
10420   {
10421     /* VEX_W_0F3A01_P_2 */
10422     { Bad_Opcode },
10423     { "vpermpd",        { XM, EXx, Ib }, 0 },
10424   },
10425   {
10426     /* VEX_W_0F3A02_P_2 */
10427     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10428   },
10429   {
10430     /* VEX_W_0F3A04_P_2 */
10431     { "vpermilps",      { XM, EXx, Ib }, 0 },
10432   },
10433   {
10434     /* VEX_W_0F3A05_P_2 */
10435     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10436   },
10437   {
10438     /* VEX_W_0F3A06_P_2_L_0 */
10439     { "vperm2f128",     { XM, Vex, EXx, Ib }, 0 },
10440   },
10441   {
10442     /* VEX_W_0F3A18_P_2_L_0 */
10443     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, 0 },
10444   },
10445   {
10446     /* VEX_W_0F3A19_P_2_L_0 */
10447     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10448   },
10449   {
10450     /* VEX_W_0F3A1D_P_2 */
10451     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10452   },
10453   {
10454     /* VEX_W_0F3A30_P_2_LEN_0 */
10455     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10456     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10457   },
10458   {
10459     /* VEX_W_0F3A31_P_2_LEN_0 */
10460     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10461     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10462   },
10463   {
10464     /* VEX_W_0F3A32_P_2_LEN_0 */
10465     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10466     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10467   },
10468   {
10469     /* VEX_W_0F3A33_P_2_LEN_0 */
10470     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10471     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10472   },
10473   {
10474     /* VEX_W_0F3A38_P_2_L_0 */
10475     { "vinserti128",    { XM, Vex, EXxmm, Ib }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F3A39_P_2_L_0 */
10479     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10480   },
10481   {
10482     /* VEX_W_0F3A46_P_2_L_0 */
10483     { "vperm2i128",     { XM, Vex, EXx, Ib }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F3A4A_P_2 */
10487     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F3A4B_P_2 */
10491     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F3A4C_P_2 */
10495     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F3ACE_P_2 */
10499     { Bad_Opcode },
10500     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10501   },
10502   {
10503     /* VEX_W_0F3ACF_P_2 */
10504     { Bad_Opcode },
10505     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10506   },
10507   /* VEX_W_0FXOP_08_85_L_0 */
10508   {
10509     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
10510   },
10511   /* VEX_W_0FXOP_08_86_L_0 */
10512   {
10513     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10514   },
10515   /* VEX_W_0FXOP_08_87_L_0 */
10516   {
10517     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
10518   },
10519   /* VEX_W_0FXOP_08_8E_L_0 */
10520   {
10521     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10522   },
10523   /* VEX_W_0FXOP_08_8F_L_0 */
10524   {
10525     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
10526   },
10527   /* VEX_W_0FXOP_08_95_L_0 */
10528   {
10529     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
10530   },
10531   /* VEX_W_0FXOP_08_96_L_0 */
10532   {
10533     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10534   },
10535   /* VEX_W_0FXOP_08_97_L_0 */
10536   {
10537     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
10538   },
10539   /* VEX_W_0FXOP_08_9E_L_0 */
10540   {
10541     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10542   },
10543   /* VEX_W_0FXOP_08_9F_L_0 */
10544   {
10545     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
10546   },
10547   /* VEX_W_0FXOP_08_A6_L_0 */
10548   {
10549     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
10550   },
10551   /* VEX_W_0FXOP_08_B6_L_0 */
10552   {
10553     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10554   },
10555   /* VEX_W_0FXOP_08_C0_L_0 */
10556   {
10557     { "vprotb",         { XM, EXx, Ib }, 0 },
10558   },
10559   /* VEX_W_0FXOP_08_C1_L_0 */
10560   {
10561     { "vprotw",         { XM, EXx, Ib }, 0 },
10562   },
10563   /* VEX_W_0FXOP_08_C2_L_0 */
10564   {
10565     { "vprotd",         { XM, EXx, Ib }, 0 },
10566   },
10567   /* VEX_W_0FXOP_08_C3_L_0 */
10568   {
10569     { "vprotq",         { XM, EXx, Ib }, 0 },
10570   },
10571   /* VEX_W_0FXOP_08_CC_L_0 */
10572   {
10573      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
10574   },
10575   /* VEX_W_0FXOP_08_CD_L_0 */
10576   {
10577      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
10578   },
10579   /* VEX_W_0FXOP_08_CE_L_0 */
10580   {
10581      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
10582   },
10583   /* VEX_W_0FXOP_08_CF_L_0 */
10584   {
10585      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
10586   },
10587   /* VEX_W_0FXOP_08_EC_L_0 */
10588   {
10589      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
10590   },
10591   /* VEX_W_0FXOP_08_ED_L_0 */
10592   {
10593      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
10594   },
10595   /* VEX_W_0FXOP_08_EE_L_0 */
10596   {
10597      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
10598   },
10599   /* VEX_W_0FXOP_08_EF_L_0 */
10600   {
10601      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
10602   },
10603   /* VEX_W_0FXOP_09_80 */
10604   {
10605     { "vfrczps",        { XM, EXx }, 0 },
10606   },
10607   /* VEX_W_0FXOP_09_81 */
10608   {
10609     { "vfrczpd",        { XM, EXx }, 0 },
10610   },
10611   /* VEX_W_0FXOP_09_82 */
10612   {
10613     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10614   },
10615   /* VEX_W_0FXOP_09_83 */
10616   {
10617     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10618   },
10619   /* VEX_W_0FXOP_09_C1_L_0 */
10620   {
10621     { "vphaddbw",       { XM, EXxmm }, 0 },
10622   },
10623   /* VEX_W_0FXOP_09_C2_L_0 */
10624   {
10625     { "vphaddbd",       { XM, EXxmm }, 0 },
10626   },
10627   /* VEX_W_0FXOP_09_C3_L_0 */
10628   {
10629     { "vphaddbq",       { XM, EXxmm }, 0 },
10630   },
10631   /* VEX_W_0FXOP_09_C6_L_0 */
10632   {
10633     { "vphaddwd",       { XM, EXxmm }, 0 },
10634   },
10635   /* VEX_W_0FXOP_09_C7_L_0 */
10636   {
10637     { "vphaddwq",       { XM, EXxmm }, 0 },
10638   },
10639   /* VEX_W_0FXOP_09_CB_L_0 */
10640   {
10641     { "vphadddq",       { XM, EXxmm }, 0 },
10642   },
10643   /* VEX_W_0FXOP_09_D1_L_0 */
10644   {
10645     { "vphaddubw",      { XM, EXxmm }, 0 },
10646   },
10647   /* VEX_W_0FXOP_09_D2_L_0 */
10648   {
10649     { "vphaddubd",      { XM, EXxmm }, 0 },
10650   },
10651   /* VEX_W_0FXOP_09_D3_L_0 */
10652   {
10653     { "vphaddubq",      { XM, EXxmm }, 0 },
10654   },
10655   /* VEX_W_0FXOP_09_D6_L_0 */
10656   {
10657     { "vphadduwd",      { XM, EXxmm }, 0 },
10658   },
10659   /* VEX_W_0FXOP_09_D7_L_0 */
10660   {
10661     { "vphadduwq",      { XM, EXxmm }, 0 },
10662   },
10663   /* VEX_W_0FXOP_09_DB_L_0 */
10664   {
10665     { "vphaddudq",      { XM, EXxmm }, 0 },
10666   },
10667   /* VEX_W_0FXOP_09_E1_L_0 */
10668   {
10669     { "vphsubbw",       { XM, EXxmm }, 0 },
10670   },
10671   /* VEX_W_0FXOP_09_E2_L_0 */
10672   {
10673     { "vphsubwd",       { XM, EXxmm }, 0 },
10674   },
10675   /* VEX_W_0FXOP_09_E3_L_0 */
10676   {
10677     { "vphsubdq",       { XM, EXxmm }, 0 },
10678   },
10679
10680 #include "i386-dis-evex-w.h"
10681 };
10682
10683 static const struct dis386 mod_table[][2] = {
10684   {
10685     /* MOD_8D */
10686     { "leaS",           { Gv, M }, 0 },
10687   },
10688   {
10689     /* MOD_C6_REG_7 */
10690     { Bad_Opcode },
10691     { RM_TABLE (RM_C6_REG_7) },
10692   },
10693   {
10694     /* MOD_C7_REG_7 */
10695     { Bad_Opcode },
10696     { RM_TABLE (RM_C7_REG_7) },
10697   },
10698   {
10699     /* MOD_FF_REG_3 */
10700     { "{l|}call^", { indirEp }, 0 },
10701   },
10702   {
10703     /* MOD_FF_REG_5 */
10704     { "{l|}jmp^", { indirEp }, 0 },
10705   },
10706   {
10707     /* MOD_0F01_REG_0 */
10708     { X86_64_TABLE (X86_64_0F01_REG_0) },
10709     { RM_TABLE (RM_0F01_REG_0) },
10710   },
10711   {
10712     /* MOD_0F01_REG_1 */
10713     { X86_64_TABLE (X86_64_0F01_REG_1) },
10714     { RM_TABLE (RM_0F01_REG_1) },
10715   },
10716   {
10717     /* MOD_0F01_REG_2 */
10718     { X86_64_TABLE (X86_64_0F01_REG_2) },
10719     { RM_TABLE (RM_0F01_REG_2) },
10720   },
10721   {
10722     /* MOD_0F01_REG_3 */
10723     { X86_64_TABLE (X86_64_0F01_REG_3) },
10724     { RM_TABLE (RM_0F01_REG_3) },
10725   },
10726   {
10727     /* MOD_0F01_REG_5 */
10728     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10729     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10730   },
10731   {
10732     /* MOD_0F01_REG_7 */
10733     { "invlpg",         { Mb }, 0 },
10734     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10735   },
10736   {
10737     /* MOD_0F12_PREFIX_0 */
10738     { "movlpX",         { XM, EXq }, 0 },
10739     { "movhlps",        { XM, EXq }, 0 },
10740   },
10741   {
10742     /* MOD_0F12_PREFIX_2 */
10743     { "movlpX", { XM, EXq }, 0 },
10744   },
10745   {
10746     /* MOD_0F13 */
10747     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10748   },
10749   {
10750     /* MOD_0F16_PREFIX_0 */
10751     { "movhpX",         { XM, EXq }, 0 },
10752     { "movlhps",        { XM, EXq }, 0 },
10753   },
10754   {
10755     /* MOD_0F16_PREFIX_2 */
10756     { "movhpX", { XM, EXq }, 0 },
10757   },
10758   {
10759     /* MOD_0F17 */
10760     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10761   },
10762   {
10763     /* MOD_0F18_REG_0 */
10764     { "prefetchnta",    { Mb }, 0 },
10765   },
10766   {
10767     /* MOD_0F18_REG_1 */
10768     { "prefetcht0",     { Mb }, 0 },
10769   },
10770   {
10771     /* MOD_0F18_REG_2 */
10772     { "prefetcht1",     { Mb }, 0 },
10773   },
10774   {
10775     /* MOD_0F18_REG_3 */
10776     { "prefetcht2",     { Mb }, 0 },
10777   },
10778   {
10779     /* MOD_0F18_REG_4 */
10780     { "nop/reserved",   { Mb }, 0 },
10781   },
10782   {
10783     /* MOD_0F18_REG_5 */
10784     { "nop/reserved",   { Mb }, 0 },
10785   },
10786   {
10787     /* MOD_0F18_REG_6 */
10788     { "nop/reserved",   { Mb }, 0 },
10789   },
10790   {
10791     /* MOD_0F18_REG_7 */
10792     { "nop/reserved",   { Mb }, 0 },
10793   },
10794   {
10795     /* MOD_0F1A_PREFIX_0 */
10796     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10797     { "nopQ",           { Ev }, 0 },
10798   },
10799   {
10800     /* MOD_0F1B_PREFIX_0 */
10801     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10802     { "nopQ",           { Ev }, 0 },
10803   },
10804   {
10805     /* MOD_0F1B_PREFIX_1 */
10806     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10807     { "nopQ",           { Ev }, 0 },
10808   },
10809   {
10810     /* MOD_0F1C_PREFIX_0 */
10811     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10812     { "nopQ",           { Ev }, 0 },
10813   },
10814   {
10815     /* MOD_0F1E_PREFIX_1 */
10816     { "nopQ",           { Ev }, 0 },
10817     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10818   },
10819   {
10820     /* MOD_0F24 */
10821     { Bad_Opcode },
10822     { "movL",           { Rd, Td }, 0 },
10823   },
10824   {
10825     /* MOD_0F26 */
10826     { Bad_Opcode },
10827     { "movL",           { Td, Rd }, 0 },
10828   },
10829   {
10830     /* MOD_0F2B_PREFIX_0 */
10831     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10832   },
10833   {
10834     /* MOD_0F2B_PREFIX_1 */
10835     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10836   },
10837   {
10838     /* MOD_0F2B_PREFIX_2 */
10839     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10840   },
10841   {
10842     /* MOD_0F2B_PREFIX_3 */
10843     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10844   },
10845   {
10846     /* MOD_0F50 */
10847     { Bad_Opcode },
10848     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10849   },
10850   {
10851     /* MOD_0F71_REG_2 */
10852     { Bad_Opcode },
10853     { "psrlw",          { MS, Ib }, 0 },
10854   },
10855   {
10856     /* MOD_0F71_REG_4 */
10857     { Bad_Opcode },
10858     { "psraw",          { MS, Ib }, 0 },
10859   },
10860   {
10861     /* MOD_0F71_REG_6 */
10862     { Bad_Opcode },
10863     { "psllw",          { MS, Ib }, 0 },
10864   },
10865   {
10866     /* MOD_0F72_REG_2 */
10867     { Bad_Opcode },
10868     { "psrld",          { MS, Ib }, 0 },
10869   },
10870   {
10871     /* MOD_0F72_REG_4 */
10872     { Bad_Opcode },
10873     { "psrad",          { MS, Ib }, 0 },
10874   },
10875   {
10876     /* MOD_0F72_REG_6 */
10877     { Bad_Opcode },
10878     { "pslld",          { MS, Ib }, 0 },
10879   },
10880   {
10881     /* MOD_0F73_REG_2 */
10882     { Bad_Opcode },
10883     { "psrlq",          { MS, Ib }, 0 },
10884   },
10885   {
10886     /* MOD_0F73_REG_3 */
10887     { Bad_Opcode },
10888     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10889   },
10890   {
10891     /* MOD_0F73_REG_6 */
10892     { Bad_Opcode },
10893     { "psllq",          { MS, Ib }, 0 },
10894   },
10895   {
10896     /* MOD_0F73_REG_7 */
10897     { Bad_Opcode },
10898     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10899   },
10900   {
10901     /* MOD_0FAE_REG_0 */
10902     { "fxsave",         { FXSAVE }, 0 },
10903     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10904   },
10905   {
10906     /* MOD_0FAE_REG_1 */
10907     { "fxrstor",        { FXSAVE }, 0 },
10908     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10909   },
10910   {
10911     /* MOD_0FAE_REG_2 */
10912     { "ldmxcsr",        { Md }, 0 },
10913     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10914   },
10915   {
10916     /* MOD_0FAE_REG_3 */
10917     { "stmxcsr",        { Md }, 0 },
10918     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10919   },
10920   {
10921     /* MOD_0FAE_REG_4 */
10922     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10923     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10924   },
10925   {
10926     /* MOD_0FAE_REG_5 */
10927     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10928     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10929   },
10930   {
10931     /* MOD_0FAE_REG_6 */
10932     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10933     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10934   },
10935   {
10936     /* MOD_0FAE_REG_7 */
10937     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10938     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10939   },
10940   {
10941     /* MOD_0FB2 */
10942     { "lssS",           { Gv, Mp }, 0 },
10943   },
10944   {
10945     /* MOD_0FB4 */
10946     { "lfsS",           { Gv, Mp }, 0 },
10947   },
10948   {
10949     /* MOD_0FB5 */
10950     { "lgsS",           { Gv, Mp }, 0 },
10951   },
10952   {
10953     /* MOD_0FC3 */
10954     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10955   },
10956   {
10957     /* MOD_0FC7_REG_3 */
10958     { "xrstors",        { FXSAVE }, 0 },
10959   },
10960   {
10961     /* MOD_0FC7_REG_4 */
10962     { "xsavec",         { FXSAVE }, 0 },
10963   },
10964   {
10965     /* MOD_0FC7_REG_5 */
10966     { "xsaves",         { FXSAVE }, 0 },
10967   },
10968   {
10969     /* MOD_0FC7_REG_6 */
10970     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10971     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10972   },
10973   {
10974     /* MOD_0FC7_REG_7 */
10975     { "vmptrst",        { Mq }, 0 },
10976     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10977   },
10978   {
10979     /* MOD_0FD7 */
10980     { Bad_Opcode },
10981     { "pmovmskb",       { Gdq, MS }, 0 },
10982   },
10983   {
10984     /* MOD_0FE7_PREFIX_2 */
10985     { "movntdq",        { Mx, XM }, 0 },
10986   },
10987   {
10988     /* MOD_0FF0_PREFIX_3 */
10989     { "lddqu",          { XM, M }, 0 },
10990   },
10991   {
10992     /* MOD_0F382A_PREFIX_2 */
10993     { "movntdqa",       { XM, Mx }, 0 },
10994   },
10995   {
10996     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
10997     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
10998     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
10999   },
11000   {
11001     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
11002     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
11003   },
11004   {
11005     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
11006     { Bad_Opcode },
11007     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
11008   },
11009   {
11010     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
11011     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
11012   },
11013   {
11014     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
11015     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
11016   },
11017   {
11018     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
11019     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
11020   },
11021   {
11022     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
11023     { Bad_Opcode },
11024     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
11025   },
11026   {
11027     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
11028     { Bad_Opcode },
11029     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
11030   },
11031   {
11032     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
11033     { Bad_Opcode },
11034     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
11035   },
11036   {
11037     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
11038     { Bad_Opcode },
11039     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
11040   },
11041   {
11042     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
11043     { Bad_Opcode },
11044     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
11045   },
11046   {
11047     /* MOD_0F38F5_PREFIX_2 */
11048     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11049   },
11050   {
11051     /* MOD_0F38F6_PREFIX_0 */
11052     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11053   },
11054   {
11055     /* MOD_0F38F8_PREFIX_1 */
11056     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
11057   },
11058   {
11059     /* MOD_0F38F8_PREFIX_2 */
11060     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
11061   },
11062   {
11063     /* MOD_0F38F8_PREFIX_3 */
11064     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
11065   },
11066   {
11067     /* MOD_0F38F9_PREFIX_0 */
11068     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
11069   },
11070   {
11071     /* MOD_62_32BIT */
11072     { "bound{S|}",      { Gv, Ma }, 0 },
11073     { EVEX_TABLE (EVEX_0F) },
11074   },
11075   {
11076     /* MOD_C4_32BIT */
11077     { "lesS",           { Gv, Mp }, 0 },
11078     { VEX_C4_TABLE (VEX_0F) },
11079   },
11080   {
11081     /* MOD_C5_32BIT */
11082     { "ldsS",           { Gv, Mp }, 0 },
11083     { VEX_C5_TABLE (VEX_0F) },
11084   },
11085   {
11086     /* MOD_VEX_0F12_PREFIX_0 */
11087     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11088     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11089   },
11090   {
11091     /* MOD_VEX_0F12_PREFIX_2 */
11092     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
11093   },
11094   {
11095     /* MOD_VEX_0F13 */
11096     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11097   },
11098   {
11099     /* MOD_VEX_0F16_PREFIX_0 */
11100     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11101     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11102   },
11103   {
11104     /* MOD_VEX_0F16_PREFIX_2 */
11105     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
11106   },
11107   {
11108     /* MOD_VEX_0F17 */
11109     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11110   },
11111   {
11112     /* MOD_VEX_0F2B */
11113     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
11114   },
11115   {
11116     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11117     { Bad_Opcode },
11118     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11119   },
11120   {
11121     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11122     { Bad_Opcode },
11123     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11124   },
11125   {
11126     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11127     { Bad_Opcode },
11128     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11129   },
11130   {
11131     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11132     { Bad_Opcode },
11133     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11134   },
11135   {
11136     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11137     { Bad_Opcode },
11138     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11139   },
11140   {
11141     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11142     { Bad_Opcode },
11143     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11144   },
11145   {
11146     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11147     { Bad_Opcode },
11148     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11149   },
11150   {
11151     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11152     { Bad_Opcode },
11153     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11154   },
11155   {
11156     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11157     { Bad_Opcode },
11158     { "knotw",          { MaskG, MaskR }, 0 },
11159   },
11160   {
11161     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11162     { Bad_Opcode },
11163     { "knotq",          { MaskG, MaskR }, 0 },
11164   },
11165   {
11166     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11167     { Bad_Opcode },
11168     { "knotb",          { MaskG, MaskR }, 0 },
11169   },
11170   {
11171     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11172     { Bad_Opcode },
11173     { "knotd",          { MaskG, MaskR }, 0 },
11174   },
11175   {
11176     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11177     { Bad_Opcode },
11178     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11179   },
11180   {
11181     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11182     { Bad_Opcode },
11183     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11184   },
11185   {
11186     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11187     { Bad_Opcode },
11188     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11189   },
11190   {
11191     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11192     { Bad_Opcode },
11193     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11194   },
11195  {
11196     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11197     { Bad_Opcode },
11198     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11199   },
11200   {
11201     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11202     { Bad_Opcode },
11203     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11204   },
11205   {
11206     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11207     { Bad_Opcode },
11208     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11209   },
11210   {
11211     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11212     { Bad_Opcode },
11213     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11214   },
11215   {
11216     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11217     { Bad_Opcode },
11218     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11219   },
11220   {
11221     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11222     { Bad_Opcode },
11223     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11224   },
11225   {
11226     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11227     { Bad_Opcode },
11228     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11229   },
11230   {
11231     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11232     { Bad_Opcode },
11233     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11234   },
11235   {
11236     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11237     { Bad_Opcode },
11238     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11239   },
11240   {
11241     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11242     { Bad_Opcode },
11243     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11244   },
11245   {
11246     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11247     { Bad_Opcode },
11248     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11249   },
11250   {
11251     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11252     { Bad_Opcode },
11253     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11254   },
11255   {
11256     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11257     { Bad_Opcode },
11258     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11259   },
11260   {
11261     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11262     { Bad_Opcode },
11263     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11264   },
11265   {
11266     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11267     { Bad_Opcode },
11268     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11269   },
11270   {
11271     /* MOD_VEX_0F50 */
11272     { Bad_Opcode },
11273     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
11274   },
11275   {
11276     /* MOD_VEX_0F71_REG_2 */
11277     { Bad_Opcode },
11278     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11279   },
11280   {
11281     /* MOD_VEX_0F71_REG_4 */
11282     { Bad_Opcode },
11283     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11284   },
11285   {
11286     /* MOD_VEX_0F71_REG_6 */
11287     { Bad_Opcode },
11288     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11289   },
11290   {
11291     /* MOD_VEX_0F72_REG_2 */
11292     { Bad_Opcode },
11293     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11294   },
11295   {
11296     /* MOD_VEX_0F72_REG_4 */
11297     { Bad_Opcode },
11298     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11299   },
11300   {
11301     /* MOD_VEX_0F72_REG_6 */
11302     { Bad_Opcode },
11303     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11304   },
11305   {
11306     /* MOD_VEX_0F73_REG_2 */
11307     { Bad_Opcode },
11308     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11309   },
11310   {
11311     /* MOD_VEX_0F73_REG_3 */
11312     { Bad_Opcode },
11313     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11314   },
11315   {
11316     /* MOD_VEX_0F73_REG_6 */
11317     { Bad_Opcode },
11318     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11319   },
11320   {
11321     /* MOD_VEX_0F73_REG_7 */
11322     { Bad_Opcode },
11323     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11324   },
11325   {
11326     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11327     { "kmovw",          { Ew, MaskG }, 0 },
11328     { Bad_Opcode },
11329   },
11330   {
11331     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11332     { "kmovq",          { Eq, MaskG }, 0 },
11333     { Bad_Opcode },
11334   },
11335   {
11336     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11337     { "kmovb",          { Eb, MaskG }, 0 },
11338     { Bad_Opcode },
11339   },
11340   {
11341     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11342     { "kmovd",          { Ed, MaskG }, 0 },
11343     { Bad_Opcode },
11344   },
11345   {
11346     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11347     { Bad_Opcode },
11348     { "kmovw",          { MaskG, Rdq }, 0 },
11349   },
11350   {
11351     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11352     { Bad_Opcode },
11353     { "kmovb",          { MaskG, Rdq }, 0 },
11354   },
11355   {
11356     /* MOD_VEX_0F92_P_3_LEN_0 */
11357     { Bad_Opcode },
11358     { "kmovK",          { MaskG, Rdq }, 0 },
11359   },
11360   {
11361     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11362     { Bad_Opcode },
11363     { "kmovw",          { Gdq, MaskR }, 0 },
11364   },
11365   {
11366     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11367     { Bad_Opcode },
11368     { "kmovb",          { Gdq, MaskR }, 0 },
11369   },
11370   {
11371     /* MOD_VEX_0F93_P_3_LEN_0 */
11372     { Bad_Opcode },
11373     { "kmovK",          { Gdq, MaskR }, 0 },
11374   },
11375   {
11376     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11377     { Bad_Opcode },
11378     { "kortestw", { MaskG, MaskR }, 0 },
11379   },
11380   {
11381     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11382     { Bad_Opcode },
11383     { "kortestq", { MaskG, MaskR }, 0 },
11384   },
11385   {
11386     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11387     { Bad_Opcode },
11388     { "kortestb", { MaskG, MaskR }, 0 },
11389   },
11390   {
11391     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11392     { Bad_Opcode },
11393     { "kortestd", { MaskG, MaskR }, 0 },
11394   },
11395   {
11396     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11397     { Bad_Opcode },
11398     { "ktestw", { MaskG, MaskR }, 0 },
11399   },
11400   {
11401     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11402     { Bad_Opcode },
11403     { "ktestq", { MaskG, MaskR }, 0 },
11404   },
11405   {
11406     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11407     { Bad_Opcode },
11408     { "ktestb", { MaskG, MaskR }, 0 },
11409   },
11410   {
11411     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
11412     { Bad_Opcode },
11413     { "ktestd", { MaskG, MaskR }, 0 },
11414   },
11415   {
11416     /* MOD_VEX_0FAE_REG_2 */
11417     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11418   },
11419   {
11420     /* MOD_VEX_0FAE_REG_3 */
11421     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11422   },
11423   {
11424     /* MOD_VEX_0FD7_PREFIX_2 */
11425     { Bad_Opcode },
11426     { "vpmovmskb",      { Gdq, XS }, 0 },
11427   },
11428   {
11429     /* MOD_VEX_0FE7_PREFIX_2 */
11430     { "vmovntdq",       { Mx, XM }, 0 },
11431   },
11432   {
11433     /* MOD_VEX_0FF0_PREFIX_3 */
11434     { "vlddqu",         { XM, M }, 0 },
11435   },
11436   {
11437     /* MOD_VEX_0F381A_PREFIX_2 */
11438     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11439   },
11440   {
11441     /* MOD_VEX_0F382A_PREFIX_2 */
11442     { "vmovntdqa",      { XM, Mx }, 0 },
11443   },
11444   {
11445     /* MOD_VEX_0F382C_PREFIX_2 */
11446     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11447   },
11448   {
11449     /* MOD_VEX_0F382D_PREFIX_2 */
11450     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11451   },
11452   {
11453     /* MOD_VEX_0F382E_PREFIX_2 */
11454     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11455   },
11456   {
11457     /* MOD_VEX_0F382F_PREFIX_2 */
11458     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11459   },
11460   {
11461     /* MOD_VEX_0F385A_PREFIX_2 */
11462     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11463   },
11464   {
11465     /* MOD_VEX_0F388C_PREFIX_2 */
11466     { "vpmaskmov%DQ",   { XM, Vex, Mx }, 0 },
11467   },
11468   {
11469     /* MOD_VEX_0F388E_PREFIX_2 */
11470     { "vpmaskmov%DQ",   { Mx, Vex, XM }, 0 },
11471   },
11472   {
11473     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
11474     { Bad_Opcode },
11475     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11476   },
11477   {
11478     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
11479     { Bad_Opcode },
11480     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11481   },
11482   {
11483     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
11484     { Bad_Opcode },
11485     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11486   },
11487   {
11488     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
11489     { Bad_Opcode },
11490     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11491   },
11492   {
11493     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
11494     { Bad_Opcode },
11495     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11496   },
11497   {
11498     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11499     { Bad_Opcode },
11500     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11501   },
11502   {
11503     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11504     { Bad_Opcode },
11505     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11506   },
11507   {
11508     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11509     { Bad_Opcode },
11510     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11511   },
11512   {
11513     /* MOD_VEX_0FXOP_09_12 */
11514     { Bad_Opcode },
11515     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
11516   },
11517
11518 #include "i386-dis-evex-mod.h"
11519 };
11520
11521 static const struct dis386 rm_table[][8] = {
11522   {
11523     /* RM_C6_REG_7 */
11524     { "xabort",         { Skip_MODRM, Ib }, 0 },
11525   },
11526   {
11527     /* RM_C7_REG_7 */
11528     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
11529   },
11530   {
11531     /* RM_0F01_REG_0 */
11532     { "enclv",          { Skip_MODRM }, 0 },
11533     { "vmcall",         { Skip_MODRM }, 0 },
11534     { "vmlaunch",       { Skip_MODRM }, 0 },
11535     { "vmresume",       { Skip_MODRM }, 0 },
11536     { "vmxoff",         { Skip_MODRM }, 0 },
11537     { "pconfig",        { Skip_MODRM }, 0 },
11538   },
11539   {
11540     /* RM_0F01_REG_1 */
11541     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11542     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11543     { "clac",           { Skip_MODRM }, 0 },
11544     { "stac",           { Skip_MODRM }, 0 },
11545     { Bad_Opcode },
11546     { Bad_Opcode },
11547     { Bad_Opcode },
11548     { "encls",          { Skip_MODRM }, 0 },
11549   },
11550   {
11551     /* RM_0F01_REG_2 */
11552     { "xgetbv",         { Skip_MODRM }, 0 },
11553     { "xsetbv",         { Skip_MODRM }, 0 },
11554     { Bad_Opcode },
11555     { Bad_Opcode },
11556     { "vmfunc",         { Skip_MODRM }, 0 },
11557     { "xend",           { Skip_MODRM }, 0 },
11558     { "xtest",          { Skip_MODRM }, 0 },
11559     { "enclu",          { Skip_MODRM }, 0 },
11560   },
11561   {
11562     /* RM_0F01_REG_3 */
11563     { "vmrun",          { Skip_MODRM }, 0 },
11564     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
11565     { "vmload",         { Skip_MODRM }, 0 },
11566     { "vmsave",         { Skip_MODRM }, 0 },
11567     { "stgi",           { Skip_MODRM }, 0 },
11568     { "clgi",           { Skip_MODRM }, 0 },
11569     { "skinit",         { Skip_MODRM }, 0 },
11570     { "invlpga",        { Skip_MODRM }, 0 },
11571   },
11572   {
11573     /* RM_0F01_REG_5_MOD_3 */
11574     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11575     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
11576     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11577     { Bad_Opcode },
11578     { Bad_Opcode },
11579     { Bad_Opcode },
11580     { "rdpkru",         { Skip_MODRM }, 0 },
11581     { "wrpkru",         { Skip_MODRM }, 0 },
11582   },
11583   {
11584     /* RM_0F01_REG_7_MOD_3 */
11585     { "swapgs",         { Skip_MODRM }, 0  },
11586     { "rdtscp",         { Skip_MODRM }, 0  },
11587     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11588     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11589     { "clzero",         { Skip_MODRM }, 0  },
11590     { "rdpru",          { Skip_MODRM }, 0  },
11591   },
11592   {
11593     /* RM_0F1E_P_1_MOD_3_REG_7 */
11594     { "nopQ",           { Ev }, 0 },
11595     { "nopQ",           { Ev }, 0 },
11596     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11597     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11598     { "nopQ",           { Ev }, 0 },
11599     { "nopQ",           { Ev }, 0 },
11600     { "nopQ",           { Ev }, 0 },
11601     { "nopQ",           { Ev }, 0 },
11602   },
11603   {
11604     /* RM_0FAE_REG_6_MOD_3 */
11605     { "mfence",         { Skip_MODRM }, 0 },
11606   },
11607   {
11608     /* RM_0FAE_REG_7_MOD_3 */
11609     { "sfence",         { Skip_MODRM }, 0 },
11610
11611   },
11612   {
11613     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
11614     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
11615   },
11616 };
11617
11618 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11619
11620 /* We use the high bit to indicate different name for the same
11621    prefix.  */
11622 #define REP_PREFIX      (0xf3 | 0x100)
11623 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11624 #define XRELEASE_PREFIX (0xf3 | 0x400)
11625 #define BND_PREFIX      (0xf2 | 0x400)
11626 #define NOTRACK_PREFIX  (0x3e | 0x100)
11627
11628 /* Remember if the current op is a jump instruction.  */
11629 static bfd_boolean op_is_jump = FALSE;
11630
11631 static int
11632 ckprefix (void)
11633 {
11634   int newrex, i, length;
11635   rex = 0;
11636   prefixes = 0;
11637   used_prefixes = 0;
11638   rex_used = 0;
11639   last_lock_prefix = -1;
11640   last_repz_prefix = -1;
11641   last_repnz_prefix = -1;
11642   last_data_prefix = -1;
11643   last_addr_prefix = -1;
11644   last_rex_prefix = -1;
11645   last_seg_prefix = -1;
11646   fwait_prefix = -1;
11647   active_seg_prefix = 0;
11648   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11649     all_prefixes[i] = 0;
11650   i = 0;
11651   length = 0;
11652   /* The maximum instruction length is 15bytes.  */
11653   while (length < MAX_CODE_LENGTH - 1)
11654     {
11655       FETCH_DATA (the_info, codep + 1);
11656       newrex = 0;
11657       switch (*codep)
11658         {
11659         /* REX prefixes family.  */
11660         case 0x40:
11661         case 0x41:
11662         case 0x42:
11663         case 0x43:
11664         case 0x44:
11665         case 0x45:
11666         case 0x46:
11667         case 0x47:
11668         case 0x48:
11669         case 0x49:
11670         case 0x4a:
11671         case 0x4b:
11672         case 0x4c:
11673         case 0x4d:
11674         case 0x4e:
11675         case 0x4f:
11676           if (address_mode == mode_64bit)
11677             newrex = *codep;
11678           else
11679             return 1;
11680           last_rex_prefix = i;
11681           break;
11682         case 0xf3:
11683           prefixes |= PREFIX_REPZ;
11684           last_repz_prefix = i;
11685           break;
11686         case 0xf2:
11687           prefixes |= PREFIX_REPNZ;
11688           last_repnz_prefix = i;
11689           break;
11690         case 0xf0:
11691           prefixes |= PREFIX_LOCK;
11692           last_lock_prefix = i;
11693           break;
11694         case 0x2e:
11695           prefixes |= PREFIX_CS;
11696           last_seg_prefix = i;
11697           active_seg_prefix = PREFIX_CS;
11698           break;
11699         case 0x36:
11700           prefixes |= PREFIX_SS;
11701           last_seg_prefix = i;
11702           active_seg_prefix = PREFIX_SS;
11703           break;
11704         case 0x3e:
11705           prefixes |= PREFIX_DS;
11706           last_seg_prefix = i;
11707           active_seg_prefix = PREFIX_DS;
11708           break;
11709         case 0x26:
11710           prefixes |= PREFIX_ES;
11711           last_seg_prefix = i;
11712           active_seg_prefix = PREFIX_ES;
11713           break;
11714         case 0x64:
11715           prefixes |= PREFIX_FS;
11716           last_seg_prefix = i;
11717           active_seg_prefix = PREFIX_FS;
11718           break;
11719         case 0x65:
11720           prefixes |= PREFIX_GS;
11721           last_seg_prefix = i;
11722           active_seg_prefix = PREFIX_GS;
11723           break;
11724         case 0x66:
11725           prefixes |= PREFIX_DATA;
11726           last_data_prefix = i;
11727           break;
11728         case 0x67:
11729           prefixes |= PREFIX_ADDR;
11730           last_addr_prefix = i;
11731           break;
11732         case FWAIT_OPCODE:
11733           /* fwait is really an instruction.  If there are prefixes
11734              before the fwait, they belong to the fwait, *not* to the
11735              following instruction.  */
11736           fwait_prefix = i;
11737           if (prefixes || rex)
11738             {
11739               prefixes |= PREFIX_FWAIT;
11740               codep++;
11741               /* This ensures that the previous REX prefixes are noticed
11742                  as unused prefixes, as in the return case below.  */
11743               rex_used = rex;
11744               return 1;
11745             }
11746           prefixes = PREFIX_FWAIT;
11747           break;
11748         default:
11749           return 1;
11750         }
11751       /* Rex is ignored when followed by another prefix.  */
11752       if (rex)
11753         {
11754           rex_used = rex;
11755           return 1;
11756         }
11757       if (*codep != FWAIT_OPCODE)
11758         all_prefixes[i++] = *codep;
11759       rex = newrex;
11760       codep++;
11761       length++;
11762     }
11763   return 0;
11764 }
11765
11766 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11767    prefix byte.  */
11768
11769 static const char *
11770 prefix_name (int pref, int sizeflag)
11771 {
11772   static const char *rexes [16] =
11773     {
11774       "rex",            /* 0x40 */
11775       "rex.B",          /* 0x41 */
11776       "rex.X",          /* 0x42 */
11777       "rex.XB",         /* 0x43 */
11778       "rex.R",          /* 0x44 */
11779       "rex.RB",         /* 0x45 */
11780       "rex.RX",         /* 0x46 */
11781       "rex.RXB",        /* 0x47 */
11782       "rex.W",          /* 0x48 */
11783       "rex.WB",         /* 0x49 */
11784       "rex.WX",         /* 0x4a */
11785       "rex.WXB",        /* 0x4b */
11786       "rex.WR",         /* 0x4c */
11787       "rex.WRB",        /* 0x4d */
11788       "rex.WRX",        /* 0x4e */
11789       "rex.WRXB",       /* 0x4f */
11790     };
11791
11792   switch (pref)
11793     {
11794     /* REX prefixes family.  */
11795     case 0x40:
11796     case 0x41:
11797     case 0x42:
11798     case 0x43:
11799     case 0x44:
11800     case 0x45:
11801     case 0x46:
11802     case 0x47:
11803     case 0x48:
11804     case 0x49:
11805     case 0x4a:
11806     case 0x4b:
11807     case 0x4c:
11808     case 0x4d:
11809     case 0x4e:
11810     case 0x4f:
11811       return rexes [pref - 0x40];
11812     case 0xf3:
11813       return "repz";
11814     case 0xf2:
11815       return "repnz";
11816     case 0xf0:
11817       return "lock";
11818     case 0x2e:
11819       return "cs";
11820     case 0x36:
11821       return "ss";
11822     case 0x3e:
11823       return "ds";
11824     case 0x26:
11825       return "es";
11826     case 0x64:
11827       return "fs";
11828     case 0x65:
11829       return "gs";
11830     case 0x66:
11831       return (sizeflag & DFLAG) ? "data16" : "data32";
11832     case 0x67:
11833       if (address_mode == mode_64bit)
11834         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11835       else
11836         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11837     case FWAIT_OPCODE:
11838       return "fwait";
11839     case REP_PREFIX:
11840       return "rep";
11841     case XACQUIRE_PREFIX:
11842       return "xacquire";
11843     case XRELEASE_PREFIX:
11844       return "xrelease";
11845     case BND_PREFIX:
11846       return "bnd";
11847     case NOTRACK_PREFIX:
11848       return "notrack";
11849     default:
11850       return NULL;
11851     }
11852 }
11853
11854 static char op_out[MAX_OPERANDS][100];
11855 static int op_ad, op_index[MAX_OPERANDS];
11856 static int two_source_ops;
11857 static bfd_vma op_address[MAX_OPERANDS];
11858 static bfd_vma op_riprel[MAX_OPERANDS];
11859 static bfd_vma start_pc;
11860
11861 /*
11862  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11863  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11864  *   section of the "Virtual 8086 Mode" chapter.)
11865  * 'pc' should be the address of this instruction, it will
11866  *   be used to print the target address if this is a relative jump or call
11867  * The function returns the length of this instruction in bytes.
11868  */
11869
11870 static char intel_syntax;
11871 static char intel_mnemonic = !SYSV386_COMPAT;
11872 static char open_char;
11873 static char close_char;
11874 static char separator_char;
11875 static char scale_char;
11876
11877 enum x86_64_isa
11878 {
11879   amd64 = 1,
11880   intel64
11881 };
11882
11883 static enum x86_64_isa isa64;
11884
11885 /* Here for backwards compatibility.  When gdb stops using
11886    print_insn_i386_att and print_insn_i386_intel these functions can
11887    disappear, and print_insn_i386 be merged into print_insn.  */
11888 int
11889 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11890 {
11891   intel_syntax = 0;
11892
11893   return print_insn (pc, info);
11894 }
11895
11896 int
11897 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11898 {
11899   intel_syntax = 1;
11900
11901   return print_insn (pc, info);
11902 }
11903
11904 int
11905 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11906 {
11907   intel_syntax = -1;
11908
11909   return print_insn (pc, info);
11910 }
11911
11912 void
11913 print_i386_disassembler_options (FILE *stream)
11914 {
11915   fprintf (stream, _("\n\
11916 The following i386/x86-64 specific disassembler options are supported for use\n\
11917 with the -M switch (multiple options should be separated by commas):\n"));
11918
11919   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11920   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11921   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11922   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11923   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11924   fprintf (stream, _("  att-mnemonic\n"
11925                      "              Display instruction in AT&T mnemonic\n"));
11926   fprintf (stream, _("  intel-mnemonic\n"
11927                      "              Display instruction in Intel mnemonic\n"));
11928   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11929   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11930   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11931   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11932   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11933   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11934   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11935   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11936 }
11937
11938 /* Bad opcode.  */
11939 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11940
11941 /* Get a pointer to struct dis386 with a valid name.  */
11942
11943 static const struct dis386 *
11944 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11945 {
11946   int vindex, vex_table_index;
11947
11948   if (dp->name != NULL)
11949     return dp;
11950
11951   switch (dp->op[0].bytemode)
11952     {
11953     case USE_REG_TABLE:
11954       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11955       break;
11956
11957     case USE_MOD_TABLE:
11958       vindex = modrm.mod == 0x3 ? 1 : 0;
11959       dp = &mod_table[dp->op[1].bytemode][vindex];
11960       break;
11961
11962     case USE_RM_TABLE:
11963       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11964       break;
11965
11966     case USE_PREFIX_TABLE:
11967       if (need_vex)
11968         {
11969           /* The prefix in VEX is implicit.  */
11970           switch (vex.prefix)
11971             {
11972             case 0:
11973               vindex = 0;
11974               break;
11975             case REPE_PREFIX_OPCODE:
11976               vindex = 1;
11977               break;
11978             case DATA_PREFIX_OPCODE:
11979               vindex = 2;
11980               break;
11981             case REPNE_PREFIX_OPCODE:
11982               vindex = 3;
11983               break;
11984             default:
11985               abort ();
11986               break;
11987             }
11988         }
11989       else
11990         {
11991           int last_prefix = -1;
11992           int prefix = 0;
11993           vindex = 0;
11994           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11995              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11996              last one wins.  */
11997           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11998             {
11999               if (last_repz_prefix > last_repnz_prefix)
12000                 {
12001                   vindex = 1;
12002                   prefix = PREFIX_REPZ;
12003                   last_prefix = last_repz_prefix;
12004                 }
12005               else
12006                 {
12007                   vindex = 3;
12008                   prefix = PREFIX_REPNZ;
12009                   last_prefix = last_repnz_prefix;
12010                 }
12011
12012               /* Check if prefix should be ignored.  */
12013               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12014                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12015                    & prefix) != 0)
12016                 vindex = 0;
12017             }
12018
12019           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12020             {
12021               vindex = 2;
12022               prefix = PREFIX_DATA;
12023               last_prefix = last_data_prefix;
12024             }
12025
12026           if (vindex != 0)
12027             {
12028               used_prefixes |= prefix;
12029               all_prefixes[last_prefix] = 0;
12030             }
12031         }
12032       dp = &prefix_table[dp->op[1].bytemode][vindex];
12033       break;
12034
12035     case USE_X86_64_TABLE:
12036       vindex = address_mode == mode_64bit ? 1 : 0;
12037       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12038       break;
12039
12040     case USE_3BYTE_TABLE:
12041       FETCH_DATA (info, codep + 2);
12042       vindex = *codep++;
12043       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12044       end_codep = codep;
12045       modrm.mod = (*codep >> 6) & 3;
12046       modrm.reg = (*codep >> 3) & 7;
12047       modrm.rm = *codep & 7;
12048       break;
12049
12050     case USE_VEX_LEN_TABLE:
12051       if (!need_vex)
12052         abort ();
12053
12054       switch (vex.length)
12055         {
12056         case 128:
12057           vindex = 0;
12058           break;
12059         case 256:
12060           vindex = 1;
12061           break;
12062         default:
12063           abort ();
12064           break;
12065         }
12066
12067       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12068       break;
12069
12070     case USE_EVEX_LEN_TABLE:
12071       if (!vex.evex)
12072         abort ();
12073
12074       switch (vex.length)
12075         {
12076         case 128:
12077           vindex = 0;
12078           break;
12079         case 256:
12080           vindex = 1;
12081           break;
12082         case 512:
12083           vindex = 2;
12084           break;
12085         default:
12086           abort ();
12087           break;
12088         }
12089
12090       dp = &evex_len_table[dp->op[1].bytemode][vindex];
12091       break;
12092
12093     case USE_XOP_8F_TABLE:
12094       FETCH_DATA (info, codep + 3);
12095       rex = ~(*codep >> 5) & 0x7;
12096
12097       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12098       switch ((*codep & 0x1f))
12099         {
12100         default:
12101           dp = &bad_opcode;
12102           return dp;
12103         case 0x8:
12104           vex_table_index = XOP_08;
12105           break;
12106         case 0x9:
12107           vex_table_index = XOP_09;
12108           break;
12109         case 0xa:
12110           vex_table_index = XOP_0A;
12111           break;
12112         }
12113       codep++;
12114       vex.w = *codep & 0x80;
12115       if (vex.w && address_mode == mode_64bit)
12116         rex |= REX_W;
12117
12118       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12119       if (address_mode != mode_64bit)
12120         {
12121           /* In 16/32-bit mode REX_B is silently ignored.  */
12122           rex &= ~REX_B;
12123         }
12124
12125       vex.length = (*codep & 0x4) ? 256 : 128;
12126       switch ((*codep & 0x3))
12127         {
12128         case 0:
12129           break;
12130         case 1:
12131           vex.prefix = DATA_PREFIX_OPCODE;
12132           break;
12133         case 2:
12134           vex.prefix = REPE_PREFIX_OPCODE;
12135           break;
12136         case 3:
12137           vex.prefix = REPNE_PREFIX_OPCODE;
12138           break;
12139         }
12140       need_vex = 1;
12141       codep++;
12142       vindex = *codep++;
12143       dp = &xop_table[vex_table_index][vindex];
12144
12145       end_codep = codep;
12146       FETCH_DATA (info, codep + 1);
12147       modrm.mod = (*codep >> 6) & 3;
12148       modrm.reg = (*codep >> 3) & 7;
12149       modrm.rm = *codep & 7;
12150
12151       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
12152          having to decode the bits for every otherwise valid encoding.  */
12153       if (vex.prefix)
12154         return &bad_opcode;
12155       break;
12156
12157     case USE_VEX_C4_TABLE:
12158       /* VEX prefix.  */
12159       FETCH_DATA (info, codep + 3);
12160       rex = ~(*codep >> 5) & 0x7;
12161       switch ((*codep & 0x1f))
12162         {
12163         default:
12164           dp = &bad_opcode;
12165           return dp;
12166         case 0x1:
12167           vex_table_index = VEX_0F;
12168           break;
12169         case 0x2:
12170           vex_table_index = VEX_0F38;
12171           break;
12172         case 0x3:
12173           vex_table_index = VEX_0F3A;
12174           break;
12175         }
12176       codep++;
12177       vex.w = *codep & 0x80;
12178       if (address_mode == mode_64bit)
12179         {
12180           if (vex.w)
12181             rex |= REX_W;
12182         }
12183       else
12184         {
12185           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12186              is ignored, other REX bits are 0 and the highest bit in
12187              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12188           rex = 0;
12189         }
12190       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12191       vex.length = (*codep & 0x4) ? 256 : 128;
12192       switch ((*codep & 0x3))
12193         {
12194         case 0:
12195           break;
12196         case 1:
12197           vex.prefix = DATA_PREFIX_OPCODE;
12198           break;
12199         case 2:
12200           vex.prefix = REPE_PREFIX_OPCODE;
12201           break;
12202         case 3:
12203           vex.prefix = REPNE_PREFIX_OPCODE;
12204           break;
12205         }
12206       need_vex = 1;
12207       codep++;
12208       vindex = *codep++;
12209       dp = &vex_table[vex_table_index][vindex];
12210       end_codep = codep;
12211       /* There is no MODRM byte for VEX0F 77.  */
12212       if (vex_table_index != VEX_0F || vindex != 0x77)
12213         {
12214           FETCH_DATA (info, codep + 1);
12215           modrm.mod = (*codep >> 6) & 3;
12216           modrm.reg = (*codep >> 3) & 7;
12217           modrm.rm = *codep & 7;
12218         }
12219       break;
12220
12221     case USE_VEX_C5_TABLE:
12222       /* VEX prefix.  */
12223       FETCH_DATA (info, codep + 2);
12224       rex = (*codep & 0x80) ? 0 : REX_R;
12225
12226       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12227          VEX.vvvv is 1.  */
12228       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12229       vex.length = (*codep & 0x4) ? 256 : 128;
12230       switch ((*codep & 0x3))
12231         {
12232         case 0:
12233           break;
12234         case 1:
12235           vex.prefix = DATA_PREFIX_OPCODE;
12236           break;
12237         case 2:
12238           vex.prefix = REPE_PREFIX_OPCODE;
12239           break;
12240         case 3:
12241           vex.prefix = REPNE_PREFIX_OPCODE;
12242           break;
12243         }
12244       need_vex = 1;
12245       codep++;
12246       vindex = *codep++;
12247       dp = &vex_table[dp->op[1].bytemode][vindex];
12248       end_codep = codep;
12249       /* There is no MODRM byte for VEX 77.  */
12250       if (vindex != 0x77)
12251         {
12252           FETCH_DATA (info, codep + 1);
12253           modrm.mod = (*codep >> 6) & 3;
12254           modrm.reg = (*codep >> 3) & 7;
12255           modrm.rm = *codep & 7;
12256         }
12257       break;
12258
12259     case USE_VEX_W_TABLE:
12260       if (!need_vex)
12261         abort ();
12262
12263       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12264       break;
12265
12266     case USE_EVEX_TABLE:
12267       two_source_ops = 0;
12268       /* EVEX prefix.  */
12269       vex.evex = 1;
12270       FETCH_DATA (info, codep + 4);
12271       /* The first byte after 0x62.  */
12272       rex = ~(*codep >> 5) & 0x7;
12273       vex.r = *codep & 0x10;
12274       switch ((*codep & 0xf))
12275         {
12276         default:
12277           return &bad_opcode;
12278         case 0x1:
12279           vex_table_index = EVEX_0F;
12280           break;
12281         case 0x2:
12282           vex_table_index = EVEX_0F38;
12283           break;
12284         case 0x3:
12285           vex_table_index = EVEX_0F3A;
12286           break;
12287         }
12288
12289       /* The second byte after 0x62.  */
12290       codep++;
12291       vex.w = *codep & 0x80;
12292       if (vex.w && address_mode == mode_64bit)
12293         rex |= REX_W;
12294
12295       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12296
12297       /* The U bit.  */
12298       if (!(*codep & 0x4))
12299         return &bad_opcode;
12300
12301       switch ((*codep & 0x3))
12302         {
12303         case 0:
12304           break;
12305         case 1:
12306           vex.prefix = DATA_PREFIX_OPCODE;
12307           break;
12308         case 2:
12309           vex.prefix = REPE_PREFIX_OPCODE;
12310           break;
12311         case 3:
12312           vex.prefix = REPNE_PREFIX_OPCODE;
12313           break;
12314         }
12315
12316       /* The third byte after 0x62.  */
12317       codep++;
12318
12319       /* Remember the static rounding bits.  */
12320       vex.ll = (*codep >> 5) & 3;
12321       vex.b = (*codep & 0x10) != 0;
12322
12323       vex.v = *codep & 0x8;
12324       vex.mask_register_specifier = *codep & 0x7;
12325       vex.zeroing = *codep & 0x80;
12326
12327       if (address_mode != mode_64bit)
12328         {
12329           /* In 16/32-bit mode silently ignore following bits.  */
12330           rex &= ~REX_B;
12331           vex.r = 1;
12332           vex.v = 1;
12333         }
12334
12335       need_vex = 1;
12336       codep++;
12337       vindex = *codep++;
12338       dp = &evex_table[vex_table_index][vindex];
12339       end_codep = codep;
12340       FETCH_DATA (info, codep + 1);
12341       modrm.mod = (*codep >> 6) & 3;
12342       modrm.reg = (*codep >> 3) & 7;
12343       modrm.rm = *codep & 7;
12344
12345       /* Set vector length.  */
12346       if (modrm.mod == 3 && vex.b)
12347         vex.length = 512;
12348       else
12349         {
12350           switch (vex.ll)
12351             {
12352             case 0x0:
12353               vex.length = 128;
12354               break;
12355             case 0x1:
12356               vex.length = 256;
12357               break;
12358             case 0x2:
12359               vex.length = 512;
12360               break;
12361             default:
12362               return &bad_opcode;
12363             }
12364         }
12365       break;
12366
12367     case 0:
12368       dp = &bad_opcode;
12369       break;
12370
12371     default:
12372       abort ();
12373     }
12374
12375   if (dp->name != NULL)
12376     return dp;
12377   else
12378     return get_valid_dis386 (dp, info);
12379 }
12380
12381 static void
12382 get_sib (disassemble_info *info, int sizeflag)
12383 {
12384   /* If modrm.mod == 3, operand must be register.  */
12385   if (need_modrm
12386       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12387       && modrm.mod != 3
12388       && modrm.rm == 4)
12389     {
12390       FETCH_DATA (info, codep + 2);
12391       sib.index = (codep [1] >> 3) & 7;
12392       sib.scale = (codep [1] >> 6) & 3;
12393       sib.base = codep [1] & 7;
12394     }
12395 }
12396
12397 static int
12398 print_insn (bfd_vma pc, disassemble_info *info)
12399 {
12400   const struct dis386 *dp;
12401   int i;
12402   char *op_txt[MAX_OPERANDS];
12403   int needcomma;
12404   int sizeflag, orig_sizeflag;
12405   const char *p;
12406   struct dis_private priv;
12407   int prefix_length;
12408
12409   priv.orig_sizeflag = AFLAG | DFLAG;
12410   if ((info->mach & bfd_mach_i386_i386) != 0)
12411     address_mode = mode_32bit;
12412   else if (info->mach == bfd_mach_i386_i8086)
12413     {
12414       address_mode = mode_16bit;
12415       priv.orig_sizeflag = 0;
12416     }
12417   else
12418     address_mode = mode_64bit;
12419
12420   if (intel_syntax == (char) -1)
12421     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12422
12423   for (p = info->disassembler_options; p != NULL; )
12424     {
12425       if (CONST_STRNEQ (p, "amd64"))
12426         isa64 = amd64;
12427       else if (CONST_STRNEQ (p, "intel64"))
12428         isa64 = intel64;
12429       else if (CONST_STRNEQ (p, "x86-64"))
12430         {
12431           address_mode = mode_64bit;
12432           priv.orig_sizeflag |= AFLAG | DFLAG;
12433         }
12434       else if (CONST_STRNEQ (p, "i386"))
12435         {
12436           address_mode = mode_32bit;
12437           priv.orig_sizeflag |= AFLAG | DFLAG;
12438         }
12439       else if (CONST_STRNEQ (p, "i8086"))
12440         {
12441           address_mode = mode_16bit;
12442           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
12443         }
12444       else if (CONST_STRNEQ (p, "intel"))
12445         {
12446           intel_syntax = 1;
12447           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12448             intel_mnemonic = 1;
12449         }
12450       else if (CONST_STRNEQ (p, "att"))
12451         {
12452           intel_syntax = 0;
12453           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12454             intel_mnemonic = 0;
12455         }
12456       else if (CONST_STRNEQ (p, "addr"))
12457         {
12458           if (address_mode == mode_64bit)
12459             {
12460               if (p[4] == '3' && p[5] == '2')
12461                 priv.orig_sizeflag &= ~AFLAG;
12462               else if (p[4] == '6' && p[5] == '4')
12463                 priv.orig_sizeflag |= AFLAG;
12464             }
12465           else
12466             {
12467               if (p[4] == '1' && p[5] == '6')
12468                 priv.orig_sizeflag &= ~AFLAG;
12469               else if (p[4] == '3' && p[5] == '2')
12470                 priv.orig_sizeflag |= AFLAG;
12471             }
12472         }
12473       else if (CONST_STRNEQ (p, "data"))
12474         {
12475           if (p[4] == '1' && p[5] == '6')
12476             priv.orig_sizeflag &= ~DFLAG;
12477           else if (p[4] == '3' && p[5] == '2')
12478             priv.orig_sizeflag |= DFLAG;
12479         }
12480       else if (CONST_STRNEQ (p, "suffix"))
12481         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12482
12483       p = strchr (p, ',');
12484       if (p != NULL)
12485         p++;
12486     }
12487
12488   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
12489     {
12490       (*info->fprintf_func) (info->stream,
12491                              _("64-bit address is disabled"));
12492       return -1;
12493     }
12494
12495   if (intel_syntax)
12496     {
12497       names64 = intel_names64;
12498       names32 = intel_names32;
12499       names16 = intel_names16;
12500       names8 = intel_names8;
12501       names8rex = intel_names8rex;
12502       names_seg = intel_names_seg;
12503       names_mm = intel_names_mm;
12504       names_bnd = intel_names_bnd;
12505       names_xmm = intel_names_xmm;
12506       names_ymm = intel_names_ymm;
12507       names_zmm = intel_names_zmm;
12508       names_tmm = intel_names_tmm;
12509       index64 = intel_index64;
12510       index32 = intel_index32;
12511       names_mask = intel_names_mask;
12512       index16 = intel_index16;
12513       open_char = '[';
12514       close_char = ']';
12515       separator_char = '+';
12516       scale_char = '*';
12517     }
12518   else
12519     {
12520       names64 = att_names64;
12521       names32 = att_names32;
12522       names16 = att_names16;
12523       names8 = att_names8;
12524       names8rex = att_names8rex;
12525       names_seg = att_names_seg;
12526       names_mm = att_names_mm;
12527       names_bnd = att_names_bnd;
12528       names_xmm = att_names_xmm;
12529       names_ymm = att_names_ymm;
12530       names_zmm = att_names_zmm;
12531       names_tmm = att_names_tmm;
12532       index64 = att_index64;
12533       index32 = att_index32;
12534       names_mask = att_names_mask;
12535       index16 = att_index16;
12536       open_char = '(';
12537       close_char =  ')';
12538       separator_char = ',';
12539       scale_char = ',';
12540     }
12541
12542   /* The output looks better if we put 7 bytes on a line, since that
12543      puts most long word instructions on a single line.  Use 8 bytes
12544      for Intel L1OM.  */
12545   if ((info->mach & bfd_mach_l1om) != 0)
12546     info->bytes_per_line = 8;
12547   else
12548     info->bytes_per_line = 7;
12549
12550   info->private_data = &priv;
12551   priv.max_fetched = priv.the_buffer;
12552   priv.insn_start = pc;
12553
12554   obuf[0] = 0;
12555   for (i = 0; i < MAX_OPERANDS; ++i)
12556     {
12557       op_out[i][0] = 0;
12558       op_index[i] = -1;
12559     }
12560
12561   the_info = info;
12562   start_pc = pc;
12563   start_codep = priv.the_buffer;
12564   codep = priv.the_buffer;
12565
12566   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12567     {
12568       const char *name;
12569
12570       /* Getting here means we tried for data but didn't get it.  That
12571          means we have an incomplete instruction of some sort.  Just
12572          print the first byte as a prefix or a .byte pseudo-op.  */
12573       if (codep > priv.the_buffer)
12574         {
12575           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12576           if (name != NULL)
12577             (*info->fprintf_func) (info->stream, "%s", name);
12578           else
12579             {
12580               /* Just print the first byte as a .byte instruction.  */
12581               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12582                                      (unsigned int) priv.the_buffer[0]);
12583             }
12584
12585           return 1;
12586         }
12587
12588       return -1;
12589     }
12590
12591   obufp = obuf;
12592   sizeflag = priv.orig_sizeflag;
12593
12594   if (!ckprefix () || rex_used)
12595     {
12596       /* Too many prefixes or unused REX prefixes.  */
12597       for (i = 0;
12598            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12599            i++)
12600         (*info->fprintf_func) (info->stream, "%s%s",
12601                                i == 0 ? "" : " ",
12602                                prefix_name (all_prefixes[i], sizeflag));
12603       return i;
12604     }
12605
12606   insn_codep = codep;
12607
12608   FETCH_DATA (info, codep + 1);
12609   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12610
12611   if (((prefixes & PREFIX_FWAIT)
12612        && ((*codep < 0xd8) || (*codep > 0xdf))))
12613     {
12614       /* Handle prefixes before fwait.  */
12615       for (i = 0; i < fwait_prefix && all_prefixes[i];
12616            i++)
12617         (*info->fprintf_func) (info->stream, "%s ",
12618                                prefix_name (all_prefixes[i], sizeflag));
12619       (*info->fprintf_func) (info->stream, "fwait");
12620       return i + 1;
12621     }
12622
12623   if (*codep == 0x0f)
12624     {
12625       unsigned char threebyte;
12626
12627       codep++;
12628       FETCH_DATA (info, codep + 1);
12629       threebyte = *codep;
12630       dp = &dis386_twobyte[threebyte];
12631       need_modrm = twobyte_has_modrm[*codep];
12632       codep++;
12633     }
12634   else
12635     {
12636       dp = &dis386[*codep];
12637       need_modrm = onebyte_has_modrm[*codep];
12638       codep++;
12639     }
12640
12641   /* Save sizeflag for printing the extra prefixes later before updating
12642      it for mnemonic and operand processing.  The prefix names depend
12643      only on the address mode.  */
12644   orig_sizeflag = sizeflag;
12645   if (prefixes & PREFIX_ADDR)
12646     sizeflag ^= AFLAG;
12647   if ((prefixes & PREFIX_DATA))
12648     sizeflag ^= DFLAG;
12649
12650   end_codep = codep;
12651   if (need_modrm)
12652     {
12653       FETCH_DATA (info, codep + 1);
12654       modrm.mod = (*codep >> 6) & 3;
12655       modrm.reg = (*codep >> 3) & 7;
12656       modrm.rm = *codep & 7;
12657     }
12658
12659   need_vex = 0;
12660   memset (&vex, 0, sizeof (vex));
12661
12662   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12663     {
12664       get_sib (info, sizeflag);
12665       dofloat (sizeflag);
12666     }
12667   else
12668     {
12669       dp = get_valid_dis386 (dp, info);
12670       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12671         {
12672           get_sib (info, sizeflag);
12673           for (i = 0; i < MAX_OPERANDS; ++i)
12674             {
12675               obufp = op_out[i];
12676               op_ad = MAX_OPERANDS - 1 - i;
12677               if (dp->op[i].rtn)
12678                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12679               /* For EVEX instruction after the last operand masking
12680                  should be printed.  */
12681               if (i == 0 && vex.evex)
12682                 {
12683                   /* Don't print {%k0}.  */
12684                   if (vex.mask_register_specifier)
12685                     {
12686                       oappend ("{");
12687                       oappend (names_mask[vex.mask_register_specifier]);
12688                       oappend ("}");
12689                     }
12690                   if (vex.zeroing)
12691                     oappend ("{z}");
12692                 }
12693             }
12694         }
12695     }
12696
12697   /* Clear instruction information.  */
12698   if (the_info)
12699     {
12700       the_info->insn_info_valid = 0;
12701       the_info->branch_delay_insns = 0;
12702       the_info->data_size = 0;
12703       the_info->insn_type = dis_noninsn;
12704       the_info->target = 0;
12705       the_info->target2 = 0;
12706     }
12707
12708   /* Reset jump operation indicator.  */
12709   op_is_jump = FALSE;
12710
12711   {
12712     int jump_detection = 0;
12713
12714     /* Extract flags.  */
12715     for (i = 0; i < MAX_OPERANDS; ++i)
12716       {
12717         if ((dp->op[i].rtn == OP_J)
12718             || (dp->op[i].rtn == OP_indirE))
12719           jump_detection |= 1;
12720         else if ((dp->op[i].rtn == BND_Fixup)
12721                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12722           jump_detection |= 2;
12723         else if ((dp->op[i].bytemode == cond_jump_mode)
12724                  || (dp->op[i].bytemode == loop_jcxz_mode))
12725           jump_detection |= 4;
12726       }
12727
12728     /* Determine if this is a jump or branch.  */
12729     if ((jump_detection & 0x3) == 0x3)
12730       {
12731         op_is_jump = TRUE;
12732         if (jump_detection & 0x4)
12733           the_info->insn_type = dis_condbranch;
12734         else
12735           the_info->insn_type =
12736             (dp->name && !strncmp(dp->name, "call", 4))
12737             ? dis_jsr : dis_branch;
12738       }
12739   }
12740
12741   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12742      are all 0s in inverted form.  */
12743   if (need_vex && vex.register_specifier != 0)
12744     {
12745       (*info->fprintf_func) (info->stream, "(bad)");
12746       return end_codep - priv.the_buffer;
12747     }
12748
12749   /* Check if the REX prefix is used.  */
12750   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12751     all_prefixes[last_rex_prefix] = 0;
12752
12753   /* Check if the SEG prefix is used.  */
12754   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12755                    | PREFIX_FS | PREFIX_GS)) != 0
12756       && (used_prefixes & active_seg_prefix) != 0)
12757     all_prefixes[last_seg_prefix] = 0;
12758
12759   /* Check if the ADDR prefix is used.  */
12760   if ((prefixes & PREFIX_ADDR) != 0
12761       && (used_prefixes & PREFIX_ADDR) != 0)
12762     all_prefixes[last_addr_prefix] = 0;
12763
12764   /* Check if the DATA prefix is used.  */
12765   if ((prefixes & PREFIX_DATA) != 0
12766       && (used_prefixes & PREFIX_DATA) != 0
12767       && !need_vex)
12768     all_prefixes[last_data_prefix] = 0;
12769
12770   /* Print the extra prefixes.  */
12771   prefix_length = 0;
12772   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12773     if (all_prefixes[i])
12774       {
12775         const char *name;
12776         name = prefix_name (all_prefixes[i], orig_sizeflag);
12777         if (name == NULL)
12778           abort ();
12779         prefix_length += strlen (name) + 1;
12780         (*info->fprintf_func) (info->stream, "%s ", name);
12781       }
12782
12783   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12784      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12785      used by putop and MMX/SSE operand and may be overriden by the
12786      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12787      separately.  */
12788   if (dp->prefix_requirement == PREFIX_OPCODE
12789       && (((need_vex
12790             ? vex.prefix == REPE_PREFIX_OPCODE
12791               || vex.prefix == REPNE_PREFIX_OPCODE
12792             : (prefixes
12793                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12794            && (used_prefixes
12795                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12796           || (((need_vex
12797                 ? vex.prefix == DATA_PREFIX_OPCODE
12798                 : ((prefixes
12799                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12800                    == PREFIX_DATA))
12801                && (used_prefixes & PREFIX_DATA) == 0))
12802           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12803     {
12804       (*info->fprintf_func) (info->stream, "(bad)");
12805       return end_codep - priv.the_buffer;
12806     }
12807
12808   /* Check maximum code length.  */
12809   if ((codep - start_codep) > MAX_CODE_LENGTH)
12810     {
12811       (*info->fprintf_func) (info->stream, "(bad)");
12812       return MAX_CODE_LENGTH;
12813     }
12814
12815   obufp = mnemonicendp;
12816   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12817     oappend (" ");
12818   oappend (" ");
12819   (*info->fprintf_func) (info->stream, "%s", obuf);
12820
12821   /* The enter and bound instructions are printed with operands in the same
12822      order as the intel book; everything else is printed in reverse order.  */
12823   if (intel_syntax || two_source_ops)
12824     {
12825       bfd_vma riprel;
12826
12827       for (i = 0; i < MAX_OPERANDS; ++i)
12828         op_txt[i] = op_out[i];
12829
12830       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12831           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12832         {
12833           op_txt[2] = op_out[3];
12834           op_txt[3] = op_out[2];
12835         }
12836
12837       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12838         {
12839           op_ad = op_index[i];
12840           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12841           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12842           riprel = op_riprel[i];
12843           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12844           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12845         }
12846     }
12847   else
12848     {
12849       for (i = 0; i < MAX_OPERANDS; ++i)
12850         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12851     }
12852
12853   needcomma = 0;
12854   for (i = 0; i < MAX_OPERANDS; ++i)
12855     if (*op_txt[i])
12856       {
12857         if (needcomma)
12858           (*info->fprintf_func) (info->stream, ",");
12859         if (op_index[i] != -1 && !op_riprel[i])
12860           {
12861             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12862
12863             if (the_info && op_is_jump)
12864               {
12865                 the_info->insn_info_valid = 1;
12866                 the_info->branch_delay_insns = 0;
12867                 the_info->data_size = 0;
12868                 the_info->target = target;
12869                 the_info->target2 = 0;
12870               }
12871             (*info->print_address_func) (target, info);
12872           }
12873         else
12874           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12875         needcomma = 1;
12876       }
12877
12878   for (i = 0; i < MAX_OPERANDS; i++)
12879     if (op_index[i] != -1 && op_riprel[i])
12880       {
12881         (*info->fprintf_func) (info->stream, "        # ");
12882         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12883                                                 + op_address[op_index[i]]), info);
12884         break;
12885       }
12886   return codep - priv.the_buffer;
12887 }
12888
12889 static const char *float_mem[] = {
12890   /* d8 */
12891   "fadd{s|}",
12892   "fmul{s|}",
12893   "fcom{s|}",
12894   "fcomp{s|}",
12895   "fsub{s|}",
12896   "fsubr{s|}",
12897   "fdiv{s|}",
12898   "fdivr{s|}",
12899   /* d9 */
12900   "fld{s|}",
12901   "(bad)",
12902   "fst{s|}",
12903   "fstp{s|}",
12904   "fldenv{C|C}",
12905   "fldcw",
12906   "fNstenv{C|C}",
12907   "fNstcw",
12908   /* da */
12909   "fiadd{l|}",
12910   "fimul{l|}",
12911   "ficom{l|}",
12912   "ficomp{l|}",
12913   "fisub{l|}",
12914   "fisubr{l|}",
12915   "fidiv{l|}",
12916   "fidivr{l|}",
12917   /* db */
12918   "fild{l|}",
12919   "fisttp{l|}",
12920   "fist{l|}",
12921   "fistp{l|}",
12922   "(bad)",
12923   "fld{t|}",
12924   "(bad)",
12925   "fstp{t|}",
12926   /* dc */
12927   "fadd{l|}",
12928   "fmul{l|}",
12929   "fcom{l|}",
12930   "fcomp{l|}",
12931   "fsub{l|}",
12932   "fsubr{l|}",
12933   "fdiv{l|}",
12934   "fdivr{l|}",
12935   /* dd */
12936   "fld{l|}",
12937   "fisttp{ll|}",
12938   "fst{l||}",
12939   "fstp{l|}",
12940   "frstor{C|C}",
12941   "(bad)",
12942   "fNsave{C|C}",
12943   "fNstsw",
12944   /* de */
12945   "fiadd{s|}",
12946   "fimul{s|}",
12947   "ficom{s|}",
12948   "ficomp{s|}",
12949   "fisub{s|}",
12950   "fisubr{s|}",
12951   "fidiv{s|}",
12952   "fidivr{s|}",
12953   /* df */
12954   "fild{s|}",
12955   "fisttp{s|}",
12956   "fist{s|}",
12957   "fistp{s|}",
12958   "fbld",
12959   "fild{ll|}",
12960   "fbstp",
12961   "fistp{ll|}",
12962 };
12963
12964 static const unsigned char float_mem_mode[] = {
12965   /* d8 */
12966   d_mode,
12967   d_mode,
12968   d_mode,
12969   d_mode,
12970   d_mode,
12971   d_mode,
12972   d_mode,
12973   d_mode,
12974   /* d9 */
12975   d_mode,
12976   0,
12977   d_mode,
12978   d_mode,
12979   0,
12980   w_mode,
12981   0,
12982   w_mode,
12983   /* da */
12984   d_mode,
12985   d_mode,
12986   d_mode,
12987   d_mode,
12988   d_mode,
12989   d_mode,
12990   d_mode,
12991   d_mode,
12992   /* db */
12993   d_mode,
12994   d_mode,
12995   d_mode,
12996   d_mode,
12997   0,
12998   t_mode,
12999   0,
13000   t_mode,
13001   /* dc */
13002   q_mode,
13003   q_mode,
13004   q_mode,
13005   q_mode,
13006   q_mode,
13007   q_mode,
13008   q_mode,
13009   q_mode,
13010   /* dd */
13011   q_mode,
13012   q_mode,
13013   q_mode,
13014   q_mode,
13015   0,
13016   0,
13017   0,
13018   w_mode,
13019   /* de */
13020   w_mode,
13021   w_mode,
13022   w_mode,
13023   w_mode,
13024   w_mode,
13025   w_mode,
13026   w_mode,
13027   w_mode,
13028   /* df */
13029   w_mode,
13030   w_mode,
13031   w_mode,
13032   w_mode,
13033   t_mode,
13034   q_mode,
13035   t_mode,
13036   q_mode
13037 };
13038
13039 #define ST { OP_ST, 0 }
13040 #define STi { OP_STi, 0 }
13041
13042 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13043 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13044 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13045 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13046 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13047 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13048 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13049 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13050 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13051
13052 static const struct dis386 float_reg[][8] = {
13053   /* d8 */
13054   {
13055     { "fadd",   { ST, STi }, 0 },
13056     { "fmul",   { ST, STi }, 0 },
13057     { "fcom",   { STi }, 0 },
13058     { "fcomp",  { STi }, 0 },
13059     { "fsub",   { ST, STi }, 0 },
13060     { "fsubr",  { ST, STi }, 0 },
13061     { "fdiv",   { ST, STi }, 0 },
13062     { "fdivr",  { ST, STi }, 0 },
13063   },
13064   /* d9 */
13065   {
13066     { "fld",    { STi }, 0 },
13067     { "fxch",   { STi }, 0 },
13068     { FGRPd9_2 },
13069     { Bad_Opcode },
13070     { FGRPd9_4 },
13071     { FGRPd9_5 },
13072     { FGRPd9_6 },
13073     { FGRPd9_7 },
13074   },
13075   /* da */
13076   {
13077     { "fcmovb", { ST, STi }, 0 },
13078     { "fcmove", { ST, STi }, 0 },
13079     { "fcmovbe",{ ST, STi }, 0 },
13080     { "fcmovu", { ST, STi }, 0 },
13081     { Bad_Opcode },
13082     { FGRPda_5 },
13083     { Bad_Opcode },
13084     { Bad_Opcode },
13085   },
13086   /* db */
13087   {
13088     { "fcmovnb",{ ST, STi }, 0 },
13089     { "fcmovne",{ ST, STi }, 0 },
13090     { "fcmovnbe",{ ST, STi }, 0 },
13091     { "fcmovnu",{ ST, STi }, 0 },
13092     { FGRPdb_4 },
13093     { "fucomi", { ST, STi }, 0 },
13094     { "fcomi",  { ST, STi }, 0 },
13095     { Bad_Opcode },
13096   },
13097   /* dc */
13098   {
13099     { "fadd",   { STi, ST }, 0 },
13100     { "fmul",   { STi, ST }, 0 },
13101     { Bad_Opcode },
13102     { Bad_Opcode },
13103     { "fsub{!M|r}",     { STi, ST }, 0 },
13104     { "fsub{M|}",       { STi, ST }, 0 },
13105     { "fdiv{!M|r}",     { STi, ST }, 0 },
13106     { "fdiv{M|}",       { STi, ST }, 0 },
13107   },
13108   /* dd */
13109   {
13110     { "ffree",  { STi }, 0 },
13111     { Bad_Opcode },
13112     { "fst",    { STi }, 0 },
13113     { "fstp",   { STi }, 0 },
13114     { "fucom",  { STi }, 0 },
13115     { "fucomp", { STi }, 0 },
13116     { Bad_Opcode },
13117     { Bad_Opcode },
13118   },
13119   /* de */
13120   {
13121     { "faddp",  { STi, ST }, 0 },
13122     { "fmulp",  { STi, ST }, 0 },
13123     { Bad_Opcode },
13124     { FGRPde_3 },
13125     { "fsub{!M|r}p",    { STi, ST }, 0 },
13126     { "fsub{M|}p",      { STi, ST }, 0 },
13127     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13128     { "fdiv{M|}p",      { STi, ST }, 0 },
13129   },
13130   /* df */
13131   {
13132     { "ffreep", { STi }, 0 },
13133     { Bad_Opcode },
13134     { Bad_Opcode },
13135     { Bad_Opcode },
13136     { FGRPdf_4 },
13137     { "fucomip", { ST, STi }, 0 },
13138     { "fcomip", { ST, STi }, 0 },
13139     { Bad_Opcode },
13140   },
13141 };
13142
13143 static char *fgrps[][8] = {
13144   /* Bad opcode 0 */
13145   {
13146     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13147   },
13148
13149   /* d9_2  1 */
13150   {
13151     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13152   },
13153
13154   /* d9_4  2 */
13155   {
13156     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13157   },
13158
13159   /* d9_5  3 */
13160   {
13161     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13162   },
13163
13164   /* d9_6  4 */
13165   {
13166     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13167   },
13168
13169   /* d9_7  5 */
13170   {
13171     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13172   },
13173
13174   /* da_5  6 */
13175   {
13176     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13177   },
13178
13179   /* db_4  7 */
13180   {
13181     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13182     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13183   },
13184
13185   /* de_3  8 */
13186   {
13187     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13188   },
13189
13190   /* df_4  9 */
13191   {
13192     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13193   },
13194 };
13195
13196 static void
13197 swap_operand (void)
13198 {
13199   mnemonicendp[0] = '.';
13200   mnemonicendp[1] = 's';
13201   mnemonicendp += 2;
13202 }
13203
13204 static void
13205 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13206                int sizeflag ATTRIBUTE_UNUSED)
13207 {
13208   /* Skip mod/rm byte.  */
13209   MODRM_CHECK;
13210   codep++;
13211 }
13212
13213 static void
13214 dofloat (int sizeflag)
13215 {
13216   const struct dis386 *dp;
13217   unsigned char floatop;
13218
13219   floatop = codep[-1];
13220
13221   if (modrm.mod != 3)
13222     {
13223       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13224
13225       putop (float_mem[fp_indx], sizeflag);
13226       obufp = op_out[0];
13227       op_ad = 2;
13228       OP_E (float_mem_mode[fp_indx], sizeflag);
13229       return;
13230     }
13231   /* Skip mod/rm byte.  */
13232   MODRM_CHECK;
13233   codep++;
13234
13235   dp = &float_reg[floatop - 0xd8][modrm.reg];
13236   if (dp->name == NULL)
13237     {
13238       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13239
13240       /* Instruction fnstsw is only one with strange arg.  */
13241       if (floatop == 0xdf && codep[-1] == 0xe0)
13242         strcpy (op_out[0], names16[0]);
13243     }
13244   else
13245     {
13246       putop (dp->name, sizeflag);
13247
13248       obufp = op_out[0];
13249       op_ad = 2;
13250       if (dp->op[0].rtn)
13251         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13252
13253       obufp = op_out[1];
13254       op_ad = 1;
13255       if (dp->op[1].rtn)
13256         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13257     }
13258 }
13259
13260 /* Like oappend (below), but S is a string starting with '%'.
13261    In Intel syntax, the '%' is elided.  */
13262 static void
13263 oappend_maybe_intel (const char *s)
13264 {
13265   oappend (s + intel_syntax);
13266 }
13267
13268 static void
13269 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13270 {
13271   oappend_maybe_intel ("%st");
13272 }
13273
13274 static void
13275 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13276 {
13277   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13278   oappend_maybe_intel (scratchbuf);
13279 }
13280
13281 /* Capital letters in template are macros.  */
13282 static int
13283 putop (const char *in_template, int sizeflag)
13284 {
13285   const char *p;
13286   int alt = 0;
13287   int cond = 1;
13288   unsigned int l = 0, len = 0;
13289   char last[4];
13290
13291   for (p = in_template; *p; p++)
13292     {
13293       if (len > l)
13294         {
13295           if (l >= sizeof (last) || !ISUPPER (*p))
13296             abort ();
13297           last[l++] = *p;
13298           continue;
13299         }
13300       switch (*p)
13301         {
13302         default:
13303           *obufp++ = *p;
13304           break;
13305         case '%':
13306           len++;
13307           break;
13308         case '!':
13309           cond = 0;
13310           break;
13311         case '{':
13312           if (intel_syntax)
13313             {
13314               while (*++p != '|')
13315                 if (*p == '}' || *p == '\0')
13316                   abort ();
13317               alt = 1;
13318             }
13319           break;
13320         case '|':
13321           while (*++p != '}')
13322             {
13323               if (*p == '\0')
13324                 abort ();
13325             }
13326           break;
13327         case '}':
13328           alt = 0;
13329           break;
13330         case 'A':
13331           if (intel_syntax)
13332             break;
13333           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13334             *obufp++ = 'b';
13335           break;
13336         case 'B':
13337           if (l == 0)
13338             {
13339             case_B:
13340               if (intel_syntax)
13341                 break;
13342               if (sizeflag & SUFFIX_ALWAYS)
13343                 *obufp++ = 'b';
13344             }
13345           else if (l == 1 && last[0] == 'L')
13346             {
13347               if (address_mode == mode_64bit
13348                   && !(prefixes & PREFIX_ADDR))
13349                 {
13350                   *obufp++ = 'a';
13351                   *obufp++ = 'b';
13352                   *obufp++ = 's';
13353                 }
13354
13355               goto case_B;
13356             }
13357           else
13358             abort ();
13359           break;
13360         case 'C':
13361           if (intel_syntax && !alt)
13362             break;
13363           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13364             {
13365               if (sizeflag & DFLAG)
13366                 *obufp++ = intel_syntax ? 'd' : 'l';
13367               else
13368                 *obufp++ = intel_syntax ? 'w' : 's';
13369               used_prefixes |= (prefixes & PREFIX_DATA);
13370             }
13371           break;
13372         case 'D':
13373           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13374             break;
13375           USED_REX (REX_W);
13376           if (modrm.mod == 3)
13377             {
13378               if (rex & REX_W)
13379                 *obufp++ = 'q';
13380               else
13381                 {
13382                   if (sizeflag & DFLAG)
13383                     *obufp++ = intel_syntax ? 'd' : 'l';
13384                   else
13385                     *obufp++ = 'w';
13386                   used_prefixes |= (prefixes & PREFIX_DATA);
13387                 }
13388             }
13389           else
13390             *obufp++ = 'w';
13391           break;
13392         case 'E':               /* For jcxz/jecxz */
13393           if (address_mode == mode_64bit)
13394             {
13395               if (sizeflag & AFLAG)
13396                 *obufp++ = 'r';
13397               else
13398                 *obufp++ = 'e';
13399             }
13400           else
13401             if (sizeflag & AFLAG)
13402               *obufp++ = 'e';
13403           used_prefixes |= (prefixes & PREFIX_ADDR);
13404           break;
13405         case 'F':
13406           if (intel_syntax)
13407             break;
13408           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13409             {
13410               if (sizeflag & AFLAG)
13411                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13412               else
13413                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13414               used_prefixes |= (prefixes & PREFIX_ADDR);
13415             }
13416           break;
13417         case 'G':
13418           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13419             break;
13420           if ((rex & REX_W) || (sizeflag & DFLAG))
13421             *obufp++ = 'l';
13422           else
13423             *obufp++ = 'w';
13424           if (!(rex & REX_W))
13425             used_prefixes |= (prefixes & PREFIX_DATA);
13426           break;
13427         case 'H':
13428           if (intel_syntax)
13429             break;
13430           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13431               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13432             {
13433               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13434               *obufp++ = ',';
13435               *obufp++ = 'p';
13436               if (prefixes & PREFIX_DS)
13437                 *obufp++ = 't';
13438               else
13439                 *obufp++ = 'n';
13440             }
13441           break;
13442         case 'K':
13443           USED_REX (REX_W);
13444           if (rex & REX_W)
13445             *obufp++ = 'q';
13446           else
13447             *obufp++ = 'd';
13448           break;
13449         case 'Z':
13450           if (l != 0)
13451             {
13452               if (l != 1 || last[0] != 'X')
13453                 abort ();
13454               if (!need_vex || !vex.evex)
13455                 abort ();
13456               if (intel_syntax
13457                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13458                 break;
13459               switch (vex.length)
13460                 {
13461                 case 128:
13462                   *obufp++ = 'x';
13463                   break;
13464                 case 256:
13465                   *obufp++ = 'y';
13466                   break;
13467                 case 512:
13468                   *obufp++ = 'z';
13469                   break;
13470                 default:
13471                   abort ();
13472                 }
13473               break;
13474             }
13475           if (intel_syntax)
13476             break;
13477           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13478             {
13479               *obufp++ = 'q';
13480               break;
13481             }
13482           /* Fall through.  */
13483           goto case_L;
13484         case 'L':
13485           if (l != 0)
13486             abort ();
13487         case_L:
13488           if (intel_syntax)
13489             break;
13490           if (sizeflag & SUFFIX_ALWAYS)
13491             *obufp++ = 'l';
13492           break;
13493         case 'M':
13494           if (intel_mnemonic != cond)
13495             *obufp++ = 'r';
13496           break;
13497         case 'N':
13498           if ((prefixes & PREFIX_FWAIT) == 0)
13499             *obufp++ = 'n';
13500           else
13501             used_prefixes |= PREFIX_FWAIT;
13502           break;
13503         case 'O':
13504           USED_REX (REX_W);
13505           if (rex & REX_W)
13506             *obufp++ = 'o';
13507           else if (intel_syntax && (sizeflag & DFLAG))
13508             *obufp++ = 'q';
13509           else
13510             *obufp++ = 'd';
13511           if (!(rex & REX_W))
13512             used_prefixes |= (prefixes & PREFIX_DATA);
13513           break;
13514         case '&':
13515           if (!intel_syntax
13516               && address_mode == mode_64bit
13517               && isa64 == intel64)
13518             {
13519               *obufp++ = 'q';
13520               break;
13521             }
13522           /* Fall through.  */
13523         case 'T':
13524           if (!intel_syntax
13525               && address_mode == mode_64bit
13526               && ((sizeflag & DFLAG) || (rex & REX_W)))
13527             {
13528               *obufp++ = 'q';
13529               break;
13530             }
13531           /* Fall through.  */
13532           goto case_P;
13533         case 'P':
13534           if (l == 0)
13535             {
13536             case_P:
13537               if (intel_syntax)
13538                 {
13539                   if ((rex & REX_W) == 0
13540                       && (prefixes & PREFIX_DATA))
13541                     {
13542                       if ((sizeflag & DFLAG) == 0)
13543                         *obufp++ = 'w';
13544                       used_prefixes |= (prefixes & PREFIX_DATA);
13545                     }
13546                   break;
13547                 }
13548               if ((prefixes & PREFIX_DATA)
13549                   || (rex & REX_W)
13550                   || (sizeflag & SUFFIX_ALWAYS))
13551                 {
13552                   USED_REX (REX_W);
13553                   if (rex & REX_W)
13554                     *obufp++ = 'q';
13555                   else
13556                     {
13557                       if (sizeflag & DFLAG)
13558                         *obufp++ = 'l';
13559                       else
13560                         *obufp++ = 'w';
13561                       used_prefixes |= (prefixes & PREFIX_DATA);
13562                     }
13563                 }
13564             }
13565           else if (l == 1 && last[0] == 'L')
13566             {
13567               if ((prefixes & PREFIX_DATA)
13568                   || (rex & REX_W)
13569                   || (sizeflag & SUFFIX_ALWAYS))
13570                 {
13571                   USED_REX (REX_W);
13572                   if (rex & REX_W)
13573                     *obufp++ = 'q';
13574                   else
13575                     {
13576                       if (sizeflag & DFLAG)
13577                         *obufp++ = intel_syntax ? 'd' : 'l';
13578                       else
13579                         *obufp++ = 'w';
13580                       used_prefixes |= (prefixes & PREFIX_DATA);
13581                     }
13582                 }
13583             }
13584           else
13585             abort ();
13586           break;
13587         case 'U':
13588           if (intel_syntax)
13589             break;
13590           if (address_mode == mode_64bit
13591               && ((sizeflag & DFLAG) || (rex & REX_W)))
13592             {
13593               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13594                 *obufp++ = 'q';
13595               break;
13596             }
13597           /* Fall through.  */
13598           goto case_Q;
13599         case 'Q':
13600           if (l == 0)
13601             {
13602             case_Q:
13603               if (intel_syntax && !alt)
13604                 break;
13605               USED_REX (REX_W);
13606               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13607                 {
13608                   if (rex & REX_W)
13609                     *obufp++ = 'q';
13610                   else
13611                     {
13612                       if (sizeflag & DFLAG)
13613                         *obufp++ = intel_syntax ? 'd' : 'l';
13614                       else
13615                         *obufp++ = 'w';
13616                       used_prefixes |= (prefixes & PREFIX_DATA);
13617                     }
13618                 }
13619             }
13620           else if (l == 1 && last[0] == 'D')
13621             *obufp++ = vex.w ? 'q' : 'd';
13622           else if (l == 1 && last[0] == 'L')
13623             {
13624               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
13625                        : address_mode != mode_64bit)
13626                 break;
13627               if ((rex & REX_W))
13628                 {
13629                   USED_REX (REX_W);
13630                   *obufp++ = 'q';
13631                 }
13632               else if((address_mode == mode_64bit && need_modrm && cond)
13633                       || (sizeflag & SUFFIX_ALWAYS))
13634                 *obufp++ = intel_syntax? 'd' : 'l';
13635             }
13636           else
13637             abort ();
13638           break;
13639         case 'R':
13640           USED_REX (REX_W);
13641           if (rex & REX_W)
13642             *obufp++ = 'q';
13643           else if (sizeflag & DFLAG)
13644             {
13645               if (intel_syntax)
13646                   *obufp++ = 'd';
13647               else
13648                   *obufp++ = 'l';
13649             }
13650           else
13651             *obufp++ = 'w';
13652           if (intel_syntax && !p[1]
13653               && ((rex & REX_W) || (sizeflag & DFLAG)))
13654             *obufp++ = 'e';
13655           if (!(rex & REX_W))
13656             used_prefixes |= (prefixes & PREFIX_DATA);
13657           break;
13658         case 'V':
13659           if (l == 0)
13660             {
13661               if (intel_syntax)
13662                 break;
13663               if (address_mode == mode_64bit
13664                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13665                 {
13666                   if (sizeflag & SUFFIX_ALWAYS)
13667                     *obufp++ = 'q';
13668                   break;
13669                 }
13670             }
13671           else if (l == 1 && last[0] == 'L')
13672             {
13673               if (rex & REX_W)
13674                 {
13675                   *obufp++ = 'a';
13676                   *obufp++ = 'b';
13677                   *obufp++ = 's';
13678                 }
13679             }
13680           else
13681             abort ();
13682           /* Fall through.  */
13683           goto case_S;
13684         case 'S':
13685           if (l == 0)
13686             {
13687             case_S:
13688               if (intel_syntax)
13689                 break;
13690               if (sizeflag & SUFFIX_ALWAYS)
13691                 {
13692                   if (rex & REX_W)
13693                     *obufp++ = 'q';
13694                   else
13695                     {
13696                       if (sizeflag & DFLAG)
13697                         *obufp++ = 'l';
13698                       else
13699                         *obufp++ = 'w';
13700                       used_prefixes |= (prefixes & PREFIX_DATA);
13701                     }
13702                 }
13703             }
13704           else if (l == 1 && last[0] == 'L')
13705             {
13706               if (address_mode == mode_64bit
13707                   && !(prefixes & PREFIX_ADDR))
13708                 {
13709                   *obufp++ = 'a';
13710                   *obufp++ = 'b';
13711                   *obufp++ = 's';
13712                 }
13713
13714               goto case_S;
13715             }
13716           else
13717             abort ();
13718           break;
13719         case 'X':
13720           if (l != 0)
13721             abort ();
13722           if (need_vex
13723               ? vex.prefix == DATA_PREFIX_OPCODE
13724               : prefixes & PREFIX_DATA)
13725             {
13726               *obufp++ = 'd';
13727               used_prefixes |= PREFIX_DATA;
13728             }
13729           else
13730             *obufp++ = 's';
13731           break;
13732         case 'Y':
13733           if (l == 1 && last[0] == 'X')
13734             {
13735               if (!need_vex)
13736                 abort ();
13737               if (intel_syntax
13738                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13739                 break;
13740               switch (vex.length)
13741                 {
13742                 case 128:
13743                   *obufp++ = 'x';
13744                   break;
13745                 case 256:
13746                   *obufp++ = 'y';
13747                   break;
13748                 case 512:
13749                   if (!vex.evex)
13750                 default:
13751                     abort ();
13752                 }
13753             }
13754           else
13755             abort ();
13756           break;
13757         case 'W':
13758           if (l == 0)
13759             {
13760               /* operand size flag for cwtl, cbtw */
13761               USED_REX (REX_W);
13762               if (rex & REX_W)
13763                 {
13764                   if (intel_syntax)
13765                     *obufp++ = 'd';
13766                   else
13767                     *obufp++ = 'l';
13768                 }
13769               else if (sizeflag & DFLAG)
13770                 *obufp++ = 'w';
13771               else
13772                 *obufp++ = 'b';
13773               if (!(rex & REX_W))
13774                 used_prefixes |= (prefixes & PREFIX_DATA);
13775             }
13776           else if (l == 1)
13777             {
13778               if (!need_vex)
13779                 abort ();
13780               if (last[0] == 'X')
13781                 *obufp++ = vex.w ? 'd': 's';
13782               else if (last[0] == 'B')
13783                 *obufp++ = vex.w ? 'w': 'b';
13784               else
13785                 abort ();
13786             }
13787           else
13788             abort ();
13789           break;
13790         case '^':
13791           if (intel_syntax)
13792             break;
13793           if (isa64 == intel64 && (rex & REX_W))
13794             {
13795               USED_REX (REX_W);
13796               *obufp++ = 'q';
13797               break;
13798             }
13799           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13800             {
13801               if (sizeflag & DFLAG)
13802                 *obufp++ = 'l';
13803               else
13804                 *obufp++ = 'w';
13805               used_prefixes |= (prefixes & PREFIX_DATA);
13806             }
13807           break;
13808         case '@':
13809           if (intel_syntax)
13810             break;
13811           if (address_mode == mode_64bit
13812               && (isa64 == intel64
13813                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13814               *obufp++ = 'q';
13815           else if ((prefixes & PREFIX_DATA))
13816             {
13817               if (!(sizeflag & DFLAG))
13818                 *obufp++ = 'w';
13819               used_prefixes |= (prefixes & PREFIX_DATA);
13820             }
13821           break;
13822         }
13823
13824       if (len == l)
13825         len = l = 0;
13826     }
13827   *obufp = 0;
13828   mnemonicendp = obufp;
13829   return 0;
13830 }
13831
13832 static void
13833 oappend (const char *s)
13834 {
13835   obufp = stpcpy (obufp, s);
13836 }
13837
13838 static void
13839 append_seg (void)
13840 {
13841   /* Only print the active segment register.  */
13842   if (!active_seg_prefix)
13843     return;
13844
13845   used_prefixes |= active_seg_prefix;
13846   switch (active_seg_prefix)
13847     {
13848     case PREFIX_CS:
13849       oappend_maybe_intel ("%cs:");
13850       break;
13851     case PREFIX_DS:
13852       oappend_maybe_intel ("%ds:");
13853       break;
13854     case PREFIX_SS:
13855       oappend_maybe_intel ("%ss:");
13856       break;
13857     case PREFIX_ES:
13858       oappend_maybe_intel ("%es:");
13859       break;
13860     case PREFIX_FS:
13861       oappend_maybe_intel ("%fs:");
13862       break;
13863     case PREFIX_GS:
13864       oappend_maybe_intel ("%gs:");
13865       break;
13866     default:
13867       break;
13868     }
13869 }
13870
13871 static void
13872 OP_indirE (int bytemode, int sizeflag)
13873 {
13874   if (!intel_syntax)
13875     oappend ("*");
13876   OP_E (bytemode, sizeflag);
13877 }
13878
13879 static void
13880 print_operand_value (char *buf, int hex, bfd_vma disp)
13881 {
13882   if (address_mode == mode_64bit)
13883     {
13884       if (hex)
13885         {
13886           char tmp[30];
13887           int i;
13888           buf[0] = '0';
13889           buf[1] = 'x';
13890           sprintf_vma (tmp, disp);
13891           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13892           strcpy (buf + 2, tmp + i);
13893         }
13894       else
13895         {
13896           bfd_signed_vma v = disp;
13897           char tmp[30];
13898           int i;
13899           if (v < 0)
13900             {
13901               *(buf++) = '-';
13902               v = -disp;
13903               /* Check for possible overflow on 0x8000000000000000.  */
13904               if (v < 0)
13905                 {
13906                   strcpy (buf, "9223372036854775808");
13907                   return;
13908                 }
13909             }
13910           if (!v)
13911             {
13912               strcpy (buf, "0");
13913               return;
13914             }
13915
13916           i = 0;
13917           tmp[29] = 0;
13918           while (v)
13919             {
13920               tmp[28 - i] = (v % 10) + '0';
13921               v /= 10;
13922               i++;
13923             }
13924           strcpy (buf, tmp + 29 - i);
13925         }
13926     }
13927   else
13928     {
13929       if (hex)
13930         sprintf (buf, "0x%x", (unsigned int) disp);
13931       else
13932         sprintf (buf, "%d", (int) disp);
13933     }
13934 }
13935
13936 /* Put DISP in BUF as signed hex number.  */
13937
13938 static void
13939 print_displacement (char *buf, bfd_vma disp)
13940 {
13941   bfd_signed_vma val = disp;
13942   char tmp[30];
13943   int i, j = 0;
13944
13945   if (val < 0)
13946     {
13947       buf[j++] = '-';
13948       val = -disp;
13949
13950       /* Check for possible overflow.  */
13951       if (val < 0)
13952         {
13953           switch (address_mode)
13954             {
13955             case mode_64bit:
13956               strcpy (buf + j, "0x8000000000000000");
13957               break;
13958             case mode_32bit:
13959               strcpy (buf + j, "0x80000000");
13960               break;
13961             case mode_16bit:
13962               strcpy (buf + j, "0x8000");
13963               break;
13964             }
13965           return;
13966         }
13967     }
13968
13969   buf[j++] = '0';
13970   buf[j++] = 'x';
13971
13972   sprintf_vma (tmp, (bfd_vma) val);
13973   for (i = 0; tmp[i] == '0'; i++)
13974     continue;
13975   if (tmp[i] == '\0')
13976     i--;
13977   strcpy (buf + j, tmp + i);
13978 }
13979
13980 static void
13981 intel_operand_size (int bytemode, int sizeflag)
13982 {
13983   if (vex.evex
13984       && vex.b
13985       && (bytemode == x_mode
13986           || bytemode == evex_half_bcst_xmmq_mode))
13987     {
13988       if (vex.w)
13989         oappend ("QWORD PTR ");
13990       else
13991         oappend ("DWORD PTR ");
13992       return;
13993     }
13994   switch (bytemode)
13995     {
13996     case b_mode:
13997     case b_swap_mode:
13998     case dqb_mode:
13999     case db_mode:
14000       oappend ("BYTE PTR ");
14001       break;
14002     case w_mode:
14003     case dw_mode:
14004     case dqw_mode:
14005       oappend ("WORD PTR ");
14006       break;
14007     case indir_v_mode:
14008       if (address_mode == mode_64bit && isa64 == intel64)
14009         {
14010           oappend ("QWORD PTR ");
14011           break;
14012         }
14013       /* Fall through.  */
14014     case stack_v_mode:
14015       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14016         {
14017           oappend ("QWORD PTR ");
14018           break;
14019         }
14020       /* Fall through.  */
14021     case v_mode:
14022     case v_swap_mode:
14023     case dq_mode:
14024       USED_REX (REX_W);
14025       if (rex & REX_W)
14026         oappend ("QWORD PTR ");
14027       else
14028         {
14029           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14030             oappend ("DWORD PTR ");
14031           else
14032             oappend ("WORD PTR ");
14033           used_prefixes |= (prefixes & PREFIX_DATA);
14034         }
14035       break;
14036     case z_mode:
14037       if ((rex & REX_W) || (sizeflag & DFLAG))
14038         *obufp++ = 'D';
14039       oappend ("WORD PTR ");
14040       if (!(rex & REX_W))
14041         used_prefixes |= (prefixes & PREFIX_DATA);
14042       break;
14043     case a_mode:
14044       if (sizeflag & DFLAG)
14045         oappend ("QWORD PTR ");
14046       else
14047         oappend ("DWORD PTR ");
14048       used_prefixes |= (prefixes & PREFIX_DATA);
14049       break;
14050     case movsxd_mode:
14051       if (!(sizeflag & DFLAG) && isa64 == intel64)
14052         oappend ("WORD PTR ");
14053       else
14054         oappend ("DWORD PTR ");
14055       used_prefixes |= (prefixes & PREFIX_DATA);
14056       break;
14057     case d_mode:
14058     case d_swap_mode:
14059     case dqd_mode:
14060       oappend ("DWORD PTR ");
14061       break;
14062     case q_mode:
14063     case q_swap_mode:
14064       oappend ("QWORD PTR ");
14065       break;
14066     case m_mode:
14067       if (address_mode == mode_64bit)
14068         oappend ("QWORD PTR ");
14069       else
14070         oappend ("DWORD PTR ");
14071       break;
14072     case f_mode:
14073       if (sizeflag & DFLAG)
14074         oappend ("FWORD PTR ");
14075       else
14076         oappend ("DWORD PTR ");
14077       used_prefixes |= (prefixes & PREFIX_DATA);
14078       break;
14079     case t_mode:
14080       oappend ("TBYTE PTR ");
14081       break;
14082     case x_mode:
14083     case x_swap_mode:
14084     case evex_x_gscat_mode:
14085     case evex_x_nobcst_mode:
14086     case bw_unit_mode:
14087       if (need_vex)
14088         {
14089           switch (vex.length)
14090             {
14091             case 128:
14092               oappend ("XMMWORD PTR ");
14093               break;
14094             case 256:
14095               oappend ("YMMWORD PTR ");
14096               break;
14097             case 512:
14098               oappend ("ZMMWORD PTR ");
14099               break;
14100             default:
14101               abort ();
14102             }
14103         }
14104       else
14105         oappend ("XMMWORD PTR ");
14106       break;
14107     case xmm_mode:
14108       oappend ("XMMWORD PTR ");
14109       break;
14110     case ymm_mode:
14111       oappend ("YMMWORD PTR ");
14112       break;
14113     case xmmq_mode:
14114     case evex_half_bcst_xmmq_mode:
14115       if (!need_vex)
14116         abort ();
14117
14118       switch (vex.length)
14119         {
14120         case 128:
14121           oappend ("QWORD PTR ");
14122           break;
14123         case 256:
14124           oappend ("XMMWORD PTR ");
14125           break;
14126         case 512:
14127           oappend ("YMMWORD PTR ");
14128           break;
14129         default:
14130           abort ();
14131         }
14132       break;
14133     case xmm_mb_mode:
14134       if (!need_vex)
14135         abort ();
14136
14137       switch (vex.length)
14138         {
14139         case 128:
14140         case 256:
14141         case 512:
14142           oappend ("BYTE PTR ");
14143           break;
14144         default:
14145           abort ();
14146         }
14147       break;
14148     case xmm_mw_mode:
14149       if (!need_vex)
14150         abort ();
14151
14152       switch (vex.length)
14153         {
14154         case 128:
14155         case 256:
14156         case 512:
14157           oappend ("WORD PTR ");
14158           break;
14159         default:
14160           abort ();
14161         }
14162       break;
14163     case xmm_md_mode:
14164       if (!need_vex)
14165         abort ();
14166
14167       switch (vex.length)
14168         {
14169         case 128:
14170         case 256:
14171         case 512:
14172           oappend ("DWORD PTR ");
14173           break;
14174         default:
14175           abort ();
14176         }
14177       break;
14178     case xmm_mq_mode:
14179       if (!need_vex)
14180         abort ();
14181
14182       switch (vex.length)
14183         {
14184         case 128:
14185         case 256:
14186         case 512:
14187           oappend ("QWORD PTR ");
14188           break;
14189         default:
14190           abort ();
14191         }
14192       break;
14193     case xmmdw_mode:
14194       if (!need_vex)
14195         abort ();
14196
14197       switch (vex.length)
14198         {
14199         case 128:
14200           oappend ("WORD PTR ");
14201           break;
14202         case 256:
14203           oappend ("DWORD PTR ");
14204           break;
14205         case 512:
14206           oappend ("QWORD PTR ");
14207           break;
14208         default:
14209           abort ();
14210         }
14211       break;
14212     case xmmqd_mode:
14213       if (!need_vex)
14214         abort ();
14215
14216       switch (vex.length)
14217         {
14218         case 128:
14219           oappend ("DWORD PTR ");
14220           break;
14221         case 256:
14222           oappend ("QWORD PTR ");
14223           break;
14224         case 512:
14225           oappend ("XMMWORD PTR ");
14226           break;
14227         default:
14228           abort ();
14229         }
14230       break;
14231     case ymmq_mode:
14232       if (!need_vex)
14233         abort ();
14234
14235       switch (vex.length)
14236         {
14237         case 128:
14238           oappend ("QWORD PTR ");
14239           break;
14240         case 256:
14241           oappend ("YMMWORD PTR ");
14242           break;
14243         case 512:
14244           oappend ("ZMMWORD PTR ");
14245           break;
14246         default:
14247           abort ();
14248         }
14249       break;
14250     case ymmxmm_mode:
14251       if (!need_vex)
14252         abort ();
14253
14254       switch (vex.length)
14255         {
14256         case 128:
14257         case 256:
14258           oappend ("XMMWORD PTR ");
14259           break;
14260         default:
14261           abort ();
14262         }
14263       break;
14264     case o_mode:
14265       oappend ("OWORD PTR ");
14266       break;
14267     case vex_scalar_w_dq_mode:
14268       if (!need_vex)
14269         abort ();
14270
14271       if (vex.w)
14272         oappend ("QWORD PTR ");
14273       else
14274         oappend ("DWORD PTR ");
14275       break;
14276     case vex_vsib_d_w_dq_mode:
14277     case vex_vsib_q_w_dq_mode:
14278       if (!need_vex)
14279         abort ();
14280
14281       if (!vex.evex)
14282         {
14283           if (vex.w)
14284             oappend ("QWORD PTR ");
14285           else
14286             oappend ("DWORD PTR ");
14287         }
14288       else
14289         {
14290           switch (vex.length)
14291             {
14292             case 128:
14293               oappend ("XMMWORD PTR ");
14294               break;
14295             case 256:
14296               oappend ("YMMWORD PTR ");
14297               break;
14298             case 512:
14299               oappend ("ZMMWORD PTR ");
14300               break;
14301             default:
14302               abort ();
14303             }
14304         }
14305       break;
14306     case vex_vsib_q_w_d_mode:
14307     case vex_vsib_d_w_d_mode:
14308       if (!need_vex || !vex.evex)
14309         abort ();
14310
14311       switch (vex.length)
14312         {
14313         case 128:
14314           oappend ("QWORD PTR ");
14315           break;
14316         case 256:
14317           oappend ("XMMWORD PTR ");
14318           break;
14319         case 512:
14320           oappend ("YMMWORD PTR ");
14321           break;
14322         default:
14323           abort ();
14324         }
14325
14326       break;
14327     case mask_bd_mode:
14328       if (!need_vex || vex.length != 128)
14329         abort ();
14330       if (vex.w)
14331         oappend ("DWORD PTR ");
14332       else
14333         oappend ("BYTE PTR ");
14334       break;
14335     case mask_mode:
14336       if (!need_vex)
14337         abort ();
14338       if (vex.w)
14339         oappend ("QWORD PTR ");
14340       else
14341         oappend ("WORD PTR ");
14342       break;
14343     case v_bnd_mode:
14344     case v_bndmk_mode:
14345     default:
14346       break;
14347     }
14348 }
14349
14350 static void
14351 OP_E_register (int bytemode, int sizeflag)
14352 {
14353   int reg = modrm.rm;
14354   const char **names;
14355
14356   USED_REX (REX_B);
14357   if ((rex & REX_B))
14358     reg += 8;
14359
14360   if ((sizeflag & SUFFIX_ALWAYS)
14361       && (bytemode == b_swap_mode
14362           || bytemode == bnd_swap_mode
14363           || bytemode == v_swap_mode))
14364     swap_operand ();
14365
14366   switch (bytemode)
14367     {
14368     case b_mode:
14369     case b_swap_mode:
14370       if (reg & 4)
14371         USED_REX (0);
14372       if (rex)
14373         names = names8rex;
14374       else
14375         names = names8;
14376       break;
14377     case w_mode:
14378       names = names16;
14379       break;
14380     case d_mode:
14381     case dw_mode:
14382     case db_mode:
14383       names = names32;
14384       break;
14385     case q_mode:
14386       names = names64;
14387       break;
14388     case m_mode:
14389     case v_bnd_mode:
14390       names = address_mode == mode_64bit ? names64 : names32;
14391       break;
14392     case bnd_mode:
14393     case bnd_swap_mode:
14394       if (reg > 0x3)
14395         {
14396           oappend ("(bad)");
14397           return;
14398         }
14399       names = names_bnd;
14400       break;
14401     case indir_v_mode:
14402       if (address_mode == mode_64bit && isa64 == intel64)
14403         {
14404           names = names64;
14405           break;
14406         }
14407       /* Fall through.  */
14408     case stack_v_mode:
14409       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14410         {
14411           names = names64;
14412           break;
14413         }
14414       bytemode = v_mode;
14415       /* Fall through.  */
14416     case v_mode:
14417     case v_swap_mode:
14418     case dq_mode:
14419     case dqb_mode:
14420     case dqd_mode:
14421     case dqw_mode:
14422       USED_REX (REX_W);
14423       if (rex & REX_W)
14424         names = names64;
14425       else
14426         {
14427           if ((sizeflag & DFLAG)
14428               || (bytemode != v_mode
14429                   && bytemode != v_swap_mode))
14430             names = names32;
14431           else
14432             names = names16;
14433           used_prefixes |= (prefixes & PREFIX_DATA);
14434         }
14435       break;
14436     case movsxd_mode:
14437       if (!(sizeflag & DFLAG) && isa64 == intel64)
14438         names = names16;
14439       else
14440         names = names32;
14441       used_prefixes |= (prefixes & PREFIX_DATA);
14442       break;
14443     case va_mode:
14444       names = (address_mode == mode_64bit
14445                ? names64 : names32);
14446       if (!(prefixes & PREFIX_ADDR))
14447         names = (address_mode == mode_16bit
14448                      ? names16 : names);
14449       else
14450         {
14451           /* Remove "addr16/addr32".  */
14452           all_prefixes[last_addr_prefix] = 0;
14453           names = (address_mode != mode_32bit
14454                        ? names32 : names16);
14455           used_prefixes |= PREFIX_ADDR;
14456         }
14457       break;
14458     case mask_bd_mode:
14459     case mask_mode:
14460       if (reg > 0x7)
14461         {
14462           oappend ("(bad)");
14463           return;
14464         }
14465       names = names_mask;
14466       break;
14467     case 0:
14468       return;
14469     default:
14470       oappend (INTERNAL_DISASSEMBLER_ERROR);
14471       return;
14472     }
14473   oappend (names[reg]);
14474 }
14475
14476 static void
14477 OP_E_memory (int bytemode, int sizeflag)
14478 {
14479   bfd_vma disp = 0;
14480   int add = (rex & REX_B) ? 8 : 0;
14481   int riprel = 0;
14482   int shift;
14483
14484   if (vex.evex)
14485     {
14486       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14487       if (vex.b
14488           && bytemode != x_mode
14489           && bytemode != xmmq_mode
14490           && bytemode != evex_half_bcst_xmmq_mode)
14491         {
14492           BadOp ();
14493           return;
14494         }
14495       switch (bytemode)
14496         {
14497         case dqw_mode:
14498         case dw_mode:
14499         case xmm_mw_mode:
14500           shift = 1;
14501           break;
14502         case dqb_mode:
14503         case db_mode:
14504         case xmm_mb_mode:
14505           shift = 0;
14506           break;
14507         case dq_mode:
14508           if (address_mode != mode_64bit)
14509             {
14510         case dqd_mode:
14511         case xmm_md_mode:
14512         case d_mode:
14513         case d_swap_mode:
14514               shift = 2;
14515               break;
14516             }
14517             /* fall through */
14518         case vex_scalar_w_dq_mode:
14519         case vex_vsib_d_w_dq_mode:
14520         case vex_vsib_d_w_d_mode:
14521         case vex_vsib_q_w_dq_mode:
14522         case vex_vsib_q_w_d_mode:
14523         case evex_x_gscat_mode:
14524           shift = vex.w ? 3 : 2;
14525           break;
14526         case x_mode:
14527         case evex_half_bcst_xmmq_mode:
14528         case xmmq_mode:
14529           if (vex.b)
14530             {
14531               shift = vex.w ? 3 : 2;
14532               break;
14533             }
14534           /* Fall through.  */
14535         case xmmqd_mode:
14536         case xmmdw_mode:
14537         case ymmq_mode:
14538         case evex_x_nobcst_mode:
14539         case x_swap_mode:
14540           switch (vex.length)
14541             {
14542             case 128:
14543               shift = 4;
14544               break;
14545             case 256:
14546               shift = 5;
14547               break;
14548             case 512:
14549               shift = 6;
14550               break;
14551             default:
14552               abort ();
14553             }
14554           /* Make necessary corrections to shift for modes that need it.  */
14555           if (bytemode == xmmq_mode
14556               || bytemode == evex_half_bcst_xmmq_mode
14557               || (bytemode == ymmq_mode && vex.length == 128))
14558             shift -= 1;
14559           else if (bytemode == xmmqd_mode)
14560             shift -= 2;
14561           else if (bytemode == xmmdw_mode)
14562             shift -= 3;
14563           break;
14564         case ymm_mode:
14565           shift = 5;
14566           break;
14567         case xmm_mode:
14568           shift = 4;
14569           break;
14570         case xmm_mq_mode:
14571         case q_mode:
14572         case q_swap_mode:
14573           shift = 3;
14574           break;
14575         case bw_unit_mode:
14576           shift = vex.w ? 1 : 0;
14577           break;
14578         default:
14579           abort ();
14580         }
14581     }
14582   else
14583     shift = 0;
14584
14585   USED_REX (REX_B);
14586   if (intel_syntax)
14587     intel_operand_size (bytemode, sizeflag);
14588   append_seg ();
14589
14590   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14591     {
14592       /* 32/64 bit address mode */
14593       int havedisp;
14594       int havesib;
14595       int havebase;
14596       int haveindex;
14597       int needindex;
14598       int needaddr32;
14599       int base, rbase;
14600       int vindex = 0;
14601       int scale = 0;
14602       int addr32flag = !((sizeflag & AFLAG)
14603                          || bytemode == v_bnd_mode
14604                          || bytemode == v_bndmk_mode
14605                          || bytemode == bnd_mode
14606                          || bytemode == bnd_swap_mode);
14607       const char **indexes64 = names64;
14608       const char **indexes32 = names32;
14609
14610       havesib = 0;
14611       havebase = 1;
14612       haveindex = 0;
14613       base = modrm.rm;
14614
14615       if (base == 4)
14616         {
14617           havesib = 1;
14618           vindex = sib.index;
14619           USED_REX (REX_X);
14620           if (rex & REX_X)
14621             vindex += 8;
14622           switch (bytemode)
14623             {
14624             case vex_vsib_d_w_dq_mode:
14625             case vex_vsib_d_w_d_mode:
14626             case vex_vsib_q_w_dq_mode:
14627             case vex_vsib_q_w_d_mode:
14628               if (!need_vex)
14629                 abort ();
14630               if (vex.evex)
14631                 {
14632                   if (!vex.v)
14633                     vindex += 16;
14634                 }
14635
14636               haveindex = 1;
14637               switch (vex.length)
14638                 {
14639                 case 128:
14640                   indexes64 = indexes32 = names_xmm;
14641                   break;
14642                 case 256:
14643                   if (!vex.w
14644                       || bytemode == vex_vsib_q_w_dq_mode
14645                       || bytemode == vex_vsib_q_w_d_mode)
14646                     indexes64 = indexes32 = names_ymm;
14647                   else
14648                     indexes64 = indexes32 = names_xmm;
14649                   break;
14650                 case 512:
14651                   if (!vex.w
14652                       || bytemode == vex_vsib_q_w_dq_mode
14653                       || bytemode == vex_vsib_q_w_d_mode)
14654                     indexes64 = indexes32 = names_zmm;
14655                   else
14656                     indexes64 = indexes32 = names_ymm;
14657                   break;
14658                 default:
14659                   abort ();
14660                 }
14661               break;
14662             default:
14663               haveindex = vindex != 4;
14664               break;
14665             }
14666           scale = sib.scale;
14667           base = sib.base;
14668           codep++;
14669         }
14670       else
14671         {
14672           /* mandatory non-vector SIB must have sib */
14673           if (bytemode == vex_sibmem_mode)
14674             {
14675               oappend ("(bad)");
14676               return;
14677             }
14678         }
14679       rbase = base + add;
14680
14681       switch (modrm.mod)
14682         {
14683         case 0:
14684           if (base == 5)
14685             {
14686               havebase = 0;
14687               if (address_mode == mode_64bit && !havesib)
14688                 riprel = 1;
14689               disp = get32s ();
14690               if (riprel && bytemode == v_bndmk_mode)
14691                 {
14692                   oappend ("(bad)");
14693                   return;
14694                 }
14695             }
14696           break;
14697         case 1:
14698           FETCH_DATA (the_info, codep + 1);
14699           disp = *codep++;
14700           if ((disp & 0x80) != 0)
14701             disp -= 0x100;
14702           if (vex.evex && shift > 0)
14703             disp <<= shift;
14704           break;
14705         case 2:
14706           disp = get32s ();
14707           break;
14708         }
14709
14710       needindex = 0;
14711       needaddr32 = 0;
14712       if (havesib
14713           && !havebase
14714           && !haveindex
14715           && address_mode != mode_16bit)
14716         {
14717           if (address_mode == mode_64bit)
14718             {
14719               /* Display eiz instead of addr32.  */
14720               needindex = addr32flag;
14721               needaddr32 = 1;
14722             }
14723           else
14724             {
14725               /* In 32-bit mode, we need index register to tell [offset]
14726                  from [eiz*1 + offset].  */
14727               needindex = 1;
14728             }
14729         }
14730
14731       havedisp = (havebase
14732                   || needindex
14733                   || (havesib && (haveindex || scale != 0)));
14734
14735       if (!intel_syntax)
14736         if (modrm.mod != 0 || base == 5)
14737           {
14738             if (havedisp || riprel)
14739               print_displacement (scratchbuf, disp);
14740             else
14741               print_operand_value (scratchbuf, 1, disp);
14742             oappend (scratchbuf);
14743             if (riprel)
14744               {
14745                 set_op (disp, 1);
14746                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14747               }
14748           }
14749
14750       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14751           && (address_mode != mode_64bit
14752               || ((bytemode != v_bnd_mode)
14753                   && (bytemode != v_bndmk_mode)
14754                   && (bytemode != bnd_mode)
14755                   && (bytemode != bnd_swap_mode))))
14756         used_prefixes |= PREFIX_ADDR;
14757
14758       if (havedisp || (intel_syntax && riprel))
14759         {
14760           *obufp++ = open_char;
14761           if (intel_syntax && riprel)
14762             {
14763               set_op (disp, 1);
14764               oappend (!addr32flag ? "rip" : "eip");
14765             }
14766           *obufp = '\0';
14767           if (havebase)
14768             oappend (address_mode == mode_64bit && !addr32flag
14769                      ? names64[rbase] : names32[rbase]);
14770           if (havesib)
14771             {
14772               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14773                  print index to tell base + index from base.  */
14774               if (scale != 0
14775                   || needindex
14776                   || haveindex
14777                   || (havebase && base != ESP_REG_NUM))
14778                 {
14779                   if (!intel_syntax || havebase)
14780                     {
14781                       *obufp++ = separator_char;
14782                       *obufp = '\0';
14783                     }
14784                   if (haveindex)
14785                     oappend (address_mode == mode_64bit && !addr32flag
14786                              ? indexes64[vindex] : indexes32[vindex]);
14787                   else
14788                     oappend (address_mode == mode_64bit && !addr32flag
14789                              ? index64 : index32);
14790
14791                   *obufp++ = scale_char;
14792                   *obufp = '\0';
14793                   sprintf (scratchbuf, "%d", 1 << scale);
14794                   oappend (scratchbuf);
14795                 }
14796             }
14797           if (intel_syntax
14798               && (disp || modrm.mod != 0 || base == 5))
14799             {
14800               if (!havedisp || (bfd_signed_vma) disp >= 0)
14801                 {
14802                   *obufp++ = '+';
14803                   *obufp = '\0';
14804                 }
14805               else if (modrm.mod != 1 && disp != -disp)
14806                 {
14807                   *obufp++ = '-';
14808                   *obufp = '\0';
14809                   disp = - (bfd_signed_vma) disp;
14810                 }
14811
14812               if (havedisp)
14813                 print_displacement (scratchbuf, disp);
14814               else
14815                 print_operand_value (scratchbuf, 1, disp);
14816               oappend (scratchbuf);
14817             }
14818
14819           *obufp++ = close_char;
14820           *obufp = '\0';
14821         }
14822       else if (intel_syntax)
14823         {
14824           if (modrm.mod != 0 || base == 5)
14825             {
14826               if (!active_seg_prefix)
14827                 {
14828                   oappend (names_seg[ds_reg - es_reg]);
14829                   oappend (":");
14830                 }
14831               print_operand_value (scratchbuf, 1, disp);
14832               oappend (scratchbuf);
14833             }
14834         }
14835     }
14836   else if (bytemode == v_bnd_mode
14837            || bytemode == v_bndmk_mode
14838            || bytemode == bnd_mode
14839            || bytemode == bnd_swap_mode)
14840     {
14841       oappend ("(bad)");
14842       return;
14843     }
14844   else
14845     {
14846       /* 16 bit address mode */
14847       used_prefixes |= prefixes & PREFIX_ADDR;
14848       switch (modrm.mod)
14849         {
14850         case 0:
14851           if (modrm.rm == 6)
14852             {
14853               disp = get16 ();
14854               if ((disp & 0x8000) != 0)
14855                 disp -= 0x10000;
14856             }
14857           break;
14858         case 1:
14859           FETCH_DATA (the_info, codep + 1);
14860           disp = *codep++;
14861           if ((disp & 0x80) != 0)
14862             disp -= 0x100;
14863           if (vex.evex && shift > 0)
14864             disp <<= shift;
14865           break;
14866         case 2:
14867           disp = get16 ();
14868           if ((disp & 0x8000) != 0)
14869             disp -= 0x10000;
14870           break;
14871         }
14872
14873       if (!intel_syntax)
14874         if (modrm.mod != 0 || modrm.rm == 6)
14875           {
14876             print_displacement (scratchbuf, disp);
14877             oappend (scratchbuf);
14878           }
14879
14880       if (modrm.mod != 0 || modrm.rm != 6)
14881         {
14882           *obufp++ = open_char;
14883           *obufp = '\0';
14884           oappend (index16[modrm.rm]);
14885           if (intel_syntax
14886               && (disp || modrm.mod != 0 || modrm.rm == 6))
14887             {
14888               if ((bfd_signed_vma) disp >= 0)
14889                 {
14890                   *obufp++ = '+';
14891                   *obufp = '\0';
14892                 }
14893               else if (modrm.mod != 1)
14894                 {
14895                   *obufp++ = '-';
14896                   *obufp = '\0';
14897                   disp = - (bfd_signed_vma) disp;
14898                 }
14899
14900               print_displacement (scratchbuf, disp);
14901               oappend (scratchbuf);
14902             }
14903
14904           *obufp++ = close_char;
14905           *obufp = '\0';
14906         }
14907       else if (intel_syntax)
14908         {
14909           if (!active_seg_prefix)
14910             {
14911               oappend (names_seg[ds_reg - es_reg]);
14912               oappend (":");
14913             }
14914           print_operand_value (scratchbuf, 1, disp & 0xffff);
14915           oappend (scratchbuf);
14916         }
14917     }
14918   if (vex.evex && vex.b
14919       && (bytemode == x_mode
14920           || bytemode == xmmq_mode
14921           || bytemode == evex_half_bcst_xmmq_mode))
14922     {
14923       if (vex.w
14924           || bytemode == xmmq_mode
14925           || bytemode == evex_half_bcst_xmmq_mode)
14926         {
14927           switch (vex.length)
14928             {
14929             case 128:
14930               oappend ("{1to2}");
14931               break;
14932             case 256:
14933               oappend ("{1to4}");
14934               break;
14935             case 512:
14936               oappend ("{1to8}");
14937               break;
14938             default:
14939               abort ();
14940             }
14941         }
14942       else
14943         {
14944           switch (vex.length)
14945             {
14946             case 128:
14947               oappend ("{1to4}");
14948               break;
14949             case 256:
14950               oappend ("{1to8}");
14951               break;
14952             case 512:
14953               oappend ("{1to16}");
14954               break;
14955             default:
14956               abort ();
14957             }
14958         }
14959     }
14960 }
14961
14962 static void
14963 OP_E (int bytemode, int sizeflag)
14964 {
14965   /* Skip mod/rm byte.  */
14966   MODRM_CHECK;
14967   codep++;
14968
14969   if (modrm.mod == 3)
14970     OP_E_register (bytemode, sizeflag);
14971   else
14972     OP_E_memory (bytemode, sizeflag);
14973 }
14974
14975 static void
14976 OP_G (int bytemode, int sizeflag)
14977 {
14978   int add = 0;
14979   const char **names;
14980   USED_REX (REX_R);
14981   if (rex & REX_R)
14982     add += 8;
14983   switch (bytemode)
14984     {
14985     case b_mode:
14986       if (modrm.reg & 4)
14987         USED_REX (0);
14988       if (rex)
14989         oappend (names8rex[modrm.reg + add]);
14990       else
14991         oappend (names8[modrm.reg + add]);
14992       break;
14993     case w_mode:
14994       oappend (names16[modrm.reg + add]);
14995       break;
14996     case d_mode:
14997     case db_mode:
14998     case dw_mode:
14999       oappend (names32[modrm.reg + add]);
15000       break;
15001     case q_mode:
15002       oappend (names64[modrm.reg + add]);
15003       break;
15004     case bnd_mode:
15005       if (modrm.reg > 0x3)
15006         {
15007           oappend ("(bad)");
15008           return;
15009         }
15010       oappend (names_bnd[modrm.reg]);
15011       break;
15012     case v_mode:
15013     case dq_mode:
15014     case dqb_mode:
15015     case dqd_mode:
15016     case dqw_mode:
15017     case movsxd_mode:
15018       USED_REX (REX_W);
15019       if (rex & REX_W)
15020         oappend (names64[modrm.reg + add]);
15021       else
15022         {
15023           if ((sizeflag & DFLAG)
15024               || (bytemode != v_mode && bytemode != movsxd_mode))
15025             oappend (names32[modrm.reg + add]);
15026           else
15027             oappend (names16[modrm.reg + add]);
15028           used_prefixes |= (prefixes & PREFIX_DATA);
15029         }
15030       break;
15031     case va_mode:
15032       names = (address_mode == mode_64bit
15033                ? names64 : names32);
15034       if (!(prefixes & PREFIX_ADDR))
15035         {
15036           if (address_mode == mode_16bit)
15037             names = names16;
15038         }
15039       else
15040         {
15041           /* Remove "addr16/addr32".  */
15042           all_prefixes[last_addr_prefix] = 0;
15043           names = (address_mode != mode_32bit
15044                        ? names32 : names16);
15045           used_prefixes |= PREFIX_ADDR;
15046         }
15047       oappend (names[modrm.reg + add]);
15048       break;
15049     case m_mode:
15050       if (address_mode == mode_64bit)
15051         oappend (names64[modrm.reg + add]);
15052       else
15053         oappend (names32[modrm.reg + add]);
15054       break;
15055     case mask_bd_mode:
15056     case mask_mode:
15057       if ((modrm.reg + add) > 0x7)
15058         {
15059           oappend ("(bad)");
15060           return;
15061         }
15062       oappend (names_mask[modrm.reg + add]);
15063       break;
15064     default:
15065       oappend (INTERNAL_DISASSEMBLER_ERROR);
15066       break;
15067     }
15068 }
15069
15070 static bfd_vma
15071 get64 (void)
15072 {
15073   bfd_vma x;
15074 #ifdef BFD64
15075   unsigned int a;
15076   unsigned int b;
15077
15078   FETCH_DATA (the_info, codep + 8);
15079   a = *codep++ & 0xff;
15080   a |= (*codep++ & 0xff) << 8;
15081   a |= (*codep++ & 0xff) << 16;
15082   a |= (*codep++ & 0xffu) << 24;
15083   b = *codep++ & 0xff;
15084   b |= (*codep++ & 0xff) << 8;
15085   b |= (*codep++ & 0xff) << 16;
15086   b |= (*codep++ & 0xffu) << 24;
15087   x = a + ((bfd_vma) b << 32);
15088 #else
15089   abort ();
15090   x = 0;
15091 #endif
15092   return x;
15093 }
15094
15095 static bfd_signed_vma
15096 get32 (void)
15097 {
15098   bfd_signed_vma x = 0;
15099
15100   FETCH_DATA (the_info, codep + 4);
15101   x = *codep++ & (bfd_signed_vma) 0xff;
15102   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15103   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15104   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15105   return x;
15106 }
15107
15108 static bfd_signed_vma
15109 get32s (void)
15110 {
15111   bfd_signed_vma x = 0;
15112
15113   FETCH_DATA (the_info, codep + 4);
15114   x = *codep++ & (bfd_signed_vma) 0xff;
15115   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15116   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15117   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15118
15119   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15120
15121   return x;
15122 }
15123
15124 static int
15125 get16 (void)
15126 {
15127   int x = 0;
15128
15129   FETCH_DATA (the_info, codep + 2);
15130   x = *codep++ & 0xff;
15131   x |= (*codep++ & 0xff) << 8;
15132   return x;
15133 }
15134
15135 static void
15136 set_op (bfd_vma op, int riprel)
15137 {
15138   op_index[op_ad] = op_ad;
15139   if (address_mode == mode_64bit)
15140     {
15141       op_address[op_ad] = op;
15142       op_riprel[op_ad] = riprel;
15143     }
15144   else
15145     {
15146       /* Mask to get a 32-bit address.  */
15147       op_address[op_ad] = op & 0xffffffff;
15148       op_riprel[op_ad] = riprel & 0xffffffff;
15149     }
15150 }
15151
15152 static void
15153 OP_REG (int code, int sizeflag)
15154 {
15155   const char *s;
15156   int add;
15157
15158   switch (code)
15159     {
15160     case es_reg: case ss_reg: case cs_reg:
15161     case ds_reg: case fs_reg: case gs_reg:
15162       oappend (names_seg[code - es_reg]);
15163       return;
15164     }
15165
15166   USED_REX (REX_B);
15167   if (rex & REX_B)
15168     add = 8;
15169   else
15170     add = 0;
15171
15172   switch (code)
15173     {
15174     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15175     case sp_reg: case bp_reg: case si_reg: case di_reg:
15176       s = names16[code - ax_reg + add];
15177       break;
15178     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
15179       USED_REX (0);
15180       /* Fall through.  */
15181     case al_reg: case cl_reg: case dl_reg: case bl_reg:
15182       if (rex)
15183         s = names8rex[code - al_reg + add];
15184       else
15185         s = names8[code - al_reg];
15186       break;
15187     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15188     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15189       if (address_mode == mode_64bit
15190           && ((sizeflag & DFLAG) || (rex & REX_W)))
15191         {
15192           s = names64[code - rAX_reg + add];
15193           break;
15194         }
15195       code += eAX_reg - rAX_reg;
15196       /* Fall through.  */
15197     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15198     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15199       USED_REX (REX_W);
15200       if (rex & REX_W)
15201         s = names64[code - eAX_reg + add];
15202       else
15203         {
15204           if (sizeflag & DFLAG)
15205             s = names32[code - eAX_reg + add];
15206           else
15207             s = names16[code - eAX_reg + add];
15208           used_prefixes |= (prefixes & PREFIX_DATA);
15209         }
15210       break;
15211     default:
15212       s = INTERNAL_DISASSEMBLER_ERROR;
15213       break;
15214     }
15215   oappend (s);
15216 }
15217
15218 static void
15219 OP_IMREG (int code, int sizeflag)
15220 {
15221   const char *s;
15222
15223   switch (code)
15224     {
15225     case indir_dx_reg:
15226       if (intel_syntax)
15227         s = "dx";
15228       else
15229         s = "(%dx)";
15230       break;
15231     case al_reg: case cl_reg:
15232       s = names8[code - al_reg];
15233       break;
15234     case eAX_reg:
15235       USED_REX (REX_W);
15236       if (rex & REX_W)
15237         {
15238           s = *names64;
15239           break;
15240         }
15241       /* Fall through.  */
15242     case z_mode_ax_reg:
15243       if ((rex & REX_W) || (sizeflag & DFLAG))
15244         s = *names32;
15245       else
15246         s = *names16;
15247       if (!(rex & REX_W))
15248         used_prefixes |= (prefixes & PREFIX_DATA);
15249       break;
15250     default:
15251       s = INTERNAL_DISASSEMBLER_ERROR;
15252       break;
15253     }
15254   oappend (s);
15255 }
15256
15257 static void
15258 OP_I (int bytemode, int sizeflag)
15259 {
15260   bfd_signed_vma op;
15261   bfd_signed_vma mask = -1;
15262
15263   switch (bytemode)
15264     {
15265     case b_mode:
15266       FETCH_DATA (the_info, codep + 1);
15267       op = *codep++;
15268       mask = 0xff;
15269       break;
15270     case v_mode:
15271       USED_REX (REX_W);
15272       if (rex & REX_W)
15273         op = get32s ();
15274       else
15275         {
15276           if (sizeflag & DFLAG)
15277             {
15278               op = get32 ();
15279               mask = 0xffffffff;
15280             }
15281           else
15282             {
15283               op = get16 ();
15284               mask = 0xfffff;
15285             }
15286           used_prefixes |= (prefixes & PREFIX_DATA);
15287         }
15288       break;
15289     case d_mode:
15290       mask = 0xffffffff;
15291       op = get32 ();
15292       break;
15293     case w_mode:
15294       mask = 0xfffff;
15295       op = get16 ();
15296       break;
15297     case const_1_mode:
15298       if (intel_syntax)
15299         oappend ("1");
15300       return;
15301     default:
15302       oappend (INTERNAL_DISASSEMBLER_ERROR);
15303       return;
15304     }
15305
15306   op &= mask;
15307   scratchbuf[0] = '$';
15308   print_operand_value (scratchbuf + 1, 1, op);
15309   oappend_maybe_intel (scratchbuf);
15310   scratchbuf[0] = '\0';
15311 }
15312
15313 static void
15314 OP_I64 (int bytemode, int sizeflag)
15315 {
15316   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
15317     {
15318       OP_I (bytemode, sizeflag);
15319       return;
15320     }
15321
15322   USED_REX (REX_W);
15323
15324   scratchbuf[0] = '$';
15325   print_operand_value (scratchbuf + 1, 1, get64 ());
15326   oappend_maybe_intel (scratchbuf);
15327   scratchbuf[0] = '\0';
15328 }
15329
15330 static void
15331 OP_sI (int bytemode, int sizeflag)
15332 {
15333   bfd_signed_vma op;
15334
15335   switch (bytemode)
15336     {
15337     case b_mode:
15338     case b_T_mode:
15339       FETCH_DATA (the_info, codep + 1);
15340       op = *codep++;
15341       if ((op & 0x80) != 0)
15342         op -= 0x100;
15343       if (bytemode == b_T_mode)
15344         {
15345           if (address_mode != mode_64bit
15346               || !((sizeflag & DFLAG) || (rex & REX_W)))
15347             {
15348               /* The operand-size prefix is overridden by a REX prefix.  */
15349               if ((sizeflag & DFLAG) || (rex & REX_W))
15350                 op &= 0xffffffff;
15351               else
15352                 op &= 0xffff;
15353           }
15354         }
15355       else
15356         {
15357           if (!(rex & REX_W))
15358             {
15359               if (sizeflag & DFLAG)
15360                 op &= 0xffffffff;
15361               else
15362                 op &= 0xffff;
15363             }
15364         }
15365       break;
15366     case v_mode:
15367       /* The operand-size prefix is overridden by a REX prefix.  */
15368       if ((sizeflag & DFLAG) || (rex & REX_W))
15369         op = get32s ();
15370       else
15371         op = get16 ();
15372       break;
15373     default:
15374       oappend (INTERNAL_DISASSEMBLER_ERROR);
15375       return;
15376     }
15377
15378   scratchbuf[0] = '$';
15379   print_operand_value (scratchbuf + 1, 1, op);
15380   oappend_maybe_intel (scratchbuf);
15381 }
15382
15383 static void
15384 OP_J (int bytemode, int sizeflag)
15385 {
15386   bfd_vma disp;
15387   bfd_vma mask = -1;
15388   bfd_vma segment = 0;
15389
15390   switch (bytemode)
15391     {
15392     case b_mode:
15393       FETCH_DATA (the_info, codep + 1);
15394       disp = *codep++;
15395       if ((disp & 0x80) != 0)
15396         disp -= 0x100;
15397       break;
15398     case v_mode:
15399       if (isa64 != intel64)
15400     case dqw_mode:
15401         USED_REX (REX_W);
15402       if ((sizeflag & DFLAG)
15403           || (address_mode == mode_64bit
15404               && ((isa64 == intel64 && bytemode != dqw_mode)
15405                   || (rex & REX_W))))
15406         disp = get32s ();
15407       else
15408         {
15409           disp = get16 ();
15410           if ((disp & 0x8000) != 0)
15411             disp -= 0x10000;
15412           /* In 16bit mode, address is wrapped around at 64k within
15413              the same segment.  Otherwise, a data16 prefix on a jump
15414              instruction means that the pc is masked to 16 bits after
15415              the displacement is added!  */
15416           mask = 0xffff;
15417           if ((prefixes & PREFIX_DATA) == 0)
15418             segment = ((start_pc + (codep - start_codep))
15419                        & ~((bfd_vma) 0xffff));
15420         }
15421       if (address_mode != mode_64bit
15422           || (isa64 != intel64 && !(rex & REX_W)))
15423         used_prefixes |= (prefixes & PREFIX_DATA);
15424       break;
15425     default:
15426       oappend (INTERNAL_DISASSEMBLER_ERROR);
15427       return;
15428     }
15429   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15430   set_op (disp, 0);
15431   print_operand_value (scratchbuf, 1, disp);
15432   oappend (scratchbuf);
15433 }
15434
15435 static void
15436 OP_SEG (int bytemode, int sizeflag)
15437 {
15438   if (bytemode == w_mode)
15439     oappend (names_seg[modrm.reg]);
15440   else
15441     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15442 }
15443
15444 static void
15445 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15446 {
15447   int seg, offset;
15448
15449   if (sizeflag & DFLAG)
15450     {
15451       offset = get32 ();
15452       seg = get16 ();
15453     }
15454   else
15455     {
15456       offset = get16 ();
15457       seg = get16 ();
15458     }
15459   used_prefixes |= (prefixes & PREFIX_DATA);
15460   if (intel_syntax)
15461     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15462   else
15463     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15464   oappend (scratchbuf);
15465 }
15466
15467 static void
15468 OP_OFF (int bytemode, int sizeflag)
15469 {
15470   bfd_vma off;
15471
15472   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15473     intel_operand_size (bytemode, sizeflag);
15474   append_seg ();
15475
15476   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15477     off = get32 ();
15478   else
15479     off = get16 ();
15480
15481   if (intel_syntax)
15482     {
15483       if (!active_seg_prefix)
15484         {
15485           oappend (names_seg[ds_reg - es_reg]);
15486           oappend (":");
15487         }
15488     }
15489   print_operand_value (scratchbuf, 1, off);
15490   oappend (scratchbuf);
15491 }
15492
15493 static void
15494 OP_OFF64 (int bytemode, int sizeflag)
15495 {
15496   bfd_vma off;
15497
15498   if (address_mode != mode_64bit
15499       || (prefixes & PREFIX_ADDR))
15500     {
15501       OP_OFF (bytemode, sizeflag);
15502       return;
15503     }
15504
15505   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15506     intel_operand_size (bytemode, sizeflag);
15507   append_seg ();
15508
15509   off = get64 ();
15510
15511   if (intel_syntax)
15512     {
15513       if (!active_seg_prefix)
15514         {
15515           oappend (names_seg[ds_reg - es_reg]);
15516           oappend (":");
15517         }
15518     }
15519   print_operand_value (scratchbuf, 1, off);
15520   oappend (scratchbuf);
15521 }
15522
15523 static void
15524 ptr_reg (int code, int sizeflag)
15525 {
15526   const char *s;
15527
15528   *obufp++ = open_char;
15529   used_prefixes |= (prefixes & PREFIX_ADDR);
15530   if (address_mode == mode_64bit)
15531     {
15532       if (!(sizeflag & AFLAG))
15533         s = names32[code - eAX_reg];
15534       else
15535         s = names64[code - eAX_reg];
15536     }
15537   else if (sizeflag & AFLAG)
15538     s = names32[code - eAX_reg];
15539   else
15540     s = names16[code - eAX_reg];
15541   oappend (s);
15542   *obufp++ = close_char;
15543   *obufp = 0;
15544 }
15545
15546 static void
15547 OP_ESreg (int code, int sizeflag)
15548 {
15549   if (intel_syntax)
15550     {
15551       switch (codep[-1])
15552         {
15553         case 0x6d:      /* insw/insl */
15554           intel_operand_size (z_mode, sizeflag);
15555           break;
15556         case 0xa5:      /* movsw/movsl/movsq */
15557         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15558         case 0xab:      /* stosw/stosl */
15559         case 0xaf:      /* scasw/scasl */
15560           intel_operand_size (v_mode, sizeflag);
15561           break;
15562         default:
15563           intel_operand_size (b_mode, sizeflag);
15564         }
15565     }
15566   oappend_maybe_intel ("%es:");
15567   ptr_reg (code, sizeflag);
15568 }
15569
15570 static void
15571 OP_DSreg (int code, int sizeflag)
15572 {
15573   if (intel_syntax)
15574     {
15575       switch (codep[-1])
15576         {
15577         case 0x6f:      /* outsw/outsl */
15578           intel_operand_size (z_mode, sizeflag);
15579           break;
15580         case 0xa5:      /* movsw/movsl/movsq */
15581         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15582         case 0xad:      /* lodsw/lodsl/lodsq */
15583           intel_operand_size (v_mode, sizeflag);
15584           break;
15585         default:
15586           intel_operand_size (b_mode, sizeflag);
15587         }
15588     }
15589   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15590      default segment register DS is printed.  */
15591   if (!active_seg_prefix)
15592     active_seg_prefix = PREFIX_DS;
15593   append_seg ();
15594   ptr_reg (code, sizeflag);
15595 }
15596
15597 static void
15598 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15599 {
15600   int add;
15601   if (rex & REX_R)
15602     {
15603       USED_REX (REX_R);
15604       add = 8;
15605     }
15606   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15607     {
15608       all_prefixes[last_lock_prefix] = 0;
15609       used_prefixes |= PREFIX_LOCK;
15610       add = 8;
15611     }
15612   else
15613     add = 0;
15614   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15615   oappend_maybe_intel (scratchbuf);
15616 }
15617
15618 static void
15619 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15620 {
15621   int add;
15622   USED_REX (REX_R);
15623   if (rex & REX_R)
15624     add = 8;
15625   else
15626     add = 0;
15627   if (intel_syntax)
15628     sprintf (scratchbuf, "db%d", modrm.reg + add);
15629   else
15630     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15631   oappend (scratchbuf);
15632 }
15633
15634 static void
15635 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15636 {
15637   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15638   oappend_maybe_intel (scratchbuf);
15639 }
15640
15641 static void
15642 OP_R (int bytemode, int sizeflag)
15643 {
15644   /* Skip mod/rm byte.  */
15645   MODRM_CHECK;
15646   codep++;
15647   OP_E_register (bytemode, sizeflag);
15648 }
15649
15650 static void
15651 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15652 {
15653   int reg = modrm.reg;
15654   const char **names;
15655
15656   used_prefixes |= (prefixes & PREFIX_DATA);
15657   if (prefixes & PREFIX_DATA)
15658     {
15659       names = names_xmm;
15660       USED_REX (REX_R);
15661       if (rex & REX_R)
15662         reg += 8;
15663     }
15664   else
15665     names = names_mm;
15666   oappend (names[reg]);
15667 }
15668
15669 static void
15670 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15671 {
15672   int reg = modrm.reg;
15673   const char **names;
15674
15675   USED_REX (REX_R);
15676   if (rex & REX_R)
15677     reg += 8;
15678   if (vex.evex)
15679     {
15680       if (!vex.r)
15681         reg += 16;
15682     }
15683
15684   if (need_vex
15685       && bytemode != xmm_mode
15686       && bytemode != xmmq_mode
15687       && bytemode != evex_half_bcst_xmmq_mode
15688       && bytemode != ymm_mode
15689       && bytemode != tmm_mode
15690       && bytemode != scalar_mode)
15691     {
15692       switch (vex.length)
15693         {
15694         case 128:
15695           names = names_xmm;
15696           break;
15697         case 256:
15698           if (vex.w
15699               || (bytemode != vex_vsib_q_w_dq_mode
15700                   && bytemode != vex_vsib_q_w_d_mode))
15701             names = names_ymm;
15702           else
15703             names = names_xmm;
15704           break;
15705         case 512:
15706           names = names_zmm;
15707           break;
15708         default:
15709           abort ();
15710         }
15711     }
15712   else if (bytemode == xmmq_mode
15713            || bytemode == evex_half_bcst_xmmq_mode)
15714     {
15715       switch (vex.length)
15716         {
15717         case 128:
15718         case 256:
15719           names = names_xmm;
15720           break;
15721         case 512:
15722           names = names_ymm;
15723           break;
15724         default:
15725           abort ();
15726         }
15727     }
15728   else if (bytemode == tmm_mode)
15729     {
15730       modrm.reg = reg;
15731       if (reg >= 8)
15732         {
15733           oappend ("(bad)");
15734           return;
15735         }
15736       names = names_tmm;
15737     }
15738   else if (bytemode == ymm_mode)
15739     names = names_ymm;
15740   else
15741     names = names_xmm;
15742   oappend (names[reg]);
15743 }
15744
15745 static void
15746 OP_EM (int bytemode, int sizeflag)
15747 {
15748   int reg;
15749   const char **names;
15750
15751   if (modrm.mod != 3)
15752     {
15753       if (intel_syntax
15754           && (bytemode == v_mode || bytemode == v_swap_mode))
15755         {
15756           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15757           used_prefixes |= (prefixes & PREFIX_DATA);
15758         }
15759       OP_E (bytemode, sizeflag);
15760       return;
15761     }
15762
15763   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15764     swap_operand ();
15765
15766   /* Skip mod/rm byte.  */
15767   MODRM_CHECK;
15768   codep++;
15769   used_prefixes |= (prefixes & PREFIX_DATA);
15770   reg = modrm.rm;
15771   if (prefixes & PREFIX_DATA)
15772     {
15773       names = names_xmm;
15774       USED_REX (REX_B);
15775       if (rex & REX_B)
15776         reg += 8;
15777     }
15778   else
15779     names = names_mm;
15780   oappend (names[reg]);
15781 }
15782
15783 /* cvt* are the only instructions in sse2 which have
15784    both SSE and MMX operands and also have 0x66 prefix
15785    in their opcode. 0x66 was originally used to differentiate
15786    between SSE and MMX instruction(operands). So we have to handle the
15787    cvt* separately using OP_EMC and OP_MXC */
15788 static void
15789 OP_EMC (int bytemode, int sizeflag)
15790 {
15791   if (modrm.mod != 3)
15792     {
15793       if (intel_syntax && bytemode == v_mode)
15794         {
15795           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15796           used_prefixes |= (prefixes & PREFIX_DATA);
15797         }
15798       OP_E (bytemode, sizeflag);
15799       return;
15800     }
15801
15802   /* Skip mod/rm byte.  */
15803   MODRM_CHECK;
15804   codep++;
15805   used_prefixes |= (prefixes & PREFIX_DATA);
15806   oappend (names_mm[modrm.rm]);
15807 }
15808
15809 static void
15810 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15811 {
15812   used_prefixes |= (prefixes & PREFIX_DATA);
15813   oappend (names_mm[modrm.reg]);
15814 }
15815
15816 static void
15817 OP_EX (int bytemode, int sizeflag)
15818 {
15819   int reg;
15820   const char **names;
15821
15822   /* Skip mod/rm byte.  */
15823   MODRM_CHECK;
15824   codep++;
15825
15826   if (modrm.mod != 3)
15827     {
15828       OP_E_memory (bytemode, sizeflag);
15829       return;
15830     }
15831
15832   reg = modrm.rm;
15833   USED_REX (REX_B);
15834   if (rex & REX_B)
15835     reg += 8;
15836   if (vex.evex)
15837     {
15838       USED_REX (REX_X);
15839       if ((rex & REX_X))
15840         reg += 16;
15841     }
15842
15843   if ((sizeflag & SUFFIX_ALWAYS)
15844       && (bytemode == x_swap_mode
15845           || bytemode == d_swap_mode
15846           || bytemode == q_swap_mode))
15847     swap_operand ();
15848
15849   if (need_vex
15850       && bytemode != xmm_mode
15851       && bytemode != xmmdw_mode
15852       && bytemode != xmmqd_mode
15853       && bytemode != xmm_mb_mode
15854       && bytemode != xmm_mw_mode
15855       && bytemode != xmm_md_mode
15856       && bytemode != xmm_mq_mode
15857       && bytemode != xmmq_mode
15858       && bytemode != evex_half_bcst_xmmq_mode
15859       && bytemode != ymm_mode
15860       && bytemode != tmm_mode
15861       && bytemode != vex_scalar_w_dq_mode)
15862     {
15863       switch (vex.length)
15864         {
15865         case 128:
15866           names = names_xmm;
15867           break;
15868         case 256:
15869           names = names_ymm;
15870           break;
15871         case 512:
15872           names = names_zmm;
15873           break;
15874         default:
15875           abort ();
15876         }
15877     }
15878   else if (bytemode == xmmq_mode
15879            || bytemode == evex_half_bcst_xmmq_mode)
15880     {
15881       switch (vex.length)
15882         {
15883         case 128:
15884         case 256:
15885           names = names_xmm;
15886           break;
15887         case 512:
15888           names = names_ymm;
15889           break;
15890         default:
15891           abort ();
15892         }
15893     }
15894   else if (bytemode == tmm_mode)
15895     {
15896       modrm.rm = reg;
15897       if (reg >= 8)
15898         {
15899           oappend ("(bad)");
15900           return;
15901         }
15902       names = names_tmm;
15903     }
15904   else if (bytemode == ymm_mode)
15905     names = names_ymm;
15906   else
15907     names = names_xmm;
15908   oappend (names[reg]);
15909 }
15910
15911 static void
15912 OP_MS (int bytemode, int sizeflag)
15913 {
15914   if (modrm.mod == 3)
15915     OP_EM (bytemode, sizeflag);
15916   else
15917     BadOp ();
15918 }
15919
15920 static void
15921 OP_XS (int bytemode, int sizeflag)
15922 {
15923   if (modrm.mod == 3)
15924     OP_EX (bytemode, sizeflag);
15925   else
15926     BadOp ();
15927 }
15928
15929 static void
15930 OP_M (int bytemode, int sizeflag)
15931 {
15932   if (modrm.mod == 3)
15933     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15934     BadOp ();
15935   else
15936     OP_E (bytemode, sizeflag);
15937 }
15938
15939 static void
15940 OP_0f07 (int bytemode, int sizeflag)
15941 {
15942   if (modrm.mod != 3 || modrm.rm != 0)
15943     BadOp ();
15944   else
15945     OP_E (bytemode, sizeflag);
15946 }
15947
15948 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15949    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15950
15951 static void
15952 NOP_Fixup1 (int bytemode, int sizeflag)
15953 {
15954   if ((prefixes & PREFIX_DATA) != 0
15955       || (rex != 0
15956           && rex != 0x48
15957           && address_mode == mode_64bit))
15958     OP_REG (bytemode, sizeflag);
15959   else
15960     strcpy (obuf, "nop");
15961 }
15962
15963 static void
15964 NOP_Fixup2 (int bytemode, int sizeflag)
15965 {
15966   if ((prefixes & PREFIX_DATA) != 0
15967       || (rex != 0
15968           && rex != 0x48
15969           && address_mode == mode_64bit))
15970     OP_IMREG (bytemode, sizeflag);
15971 }
15972
15973 static const char *const Suffix3DNow[] = {
15974 /* 00 */        NULL,           NULL,           NULL,           NULL,
15975 /* 04 */        NULL,           NULL,           NULL,           NULL,
15976 /* 08 */        NULL,           NULL,           NULL,           NULL,
15977 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15978 /* 10 */        NULL,           NULL,           NULL,           NULL,
15979 /* 14 */        NULL,           NULL,           NULL,           NULL,
15980 /* 18 */        NULL,           NULL,           NULL,           NULL,
15981 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15982 /* 20 */        NULL,           NULL,           NULL,           NULL,
15983 /* 24 */        NULL,           NULL,           NULL,           NULL,
15984 /* 28 */        NULL,           NULL,           NULL,           NULL,
15985 /* 2C */        NULL,           NULL,           NULL,           NULL,
15986 /* 30 */        NULL,           NULL,           NULL,           NULL,
15987 /* 34 */        NULL,           NULL,           NULL,           NULL,
15988 /* 38 */        NULL,           NULL,           NULL,           NULL,
15989 /* 3C */        NULL,           NULL,           NULL,           NULL,
15990 /* 40 */        NULL,           NULL,           NULL,           NULL,
15991 /* 44 */        NULL,           NULL,           NULL,           NULL,
15992 /* 48 */        NULL,           NULL,           NULL,           NULL,
15993 /* 4C */        NULL,           NULL,           NULL,           NULL,
15994 /* 50 */        NULL,           NULL,           NULL,           NULL,
15995 /* 54 */        NULL,           NULL,           NULL,           NULL,
15996 /* 58 */        NULL,           NULL,           NULL,           NULL,
15997 /* 5C */        NULL,           NULL,           NULL,           NULL,
15998 /* 60 */        NULL,           NULL,           NULL,           NULL,
15999 /* 64 */        NULL,           NULL,           NULL,           NULL,
16000 /* 68 */        NULL,           NULL,           NULL,           NULL,
16001 /* 6C */        NULL,           NULL,           NULL,           NULL,
16002 /* 70 */        NULL,           NULL,           NULL,           NULL,
16003 /* 74 */        NULL,           NULL,           NULL,           NULL,
16004 /* 78 */        NULL,           NULL,           NULL,           NULL,
16005 /* 7C */        NULL,           NULL,           NULL,           NULL,
16006 /* 80 */        NULL,           NULL,           NULL,           NULL,
16007 /* 84 */        NULL,           NULL,           NULL,           NULL,
16008 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16009 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16010 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16011 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16012 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16013 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16014 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16015 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16016 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16017 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16018 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16019 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16020 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16021 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16022 /* C0 */        NULL,           NULL,           NULL,           NULL,
16023 /* C4 */        NULL,           NULL,           NULL,           NULL,
16024 /* C8 */        NULL,           NULL,           NULL,           NULL,
16025 /* CC */        NULL,           NULL,           NULL,           NULL,
16026 /* D0 */        NULL,           NULL,           NULL,           NULL,
16027 /* D4 */        NULL,           NULL,           NULL,           NULL,
16028 /* D8 */        NULL,           NULL,           NULL,           NULL,
16029 /* DC */        NULL,           NULL,           NULL,           NULL,
16030 /* E0 */        NULL,           NULL,           NULL,           NULL,
16031 /* E4 */        NULL,           NULL,           NULL,           NULL,
16032 /* E8 */        NULL,           NULL,           NULL,           NULL,
16033 /* EC */        NULL,           NULL,           NULL,           NULL,
16034 /* F0 */        NULL,           NULL,           NULL,           NULL,
16035 /* F4 */        NULL,           NULL,           NULL,           NULL,
16036 /* F8 */        NULL,           NULL,           NULL,           NULL,
16037 /* FC */        NULL,           NULL,           NULL,           NULL,
16038 };
16039
16040 static void
16041 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16042 {
16043   const char *mnemonic;
16044
16045   FETCH_DATA (the_info, codep + 1);
16046   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16047      place where an 8-bit immediate would normally go.  ie. the last
16048      byte of the instruction.  */
16049   obufp = mnemonicendp;
16050   mnemonic = Suffix3DNow[*codep++ & 0xff];
16051   if (mnemonic)
16052     oappend (mnemonic);
16053   else
16054     {
16055       /* Since a variable sized modrm/sib chunk is between the start
16056          of the opcode (0x0f0f) and the opcode suffix, we need to do
16057          all the modrm processing first, and don't know until now that
16058          we have a bad opcode.  This necessitates some cleaning up.  */
16059       op_out[0][0] = '\0';
16060       op_out[1][0] = '\0';
16061       BadOp ();
16062     }
16063   mnemonicendp = obufp;
16064 }
16065
16066 static const struct op simd_cmp_op[] =
16067 {
16068   { STRING_COMMA_LEN ("eq") },
16069   { STRING_COMMA_LEN ("lt") },
16070   { STRING_COMMA_LEN ("le") },
16071   { STRING_COMMA_LEN ("unord") },
16072   { STRING_COMMA_LEN ("neq") },
16073   { STRING_COMMA_LEN ("nlt") },
16074   { STRING_COMMA_LEN ("nle") },
16075   { STRING_COMMA_LEN ("ord") }
16076 };
16077
16078 static const struct op vex_cmp_op[] =
16079 {
16080   { STRING_COMMA_LEN ("eq_uq") },
16081   { STRING_COMMA_LEN ("nge") },
16082   { STRING_COMMA_LEN ("ngt") },
16083   { STRING_COMMA_LEN ("false") },
16084   { STRING_COMMA_LEN ("neq_oq") },
16085   { STRING_COMMA_LEN ("ge") },
16086   { STRING_COMMA_LEN ("gt") },
16087   { STRING_COMMA_LEN ("true") },
16088   { STRING_COMMA_LEN ("eq_os") },
16089   { STRING_COMMA_LEN ("lt_oq") },
16090   { STRING_COMMA_LEN ("le_oq") },
16091   { STRING_COMMA_LEN ("unord_s") },
16092   { STRING_COMMA_LEN ("neq_us") },
16093   { STRING_COMMA_LEN ("nlt_uq") },
16094   { STRING_COMMA_LEN ("nle_uq") },
16095   { STRING_COMMA_LEN ("ord_s") },
16096   { STRING_COMMA_LEN ("eq_us") },
16097   { STRING_COMMA_LEN ("nge_uq") },
16098   { STRING_COMMA_LEN ("ngt_uq") },
16099   { STRING_COMMA_LEN ("false_os") },
16100   { STRING_COMMA_LEN ("neq_os") },
16101   { STRING_COMMA_LEN ("ge_oq") },
16102   { STRING_COMMA_LEN ("gt_oq") },
16103   { STRING_COMMA_LEN ("true_us") },
16104 };
16105
16106 static void
16107 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16108 {
16109   unsigned int cmp_type;
16110
16111   FETCH_DATA (the_info, codep + 1);
16112   cmp_type = *codep++ & 0xff;
16113   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16114     {
16115       char suffix [3];
16116       char *p = mnemonicendp - 2;
16117       suffix[0] = p[0];
16118       suffix[1] = p[1];
16119       suffix[2] = '\0';
16120       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16121       mnemonicendp += simd_cmp_op[cmp_type].len;
16122     }
16123   else if (need_vex
16124            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
16125     {
16126       char suffix [3];
16127       char *p = mnemonicendp - 2;
16128       suffix[0] = p[0];
16129       suffix[1] = p[1];
16130       suffix[2] = '\0';
16131       cmp_type -= ARRAY_SIZE (simd_cmp_op);
16132       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16133       mnemonicendp += vex_cmp_op[cmp_type].len;
16134     }
16135   else
16136     {
16137       /* We have a reserved extension byte.  Output it directly.  */
16138       scratchbuf[0] = '$';
16139       print_operand_value (scratchbuf + 1, 1, cmp_type);
16140       oappend_maybe_intel (scratchbuf);
16141       scratchbuf[0] = '\0';
16142     }
16143 }
16144
16145 static void
16146 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16147 {
16148   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
16149   if (!intel_syntax)
16150     {
16151       strcpy (op_out[0], names32[0]);
16152       strcpy (op_out[1], names32[1]);
16153       if (bytemode == eBX_reg)
16154         strcpy (op_out[2], names32[3]);
16155       two_source_ops = 1;
16156     }
16157   /* Skip mod/rm byte.  */
16158   MODRM_CHECK;
16159   codep++;
16160 }
16161
16162 static void
16163 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16164             int sizeflag ATTRIBUTE_UNUSED)
16165 {
16166   /* monitor %{e,r,}ax,%ecx,%edx"  */
16167   if (!intel_syntax)
16168     {
16169       const char **names = (address_mode == mode_64bit
16170                             ? names64 : names32);
16171
16172       if (prefixes & PREFIX_ADDR)
16173         {
16174           /* Remove "addr16/addr32".  */
16175           all_prefixes[last_addr_prefix] = 0;
16176           names = (address_mode != mode_32bit
16177                    ? names32 : names16);
16178           used_prefixes |= PREFIX_ADDR;
16179         }
16180       else if (address_mode == mode_16bit)
16181         names = names16;
16182       strcpy (op_out[0], names[0]);
16183       strcpy (op_out[1], names32[1]);
16184       strcpy (op_out[2], names32[2]);
16185       two_source_ops = 1;
16186     }
16187   /* Skip mod/rm byte.  */
16188   MODRM_CHECK;
16189   codep++;
16190 }
16191
16192 static void
16193 BadOp (void)
16194 {
16195   /* Throw away prefixes and 1st. opcode byte.  */
16196   codep = insn_codep + 1;
16197   oappend ("(bad)");
16198 }
16199
16200 static void
16201 REP_Fixup (int bytemode, int sizeflag)
16202 {
16203   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16204      lods and stos.  */
16205   if (prefixes & PREFIX_REPZ)
16206     all_prefixes[last_repz_prefix] = REP_PREFIX;
16207
16208   switch (bytemode)
16209     {
16210     case al_reg:
16211     case eAX_reg:
16212     case indir_dx_reg:
16213       OP_IMREG (bytemode, sizeflag);
16214       break;
16215     case eDI_reg:
16216       OP_ESreg (bytemode, sizeflag);
16217       break;
16218     case eSI_reg:
16219       OP_DSreg (bytemode, sizeflag);
16220       break;
16221     default:
16222       abort ();
16223       break;
16224     }
16225 }
16226
16227 static void
16228 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16229 {
16230   if ( isa64 != amd64 )
16231     return;
16232
16233   obufp = obuf;
16234   BadOp ();
16235   mnemonicendp = obufp;
16236   ++codep;
16237 }
16238
16239 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16240    "bnd".  */
16241
16242 static void
16243 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16244 {
16245   if (prefixes & PREFIX_REPNZ)
16246     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16247 }
16248
16249 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16250    "notrack".  */
16251
16252 static void
16253 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16254                int sizeflag ATTRIBUTE_UNUSED)
16255 {
16256   if (active_seg_prefix == PREFIX_DS
16257       && (address_mode != mode_64bit || last_data_prefix < 0))
16258     {
16259       /* NOTRACK prefix is only valid on indirect branch instructions.
16260          NB: DATA prefix is unsupported for Intel64.  */
16261       active_seg_prefix = 0;
16262       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16263     }
16264 }
16265
16266 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16267    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16268  */
16269
16270 static void
16271 HLE_Fixup1 (int bytemode, int sizeflag)
16272 {
16273   if (modrm.mod != 3
16274       && (prefixes & PREFIX_LOCK) != 0)
16275     {
16276       if (prefixes & PREFIX_REPZ)
16277         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16278       if (prefixes & PREFIX_REPNZ)
16279         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16280     }
16281
16282   OP_E (bytemode, sizeflag);
16283 }
16284
16285 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16286    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16287  */
16288
16289 static void
16290 HLE_Fixup2 (int bytemode, int sizeflag)
16291 {
16292   if (modrm.mod != 3)
16293     {
16294       if (prefixes & PREFIX_REPZ)
16295         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16296       if (prefixes & PREFIX_REPNZ)
16297         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16298     }
16299
16300   OP_E (bytemode, sizeflag);
16301 }
16302
16303 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16304    "xrelease" for memory operand.  No check for LOCK prefix.   */
16305
16306 static void
16307 HLE_Fixup3 (int bytemode, int sizeflag)
16308 {
16309   if (modrm.mod != 3
16310       && last_repz_prefix > last_repnz_prefix
16311       && (prefixes & PREFIX_REPZ) != 0)
16312     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16313
16314   OP_E (bytemode, sizeflag);
16315 }
16316
16317 static void
16318 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16319 {
16320   USED_REX (REX_W);
16321   if (rex & REX_W)
16322     {
16323       /* Change cmpxchg8b to cmpxchg16b.  */
16324       char *p = mnemonicendp - 2;
16325       mnemonicendp = stpcpy (p, "16b");
16326       bytemode = o_mode;
16327     }
16328   else if ((prefixes & PREFIX_LOCK) != 0)
16329     {
16330       if (prefixes & PREFIX_REPZ)
16331         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16332       if (prefixes & PREFIX_REPNZ)
16333         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16334     }
16335
16336   OP_M (bytemode, sizeflag);
16337 }
16338
16339 static void
16340 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16341 {
16342   const char **names;
16343
16344   if (need_vex)
16345     {
16346       switch (vex.length)
16347         {
16348         case 128:
16349           names = names_xmm;
16350           break;
16351         case 256:
16352           names = names_ymm;
16353           break;
16354         default:
16355           abort ();
16356         }
16357     }
16358   else
16359     names = names_xmm;
16360   oappend (names[reg]);
16361 }
16362
16363 static void
16364 FXSAVE_Fixup (int bytemode, int sizeflag)
16365 {
16366   /* Add proper suffix to "fxsave" and "fxrstor".  */
16367   USED_REX (REX_W);
16368   if (rex & REX_W)
16369     {
16370       char *p = mnemonicendp;
16371       *p++ = '6';
16372       *p++ = '4';
16373       *p = '\0';
16374       mnemonicendp = p;
16375     }
16376   OP_M (bytemode, sizeflag);
16377 }
16378
16379 /* Display the destination register operand for instructions with
16380    VEX. */
16381
16382 static void
16383 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16384 {
16385   int reg;
16386   const char **names;
16387
16388   if (!need_vex)
16389     abort ();
16390
16391   reg = vex.register_specifier;
16392   vex.register_specifier = 0;
16393   if (address_mode != mode_64bit)
16394     reg &= 7;
16395   else if (vex.evex && !vex.v)
16396     reg += 16;
16397
16398   if (bytemode == vex_scalar_mode)
16399     {
16400       oappend (names_xmm[reg]);
16401       return;
16402     }
16403
16404   if (bytemode == tmm_mode)
16405     {
16406       /* All 3 TMM registers must be distinct.  */
16407       if (reg >= 8)
16408         oappend ("(bad)");
16409       else
16410         {
16411           /* This must be the 3rd operand.  */
16412           if (obufp != op_out[2])
16413             abort ();
16414           oappend (names_tmm[reg]);
16415           if (reg == modrm.reg || reg == modrm.rm)
16416             strcpy (obufp, "/(bad)");
16417         }
16418
16419       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
16420         {
16421           if (modrm.reg <= 8
16422               && (modrm.reg == modrm.rm || modrm.reg == reg))
16423             strcat (op_out[0], "/(bad)");
16424           if (modrm.rm <= 8
16425               && (modrm.rm == modrm.reg || modrm.rm == reg))
16426             strcat (op_out[1], "/(bad)");
16427         }
16428
16429       return;
16430     }
16431
16432   switch (vex.length)
16433     {
16434     case 128:
16435       switch (bytemode)
16436         {
16437         case vex_mode:
16438         case vex_vsib_q_w_dq_mode:
16439         case vex_vsib_q_w_d_mode:
16440           names = names_xmm;
16441           break;
16442         case dq_mode:
16443           if (rex & REX_W)
16444             names = names64;
16445           else
16446             names = names32;
16447           break;
16448         case mask_bd_mode:
16449         case mask_mode:
16450           if (reg > 0x7)
16451             {
16452               oappend ("(bad)");
16453               return;
16454             }
16455           names = names_mask;
16456           break;
16457         default:
16458           abort ();
16459           return;
16460         }
16461       break;
16462     case 256:
16463       switch (bytemode)
16464         {
16465         case vex_mode:
16466           names = names_ymm;
16467           break;
16468         case vex_vsib_q_w_dq_mode:
16469         case vex_vsib_q_w_d_mode:
16470           names = vex.w ? names_ymm : names_xmm;
16471           break;
16472         case mask_bd_mode:
16473         case mask_mode:
16474           if (reg > 0x7)
16475             {
16476               oappend ("(bad)");
16477               return;
16478             }
16479           names = names_mask;
16480           break;
16481         default:
16482           /* See PR binutils/20893 for a reproducer.  */
16483           oappend ("(bad)");
16484           return;
16485         }
16486       break;
16487     case 512:
16488       names = names_zmm;
16489       break;
16490     default:
16491       abort ();
16492       break;
16493     }
16494   oappend (names[reg]);
16495 }
16496
16497 static void
16498 OP_VexR (int bytemode, int sizeflag)
16499 {
16500   if (modrm.mod == 3)
16501     OP_VEX (bytemode, sizeflag);
16502 }
16503
16504 static void
16505 OP_VexW (int bytemode, int sizeflag)
16506 {
16507   OP_VEX (bytemode, sizeflag);
16508
16509   if (vex.w)
16510     {
16511       /* Swap 2nd and 3rd operands.  */
16512       strcpy (scratchbuf, op_out[2]);
16513       strcpy (op_out[2], op_out[1]);
16514       strcpy (op_out[1], scratchbuf);
16515     }
16516 }
16517
16518 static void
16519 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16520 {
16521   int reg;
16522   const char **names = names_xmm;
16523
16524   FETCH_DATA (the_info, codep + 1);
16525   reg = *codep++;
16526
16527   if (bytemode != x_mode && bytemode != scalar_mode)
16528     abort ();
16529
16530   reg >>= 4;
16531   if (address_mode != mode_64bit)
16532     reg &= 7;
16533
16534   if (bytemode == x_mode && vex.length == 256)
16535     names = names_ymm;
16536
16537   oappend (names[reg]);
16538
16539   if (vex.w)
16540     {
16541       /* Swap 3rd and 4th operands.  */
16542       strcpy (scratchbuf, op_out[3]);
16543       strcpy (op_out[3], op_out[2]);
16544       strcpy (op_out[2], scratchbuf);
16545     }
16546 }
16547
16548 static void
16549 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
16550           int sizeflag ATTRIBUTE_UNUSED)
16551 {
16552   scratchbuf[0] = '$';
16553   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
16554   oappend_maybe_intel (scratchbuf);
16555 }
16556
16557 static void
16558 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16559              int sizeflag ATTRIBUTE_UNUSED)
16560 {
16561   unsigned int cmp_type;
16562
16563   if (!vex.evex)
16564     abort ();
16565
16566   FETCH_DATA (the_info, codep + 1);
16567   cmp_type = *codep++ & 0xff;
16568   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16569      If it's the case, print suffix, otherwise - print the immediate.  */
16570   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16571       && cmp_type != 3
16572       && cmp_type != 7)
16573     {
16574       char suffix [3];
16575       char *p = mnemonicendp - 2;
16576
16577       /* vpcmp* can have both one- and two-lettered suffix.  */
16578       if (p[0] == 'p')
16579         {
16580           p++;
16581           suffix[0] = p[0];
16582           suffix[1] = '\0';
16583         }
16584       else
16585         {
16586           suffix[0] = p[0];
16587           suffix[1] = p[1];
16588           suffix[2] = '\0';
16589         }
16590
16591       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16592       mnemonicendp += simd_cmp_op[cmp_type].len;
16593     }
16594   else
16595     {
16596       /* We have a reserved extension byte.  Output it directly.  */
16597       scratchbuf[0] = '$';
16598       print_operand_value (scratchbuf + 1, 1, cmp_type);
16599       oappend_maybe_intel (scratchbuf);
16600       scratchbuf[0] = '\0';
16601     }
16602 }
16603
16604 static const struct op xop_cmp_op[] =
16605 {
16606   { STRING_COMMA_LEN ("lt") },
16607   { STRING_COMMA_LEN ("le") },
16608   { STRING_COMMA_LEN ("gt") },
16609   { STRING_COMMA_LEN ("ge") },
16610   { STRING_COMMA_LEN ("eq") },
16611   { STRING_COMMA_LEN ("neq") },
16612   { STRING_COMMA_LEN ("false") },
16613   { STRING_COMMA_LEN ("true") }
16614 };
16615
16616 static void
16617 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16618              int sizeflag ATTRIBUTE_UNUSED)
16619 {
16620   unsigned int cmp_type;
16621
16622   FETCH_DATA (the_info, codep + 1);
16623   cmp_type = *codep++ & 0xff;
16624   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16625     {
16626       char suffix[3];
16627       char *p = mnemonicendp - 2;
16628
16629       /* vpcom* can have both one- and two-lettered suffix.  */
16630       if (p[0] == 'm')
16631         {
16632           p++;
16633           suffix[0] = p[0];
16634           suffix[1] = '\0';
16635         }
16636       else
16637         {
16638           suffix[0] = p[0];
16639           suffix[1] = p[1];
16640           suffix[2] = '\0';
16641         }
16642
16643       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16644       mnemonicendp += xop_cmp_op[cmp_type].len;
16645     }
16646   else
16647     {
16648       /* We have a reserved extension byte.  Output it directly.  */
16649       scratchbuf[0] = '$';
16650       print_operand_value (scratchbuf + 1, 1, cmp_type);
16651       oappend_maybe_intel (scratchbuf);
16652       scratchbuf[0] = '\0';
16653     }
16654 }
16655
16656 static const struct op pclmul_op[] =
16657 {
16658   { STRING_COMMA_LEN ("lql") },
16659   { STRING_COMMA_LEN ("hql") },
16660   { STRING_COMMA_LEN ("lqh") },
16661   { STRING_COMMA_LEN ("hqh") }
16662 };
16663
16664 static void
16665 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16666               int sizeflag ATTRIBUTE_UNUSED)
16667 {
16668   unsigned int pclmul_type;
16669
16670   FETCH_DATA (the_info, codep + 1);
16671   pclmul_type = *codep++ & 0xff;
16672   switch (pclmul_type)
16673     {
16674     case 0x10:
16675       pclmul_type = 2;
16676       break;
16677     case 0x11:
16678       pclmul_type = 3;
16679       break;
16680     default:
16681       break;
16682     }
16683   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16684     {
16685       char suffix [4];
16686       char *p = mnemonicendp - 3;
16687       suffix[0] = p[0];
16688       suffix[1] = p[1];
16689       suffix[2] = p[2];
16690       suffix[3] = '\0';
16691       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16692       mnemonicendp += pclmul_op[pclmul_type].len;
16693     }
16694   else
16695     {
16696       /* We have a reserved extension byte.  Output it directly.  */
16697       scratchbuf[0] = '$';
16698       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16699       oappend_maybe_intel (scratchbuf);
16700       scratchbuf[0] = '\0';
16701     }
16702 }
16703
16704 static void
16705 MOVSXD_Fixup (int bytemode, int sizeflag)
16706 {
16707   /* Add proper suffix to "movsxd".  */
16708   char *p = mnemonicendp;
16709
16710   switch (bytemode)
16711     {
16712     case movsxd_mode:
16713       if (intel_syntax)
16714         {
16715           *p++ = 'x';
16716           *p++ = 'd';
16717           goto skip;
16718         }
16719
16720       USED_REX (REX_W);
16721       if (rex & REX_W)
16722         {
16723           *p++ = 'l';
16724           *p++ = 'q';
16725         }
16726       else
16727         {
16728           *p++ = 'x';
16729           *p++ = 'd';
16730         }
16731       break;
16732     default:
16733       oappend (INTERNAL_DISASSEMBLER_ERROR);
16734       break;
16735     }
16736
16737  skip:
16738   mnemonicendp = p;
16739   *p = '\0';
16740   OP_E (bytemode, sizeflag);
16741 }
16742
16743 static void
16744 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16745 {
16746   if (!vex.evex
16747       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16748     abort ();
16749
16750   USED_REX (REX_R);
16751   if ((rex & REX_R) != 0 || !vex.r)
16752     {
16753       BadOp ();
16754       return;
16755     }
16756
16757   oappend (names_mask [modrm.reg]);
16758 }
16759
16760 static void
16761 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16762 {
16763   if (modrm.mod == 3 && vex.b)
16764     switch (bytemode)
16765       {
16766       case evex_rounding_64_mode:
16767         if (address_mode != mode_64bit)
16768           {
16769             oappend ("(bad)");
16770             break;
16771           }
16772         /* Fall through.  */
16773       case evex_rounding_mode:
16774         oappend (names_rounding[vex.ll]);
16775         break;
16776       case evex_sae_mode:
16777         oappend ("{sae}");
16778         break;
16779       default:
16780         abort ();
16781         break;
16782       }
16783 }