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x86: fold duplicate code in MOVSXD_Fixup()
[binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2021 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43
44 static int print_insn (bfd_vma, disassemble_info *);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_MMX (int, int);
80 static void OP_XMM (int, int);
81 static void OP_EM (int, int);
82 static void OP_EX (int, int);
83 static void OP_EMC (int,int);
84 static void OP_MXC (int,int);
85 static void OP_MS (int, int);
86 static void OP_XS (int, int);
87 static void OP_M (int, int);
88 static void OP_VEX (int, int);
89 static void OP_VexR (int, int);
90 static void OP_VexW (int, int);
91 static void OP_Rounding (int, int);
92 static void OP_REG_VexI4 (int, int);
93 static void OP_VexI4 (int, int);
94 static void PCLMUL_Fixup (int, int);
95 static void VPCMP_Fixup (int, int);
96 static void VPCOM_Fixup (int, int);
97 static void OP_0f07 (int, int);
98 static void OP_Monitor (int, int);
99 static void OP_Mwait (int, int);
100 static void NOP_Fixup1 (int, int);
101 static void NOP_Fixup2 (int, int);
102 static void OP_3DNowSuffix (int, int);
103 static void CMP_Fixup (int, int);
104 static void BadOp (void);
105 static void REP_Fixup (int, int);
106 static void SEP_Fixup (int, int);
107 static void BND_Fixup (int, int);
108 static void NOTRACK_Fixup (int, int);
109 static void HLE_Fixup1 (int, int);
110 static void HLE_Fixup2 (int, int);
111 static void HLE_Fixup3 (int, int);
112 static void CMPXCHG8B_Fixup (int, int);
113 static void XMM_Fixup (int, int);
114 static void FXSAVE_Fixup (int, int);
115
116 static void MOVSXD_Fixup (int, int);
117
118 struct dis_private {
119 /* Points to first byte not fetched. */
120 bfd_byte *max_fetched;
121 bfd_byte the_buffer[MAX_MNEM_SIZE];
122 bfd_vma insn_start;
123 int orig_sizeflag;
124 OPCODES_SIGJMP_BUF bailout;
125 };
126
127 enum address_mode
128 {
129 mode_16bit,
130 mode_32bit,
131 mode_64bit
132 };
133
134 enum address_mode address_mode;
135
136 /* Flags for the prefixes for the current instruction. See below. */
137 static int prefixes;
138
139 /* REX prefix the current instruction. See below. */
140 static int rex;
141 /* Bits of REX we've already used. */
142 static int rex_used;
143 /* Mark parts used in the REX prefix. When we are testing for
144 empty prefix (for 8bit register REX extension), just mask it
145 out. Otherwise test for REX bit is excuse for existence of REX
146 only in case value is nonzero. */
147 #define USED_REX(value) \
148 { \
149 if (value) \
150 { \
151 if ((rex & value)) \
152 rex_used |= (value) | REX_OPCODE; \
153 } \
154 else \
155 rex_used |= REX_OPCODE; \
156 }
157
158 /* Flags for prefixes which we somehow handled when printing the
159 current instruction. */
160 static int used_prefixes;
161
162 /* Flags stored in PREFIXES. */
163 #define PREFIX_REPZ 1
164 #define PREFIX_REPNZ 2
165 #define PREFIX_LOCK 4
166 #define PREFIX_CS 8
167 #define PREFIX_SS 0x10
168 #define PREFIX_DS 0x20
169 #define PREFIX_ES 0x40
170 #define PREFIX_FS 0x80
171 #define PREFIX_GS 0x100
172 #define PREFIX_DATA 0x200
173 #define PREFIX_ADDR 0x400
174 #define PREFIX_FWAIT 0x800
175
176 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
177 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
178 on error. */
179 #define FETCH_DATA(info, addr) \
180 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
181 ? 1 : fetch_data ((info), (addr)))
182
183 static int
184 fetch_data (struct disassemble_info *info, bfd_byte *addr)
185 {
186 int status;
187 struct dis_private *priv = (struct dis_private *) info->private_data;
188 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
189
190 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
191 status = (*info->read_memory_func) (start,
192 priv->max_fetched,
193 addr - priv->max_fetched,
194 info);
195 else
196 status = -1;
197 if (status != 0)
198 {
199 /* If we did manage to read at least one byte, then
200 print_insn_i386 will do something sensible. Otherwise, print
201 an error. We do that here because this is where we know
202 STATUS. */
203 if (priv->max_fetched == priv->the_buffer)
204 (*info->memory_error_func) (status, start, info);
205 OPCODES_SIGLONGJMP (priv->bailout, 1);
206 }
207 else
208 priv->max_fetched = addr;
209 return 1;
210 }
211
212 /* Possible values for prefix requirement. */
213 #define PREFIX_IGNORED_SHIFT 16
214 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
215 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
216 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
217 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
219
220 /* Opcode prefixes. */
221 #define PREFIX_OPCODE (PREFIX_REPZ \
222 | PREFIX_REPNZ \
223 | PREFIX_DATA)
224
225 /* Prefixes ignored. */
226 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
227 | PREFIX_IGNORED_REPNZ \
228 | PREFIX_IGNORED_DATA)
229
230 #define XX { NULL, 0 }
231 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
232
233 #define Eb { OP_E, b_mode }
234 #define Ebnd { OP_E, bnd_mode }
235 #define EbS { OP_E, b_swap_mode }
236 #define EbndS { OP_E, bnd_swap_mode }
237 #define Ev { OP_E, v_mode }
238 #define Eva { OP_E, va_mode }
239 #define Ev_bnd { OP_E, v_bnd_mode }
240 #define EvS { OP_E, v_swap_mode }
241 #define Ed { OP_E, d_mode }
242 #define Edq { OP_E, dq_mode }
243 #define Edqw { OP_E, dqw_mode }
244 #define Edqb { OP_E, dqb_mode }
245 #define Edb { OP_E, db_mode }
246 #define Edw { OP_E, dw_mode }
247 #define Edqd { OP_E, dqd_mode }
248 #define Eq { OP_E, q_mode }
249 #define indirEv { OP_indirE, indir_v_mode }
250 #define indirEp { OP_indirE, f_mode }
251 #define stackEv { OP_E, stack_v_mode }
252 #define Em { OP_E, m_mode }
253 #define Ew { OP_E, w_mode }
254 #define M { OP_M, 0 } /* lea, lgdt, etc. */
255 #define Ma { OP_M, a_mode }
256 #define Mb { OP_M, b_mode }
257 #define Md { OP_M, d_mode }
258 #define Mo { OP_M, o_mode }
259 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
260 #define Mq { OP_M, q_mode }
261 #define Mv { OP_M, v_mode }
262 #define Mv_bnd { OP_M, v_bndmk_mode }
263 #define Mx { OP_M, x_mode }
264 #define Mxmm { OP_M, xmm_mode }
265 #define Gb { OP_G, b_mode }
266 #define Gbnd { OP_G, bnd_mode }
267 #define Gv { OP_G, v_mode }
268 #define Gd { OP_G, d_mode }
269 #define Gdq { OP_G, dq_mode }
270 #define Gm { OP_G, m_mode }
271 #define Gva { OP_G, va_mode }
272 #define Gw { OP_G, w_mode }
273 #define Ib { OP_I, b_mode }
274 #define sIb { OP_sI, b_mode } /* sign extened byte */
275 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
276 #define Iv { OP_I, v_mode }
277 #define sIv { OP_sI, v_mode }
278 #define Iv64 { OP_I64, v_mode }
279 #define Id { OP_I, d_mode }
280 #define Iw { OP_I, w_mode }
281 #define I1 { OP_I, const_1_mode }
282 #define Jb { OP_J, b_mode }
283 #define Jv { OP_J, v_mode }
284 #define Jdqw { OP_J, dqw_mode }
285 #define Cm { OP_C, m_mode }
286 #define Dm { OP_D, m_mode }
287 #define Td { OP_T, d_mode }
288 #define Skip_MODRM { OP_Skip_MODRM, 0 }
289
290 #define RMeAX { OP_REG, eAX_reg }
291 #define RMeBX { OP_REG, eBX_reg }
292 #define RMeCX { OP_REG, eCX_reg }
293 #define RMeDX { OP_REG, eDX_reg }
294 #define RMeSP { OP_REG, eSP_reg }
295 #define RMeBP { OP_REG, eBP_reg }
296 #define RMeSI { OP_REG, eSI_reg }
297 #define RMeDI { OP_REG, eDI_reg }
298 #define RMrAX { OP_REG, rAX_reg }
299 #define RMrBX { OP_REG, rBX_reg }
300 #define RMrCX { OP_REG, rCX_reg }
301 #define RMrDX { OP_REG, rDX_reg }
302 #define RMrSP { OP_REG, rSP_reg }
303 #define RMrBP { OP_REG, rBP_reg }
304 #define RMrSI { OP_REG, rSI_reg }
305 #define RMrDI { OP_REG, rDI_reg }
306 #define RMAL { OP_REG, al_reg }
307 #define RMCL { OP_REG, cl_reg }
308 #define RMDL { OP_REG, dl_reg }
309 #define RMBL { OP_REG, bl_reg }
310 #define RMAH { OP_REG, ah_reg }
311 #define RMCH { OP_REG, ch_reg }
312 #define RMDH { OP_REG, dh_reg }
313 #define RMBH { OP_REG, bh_reg }
314 #define RMAX { OP_REG, ax_reg }
315 #define RMDX { OP_REG, dx_reg }
316
317 #define eAX { OP_IMREG, eAX_reg }
318 #define AL { OP_IMREG, al_reg }
319 #define CL { OP_IMREG, cl_reg }
320 #define zAX { OP_IMREG, z_mode_ax_reg }
321 #define indirDX { OP_IMREG, indir_dx_reg }
322
323 #define Sw { OP_SEG, w_mode }
324 #define Sv { OP_SEG, v_mode }
325 #define Ap { OP_DIR, 0 }
326 #define Ob { OP_OFF64, b_mode }
327 #define Ov { OP_OFF64, v_mode }
328 #define Xb { OP_DSreg, eSI_reg }
329 #define Xv { OP_DSreg, eSI_reg }
330 #define Xz { OP_DSreg, eSI_reg }
331 #define Yb { OP_ESreg, eDI_reg }
332 #define Yv { OP_ESreg, eDI_reg }
333 #define DSBX { OP_DSreg, eBX_reg }
334
335 #define es { OP_REG, es_reg }
336 #define ss { OP_REG, ss_reg }
337 #define cs { OP_REG, cs_reg }
338 #define ds { OP_REG, ds_reg }
339 #define fs { OP_REG, fs_reg }
340 #define gs { OP_REG, gs_reg }
341
342 #define MX { OP_MMX, 0 }
343 #define XM { OP_XMM, 0 }
344 #define XMScalar { OP_XMM, scalar_mode }
345 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
346 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
347 #define XMM { OP_XMM, xmm_mode }
348 #define TMM { OP_XMM, tmm_mode }
349 #define XMxmmq { OP_XMM, xmmq_mode }
350 #define EM { OP_EM, v_mode }
351 #define EMS { OP_EM, v_swap_mode }
352 #define EMd { OP_EM, d_mode }
353 #define EMx { OP_EM, x_mode }
354 #define EXbwUnit { OP_EX, bw_unit_mode }
355 #define EXw { OP_EX, w_mode }
356 #define EXd { OP_EX, d_mode }
357 #define EXdS { OP_EX, d_swap_mode }
358 #define EXq { OP_EX, q_mode }
359 #define EXqS { OP_EX, q_swap_mode }
360 #define EXx { OP_EX, x_mode }
361 #define EXxS { OP_EX, x_swap_mode }
362 #define EXxmm { OP_EX, xmm_mode }
363 #define EXymm { OP_EX, ymm_mode }
364 #define EXtmm { OP_EX, tmm_mode }
365 #define EXxmmq { OP_EX, xmmq_mode }
366 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
367 #define EXxmm_mb { OP_EX, xmm_mb_mode }
368 #define EXxmm_mw { OP_EX, xmm_mw_mode }
369 #define EXxmm_md { OP_EX, xmm_md_mode }
370 #define EXxmm_mq { OP_EX, xmm_mq_mode }
371 #define EXxmmdw { OP_EX, xmmdw_mode }
372 #define EXxmmqd { OP_EX, xmmqd_mode }
373 #define EXymmq { OP_EX, ymmq_mode }
374 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
375 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
376 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
377 #define MS { OP_MS, v_mode }
378 #define XS { OP_XS, v_mode }
379 #define EMCq { OP_EMC, q_mode }
380 #define MXC { OP_MXC, 0 }
381 #define OPSUF { OP_3DNowSuffix, 0 }
382 #define SEP { SEP_Fixup, 0 }
383 #define CMP { CMP_Fixup, 0 }
384 #define XMM0 { XMM_Fixup, 0 }
385 #define FXSAVE { FXSAVE_Fixup, 0 }
386
387 #define Vex { OP_VEX, vex_mode }
388 #define VexW { OP_VexW, vex_mode }
389 #define VexScalar { OP_VEX, vex_scalar_mode }
390 #define VexScalarR { OP_VexR, vex_scalar_mode }
391 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
392 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
393 #define VexGdq { OP_VEX, dq_mode }
394 #define VexTmm { OP_VEX, tmm_mode }
395 #define XMVexI4 { OP_REG_VexI4, x_mode }
396 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
397 #define VexI4 { OP_VexI4, 0 }
398 #define PCLMUL { PCLMUL_Fixup, 0 }
399 #define VPCMP { VPCMP_Fixup, 0 }
400 #define VPCOM { VPCOM_Fixup, 0 }
401
402 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
403 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
404 #define EXxEVexS { OP_Rounding, evex_sae_mode }
405
406 #define MaskG { OP_G, mask_mode }
407 #define MaskE { OP_E, mask_mode }
408 #define MaskBDE { OP_E, mask_bd_mode }
409 #define MaskVex { OP_VEX, mask_mode }
410
411 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
412 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
413
414 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
415
416 /* Used handle "rep" prefix for string instructions. */
417 #define Xbr { REP_Fixup, eSI_reg }
418 #define Xvr { REP_Fixup, eSI_reg }
419 #define Ybr { REP_Fixup, eDI_reg }
420 #define Yvr { REP_Fixup, eDI_reg }
421 #define Yzr { REP_Fixup, eDI_reg }
422 #define indirDXr { REP_Fixup, indir_dx_reg }
423 #define ALr { REP_Fixup, al_reg }
424 #define eAXr { REP_Fixup, eAX_reg }
425
426 /* Used handle HLE prefix for lockable instructions. */
427 #define Ebh1 { HLE_Fixup1, b_mode }
428 #define Evh1 { HLE_Fixup1, v_mode }
429 #define Ebh2 { HLE_Fixup2, b_mode }
430 #define Evh2 { HLE_Fixup2, v_mode }
431 #define Ebh3 { HLE_Fixup3, b_mode }
432 #define Evh3 { HLE_Fixup3, v_mode }
433
434 #define BND { BND_Fixup, 0 }
435 #define NOTRACK { NOTRACK_Fixup, 0 }
436
437 #define cond_jump_flag { NULL, cond_jump_mode }
438 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
439
440 /* bits in sizeflag */
441 #define SUFFIX_ALWAYS 4
442 #define AFLAG 2
443 #define DFLAG 1
444
445 enum
446 {
447 /* byte operand */
448 b_mode = 1,
449 /* byte operand with operand swapped */
450 b_swap_mode,
451 /* byte operand, sign extend like 'T' suffix */
452 b_T_mode,
453 /* operand size depends on prefixes */
454 v_mode,
455 /* operand size depends on prefixes with operand swapped */
456 v_swap_mode,
457 /* operand size depends on address prefix */
458 va_mode,
459 /* word operand */
460 w_mode,
461 /* double word operand */
462 d_mode,
463 /* double word operand with operand swapped */
464 d_swap_mode,
465 /* quad word operand */
466 q_mode,
467 /* quad word operand with operand swapped */
468 q_swap_mode,
469 /* ten-byte operand */
470 t_mode,
471 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
472 broadcast enabled. */
473 x_mode,
474 /* Similar to x_mode, but with different EVEX mem shifts. */
475 evex_x_gscat_mode,
476 /* Similar to x_mode, but with yet different EVEX mem shifts. */
477 bw_unit_mode,
478 /* Similar to x_mode, but with disabled broadcast. */
479 evex_x_nobcst_mode,
480 /* Similar to x_mode, but with operands swapped and disabled broadcast
481 in EVEX. */
482 x_swap_mode,
483 /* 16-byte XMM operand */
484 xmm_mode,
485 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
486 memory operand (depending on vector length). Broadcast isn't
487 allowed. */
488 xmmq_mode,
489 /* Same as xmmq_mode, but broadcast is allowed. */
490 evex_half_bcst_xmmq_mode,
491 /* XMM register or byte memory operand */
492 xmm_mb_mode,
493 /* XMM register or word memory operand */
494 xmm_mw_mode,
495 /* XMM register or double word memory operand */
496 xmm_md_mode,
497 /* XMM register or quad word memory operand */
498 xmm_mq_mode,
499 /* 16-byte XMM, word, double word or quad word operand. */
500 xmmdw_mode,
501 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
502 xmmqd_mode,
503 /* 32-byte YMM operand */
504 ymm_mode,
505 /* quad word, ymmword or zmmword memory operand. */
506 ymmq_mode,
507 /* 32-byte YMM or 16-byte word operand */
508 ymmxmm_mode,
509 /* TMM operand */
510 tmm_mode,
511 /* d_mode in 32bit, q_mode in 64bit mode. */
512 m_mode,
513 /* pair of v_mode operands */
514 a_mode,
515 cond_jump_mode,
516 loop_jcxz_mode,
517 movsxd_mode,
518 v_bnd_mode,
519 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
520 v_bndmk_mode,
521 /* operand size depends on REX prefixes. */
522 dq_mode,
523 /* registers like dq_mode, memory like w_mode, displacements like
524 v_mode without considering Intel64 ISA. */
525 dqw_mode,
526 /* bounds operand */
527 bnd_mode,
528 /* bounds operand with operand swapped */
529 bnd_swap_mode,
530 /* 4- or 6-byte pointer operand */
531 f_mode,
532 const_1_mode,
533 /* v_mode for indirect branch opcodes. */
534 indir_v_mode,
535 /* v_mode for stack-related opcodes. */
536 stack_v_mode,
537 /* non-quad operand size depends on prefixes */
538 z_mode,
539 /* 16-byte operand */
540 o_mode,
541 /* registers like dq_mode, memory like b_mode. */
542 dqb_mode,
543 /* registers like d_mode, memory like b_mode. */
544 db_mode,
545 /* registers like d_mode, memory like w_mode. */
546 dw_mode,
547 /* registers like dq_mode, memory like d_mode. */
548 dqd_mode,
549 /* normal vex mode */
550 vex_mode,
551
552 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
553 vex_vsib_d_w_dq_mode,
554 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
555 vex_vsib_q_w_dq_mode,
556 /* mandatory non-vector SIB. */
557 vex_sibmem_mode,
558
559 /* scalar, ignore vector length. */
560 scalar_mode,
561 /* like vex_mode, ignore vector length. */
562 vex_scalar_mode,
563 /* Operand size depends on the VEX.W bit, ignore vector length. */
564 vex_scalar_w_dq_mode,
565
566 /* Static rounding. */
567 evex_rounding_mode,
568 /* Static rounding, 64-bit mode only. */
569 evex_rounding_64_mode,
570 /* Supress all exceptions. */
571 evex_sae_mode,
572
573 /* Mask register operand. */
574 mask_mode,
575 /* Mask register operand. */
576 mask_bd_mode,
577
578 es_reg,
579 cs_reg,
580 ss_reg,
581 ds_reg,
582 fs_reg,
583 gs_reg,
584
585 eAX_reg,
586 eCX_reg,
587 eDX_reg,
588 eBX_reg,
589 eSP_reg,
590 eBP_reg,
591 eSI_reg,
592 eDI_reg,
593
594 al_reg,
595 cl_reg,
596 dl_reg,
597 bl_reg,
598 ah_reg,
599 ch_reg,
600 dh_reg,
601 bh_reg,
602
603 ax_reg,
604 cx_reg,
605 dx_reg,
606 bx_reg,
607 sp_reg,
608 bp_reg,
609 si_reg,
610 di_reg,
611
612 rAX_reg,
613 rCX_reg,
614 rDX_reg,
615 rBX_reg,
616 rSP_reg,
617 rBP_reg,
618 rSI_reg,
619 rDI_reg,
620
621 z_mode_ax_reg,
622 indir_dx_reg
623 };
624
625 enum
626 {
627 FLOATCODE = 1,
628 USE_REG_TABLE,
629 USE_MOD_TABLE,
630 USE_RM_TABLE,
631 USE_PREFIX_TABLE,
632 USE_X86_64_TABLE,
633 USE_3BYTE_TABLE,
634 USE_XOP_8F_TABLE,
635 USE_VEX_C4_TABLE,
636 USE_VEX_C5_TABLE,
637 USE_VEX_LEN_TABLE,
638 USE_VEX_W_TABLE,
639 USE_EVEX_TABLE,
640 USE_EVEX_LEN_TABLE
641 };
642
643 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
644
645 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
646 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
647 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
648 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
649 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
650 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
651 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
652 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
653 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
654 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
655 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
656 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
657 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
658 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
659 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
660 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
661
662 enum
663 {
664 REG_80 = 0,
665 REG_81,
666 REG_83,
667 REG_8F,
668 REG_C0,
669 REG_C1,
670 REG_C6,
671 REG_C7,
672 REG_D0,
673 REG_D1,
674 REG_D2,
675 REG_D3,
676 REG_F6,
677 REG_F7,
678 REG_FE,
679 REG_FF,
680 REG_0F00,
681 REG_0F01,
682 REG_0F0D,
683 REG_0F18,
684 REG_0F1C_P_0_MOD_0,
685 REG_0F1E_P_1_MOD_3,
686 REG_0F38D8_PREFIX_1,
687 REG_0F3A0F_PREFIX_1_MOD_3,
688 REG_0F71_MOD_0,
689 REG_0F72_MOD_0,
690 REG_0F73_MOD_0,
691 REG_0FA6,
692 REG_0FA7,
693 REG_0FAE,
694 REG_0FBA,
695 REG_0FC7,
696 REG_VEX_0F71_M_0,
697 REG_VEX_0F72_M_0,
698 REG_VEX_0F73_M_0,
699 REG_VEX_0FAE,
700 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
701 REG_VEX_0F38F3_L_0,
702
703 REG_XOP_09_01_L_0,
704 REG_XOP_09_02_L_0,
705 REG_XOP_09_12_M_1_L_0,
706 REG_XOP_0A_12_L_0,
707
708 REG_EVEX_0F71,
709 REG_EVEX_0F72,
710 REG_EVEX_0F73,
711 REG_EVEX_0F38C6_M_0_L_2,
712 REG_EVEX_0F38C7_M_0_L_2
713 };
714
715 enum
716 {
717 MOD_62_32BIT = 0,
718 MOD_8D,
719 MOD_C4_32BIT,
720 MOD_C5_32BIT,
721 MOD_C6_REG_7,
722 MOD_C7_REG_7,
723 MOD_FF_REG_3,
724 MOD_FF_REG_5,
725 MOD_0F01_REG_0,
726 MOD_0F01_REG_1,
727 MOD_0F01_REG_2,
728 MOD_0F01_REG_3,
729 MOD_0F01_REG_5,
730 MOD_0F01_REG_7,
731 MOD_0F12_PREFIX_0,
732 MOD_0F12_PREFIX_2,
733 MOD_0F13,
734 MOD_0F16_PREFIX_0,
735 MOD_0F16_PREFIX_2,
736 MOD_0F17,
737 MOD_0F18_REG_0,
738 MOD_0F18_REG_1,
739 MOD_0F18_REG_2,
740 MOD_0F18_REG_3,
741 MOD_0F1A_PREFIX_0,
742 MOD_0F1B_PREFIX_0,
743 MOD_0F1B_PREFIX_1,
744 MOD_0F1C_PREFIX_0,
745 MOD_0F1E_PREFIX_1,
746 MOD_0F2B_PREFIX_0,
747 MOD_0F2B_PREFIX_1,
748 MOD_0F2B_PREFIX_2,
749 MOD_0F2B_PREFIX_3,
750 MOD_0F50,
751 MOD_0F71,
752 MOD_0F72,
753 MOD_0F73,
754 MOD_0FAE_REG_0,
755 MOD_0FAE_REG_1,
756 MOD_0FAE_REG_2,
757 MOD_0FAE_REG_3,
758 MOD_0FAE_REG_4,
759 MOD_0FAE_REG_5,
760 MOD_0FAE_REG_6,
761 MOD_0FAE_REG_7,
762 MOD_0FB2,
763 MOD_0FB4,
764 MOD_0FB5,
765 MOD_0FC3,
766 MOD_0FC7_REG_3,
767 MOD_0FC7_REG_4,
768 MOD_0FC7_REG_5,
769 MOD_0FC7_REG_6,
770 MOD_0FC7_REG_7,
771 MOD_0FD7,
772 MOD_0FE7_PREFIX_2,
773 MOD_0FF0_PREFIX_3,
774 MOD_0F382A,
775 MOD_0F38DC_PREFIX_1,
776 MOD_0F38DD_PREFIX_1,
777 MOD_0F38DE_PREFIX_1,
778 MOD_0F38DF_PREFIX_1,
779 MOD_0F38F5,
780 MOD_0F38F6_PREFIX_0,
781 MOD_0F38F8_PREFIX_1,
782 MOD_0F38F8_PREFIX_2,
783 MOD_0F38F8_PREFIX_3,
784 MOD_0F38F9,
785 MOD_0F38FA_PREFIX_1,
786 MOD_0F38FB_PREFIX_1,
787 MOD_0F3A0F_PREFIX_1,
788
789 MOD_VEX_0F12_PREFIX_0,
790 MOD_VEX_0F12_PREFIX_2,
791 MOD_VEX_0F13,
792 MOD_VEX_0F16_PREFIX_0,
793 MOD_VEX_0F16_PREFIX_2,
794 MOD_VEX_0F17,
795 MOD_VEX_0F2B,
796 MOD_VEX_0F41_L_1,
797 MOD_VEX_0F42_L_1,
798 MOD_VEX_0F44_L_0,
799 MOD_VEX_0F45_L_1,
800 MOD_VEX_0F46_L_1,
801 MOD_VEX_0F47_L_1,
802 MOD_VEX_0F4A_L_1,
803 MOD_VEX_0F4B_L_1,
804 MOD_VEX_0F50,
805 MOD_VEX_0F71,
806 MOD_VEX_0F72,
807 MOD_VEX_0F73,
808 MOD_VEX_0F91_L_0,
809 MOD_VEX_0F92_L_0,
810 MOD_VEX_0F93_L_0,
811 MOD_VEX_0F98_L_0,
812 MOD_VEX_0F99_L_0,
813 MOD_VEX_0FAE_REG_2,
814 MOD_VEX_0FAE_REG_3,
815 MOD_VEX_0FD7,
816 MOD_VEX_0FE7,
817 MOD_VEX_0FF0_PREFIX_3,
818 MOD_VEX_0F381A,
819 MOD_VEX_0F382A,
820 MOD_VEX_0F382C,
821 MOD_VEX_0F382D,
822 MOD_VEX_0F382E,
823 MOD_VEX_0F382F,
824 MOD_VEX_0F3849_X86_64_P_0_W_0,
825 MOD_VEX_0F3849_X86_64_P_2_W_0,
826 MOD_VEX_0F3849_X86_64_P_3_W_0,
827 MOD_VEX_0F384B_X86_64_P_1_W_0,
828 MOD_VEX_0F384B_X86_64_P_2_W_0,
829 MOD_VEX_0F384B_X86_64_P_3_W_0,
830 MOD_VEX_0F385A,
831 MOD_VEX_0F385C_X86_64_P_1_W_0,
832 MOD_VEX_0F385E_X86_64_P_0_W_0,
833 MOD_VEX_0F385E_X86_64_P_1_W_0,
834 MOD_VEX_0F385E_X86_64_P_2_W_0,
835 MOD_VEX_0F385E_X86_64_P_3_W_0,
836 MOD_VEX_0F388C,
837 MOD_VEX_0F388E,
838 MOD_VEX_0F3A30_L_0,
839 MOD_VEX_0F3A31_L_0,
840 MOD_VEX_0F3A32_L_0,
841 MOD_VEX_0F3A33_L_0,
842
843 MOD_XOP_09_12,
844
845 MOD_EVEX_0F12_PREFIX_0,
846 MOD_EVEX_0F12_PREFIX_2,
847 MOD_EVEX_0F13,
848 MOD_EVEX_0F16_PREFIX_0,
849 MOD_EVEX_0F16_PREFIX_2,
850 MOD_EVEX_0F17,
851 MOD_EVEX_0F2B,
852 MOD_EVEX_0F381A,
853 MOD_EVEX_0F381B,
854 MOD_EVEX_0F3828_P_1,
855 MOD_EVEX_0F382A_P_1_W_1,
856 MOD_EVEX_0F3838_P_1,
857 MOD_EVEX_0F383A_P_1_W_0,
858 MOD_EVEX_0F385A,
859 MOD_EVEX_0F385B,
860 MOD_EVEX_0F387A_W_0,
861 MOD_EVEX_0F387B_W_0,
862 MOD_EVEX_0F387C,
863 MOD_EVEX_0F38C6,
864 MOD_EVEX_0F38C7
865 };
866
867 enum
868 {
869 RM_C6_REG_7 = 0,
870 RM_C7_REG_7,
871 RM_0F01_REG_0,
872 RM_0F01_REG_1,
873 RM_0F01_REG_2,
874 RM_0F01_REG_3,
875 RM_0F01_REG_5_MOD_3,
876 RM_0F01_REG_7_MOD_3,
877 RM_0F1E_P_1_MOD_3_REG_7,
878 RM_0FAE_REG_6_MOD_3_P_0,
879 RM_0FAE_REG_7_MOD_3,
880 RM_0F3A0F_P_1_MOD_3_REG_0,
881
882 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
883 };
884
885 enum
886 {
887 PREFIX_90 = 0,
888 PREFIX_0F01_REG_1_RM_4,
889 PREFIX_0F01_REG_1_RM_5,
890 PREFIX_0F01_REG_1_RM_6,
891 PREFIX_0F01_REG_1_RM_7,
892 PREFIX_0F01_REG_3_RM_1,
893 PREFIX_0F01_REG_5_MOD_0,
894 PREFIX_0F01_REG_5_MOD_3_RM_0,
895 PREFIX_0F01_REG_5_MOD_3_RM_1,
896 PREFIX_0F01_REG_5_MOD_3_RM_2,
897 PREFIX_0F01_REG_5_MOD_3_RM_4,
898 PREFIX_0F01_REG_5_MOD_3_RM_5,
899 PREFIX_0F01_REG_5_MOD_3_RM_6,
900 PREFIX_0F01_REG_5_MOD_3_RM_7,
901 PREFIX_0F01_REG_7_MOD_3_RM_2,
902 PREFIX_0F01_REG_7_MOD_3_RM_6,
903 PREFIX_0F01_REG_7_MOD_3_RM_7,
904 PREFIX_0F09,
905 PREFIX_0F10,
906 PREFIX_0F11,
907 PREFIX_0F12,
908 PREFIX_0F16,
909 PREFIX_0F1A,
910 PREFIX_0F1B,
911 PREFIX_0F1C,
912 PREFIX_0F1E,
913 PREFIX_0F2A,
914 PREFIX_0F2B,
915 PREFIX_0F2C,
916 PREFIX_0F2D,
917 PREFIX_0F2E,
918 PREFIX_0F2F,
919 PREFIX_0F51,
920 PREFIX_0F52,
921 PREFIX_0F53,
922 PREFIX_0F58,
923 PREFIX_0F59,
924 PREFIX_0F5A,
925 PREFIX_0F5B,
926 PREFIX_0F5C,
927 PREFIX_0F5D,
928 PREFIX_0F5E,
929 PREFIX_0F5F,
930 PREFIX_0F60,
931 PREFIX_0F61,
932 PREFIX_0F62,
933 PREFIX_0F6F,
934 PREFIX_0F70,
935 PREFIX_0F78,
936 PREFIX_0F79,
937 PREFIX_0F7C,
938 PREFIX_0F7D,
939 PREFIX_0F7E,
940 PREFIX_0F7F,
941 PREFIX_0FAE_REG_0_MOD_3,
942 PREFIX_0FAE_REG_1_MOD_3,
943 PREFIX_0FAE_REG_2_MOD_3,
944 PREFIX_0FAE_REG_3_MOD_3,
945 PREFIX_0FAE_REG_4_MOD_0,
946 PREFIX_0FAE_REG_4_MOD_3,
947 PREFIX_0FAE_REG_5_MOD_3,
948 PREFIX_0FAE_REG_6_MOD_0,
949 PREFIX_0FAE_REG_6_MOD_3,
950 PREFIX_0FAE_REG_7_MOD_0,
951 PREFIX_0FB8,
952 PREFIX_0FBC,
953 PREFIX_0FBD,
954 PREFIX_0FC2,
955 PREFIX_0FC7_REG_6_MOD_0,
956 PREFIX_0FC7_REG_6_MOD_3,
957 PREFIX_0FC7_REG_7_MOD_3,
958 PREFIX_0FD0,
959 PREFIX_0FD6,
960 PREFIX_0FE6,
961 PREFIX_0FE7,
962 PREFIX_0FF0,
963 PREFIX_0FF7,
964 PREFIX_0F38D8,
965 PREFIX_0F38DC,
966 PREFIX_0F38DD,
967 PREFIX_0F38DE,
968 PREFIX_0F38DF,
969 PREFIX_0F38F0,
970 PREFIX_0F38F1,
971 PREFIX_0F38F6,
972 PREFIX_0F38F8,
973 PREFIX_0F38FA,
974 PREFIX_0F38FB,
975 PREFIX_0F3A0F,
976 PREFIX_VEX_0F10,
977 PREFIX_VEX_0F11,
978 PREFIX_VEX_0F12,
979 PREFIX_VEX_0F16,
980 PREFIX_VEX_0F2A,
981 PREFIX_VEX_0F2C,
982 PREFIX_VEX_0F2D,
983 PREFIX_VEX_0F2E,
984 PREFIX_VEX_0F2F,
985 PREFIX_VEX_0F41_L_1_M_1_W_0,
986 PREFIX_VEX_0F41_L_1_M_1_W_1,
987 PREFIX_VEX_0F42_L_1_M_1_W_0,
988 PREFIX_VEX_0F42_L_1_M_1_W_1,
989 PREFIX_VEX_0F44_L_0_M_1_W_0,
990 PREFIX_VEX_0F44_L_0_M_1_W_1,
991 PREFIX_VEX_0F45_L_1_M_1_W_0,
992 PREFIX_VEX_0F45_L_1_M_1_W_1,
993 PREFIX_VEX_0F46_L_1_M_1_W_0,
994 PREFIX_VEX_0F46_L_1_M_1_W_1,
995 PREFIX_VEX_0F47_L_1_M_1_W_0,
996 PREFIX_VEX_0F47_L_1_M_1_W_1,
997 PREFIX_VEX_0F4A_L_1_M_1_W_0,
998 PREFIX_VEX_0F4A_L_1_M_1_W_1,
999 PREFIX_VEX_0F4B_L_1_M_1_W_0,
1000 PREFIX_VEX_0F4B_L_1_M_1_W_1,
1001 PREFIX_VEX_0F51,
1002 PREFIX_VEX_0F52,
1003 PREFIX_VEX_0F53,
1004 PREFIX_VEX_0F58,
1005 PREFIX_VEX_0F59,
1006 PREFIX_VEX_0F5A,
1007 PREFIX_VEX_0F5B,
1008 PREFIX_VEX_0F5C,
1009 PREFIX_VEX_0F5D,
1010 PREFIX_VEX_0F5E,
1011 PREFIX_VEX_0F5F,
1012 PREFIX_VEX_0F6F,
1013 PREFIX_VEX_0F70,
1014 PREFIX_VEX_0F7C,
1015 PREFIX_VEX_0F7D,
1016 PREFIX_VEX_0F7E,
1017 PREFIX_VEX_0F7F,
1018 PREFIX_VEX_0F90_L_0_W_0,
1019 PREFIX_VEX_0F90_L_0_W_1,
1020 PREFIX_VEX_0F91_L_0_M_0_W_0,
1021 PREFIX_VEX_0F91_L_0_M_0_W_1,
1022 PREFIX_VEX_0F92_L_0_M_1_W_0,
1023 PREFIX_VEX_0F92_L_0_M_1_W_1,
1024 PREFIX_VEX_0F93_L_0_M_1_W_0,
1025 PREFIX_VEX_0F93_L_0_M_1_W_1,
1026 PREFIX_VEX_0F98_L_0_M_1_W_0,
1027 PREFIX_VEX_0F98_L_0_M_1_W_1,
1028 PREFIX_VEX_0F99_L_0_M_1_W_0,
1029 PREFIX_VEX_0F99_L_0_M_1_W_1,
1030 PREFIX_VEX_0FC2,
1031 PREFIX_VEX_0FD0,
1032 PREFIX_VEX_0FE6,
1033 PREFIX_VEX_0FF0,
1034 PREFIX_VEX_0F3849_X86_64,
1035 PREFIX_VEX_0F384B_X86_64,
1036 PREFIX_VEX_0F385C_X86_64,
1037 PREFIX_VEX_0F385E_X86_64,
1038 PREFIX_VEX_0F38F5_L_0,
1039 PREFIX_VEX_0F38F6_L_0,
1040 PREFIX_VEX_0F38F7_L_0,
1041 PREFIX_VEX_0F3AF0_L_0,
1042
1043 PREFIX_EVEX_0F10,
1044 PREFIX_EVEX_0F11,
1045 PREFIX_EVEX_0F12,
1046 PREFIX_EVEX_0F16,
1047 PREFIX_EVEX_0F2A,
1048 PREFIX_EVEX_0F51,
1049 PREFIX_EVEX_0F58,
1050 PREFIX_EVEX_0F59,
1051 PREFIX_EVEX_0F5A,
1052 PREFIX_EVEX_0F5B,
1053 PREFIX_EVEX_0F5C,
1054 PREFIX_EVEX_0F5D,
1055 PREFIX_EVEX_0F5E,
1056 PREFIX_EVEX_0F5F,
1057 PREFIX_EVEX_0F6F,
1058 PREFIX_EVEX_0F70,
1059 PREFIX_EVEX_0F78,
1060 PREFIX_EVEX_0F79,
1061 PREFIX_EVEX_0F7A,
1062 PREFIX_EVEX_0F7B,
1063 PREFIX_EVEX_0F7E,
1064 PREFIX_EVEX_0F7F,
1065 PREFIX_EVEX_0FC2,
1066 PREFIX_EVEX_0FE6,
1067 PREFIX_EVEX_0F3810,
1068 PREFIX_EVEX_0F3811,
1069 PREFIX_EVEX_0F3812,
1070 PREFIX_EVEX_0F3813,
1071 PREFIX_EVEX_0F3814,
1072 PREFIX_EVEX_0F3815,
1073 PREFIX_EVEX_0F3820,
1074 PREFIX_EVEX_0F3821,
1075 PREFIX_EVEX_0F3822,
1076 PREFIX_EVEX_0F3823,
1077 PREFIX_EVEX_0F3824,
1078 PREFIX_EVEX_0F3825,
1079 PREFIX_EVEX_0F3826,
1080 PREFIX_EVEX_0F3827,
1081 PREFIX_EVEX_0F3828,
1082 PREFIX_EVEX_0F3829,
1083 PREFIX_EVEX_0F382A,
1084 PREFIX_EVEX_0F3830,
1085 PREFIX_EVEX_0F3831,
1086 PREFIX_EVEX_0F3832,
1087 PREFIX_EVEX_0F3833,
1088 PREFIX_EVEX_0F3834,
1089 PREFIX_EVEX_0F3835,
1090 PREFIX_EVEX_0F3838,
1091 PREFIX_EVEX_0F3839,
1092 PREFIX_EVEX_0F383A,
1093 PREFIX_EVEX_0F3852,
1094 PREFIX_EVEX_0F3853,
1095 PREFIX_EVEX_0F3868,
1096 PREFIX_EVEX_0F3872,
1097 PREFIX_EVEX_0F389A,
1098 PREFIX_EVEX_0F389B,
1099 PREFIX_EVEX_0F38AA,
1100 PREFIX_EVEX_0F38AB,
1101 };
1102
1103 enum
1104 {
1105 X86_64_06 = 0,
1106 X86_64_07,
1107 X86_64_0E,
1108 X86_64_16,
1109 X86_64_17,
1110 X86_64_1E,
1111 X86_64_1F,
1112 X86_64_27,
1113 X86_64_2F,
1114 X86_64_37,
1115 X86_64_3F,
1116 X86_64_60,
1117 X86_64_61,
1118 X86_64_62,
1119 X86_64_63,
1120 X86_64_6D,
1121 X86_64_6F,
1122 X86_64_82,
1123 X86_64_9A,
1124 X86_64_C2,
1125 X86_64_C3,
1126 X86_64_C4,
1127 X86_64_C5,
1128 X86_64_CE,
1129 X86_64_D4,
1130 X86_64_D5,
1131 X86_64_E8,
1132 X86_64_E9,
1133 X86_64_EA,
1134 X86_64_0F01_REG_0,
1135 X86_64_0F01_REG_1,
1136 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1137 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1138 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1139 X86_64_0F01_REG_2,
1140 X86_64_0F01_REG_3,
1141 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1142 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1143 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1144 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1145 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1146 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1147 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1148 X86_64_0F24,
1149 X86_64_0F26,
1150 X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1151
1152 X86_64_VEX_0F3849,
1153 X86_64_VEX_0F384B,
1154 X86_64_VEX_0F385C,
1155 X86_64_VEX_0F385E
1156 };
1157
1158 enum
1159 {
1160 THREE_BYTE_0F38 = 0,
1161 THREE_BYTE_0F3A
1162 };
1163
1164 enum
1165 {
1166 XOP_08 = 0,
1167 XOP_09,
1168 XOP_0A
1169 };
1170
1171 enum
1172 {
1173 VEX_0F = 0,
1174 VEX_0F38,
1175 VEX_0F3A
1176 };
1177
1178 enum
1179 {
1180 EVEX_0F = 0,
1181 EVEX_0F38,
1182 EVEX_0F3A
1183 };
1184
1185 enum
1186 {
1187 VEX_LEN_0F12_P_0_M_0 = 0,
1188 VEX_LEN_0F12_P_0_M_1,
1189 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1190 VEX_LEN_0F13_M_0,
1191 VEX_LEN_0F16_P_0_M_0,
1192 VEX_LEN_0F16_P_0_M_1,
1193 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1194 VEX_LEN_0F17_M_0,
1195 VEX_LEN_0F41,
1196 VEX_LEN_0F42,
1197 VEX_LEN_0F44,
1198 VEX_LEN_0F45,
1199 VEX_LEN_0F46,
1200 VEX_LEN_0F47,
1201 VEX_LEN_0F4A,
1202 VEX_LEN_0F4B,
1203 VEX_LEN_0F6E,
1204 VEX_LEN_0F77,
1205 VEX_LEN_0F7E_P_1,
1206 VEX_LEN_0F7E_P_2,
1207 VEX_LEN_0F90,
1208 VEX_LEN_0F91,
1209 VEX_LEN_0F92,
1210 VEX_LEN_0F93,
1211 VEX_LEN_0F98,
1212 VEX_LEN_0F99,
1213 VEX_LEN_0FAE_R_2_M_0,
1214 VEX_LEN_0FAE_R_3_M_0,
1215 VEX_LEN_0FC4,
1216 VEX_LEN_0FC5,
1217 VEX_LEN_0FD6,
1218 VEX_LEN_0FF7,
1219 VEX_LEN_0F3816,
1220 VEX_LEN_0F3819,
1221 VEX_LEN_0F381A_M_0,
1222 VEX_LEN_0F3836,
1223 VEX_LEN_0F3841,
1224 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1225 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1226 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1227 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1228 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1229 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1230 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1231 VEX_LEN_0F385A_M_0,
1232 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1233 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1234 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1235 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1236 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1237 VEX_LEN_0F38DB,
1238 VEX_LEN_0F38F2,
1239 VEX_LEN_0F38F3,
1240 VEX_LEN_0F38F5,
1241 VEX_LEN_0F38F6,
1242 VEX_LEN_0F38F7,
1243 VEX_LEN_0F3A00,
1244 VEX_LEN_0F3A01,
1245 VEX_LEN_0F3A06,
1246 VEX_LEN_0F3A14,
1247 VEX_LEN_0F3A15,
1248 VEX_LEN_0F3A16,
1249 VEX_LEN_0F3A17,
1250 VEX_LEN_0F3A18,
1251 VEX_LEN_0F3A19,
1252 VEX_LEN_0F3A20,
1253 VEX_LEN_0F3A21,
1254 VEX_LEN_0F3A22,
1255 VEX_LEN_0F3A30,
1256 VEX_LEN_0F3A31,
1257 VEX_LEN_0F3A32,
1258 VEX_LEN_0F3A33,
1259 VEX_LEN_0F3A38,
1260 VEX_LEN_0F3A39,
1261 VEX_LEN_0F3A41,
1262 VEX_LEN_0F3A46,
1263 VEX_LEN_0F3A60,
1264 VEX_LEN_0F3A61,
1265 VEX_LEN_0F3A62,
1266 VEX_LEN_0F3A63,
1267 VEX_LEN_0F3ADF,
1268 VEX_LEN_0F3AF0,
1269 VEX_LEN_0FXOP_08_85,
1270 VEX_LEN_0FXOP_08_86,
1271 VEX_LEN_0FXOP_08_87,
1272 VEX_LEN_0FXOP_08_8E,
1273 VEX_LEN_0FXOP_08_8F,
1274 VEX_LEN_0FXOP_08_95,
1275 VEX_LEN_0FXOP_08_96,
1276 VEX_LEN_0FXOP_08_97,
1277 VEX_LEN_0FXOP_08_9E,
1278 VEX_LEN_0FXOP_08_9F,
1279 VEX_LEN_0FXOP_08_A3,
1280 VEX_LEN_0FXOP_08_A6,
1281 VEX_LEN_0FXOP_08_B6,
1282 VEX_LEN_0FXOP_08_C0,
1283 VEX_LEN_0FXOP_08_C1,
1284 VEX_LEN_0FXOP_08_C2,
1285 VEX_LEN_0FXOP_08_C3,
1286 VEX_LEN_0FXOP_08_CC,
1287 VEX_LEN_0FXOP_08_CD,
1288 VEX_LEN_0FXOP_08_CE,
1289 VEX_LEN_0FXOP_08_CF,
1290 VEX_LEN_0FXOP_08_EC,
1291 VEX_LEN_0FXOP_08_ED,
1292 VEX_LEN_0FXOP_08_EE,
1293 VEX_LEN_0FXOP_08_EF,
1294 VEX_LEN_0FXOP_09_01,
1295 VEX_LEN_0FXOP_09_02,
1296 VEX_LEN_0FXOP_09_12_M_1,
1297 VEX_LEN_0FXOP_09_82_W_0,
1298 VEX_LEN_0FXOP_09_83_W_0,
1299 VEX_LEN_0FXOP_09_90,
1300 VEX_LEN_0FXOP_09_91,
1301 VEX_LEN_0FXOP_09_92,
1302 VEX_LEN_0FXOP_09_93,
1303 VEX_LEN_0FXOP_09_94,
1304 VEX_LEN_0FXOP_09_95,
1305 VEX_LEN_0FXOP_09_96,
1306 VEX_LEN_0FXOP_09_97,
1307 VEX_LEN_0FXOP_09_98,
1308 VEX_LEN_0FXOP_09_99,
1309 VEX_LEN_0FXOP_09_9A,
1310 VEX_LEN_0FXOP_09_9B,
1311 VEX_LEN_0FXOP_09_C1,
1312 VEX_LEN_0FXOP_09_C2,
1313 VEX_LEN_0FXOP_09_C3,
1314 VEX_LEN_0FXOP_09_C6,
1315 VEX_LEN_0FXOP_09_C7,
1316 VEX_LEN_0FXOP_09_CB,
1317 VEX_LEN_0FXOP_09_D1,
1318 VEX_LEN_0FXOP_09_D2,
1319 VEX_LEN_0FXOP_09_D3,
1320 VEX_LEN_0FXOP_09_D6,
1321 VEX_LEN_0FXOP_09_D7,
1322 VEX_LEN_0FXOP_09_DB,
1323 VEX_LEN_0FXOP_09_E1,
1324 VEX_LEN_0FXOP_09_E2,
1325 VEX_LEN_0FXOP_09_E3,
1326 VEX_LEN_0FXOP_0A_12,
1327 };
1328
1329 enum
1330 {
1331 EVEX_LEN_0F3816 = 0,
1332 EVEX_LEN_0F3819,
1333 EVEX_LEN_0F381A_M_0,
1334 EVEX_LEN_0F381B_M_0,
1335 EVEX_LEN_0F3836,
1336 EVEX_LEN_0F385A_M_0,
1337 EVEX_LEN_0F385B_M_0,
1338 EVEX_LEN_0F38C6_M_0,
1339 EVEX_LEN_0F38C7_M_0,
1340 EVEX_LEN_0F3A00,
1341 EVEX_LEN_0F3A01,
1342 EVEX_LEN_0F3A18,
1343 EVEX_LEN_0F3A19,
1344 EVEX_LEN_0F3A1A,
1345 EVEX_LEN_0F3A1B,
1346 EVEX_LEN_0F3A23,
1347 EVEX_LEN_0F3A38,
1348 EVEX_LEN_0F3A39,
1349 EVEX_LEN_0F3A3A,
1350 EVEX_LEN_0F3A3B,
1351 EVEX_LEN_0F3A43
1352 };
1353
1354 enum
1355 {
1356 VEX_W_0F41_L_1_M_1 = 0,
1357 VEX_W_0F42_L_1_M_1,
1358 VEX_W_0F44_L_0_M_1,
1359 VEX_W_0F45_L_1_M_1,
1360 VEX_W_0F46_L_1_M_1,
1361 VEX_W_0F47_L_1_M_1,
1362 VEX_W_0F4A_L_1_M_1,
1363 VEX_W_0F4B_L_1_M_1,
1364 VEX_W_0F90_L_0,
1365 VEX_W_0F91_L_0_M_0,
1366 VEX_W_0F92_L_0_M_1,
1367 VEX_W_0F93_L_0_M_1,
1368 VEX_W_0F98_L_0_M_1,
1369 VEX_W_0F99_L_0_M_1,
1370 VEX_W_0F380C,
1371 VEX_W_0F380D,
1372 VEX_W_0F380E,
1373 VEX_W_0F380F,
1374 VEX_W_0F3813,
1375 VEX_W_0F3816_L_1,
1376 VEX_W_0F3818,
1377 VEX_W_0F3819_L_1,
1378 VEX_W_0F381A_M_0_L_1,
1379 VEX_W_0F382C_M_0,
1380 VEX_W_0F382D_M_0,
1381 VEX_W_0F382E_M_0,
1382 VEX_W_0F382F_M_0,
1383 VEX_W_0F3836,
1384 VEX_W_0F3846,
1385 VEX_W_0F3849_X86_64_P_0,
1386 VEX_W_0F3849_X86_64_P_2,
1387 VEX_W_0F3849_X86_64_P_3,
1388 VEX_W_0F384B_X86_64_P_1,
1389 VEX_W_0F384B_X86_64_P_2,
1390 VEX_W_0F384B_X86_64_P_3,
1391 VEX_W_0F3850,
1392 VEX_W_0F3851,
1393 VEX_W_0F3852,
1394 VEX_W_0F3853,
1395 VEX_W_0F3858,
1396 VEX_W_0F3859,
1397 VEX_W_0F385A_M_0_L_0,
1398 VEX_W_0F385C_X86_64_P_1,
1399 VEX_W_0F385E_X86_64_P_0,
1400 VEX_W_0F385E_X86_64_P_1,
1401 VEX_W_0F385E_X86_64_P_2,
1402 VEX_W_0F385E_X86_64_P_3,
1403 VEX_W_0F3878,
1404 VEX_W_0F3879,
1405 VEX_W_0F38CF,
1406 VEX_W_0F3A00_L_1,
1407 VEX_W_0F3A01_L_1,
1408 VEX_W_0F3A02,
1409 VEX_W_0F3A04,
1410 VEX_W_0F3A05,
1411 VEX_W_0F3A06_L_1,
1412 VEX_W_0F3A18_L_1,
1413 VEX_W_0F3A19_L_1,
1414 VEX_W_0F3A1D,
1415 VEX_W_0F3A38_L_1,
1416 VEX_W_0F3A39_L_1,
1417 VEX_W_0F3A46_L_1,
1418 VEX_W_0F3A4A,
1419 VEX_W_0F3A4B,
1420 VEX_W_0F3A4C,
1421 VEX_W_0F3ACE,
1422 VEX_W_0F3ACF,
1423
1424 VEX_W_0FXOP_08_85_L_0,
1425 VEX_W_0FXOP_08_86_L_0,
1426 VEX_W_0FXOP_08_87_L_0,
1427 VEX_W_0FXOP_08_8E_L_0,
1428 VEX_W_0FXOP_08_8F_L_0,
1429 VEX_W_0FXOP_08_95_L_0,
1430 VEX_W_0FXOP_08_96_L_0,
1431 VEX_W_0FXOP_08_97_L_0,
1432 VEX_W_0FXOP_08_9E_L_0,
1433 VEX_W_0FXOP_08_9F_L_0,
1434 VEX_W_0FXOP_08_A6_L_0,
1435 VEX_W_0FXOP_08_B6_L_0,
1436 VEX_W_0FXOP_08_C0_L_0,
1437 VEX_W_0FXOP_08_C1_L_0,
1438 VEX_W_0FXOP_08_C2_L_0,
1439 VEX_W_0FXOP_08_C3_L_0,
1440 VEX_W_0FXOP_08_CC_L_0,
1441 VEX_W_0FXOP_08_CD_L_0,
1442 VEX_W_0FXOP_08_CE_L_0,
1443 VEX_W_0FXOP_08_CF_L_0,
1444 VEX_W_0FXOP_08_EC_L_0,
1445 VEX_W_0FXOP_08_ED_L_0,
1446 VEX_W_0FXOP_08_EE_L_0,
1447 VEX_W_0FXOP_08_EF_L_0,
1448
1449 VEX_W_0FXOP_09_80,
1450 VEX_W_0FXOP_09_81,
1451 VEX_W_0FXOP_09_82,
1452 VEX_W_0FXOP_09_83,
1453 VEX_W_0FXOP_09_C1_L_0,
1454 VEX_W_0FXOP_09_C2_L_0,
1455 VEX_W_0FXOP_09_C3_L_0,
1456 VEX_W_0FXOP_09_C6_L_0,
1457 VEX_W_0FXOP_09_C7_L_0,
1458 VEX_W_0FXOP_09_CB_L_0,
1459 VEX_W_0FXOP_09_D1_L_0,
1460 VEX_W_0FXOP_09_D2_L_0,
1461 VEX_W_0FXOP_09_D3_L_0,
1462 VEX_W_0FXOP_09_D6_L_0,
1463 VEX_W_0FXOP_09_D7_L_0,
1464 VEX_W_0FXOP_09_DB_L_0,
1465 VEX_W_0FXOP_09_E1_L_0,
1466 VEX_W_0FXOP_09_E2_L_0,
1467 VEX_W_0FXOP_09_E3_L_0,
1468
1469 EVEX_W_0F10_P_1,
1470 EVEX_W_0F10_P_3,
1471 EVEX_W_0F11_P_1,
1472 EVEX_W_0F11_P_3,
1473 EVEX_W_0F12_P_0_M_1,
1474 EVEX_W_0F12_P_1,
1475 EVEX_W_0F12_P_3,
1476 EVEX_W_0F16_P_0_M_1,
1477 EVEX_W_0F16_P_1,
1478 EVEX_W_0F51_P_1,
1479 EVEX_W_0F51_P_3,
1480 EVEX_W_0F58_P_1,
1481 EVEX_W_0F58_P_3,
1482 EVEX_W_0F59_P_1,
1483 EVEX_W_0F59_P_3,
1484 EVEX_W_0F5A_P_0,
1485 EVEX_W_0F5A_P_1,
1486 EVEX_W_0F5A_P_2,
1487 EVEX_W_0F5A_P_3,
1488 EVEX_W_0F5B_P_0,
1489 EVEX_W_0F5B_P_1,
1490 EVEX_W_0F5B_P_2,
1491 EVEX_W_0F5C_P_1,
1492 EVEX_W_0F5C_P_3,
1493 EVEX_W_0F5D_P_1,
1494 EVEX_W_0F5D_P_3,
1495 EVEX_W_0F5E_P_1,
1496 EVEX_W_0F5E_P_3,
1497 EVEX_W_0F5F_P_1,
1498 EVEX_W_0F5F_P_3,
1499 EVEX_W_0F62,
1500 EVEX_W_0F66,
1501 EVEX_W_0F6A,
1502 EVEX_W_0F6B,
1503 EVEX_W_0F6C,
1504 EVEX_W_0F6D,
1505 EVEX_W_0F6F_P_1,
1506 EVEX_W_0F6F_P_2,
1507 EVEX_W_0F6F_P_3,
1508 EVEX_W_0F70_P_2,
1509 EVEX_W_0F72_R_2,
1510 EVEX_W_0F72_R_6,
1511 EVEX_W_0F73_R_2,
1512 EVEX_W_0F73_R_6,
1513 EVEX_W_0F76,
1514 EVEX_W_0F78_P_0,
1515 EVEX_W_0F78_P_2,
1516 EVEX_W_0F79_P_0,
1517 EVEX_W_0F79_P_2,
1518 EVEX_W_0F7A_P_1,
1519 EVEX_W_0F7A_P_2,
1520 EVEX_W_0F7A_P_3,
1521 EVEX_W_0F7B_P_2,
1522 EVEX_W_0F7E_P_1,
1523 EVEX_W_0F7F_P_1,
1524 EVEX_W_0F7F_P_2,
1525 EVEX_W_0F7F_P_3,
1526 EVEX_W_0FC2_P_1,
1527 EVEX_W_0FC2_P_3,
1528 EVEX_W_0FD2,
1529 EVEX_W_0FD3,
1530 EVEX_W_0FD4,
1531 EVEX_W_0FD6,
1532 EVEX_W_0FE6_P_1,
1533 EVEX_W_0FE6_P_2,
1534 EVEX_W_0FE6_P_3,
1535 EVEX_W_0FE7,
1536 EVEX_W_0FF2,
1537 EVEX_W_0FF3,
1538 EVEX_W_0FF4,
1539 EVEX_W_0FFA,
1540 EVEX_W_0FFB,
1541 EVEX_W_0FFE,
1542 EVEX_W_0F380D,
1543 EVEX_W_0F3810_P_1,
1544 EVEX_W_0F3810_P_2,
1545 EVEX_W_0F3811_P_1,
1546 EVEX_W_0F3811_P_2,
1547 EVEX_W_0F3812_P_1,
1548 EVEX_W_0F3812_P_2,
1549 EVEX_W_0F3813_P_1,
1550 EVEX_W_0F3813_P_2,
1551 EVEX_W_0F3814_P_1,
1552 EVEX_W_0F3815_P_1,
1553 EVEX_W_0F3819_L_n,
1554 EVEX_W_0F381A_M_0_L_n,
1555 EVEX_W_0F381B_M_0_L_2,
1556 EVEX_W_0F381E,
1557 EVEX_W_0F381F,
1558 EVEX_W_0F3820_P_1,
1559 EVEX_W_0F3821_P_1,
1560 EVEX_W_0F3822_P_1,
1561 EVEX_W_0F3823_P_1,
1562 EVEX_W_0F3824_P_1,
1563 EVEX_W_0F3825_P_1,
1564 EVEX_W_0F3825_P_2,
1565 EVEX_W_0F3828_P_2,
1566 EVEX_W_0F3829_P_2,
1567 EVEX_W_0F382A_P_1,
1568 EVEX_W_0F382A_P_2,
1569 EVEX_W_0F382B,
1570 EVEX_W_0F3830_P_1,
1571 EVEX_W_0F3831_P_1,
1572 EVEX_W_0F3832_P_1,
1573 EVEX_W_0F3833_P_1,
1574 EVEX_W_0F3834_P_1,
1575 EVEX_W_0F3835_P_1,
1576 EVEX_W_0F3835_P_2,
1577 EVEX_W_0F3837,
1578 EVEX_W_0F383A_P_1,
1579 EVEX_W_0F3852_P_1,
1580 EVEX_W_0F3859,
1581 EVEX_W_0F385A_M_0_L_n,
1582 EVEX_W_0F385B_M_0_L_2,
1583 EVEX_W_0F3870,
1584 EVEX_W_0F3872_P_1,
1585 EVEX_W_0F3872_P_2,
1586 EVEX_W_0F3872_P_3,
1587 EVEX_W_0F387A,
1588 EVEX_W_0F387B,
1589 EVEX_W_0F3883,
1590
1591 EVEX_W_0F3A05,
1592 EVEX_W_0F3A08,
1593 EVEX_W_0F3A09,
1594 EVEX_W_0F3A0A,
1595 EVEX_W_0F3A0B,
1596 EVEX_W_0F3A18_L_n,
1597 EVEX_W_0F3A19_L_n,
1598 EVEX_W_0F3A1A_L_2,
1599 EVEX_W_0F3A1B_L_2,
1600 EVEX_W_0F3A21,
1601 EVEX_W_0F3A23_L_n,
1602 EVEX_W_0F3A38_L_n,
1603 EVEX_W_0F3A39_L_n,
1604 EVEX_W_0F3A3A_L_2,
1605 EVEX_W_0F3A3B_L_2,
1606 EVEX_W_0F3A42,
1607 EVEX_W_0F3A43_L_n,
1608 EVEX_W_0F3A70,
1609 EVEX_W_0F3A72,
1610 };
1611
1612 typedef void (*op_rtn) (int bytemode, int sizeflag);
1613
1614 struct dis386 {
1615 const char *name;
1616 struct
1617 {
1618 op_rtn rtn;
1619 int bytemode;
1620 } op[MAX_OPERANDS];
1621 unsigned int prefix_requirement;
1622 };
1623
1624 /* Upper case letters in the instruction names here are macros.
1625 'A' => print 'b' if no register operands or suffix_always is true
1626 'B' => print 'b' if suffix_always is true
1627 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1628 size prefix
1629 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1630 suffix_always is true
1631 'E' => print 'e' if 32-bit form of jcxz
1632 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1633 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1634 'H' => print ",pt" or ",pn" branch hint
1635 'I' unused.
1636 'J' unused.
1637 'K' => print 'd' or 'q' if rex prefix is present.
1638 'L' unused.
1639 'M' => print 'r' if intel_mnemonic is false.
1640 'N' => print 'n' if instruction has no wait "prefix"
1641 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1642 'P' => behave as 'T' except with register operand outside of suffix_always
1643 mode
1644 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1645 is true
1646 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1647 'S' => print 'w', 'l' or 'q' if suffix_always is true
1648 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1649 prefix or if suffix_always is true.
1650 'U' unused.
1651 'V' unused.
1652 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1653 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1654 'Y' unused.
1655 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1656 '!' => change condition from true to false or from false to true.
1657 '%' => add 1 upper case letter to the macro.
1658 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1659 prefix or suffix_always is true (lcall/ljmp).
1660 '@' => in 64bit mode for Intel64 ISA or if instruction
1661 has no operand sizing prefix, print 'q' if suffix_always is true or
1662 nothing otherwise; behave as 'P' in all other cases
1663
1664 2 upper case letter macros:
1665 "XY" => print 'x' or 'y' if suffix_always is true or no register
1666 operands and no broadcast.
1667 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1668 register operands and no broadcast.
1669 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1670 "XV" => print "{vex3}" pseudo prefix
1671 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1672 being false, or no operand at all in 64bit mode, or if suffix_always
1673 is true.
1674 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1675 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1676 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1677 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1678 "BW" => print 'b' or 'w' depending on the VEX.W bit
1679 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1680 an operand size prefix, or suffix_always is true. print
1681 'q' if rex prefix is present.
1682
1683 Many of the above letters print nothing in Intel mode. See "putop"
1684 for the details.
1685
1686 Braces '{' and '}', and vertical bars '|', indicate alternative
1687 mnemonic strings for AT&T and Intel. */
1688
1689 static const struct dis386 dis386[] = {
1690 /* 00 */
1691 { "addB", { Ebh1, Gb }, 0 },
1692 { "addS", { Evh1, Gv }, 0 },
1693 { "addB", { Gb, EbS }, 0 },
1694 { "addS", { Gv, EvS }, 0 },
1695 { "addB", { AL, Ib }, 0 },
1696 { "addS", { eAX, Iv }, 0 },
1697 { X86_64_TABLE (X86_64_06) },
1698 { X86_64_TABLE (X86_64_07) },
1699 /* 08 */
1700 { "orB", { Ebh1, Gb }, 0 },
1701 { "orS", { Evh1, Gv }, 0 },
1702 { "orB", { Gb, EbS }, 0 },
1703 { "orS", { Gv, EvS }, 0 },
1704 { "orB", { AL, Ib }, 0 },
1705 { "orS", { eAX, Iv }, 0 },
1706 { X86_64_TABLE (X86_64_0E) },
1707 { Bad_Opcode }, /* 0x0f extended opcode escape */
1708 /* 10 */
1709 { "adcB", { Ebh1, Gb }, 0 },
1710 { "adcS", { Evh1, Gv }, 0 },
1711 { "adcB", { Gb, EbS }, 0 },
1712 { "adcS", { Gv, EvS }, 0 },
1713 { "adcB", { AL, Ib }, 0 },
1714 { "adcS", { eAX, Iv }, 0 },
1715 { X86_64_TABLE (X86_64_16) },
1716 { X86_64_TABLE (X86_64_17) },
1717 /* 18 */
1718 { "sbbB", { Ebh1, Gb }, 0 },
1719 { "sbbS", { Evh1, Gv }, 0 },
1720 { "sbbB", { Gb, EbS }, 0 },
1721 { "sbbS", { Gv, EvS }, 0 },
1722 { "sbbB", { AL, Ib }, 0 },
1723 { "sbbS", { eAX, Iv }, 0 },
1724 { X86_64_TABLE (X86_64_1E) },
1725 { X86_64_TABLE (X86_64_1F) },
1726 /* 20 */
1727 { "andB", { Ebh1, Gb }, 0 },
1728 { "andS", { Evh1, Gv }, 0 },
1729 { "andB", { Gb, EbS }, 0 },
1730 { "andS", { Gv, EvS }, 0 },
1731 { "andB", { AL, Ib }, 0 },
1732 { "andS", { eAX, Iv }, 0 },
1733 { Bad_Opcode }, /* SEG ES prefix */
1734 { X86_64_TABLE (X86_64_27) },
1735 /* 28 */
1736 { "subB", { Ebh1, Gb }, 0 },
1737 { "subS", { Evh1, Gv }, 0 },
1738 { "subB", { Gb, EbS }, 0 },
1739 { "subS", { Gv, EvS }, 0 },
1740 { "subB", { AL, Ib }, 0 },
1741 { "subS", { eAX, Iv }, 0 },
1742 { Bad_Opcode }, /* SEG CS prefix */
1743 { X86_64_TABLE (X86_64_2F) },
1744 /* 30 */
1745 { "xorB", { Ebh1, Gb }, 0 },
1746 { "xorS", { Evh1, Gv }, 0 },
1747 { "xorB", { Gb, EbS }, 0 },
1748 { "xorS", { Gv, EvS }, 0 },
1749 { "xorB", { AL, Ib }, 0 },
1750 { "xorS", { eAX, Iv }, 0 },
1751 { Bad_Opcode }, /* SEG SS prefix */
1752 { X86_64_TABLE (X86_64_37) },
1753 /* 38 */
1754 { "cmpB", { Eb, Gb }, 0 },
1755 { "cmpS", { Ev, Gv }, 0 },
1756 { "cmpB", { Gb, EbS }, 0 },
1757 { "cmpS", { Gv, EvS }, 0 },
1758 { "cmpB", { AL, Ib }, 0 },
1759 { "cmpS", { eAX, Iv }, 0 },
1760 { Bad_Opcode }, /* SEG DS prefix */
1761 { X86_64_TABLE (X86_64_3F) },
1762 /* 40 */
1763 { "inc{S|}", { RMeAX }, 0 },
1764 { "inc{S|}", { RMeCX }, 0 },
1765 { "inc{S|}", { RMeDX }, 0 },
1766 { "inc{S|}", { RMeBX }, 0 },
1767 { "inc{S|}", { RMeSP }, 0 },
1768 { "inc{S|}", { RMeBP }, 0 },
1769 { "inc{S|}", { RMeSI }, 0 },
1770 { "inc{S|}", { RMeDI }, 0 },
1771 /* 48 */
1772 { "dec{S|}", { RMeAX }, 0 },
1773 { "dec{S|}", { RMeCX }, 0 },
1774 { "dec{S|}", { RMeDX }, 0 },
1775 { "dec{S|}", { RMeBX }, 0 },
1776 { "dec{S|}", { RMeSP }, 0 },
1777 { "dec{S|}", { RMeBP }, 0 },
1778 { "dec{S|}", { RMeSI }, 0 },
1779 { "dec{S|}", { RMeDI }, 0 },
1780 /* 50 */
1781 { "push{!P|}", { RMrAX }, 0 },
1782 { "push{!P|}", { RMrCX }, 0 },
1783 { "push{!P|}", { RMrDX }, 0 },
1784 { "push{!P|}", { RMrBX }, 0 },
1785 { "push{!P|}", { RMrSP }, 0 },
1786 { "push{!P|}", { RMrBP }, 0 },
1787 { "push{!P|}", { RMrSI }, 0 },
1788 { "push{!P|}", { RMrDI }, 0 },
1789 /* 58 */
1790 { "pop{!P|}", { RMrAX }, 0 },
1791 { "pop{!P|}", { RMrCX }, 0 },
1792 { "pop{!P|}", { RMrDX }, 0 },
1793 { "pop{!P|}", { RMrBX }, 0 },
1794 { "pop{!P|}", { RMrSP }, 0 },
1795 { "pop{!P|}", { RMrBP }, 0 },
1796 { "pop{!P|}", { RMrSI }, 0 },
1797 { "pop{!P|}", { RMrDI }, 0 },
1798 /* 60 */
1799 { X86_64_TABLE (X86_64_60) },
1800 { X86_64_TABLE (X86_64_61) },
1801 { X86_64_TABLE (X86_64_62) },
1802 { X86_64_TABLE (X86_64_63) },
1803 { Bad_Opcode }, /* seg fs */
1804 { Bad_Opcode }, /* seg gs */
1805 { Bad_Opcode }, /* op size prefix */
1806 { Bad_Opcode }, /* adr size prefix */
1807 /* 68 */
1808 { "pushP", { sIv }, 0 },
1809 { "imulS", { Gv, Ev, Iv }, 0 },
1810 { "pushP", { sIbT }, 0 },
1811 { "imulS", { Gv, Ev, sIb }, 0 },
1812 { "ins{b|}", { Ybr, indirDX }, 0 },
1813 { X86_64_TABLE (X86_64_6D) },
1814 { "outs{b|}", { indirDXr, Xb }, 0 },
1815 { X86_64_TABLE (X86_64_6F) },
1816 /* 70 */
1817 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1818 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1819 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1820 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1821 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1822 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1823 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1824 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1825 /* 78 */
1826 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1827 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1828 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1829 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1830 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1831 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1832 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1833 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1834 /* 80 */
1835 { REG_TABLE (REG_80) },
1836 { REG_TABLE (REG_81) },
1837 { X86_64_TABLE (X86_64_82) },
1838 { REG_TABLE (REG_83) },
1839 { "testB", { Eb, Gb }, 0 },
1840 { "testS", { Ev, Gv }, 0 },
1841 { "xchgB", { Ebh2, Gb }, 0 },
1842 { "xchgS", { Evh2, Gv }, 0 },
1843 /* 88 */
1844 { "movB", { Ebh3, Gb }, 0 },
1845 { "movS", { Evh3, Gv }, 0 },
1846 { "movB", { Gb, EbS }, 0 },
1847 { "movS", { Gv, EvS }, 0 },
1848 { "movD", { Sv, Sw }, 0 },
1849 { MOD_TABLE (MOD_8D) },
1850 { "movD", { Sw, Sv }, 0 },
1851 { REG_TABLE (REG_8F) },
1852 /* 90 */
1853 { PREFIX_TABLE (PREFIX_90) },
1854 { "xchgS", { RMeCX, eAX }, 0 },
1855 { "xchgS", { RMeDX, eAX }, 0 },
1856 { "xchgS", { RMeBX, eAX }, 0 },
1857 { "xchgS", { RMeSP, eAX }, 0 },
1858 { "xchgS", { RMeBP, eAX }, 0 },
1859 { "xchgS", { RMeSI, eAX }, 0 },
1860 { "xchgS", { RMeDI, eAX }, 0 },
1861 /* 98 */
1862 { "cW{t|}R", { XX }, 0 },
1863 { "cR{t|}O", { XX }, 0 },
1864 { X86_64_TABLE (X86_64_9A) },
1865 { Bad_Opcode }, /* fwait */
1866 { "pushfP", { XX }, 0 },
1867 { "popfP", { XX }, 0 },
1868 { "sahf", { XX }, 0 },
1869 { "lahf", { XX }, 0 },
1870 /* a0 */
1871 { "mov%LB", { AL, Ob }, 0 },
1872 { "mov%LS", { eAX, Ov }, 0 },
1873 { "mov%LB", { Ob, AL }, 0 },
1874 { "mov%LS", { Ov, eAX }, 0 },
1875 { "movs{b|}", { Ybr, Xb }, 0 },
1876 { "movs{R|}", { Yvr, Xv }, 0 },
1877 { "cmps{b|}", { Xb, Yb }, 0 },
1878 { "cmps{R|}", { Xv, Yv }, 0 },
1879 /* a8 */
1880 { "testB", { AL, Ib }, 0 },
1881 { "testS", { eAX, Iv }, 0 },
1882 { "stosB", { Ybr, AL }, 0 },
1883 { "stosS", { Yvr, eAX }, 0 },
1884 { "lodsB", { ALr, Xb }, 0 },
1885 { "lodsS", { eAXr, Xv }, 0 },
1886 { "scasB", { AL, Yb }, 0 },
1887 { "scasS", { eAX, Yv }, 0 },
1888 /* b0 */
1889 { "movB", { RMAL, Ib }, 0 },
1890 { "movB", { RMCL, Ib }, 0 },
1891 { "movB", { RMDL, Ib }, 0 },
1892 { "movB", { RMBL, Ib }, 0 },
1893 { "movB", { RMAH, Ib }, 0 },
1894 { "movB", { RMCH, Ib }, 0 },
1895 { "movB", { RMDH, Ib }, 0 },
1896 { "movB", { RMBH, Ib }, 0 },
1897 /* b8 */
1898 { "mov%LV", { RMeAX, Iv64 }, 0 },
1899 { "mov%LV", { RMeCX, Iv64 }, 0 },
1900 { "mov%LV", { RMeDX, Iv64 }, 0 },
1901 { "mov%LV", { RMeBX, Iv64 }, 0 },
1902 { "mov%LV", { RMeSP, Iv64 }, 0 },
1903 { "mov%LV", { RMeBP, Iv64 }, 0 },
1904 { "mov%LV", { RMeSI, Iv64 }, 0 },
1905 { "mov%LV", { RMeDI, Iv64 }, 0 },
1906 /* c0 */
1907 { REG_TABLE (REG_C0) },
1908 { REG_TABLE (REG_C1) },
1909 { X86_64_TABLE (X86_64_C2) },
1910 { X86_64_TABLE (X86_64_C3) },
1911 { X86_64_TABLE (X86_64_C4) },
1912 { X86_64_TABLE (X86_64_C5) },
1913 { REG_TABLE (REG_C6) },
1914 { REG_TABLE (REG_C7) },
1915 /* c8 */
1916 { "enterP", { Iw, Ib }, 0 },
1917 { "leaveP", { XX }, 0 },
1918 { "{l|}ret{|f}%LP", { Iw }, 0 },
1919 { "{l|}ret{|f}%LP", { XX }, 0 },
1920 { "int3", { XX }, 0 },
1921 { "int", { Ib }, 0 },
1922 { X86_64_TABLE (X86_64_CE) },
1923 { "iret%LP", { XX }, 0 },
1924 /* d0 */
1925 { REG_TABLE (REG_D0) },
1926 { REG_TABLE (REG_D1) },
1927 { REG_TABLE (REG_D2) },
1928 { REG_TABLE (REG_D3) },
1929 { X86_64_TABLE (X86_64_D4) },
1930 { X86_64_TABLE (X86_64_D5) },
1931 { Bad_Opcode },
1932 { "xlat", { DSBX }, 0 },
1933 /* d8 */
1934 { FLOAT },
1935 { FLOAT },
1936 { FLOAT },
1937 { FLOAT },
1938 { FLOAT },
1939 { FLOAT },
1940 { FLOAT },
1941 { FLOAT },
1942 /* e0 */
1943 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
1944 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
1945 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
1946 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
1947 { "inB", { AL, Ib }, 0 },
1948 { "inG", { zAX, Ib }, 0 },
1949 { "outB", { Ib, AL }, 0 },
1950 { "outG", { Ib, zAX }, 0 },
1951 /* e8 */
1952 { X86_64_TABLE (X86_64_E8) },
1953 { X86_64_TABLE (X86_64_E9) },
1954 { X86_64_TABLE (X86_64_EA) },
1955 { "jmp", { Jb, BND }, 0 },
1956 { "inB", { AL, indirDX }, 0 },
1957 { "inG", { zAX, indirDX }, 0 },
1958 { "outB", { indirDX, AL }, 0 },
1959 { "outG", { indirDX, zAX }, 0 },
1960 /* f0 */
1961 { Bad_Opcode }, /* lock prefix */
1962 { "int1", { XX }, 0 },
1963 { Bad_Opcode }, /* repne */
1964 { Bad_Opcode }, /* repz */
1965 { "hlt", { XX }, 0 },
1966 { "cmc", { XX }, 0 },
1967 { REG_TABLE (REG_F6) },
1968 { REG_TABLE (REG_F7) },
1969 /* f8 */
1970 { "clc", { XX }, 0 },
1971 { "stc", { XX }, 0 },
1972 { "cli", { XX }, 0 },
1973 { "sti", { XX }, 0 },
1974 { "cld", { XX }, 0 },
1975 { "std", { XX }, 0 },
1976 { REG_TABLE (REG_FE) },
1977 { REG_TABLE (REG_FF) },
1978 };
1979
1980 static const struct dis386 dis386_twobyte[] = {
1981 /* 00 */
1982 { REG_TABLE (REG_0F00 ) },
1983 { REG_TABLE (REG_0F01 ) },
1984 { "larS", { Gv, Ew }, 0 },
1985 { "lslS", { Gv, Ew }, 0 },
1986 { Bad_Opcode },
1987 { "syscall", { XX }, 0 },
1988 { "clts", { XX }, 0 },
1989 { "sysret%LQ", { XX }, 0 },
1990 /* 08 */
1991 { "invd", { XX }, 0 },
1992 { PREFIX_TABLE (PREFIX_0F09) },
1993 { Bad_Opcode },
1994 { "ud2", { XX }, 0 },
1995 { Bad_Opcode },
1996 { REG_TABLE (REG_0F0D) },
1997 { "femms", { XX }, 0 },
1998 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
1999 /* 10 */
2000 { PREFIX_TABLE (PREFIX_0F10) },
2001 { PREFIX_TABLE (PREFIX_0F11) },
2002 { PREFIX_TABLE (PREFIX_0F12) },
2003 { MOD_TABLE (MOD_0F13) },
2004 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2005 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2006 { PREFIX_TABLE (PREFIX_0F16) },
2007 { MOD_TABLE (MOD_0F17) },
2008 /* 18 */
2009 { REG_TABLE (REG_0F18) },
2010 { "nopQ", { Ev }, 0 },
2011 { PREFIX_TABLE (PREFIX_0F1A) },
2012 { PREFIX_TABLE (PREFIX_0F1B) },
2013 { PREFIX_TABLE (PREFIX_0F1C) },
2014 { "nopQ", { Ev }, 0 },
2015 { PREFIX_TABLE (PREFIX_0F1E) },
2016 { "nopQ", { Ev }, 0 },
2017 /* 20 */
2018 { "movZ", { Em, Cm }, 0 },
2019 { "movZ", { Em, Dm }, 0 },
2020 { "movZ", { Cm, Em }, 0 },
2021 { "movZ", { Dm, Em }, 0 },
2022 { X86_64_TABLE (X86_64_0F24) },
2023 { Bad_Opcode },
2024 { X86_64_TABLE (X86_64_0F26) },
2025 { Bad_Opcode },
2026 /* 28 */
2027 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2028 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2029 { PREFIX_TABLE (PREFIX_0F2A) },
2030 { PREFIX_TABLE (PREFIX_0F2B) },
2031 { PREFIX_TABLE (PREFIX_0F2C) },
2032 { PREFIX_TABLE (PREFIX_0F2D) },
2033 { PREFIX_TABLE (PREFIX_0F2E) },
2034 { PREFIX_TABLE (PREFIX_0F2F) },
2035 /* 30 */
2036 { "wrmsr", { XX }, 0 },
2037 { "rdtsc", { XX }, 0 },
2038 { "rdmsr", { XX }, 0 },
2039 { "rdpmc", { XX }, 0 },
2040 { "sysenter", { SEP }, 0 },
2041 { "sysexit%LQ", { SEP }, 0 },
2042 { Bad_Opcode },
2043 { "getsec", { XX }, 0 },
2044 /* 38 */
2045 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2046 { Bad_Opcode },
2047 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2048 { Bad_Opcode },
2049 { Bad_Opcode },
2050 { Bad_Opcode },
2051 { Bad_Opcode },
2052 { Bad_Opcode },
2053 /* 40 */
2054 { "cmovoS", { Gv, Ev }, 0 },
2055 { "cmovnoS", { Gv, Ev }, 0 },
2056 { "cmovbS", { Gv, Ev }, 0 },
2057 { "cmovaeS", { Gv, Ev }, 0 },
2058 { "cmoveS", { Gv, Ev }, 0 },
2059 { "cmovneS", { Gv, Ev }, 0 },
2060 { "cmovbeS", { Gv, Ev }, 0 },
2061 { "cmovaS", { Gv, Ev }, 0 },
2062 /* 48 */
2063 { "cmovsS", { Gv, Ev }, 0 },
2064 { "cmovnsS", { Gv, Ev }, 0 },
2065 { "cmovpS", { Gv, Ev }, 0 },
2066 { "cmovnpS", { Gv, Ev }, 0 },
2067 { "cmovlS", { Gv, Ev }, 0 },
2068 { "cmovgeS", { Gv, Ev }, 0 },
2069 { "cmovleS", { Gv, Ev }, 0 },
2070 { "cmovgS", { Gv, Ev }, 0 },
2071 /* 50 */
2072 { MOD_TABLE (MOD_0F50) },
2073 { PREFIX_TABLE (PREFIX_0F51) },
2074 { PREFIX_TABLE (PREFIX_0F52) },
2075 { PREFIX_TABLE (PREFIX_0F53) },
2076 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2077 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2078 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2079 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2080 /* 58 */
2081 { PREFIX_TABLE (PREFIX_0F58) },
2082 { PREFIX_TABLE (PREFIX_0F59) },
2083 { PREFIX_TABLE (PREFIX_0F5A) },
2084 { PREFIX_TABLE (PREFIX_0F5B) },
2085 { PREFIX_TABLE (PREFIX_0F5C) },
2086 { PREFIX_TABLE (PREFIX_0F5D) },
2087 { PREFIX_TABLE (PREFIX_0F5E) },
2088 { PREFIX_TABLE (PREFIX_0F5F) },
2089 /* 60 */
2090 { PREFIX_TABLE (PREFIX_0F60) },
2091 { PREFIX_TABLE (PREFIX_0F61) },
2092 { PREFIX_TABLE (PREFIX_0F62) },
2093 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2094 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2095 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2096 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2097 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2098 /* 68 */
2099 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2100 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2101 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2102 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2103 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2104 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2105 { "movK", { MX, Edq }, PREFIX_OPCODE },
2106 { PREFIX_TABLE (PREFIX_0F6F) },
2107 /* 70 */
2108 { PREFIX_TABLE (PREFIX_0F70) },
2109 { MOD_TABLE (MOD_0F71) },
2110 { MOD_TABLE (MOD_0F72) },
2111 { MOD_TABLE (MOD_0F73) },
2112 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2113 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2114 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2115 { "emms", { XX }, PREFIX_OPCODE },
2116 /* 78 */
2117 { PREFIX_TABLE (PREFIX_0F78) },
2118 { PREFIX_TABLE (PREFIX_0F79) },
2119 { Bad_Opcode },
2120 { Bad_Opcode },
2121 { PREFIX_TABLE (PREFIX_0F7C) },
2122 { PREFIX_TABLE (PREFIX_0F7D) },
2123 { PREFIX_TABLE (PREFIX_0F7E) },
2124 { PREFIX_TABLE (PREFIX_0F7F) },
2125 /* 80 */
2126 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2127 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2128 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2129 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2130 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2131 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2132 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2133 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2134 /* 88 */
2135 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2136 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2137 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2138 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2139 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2140 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2141 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2142 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2143 /* 90 */
2144 { "seto", { Eb }, 0 },
2145 { "setno", { Eb }, 0 },
2146 { "setb", { Eb }, 0 },
2147 { "setae", { Eb }, 0 },
2148 { "sete", { Eb }, 0 },
2149 { "setne", { Eb }, 0 },
2150 { "setbe", { Eb }, 0 },
2151 { "seta", { Eb }, 0 },
2152 /* 98 */
2153 { "sets", { Eb }, 0 },
2154 { "setns", { Eb }, 0 },
2155 { "setp", { Eb }, 0 },
2156 { "setnp", { Eb }, 0 },
2157 { "setl", { Eb }, 0 },
2158 { "setge", { Eb }, 0 },
2159 { "setle", { Eb }, 0 },
2160 { "setg", { Eb }, 0 },
2161 /* a0 */
2162 { "pushP", { fs }, 0 },
2163 { "popP", { fs }, 0 },
2164 { "cpuid", { XX }, 0 },
2165 { "btS", { Ev, Gv }, 0 },
2166 { "shldS", { Ev, Gv, Ib }, 0 },
2167 { "shldS", { Ev, Gv, CL }, 0 },
2168 { REG_TABLE (REG_0FA6) },
2169 { REG_TABLE (REG_0FA7) },
2170 /* a8 */
2171 { "pushP", { gs }, 0 },
2172 { "popP", { gs }, 0 },
2173 { "rsm", { XX }, 0 },
2174 { "btsS", { Evh1, Gv }, 0 },
2175 { "shrdS", { Ev, Gv, Ib }, 0 },
2176 { "shrdS", { Ev, Gv, CL }, 0 },
2177 { REG_TABLE (REG_0FAE) },
2178 { "imulS", { Gv, Ev }, 0 },
2179 /* b0 */
2180 { "cmpxchgB", { Ebh1, Gb }, 0 },
2181 { "cmpxchgS", { Evh1, Gv }, 0 },
2182 { MOD_TABLE (MOD_0FB2) },
2183 { "btrS", { Evh1, Gv }, 0 },
2184 { MOD_TABLE (MOD_0FB4) },
2185 { MOD_TABLE (MOD_0FB5) },
2186 { "movz{bR|x}", { Gv, Eb }, 0 },
2187 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2188 /* b8 */
2189 { PREFIX_TABLE (PREFIX_0FB8) },
2190 { "ud1S", { Gv, Ev }, 0 },
2191 { REG_TABLE (REG_0FBA) },
2192 { "btcS", { Evh1, Gv }, 0 },
2193 { PREFIX_TABLE (PREFIX_0FBC) },
2194 { PREFIX_TABLE (PREFIX_0FBD) },
2195 { "movs{bR|x}", { Gv, Eb }, 0 },
2196 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2197 /* c0 */
2198 { "xaddB", { Ebh1, Gb }, 0 },
2199 { "xaddS", { Evh1, Gv }, 0 },
2200 { PREFIX_TABLE (PREFIX_0FC2) },
2201 { MOD_TABLE (MOD_0FC3) },
2202 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2203 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2204 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2205 { REG_TABLE (REG_0FC7) },
2206 /* c8 */
2207 { "bswap", { RMeAX }, 0 },
2208 { "bswap", { RMeCX }, 0 },
2209 { "bswap", { RMeDX }, 0 },
2210 { "bswap", { RMeBX }, 0 },
2211 { "bswap", { RMeSP }, 0 },
2212 { "bswap", { RMeBP }, 0 },
2213 { "bswap", { RMeSI }, 0 },
2214 { "bswap", { RMeDI }, 0 },
2215 /* d0 */
2216 { PREFIX_TABLE (PREFIX_0FD0) },
2217 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2218 { "psrld", { MX, EM }, PREFIX_OPCODE },
2219 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2220 { "paddq", { MX, EM }, PREFIX_OPCODE },
2221 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2222 { PREFIX_TABLE (PREFIX_0FD6) },
2223 { MOD_TABLE (MOD_0FD7) },
2224 /* d8 */
2225 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2226 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2227 { "pminub", { MX, EM }, PREFIX_OPCODE },
2228 { "pand", { MX, EM }, PREFIX_OPCODE },
2229 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2230 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2231 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2232 { "pandn", { MX, EM }, PREFIX_OPCODE },
2233 /* e0 */
2234 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2235 { "psraw", { MX, EM }, PREFIX_OPCODE },
2236 { "psrad", { MX, EM }, PREFIX_OPCODE },
2237 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2238 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2239 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2240 { PREFIX_TABLE (PREFIX_0FE6) },
2241 { PREFIX_TABLE (PREFIX_0FE7) },
2242 /* e8 */
2243 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2244 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2245 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2246 { "por", { MX, EM }, PREFIX_OPCODE },
2247 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2248 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2249 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2250 { "pxor", { MX, EM }, PREFIX_OPCODE },
2251 /* f0 */
2252 { PREFIX_TABLE (PREFIX_0FF0) },
2253 { "psllw", { MX, EM }, PREFIX_OPCODE },
2254 { "pslld", { MX, EM }, PREFIX_OPCODE },
2255 { "psllq", { MX, EM }, PREFIX_OPCODE },
2256 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2257 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2258 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2259 { PREFIX_TABLE (PREFIX_0FF7) },
2260 /* f8 */
2261 { "psubb", { MX, EM }, PREFIX_OPCODE },
2262 { "psubw", { MX, EM }, PREFIX_OPCODE },
2263 { "psubd", { MX, EM }, PREFIX_OPCODE },
2264 { "psubq", { MX, EM }, PREFIX_OPCODE },
2265 { "paddb", { MX, EM }, PREFIX_OPCODE },
2266 { "paddw", { MX, EM }, PREFIX_OPCODE },
2267 { "paddd", { MX, EM }, PREFIX_OPCODE },
2268 { "ud0S", { Gv, Ev }, 0 },
2269 };
2270
2271 static const unsigned char onebyte_has_modrm[256] = {
2272 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2273 /* ------------------------------- */
2274 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2275 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2276 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2277 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2278 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2279 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2280 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2281 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2282 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2283 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2284 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2285 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2286 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2287 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2288 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2289 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2290 /* ------------------------------- */
2291 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2292 };
2293
2294 static const unsigned char twobyte_has_modrm[256] = {
2295 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2296 /* ------------------------------- */
2297 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2298 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2299 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2300 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2301 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2302 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2303 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2304 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2305 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2306 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2307 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2308 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2309 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2310 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2311 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2312 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2313 /* ------------------------------- */
2314 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2315 };
2316
2317 static char obuf[100];
2318 static char *obufp;
2319 static char *mnemonicendp;
2320 static char scratchbuf[100];
2321 static unsigned char *start_codep;
2322 static unsigned char *insn_codep;
2323 static unsigned char *codep;
2324 static unsigned char *end_codep;
2325 static int last_lock_prefix;
2326 static int last_repz_prefix;
2327 static int last_repnz_prefix;
2328 static int last_data_prefix;
2329 static int last_addr_prefix;
2330 static int last_rex_prefix;
2331 static int last_seg_prefix;
2332 static int fwait_prefix;
2333 /* The active segment register prefix. */
2334 static int active_seg_prefix;
2335 #define MAX_CODE_LENGTH 15
2336 /* We can up to 14 prefixes since the maximum instruction length is
2337 15bytes. */
2338 static int all_prefixes[MAX_CODE_LENGTH - 1];
2339 static disassemble_info *the_info;
2340 static struct
2341 {
2342 int mod;
2343 int reg;
2344 int rm;
2345 }
2346 modrm;
2347 static unsigned char need_modrm;
2348 static struct
2349 {
2350 int scale;
2351 int index;
2352 int base;
2353 }
2354 sib;
2355 static struct
2356 {
2357 int register_specifier;
2358 int length;
2359 int prefix;
2360 int w;
2361 int evex;
2362 int r;
2363 int v;
2364 int mask_register_specifier;
2365 int zeroing;
2366 int ll;
2367 int b;
2368 }
2369 vex;
2370 static unsigned char need_vex;
2371
2372 struct op
2373 {
2374 const char *name;
2375 unsigned int len;
2376 };
2377
2378 /* If we are accessing mod/rm/reg without need_modrm set, then the
2379 values are stale. Hitting this abort likely indicates that you
2380 need to update onebyte_has_modrm or twobyte_has_modrm. */
2381 #define MODRM_CHECK if (!need_modrm) abort ()
2382
2383 static const char **names64;
2384 static const char **names32;
2385 static const char **names16;
2386 static const char **names8;
2387 static const char **names8rex;
2388 static const char **names_seg;
2389 static const char *index64;
2390 static const char *index32;
2391 static const char **index16;
2392 static const char **names_bnd;
2393
2394 static const char *intel_names64[] = {
2395 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2396 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2397 };
2398 static const char *intel_names32[] = {
2399 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2400 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2401 };
2402 static const char *intel_names16[] = {
2403 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2404 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2405 };
2406 static const char *intel_names8[] = {
2407 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2408 };
2409 static const char *intel_names8rex[] = {
2410 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2411 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2412 };
2413 static const char *intel_names_seg[] = {
2414 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2415 };
2416 static const char *intel_index64 = "riz";
2417 static const char *intel_index32 = "eiz";
2418 static const char *intel_index16[] = {
2419 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2420 };
2421
2422 static const char *att_names64[] = {
2423 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2424 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2425 };
2426 static const char *att_names32[] = {
2427 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2428 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2429 };
2430 static const char *att_names16[] = {
2431 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2432 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2433 };
2434 static const char *att_names8[] = {
2435 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2436 };
2437 static const char *att_names8rex[] = {
2438 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2439 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2440 };
2441 static const char *att_names_seg[] = {
2442 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2443 };
2444 static const char *att_index64 = "%riz";
2445 static const char *att_index32 = "%eiz";
2446 static const char *att_index16[] = {
2447 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2448 };
2449
2450 static const char **names_mm;
2451 static const char *intel_names_mm[] = {
2452 "mm0", "mm1", "mm2", "mm3",
2453 "mm4", "mm5", "mm6", "mm7"
2454 };
2455 static const char *att_names_mm[] = {
2456 "%mm0", "%mm1", "%mm2", "%mm3",
2457 "%mm4", "%mm5", "%mm6", "%mm7"
2458 };
2459
2460 static const char *intel_names_bnd[] = {
2461 "bnd0", "bnd1", "bnd2", "bnd3"
2462 };
2463
2464 static const char *att_names_bnd[] = {
2465 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2466 };
2467
2468 static const char **names_xmm;
2469 static const char *intel_names_xmm[] = {
2470 "xmm0", "xmm1", "xmm2", "xmm3",
2471 "xmm4", "xmm5", "xmm6", "xmm7",
2472 "xmm8", "xmm9", "xmm10", "xmm11",
2473 "xmm12", "xmm13", "xmm14", "xmm15",
2474 "xmm16", "xmm17", "xmm18", "xmm19",
2475 "xmm20", "xmm21", "xmm22", "xmm23",
2476 "xmm24", "xmm25", "xmm26", "xmm27",
2477 "xmm28", "xmm29", "xmm30", "xmm31"
2478 };
2479 static const char *att_names_xmm[] = {
2480 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2481 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2482 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2483 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2484 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2485 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2486 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2487 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2488 };
2489
2490 static const char **names_ymm;
2491 static const char *intel_names_ymm[] = {
2492 "ymm0", "ymm1", "ymm2", "ymm3",
2493 "ymm4", "ymm5", "ymm6", "ymm7",
2494 "ymm8", "ymm9", "ymm10", "ymm11",
2495 "ymm12", "ymm13", "ymm14", "ymm15",
2496 "ymm16", "ymm17", "ymm18", "ymm19",
2497 "ymm20", "ymm21", "ymm22", "ymm23",
2498 "ymm24", "ymm25", "ymm26", "ymm27",
2499 "ymm28", "ymm29", "ymm30", "ymm31"
2500 };
2501 static const char *att_names_ymm[] = {
2502 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2503 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2504 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2505 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2506 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2507 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2508 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2509 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2510 };
2511
2512 static const char **names_zmm;
2513 static const char *intel_names_zmm[] = {
2514 "zmm0", "zmm1", "zmm2", "zmm3",
2515 "zmm4", "zmm5", "zmm6", "zmm7",
2516 "zmm8", "zmm9", "zmm10", "zmm11",
2517 "zmm12", "zmm13", "zmm14", "zmm15",
2518 "zmm16", "zmm17", "zmm18", "zmm19",
2519 "zmm20", "zmm21", "zmm22", "zmm23",
2520 "zmm24", "zmm25", "zmm26", "zmm27",
2521 "zmm28", "zmm29", "zmm30", "zmm31"
2522 };
2523 static const char *att_names_zmm[] = {
2524 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2525 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2526 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2527 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2528 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2529 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2530 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2531 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2532 };
2533
2534 static const char **names_tmm;
2535 static const char *intel_names_tmm[] = {
2536 "tmm0", "tmm1", "tmm2", "tmm3",
2537 "tmm4", "tmm5", "tmm6", "tmm7"
2538 };
2539 static const char *att_names_tmm[] = {
2540 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2541 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2542 };
2543
2544 static const char **names_mask;
2545 static const char *intel_names_mask[] = {
2546 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2547 };
2548 static const char *att_names_mask[] = {
2549 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2550 };
2551
2552 static const char *names_rounding[] =
2553 {
2554 "{rn-sae}",
2555 "{rd-sae}",
2556 "{ru-sae}",
2557 "{rz-sae}"
2558 };
2559
2560 static const struct dis386 reg_table[][8] = {
2561 /* REG_80 */
2562 {
2563 { "addA", { Ebh1, Ib }, 0 },
2564 { "orA", { Ebh1, Ib }, 0 },
2565 { "adcA", { Ebh1, Ib }, 0 },
2566 { "sbbA", { Ebh1, Ib }, 0 },
2567 { "andA", { Ebh1, Ib }, 0 },
2568 { "subA", { Ebh1, Ib }, 0 },
2569 { "xorA", { Ebh1, Ib }, 0 },
2570 { "cmpA", { Eb, Ib }, 0 },
2571 },
2572 /* REG_81 */
2573 {
2574 { "addQ", { Evh1, Iv }, 0 },
2575 { "orQ", { Evh1, Iv }, 0 },
2576 { "adcQ", { Evh1, Iv }, 0 },
2577 { "sbbQ", { Evh1, Iv }, 0 },
2578 { "andQ", { Evh1, Iv }, 0 },
2579 { "subQ", { Evh1, Iv }, 0 },
2580 { "xorQ", { Evh1, Iv }, 0 },
2581 { "cmpQ", { Ev, Iv }, 0 },
2582 },
2583 /* REG_83 */
2584 {
2585 { "addQ", { Evh1, sIb }, 0 },
2586 { "orQ", { Evh1, sIb }, 0 },
2587 { "adcQ", { Evh1, sIb }, 0 },
2588 { "sbbQ", { Evh1, sIb }, 0 },
2589 { "andQ", { Evh1, sIb }, 0 },
2590 { "subQ", { Evh1, sIb }, 0 },
2591 { "xorQ", { Evh1, sIb }, 0 },
2592 { "cmpQ", { Ev, sIb }, 0 },
2593 },
2594 /* REG_8F */
2595 {
2596 { "pop{P|}", { stackEv }, 0 },
2597 { XOP_8F_TABLE (XOP_09) },
2598 { Bad_Opcode },
2599 { Bad_Opcode },
2600 { Bad_Opcode },
2601 { XOP_8F_TABLE (XOP_09) },
2602 },
2603 /* REG_C0 */
2604 {
2605 { "rolA", { Eb, Ib }, 0 },
2606 { "rorA", { Eb, Ib }, 0 },
2607 { "rclA", { Eb, Ib }, 0 },
2608 { "rcrA", { Eb, Ib }, 0 },
2609 { "shlA", { Eb, Ib }, 0 },
2610 { "shrA", { Eb, Ib }, 0 },
2611 { "shlA", { Eb, Ib }, 0 },
2612 { "sarA", { Eb, Ib }, 0 },
2613 },
2614 /* REG_C1 */
2615 {
2616 { "rolQ", { Ev, Ib }, 0 },
2617 { "rorQ", { Ev, Ib }, 0 },
2618 { "rclQ", { Ev, Ib }, 0 },
2619 { "rcrQ", { Ev, Ib }, 0 },
2620 { "shlQ", { Ev, Ib }, 0 },
2621 { "shrQ", { Ev, Ib }, 0 },
2622 { "shlQ", { Ev, Ib }, 0 },
2623 { "sarQ", { Ev, Ib }, 0 },
2624 },
2625 /* REG_C6 */
2626 {
2627 { "movA", { Ebh3, Ib }, 0 },
2628 { Bad_Opcode },
2629 { Bad_Opcode },
2630 { Bad_Opcode },
2631 { Bad_Opcode },
2632 { Bad_Opcode },
2633 { Bad_Opcode },
2634 { MOD_TABLE (MOD_C6_REG_7) },
2635 },
2636 /* REG_C7 */
2637 {
2638 { "movQ", { Evh3, Iv }, 0 },
2639 { Bad_Opcode },
2640 { Bad_Opcode },
2641 { Bad_Opcode },
2642 { Bad_Opcode },
2643 { Bad_Opcode },
2644 { Bad_Opcode },
2645 { MOD_TABLE (MOD_C7_REG_7) },
2646 },
2647 /* REG_D0 */
2648 {
2649 { "rolA", { Eb, I1 }, 0 },
2650 { "rorA", { Eb, I1 }, 0 },
2651 { "rclA", { Eb, I1 }, 0 },
2652 { "rcrA", { Eb, I1 }, 0 },
2653 { "shlA", { Eb, I1 }, 0 },
2654 { "shrA", { Eb, I1 }, 0 },
2655 { "shlA", { Eb, I1 }, 0 },
2656 { "sarA", { Eb, I1 }, 0 },
2657 },
2658 /* REG_D1 */
2659 {
2660 { "rolQ", { Ev, I1 }, 0 },
2661 { "rorQ", { Ev, I1 }, 0 },
2662 { "rclQ", { Ev, I1 }, 0 },
2663 { "rcrQ", { Ev, I1 }, 0 },
2664 { "shlQ", { Ev, I1 }, 0 },
2665 { "shrQ", { Ev, I1 }, 0 },
2666 { "shlQ", { Ev, I1 }, 0 },
2667 { "sarQ", { Ev, I1 }, 0 },
2668 },
2669 /* REG_D2 */
2670 {
2671 { "rolA", { Eb, CL }, 0 },
2672 { "rorA", { Eb, CL }, 0 },
2673 { "rclA", { Eb, CL }, 0 },
2674 { "rcrA", { Eb, CL }, 0 },
2675 { "shlA", { Eb, CL }, 0 },
2676 { "shrA", { Eb, CL }, 0 },
2677 { "shlA", { Eb, CL }, 0 },
2678 { "sarA", { Eb, CL }, 0 },
2679 },
2680 /* REG_D3 */
2681 {
2682 { "rolQ", { Ev, CL }, 0 },
2683 { "rorQ", { Ev, CL }, 0 },
2684 { "rclQ", { Ev, CL }, 0 },
2685 { "rcrQ", { Ev, CL }, 0 },
2686 { "shlQ", { Ev, CL }, 0 },
2687 { "shrQ", { Ev, CL }, 0 },
2688 { "shlQ", { Ev, CL }, 0 },
2689 { "sarQ", { Ev, CL }, 0 },
2690 },
2691 /* REG_F6 */
2692 {
2693 { "testA", { Eb, Ib }, 0 },
2694 { "testA", { Eb, Ib }, 0 },
2695 { "notA", { Ebh1 }, 0 },
2696 { "negA", { Ebh1 }, 0 },
2697 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2698 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2699 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2700 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2701 },
2702 /* REG_F7 */
2703 {
2704 { "testQ", { Ev, Iv }, 0 },
2705 { "testQ", { Ev, Iv }, 0 },
2706 { "notQ", { Evh1 }, 0 },
2707 { "negQ", { Evh1 }, 0 },
2708 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2709 { "imulQ", { Ev }, 0 },
2710 { "divQ", { Ev }, 0 },
2711 { "idivQ", { Ev }, 0 },
2712 },
2713 /* REG_FE */
2714 {
2715 { "incA", { Ebh1 }, 0 },
2716 { "decA", { Ebh1 }, 0 },
2717 },
2718 /* REG_FF */
2719 {
2720 { "incQ", { Evh1 }, 0 },
2721 { "decQ", { Evh1 }, 0 },
2722 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2723 { MOD_TABLE (MOD_FF_REG_3) },
2724 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2725 { MOD_TABLE (MOD_FF_REG_5) },
2726 { "push{P|}", { stackEv }, 0 },
2727 { Bad_Opcode },
2728 },
2729 /* REG_0F00 */
2730 {
2731 { "sldtD", { Sv }, 0 },
2732 { "strD", { Sv }, 0 },
2733 { "lldt", { Ew }, 0 },
2734 { "ltr", { Ew }, 0 },
2735 { "verr", { Ew }, 0 },
2736 { "verw", { Ew }, 0 },
2737 { Bad_Opcode },
2738 { Bad_Opcode },
2739 },
2740 /* REG_0F01 */
2741 {
2742 { MOD_TABLE (MOD_0F01_REG_0) },
2743 { MOD_TABLE (MOD_0F01_REG_1) },
2744 { MOD_TABLE (MOD_0F01_REG_2) },
2745 { MOD_TABLE (MOD_0F01_REG_3) },
2746 { "smswD", { Sv }, 0 },
2747 { MOD_TABLE (MOD_0F01_REG_5) },
2748 { "lmsw", { Ew }, 0 },
2749 { MOD_TABLE (MOD_0F01_REG_7) },
2750 },
2751 /* REG_0F0D */
2752 {
2753 { "prefetch", { Mb }, 0 },
2754 { "prefetchw", { Mb }, 0 },
2755 { "prefetchwt1", { Mb }, 0 },
2756 { "prefetch", { Mb }, 0 },
2757 { "prefetch", { Mb }, 0 },
2758 { "prefetch", { Mb }, 0 },
2759 { "prefetch", { Mb }, 0 },
2760 { "prefetch", { Mb }, 0 },
2761 },
2762 /* REG_0F18 */
2763 {
2764 { MOD_TABLE (MOD_0F18_REG_0) },
2765 { MOD_TABLE (MOD_0F18_REG_1) },
2766 { MOD_TABLE (MOD_0F18_REG_2) },
2767 { MOD_TABLE (MOD_0F18_REG_3) },
2768 { "nopQ", { Ev }, 0 },
2769 { "nopQ", { Ev }, 0 },
2770 { "nopQ", { Ev }, 0 },
2771 { "nopQ", { Ev }, 0 },
2772 },
2773 /* REG_0F1C_P_0_MOD_0 */
2774 {
2775 { "cldemote", { Mb }, 0 },
2776 { "nopQ", { Ev }, 0 },
2777 { "nopQ", { Ev }, 0 },
2778 { "nopQ", { Ev }, 0 },
2779 { "nopQ", { Ev }, 0 },
2780 { "nopQ", { Ev }, 0 },
2781 { "nopQ", { Ev }, 0 },
2782 { "nopQ", { Ev }, 0 },
2783 },
2784 /* REG_0F1E_P_1_MOD_3 */
2785 {
2786 { "nopQ", { Ev }, PREFIX_IGNORED },
2787 { "rdsspK", { Edq }, 0 },
2788 { "nopQ", { Ev }, PREFIX_IGNORED },
2789 { "nopQ", { Ev }, PREFIX_IGNORED },
2790 { "nopQ", { Ev }, PREFIX_IGNORED },
2791 { "nopQ", { Ev }, PREFIX_IGNORED },
2792 { "nopQ", { Ev }, PREFIX_IGNORED },
2793 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2794 },
2795 /* REG_0F38D8_PREFIX_1 */
2796 {
2797 { "aesencwide128kl", { M }, 0 },
2798 { "aesdecwide128kl", { M }, 0 },
2799 { "aesencwide256kl", { M }, 0 },
2800 { "aesdecwide256kl", { M }, 0 },
2801 },
2802 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2803 {
2804 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2805 },
2806 /* REG_0F71_MOD_0 */
2807 {
2808 { Bad_Opcode },
2809 { Bad_Opcode },
2810 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
2811 { Bad_Opcode },
2812 { "psraw", { MS, Ib }, PREFIX_OPCODE },
2813 { Bad_Opcode },
2814 { "psllw", { MS, Ib }, PREFIX_OPCODE },
2815 },
2816 /* REG_0F72_MOD_0 */
2817 {
2818 { Bad_Opcode },
2819 { Bad_Opcode },
2820 { "psrld", { MS, Ib }, PREFIX_OPCODE },
2821 { Bad_Opcode },
2822 { "psrad", { MS, Ib }, PREFIX_OPCODE },
2823 { Bad_Opcode },
2824 { "pslld", { MS, Ib }, PREFIX_OPCODE },
2825 },
2826 /* REG_0F73_MOD_0 */
2827 {
2828 { Bad_Opcode },
2829 { Bad_Opcode },
2830 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
2831 { "psrldq", { XS, Ib }, PREFIX_DATA },
2832 { Bad_Opcode },
2833 { Bad_Opcode },
2834 { "psllq", { MS, Ib }, PREFIX_OPCODE },
2835 { "pslldq", { XS, Ib }, PREFIX_DATA },
2836 },
2837 /* REG_0FA6 */
2838 {
2839 { "montmul", { { OP_0f07, 0 } }, 0 },
2840 { "xsha1", { { OP_0f07, 0 } }, 0 },
2841 { "xsha256", { { OP_0f07, 0 } }, 0 },
2842 },
2843 /* REG_0FA7 */
2844 {
2845 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2846 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2847 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2848 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2849 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2850 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2851 },
2852 /* REG_0FAE */
2853 {
2854 { MOD_TABLE (MOD_0FAE_REG_0) },
2855 { MOD_TABLE (MOD_0FAE_REG_1) },
2856 { MOD_TABLE (MOD_0FAE_REG_2) },
2857 { MOD_TABLE (MOD_0FAE_REG_3) },
2858 { MOD_TABLE (MOD_0FAE_REG_4) },
2859 { MOD_TABLE (MOD_0FAE_REG_5) },
2860 { MOD_TABLE (MOD_0FAE_REG_6) },
2861 { MOD_TABLE (MOD_0FAE_REG_7) },
2862 },
2863 /* REG_0FBA */
2864 {
2865 { Bad_Opcode },
2866 { Bad_Opcode },
2867 { Bad_Opcode },
2868 { Bad_Opcode },
2869 { "btQ", { Ev, Ib }, 0 },
2870 { "btsQ", { Evh1, Ib }, 0 },
2871 { "btrQ", { Evh1, Ib }, 0 },
2872 { "btcQ", { Evh1, Ib }, 0 },
2873 },
2874 /* REG_0FC7 */
2875 {
2876 { Bad_Opcode },
2877 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2878 { Bad_Opcode },
2879 { MOD_TABLE (MOD_0FC7_REG_3) },
2880 { MOD_TABLE (MOD_0FC7_REG_4) },
2881 { MOD_TABLE (MOD_0FC7_REG_5) },
2882 { MOD_TABLE (MOD_0FC7_REG_6) },
2883 { MOD_TABLE (MOD_0FC7_REG_7) },
2884 },
2885 /* REG_VEX_0F71_M_0 */
2886 {
2887 { Bad_Opcode },
2888 { Bad_Opcode },
2889 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
2890 { Bad_Opcode },
2891 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
2892 { Bad_Opcode },
2893 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
2894 },
2895 /* REG_VEX_0F72_M_0 */
2896 {
2897 { Bad_Opcode },
2898 { Bad_Opcode },
2899 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
2900 { Bad_Opcode },
2901 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
2902 { Bad_Opcode },
2903 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
2904 },
2905 /* REG_VEX_0F73_M_0 */
2906 {
2907 { Bad_Opcode },
2908 { Bad_Opcode },
2909 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
2910 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
2911 { Bad_Opcode },
2912 { Bad_Opcode },
2913 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
2914 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
2915 },
2916 /* REG_VEX_0FAE */
2917 {
2918 { Bad_Opcode },
2919 { Bad_Opcode },
2920 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2921 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2922 },
2923 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2924 {
2925 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2926 },
2927 /* REG_VEX_0F38F3_L_0 */
2928 {
2929 { Bad_Opcode },
2930 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
2931 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
2932 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
2933 },
2934 /* REG_XOP_09_01_L_0 */
2935 {
2936 { Bad_Opcode },
2937 { "blcfill", { VexGdq, Edq }, 0 },
2938 { "blsfill", { VexGdq, Edq }, 0 },
2939 { "blcs", { VexGdq, Edq }, 0 },
2940 { "tzmsk", { VexGdq, Edq }, 0 },
2941 { "blcic", { VexGdq, Edq }, 0 },
2942 { "blsic", { VexGdq, Edq }, 0 },
2943 { "t1mskc", { VexGdq, Edq }, 0 },
2944 },
2945 /* REG_XOP_09_02_L_0 */
2946 {
2947 { Bad_Opcode },
2948 { "blcmsk", { VexGdq, Edq }, 0 },
2949 { Bad_Opcode },
2950 { Bad_Opcode },
2951 { Bad_Opcode },
2952 { Bad_Opcode },
2953 { "blci", { VexGdq, Edq }, 0 },
2954 },
2955 /* REG_XOP_09_12_M_1_L_0 */
2956 {
2957 { "llwpcb", { Edq }, 0 },
2958 { "slwpcb", { Edq }, 0 },
2959 },
2960 /* REG_XOP_0A_12_L_0 */
2961 {
2962 { "lwpins", { VexGdq, Ed, Id }, 0 },
2963 { "lwpval", { VexGdq, Ed, Id }, 0 },
2964 },
2965
2966 #include "i386-dis-evex-reg.h"
2967 };
2968
2969 static const struct dis386 prefix_table[][4] = {
2970 /* PREFIX_90 */
2971 {
2972 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
2973 { "pause", { XX }, 0 },
2974 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
2975 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2976 },
2977
2978 /* PREFIX_0F01_REG_1_RM_4 */
2979 {
2980 { Bad_Opcode },
2981 { Bad_Opcode },
2982 { "tdcall", { Skip_MODRM }, 0 },
2983 { Bad_Opcode },
2984 },
2985
2986 /* PREFIX_0F01_REG_1_RM_5 */
2987 {
2988 { Bad_Opcode },
2989 { Bad_Opcode },
2990 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2991 { Bad_Opcode },
2992 },
2993
2994 /* PREFIX_0F01_REG_1_RM_6 */
2995 {
2996 { Bad_Opcode },
2997 { Bad_Opcode },
2998 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
2999 { Bad_Opcode },
3000 },
3001
3002 /* PREFIX_0F01_REG_1_RM_7 */
3003 {
3004 { "encls", { Skip_MODRM }, 0 },
3005 { Bad_Opcode },
3006 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3007 { Bad_Opcode },
3008 },
3009
3010 /* PREFIX_0F01_REG_3_RM_1 */
3011 {
3012 { "vmmcall", { Skip_MODRM }, 0 },
3013 { "vmgexit", { Skip_MODRM }, 0 },
3014 { Bad_Opcode },
3015 { "vmgexit", { Skip_MODRM }, 0 },
3016 },
3017
3018 /* PREFIX_0F01_REG_5_MOD_0 */
3019 {
3020 { Bad_Opcode },
3021 { "rstorssp", { Mq }, PREFIX_OPCODE },
3022 },
3023
3024 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3025 {
3026 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3027 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3028 { Bad_Opcode },
3029 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3030 },
3031
3032 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3033 {
3034 { Bad_Opcode },
3035 { Bad_Opcode },
3036 { Bad_Opcode },
3037 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3038 },
3039
3040 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3041 {
3042 { Bad_Opcode },
3043 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3044 },
3045
3046 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3047 {
3048 { Bad_Opcode },
3049 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3050 },
3051
3052 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3053 {
3054 { Bad_Opcode },
3055 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3056 },
3057
3058 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3059 {
3060 { "rdpkru", { Skip_MODRM }, 0 },
3061 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3062 },
3063
3064 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3065 {
3066 { "wrpkru", { Skip_MODRM }, 0 },
3067 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3068 },
3069
3070 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3071 {
3072 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3073 { "mcommit", { Skip_MODRM }, 0 },
3074 },
3075
3076 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3077 {
3078 { "invlpgb", { Skip_MODRM }, 0 },
3079 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3080 { Bad_Opcode },
3081 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3082 },
3083
3084 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3085 {
3086 { "tlbsync", { Skip_MODRM }, 0 },
3087 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3088 { Bad_Opcode },
3089 { "pvalidate", { Skip_MODRM }, 0 },
3090 },
3091
3092 /* PREFIX_0F09 */
3093 {
3094 { "wbinvd", { XX }, 0 },
3095 { "wbnoinvd", { XX }, 0 },
3096 },
3097
3098 /* PREFIX_0F10 */
3099 {
3100 { "movups", { XM, EXx }, PREFIX_OPCODE },
3101 { "movss", { XM, EXd }, PREFIX_OPCODE },
3102 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3103 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3104 },
3105
3106 /* PREFIX_0F11 */
3107 {
3108 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3109 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3110 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3111 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3112 },
3113
3114 /* PREFIX_0F12 */
3115 {
3116 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3117 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3118 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3119 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3120 },
3121
3122 /* PREFIX_0F16 */
3123 {
3124 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3125 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3126 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3127 },
3128
3129 /* PREFIX_0F1A */
3130 {
3131 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3132 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3133 { "bndmov", { Gbnd, Ebnd }, 0 },
3134 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3135 },
3136
3137 /* PREFIX_0F1B */
3138 {
3139 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3140 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3141 { "bndmov", { EbndS, Gbnd }, 0 },
3142 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3143 },
3144
3145 /* PREFIX_0F1C */
3146 {
3147 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3148 { "nopQ", { Ev }, PREFIX_IGNORED },
3149 { "nopQ", { Ev }, 0 },
3150 { "nopQ", { Ev }, PREFIX_IGNORED },
3151 },
3152
3153 /* PREFIX_0F1E */
3154 {
3155 { "nopQ", { Ev }, 0 },
3156 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3157 { "nopQ", { Ev }, 0 },
3158 { NULL, { XX }, PREFIX_IGNORED },
3159 },
3160
3161 /* PREFIX_0F2A */
3162 {
3163 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3164 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3165 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3166 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3167 },
3168
3169 /* PREFIX_0F2B */
3170 {
3171 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3172 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3173 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3174 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3175 },
3176
3177 /* PREFIX_0F2C */
3178 {
3179 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3180 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3181 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3182 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3183 },
3184
3185 /* PREFIX_0F2D */
3186 {
3187 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3188 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3189 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3190 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3191 },
3192
3193 /* PREFIX_0F2E */
3194 {
3195 { "ucomiss",{ XM, EXd }, 0 },
3196 { Bad_Opcode },
3197 { "ucomisd",{ XM, EXq }, 0 },
3198 },
3199
3200 /* PREFIX_0F2F */
3201 {
3202 { "comiss", { XM, EXd }, 0 },
3203 { Bad_Opcode },
3204 { "comisd", { XM, EXq }, 0 },
3205 },
3206
3207 /* PREFIX_0F51 */
3208 {
3209 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3210 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3211 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3212 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3213 },
3214
3215 /* PREFIX_0F52 */
3216 {
3217 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3218 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3219 },
3220
3221 /* PREFIX_0F53 */
3222 {
3223 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3224 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3225 },
3226
3227 /* PREFIX_0F58 */
3228 {
3229 { "addps", { XM, EXx }, PREFIX_OPCODE },
3230 { "addss", { XM, EXd }, PREFIX_OPCODE },
3231 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3232 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3233 },
3234
3235 /* PREFIX_0F59 */
3236 {
3237 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3238 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3239 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3240 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3241 },
3242
3243 /* PREFIX_0F5A */
3244 {
3245 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3246 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3247 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3248 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3249 },
3250
3251 /* PREFIX_0F5B */
3252 {
3253 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3254 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3255 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3256 },
3257
3258 /* PREFIX_0F5C */
3259 {
3260 { "subps", { XM, EXx }, PREFIX_OPCODE },
3261 { "subss", { XM, EXd }, PREFIX_OPCODE },
3262 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3263 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3264 },
3265
3266 /* PREFIX_0F5D */
3267 {
3268 { "minps", { XM, EXx }, PREFIX_OPCODE },
3269 { "minss", { XM, EXd }, PREFIX_OPCODE },
3270 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3271 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3272 },
3273
3274 /* PREFIX_0F5E */
3275 {
3276 { "divps", { XM, EXx }, PREFIX_OPCODE },
3277 { "divss", { XM, EXd }, PREFIX_OPCODE },
3278 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3279 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3280 },
3281
3282 /* PREFIX_0F5F */
3283 {
3284 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3285 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3286 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3287 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3288 },
3289
3290 /* PREFIX_0F60 */
3291 {
3292 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3293 { Bad_Opcode },
3294 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3295 },
3296
3297 /* PREFIX_0F61 */
3298 {
3299 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3300 { Bad_Opcode },
3301 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3302 },
3303
3304 /* PREFIX_0F62 */
3305 {
3306 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3307 { Bad_Opcode },
3308 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3309 },
3310
3311 /* PREFIX_0F6F */
3312 {
3313 { "movq", { MX, EM }, PREFIX_OPCODE },
3314 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3315 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3316 },
3317
3318 /* PREFIX_0F70 */
3319 {
3320 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3321 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3322 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3323 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3324 },
3325
3326 /* PREFIX_0F78 */
3327 {
3328 {"vmread", { Em, Gm }, 0 },
3329 { Bad_Opcode },
3330 {"extrq", { XS, Ib, Ib }, 0 },
3331 {"insertq", { XM, XS, Ib, Ib }, 0 },
3332 },
3333
3334 /* PREFIX_0F79 */
3335 {
3336 {"vmwrite", { Gm, Em }, 0 },
3337 { Bad_Opcode },
3338 {"extrq", { XM, XS }, 0 },
3339 {"insertq", { XM, XS }, 0 },
3340 },
3341
3342 /* PREFIX_0F7C */
3343 {
3344 { Bad_Opcode },
3345 { Bad_Opcode },
3346 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3347 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3348 },
3349
3350 /* PREFIX_0F7D */
3351 {
3352 { Bad_Opcode },
3353 { Bad_Opcode },
3354 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3355 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3356 },
3357
3358 /* PREFIX_0F7E */
3359 {
3360 { "movK", { Edq, MX }, PREFIX_OPCODE },
3361 { "movq", { XM, EXq }, PREFIX_OPCODE },
3362 { "movK", { Edq, XM }, PREFIX_OPCODE },
3363 },
3364
3365 /* PREFIX_0F7F */
3366 {
3367 { "movq", { EMS, MX }, PREFIX_OPCODE },
3368 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3369 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3370 },
3371
3372 /* PREFIX_0FAE_REG_0_MOD_3 */
3373 {
3374 { Bad_Opcode },
3375 { "rdfsbase", { Ev }, 0 },
3376 },
3377
3378 /* PREFIX_0FAE_REG_1_MOD_3 */
3379 {
3380 { Bad_Opcode },
3381 { "rdgsbase", { Ev }, 0 },
3382 },
3383
3384 /* PREFIX_0FAE_REG_2_MOD_3 */
3385 {
3386 { Bad_Opcode },
3387 { "wrfsbase", { Ev }, 0 },
3388 },
3389
3390 /* PREFIX_0FAE_REG_3_MOD_3 */
3391 {
3392 { Bad_Opcode },
3393 { "wrgsbase", { Ev }, 0 },
3394 },
3395
3396 /* PREFIX_0FAE_REG_4_MOD_0 */
3397 {
3398 { "xsave", { FXSAVE }, 0 },
3399 { "ptwrite{%LQ|}", { Edq }, 0 },
3400 },
3401
3402 /* PREFIX_0FAE_REG_4_MOD_3 */
3403 {
3404 { Bad_Opcode },
3405 { "ptwrite{%LQ|}", { Edq }, 0 },
3406 },
3407
3408 /* PREFIX_0FAE_REG_5_MOD_3 */
3409 {
3410 { "lfence", { Skip_MODRM }, 0 },
3411 { "incsspK", { Edq }, PREFIX_OPCODE },
3412 },
3413
3414 /* PREFIX_0FAE_REG_6_MOD_0 */
3415 {
3416 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3417 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3418 { "clwb", { Mb }, PREFIX_OPCODE },
3419 },
3420
3421 /* PREFIX_0FAE_REG_6_MOD_3 */
3422 {
3423 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3424 { "umonitor", { Eva }, PREFIX_OPCODE },
3425 { "tpause", { Edq }, PREFIX_OPCODE },
3426 { "umwait", { Edq }, PREFIX_OPCODE },
3427 },
3428
3429 /* PREFIX_0FAE_REG_7_MOD_0 */
3430 {
3431 { "clflush", { Mb }, 0 },
3432 { Bad_Opcode },
3433 { "clflushopt", { Mb }, 0 },
3434 },
3435
3436 /* PREFIX_0FB8 */
3437 {
3438 { Bad_Opcode },
3439 { "popcntS", { Gv, Ev }, 0 },
3440 },
3441
3442 /* PREFIX_0FBC */
3443 {
3444 { "bsfS", { Gv, Ev }, 0 },
3445 { "tzcntS", { Gv, Ev }, 0 },
3446 { "bsfS", { Gv, Ev }, 0 },
3447 },
3448
3449 /* PREFIX_0FBD */
3450 {
3451 { "bsrS", { Gv, Ev }, 0 },
3452 { "lzcntS", { Gv, Ev }, 0 },
3453 { "bsrS", { Gv, Ev }, 0 },
3454 },
3455
3456 /* PREFIX_0FC2 */
3457 {
3458 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3459 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3460 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3461 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3462 },
3463
3464 /* PREFIX_0FC7_REG_6_MOD_0 */
3465 {
3466 { "vmptrld",{ Mq }, 0 },
3467 { "vmxon", { Mq }, 0 },
3468 { "vmclear",{ Mq }, 0 },
3469 },
3470
3471 /* PREFIX_0FC7_REG_6_MOD_3 */
3472 {
3473 { "rdrand", { Ev }, 0 },
3474 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3475 { "rdrand", { Ev }, 0 }
3476 },
3477
3478 /* PREFIX_0FC7_REG_7_MOD_3 */
3479 {
3480 { "rdseed", { Ev }, 0 },
3481 { "rdpid", { Em }, 0 },
3482 { "rdseed", { Ev }, 0 },
3483 },
3484
3485 /* PREFIX_0FD0 */
3486 {
3487 { Bad_Opcode },
3488 { Bad_Opcode },
3489 { "addsubpd", { XM, EXx }, 0 },
3490 { "addsubps", { XM, EXx }, 0 },
3491 },
3492
3493 /* PREFIX_0FD6 */
3494 {
3495 { Bad_Opcode },
3496 { "movq2dq",{ XM, MS }, 0 },
3497 { "movq", { EXqS, XM }, 0 },
3498 { "movdq2q",{ MX, XS }, 0 },
3499 },
3500
3501 /* PREFIX_0FE6 */
3502 {
3503 { Bad_Opcode },
3504 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3505 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3506 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3507 },
3508
3509 /* PREFIX_0FE7 */
3510 {
3511 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3512 { Bad_Opcode },
3513 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3514 },
3515
3516 /* PREFIX_0FF0 */
3517 {
3518 { Bad_Opcode },
3519 { Bad_Opcode },
3520 { Bad_Opcode },
3521 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3522 },
3523
3524 /* PREFIX_0FF7 */
3525 {
3526 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3527 { Bad_Opcode },
3528 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3529 },
3530
3531 /* PREFIX_0F38D8 */
3532 {
3533 { Bad_Opcode },
3534 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3535 },
3536
3537 /* PREFIX_0F38DC */
3538 {
3539 { Bad_Opcode },
3540 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3541 { "aesenc", { XM, EXx }, 0 },
3542 },
3543
3544 /* PREFIX_0F38DD */
3545 {
3546 { Bad_Opcode },
3547 { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3548 { "aesenclast", { XM, EXx }, 0 },
3549 },
3550
3551 /* PREFIX_0F38DE */
3552 {
3553 { Bad_Opcode },
3554 { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3555 { "aesdec", { XM, EXx }, 0 },
3556 },
3557
3558 /* PREFIX_0F38DF */
3559 {
3560 { Bad_Opcode },
3561 { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3562 { "aesdeclast", { XM, EXx }, 0 },
3563 },
3564
3565 /* PREFIX_0F38F0 */
3566 {
3567 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3568 { Bad_Opcode },
3569 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3570 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3571 },
3572
3573 /* PREFIX_0F38F1 */
3574 {
3575 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3576 { Bad_Opcode },
3577 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3578 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3579 },
3580
3581 /* PREFIX_0F38F6 */
3582 {
3583 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3584 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3585 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3586 { Bad_Opcode },
3587 },
3588
3589 /* PREFIX_0F38F8 */
3590 {
3591 { Bad_Opcode },
3592 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3593 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3594 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3595 },
3596 /* PREFIX_0F38FA */
3597 {
3598 { Bad_Opcode },
3599 { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3600 },
3601
3602 /* PREFIX_0F38FB */
3603 {
3604 { Bad_Opcode },
3605 { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3606 },
3607
3608 /* PREFIX_0F3A0F */
3609 {
3610 { Bad_Opcode },
3611 { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3612 },
3613
3614 /* PREFIX_VEX_0F10 */
3615 {
3616 { "vmovups", { XM, EXx }, 0 },
3617 { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
3618 { "vmovupd", { XM, EXx }, 0 },
3619 { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3620 },
3621
3622 /* PREFIX_VEX_0F11 */
3623 {
3624 { "vmovups", { EXxS, XM }, 0 },
3625 { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
3626 { "vmovupd", { EXxS, XM }, 0 },
3627 { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
3628 },
3629
3630 /* PREFIX_VEX_0F12 */
3631 {
3632 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3633 { "vmovsldup", { XM, EXx }, 0 },
3634 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3635 { "vmovddup", { XM, EXymmq }, 0 },
3636 },
3637
3638 /* PREFIX_VEX_0F16 */
3639 {
3640 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3641 { "vmovshdup", { XM, EXx }, 0 },
3642 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3643 },
3644
3645 /* PREFIX_VEX_0F2A */
3646 {
3647 { Bad_Opcode },
3648 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3649 { Bad_Opcode },
3650 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3651 },
3652
3653 /* PREFIX_VEX_0F2C */
3654 {
3655 { Bad_Opcode },
3656 { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
3657 { Bad_Opcode },
3658 { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3659 },
3660
3661 /* PREFIX_VEX_0F2D */
3662 {
3663 { Bad_Opcode },
3664 { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
3665 { Bad_Opcode },
3666 { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3667 },
3668
3669 /* PREFIX_VEX_0F2E */
3670 {
3671 { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3672 { Bad_Opcode },
3673 { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3674 },
3675
3676 /* PREFIX_VEX_0F2F */
3677 {
3678 { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3679 { Bad_Opcode },
3680 { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3681 },
3682
3683 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3684 {
3685 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
3686 { Bad_Opcode },
3687 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
3688 },
3689
3690 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3691 {
3692 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
3693 { Bad_Opcode },
3694 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
3695 },
3696
3697 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3698 {
3699 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
3700 { Bad_Opcode },
3701 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
3702 },
3703
3704 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3705 {
3706 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
3707 { Bad_Opcode },
3708 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
3709 },
3710
3711 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3712 {
3713 { "knotw", { MaskG, MaskE }, 0 },
3714 { Bad_Opcode },
3715 { "knotb", { MaskG, MaskE }, 0 },
3716 },
3717
3718 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3719 {
3720 { "knotq", { MaskG, MaskE }, 0 },
3721 { Bad_Opcode },
3722 { "knotd", { MaskG, MaskE }, 0 },
3723 },
3724
3725 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3726 {
3727 { "korw", { MaskG, MaskVex, MaskE }, 0 },
3728 { Bad_Opcode },
3729 { "korb", { MaskG, MaskVex, MaskE }, 0 },
3730 },
3731
3732 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3733 {
3734 { "korq", { MaskG, MaskVex, MaskE }, 0 },
3735 { Bad_Opcode },
3736 { "kord", { MaskG, MaskVex, MaskE }, 0 },
3737 },
3738
3739 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3740 {
3741 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
3742 { Bad_Opcode },
3743 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
3744 },
3745
3746 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3747 {
3748 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
3749 { Bad_Opcode },
3750 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
3751 },
3752
3753 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3754 {
3755 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
3756 { Bad_Opcode },
3757 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
3758 },
3759
3760 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3761 {
3762 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
3763 { Bad_Opcode },
3764 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
3765 },
3766
3767 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3768 {
3769 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
3770 { Bad_Opcode },
3771 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
3772 },
3773
3774 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3775 {
3776 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
3777 { Bad_Opcode },
3778 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
3779 },
3780
3781 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3782 {
3783 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
3784 { Bad_Opcode },
3785 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
3786 },
3787
3788 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3789 {
3790 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
3791 },
3792
3793 /* PREFIX_VEX_0F51 */
3794 {
3795 { "vsqrtps", { XM, EXx }, 0 },
3796 { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3797 { "vsqrtpd", { XM, EXx }, 0 },
3798 { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3799 },
3800
3801 /* PREFIX_VEX_0F52 */
3802 {
3803 { "vrsqrtps", { XM, EXx }, 0 },
3804 { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3805 },
3806
3807 /* PREFIX_VEX_0F53 */
3808 {
3809 { "vrcpps", { XM, EXx }, 0 },
3810 { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3811 },
3812
3813 /* PREFIX_VEX_0F58 */
3814 {
3815 { "vaddps", { XM, Vex, EXx }, 0 },
3816 { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3817 { "vaddpd", { XM, Vex, EXx }, 0 },
3818 { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3819 },
3820
3821 /* PREFIX_VEX_0F59 */
3822 {
3823 { "vmulps", { XM, Vex, EXx }, 0 },
3824 { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3825 { "vmulpd", { XM, Vex, EXx }, 0 },
3826 { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3827 },
3828
3829 /* PREFIX_VEX_0F5A */
3830 {
3831 { "vcvtps2pd", { XM, EXxmmq }, 0 },
3832 { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
3833 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3834 { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3835 },
3836
3837 /* PREFIX_VEX_0F5B */
3838 {
3839 { "vcvtdq2ps", { XM, EXx }, 0 },
3840 { "vcvttps2dq", { XM, EXx }, 0 },
3841 { "vcvtps2dq", { XM, EXx }, 0 },
3842 },
3843
3844 /* PREFIX_VEX_0F5C */
3845 {
3846 { "vsubps", { XM, Vex, EXx }, 0 },
3847 { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3848 { "vsubpd", { XM, Vex, EXx }, 0 },
3849 { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3850 },
3851
3852 /* PREFIX_VEX_0F5D */
3853 {
3854 { "vminps", { XM, Vex, EXx }, 0 },
3855 { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3856 { "vminpd", { XM, Vex, EXx }, 0 },
3857 { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3858 },
3859
3860 /* PREFIX_VEX_0F5E */
3861 {
3862 { "vdivps", { XM, Vex, EXx }, 0 },
3863 { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3864 { "vdivpd", { XM, Vex, EXx }, 0 },
3865 { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3866 },
3867
3868 /* PREFIX_VEX_0F5F */
3869 {
3870 { "vmaxps", { XM, Vex, EXx }, 0 },
3871 { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3872 { "vmaxpd", { XM, Vex, EXx }, 0 },
3873 { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3874 },
3875
3876 /* PREFIX_VEX_0F6F */
3877 {
3878 { Bad_Opcode },
3879 { "vmovdqu", { XM, EXx }, 0 },
3880 { "vmovdqa", { XM, EXx }, 0 },
3881 },
3882
3883 /* PREFIX_VEX_0F70 */
3884 {
3885 { Bad_Opcode },
3886 { "vpshufhw", { XM, EXx, Ib }, 0 },
3887 { "vpshufd", { XM, EXx, Ib }, 0 },
3888 { "vpshuflw", { XM, EXx, Ib }, 0 },
3889 },
3890
3891 /* PREFIX_VEX_0F7C */
3892 {
3893 { Bad_Opcode },
3894 { Bad_Opcode },
3895 { "vhaddpd", { XM, Vex, EXx }, 0 },
3896 { "vhaddps", { XM, Vex, EXx }, 0 },
3897 },
3898
3899 /* PREFIX_VEX_0F7D */
3900 {
3901 { Bad_Opcode },
3902 { Bad_Opcode },
3903 { "vhsubpd", { XM, Vex, EXx }, 0 },
3904 { "vhsubps", { XM, Vex, EXx }, 0 },
3905 },
3906
3907 /* PREFIX_VEX_0F7E */
3908 {
3909 { Bad_Opcode },
3910 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3911 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3912 },
3913
3914 /* PREFIX_VEX_0F7F */
3915 {
3916 { Bad_Opcode },
3917 { "vmovdqu", { EXxS, XM }, 0 },
3918 { "vmovdqa", { EXxS, XM }, 0 },
3919 },
3920
3921 /* PREFIX_VEX_0F90_L_0_W_0 */
3922 {
3923 { "kmovw", { MaskG, MaskE }, 0 },
3924 { Bad_Opcode },
3925 { "kmovb", { MaskG, MaskBDE }, 0 },
3926 },
3927
3928 /* PREFIX_VEX_0F90_L_0_W_1 */
3929 {
3930 { "kmovq", { MaskG, MaskE }, 0 },
3931 { Bad_Opcode },
3932 { "kmovd", { MaskG, MaskBDE }, 0 },
3933 },
3934
3935 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3936 {
3937 { "kmovw", { Ew, MaskG }, 0 },
3938 { Bad_Opcode },
3939 { "kmovb", { Eb, MaskG }, 0 },
3940 },
3941
3942 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3943 {
3944 { "kmovq", { Eq, MaskG }, 0 },
3945 { Bad_Opcode },
3946 { "kmovd", { Ed, MaskG }, 0 },
3947 },
3948
3949 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3950 {
3951 { "kmovw", { MaskG, Edq }, 0 },
3952 { Bad_Opcode },
3953 { "kmovb", { MaskG, Edq }, 0 },
3954 { "kmovd", { MaskG, Edq }, 0 },
3955 },
3956
3957 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3958 {
3959 { Bad_Opcode },
3960 { Bad_Opcode },
3961 { Bad_Opcode },
3962 { "kmovK", { MaskG, Edq }, 0 },
3963 },
3964
3965 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3966 {
3967 { "kmovw", { Gdq, MaskE }, 0 },
3968 { Bad_Opcode },
3969 { "kmovb", { Gdq, MaskE }, 0 },
3970 { "kmovd", { Gdq, MaskE }, 0 },
3971 },
3972
3973 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3974 {
3975 { Bad_Opcode },
3976 { Bad_Opcode },
3977 { Bad_Opcode },
3978 { "kmovK", { Gdq, MaskE }, 0 },
3979 },
3980
3981 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3982 {
3983 { "kortestw", { MaskG, MaskE }, 0 },
3984 { Bad_Opcode },
3985 { "kortestb", { MaskG, MaskE }, 0 },
3986 },
3987
3988 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3989 {
3990 { "kortestq", { MaskG, MaskE }, 0 },
3991 { Bad_Opcode },
3992 { "kortestd", { MaskG, MaskE }, 0 },
3993 },
3994
3995 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
3996 {
3997 { "ktestw", { MaskG, MaskE }, 0 },
3998 { Bad_Opcode },
3999 { "ktestb", { MaskG, MaskE }, 0 },
4000 },
4001
4002 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4003 {
4004 { "ktestq", { MaskG, MaskE }, 0 },
4005 { Bad_Opcode },
4006 { "ktestd", { MaskG, MaskE }, 0 },
4007 },
4008
4009 /* PREFIX_VEX_0FC2 */
4010 {
4011 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
4012 { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
4013 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
4014 { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
4015 },
4016
4017 /* PREFIX_VEX_0FD0 */
4018 {
4019 { Bad_Opcode },
4020 { Bad_Opcode },
4021 { "vaddsubpd", { XM, Vex, EXx }, 0 },
4022 { "vaddsubps", { XM, Vex, EXx }, 0 },
4023 },
4024
4025 /* PREFIX_VEX_0FE6 */
4026 {
4027 { Bad_Opcode },
4028 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
4029 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
4030 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
4031 },
4032
4033 /* PREFIX_VEX_0FF0 */
4034 {
4035 { Bad_Opcode },
4036 { Bad_Opcode },
4037 { Bad_Opcode },
4038 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4039 },
4040
4041 /* PREFIX_VEX_0F3849_X86_64 */
4042 {
4043 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4044 { Bad_Opcode },
4045 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4046 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4047 },
4048
4049 /* PREFIX_VEX_0F384B_X86_64 */
4050 {
4051 { Bad_Opcode },
4052 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4053 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4054 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4055 },
4056
4057 /* PREFIX_VEX_0F385C_X86_64 */
4058 {
4059 { Bad_Opcode },
4060 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4061 { Bad_Opcode },
4062 },
4063
4064 /* PREFIX_VEX_0F385E_X86_64 */
4065 {
4066 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4067 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4068 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4069 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4070 },
4071
4072 /* PREFIX_VEX_0F38F5_L_0 */
4073 {
4074 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
4075 { "pextS", { Gdq, VexGdq, Edq }, 0 },
4076 { Bad_Opcode },
4077 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
4078 },
4079
4080 /* PREFIX_VEX_0F38F6_L_0 */
4081 {
4082 { Bad_Opcode },
4083 { Bad_Opcode },
4084 { Bad_Opcode },
4085 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
4086 },
4087
4088 /* PREFIX_VEX_0F38F7_L_0 */
4089 {
4090 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
4091 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
4092 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
4093 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
4094 },
4095
4096 /* PREFIX_VEX_0F3AF0_L_0 */
4097 {
4098 { Bad_Opcode },
4099 { Bad_Opcode },
4100 { Bad_Opcode },
4101 { "rorxS", { Gdq, Edq, Ib }, 0 },
4102 },
4103
4104 #include "i386-dis-evex-prefix.h"
4105 };
4106
4107 static const struct dis386 x86_64_table[][2] = {
4108 /* X86_64_06 */
4109 {
4110 { "pushP", { es }, 0 },
4111 },
4112
4113 /* X86_64_07 */
4114 {
4115 { "popP", { es }, 0 },
4116 },
4117
4118 /* X86_64_0E */
4119 {
4120 { "pushP", { cs }, 0 },
4121 },
4122
4123 /* X86_64_16 */
4124 {
4125 { "pushP", { ss }, 0 },
4126 },
4127
4128 /* X86_64_17 */
4129 {
4130 { "popP", { ss }, 0 },
4131 },
4132
4133 /* X86_64_1E */
4134 {
4135 { "pushP", { ds }, 0 },
4136 },
4137
4138 /* X86_64_1F */
4139 {
4140 { "popP", { ds }, 0 },
4141 },
4142
4143 /* X86_64_27 */
4144 {
4145 { "daa", { XX }, 0 },
4146 },
4147
4148 /* X86_64_2F */
4149 {
4150 { "das", { XX }, 0 },
4151 },
4152
4153 /* X86_64_37 */
4154 {
4155 { "aaa", { XX }, 0 },
4156 },
4157
4158 /* X86_64_3F */
4159 {
4160 { "aas", { XX }, 0 },
4161 },
4162
4163 /* X86_64_60 */
4164 {
4165 { "pushaP", { XX }, 0 },
4166 },
4167
4168 /* X86_64_61 */
4169 {
4170 { "popaP", { XX }, 0 },
4171 },
4172
4173 /* X86_64_62 */
4174 {
4175 { MOD_TABLE (MOD_62_32BIT) },
4176 { EVEX_TABLE (EVEX_0F) },
4177 },
4178
4179 /* X86_64_63 */
4180 {
4181 { "arpl", { Ew, Gw }, 0 },
4182 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4183 },
4184
4185 /* X86_64_6D */
4186 {
4187 { "ins{R|}", { Yzr, indirDX }, 0 },
4188 { "ins{G|}", { Yzr, indirDX }, 0 },
4189 },
4190
4191 /* X86_64_6F */
4192 {
4193 { "outs{R|}", { indirDXr, Xz }, 0 },
4194 { "outs{G|}", { indirDXr, Xz }, 0 },
4195 },
4196
4197 /* X86_64_82 */
4198 {
4199 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4200 { REG_TABLE (REG_80) },
4201 },
4202
4203 /* X86_64_9A */
4204 {
4205 { "{l|}call{P|}", { Ap }, 0 },
4206 },
4207
4208 /* X86_64_C2 */
4209 {
4210 { "retP", { Iw, BND }, 0 },
4211 { "ret@", { Iw, BND }, 0 },
4212 },
4213
4214 /* X86_64_C3 */
4215 {
4216 { "retP", { BND }, 0 },
4217 { "ret@", { BND }, 0 },
4218 },
4219
4220 /* X86_64_C4 */
4221 {
4222 { MOD_TABLE (MOD_C4_32BIT) },
4223 { VEX_C4_TABLE (VEX_0F) },
4224 },
4225
4226 /* X86_64_C5 */
4227 {
4228 { MOD_TABLE (MOD_C5_32BIT) },
4229 { VEX_C5_TABLE (VEX_0F) },
4230 },
4231
4232 /* X86_64_CE */
4233 {
4234 { "into", { XX }, 0 },
4235 },
4236
4237 /* X86_64_D4 */
4238 {
4239 { "aam", { Ib }, 0 },
4240 },
4241
4242 /* X86_64_D5 */
4243 {
4244 { "aad", { Ib }, 0 },
4245 },
4246
4247 /* X86_64_E8 */
4248 {
4249 { "callP", { Jv, BND }, 0 },
4250 { "call@", { Jv, BND }, 0 }
4251 },
4252
4253 /* X86_64_E9 */
4254 {
4255 { "jmpP", { Jv, BND }, 0 },
4256 { "jmp@", { Jv, BND }, 0 }
4257 },
4258
4259 /* X86_64_EA */
4260 {
4261 { "{l|}jmp{P|}", { Ap }, 0 },
4262 },
4263
4264 /* X86_64_0F01_REG_0 */
4265 {
4266 { "sgdt{Q|Q}", { M }, 0 },
4267 { "sgdt", { M }, 0 },
4268 },
4269
4270 /* X86_64_0F01_REG_1 */
4271 {
4272 { "sidt{Q|Q}", { M }, 0 },
4273 { "sidt", { M }, 0 },
4274 },
4275
4276 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4277 {
4278 { Bad_Opcode },
4279 { "seamret", { Skip_MODRM }, 0 },
4280 },
4281
4282 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4283 {
4284 { Bad_Opcode },
4285 { "seamops", { Skip_MODRM }, 0 },
4286 },
4287
4288 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4289 {
4290 { Bad_Opcode },
4291 { "seamcall", { Skip_MODRM }, 0 },
4292 },
4293
4294 /* X86_64_0F01_REG_2 */
4295 {
4296 { "lgdt{Q|Q}", { M }, 0 },
4297 { "lgdt", { M }, 0 },
4298 },
4299
4300 /* X86_64_0F01_REG_3 */
4301 {
4302 { "lidt{Q|Q}", { M }, 0 },
4303 { "lidt", { M }, 0 },
4304 },
4305
4306 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4307 {
4308 { Bad_Opcode },
4309 { "uiret", { Skip_MODRM }, 0 },
4310 },
4311
4312 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4313 {
4314 { Bad_Opcode },
4315 { "testui", { Skip_MODRM }, 0 },
4316 },
4317
4318 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4319 {
4320 { Bad_Opcode },
4321 { "clui", { Skip_MODRM }, 0 },
4322 },
4323
4324 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4325 {
4326 { Bad_Opcode },
4327 { "stui", { Skip_MODRM }, 0 },
4328 },
4329
4330 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4331 {
4332 { Bad_Opcode },
4333 { "rmpadjust", { Skip_MODRM }, 0 },
4334 },
4335
4336 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4337 {
4338 { Bad_Opcode },
4339 { "rmpupdate", { Skip_MODRM }, 0 },
4340 },
4341
4342 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4343 {
4344 { Bad_Opcode },
4345 { "psmash", { Skip_MODRM }, 0 },
4346 },
4347
4348 {
4349 /* X86_64_0F24 */
4350 { "movZ", { Em, Td }, 0 },
4351 },
4352
4353 {
4354 /* X86_64_0F26 */
4355 { "movZ", { Td, Em }, 0 },
4356 },
4357
4358 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4359 {
4360 { Bad_Opcode },
4361 { "senduipi", { Eq }, 0 },
4362 },
4363
4364 /* X86_64_VEX_0F3849 */
4365 {
4366 { Bad_Opcode },
4367 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4368 },
4369
4370 /* X86_64_VEX_0F384B */
4371 {
4372 { Bad_Opcode },
4373 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4374 },
4375
4376 /* X86_64_VEX_0F385C */
4377 {
4378 { Bad_Opcode },
4379 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4380 },
4381
4382 /* X86_64_VEX_0F385E */
4383 {
4384 { Bad_Opcode },
4385 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4386 },
4387 };
4388
4389 static const struct dis386 three_byte_table[][256] = {
4390
4391 /* THREE_BYTE_0F38 */
4392 {
4393 /* 00 */
4394 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4395 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4396 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4397 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4398 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4399 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4400 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4401 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4402 /* 08 */
4403 { "psignb", { MX, EM }, PREFIX_OPCODE },
4404 { "psignw", { MX, EM }, PREFIX_OPCODE },
4405 { "psignd", { MX, EM }, PREFIX_OPCODE },
4406 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4407 { Bad_Opcode },
4408 { Bad_Opcode },
4409 { Bad_Opcode },
4410 { Bad_Opcode },
4411 /* 10 */
4412 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4413 { Bad_Opcode },
4414 { Bad_Opcode },
4415 { Bad_Opcode },
4416 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4417 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4418 { Bad_Opcode },
4419 { "ptest", { XM, EXx }, PREFIX_DATA },
4420 /* 18 */
4421 { Bad_Opcode },
4422 { Bad_Opcode },
4423 { Bad_Opcode },
4424 { Bad_Opcode },
4425 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4426 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4427 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4428 { Bad_Opcode },
4429 /* 20 */
4430 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4431 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4432 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4433 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4434 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4435 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4436 { Bad_Opcode },
4437 { Bad_Opcode },
4438 /* 28 */
4439 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4440 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4441 { MOD_TABLE (MOD_0F382A) },
4442 { "packusdw", { XM, EXx }, PREFIX_DATA },
4443 { Bad_Opcode },
4444 { Bad_Opcode },
4445 { Bad_Opcode },
4446 { Bad_Opcode },
4447 /* 30 */
4448 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4449 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4450 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4451 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4452 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4453 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4454 { Bad_Opcode },
4455 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4456 /* 38 */
4457 { "pminsb", { XM, EXx }, PREFIX_DATA },
4458 { "pminsd", { XM, EXx }, PREFIX_DATA },
4459 { "pminuw", { XM, EXx }, PREFIX_DATA },
4460 { "pminud", { XM, EXx }, PREFIX_DATA },
4461 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4462 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4463 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4464 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4465 /* 40 */
4466 { "pmulld", { XM, EXx }, PREFIX_DATA },
4467 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4468 { Bad_Opcode },
4469 { Bad_Opcode },
4470 { Bad_Opcode },
4471 { Bad_Opcode },
4472 { Bad_Opcode },
4473 { Bad_Opcode },
4474 /* 48 */
4475 { Bad_Opcode },
4476 { Bad_Opcode },
4477 { Bad_Opcode },
4478 { Bad_Opcode },
4479 { Bad_Opcode },
4480 { Bad_Opcode },
4481 { Bad_Opcode },
4482 { Bad_Opcode },
4483 /* 50 */
4484 { Bad_Opcode },
4485 { Bad_Opcode },
4486 { Bad_Opcode },
4487 { Bad_Opcode },
4488 { Bad_Opcode },
4489 { Bad_Opcode },
4490 { Bad_Opcode },
4491 { Bad_Opcode },
4492 /* 58 */
4493 { Bad_Opcode },
4494 { Bad_Opcode },
4495 { Bad_Opcode },
4496 { Bad_Opcode },
4497 { Bad_Opcode },
4498 { Bad_Opcode },
4499 { Bad_Opcode },
4500 { Bad_Opcode },
4501 /* 60 */
4502 { Bad_Opcode },
4503 { Bad_Opcode },
4504 { Bad_Opcode },
4505 { Bad_Opcode },
4506 { Bad_Opcode },
4507 { Bad_Opcode },
4508 { Bad_Opcode },
4509 { Bad_Opcode },
4510 /* 68 */
4511 { Bad_Opcode },
4512 { Bad_Opcode },
4513 { Bad_Opcode },
4514 { Bad_Opcode },
4515 { Bad_Opcode },
4516 { Bad_Opcode },
4517 { Bad_Opcode },
4518 { Bad_Opcode },
4519 /* 70 */
4520 { Bad_Opcode },
4521 { Bad_Opcode },
4522 { Bad_Opcode },
4523 { Bad_Opcode },
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 { Bad_Opcode },
4527 { Bad_Opcode },
4528 /* 78 */
4529 { Bad_Opcode },
4530 { Bad_Opcode },
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 { Bad_Opcode },
4534 { Bad_Opcode },
4535 { Bad_Opcode },
4536 { Bad_Opcode },
4537 /* 80 */
4538 { "invept", { Gm, Mo }, PREFIX_DATA },
4539 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4540 { "invpcid", { Gm, M }, PREFIX_DATA },
4541 { Bad_Opcode },
4542 { Bad_Opcode },
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 { Bad_Opcode },
4546 /* 88 */
4547 { Bad_Opcode },
4548 { Bad_Opcode },
4549 { Bad_Opcode },
4550 { Bad_Opcode },
4551 { Bad_Opcode },
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 { Bad_Opcode },
4555 /* 90 */
4556 { Bad_Opcode },
4557 { Bad_Opcode },
4558 { Bad_Opcode },
4559 { Bad_Opcode },
4560 { Bad_Opcode },
4561 { Bad_Opcode },
4562 { Bad_Opcode },
4563 { Bad_Opcode },
4564 /* 98 */
4565 { Bad_Opcode },
4566 { Bad_Opcode },
4567 { Bad_Opcode },
4568 { Bad_Opcode },
4569 { Bad_Opcode },
4570 { Bad_Opcode },
4571 { Bad_Opcode },
4572 { Bad_Opcode },
4573 /* a0 */
4574 { Bad_Opcode },
4575 { Bad_Opcode },
4576 { Bad_Opcode },
4577 { Bad_Opcode },
4578 { Bad_Opcode },
4579 { Bad_Opcode },
4580 { Bad_Opcode },
4581 { Bad_Opcode },
4582 /* a8 */
4583 { Bad_Opcode },
4584 { Bad_Opcode },
4585 { Bad_Opcode },
4586 { Bad_Opcode },
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 { Bad_Opcode },
4590 { Bad_Opcode },
4591 /* b0 */
4592 { Bad_Opcode },
4593 { Bad_Opcode },
4594 { Bad_Opcode },
4595 { Bad_Opcode },
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 { Bad_Opcode },
4600 /* b8 */
4601 { Bad_Opcode },
4602 { Bad_Opcode },
4603 { Bad_Opcode },
4604 { Bad_Opcode },
4605 { Bad_Opcode },
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 { Bad_Opcode },
4609 /* c0 */
4610 { Bad_Opcode },
4611 { Bad_Opcode },
4612 { Bad_Opcode },
4613 { Bad_Opcode },
4614 { Bad_Opcode },
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 { Bad_Opcode },
4618 /* c8 */
4619 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4620 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4621 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4622 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4623 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4624 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4625 { Bad_Opcode },
4626 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4627 /* d0 */
4628 { Bad_Opcode },
4629 { Bad_Opcode },
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 /* d8 */
4637 { PREFIX_TABLE (PREFIX_0F38D8) },
4638 { Bad_Opcode },
4639 { Bad_Opcode },
4640 { "aesimc", { XM, EXx }, PREFIX_DATA },
4641 { PREFIX_TABLE (PREFIX_0F38DC) },
4642 { PREFIX_TABLE (PREFIX_0F38DD) },
4643 { PREFIX_TABLE (PREFIX_0F38DE) },
4644 { PREFIX_TABLE (PREFIX_0F38DF) },
4645 /* e0 */
4646 { Bad_Opcode },
4647 { Bad_Opcode },
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 { Bad_Opcode },
4654 /* e8 */
4655 { Bad_Opcode },
4656 { Bad_Opcode },
4657 { Bad_Opcode },
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 /* f0 */
4664 { PREFIX_TABLE (PREFIX_0F38F0) },
4665 { PREFIX_TABLE (PREFIX_0F38F1) },
4666 { Bad_Opcode },
4667 { Bad_Opcode },
4668 { Bad_Opcode },
4669 { MOD_TABLE (MOD_0F38F5) },
4670 { PREFIX_TABLE (PREFIX_0F38F6) },
4671 { Bad_Opcode },
4672 /* f8 */
4673 { PREFIX_TABLE (PREFIX_0F38F8) },
4674 { MOD_TABLE (MOD_0F38F9) },
4675 { PREFIX_TABLE (PREFIX_0F38FA) },
4676 { PREFIX_TABLE (PREFIX_0F38FB) },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 },
4682 /* THREE_BYTE_0F3A */
4683 {
4684 /* 00 */
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 { Bad_Opcode },
4693 /* 08 */
4694 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4695 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4696 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4697 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4698 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4699 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4700 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4701 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4702 /* 10 */
4703 { Bad_Opcode },
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 { Bad_Opcode },
4707 { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4708 { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4709 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4710 { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4711 /* 18 */
4712 { Bad_Opcode },
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 { Bad_Opcode },
4720 /* 20 */
4721 { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4722 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4723 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { Bad_Opcode },
4728 { Bad_Opcode },
4729 /* 28 */
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 { Bad_Opcode },
4738 /* 30 */
4739 { Bad_Opcode },
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 { Bad_Opcode },
4747 /* 38 */
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 { Bad_Opcode },
4756 /* 40 */
4757 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4758 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4759 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4760 { Bad_Opcode },
4761 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 { Bad_Opcode },
4765 /* 48 */
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 { Bad_Opcode },
4774 /* 50 */
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 { Bad_Opcode },
4783 /* 58 */
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 { Bad_Opcode },
4792 /* 60 */
4793 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4794 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4795 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4796 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 { Bad_Opcode },
4801 /* 68 */
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 /* 70 */
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 { Bad_Opcode },
4819 /* 78 */
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 { Bad_Opcode },
4828 /* 80 */
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 { Bad_Opcode },
4837 /* 88 */
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 { Bad_Opcode },
4846 /* 90 */
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { Bad_Opcode },
4855 /* 98 */
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 /* a0 */
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 { Bad_Opcode },
4873 /* a8 */
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 { Bad_Opcode },
4882 /* b0 */
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 /* b8 */
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 { Bad_Opcode },
4900 /* c0 */
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 /* c8 */
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 { Bad_Opcode },
4914 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4915 { Bad_Opcode },
4916 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4917 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4918 /* d0 */
4919 { Bad_Opcode },
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 /* d8 */
4928 { Bad_Opcode },
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 { Bad_Opcode },
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4936 /* e0 */
4937 { Bad_Opcode },
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 { Bad_Opcode },
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 /* e8 */
4946 { Bad_Opcode },
4947 { Bad_Opcode },
4948 { Bad_Opcode },
4949 { Bad_Opcode },
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 /* f0 */
4955 { PREFIX_TABLE (PREFIX_0F3A0F) },
4956 { Bad_Opcode },
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 /* f8 */
4964 { Bad_Opcode },
4965 { Bad_Opcode },
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 },
4973 };
4974
4975 static const struct dis386 xop_table[][256] = {
4976 /* XOP_08 */
4977 {
4978 /* 00 */
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { Bad_Opcode },
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 /* 08 */
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 /* 10 */
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 { Bad_Opcode },
5002 { Bad_Opcode },
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 /* 18 */
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 { Bad_Opcode },
5013 { Bad_Opcode },
5014 /* 20 */
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 /* 28 */
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 /* 30 */
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 { Bad_Opcode },
5041 /* 38 */
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 /* 40 */
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 /* 48 */
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 /* 50 */
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 { Bad_Opcode },
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 /* 58 */
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 { Bad_Opcode },
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 /* 60 */
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 { Bad_Opcode },
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 /* 68 */
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 /* 70 */
5105 { Bad_Opcode },
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 /* 78 */
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 /* 80 */
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5129 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5130 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5131 /* 88 */
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5139 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5140 /* 90 */
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5147 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5148 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5149 /* 98 */
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5157 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5158 /* a0 */
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5162 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5166 { Bad_Opcode },
5167 /* a8 */
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 /* b0 */
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5184 { Bad_Opcode },
5185 /* b8 */
5186 { Bad_Opcode },
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { Bad_Opcode },
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { Bad_Opcode },
5194 /* c0 */
5195 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5196 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5197 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5198 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 /* c8 */
5204 { Bad_Opcode },
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5209 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5210 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5211 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5212 /* d0 */
5213 { Bad_Opcode },
5214 { Bad_Opcode },
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 /* d8 */
5222 { Bad_Opcode },
5223 { Bad_Opcode },
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 /* e0 */
5231 { Bad_Opcode },
5232 { Bad_Opcode },
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 /* e8 */
5240 { Bad_Opcode },
5241 { Bad_Opcode },
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5245 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5246 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5247 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5248 /* f0 */
5249 { Bad_Opcode },
5250 { Bad_Opcode },
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 /* f8 */
5258 { Bad_Opcode },
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 },
5267 /* XOP_09 */
5268 {
5269 /* 00 */
5270 { Bad_Opcode },
5271 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5272 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 { Bad_Opcode },
5278 /* 08 */
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 { Bad_Opcode },
5287 /* 10 */
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { MOD_TABLE (MOD_XOP_09_12) },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 { Bad_Opcode },
5296 /* 18 */
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 { Bad_Opcode },
5305 /* 20 */
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { Bad_Opcode },
5313 { Bad_Opcode },
5314 /* 28 */
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 { Bad_Opcode },
5323 /* 30 */
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { Bad_Opcode },
5331 { Bad_Opcode },
5332 /* 38 */
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 { Bad_Opcode },
5341 /* 40 */
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 { Bad_Opcode },
5350 /* 48 */
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 { Bad_Opcode },
5359 /* 50 */
5360 { Bad_Opcode },
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { Bad_Opcode },
5368 /* 58 */
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 { Bad_Opcode },
5377 /* 60 */
5378 { Bad_Opcode },
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 { Bad_Opcode },
5385 { Bad_Opcode },
5386 /* 68 */
5387 { Bad_Opcode },
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { Bad_Opcode },
5395 /* 70 */
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 /* 78 */
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { Bad_Opcode },
5413 /* 80 */
5414 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5415 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5416 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5417 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { Bad_Opcode },
5422 /* 88 */
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 /* 90 */
5432 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5433 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5434 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5435 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5436 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5437 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5438 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5439 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5440 /* 98 */
5441 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5442 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5443 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5444 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 /* a0 */
5450 { Bad_Opcode },
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 { Bad_Opcode },
5458 /* a8 */
5459 { Bad_Opcode },
5460 { Bad_Opcode },
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 { Bad_Opcode },
5467 /* b0 */
5468 { Bad_Opcode },
5469 { Bad_Opcode },
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 { Bad_Opcode },
5476 /* b8 */
5477 { Bad_Opcode },
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 /* c0 */
5486 { Bad_Opcode },
5487 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5488 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5489 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5493 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5494 /* c8 */
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 { Bad_Opcode },
5503 /* d0 */
5504 { Bad_Opcode },
5505 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5506 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5507 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5511 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5512 /* d8 */
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 /* e0 */
5522 { Bad_Opcode },
5523 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5524 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5525 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 /* e8 */
5531 { Bad_Opcode },
5532 { Bad_Opcode },
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 /* f0 */
5540 { Bad_Opcode },
5541 { Bad_Opcode },
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 /* f8 */
5549 { Bad_Opcode },
5550 { Bad_Opcode },
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 },
5558 /* XOP_0A */
5559 {
5560 /* 00 */
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 { Bad_Opcode },
5569 /* 08 */
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 { Bad_Opcode },
5578 /* 10 */
5579 { "bextrS", { Gdq, Edq, Id }, 0 },
5580 { Bad_Opcode },
5581 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 { Bad_Opcode },
5587 /* 18 */
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 { Bad_Opcode },
5596 /* 20 */
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 { Bad_Opcode },
5605 /* 28 */
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 { Bad_Opcode },
5614 /* 30 */
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 { Bad_Opcode },
5623 /* 38 */
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 { Bad_Opcode },
5632 /* 40 */
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { Bad_Opcode },
5641 /* 48 */
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 /* 50 */
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 /* 58 */
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 { Bad_Opcode },
5668 /* 60 */
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 { Bad_Opcode },
5677 /* 68 */
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 /* 70 */
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 /* 78 */
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 /* 80 */
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 /* 88 */
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { Bad_Opcode },
5722 /* 90 */
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 /* 98 */
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 { Bad_Opcode },
5740 /* a0 */
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 { Bad_Opcode },
5749 /* a8 */
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 { Bad_Opcode },
5758 /* b0 */
5759 { Bad_Opcode },
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 { Bad_Opcode },
5767 /* b8 */
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 { Bad_Opcode },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 { Bad_Opcode },
5776 /* c0 */
5777 { Bad_Opcode },
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 /* c8 */
5786 { Bad_Opcode },
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 /* d0 */
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 { Bad_Opcode },
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 /* d8 */
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 /* e0 */
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 /* e8 */
5822 { Bad_Opcode },
5823 { Bad_Opcode },
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 /* f0 */
5831 { Bad_Opcode },
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 /* f8 */
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 },
5849 };
5850
5851 static const struct dis386 vex_table[][256] = {
5852 /* VEX_0F */
5853 {
5854 /* 00 */
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 /* 08 */
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 /* 10 */
5873 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5874 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5875 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5876 { MOD_TABLE (MOD_VEX_0F13) },
5877 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5878 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5879 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5880 { MOD_TABLE (MOD_VEX_0F17) },
5881 /* 18 */
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 /* 20 */
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 { Bad_Opcode },
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 /* 28 */
5900 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5901 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5902 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5903 { MOD_TABLE (MOD_VEX_0F2B) },
5904 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5905 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5906 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5907 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5908 /* 30 */
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 { Bad_Opcode },
5914 { Bad_Opcode },
5915 { Bad_Opcode },
5916 { Bad_Opcode },
5917 /* 38 */
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 { Bad_Opcode },
5923 { Bad_Opcode },
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 /* 40 */
5927 { Bad_Opcode },
5928 { VEX_LEN_TABLE (VEX_LEN_0F41) },
5929 { VEX_LEN_TABLE (VEX_LEN_0F42) },
5930 { Bad_Opcode },
5931 { VEX_LEN_TABLE (VEX_LEN_0F44) },
5932 { VEX_LEN_TABLE (VEX_LEN_0F45) },
5933 { VEX_LEN_TABLE (VEX_LEN_0F46) },
5934 { VEX_LEN_TABLE (VEX_LEN_0F47) },
5935 /* 48 */
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5939 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5940 { Bad_Opcode },
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 { Bad_Opcode },
5944 /* 50 */
5945 { MOD_TABLE (MOD_VEX_0F50) },
5946 { PREFIX_TABLE (PREFIX_VEX_0F51) },
5947 { PREFIX_TABLE (PREFIX_VEX_0F52) },
5948 { PREFIX_TABLE (PREFIX_VEX_0F53) },
5949 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5950 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5951 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5952 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5953 /* 58 */
5954 { PREFIX_TABLE (PREFIX_VEX_0F58) },
5955 { PREFIX_TABLE (PREFIX_VEX_0F59) },
5956 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5957 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5958 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5959 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5960 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5961 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5962 /* 60 */
5963 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
5964 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
5965 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
5966 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
5967 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
5968 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
5969 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
5970 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
5971 /* 68 */
5972 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
5973 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
5974 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
5975 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
5976 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
5977 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
5978 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5979 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5980 /* 70 */
5981 { PREFIX_TABLE (PREFIX_VEX_0F70) },
5982 { MOD_TABLE (MOD_VEX_0F71) },
5983 { MOD_TABLE (MOD_VEX_0F72) },
5984 { MOD_TABLE (MOD_VEX_0F73) },
5985 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
5986 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
5987 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
5988 { VEX_LEN_TABLE (VEX_LEN_0F77) },
5989 /* 78 */
5990 { Bad_Opcode },
5991 { Bad_Opcode },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5995 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5996 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5997 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5998 /* 80 */
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 { Bad_Opcode },
6004 { Bad_Opcode },
6005 { Bad_Opcode },
6006 { Bad_Opcode },
6007 /* 88 */
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 { Bad_Opcode },
6013 { Bad_Opcode },
6014 { Bad_Opcode },
6015 { Bad_Opcode },
6016 /* 90 */
6017 { VEX_LEN_TABLE (VEX_LEN_0F90) },
6018 { VEX_LEN_TABLE (VEX_LEN_0F91) },
6019 { VEX_LEN_TABLE (VEX_LEN_0F92) },
6020 { VEX_LEN_TABLE (VEX_LEN_0F93) },
6021 { Bad_Opcode },
6022 { Bad_Opcode },
6023 { Bad_Opcode },
6024 { Bad_Opcode },
6025 /* 98 */
6026 { VEX_LEN_TABLE (VEX_LEN_0F98) },
6027 { VEX_LEN_TABLE (VEX_LEN_0F99) },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 /* a0 */
6035 { Bad_Opcode },
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 { Bad_Opcode },
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 /* a8 */
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 { Bad_Opcode },
6047 { Bad_Opcode },
6048 { Bad_Opcode },
6049 { Bad_Opcode },
6050 { REG_TABLE (REG_VEX_0FAE) },
6051 { Bad_Opcode },
6052 /* b0 */
6053 { Bad_Opcode },
6054 { Bad_Opcode },
6055 { Bad_Opcode },
6056 { Bad_Opcode },
6057 { Bad_Opcode },
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 /* b8 */
6062 { Bad_Opcode },
6063 { Bad_Opcode },
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 { Bad_Opcode },
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 /* c0 */
6071 { Bad_Opcode },
6072 { Bad_Opcode },
6073 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6074 { Bad_Opcode },
6075 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6076 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6077 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6078 { Bad_Opcode },
6079 /* c8 */
6080 { Bad_Opcode },
6081 { Bad_Opcode },
6082 { Bad_Opcode },
6083 { Bad_Opcode },
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 /* d0 */
6089 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6090 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6091 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6092 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6093 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6094 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6095 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6096 { MOD_TABLE (MOD_VEX_0FD7) },
6097 /* d8 */
6098 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6099 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6100 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6101 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6102 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6103 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6104 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6105 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6106 /* e0 */
6107 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6108 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6109 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6110 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6111 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6112 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6113 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6114 { MOD_TABLE (MOD_VEX_0FE7) },
6115 /* e8 */
6116 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6117 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6118 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6119 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6120 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6121 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6122 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6123 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6124 /* f0 */
6125 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6126 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6127 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6128 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6129 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6130 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6131 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6132 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6133 /* f8 */
6134 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6135 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6136 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6137 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6138 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6139 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6140 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6141 { Bad_Opcode },
6142 },
6143 /* VEX_0F38 */
6144 {
6145 /* 00 */
6146 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6147 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6148 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6149 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6150 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6151 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6152 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6153 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6154 /* 08 */
6155 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6156 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6157 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6158 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6159 { VEX_W_TABLE (VEX_W_0F380C) },
6160 { VEX_W_TABLE (VEX_W_0F380D) },
6161 { VEX_W_TABLE (VEX_W_0F380E) },
6162 { VEX_W_TABLE (VEX_W_0F380F) },
6163 /* 10 */
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { VEX_W_TABLE (VEX_W_0F3813) },
6168 { Bad_Opcode },
6169 { Bad_Opcode },
6170 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6171 { "vptest", { XM, EXx }, PREFIX_DATA },
6172 /* 18 */
6173 { VEX_W_TABLE (VEX_W_0F3818) },
6174 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6175 { MOD_TABLE (MOD_VEX_0F381A) },
6176 { Bad_Opcode },
6177 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6178 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6179 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6180 { Bad_Opcode },
6181 /* 20 */
6182 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6183 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6184 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6185 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6186 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6187 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6188 { Bad_Opcode },
6189 { Bad_Opcode },
6190 /* 28 */
6191 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6192 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6193 { MOD_TABLE (MOD_VEX_0F382A) },
6194 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6195 { MOD_TABLE (MOD_VEX_0F382C) },
6196 { MOD_TABLE (MOD_VEX_0F382D) },
6197 { MOD_TABLE (MOD_VEX_0F382E) },
6198 { MOD_TABLE (MOD_VEX_0F382F) },
6199 /* 30 */
6200 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6201 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6202 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6203 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6204 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6205 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6206 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6207 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6208 /* 38 */
6209 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6210 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6211 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6212 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6213 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6214 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6215 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6216 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6217 /* 40 */
6218 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6219 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6220 { Bad_Opcode },
6221 { Bad_Opcode },
6222 { Bad_Opcode },
6223 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6224 { VEX_W_TABLE (VEX_W_0F3846) },
6225 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6226 /* 48 */
6227 { Bad_Opcode },
6228 { X86_64_TABLE (X86_64_VEX_0F3849) },
6229 { Bad_Opcode },
6230 { X86_64_TABLE (X86_64_VEX_0F384B) },
6231 { Bad_Opcode },
6232 { Bad_Opcode },
6233 { Bad_Opcode },
6234 { Bad_Opcode },
6235 /* 50 */
6236 { VEX_W_TABLE (VEX_W_0F3850) },
6237 { VEX_W_TABLE (VEX_W_0F3851) },
6238 { VEX_W_TABLE (VEX_W_0F3852) },
6239 { VEX_W_TABLE (VEX_W_0F3853) },
6240 { Bad_Opcode },
6241 { Bad_Opcode },
6242 { Bad_Opcode },
6243 { Bad_Opcode },
6244 /* 58 */
6245 { VEX_W_TABLE (VEX_W_0F3858) },
6246 { VEX_W_TABLE (VEX_W_0F3859) },
6247 { MOD_TABLE (MOD_VEX_0F385A) },
6248 { Bad_Opcode },
6249 { X86_64_TABLE (X86_64_VEX_0F385C) },
6250 { Bad_Opcode },
6251 { X86_64_TABLE (X86_64_VEX_0F385E) },
6252 { Bad_Opcode },
6253 /* 60 */
6254 { Bad_Opcode },
6255 { Bad_Opcode },
6256 { Bad_Opcode },
6257 { Bad_Opcode },
6258 { Bad_Opcode },
6259 { Bad_Opcode },
6260 { Bad_Opcode },
6261 { Bad_Opcode },
6262 /* 68 */
6263 { Bad_Opcode },
6264 { Bad_Opcode },
6265 { Bad_Opcode },
6266 { Bad_Opcode },
6267 { Bad_Opcode },
6268 { Bad_Opcode },
6269 { Bad_Opcode },
6270 { Bad_Opcode },
6271 /* 70 */
6272 { Bad_Opcode },
6273 { Bad_Opcode },
6274 { Bad_Opcode },
6275 { Bad_Opcode },
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { Bad_Opcode },
6279 { Bad_Opcode },
6280 /* 78 */
6281 { VEX_W_TABLE (VEX_W_0F3878) },
6282 { VEX_W_TABLE (VEX_W_0F3879) },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 { Bad_Opcode },
6289 /* 80 */
6290 { Bad_Opcode },
6291 { Bad_Opcode },
6292 { Bad_Opcode },
6293 { Bad_Opcode },
6294 { Bad_Opcode },
6295 { Bad_Opcode },
6296 { Bad_Opcode },
6297 { Bad_Opcode },
6298 /* 88 */
6299 { Bad_Opcode },
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 { Bad_Opcode },
6303 { MOD_TABLE (MOD_VEX_0F388C) },
6304 { Bad_Opcode },
6305 { MOD_TABLE (MOD_VEX_0F388E) },
6306 { Bad_Opcode },
6307 /* 90 */
6308 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6309 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6310 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6311 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6315 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6316 /* 98 */
6317 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6318 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6319 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6320 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6321 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6322 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6323 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6324 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6325 /* a0 */
6326 { Bad_Opcode },
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 { Bad_Opcode },
6332 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6333 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6334 /* a8 */
6335 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6336 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6337 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6338 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6339 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6340 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6341 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6342 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6343 /* b0 */
6344 { Bad_Opcode },
6345 { Bad_Opcode },
6346 { Bad_Opcode },
6347 { Bad_Opcode },
6348 { Bad_Opcode },
6349 { Bad_Opcode },
6350 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6351 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6352 /* b8 */
6353 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6354 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6355 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6356 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6357 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6358 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6359 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6360 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6361 /* c0 */
6362 { Bad_Opcode },
6363 { Bad_Opcode },
6364 { Bad_Opcode },
6365 { Bad_Opcode },
6366 { Bad_Opcode },
6367 { Bad_Opcode },
6368 { Bad_Opcode },
6369 { Bad_Opcode },
6370 /* c8 */
6371 { Bad_Opcode },
6372 { Bad_Opcode },
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 { Bad_Opcode },
6377 { Bad_Opcode },
6378 { VEX_W_TABLE (VEX_W_0F38CF) },
6379 /* d0 */
6380 { Bad_Opcode },
6381 { Bad_Opcode },
6382 { Bad_Opcode },
6383 { Bad_Opcode },
6384 { Bad_Opcode },
6385 { Bad_Opcode },
6386 { Bad_Opcode },
6387 { Bad_Opcode },
6388 /* d8 */
6389 { Bad_Opcode },
6390 { Bad_Opcode },
6391 { Bad_Opcode },
6392 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6393 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6394 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6395 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6396 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6397 /* e0 */
6398 { Bad_Opcode },
6399 { Bad_Opcode },
6400 { Bad_Opcode },
6401 { Bad_Opcode },
6402 { Bad_Opcode },
6403 { Bad_Opcode },
6404 { Bad_Opcode },
6405 { Bad_Opcode },
6406 /* e8 */
6407 { Bad_Opcode },
6408 { Bad_Opcode },
6409 { Bad_Opcode },
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 /* f0 */
6416 { Bad_Opcode },
6417 { Bad_Opcode },
6418 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6419 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6420 { Bad_Opcode },
6421 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6422 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6423 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6424 /* f8 */
6425 { Bad_Opcode },
6426 { Bad_Opcode },
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 },
6434 /* VEX_0F3A */
6435 {
6436 /* 00 */
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6439 { VEX_W_TABLE (VEX_W_0F3A02) },
6440 { Bad_Opcode },
6441 { VEX_W_TABLE (VEX_W_0F3A04) },
6442 { VEX_W_TABLE (VEX_W_0F3A05) },
6443 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6444 { Bad_Opcode },
6445 /* 08 */
6446 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6447 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6448 { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6449 { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6450 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6451 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6452 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6453 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6454 /* 10 */
6455 { Bad_Opcode },
6456 { Bad_Opcode },
6457 { Bad_Opcode },
6458 { Bad_Opcode },
6459 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6460 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6461 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6462 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6463 /* 18 */
6464 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6466 { Bad_Opcode },
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { VEX_W_TABLE (VEX_W_0F3A1D) },
6470 { Bad_Opcode },
6471 { Bad_Opcode },
6472 /* 20 */
6473 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6474 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6475 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6476 { Bad_Opcode },
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 { Bad_Opcode },
6480 { Bad_Opcode },
6481 /* 28 */
6482 { Bad_Opcode },
6483 { Bad_Opcode },
6484 { Bad_Opcode },
6485 { Bad_Opcode },
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 { Bad_Opcode },
6489 { Bad_Opcode },
6490 /* 30 */
6491 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6492 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6493 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6494 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 { Bad_Opcode },
6499 /* 38 */
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6502 { Bad_Opcode },
6503 { Bad_Opcode },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { Bad_Opcode },
6507 { Bad_Opcode },
6508 /* 40 */
6509 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6511 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6512 { Bad_Opcode },
6513 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6514 { Bad_Opcode },
6515 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6516 { Bad_Opcode },
6517 /* 48 */
6518 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6519 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6520 { VEX_W_TABLE (VEX_W_0F3A4A) },
6521 { VEX_W_TABLE (VEX_W_0F3A4B) },
6522 { VEX_W_TABLE (VEX_W_0F3A4C) },
6523 { Bad_Opcode },
6524 { Bad_Opcode },
6525 { Bad_Opcode },
6526 /* 50 */
6527 { Bad_Opcode },
6528 { Bad_Opcode },
6529 { Bad_Opcode },
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 { Bad_Opcode },
6534 { Bad_Opcode },
6535 /* 58 */
6536 { Bad_Opcode },
6537 { Bad_Opcode },
6538 { Bad_Opcode },
6539 { Bad_Opcode },
6540 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6541 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6542 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6543 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6544 /* 60 */
6545 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6546 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6547 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6548 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 { Bad_Opcode },
6552 { Bad_Opcode },
6553 /* 68 */
6554 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6555 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6556 { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6557 { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6558 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6559 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6560 { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6561 { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6562 /* 70 */
6563 { Bad_Opcode },
6564 { Bad_Opcode },
6565 { Bad_Opcode },
6566 { Bad_Opcode },
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 { Bad_Opcode },
6570 { Bad_Opcode },
6571 /* 78 */
6572 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6573 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6574 { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6575 { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6576 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6577 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6578 { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6579 { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6580 /* 80 */
6581 { Bad_Opcode },
6582 { Bad_Opcode },
6583 { Bad_Opcode },
6584 { Bad_Opcode },
6585 { Bad_Opcode },
6586 { Bad_Opcode },
6587 { Bad_Opcode },
6588 { Bad_Opcode },
6589 /* 88 */
6590 { Bad_Opcode },
6591 { Bad_Opcode },
6592 { Bad_Opcode },
6593 { Bad_Opcode },
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 { Bad_Opcode },
6597 { Bad_Opcode },
6598 /* 90 */
6599 { Bad_Opcode },
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 { Bad_Opcode },
6603 { Bad_Opcode },
6604 { Bad_Opcode },
6605 { Bad_Opcode },
6606 { Bad_Opcode },
6607 /* 98 */
6608 { Bad_Opcode },
6609 { Bad_Opcode },
6610 { Bad_Opcode },
6611 { Bad_Opcode },
6612 { Bad_Opcode },
6613 { Bad_Opcode },
6614 { Bad_Opcode },
6615 { Bad_Opcode },
6616 /* a0 */
6617 { Bad_Opcode },
6618 { Bad_Opcode },
6619 { Bad_Opcode },
6620 { Bad_Opcode },
6621 { Bad_Opcode },
6622 { Bad_Opcode },
6623 { Bad_Opcode },
6624 { Bad_Opcode },
6625 /* a8 */
6626 { Bad_Opcode },
6627 { Bad_Opcode },
6628 { Bad_Opcode },
6629 { Bad_Opcode },
6630 { Bad_Opcode },
6631 { Bad_Opcode },
6632 { Bad_Opcode },
6633 { Bad_Opcode },
6634 /* b0 */
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 { Bad_Opcode },
6638 { Bad_Opcode },
6639 { Bad_Opcode },
6640 { Bad_Opcode },
6641 { Bad_Opcode },
6642 { Bad_Opcode },
6643 /* b8 */
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 { Bad_Opcode },
6652 /* c0 */
6653 { Bad_Opcode },
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { Bad_Opcode },
6659 { Bad_Opcode },
6660 { Bad_Opcode },
6661 /* c8 */
6662 { Bad_Opcode },
6663 { Bad_Opcode },
6664 { Bad_Opcode },
6665 { Bad_Opcode },
6666 { Bad_Opcode },
6667 { Bad_Opcode },
6668 { VEX_W_TABLE (VEX_W_0F3ACE) },
6669 { VEX_W_TABLE (VEX_W_0F3ACF) },
6670 /* d0 */
6671 { Bad_Opcode },
6672 { Bad_Opcode },
6673 { Bad_Opcode },
6674 { Bad_Opcode },
6675 { Bad_Opcode },
6676 { Bad_Opcode },
6677 { Bad_Opcode },
6678 { Bad_Opcode },
6679 /* d8 */
6680 { Bad_Opcode },
6681 { Bad_Opcode },
6682 { Bad_Opcode },
6683 { Bad_Opcode },
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6688 /* e0 */
6689 { Bad_Opcode },
6690 { Bad_Opcode },
6691 { Bad_Opcode },
6692 { Bad_Opcode },
6693 { Bad_Opcode },
6694 { Bad_Opcode },
6695 { Bad_Opcode },
6696 { Bad_Opcode },
6697 /* e8 */
6698 { Bad_Opcode },
6699 { Bad_Opcode },
6700 { Bad_Opcode },
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 { Bad_Opcode },
6704 { Bad_Opcode },
6705 { Bad_Opcode },
6706 /* f0 */
6707 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6708 { Bad_Opcode },
6709 { Bad_Opcode },
6710 { Bad_Opcode },
6711 { Bad_Opcode },
6712 { Bad_Opcode },
6713 { Bad_Opcode },
6714 { Bad_Opcode },
6715 /* f8 */
6716 { Bad_Opcode },
6717 { Bad_Opcode },
6718 { Bad_Opcode },
6719 { Bad_Opcode },
6720 { Bad_Opcode },
6721 { Bad_Opcode },
6722 { Bad_Opcode },
6723 { Bad_Opcode },
6724 },
6725 };
6726
6727 #include "i386-dis-evex.h"
6728
6729 static const struct dis386 vex_len_table[][2] = {
6730 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6731 {
6732 { "vmovlpX", { XM, Vex, EXq }, 0 },
6733 },
6734
6735 /* VEX_LEN_0F12_P_0_M_1 */
6736 {
6737 { "vmovhlps", { XM, Vex, EXq }, 0 },
6738 },
6739
6740 /* VEX_LEN_0F13_M_0 */
6741 {
6742 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6743 },
6744
6745 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6746 {
6747 { "vmovhpX", { XM, Vex, EXq }, 0 },
6748 },
6749
6750 /* VEX_LEN_0F16_P_0_M_1 */
6751 {
6752 { "vmovlhps", { XM, Vex, EXq }, 0 },
6753 },
6754
6755 /* VEX_LEN_0F17_M_0 */
6756 {
6757 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6758 },
6759
6760 /* VEX_LEN_0F41 */
6761 {
6762 { Bad_Opcode },
6763 { MOD_TABLE (MOD_VEX_0F41_L_1) },
6764 },
6765
6766 /* VEX_LEN_0F42 */
6767 {
6768 { Bad_Opcode },
6769 { MOD_TABLE (MOD_VEX_0F42_L_1) },
6770 },
6771
6772 /* VEX_LEN_0F44 */
6773 {
6774 { MOD_TABLE (MOD_VEX_0F44_L_0) },
6775 },
6776
6777 /* VEX_LEN_0F45 */
6778 {
6779 { Bad_Opcode },
6780 { MOD_TABLE (MOD_VEX_0F45_L_1) },
6781 },
6782
6783 /* VEX_LEN_0F46 */
6784 {
6785 { Bad_Opcode },
6786 { MOD_TABLE (MOD_VEX_0F46_L_1) },
6787 },
6788
6789 /* VEX_LEN_0F47 */
6790 {
6791 { Bad_Opcode },
6792 { MOD_TABLE (MOD_VEX_0F47_L_1) },
6793 },
6794
6795 /* VEX_LEN_0F4A */
6796 {
6797 { Bad_Opcode },
6798 { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6799 },
6800
6801 /* VEX_LEN_0F4B */
6802 {
6803 { Bad_Opcode },
6804 { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6805 },
6806
6807 /* VEX_LEN_0F6E */
6808 {
6809 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6810 },
6811
6812 /* VEX_LEN_0F77 */
6813 {
6814 { "vzeroupper", { XX }, 0 },
6815 { "vzeroall", { XX }, 0 },
6816 },
6817
6818 /* VEX_LEN_0F7E_P_1 */
6819 {
6820 { "vmovq", { XMScalar, EXxmm_mq }, 0 },
6821 },
6822
6823 /* VEX_LEN_0F7E_P_2 */
6824 {
6825 { "vmovK", { Edq, XMScalar }, 0 },
6826 },
6827
6828 /* VEX_LEN_0F90 */
6829 {
6830 { VEX_W_TABLE (VEX_W_0F90_L_0) },
6831 },
6832
6833 /* VEX_LEN_0F91 */
6834 {
6835 { MOD_TABLE (MOD_VEX_0F91_L_0) },
6836 },
6837
6838 /* VEX_LEN_0F92 */
6839 {
6840 { MOD_TABLE (MOD_VEX_0F92_L_0) },
6841 },
6842
6843 /* VEX_LEN_0F93 */
6844 {
6845 { MOD_TABLE (MOD_VEX_0F93_L_0) },
6846 },
6847
6848 /* VEX_LEN_0F98 */
6849 {
6850 { MOD_TABLE (MOD_VEX_0F98_L_0) },
6851 },
6852
6853 /* VEX_LEN_0F99 */
6854 {
6855 { MOD_TABLE (MOD_VEX_0F99_L_0) },
6856 },
6857
6858 /* VEX_LEN_0FAE_R_2_M_0 */
6859 {
6860 { "vldmxcsr", { Md }, 0 },
6861 },
6862
6863 /* VEX_LEN_0FAE_R_3_M_0 */
6864 {
6865 { "vstmxcsr", { Md }, 0 },
6866 },
6867
6868 /* VEX_LEN_0FC4 */
6869 {
6870 { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6871 },
6872
6873 /* VEX_LEN_0FC5 */
6874 {
6875 { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
6876 },
6877
6878 /* VEX_LEN_0FD6 */
6879 {
6880 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6881 },
6882
6883 /* VEX_LEN_0FF7 */
6884 {
6885 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6886 },
6887
6888 /* VEX_LEN_0F3816 */
6889 {
6890 { Bad_Opcode },
6891 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6892 },
6893
6894 /* VEX_LEN_0F3819 */
6895 {
6896 { Bad_Opcode },
6897 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6898 },
6899
6900 /* VEX_LEN_0F381A_M_0 */
6901 {
6902 { Bad_Opcode },
6903 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6904 },
6905
6906 /* VEX_LEN_0F3836 */
6907 {
6908 { Bad_Opcode },
6909 { VEX_W_TABLE (VEX_W_0F3836) },
6910 },
6911
6912 /* VEX_LEN_0F3841 */
6913 {
6914 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
6915 },
6916
6917 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6918 {
6919 { "ldtilecfg", { M }, 0 },
6920 },
6921
6922 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6923 {
6924 { "tilerelease", { Skip_MODRM }, 0 },
6925 },
6926
6927 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6928 {
6929 { "sttilecfg", { M }, 0 },
6930 },
6931
6932 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6933 {
6934 { "tilezero", { TMM, Skip_MODRM }, 0 },
6935 },
6936
6937 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6938 {
6939 { "tilestored", { MVexSIBMEM, TMM }, 0 },
6940 },
6941 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6942 {
6943 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6944 },
6945
6946 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6947 {
6948 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6949 },
6950
6951 /* VEX_LEN_0F385A_M_0 */
6952 {
6953 { Bad_Opcode },
6954 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6955 },
6956
6957 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6958 {
6959 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6960 },
6961
6962 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6963 {
6964 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6965 },
6966
6967 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6968 {
6969 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6970 },
6971
6972 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6973 {
6974 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6975 },
6976
6977 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6978 {
6979 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6980 },
6981
6982 /* VEX_LEN_0F38DB */
6983 {
6984 { "vaesimc", { XM, EXx }, PREFIX_DATA },
6985 },
6986
6987 /* VEX_LEN_0F38F2 */
6988 {
6989 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6990 },
6991
6992 /* VEX_LEN_0F38F3 */
6993 {
6994 { REG_TABLE(REG_VEX_0F38F3_L_0) },
6995 },
6996
6997 /* VEX_LEN_0F38F5 */
6998 {
6999 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7000 },
7001
7002 /* VEX_LEN_0F38F6 */
7003 {
7004 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7005 },
7006
7007 /* VEX_LEN_0F38F7 */
7008 {
7009 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7010 },
7011
7012 /* VEX_LEN_0F3A00 */
7013 {
7014 { Bad_Opcode },
7015 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7016 },
7017
7018 /* VEX_LEN_0F3A01 */
7019 {
7020 { Bad_Opcode },
7021 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7022 },
7023
7024 /* VEX_LEN_0F3A06 */
7025 {
7026 { Bad_Opcode },
7027 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7028 },
7029
7030 /* VEX_LEN_0F3A14 */
7031 {
7032 { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
7033 },
7034
7035 /* VEX_LEN_0F3A15 */
7036 {
7037 { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
7038 },
7039
7040 /* VEX_LEN_0F3A16 */
7041 {
7042 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7043 },
7044
7045 /* VEX_LEN_0F3A17 */
7046 {
7047 { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
7048 },
7049
7050 /* VEX_LEN_0F3A18 */
7051 {
7052 { Bad_Opcode },
7053 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7054 },
7055
7056 /* VEX_LEN_0F3A19 */
7057 {
7058 { Bad_Opcode },
7059 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7060 },
7061
7062 /* VEX_LEN_0F3A20 */
7063 {
7064 { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7065 },
7066
7067 /* VEX_LEN_0F3A21 */
7068 {
7069 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7070 },
7071
7072 /* VEX_LEN_0F3A22 */
7073 {
7074 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7075 },
7076
7077 /* VEX_LEN_0F3A30 */
7078 {
7079 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7080 },
7081
7082 /* VEX_LEN_0F3A31 */
7083 {
7084 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7085 },
7086
7087 /* VEX_LEN_0F3A32 */
7088 {
7089 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7090 },
7091
7092 /* VEX_LEN_0F3A33 */
7093 {
7094 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7095 },
7096
7097 /* VEX_LEN_0F3A38 */
7098 {
7099 { Bad_Opcode },
7100 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7101 },
7102
7103 /* VEX_LEN_0F3A39 */
7104 {
7105 { Bad_Opcode },
7106 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7107 },
7108
7109 /* VEX_LEN_0F3A41 */
7110 {
7111 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7112 },
7113
7114 /* VEX_LEN_0F3A46 */
7115 {
7116 { Bad_Opcode },
7117 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7118 },
7119
7120 /* VEX_LEN_0F3A60 */
7121 {
7122 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7123 },
7124
7125 /* VEX_LEN_0F3A61 */
7126 {
7127 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7128 },
7129
7130 /* VEX_LEN_0F3A62 */
7131 {
7132 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7133 },
7134
7135 /* VEX_LEN_0F3A63 */
7136 {
7137 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7138 },
7139
7140 /* VEX_LEN_0F3ADF */
7141 {
7142 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7143 },
7144
7145 /* VEX_LEN_0F3AF0 */
7146 {
7147 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7148 },
7149
7150 /* VEX_LEN_0FXOP_08_85 */
7151 {
7152 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7153 },
7154
7155 /* VEX_LEN_0FXOP_08_86 */
7156 {
7157 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7158 },
7159
7160 /* VEX_LEN_0FXOP_08_87 */
7161 {
7162 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7163 },
7164
7165 /* VEX_LEN_0FXOP_08_8E */
7166 {
7167 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7168 },
7169
7170 /* VEX_LEN_0FXOP_08_8F */
7171 {
7172 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7173 },
7174
7175 /* VEX_LEN_0FXOP_08_95 */
7176 {
7177 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7178 },
7179
7180 /* VEX_LEN_0FXOP_08_96 */
7181 {
7182 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7183 },
7184
7185 /* VEX_LEN_0FXOP_08_97 */
7186 {
7187 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7188 },
7189
7190 /* VEX_LEN_0FXOP_08_9E */
7191 {
7192 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7193 },
7194
7195 /* VEX_LEN_0FXOP_08_9F */
7196 {
7197 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7198 },
7199
7200 /* VEX_LEN_0FXOP_08_A3 */
7201 {
7202 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7203 },
7204
7205 /* VEX_LEN_0FXOP_08_A6 */
7206 {
7207 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7208 },
7209
7210 /* VEX_LEN_0FXOP_08_B6 */
7211 {
7212 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7213 },
7214
7215 /* VEX_LEN_0FXOP_08_C0 */
7216 {
7217 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7218 },
7219
7220 /* VEX_LEN_0FXOP_08_C1 */
7221 {
7222 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7223 },
7224
7225 /* VEX_LEN_0FXOP_08_C2 */
7226 {
7227 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7228 },
7229
7230 /* VEX_LEN_0FXOP_08_C3 */
7231 {
7232 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7233 },
7234
7235 /* VEX_LEN_0FXOP_08_CC */
7236 {
7237 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7238 },
7239
7240 /* VEX_LEN_0FXOP_08_CD */
7241 {
7242 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7243 },
7244
7245 /* VEX_LEN_0FXOP_08_CE */
7246 {
7247 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7248 },
7249
7250 /* VEX_LEN_0FXOP_08_CF */
7251 {
7252 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7253 },
7254
7255 /* VEX_LEN_0FXOP_08_EC */
7256 {
7257 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7258 },
7259
7260 /* VEX_LEN_0FXOP_08_ED */
7261 {
7262 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7263 },
7264
7265 /* VEX_LEN_0FXOP_08_EE */
7266 {
7267 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7268 },
7269
7270 /* VEX_LEN_0FXOP_08_EF */
7271 {
7272 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7273 },
7274
7275 /* VEX_LEN_0FXOP_09_01 */
7276 {
7277 { REG_TABLE (REG_XOP_09_01_L_0) },
7278 },
7279
7280 /* VEX_LEN_0FXOP_09_02 */
7281 {
7282 { REG_TABLE (REG_XOP_09_02_L_0) },
7283 },
7284
7285 /* VEX_LEN_0FXOP_09_12_M_1 */
7286 {
7287 { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7288 },
7289
7290 /* VEX_LEN_0FXOP_09_82_W_0 */
7291 {
7292 { "vfrczss", { XM, EXd }, 0 },
7293 },
7294
7295 /* VEX_LEN_0FXOP_09_83_W_0 */
7296 {
7297 { "vfrczsd", { XM, EXq }, 0 },
7298 },
7299
7300 /* VEX_LEN_0FXOP_09_90 */
7301 {
7302 { "vprotb", { XM, EXx, VexW }, 0 },
7303 },
7304
7305 /* VEX_LEN_0FXOP_09_91 */
7306 {
7307 { "vprotw", { XM, EXx, VexW }, 0 },
7308 },
7309
7310 /* VEX_LEN_0FXOP_09_92 */
7311 {
7312 { "vprotd", { XM, EXx, VexW }, 0 },
7313 },
7314
7315 /* VEX_LEN_0FXOP_09_93 */
7316 {
7317 { "vprotq", { XM, EXx, VexW }, 0 },
7318 },
7319
7320 /* VEX_LEN_0FXOP_09_94 */
7321 {
7322 { "vpshlb", { XM, EXx, VexW }, 0 },
7323 },
7324
7325 /* VEX_LEN_0FXOP_09_95 */
7326 {
7327 { "vpshlw", { XM, EXx, VexW }, 0 },
7328 },
7329
7330 /* VEX_LEN_0FXOP_09_96 */
7331 {
7332 { "vpshld", { XM, EXx, VexW }, 0 },
7333 },
7334
7335 /* VEX_LEN_0FXOP_09_97 */
7336 {
7337 { "vpshlq", { XM, EXx, VexW }, 0 },
7338 },
7339
7340 /* VEX_LEN_0FXOP_09_98 */
7341 {
7342 { "vpshab", { XM, EXx, VexW }, 0 },
7343 },
7344
7345 /* VEX_LEN_0FXOP_09_99 */
7346 {
7347 { "vpshaw", { XM, EXx, VexW }, 0 },
7348 },
7349
7350 /* VEX_LEN_0FXOP_09_9A */
7351 {
7352 { "vpshad", { XM, EXx, VexW }, 0 },
7353 },
7354
7355 /* VEX_LEN_0FXOP_09_9B */
7356 {
7357 { "vpshaq", { XM, EXx, VexW }, 0 },
7358 },
7359
7360 /* VEX_LEN_0FXOP_09_C1 */
7361 {
7362 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7363 },
7364
7365 /* VEX_LEN_0FXOP_09_C2 */
7366 {
7367 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7368 },
7369
7370 /* VEX_LEN_0FXOP_09_C3 */
7371 {
7372 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7373 },
7374
7375 /* VEX_LEN_0FXOP_09_C6 */
7376 {
7377 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7378 },
7379
7380 /* VEX_LEN_0FXOP_09_C7 */
7381 {
7382 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7383 },
7384
7385 /* VEX_LEN_0FXOP_09_CB */
7386 {
7387 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7388 },
7389
7390 /* VEX_LEN_0FXOP_09_D1 */
7391 {
7392 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7393 },
7394
7395 /* VEX_LEN_0FXOP_09_D2 */
7396 {
7397 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7398 },
7399
7400 /* VEX_LEN_0FXOP_09_D3 */
7401 {
7402 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7403 },
7404
7405 /* VEX_LEN_0FXOP_09_D6 */
7406 {
7407 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7408 },
7409
7410 /* VEX_LEN_0FXOP_09_D7 */
7411 {
7412 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7413 },
7414
7415 /* VEX_LEN_0FXOP_09_DB */
7416 {
7417 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7418 },
7419
7420 /* VEX_LEN_0FXOP_09_E1 */
7421 {
7422 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7423 },
7424
7425 /* VEX_LEN_0FXOP_09_E2 */
7426 {
7427 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7428 },
7429
7430 /* VEX_LEN_0FXOP_09_E3 */
7431 {
7432 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7433 },
7434
7435 /* VEX_LEN_0FXOP_0A_12 */
7436 {
7437 { REG_TABLE (REG_XOP_0A_12_L_0) },
7438 },
7439 };
7440
7441 #include "i386-dis-evex-len.h"
7442
7443 static const struct dis386 vex_w_table[][2] = {
7444 {
7445 /* VEX_W_0F41_L_1_M_1 */
7446 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7447 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7448 },
7449 {
7450 /* VEX_W_0F42_L_1_M_1 */
7451 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7452 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7453 },
7454 {
7455 /* VEX_W_0F44_L_0_M_1 */
7456 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7457 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7458 },
7459 {
7460 /* VEX_W_0F45_L_1_M_1 */
7461 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7462 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7463 },
7464 {
7465 /* VEX_W_0F46_L_1_M_1 */
7466 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7467 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7468 },
7469 {
7470 /* VEX_W_0F47_L_1_M_1 */
7471 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7472 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7473 },
7474 {
7475 /* VEX_W_0F4A_L_1_M_1 */
7476 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7477 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7478 },
7479 {
7480 /* VEX_W_0F4B_L_1_M_1 */
7481 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7482 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7483 },
7484 {
7485 /* VEX_W_0F90_L_0 */
7486 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7487 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7488 },
7489 {
7490 /* VEX_W_0F91_L_0_M_0 */
7491 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7492 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7493 },
7494 {
7495 /* VEX_W_0F92_L_0_M_1 */
7496 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7497 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7498 },
7499 {
7500 /* VEX_W_0F93_L_0_M_1 */
7501 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7502 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7503 },
7504 {
7505 /* VEX_W_0F98_L_0_M_1 */
7506 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7507 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7508 },
7509 {
7510 /* VEX_W_0F99_L_0_M_1 */
7511 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7512 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7513 },
7514 {
7515 /* VEX_W_0F380C */
7516 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7517 },
7518 {
7519 /* VEX_W_0F380D */
7520 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7521 },
7522 {
7523 /* VEX_W_0F380E */
7524 { "vtestps", { XM, EXx }, PREFIX_DATA },
7525 },
7526 {
7527 /* VEX_W_0F380F */
7528 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7529 },
7530 {
7531 /* VEX_W_0F3813 */
7532 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7533 },
7534 {
7535 /* VEX_W_0F3816_L_1 */
7536 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7537 },
7538 {
7539 /* VEX_W_0F3818 */
7540 { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
7541 },
7542 {
7543 /* VEX_W_0F3819_L_1 */
7544 { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
7545 },
7546 {
7547 /* VEX_W_0F381A_M_0_L_1 */
7548 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7549 },
7550 {
7551 /* VEX_W_0F382C_M_0 */
7552 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7553 },
7554 {
7555 /* VEX_W_0F382D_M_0 */
7556 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7557 },
7558 {
7559 /* VEX_W_0F382E_M_0 */
7560 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7561 },
7562 {
7563 /* VEX_W_0F382F_M_0 */
7564 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7565 },
7566 {
7567 /* VEX_W_0F3836 */
7568 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7569 },
7570 {
7571 /* VEX_W_0F3846 */
7572 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7573 },
7574 {
7575 /* VEX_W_0F3849_X86_64_P_0 */
7576 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7577 },
7578 {
7579 /* VEX_W_0F3849_X86_64_P_2 */
7580 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7581 },
7582 {
7583 /* VEX_W_0F3849_X86_64_P_3 */
7584 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7585 },
7586 {
7587 /* VEX_W_0F384B_X86_64_P_1 */
7588 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7589 },
7590 {
7591 /* VEX_W_0F384B_X86_64_P_2 */
7592 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7593 },
7594 {
7595 /* VEX_W_0F384B_X86_64_P_3 */
7596 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7597 },
7598 {
7599 /* VEX_W_0F3850 */
7600 { "%XV vpdpbusd", { XM, Vex, EXx }, 0 },
7601 },
7602 {
7603 /* VEX_W_0F3851 */
7604 { "%XV vpdpbusds", { XM, Vex, EXx }, 0 },
7605 },
7606 {
7607 /* VEX_W_0F3852 */
7608 { "%XV vpdpwssd", { XM, Vex, EXx }, 0 },
7609 },
7610 {
7611 /* VEX_W_0F3853 */
7612 { "%XV vpdpwssds", { XM, Vex, EXx }, 0 },
7613 },
7614 {
7615 /* VEX_W_0F3858 */
7616 { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7617 },
7618 {
7619 /* VEX_W_0F3859 */
7620 { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
7621 },
7622 {
7623 /* VEX_W_0F385A_M_0_L_0 */
7624 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7625 },
7626 {
7627 /* VEX_W_0F385C_X86_64_P_1 */
7628 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7629 },
7630 {
7631 /* VEX_W_0F385E_X86_64_P_0 */
7632 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7633 },
7634 {
7635 /* VEX_W_0F385E_X86_64_P_1 */
7636 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7637 },
7638 {
7639 /* VEX_W_0F385E_X86_64_P_2 */
7640 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7641 },
7642 {
7643 /* VEX_W_0F385E_X86_64_P_3 */
7644 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7645 },
7646 {
7647 /* VEX_W_0F3878 */
7648 { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
7649 },
7650 {
7651 /* VEX_W_0F3879 */
7652 { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
7653 },
7654 {
7655 /* VEX_W_0F38CF */
7656 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7657 },
7658 {
7659 /* VEX_W_0F3A00_L_1 */
7660 { Bad_Opcode },
7661 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7662 },
7663 {
7664 /* VEX_W_0F3A01_L_1 */
7665 { Bad_Opcode },
7666 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7667 },
7668 {
7669 /* VEX_W_0F3A02 */
7670 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7671 },
7672 {
7673 /* VEX_W_0F3A04 */
7674 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7675 },
7676 {
7677 /* VEX_W_0F3A05 */
7678 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7679 },
7680 {
7681 /* VEX_W_0F3A06_L_1 */
7682 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7683 },
7684 {
7685 /* VEX_W_0F3A18_L_1 */
7686 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7687 },
7688 {
7689 /* VEX_W_0F3A19_L_1 */
7690 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7691 },
7692 {
7693 /* VEX_W_0F3A1D */
7694 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7695 },
7696 {
7697 /* VEX_W_0F3A38_L_1 */
7698 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7699 },
7700 {
7701 /* VEX_W_0F3A39_L_1 */
7702 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7703 },
7704 {
7705 /* VEX_W_0F3A46_L_1 */
7706 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7707 },
7708 {
7709 /* VEX_W_0F3A4A */
7710 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7711 },
7712 {
7713 /* VEX_W_0F3A4B */
7714 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7715 },
7716 {
7717 /* VEX_W_0F3A4C */
7718 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7719 },
7720 {
7721 /* VEX_W_0F3ACE */
7722 { Bad_Opcode },
7723 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7724 },
7725 {
7726 /* VEX_W_0F3ACF */
7727 { Bad_Opcode },
7728 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7729 },
7730 /* VEX_W_0FXOP_08_85_L_0 */
7731 {
7732 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7733 },
7734 /* VEX_W_0FXOP_08_86_L_0 */
7735 {
7736 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7737 },
7738 /* VEX_W_0FXOP_08_87_L_0 */
7739 {
7740 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7741 },
7742 /* VEX_W_0FXOP_08_8E_L_0 */
7743 {
7744 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7745 },
7746 /* VEX_W_0FXOP_08_8F_L_0 */
7747 {
7748 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7749 },
7750 /* VEX_W_0FXOP_08_95_L_0 */
7751 {
7752 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7753 },
7754 /* VEX_W_0FXOP_08_96_L_0 */
7755 {
7756 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7757 },
7758 /* VEX_W_0FXOP_08_97_L_0 */
7759 {
7760 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7761 },
7762 /* VEX_W_0FXOP_08_9E_L_0 */
7763 {
7764 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7765 },
7766 /* VEX_W_0FXOP_08_9F_L_0 */
7767 {
7768 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7769 },
7770 /* VEX_W_0FXOP_08_A6_L_0 */
7771 {
7772 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7773 },
7774 /* VEX_W_0FXOP_08_B6_L_0 */
7775 {
7776 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7777 },
7778 /* VEX_W_0FXOP_08_C0_L_0 */
7779 {
7780 { "vprotb", { XM, EXx, Ib }, 0 },
7781 },
7782 /* VEX_W_0FXOP_08_C1_L_0 */
7783 {
7784 { "vprotw", { XM, EXx, Ib }, 0 },
7785 },
7786 /* VEX_W_0FXOP_08_C2_L_0 */
7787 {
7788 { "vprotd", { XM, EXx, Ib }, 0 },
7789 },
7790 /* VEX_W_0FXOP_08_C3_L_0 */
7791 {
7792 { "vprotq", { XM, EXx, Ib }, 0 },
7793 },
7794 /* VEX_W_0FXOP_08_CC_L_0 */
7795 {
7796 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7797 },
7798 /* VEX_W_0FXOP_08_CD_L_0 */
7799 {
7800 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7801 },
7802 /* VEX_W_0FXOP_08_CE_L_0 */
7803 {
7804 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7805 },
7806 /* VEX_W_0FXOP_08_CF_L_0 */
7807 {
7808 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7809 },
7810 /* VEX_W_0FXOP_08_EC_L_0 */
7811 {
7812 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7813 },
7814 /* VEX_W_0FXOP_08_ED_L_0 */
7815 {
7816 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7817 },
7818 /* VEX_W_0FXOP_08_EE_L_0 */
7819 {
7820 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7821 },
7822 /* VEX_W_0FXOP_08_EF_L_0 */
7823 {
7824 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7825 },
7826 /* VEX_W_0FXOP_09_80 */
7827 {
7828 { "vfrczps", { XM, EXx }, 0 },
7829 },
7830 /* VEX_W_0FXOP_09_81 */
7831 {
7832 { "vfrczpd", { XM, EXx }, 0 },
7833 },
7834 /* VEX_W_0FXOP_09_82 */
7835 {
7836 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7837 },
7838 /* VEX_W_0FXOP_09_83 */
7839 {
7840 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7841 },
7842 /* VEX_W_0FXOP_09_C1_L_0 */
7843 {
7844 { "vphaddbw", { XM, EXxmm }, 0 },
7845 },
7846 /* VEX_W_0FXOP_09_C2_L_0 */
7847 {
7848 { "vphaddbd", { XM, EXxmm }, 0 },
7849 },
7850 /* VEX_W_0FXOP_09_C3_L_0 */
7851 {
7852 { "vphaddbq", { XM, EXxmm }, 0 },
7853 },
7854 /* VEX_W_0FXOP_09_C6_L_0 */
7855 {
7856 { "vphaddwd", { XM, EXxmm }, 0 },
7857 },
7858 /* VEX_W_0FXOP_09_C7_L_0 */
7859 {
7860 { "vphaddwq", { XM, EXxmm }, 0 },
7861 },
7862 /* VEX_W_0FXOP_09_CB_L_0 */
7863 {
7864 { "vphadddq", { XM, EXxmm }, 0 },
7865 },
7866 /* VEX_W_0FXOP_09_D1_L_0 */
7867 {
7868 { "vphaddubw", { XM, EXxmm }, 0 },
7869 },
7870 /* VEX_W_0FXOP_09_D2_L_0 */
7871 {
7872 { "vphaddubd", { XM, EXxmm }, 0 },
7873 },
7874 /* VEX_W_0FXOP_09_D3_L_0 */
7875 {
7876 { "vphaddubq", { XM, EXxmm }, 0 },
7877 },
7878 /* VEX_W_0FXOP_09_D6_L_0 */
7879 {
7880 { "vphadduwd", { XM, EXxmm }, 0 },
7881 },
7882 /* VEX_W_0FXOP_09_D7_L_0 */
7883 {
7884 { "vphadduwq", { XM, EXxmm }, 0 },
7885 },
7886 /* VEX_W_0FXOP_09_DB_L_0 */
7887 {
7888 { "vphaddudq", { XM, EXxmm }, 0 },
7889 },
7890 /* VEX_W_0FXOP_09_E1_L_0 */
7891 {
7892 { "vphsubbw", { XM, EXxmm }, 0 },
7893 },
7894 /* VEX_W_0FXOP_09_E2_L_0 */
7895 {
7896 { "vphsubwd", { XM, EXxmm }, 0 },
7897 },
7898 /* VEX_W_0FXOP_09_E3_L_0 */
7899 {
7900 { "vphsubdq", { XM, EXxmm }, 0 },
7901 },
7902
7903 #include "i386-dis-evex-w.h"
7904 };
7905
7906 static const struct dis386 mod_table[][2] = {
7907 {
7908 /* MOD_62_32BIT */
7909 { "bound{S|}", { Gv, Ma }, 0 },
7910 { EVEX_TABLE (EVEX_0F) },
7911 },
7912 {
7913 /* MOD_8D */
7914 { "leaS", { Gv, M }, 0 },
7915 },
7916 {
7917 /* MOD_C4_32BIT */
7918 { "lesS", { Gv, Mp }, 0 },
7919 { VEX_C4_TABLE (VEX_0F) },
7920 },
7921 {
7922 /* MOD_C5_32BIT */
7923 { "ldsS", { Gv, Mp }, 0 },
7924 { VEX_C5_TABLE (VEX_0F) },
7925 },
7926 {
7927 /* MOD_C6_REG_7 */
7928 { Bad_Opcode },
7929 { RM_TABLE (RM_C6_REG_7) },
7930 },
7931 {
7932 /* MOD_C7_REG_7 */
7933 { Bad_Opcode },
7934 { RM_TABLE (RM_C7_REG_7) },
7935 },
7936 {
7937 /* MOD_FF_REG_3 */
7938 { "{l|}call^", { indirEp }, 0 },
7939 },
7940 {
7941 /* MOD_FF_REG_5 */
7942 { "{l|}jmp^", { indirEp }, 0 },
7943 },
7944 {
7945 /* MOD_0F01_REG_0 */
7946 { X86_64_TABLE (X86_64_0F01_REG_0) },
7947 { RM_TABLE (RM_0F01_REG_0) },
7948 },
7949 {
7950 /* MOD_0F01_REG_1 */
7951 { X86_64_TABLE (X86_64_0F01_REG_1) },
7952 { RM_TABLE (RM_0F01_REG_1) },
7953 },
7954 {
7955 /* MOD_0F01_REG_2 */
7956 { X86_64_TABLE (X86_64_0F01_REG_2) },
7957 { RM_TABLE (RM_0F01_REG_2) },
7958 },
7959 {
7960 /* MOD_0F01_REG_3 */
7961 { X86_64_TABLE (X86_64_0F01_REG_3) },
7962 { RM_TABLE (RM_0F01_REG_3) },
7963 },
7964 {
7965 /* MOD_0F01_REG_5 */
7966 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7967 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7968 },
7969 {
7970 /* MOD_0F01_REG_7 */
7971 { "invlpg", { Mb }, 0 },
7972 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7973 },
7974 {
7975 /* MOD_0F12_PREFIX_0 */
7976 { "movlpX", { XM, EXq }, 0 },
7977 { "movhlps", { XM, EXq }, 0 },
7978 },
7979 {
7980 /* MOD_0F12_PREFIX_2 */
7981 { "movlpX", { XM, EXq }, 0 },
7982 },
7983 {
7984 /* MOD_0F13 */
7985 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
7986 },
7987 {
7988 /* MOD_0F16_PREFIX_0 */
7989 { "movhpX", { XM, EXq }, 0 },
7990 { "movlhps", { XM, EXq }, 0 },
7991 },
7992 {
7993 /* MOD_0F16_PREFIX_2 */
7994 { "movhpX", { XM, EXq }, 0 },
7995 },
7996 {
7997 /* MOD_0F17 */
7998 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
7999 },
8000 {
8001 /* MOD_0F18_REG_0 */
8002 { "prefetchnta", { Mb }, 0 },
8003 { "nopQ", { Ev }, 0 },
8004 },
8005 {
8006 /* MOD_0F18_REG_1 */
8007 { "prefetcht0", { Mb }, 0 },
8008 { "nopQ", { Ev }, 0 },
8009 },
8010 {
8011 /* MOD_0F18_REG_2 */
8012 { "prefetcht1", { Mb }, 0 },
8013 { "nopQ", { Ev }, 0 },
8014 },
8015 {
8016 /* MOD_0F18_REG_3 */
8017 { "prefetcht2", { Mb }, 0 },
8018 { "nopQ", { Ev }, 0 },
8019 },
8020 {
8021 /* MOD_0F1A_PREFIX_0 */
8022 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8023 { "nopQ", { Ev }, 0 },
8024 },
8025 {
8026 /* MOD_0F1B_PREFIX_0 */
8027 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8028 { "nopQ", { Ev }, 0 },
8029 },
8030 {
8031 /* MOD_0F1B_PREFIX_1 */
8032 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8033 { "nopQ", { Ev }, PREFIX_IGNORED },
8034 },
8035 {
8036 /* MOD_0F1C_PREFIX_0 */
8037 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8038 { "nopQ", { Ev }, 0 },
8039 },
8040 {
8041 /* MOD_0F1E_PREFIX_1 */
8042 { "nopQ", { Ev }, PREFIX_IGNORED },
8043 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8044 },
8045 {
8046 /* MOD_0F2B_PREFIX_0 */
8047 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8048 },
8049 {
8050 /* MOD_0F2B_PREFIX_1 */
8051 {"movntss", { Md, XM }, PREFIX_OPCODE },
8052 },
8053 {
8054 /* MOD_0F2B_PREFIX_2 */
8055 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8056 },
8057 {
8058 /* MOD_0F2B_PREFIX_3 */
8059 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8060 },
8061 {
8062 /* MOD_0F50 */
8063 { Bad_Opcode },
8064 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8065 },
8066 {
8067 /* MOD_0F71 */
8068 { Bad_Opcode },
8069 { REG_TABLE (REG_0F71_MOD_0) },
8070 },
8071 {
8072 /* MOD_0F72 */
8073 { Bad_Opcode },
8074 { REG_TABLE (REG_0F72_MOD_0) },
8075 },
8076 {
8077 /* MOD_0F73 */
8078 { Bad_Opcode },
8079 { REG_TABLE (REG_0F73_MOD_0) },
8080 },
8081 {
8082 /* MOD_0FAE_REG_0 */
8083 { "fxsave", { FXSAVE }, 0 },
8084 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8085 },
8086 {
8087 /* MOD_0FAE_REG_1 */
8088 { "fxrstor", { FXSAVE }, 0 },
8089 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8090 },
8091 {
8092 /* MOD_0FAE_REG_2 */
8093 { "ldmxcsr", { Md }, 0 },
8094 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8095 },
8096 {
8097 /* MOD_0FAE_REG_3 */
8098 { "stmxcsr", { Md }, 0 },
8099 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8100 },
8101 {
8102 /* MOD_0FAE_REG_4 */
8103 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8104 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8105 },
8106 {
8107 /* MOD_0FAE_REG_5 */
8108 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8109 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8110 },
8111 {
8112 /* MOD_0FAE_REG_6 */
8113 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8114 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8115 },
8116 {
8117 /* MOD_0FAE_REG_7 */
8118 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8119 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8120 },
8121 {
8122 /* MOD_0FB2 */
8123 { "lssS", { Gv, Mp }, 0 },
8124 },
8125 {
8126 /* MOD_0FB4 */
8127 { "lfsS", { Gv, Mp }, 0 },
8128 },
8129 {
8130 /* MOD_0FB5 */
8131 { "lgsS", { Gv, Mp }, 0 },
8132 },
8133 {
8134 /* MOD_0FC3 */
8135 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8136 },
8137 {
8138 /* MOD_0FC7_REG_3 */
8139 { "xrstors", { FXSAVE }, 0 },
8140 },
8141 {
8142 /* MOD_0FC7_REG_4 */
8143 { "xsavec", { FXSAVE }, 0 },
8144 },
8145 {
8146 /* MOD_0FC7_REG_5 */
8147 { "xsaves", { FXSAVE }, 0 },
8148 },
8149 {
8150 /* MOD_0FC7_REG_6 */
8151 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8152 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8153 },
8154 {
8155 /* MOD_0FC7_REG_7 */
8156 { "vmptrst", { Mq }, 0 },
8157 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8158 },
8159 {
8160 /* MOD_0FD7 */
8161 { Bad_Opcode },
8162 { "pmovmskb", { Gdq, MS }, 0 },
8163 },
8164 {
8165 /* MOD_0FE7_PREFIX_2 */
8166 { "movntdq", { Mx, XM }, 0 },
8167 },
8168 {
8169 /* MOD_0FF0_PREFIX_3 */
8170 { "lddqu", { XM, M }, 0 },
8171 },
8172 {
8173 /* MOD_0F382A */
8174 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8175 },
8176 {
8177 /* MOD_0F38DC_PREFIX_1 */
8178 { "aesenc128kl", { XM, M }, 0 },
8179 { "loadiwkey", { XM, EXx }, 0 },
8180 },
8181 {
8182 /* MOD_0F38DD_PREFIX_1 */
8183 { "aesdec128kl", { XM, M }, 0 },
8184 },
8185 {
8186 /* MOD_0F38DE_PREFIX_1 */
8187 { "aesenc256kl", { XM, M }, 0 },
8188 },
8189 {
8190 /* MOD_0F38DF_PREFIX_1 */
8191 { "aesdec256kl", { XM, M }, 0 },
8192 },
8193 {
8194 /* MOD_0F38F5 */
8195 { "wrussK", { M, Gdq }, PREFIX_DATA },
8196 },
8197 {
8198 /* MOD_0F38F6_PREFIX_0 */
8199 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8200 },
8201 {
8202 /* MOD_0F38F8_PREFIX_1 */
8203 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8204 },
8205 {
8206 /* MOD_0F38F8_PREFIX_2 */
8207 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8208 },
8209 {
8210 /* MOD_0F38F8_PREFIX_3 */
8211 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8212 },
8213 {
8214 /* MOD_0F38F9 */
8215 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8216 },
8217 {
8218 /* MOD_0F38FA_PREFIX_1 */
8219 { Bad_Opcode },
8220 { "encodekey128", { Gd, Ed }, 0 },
8221 },
8222 {
8223 /* MOD_0F38FB_PREFIX_1 */
8224 { Bad_Opcode },
8225 { "encodekey256", { Gd, Ed }, 0 },
8226 },
8227 {
8228 /* MOD_0F3A0F_PREFIX_1 */
8229 { Bad_Opcode },
8230 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8231 },
8232 {
8233 /* MOD_VEX_0F12_PREFIX_0 */
8234 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8235 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8236 },
8237 {
8238 /* MOD_VEX_0F12_PREFIX_2 */
8239 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8240 },
8241 {
8242 /* MOD_VEX_0F13 */
8243 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8244 },
8245 {
8246 /* MOD_VEX_0F16_PREFIX_0 */
8247 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8248 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8249 },
8250 {
8251 /* MOD_VEX_0F16_PREFIX_2 */
8252 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8253 },
8254 {
8255 /* MOD_VEX_0F17 */
8256 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8257 },
8258 {
8259 /* MOD_VEX_0F2B */
8260 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8261 },
8262 {
8263 /* MOD_VEX_0F41_L_1 */
8264 { Bad_Opcode },
8265 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8266 },
8267 {
8268 /* MOD_VEX_0F42_L_1 */
8269 { Bad_Opcode },
8270 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8271 },
8272 {
8273 /* MOD_VEX_0F44_L_0 */
8274 { Bad_Opcode },
8275 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8276 },
8277 {
8278 /* MOD_VEX_0F45_L_1 */
8279 { Bad_Opcode },
8280 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8281 },
8282 {
8283 /* MOD_VEX_0F46_L_1 */
8284 { Bad_Opcode },
8285 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8286 },
8287 {
8288 /* MOD_VEX_0F47_L_1 */
8289 { Bad_Opcode },
8290 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8291 },
8292 {
8293 /* MOD_VEX_0F4A_L_1 */
8294 { Bad_Opcode },
8295 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8296 },
8297 {
8298 /* MOD_VEX_0F4B_L_1 */
8299 { Bad_Opcode },
8300 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8301 },
8302 {
8303 /* MOD_VEX_0F50 */
8304 { Bad_Opcode },
8305 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8306 },
8307 {
8308 /* MOD_VEX_0F71 */
8309 { Bad_Opcode },
8310 { REG_TABLE (REG_VEX_0F71_M_0) },
8311 },
8312 {
8313 /* MOD_VEX_0F72 */
8314 { Bad_Opcode },
8315 { REG_TABLE (REG_VEX_0F72_M_0) },
8316 },
8317 {
8318 /* MOD_VEX_0F73 */
8319 { Bad_Opcode },
8320 { REG_TABLE (REG_VEX_0F73_M_0) },
8321 },
8322 {
8323 /* MOD_VEX_0F91_L_0 */
8324 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8325 },
8326 {
8327 /* MOD_VEX_0F92_L_0 */
8328 { Bad_Opcode },
8329 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8330 },
8331 {
8332 /* MOD_VEX_0F93_L_0 */
8333 { Bad_Opcode },
8334 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8335 },
8336 {
8337 /* MOD_VEX_0F98_L_0 */
8338 { Bad_Opcode },
8339 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8340 },
8341 {
8342 /* MOD_VEX_0F99_L_0 */
8343 { Bad_Opcode },
8344 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8345 },
8346 {
8347 /* MOD_VEX_0FAE_REG_2 */
8348 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8349 },
8350 {
8351 /* MOD_VEX_0FAE_REG_3 */
8352 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8353 },
8354 {
8355 /* MOD_VEX_0FD7 */
8356 { Bad_Opcode },
8357 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8358 },
8359 {
8360 /* MOD_VEX_0FE7 */
8361 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8362 },
8363 {
8364 /* MOD_VEX_0FF0_PREFIX_3 */
8365 { "vlddqu", { XM, M }, 0 },
8366 },
8367 {
8368 /* MOD_VEX_0F381A */
8369 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8370 },
8371 {
8372 /* MOD_VEX_0F382A */
8373 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8374 },
8375 {
8376 /* MOD_VEX_0F382C */
8377 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8378 },
8379 {
8380 /* MOD_VEX_0F382D */
8381 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8382 },
8383 {
8384 /* MOD_VEX_0F382E */
8385 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8386 },
8387 {
8388 /* MOD_VEX_0F382F */
8389 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8390 },
8391 {
8392 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8393 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8394 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8395 },
8396 {
8397 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8398 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8399 },
8400 {
8401 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8402 { Bad_Opcode },
8403 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8404 },
8405 {
8406 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8407 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8408 },
8409 {
8410 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8411 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8412 },
8413 {
8414 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8415 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8416 },
8417 {
8418 /* MOD_VEX_0F385A */
8419 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8420 },
8421 {
8422 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8423 { Bad_Opcode },
8424 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8425 },
8426 {
8427 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8428 { Bad_Opcode },
8429 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8430 },
8431 {
8432 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8433 { Bad_Opcode },
8434 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8435 },
8436 {
8437 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8438 { Bad_Opcode },
8439 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8440 },
8441 {
8442 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8443 { Bad_Opcode },
8444 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8445 },
8446 {
8447 /* MOD_VEX_0F388C */
8448 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8449 },
8450 {
8451 /* MOD_VEX_0F388E */
8452 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8453 },
8454 {
8455 /* MOD_VEX_0F3A30_L_0 */
8456 { Bad_Opcode },
8457 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8458 },
8459 {
8460 /* MOD_VEX_0F3A31_L_0 */
8461 { Bad_Opcode },
8462 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8463 },
8464 {
8465 /* MOD_VEX_0F3A32_L_0 */
8466 { Bad_Opcode },
8467 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8468 },
8469 {
8470 /* MOD_VEX_0F3A33_L_0 */
8471 { Bad_Opcode },
8472 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8473 },
8474 {
8475 /* MOD_XOP_09_12 */
8476 { Bad_Opcode },
8477 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8478 },
8479
8480 #include "i386-dis-evex-mod.h"
8481 };
8482
8483 static const struct dis386 rm_table[][8] = {
8484 {
8485 /* RM_C6_REG_7 */
8486 { "xabort", { Skip_MODRM, Ib }, 0 },
8487 },
8488 {
8489 /* RM_C7_REG_7 */
8490 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8491 },
8492 {
8493 /* RM_0F01_REG_0 */
8494 { "enclv", { Skip_MODRM }, 0 },
8495 { "vmcall", { Skip_MODRM }, 0 },
8496 { "vmlaunch", { Skip_MODRM }, 0 },
8497 { "vmresume", { Skip_MODRM }, 0 },
8498 { "vmxoff", { Skip_MODRM }, 0 },
8499 { "pconfig", { Skip_MODRM }, 0 },
8500 },
8501 {
8502 /* RM_0F01_REG_1 */
8503 { "monitor", { { OP_Monitor, 0 } }, 0 },
8504 { "mwait", { { OP_Mwait, 0 } }, 0 },
8505 { "clac", { Skip_MODRM }, 0 },
8506 { "stac", { Skip_MODRM }, 0 },
8507 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8508 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8509 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8510 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8511 },
8512 {
8513 /* RM_0F01_REG_2 */
8514 { "xgetbv", { Skip_MODRM }, 0 },
8515 { "xsetbv", { Skip_MODRM }, 0 },
8516 { Bad_Opcode },
8517 { Bad_Opcode },
8518 { "vmfunc", { Skip_MODRM }, 0 },
8519 { "xend", { Skip_MODRM }, 0 },
8520 { "xtest", { Skip_MODRM }, 0 },
8521 { "enclu", { Skip_MODRM }, 0 },
8522 },
8523 {
8524 /* RM_0F01_REG_3 */
8525 { "vmrun", { Skip_MODRM }, 0 },
8526 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8527 { "vmload", { Skip_MODRM }, 0 },
8528 { "vmsave", { Skip_MODRM }, 0 },
8529 { "stgi", { Skip_MODRM }, 0 },
8530 { "clgi", { Skip_MODRM }, 0 },
8531 { "skinit", { Skip_MODRM }, 0 },
8532 { "invlpga", { Skip_MODRM }, 0 },
8533 },
8534 {
8535 /* RM_0F01_REG_5_MOD_3 */
8536 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8537 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8538 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8539 { Bad_Opcode },
8540 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8541 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8542 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8543 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8544 },
8545 {
8546 /* RM_0F01_REG_7_MOD_3 */
8547 { "swapgs", { Skip_MODRM }, 0 },
8548 { "rdtscp", { Skip_MODRM }, 0 },
8549 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8550 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8551 { "clzero", { Skip_MODRM }, 0 },
8552 { "rdpru", { Skip_MODRM }, 0 },
8553 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8554 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8555 },
8556 {
8557 /* RM_0F1E_P_1_MOD_3_REG_7 */
8558 { "nopQ", { Ev }, PREFIX_IGNORED },
8559 { "nopQ", { Ev }, PREFIX_IGNORED },
8560 { "endbr64", { Skip_MODRM }, 0 },
8561 { "endbr32", { Skip_MODRM }, 0 },
8562 { "nopQ", { Ev }, PREFIX_IGNORED },
8563 { "nopQ", { Ev }, PREFIX_IGNORED },
8564 { "nopQ", { Ev }, PREFIX_IGNORED },
8565 { "nopQ", { Ev }, PREFIX_IGNORED },
8566 },
8567 {
8568 /* RM_0FAE_REG_6_MOD_3 */
8569 { "mfence", { Skip_MODRM }, 0 },
8570 },
8571 {
8572 /* RM_0FAE_REG_7_MOD_3 */
8573 { "sfence", { Skip_MODRM }, 0 },
8574 },
8575 {
8576 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8577 { "hreset", { Skip_MODRM, Ib }, 0 },
8578 },
8579 {
8580 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8581 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8582 },
8583 };
8584
8585 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8586
8587 /* We use the high bit to indicate different name for the same
8588 prefix. */
8589 #define REP_PREFIX (0xf3 | 0x100)
8590 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8591 #define XRELEASE_PREFIX (0xf3 | 0x400)
8592 #define BND_PREFIX (0xf2 | 0x400)
8593 #define NOTRACK_PREFIX (0x3e | 0x100)
8594
8595 /* Remember if the current op is a jump instruction. */
8596 static bool op_is_jump = false;
8597
8598 static int
8599 ckprefix (void)
8600 {
8601 int newrex, i, length;
8602 rex = 0;
8603 prefixes = 0;
8604 used_prefixes = 0;
8605 rex_used = 0;
8606 last_lock_prefix = -1;
8607 last_repz_prefix = -1;
8608 last_repnz_prefix = -1;
8609 last_data_prefix = -1;
8610 last_addr_prefix = -1;
8611 last_rex_prefix = -1;
8612 last_seg_prefix = -1;
8613 fwait_prefix = -1;
8614 active_seg_prefix = 0;
8615 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8616 all_prefixes[i] = 0;
8617 i = 0;
8618 length = 0;
8619 /* The maximum instruction length is 15bytes. */
8620 while (length < MAX_CODE_LENGTH - 1)
8621 {
8622 FETCH_DATA (the_info, codep + 1);
8623 newrex = 0;
8624 switch (*codep)
8625 {
8626 /* REX prefixes family. */
8627 case 0x40:
8628 case 0x41:
8629 case 0x42:
8630 case 0x43:
8631 case 0x44:
8632 case 0x45:
8633 case 0x46:
8634 case 0x47:
8635 case 0x48:
8636 case 0x49:
8637 case 0x4a:
8638 case 0x4b:
8639 case 0x4c:
8640 case 0x4d:
8641 case 0x4e:
8642 case 0x4f:
8643 if (address_mode == mode_64bit)
8644 newrex = *codep;
8645 else
8646 return 1;
8647 last_rex_prefix = i;
8648 break;
8649 case 0xf3:
8650 prefixes |= PREFIX_REPZ;
8651 last_repz_prefix = i;
8652 break;
8653 case 0xf2:
8654 prefixes |= PREFIX_REPNZ;
8655 last_repnz_prefix = i;
8656 break;
8657 case 0xf0:
8658 prefixes |= PREFIX_LOCK;
8659 last_lock_prefix = i;
8660 break;
8661 case 0x2e:
8662 prefixes |= PREFIX_CS;
8663 last_seg_prefix = i;
8664
8665 if (address_mode != mode_64bit)
8666 active_seg_prefix = PREFIX_CS;
8667
8668 break;
8669 case 0x36:
8670 prefixes |= PREFIX_SS;
8671 last_seg_prefix = i;
8672
8673 if (address_mode != mode_64bit)
8674 active_seg_prefix = PREFIX_SS;
8675
8676 break;
8677 case 0x3e:
8678 prefixes |= PREFIX_DS;
8679 last_seg_prefix = i;
8680
8681 if (address_mode != mode_64bit)
8682 active_seg_prefix = PREFIX_DS;
8683
8684 break;
8685 case 0x26:
8686 prefixes |= PREFIX_ES;
8687 last_seg_prefix = i;
8688
8689 if (address_mode != mode_64bit)
8690 active_seg_prefix = PREFIX_ES;
8691
8692 break;
8693 case 0x64:
8694 prefixes |= PREFIX_FS;
8695 last_seg_prefix = i;
8696 active_seg_prefix = PREFIX_FS;
8697 break;
8698 case 0x65:
8699 prefixes |= PREFIX_GS;
8700 last_seg_prefix = i;
8701 active_seg_prefix = PREFIX_GS;
8702 break;
8703 case 0x66:
8704 prefixes |= PREFIX_DATA;
8705 last_data_prefix = i;
8706 break;
8707 case 0x67:
8708 prefixes |= PREFIX_ADDR;
8709 last_addr_prefix = i;
8710 break;
8711 case FWAIT_OPCODE:
8712 /* fwait is really an instruction. If there are prefixes
8713 before the fwait, they belong to the fwait, *not* to the
8714 following instruction. */
8715 fwait_prefix = i;
8716 if (prefixes || rex)
8717 {
8718 prefixes |= PREFIX_FWAIT;
8719 codep++;
8720 /* This ensures that the previous REX prefixes are noticed
8721 as unused prefixes, as in the return case below. */
8722 rex_used = rex;
8723 return 1;
8724 }
8725 prefixes = PREFIX_FWAIT;
8726 break;
8727 default:
8728 return 1;
8729 }
8730 /* Rex is ignored when followed by another prefix. */
8731 if (rex)
8732 {
8733 rex_used = rex;
8734 return 1;
8735 }
8736 if (*codep != FWAIT_OPCODE)
8737 all_prefixes[i++] = *codep;
8738 rex = newrex;
8739 codep++;
8740 length++;
8741 }
8742 return 0;
8743 }
8744
8745 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8746 prefix byte. */
8747
8748 static const char *
8749 prefix_name (int pref, int sizeflag)
8750 {
8751 static const char *rexes [16] =
8752 {
8753 "rex", /* 0x40 */
8754 "rex.B", /* 0x41 */
8755 "rex.X", /* 0x42 */
8756 "rex.XB", /* 0x43 */
8757 "rex.R", /* 0x44 */
8758 "rex.RB", /* 0x45 */
8759 "rex.RX", /* 0x46 */
8760 "rex.RXB", /* 0x47 */
8761 "rex.W", /* 0x48 */
8762 "rex.WB", /* 0x49 */
8763 "rex.WX", /* 0x4a */
8764 "rex.WXB", /* 0x4b */
8765 "rex.WR", /* 0x4c */
8766 "rex.WRB", /* 0x4d */
8767 "rex.WRX", /* 0x4e */
8768 "rex.WRXB", /* 0x4f */
8769 };
8770
8771 switch (pref)
8772 {
8773 /* REX prefixes family. */
8774 case 0x40:
8775 case 0x41:
8776 case 0x42:
8777 case 0x43:
8778 case 0x44:
8779 case 0x45:
8780 case 0x46:
8781 case 0x47:
8782 case 0x48:
8783 case 0x49:
8784 case 0x4a:
8785 case 0x4b:
8786 case 0x4c:
8787 case 0x4d:
8788 case 0x4e:
8789 case 0x4f:
8790 return rexes [pref - 0x40];
8791 case 0xf3:
8792 return "repz";
8793 case 0xf2:
8794 return "repnz";
8795 case 0xf0:
8796 return "lock";
8797 case 0x2e:
8798 return "cs";
8799 case 0x36:
8800 return "ss";
8801 case 0x3e:
8802 return "ds";
8803 case 0x26:
8804 return "es";
8805 case 0x64:
8806 return "fs";
8807 case 0x65:
8808 return "gs";
8809 case 0x66:
8810 return (sizeflag & DFLAG) ? "data16" : "data32";
8811 case 0x67:
8812 if (address_mode == mode_64bit)
8813 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8814 else
8815 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8816 case FWAIT_OPCODE:
8817 return "fwait";
8818 case REP_PREFIX:
8819 return "rep";
8820 case XACQUIRE_PREFIX:
8821 return "xacquire";
8822 case XRELEASE_PREFIX:
8823 return "xrelease";
8824 case BND_PREFIX:
8825 return "bnd";
8826 case NOTRACK_PREFIX:
8827 return "notrack";
8828 default:
8829 return NULL;
8830 }
8831 }
8832
8833 static char op_out[MAX_OPERANDS][100];
8834 static int op_ad, op_index[MAX_OPERANDS];
8835 static int two_source_ops;
8836 static bfd_vma op_address[MAX_OPERANDS];
8837 static bfd_vma op_riprel[MAX_OPERANDS];
8838 static bfd_vma start_pc;
8839
8840 /*
8841 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8842 * (see topic "Redundant prefixes" in the "Differences from 8086"
8843 * section of the "Virtual 8086 Mode" chapter.)
8844 * 'pc' should be the address of this instruction, it will
8845 * be used to print the target address if this is a relative jump or call
8846 * The function returns the length of this instruction in bytes.
8847 */
8848
8849 static char intel_syntax;
8850 static char intel_mnemonic = !SYSV386_COMPAT;
8851 static char open_char;
8852 static char close_char;
8853 static char separator_char;
8854 static char scale_char;
8855
8856 enum x86_64_isa
8857 {
8858 amd64 = 1,
8859 intel64
8860 };
8861
8862 static enum x86_64_isa isa64;
8863
8864 /* Here for backwards compatibility. When gdb stops using
8865 print_insn_i386_att and print_insn_i386_intel these functions can
8866 disappear, and print_insn_i386 be merged into print_insn. */
8867 int
8868 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
8869 {
8870 intel_syntax = 0;
8871
8872 return print_insn (pc, info);
8873 }
8874
8875 int
8876 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
8877 {
8878 intel_syntax = 1;
8879
8880 return print_insn (pc, info);
8881 }
8882
8883 int
8884 print_insn_i386 (bfd_vma pc, disassemble_info *info)
8885 {
8886 intel_syntax = -1;
8887
8888 return print_insn (pc, info);
8889 }
8890
8891 void
8892 print_i386_disassembler_options (FILE *stream)
8893 {
8894 fprintf (stream, _("\n\
8895 The following i386/x86-64 specific disassembler options are supported for use\n\
8896 with the -M switch (multiple options should be separated by commas):\n"));
8897
8898 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
8899 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
8900 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
8901 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
8902 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
8903 fprintf (stream, _(" att-mnemonic\n"
8904 " Display instruction in AT&T mnemonic\n"));
8905 fprintf (stream, _(" intel-mnemonic\n"
8906 " Display instruction in Intel mnemonic\n"));
8907 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
8908 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
8909 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
8910 fprintf (stream, _(" data32 Assume 32bit data size\n"));
8911 fprintf (stream, _(" data16 Assume 16bit data size\n"));
8912 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8913 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
8914 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
8915 }
8916
8917 /* Bad opcode. */
8918 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8919
8920 /* Get a pointer to struct dis386 with a valid name. */
8921
8922 static const struct dis386 *
8923 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
8924 {
8925 int vindex, vex_table_index;
8926
8927 if (dp->name != NULL)
8928 return dp;
8929
8930 switch (dp->op[0].bytemode)
8931 {
8932 case USE_REG_TABLE:
8933 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
8934 break;
8935
8936 case USE_MOD_TABLE:
8937 vindex = modrm.mod == 0x3 ? 1 : 0;
8938 dp = &mod_table[dp->op[1].bytemode][vindex];
8939 break;
8940
8941 case USE_RM_TABLE:
8942 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
8943 break;
8944
8945 case USE_PREFIX_TABLE:
8946 if (need_vex)
8947 {
8948 /* The prefix in VEX is implicit. */
8949 switch (vex.prefix)
8950 {
8951 case 0:
8952 vindex = 0;
8953 break;
8954 case REPE_PREFIX_OPCODE:
8955 vindex = 1;
8956 break;
8957 case DATA_PREFIX_OPCODE:
8958 vindex = 2;
8959 break;
8960 case REPNE_PREFIX_OPCODE:
8961 vindex = 3;
8962 break;
8963 default:
8964 abort ();
8965 break;
8966 }
8967 }
8968 else
8969 {
8970 int last_prefix = -1;
8971 int prefix = 0;
8972 vindex = 0;
8973 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8974 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8975 last one wins. */
8976 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8977 {
8978 if (last_repz_prefix > last_repnz_prefix)
8979 {
8980 vindex = 1;
8981 prefix = PREFIX_REPZ;
8982 last_prefix = last_repz_prefix;
8983 }
8984 else
8985 {
8986 vindex = 3;
8987 prefix = PREFIX_REPNZ;
8988 last_prefix = last_repnz_prefix;
8989 }
8990
8991 /* Check if prefix should be ignored. */
8992 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8993 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8994 & prefix) != 0
8995 && !prefix_table[dp->op[1].bytemode][vindex].name)
8996 vindex = 0;
8997 }
8998
8999 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9000 {
9001 vindex = 2;
9002 prefix = PREFIX_DATA;
9003 last_prefix = last_data_prefix;
9004 }
9005
9006 if (vindex != 0)
9007 {
9008 used_prefixes |= prefix;
9009 all_prefixes[last_prefix] = 0;
9010 }
9011 }
9012 dp = &prefix_table[dp->op[1].bytemode][vindex];
9013 break;
9014
9015 case USE_X86_64_TABLE:
9016 vindex = address_mode == mode_64bit ? 1 : 0;
9017 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9018 break;
9019
9020 case USE_3BYTE_TABLE:
9021 FETCH_DATA (info, codep + 2);
9022 vindex = *codep++;
9023 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9024 end_codep = codep;
9025 modrm.mod = (*codep >> 6) & 3;
9026 modrm.reg = (*codep >> 3) & 7;
9027 modrm.rm = *codep & 7;
9028 break;
9029
9030 case USE_VEX_LEN_TABLE:
9031 if (!need_vex)
9032 abort ();
9033
9034 switch (vex.length)
9035 {
9036 case 128:
9037 vindex = 0;
9038 break;
9039 case 512:
9040 /* This allows re-using in particular table entries where only
9041 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
9042 if (vex.evex)
9043 {
9044 case 256:
9045 vindex = 1;
9046 break;
9047 }
9048 /* Fall through. */
9049 default:
9050 abort ();
9051 break;
9052 }
9053
9054 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9055 break;
9056
9057 case USE_EVEX_LEN_TABLE:
9058 if (!vex.evex)
9059 abort ();
9060
9061 switch (vex.length)
9062 {
9063 case 128:
9064 vindex = 0;
9065 break;
9066 case 256:
9067 vindex = 1;
9068 break;
9069 case 512:
9070 vindex = 2;
9071 break;
9072 default:
9073 abort ();
9074 break;
9075 }
9076
9077 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9078 break;
9079
9080 case USE_XOP_8F_TABLE:
9081 FETCH_DATA (info, codep + 3);
9082 rex = ~(*codep >> 5) & 0x7;
9083
9084 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9085 switch ((*codep & 0x1f))
9086 {
9087 default:
9088 dp = &bad_opcode;
9089 return dp;
9090 case 0x8:
9091 vex_table_index = XOP_08;
9092 break;
9093 case 0x9:
9094 vex_table_index = XOP_09;
9095 break;
9096 case 0xa:
9097 vex_table_index = XOP_0A;
9098 break;
9099 }
9100 codep++;
9101 vex.w = *codep & 0x80;
9102 if (vex.w && address_mode == mode_64bit)
9103 rex |= REX_W;
9104
9105 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9106 if (address_mode != mode_64bit)
9107 {
9108 /* In 16/32-bit mode REX_B is silently ignored. */
9109 rex &= ~REX_B;
9110 }
9111
9112 vex.length = (*codep & 0x4) ? 256 : 128;
9113 switch ((*codep & 0x3))
9114 {
9115 case 0:
9116 break;
9117 case 1:
9118 vex.prefix = DATA_PREFIX_OPCODE;
9119 break;
9120 case 2:
9121 vex.prefix = REPE_PREFIX_OPCODE;
9122 break;
9123 case 3:
9124 vex.prefix = REPNE_PREFIX_OPCODE;
9125 break;
9126 }
9127 need_vex = 1;
9128 codep++;
9129 vindex = *codep++;
9130 dp = &xop_table[vex_table_index][vindex];
9131
9132 end_codep = codep;
9133 FETCH_DATA (info, codep + 1);
9134 modrm.mod = (*codep >> 6) & 3;
9135 modrm.reg = (*codep >> 3) & 7;
9136 modrm.rm = *codep & 7;
9137
9138 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9139 having to decode the bits for every otherwise valid encoding. */
9140 if (vex.prefix)
9141 return &bad_opcode;
9142 break;
9143
9144 case USE_VEX_C4_TABLE:
9145 /* VEX prefix. */
9146 FETCH_DATA (info, codep + 3);
9147 rex = ~(*codep >> 5) & 0x7;
9148 switch ((*codep & 0x1f))
9149 {
9150 default:
9151 dp = &bad_opcode;
9152 return dp;
9153 case 0x1:
9154 vex_table_index = VEX_0F;
9155 break;
9156 case 0x2:
9157 vex_table_index = VEX_0F38;
9158 break;
9159 case 0x3:
9160 vex_table_index = VEX_0F3A;
9161 break;
9162 }
9163 codep++;
9164 vex.w = *codep & 0x80;
9165 if (address_mode == mode_64bit)
9166 {
9167 if (vex.w)
9168 rex |= REX_W;
9169 }
9170 else
9171 {
9172 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9173 is ignored, other REX bits are 0 and the highest bit in
9174 VEX.vvvv is also ignored (but we mustn't clear it here). */
9175 rex = 0;
9176 }
9177 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9178 vex.length = (*codep & 0x4) ? 256 : 128;
9179 switch ((*codep & 0x3))
9180 {
9181 case 0:
9182 break;
9183 case 1:
9184 vex.prefix = DATA_PREFIX_OPCODE;
9185 break;
9186 case 2:
9187 vex.prefix = REPE_PREFIX_OPCODE;
9188 break;
9189 case 3:
9190 vex.prefix = REPNE_PREFIX_OPCODE;
9191 break;
9192 }
9193 need_vex = 1;
9194 codep++;
9195 vindex = *codep++;
9196 dp = &vex_table[vex_table_index][vindex];
9197 end_codep = codep;
9198 /* There is no MODRM byte for VEX0F 77. */
9199 if (vex_table_index != VEX_0F || vindex != 0x77)
9200 {
9201 FETCH_DATA (info, codep + 1);
9202 modrm.mod = (*codep >> 6) & 3;
9203 modrm.reg = (*codep >> 3) & 7;
9204 modrm.rm = *codep & 7;
9205 }
9206 break;
9207
9208 case USE_VEX_C5_TABLE:
9209 /* VEX prefix. */
9210 FETCH_DATA (info, codep + 2);
9211 rex = (*codep & 0x80) ? 0 : REX_R;
9212
9213 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9214 VEX.vvvv is 1. */
9215 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9216 vex.length = (*codep & 0x4) ? 256 : 128;
9217 switch ((*codep & 0x3))
9218 {
9219 case 0:
9220 break;
9221 case 1:
9222 vex.prefix = DATA_PREFIX_OPCODE;
9223 break;
9224 case 2:
9225 vex.prefix = REPE_PREFIX_OPCODE;
9226 break;
9227 case 3:
9228 vex.prefix = REPNE_PREFIX_OPCODE;
9229 break;
9230 }
9231 need_vex = 1;
9232 codep++;
9233 vindex = *codep++;
9234 dp = &vex_table[dp->op[1].bytemode][vindex];
9235 end_codep = codep;
9236 /* There is no MODRM byte for VEX 77. */
9237 if (vindex != 0x77)
9238 {
9239 FETCH_DATA (info, codep + 1);
9240 modrm.mod = (*codep >> 6) & 3;
9241 modrm.reg = (*codep >> 3) & 7;
9242 modrm.rm = *codep & 7;
9243 }
9244 break;
9245
9246 case USE_VEX_W_TABLE:
9247 if (!need_vex)
9248 abort ();
9249
9250 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9251 break;
9252
9253 case USE_EVEX_TABLE:
9254 two_source_ops = 0;
9255 /* EVEX prefix. */
9256 vex.evex = 1;
9257 FETCH_DATA (info, codep + 4);
9258 /* The first byte after 0x62. */
9259 rex = ~(*codep >> 5) & 0x7;
9260 vex.r = *codep & 0x10;
9261 switch ((*codep & 0xf))
9262 {
9263 default:
9264 return &bad_opcode;
9265 case 0x1:
9266 vex_table_index = EVEX_0F;
9267 break;
9268 case 0x2:
9269 vex_table_index = EVEX_0F38;
9270 break;
9271 case 0x3:
9272 vex_table_index = EVEX_0F3A;
9273 break;
9274 }
9275
9276 /* The second byte after 0x62. */
9277 codep++;
9278 vex.w = *codep & 0x80;
9279 if (vex.w && address_mode == mode_64bit)
9280 rex |= REX_W;
9281
9282 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9283
9284 /* The U bit. */
9285 if (!(*codep & 0x4))
9286 return &bad_opcode;
9287
9288 switch ((*codep & 0x3))
9289 {
9290 case 0:
9291 break;
9292 case 1:
9293 vex.prefix = DATA_PREFIX_OPCODE;
9294 break;
9295 case 2:
9296 vex.prefix = REPE_PREFIX_OPCODE;
9297 break;
9298 case 3:
9299 vex.prefix = REPNE_PREFIX_OPCODE;
9300 break;
9301 }
9302
9303 /* The third byte after 0x62. */
9304 codep++;
9305
9306 /* Remember the static rounding bits. */
9307 vex.ll = (*codep >> 5) & 3;
9308 vex.b = (*codep & 0x10) != 0;
9309
9310 vex.v = *codep & 0x8;
9311 vex.mask_register_specifier = *codep & 0x7;
9312 vex.zeroing = *codep & 0x80;
9313
9314 if (address_mode != mode_64bit)
9315 {
9316 /* In 16/32-bit mode silently ignore following bits. */
9317 rex &= ~REX_B;
9318 vex.r = 1;
9319 vex.v = 1;
9320 }
9321
9322 need_vex = 1;
9323 codep++;
9324 vindex = *codep++;
9325 dp = &evex_table[vex_table_index][vindex];
9326 end_codep = codep;
9327 FETCH_DATA (info, codep + 1);
9328 modrm.mod = (*codep >> 6) & 3;
9329 modrm.reg = (*codep >> 3) & 7;
9330 modrm.rm = *codep & 7;
9331
9332 /* Set vector length. */
9333 if (modrm.mod == 3 && vex.b)
9334 vex.length = 512;
9335 else
9336 {
9337 switch (vex.ll)
9338 {
9339 case 0x0:
9340 vex.length = 128;
9341 break;
9342 case 0x1:
9343 vex.length = 256;
9344 break;
9345 case 0x2:
9346 vex.length = 512;
9347 break;
9348 default:
9349 return &bad_opcode;
9350 }
9351 }
9352 break;
9353
9354 case 0:
9355 dp = &bad_opcode;
9356 break;
9357
9358 default:
9359 abort ();
9360 }
9361
9362 if (dp->name != NULL)
9363 return dp;
9364 else
9365 return get_valid_dis386 (dp, info);
9366 }
9367
9368 static void
9369 get_sib (disassemble_info *info, int sizeflag)
9370 {
9371 /* If modrm.mod == 3, operand must be register. */
9372 if (need_modrm
9373 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9374 && modrm.mod != 3
9375 && modrm.rm == 4)
9376 {
9377 FETCH_DATA (info, codep + 2);
9378 sib.index = (codep [1] >> 3) & 7;
9379 sib.scale = (codep [1] >> 6) & 3;
9380 sib.base = codep [1] & 7;
9381 }
9382 }
9383
9384 static int
9385 print_insn (bfd_vma pc, disassemble_info *info)
9386 {
9387 const struct dis386 *dp;
9388 int i;
9389 char *op_txt[MAX_OPERANDS];
9390 int needcomma;
9391 int sizeflag, orig_sizeflag;
9392 const char *p;
9393 struct dis_private priv;
9394 int prefix_length;
9395
9396 priv.orig_sizeflag = AFLAG | DFLAG;
9397 if ((info->mach & bfd_mach_i386_i386) != 0)
9398 address_mode = mode_32bit;
9399 else if (info->mach == bfd_mach_i386_i8086)
9400 {
9401 address_mode = mode_16bit;
9402 priv.orig_sizeflag = 0;
9403 }
9404 else
9405 address_mode = mode_64bit;
9406
9407 if (intel_syntax == (char) -1)
9408 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9409
9410 for (p = info->disassembler_options; p != NULL; )
9411 {
9412 if (startswith (p, "amd64"))
9413 isa64 = amd64;
9414 else if (startswith (p, "intel64"))
9415 isa64 = intel64;
9416 else if (startswith (p, "x86-64"))
9417 {
9418 address_mode = mode_64bit;
9419 priv.orig_sizeflag |= AFLAG | DFLAG;
9420 }
9421 else if (startswith (p, "i386"))
9422 {
9423 address_mode = mode_32bit;
9424 priv.orig_sizeflag |= AFLAG | DFLAG;
9425 }
9426 else if (startswith (p, "i8086"))
9427 {
9428 address_mode = mode_16bit;
9429 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9430 }
9431 else if (startswith (p, "intel"))
9432 {
9433 intel_syntax = 1;
9434 if (startswith (p + 5, "-mnemonic"))
9435 intel_mnemonic = 1;
9436 }
9437 else if (startswith (p, "att"))
9438 {
9439 intel_syntax = 0;
9440 if (startswith (p + 3, "-mnemonic"))
9441 intel_mnemonic = 0;
9442 }
9443 else if (startswith (p, "addr"))
9444 {
9445 if (address_mode == mode_64bit)
9446 {
9447 if (p[4] == '3' && p[5] == '2')
9448 priv.orig_sizeflag &= ~AFLAG;
9449 else if (p[4] == '6' && p[5] == '4')
9450 priv.orig_sizeflag |= AFLAG;
9451 }
9452 else
9453 {
9454 if (p[4] == '1' && p[5] == '6')
9455 priv.orig_sizeflag &= ~AFLAG;
9456 else if (p[4] == '3' && p[5] == '2')
9457 priv.orig_sizeflag |= AFLAG;
9458 }
9459 }
9460 else if (startswith (p, "data"))
9461 {
9462 if (p[4] == '1' && p[5] == '6')
9463 priv.orig_sizeflag &= ~DFLAG;
9464 else if (p[4] == '3' && p[5] == '2')
9465 priv.orig_sizeflag |= DFLAG;
9466 }
9467 else if (startswith (p, "suffix"))
9468 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9469
9470 p = strchr (p, ',');
9471 if (p != NULL)
9472 p++;
9473 }
9474
9475 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9476 {
9477 (*info->fprintf_func) (info->stream,
9478 _("64-bit address is disabled"));
9479 return -1;
9480 }
9481
9482 if (intel_syntax)
9483 {
9484 names64 = intel_names64;
9485 names32 = intel_names32;
9486 names16 = intel_names16;
9487 names8 = intel_names8;
9488 names8rex = intel_names8rex;
9489 names_seg = intel_names_seg;
9490 names_mm = intel_names_mm;
9491 names_bnd = intel_names_bnd;
9492 names_xmm = intel_names_xmm;
9493 names_ymm = intel_names_ymm;
9494 names_zmm = intel_names_zmm;
9495 names_tmm = intel_names_tmm;
9496 index64 = intel_index64;
9497 index32 = intel_index32;
9498 names_mask = intel_names_mask;
9499 index16 = intel_index16;
9500 open_char = '[';
9501 close_char = ']';
9502 separator_char = '+';
9503 scale_char = '*';
9504 }
9505 else
9506 {
9507 names64 = att_names64;
9508 names32 = att_names32;
9509 names16 = att_names16;
9510 names8 = att_names8;
9511 names8rex = att_names8rex;
9512 names_seg = att_names_seg;
9513 names_mm = att_names_mm;
9514 names_bnd = att_names_bnd;
9515 names_xmm = att_names_xmm;
9516 names_ymm = att_names_ymm;
9517 names_zmm = att_names_zmm;
9518 names_tmm = att_names_tmm;
9519 index64 = att_index64;
9520 index32 = att_index32;
9521 names_mask = att_names_mask;
9522 index16 = att_index16;
9523 open_char = '(';
9524 close_char = ')';
9525 separator_char = ',';
9526 scale_char = ',';
9527 }
9528
9529 /* The output looks better if we put 7 bytes on a line, since that
9530 puts most long word instructions on a single line. Use 8 bytes
9531 for Intel L1OM. */
9532 if ((info->mach & bfd_mach_l1om) != 0)
9533 info->bytes_per_line = 8;
9534 else
9535 info->bytes_per_line = 7;
9536
9537 info->private_data = &priv;
9538 priv.max_fetched = priv.the_buffer;
9539 priv.insn_start = pc;
9540
9541 obuf[0] = 0;
9542 for (i = 0; i < MAX_OPERANDS; ++i)
9543 {
9544 op_out[i][0] = 0;
9545 op_index[i] = -1;
9546 }
9547
9548 the_info = info;
9549 start_pc = pc;
9550 start_codep = priv.the_buffer;
9551 codep = priv.the_buffer;
9552
9553 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9554 {
9555 const char *name;
9556
9557 /* Getting here means we tried for data but didn't get it. That
9558 means we have an incomplete instruction of some sort. Just
9559 print the first byte as a prefix or a .byte pseudo-op. */
9560 if (codep > priv.the_buffer)
9561 {
9562 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9563 if (name != NULL)
9564 (*info->fprintf_func) (info->stream, "%s", name);
9565 else
9566 {
9567 /* Just print the first byte as a .byte instruction. */
9568 (*info->fprintf_func) (info->stream, ".byte 0x%x",
9569 (unsigned int) priv.the_buffer[0]);
9570 }
9571
9572 return 1;
9573 }
9574
9575 return -1;
9576 }
9577
9578 obufp = obuf;
9579 sizeflag = priv.orig_sizeflag;
9580
9581 if (!ckprefix () || rex_used)
9582 {
9583 /* Too many prefixes or unused REX prefixes. */
9584 for (i = 0;
9585 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9586 i++)
9587 (*info->fprintf_func) (info->stream, "%s%s",
9588 i == 0 ? "" : " ",
9589 prefix_name (all_prefixes[i], sizeflag));
9590 return i;
9591 }
9592
9593 insn_codep = codep;
9594
9595 FETCH_DATA (info, codep + 1);
9596 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9597
9598 if (((prefixes & PREFIX_FWAIT)
9599 && ((*codep < 0xd8) || (*codep > 0xdf))))
9600 {
9601 /* Handle prefixes before fwait. */
9602 for (i = 0; i < fwait_prefix && all_prefixes[i];
9603 i++)
9604 (*info->fprintf_func) (info->stream, "%s ",
9605 prefix_name (all_prefixes[i], sizeflag));
9606 (*info->fprintf_func) (info->stream, "fwait");
9607 return i + 1;
9608 }
9609
9610 if (*codep == 0x0f)
9611 {
9612 unsigned char threebyte;
9613
9614 codep++;
9615 FETCH_DATA (info, codep + 1);
9616 threebyte = *codep;
9617 dp = &dis386_twobyte[threebyte];
9618 need_modrm = twobyte_has_modrm[threebyte];
9619 codep++;
9620 }
9621 else
9622 {
9623 dp = &dis386[*codep];
9624 need_modrm = onebyte_has_modrm[*codep];
9625 codep++;
9626 }
9627
9628 /* Save sizeflag for printing the extra prefixes later before updating
9629 it for mnemonic and operand processing. The prefix names depend
9630 only on the address mode. */
9631 orig_sizeflag = sizeflag;
9632 if (prefixes & PREFIX_ADDR)
9633 sizeflag ^= AFLAG;
9634 if ((prefixes & PREFIX_DATA))
9635 sizeflag ^= DFLAG;
9636
9637 end_codep = codep;
9638 if (need_modrm)
9639 {
9640 FETCH_DATA (info, codep + 1);
9641 modrm.mod = (*codep >> 6) & 3;
9642 modrm.reg = (*codep >> 3) & 7;
9643 modrm.rm = *codep & 7;
9644 }
9645 else
9646 memset (&modrm, 0, sizeof (modrm));
9647
9648 need_vex = 0;
9649 memset (&vex, 0, sizeof (vex));
9650
9651 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9652 {
9653 get_sib (info, sizeflag);
9654 dofloat (sizeflag);
9655 }
9656 else
9657 {
9658 dp = get_valid_dis386 (dp, info);
9659 if (dp != NULL && putop (dp->name, sizeflag) == 0)
9660 {
9661 get_sib (info, sizeflag);
9662 for (i = 0; i < MAX_OPERANDS; ++i)
9663 {
9664 obufp = op_out[i];
9665 op_ad = MAX_OPERANDS - 1 - i;
9666 if (dp->op[i].rtn)
9667 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9668 /* For EVEX instruction after the last operand masking
9669 should be printed. */
9670 if (i == 0 && vex.evex)
9671 {
9672 /* Don't print {%k0}. */
9673 if (vex.mask_register_specifier)
9674 {
9675 oappend ("{");
9676 oappend (names_mask[vex.mask_register_specifier]);
9677 oappend ("}");
9678 }
9679 if (vex.zeroing)
9680 oappend ("{z}");
9681
9682 /* S/G insns require a mask and don't allow
9683 zeroing-masking. */
9684 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9685 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9686 && (vex.mask_register_specifier == 0 || vex.zeroing))
9687 oappend ("/(bad)");
9688 }
9689 }
9690 }
9691 }
9692
9693 /* Clear instruction information. */
9694 if (the_info)
9695 {
9696 the_info->insn_info_valid = 0;
9697 the_info->branch_delay_insns = 0;
9698 the_info->data_size = 0;
9699 the_info->insn_type = dis_noninsn;
9700 the_info->target = 0;
9701 the_info->target2 = 0;
9702 }
9703
9704 /* Reset jump operation indicator. */
9705 op_is_jump = false;
9706
9707 {
9708 int jump_detection = 0;
9709
9710 /* Extract flags. */
9711 for (i = 0; i < MAX_OPERANDS; ++i)
9712 {
9713 if ((dp->op[i].rtn == OP_J)
9714 || (dp->op[i].rtn == OP_indirE))
9715 jump_detection |= 1;
9716 else if ((dp->op[i].rtn == BND_Fixup)
9717 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9718 jump_detection |= 2;
9719 else if ((dp->op[i].bytemode == cond_jump_mode)
9720 || (dp->op[i].bytemode == loop_jcxz_mode))
9721 jump_detection |= 4;
9722 }
9723
9724 /* Determine if this is a jump or branch. */
9725 if ((jump_detection & 0x3) == 0x3)
9726 {
9727 op_is_jump = true;
9728 if (jump_detection & 0x4)
9729 the_info->insn_type = dis_condbranch;
9730 else
9731 the_info->insn_type =
9732 (dp->name && !strncmp(dp->name, "call", 4))
9733 ? dis_jsr : dis_branch;
9734 }
9735 }
9736
9737 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9738 are all 0s in inverted form. */
9739 if (need_vex && vex.register_specifier != 0)
9740 {
9741 (*info->fprintf_func) (info->stream, "(bad)");
9742 return end_codep - priv.the_buffer;
9743 }
9744
9745 /* If EVEX.z is set, there must be an actual mask register in use. */
9746 if (vex.zeroing && vex.mask_register_specifier == 0)
9747 {
9748 (*info->fprintf_func) (info->stream, "(bad)");
9749 return end_codep - priv.the_buffer;
9750 }
9751
9752 switch (dp->prefix_requirement)
9753 {
9754 case PREFIX_DATA:
9755 /* If only the data prefix is marked as mandatory, its absence renders
9756 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9757 if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9758 {
9759 (*info->fprintf_func) (info->stream, "(bad)");
9760 return end_codep - priv.the_buffer;
9761 }
9762 used_prefixes |= PREFIX_DATA;
9763 /* Fall through. */
9764 case PREFIX_OPCODE:
9765 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9766 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9767 used by putop and MMX/SSE operand and may be overridden by the
9768 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9769 separately. */
9770 if (((need_vex
9771 ? vex.prefix == REPE_PREFIX_OPCODE
9772 || vex.prefix == REPNE_PREFIX_OPCODE
9773 : (prefixes
9774 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9775 && (used_prefixes
9776 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9777 || (((need_vex
9778 ? vex.prefix == DATA_PREFIX_OPCODE
9779 : ((prefixes
9780 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9781 == PREFIX_DATA))
9782 && (used_prefixes & PREFIX_DATA) == 0))
9783 || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9784 && !vex.w != !(used_prefixes & PREFIX_DATA)))
9785 {
9786 (*info->fprintf_func) (info->stream, "(bad)");
9787 return end_codep - priv.the_buffer;
9788 }
9789 break;
9790
9791 case PREFIX_IGNORED:
9792 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9793 origins in all_prefixes. */
9794 used_prefixes &= ~PREFIX_OPCODE;
9795 if (last_data_prefix >= 0)
9796 all_prefixes[last_data_prefix] = 0x66;
9797 if (last_repz_prefix >= 0)
9798 all_prefixes[last_repz_prefix] = 0xf3;
9799 if (last_repnz_prefix >= 0)
9800 all_prefixes[last_repnz_prefix] = 0xf2;
9801 break;
9802 }
9803
9804 /* Check if the REX prefix is used. */
9805 if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9806 all_prefixes[last_rex_prefix] = 0;
9807
9808 /* Check if the SEG prefix is used. */
9809 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9810 | PREFIX_FS | PREFIX_GS)) != 0
9811 && (used_prefixes & active_seg_prefix) != 0)
9812 all_prefixes[last_seg_prefix] = 0;
9813
9814 /* Check if the ADDR prefix is used. */
9815 if ((prefixes & PREFIX_ADDR) != 0
9816 && (used_prefixes & PREFIX_ADDR) != 0)
9817 all_prefixes[last_addr_prefix] = 0;
9818
9819 /* Check if the DATA prefix is used. */
9820 if ((prefixes & PREFIX_DATA) != 0
9821 && (used_prefixes & PREFIX_DATA) != 0
9822 && !need_vex)
9823 all_prefixes[last_data_prefix] = 0;
9824
9825 /* Print the extra prefixes. */
9826 prefix_length = 0;
9827 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9828 if (all_prefixes[i])
9829 {
9830 const char *name;
9831 name = prefix_name (all_prefixes[i], orig_sizeflag);
9832 if (name == NULL)
9833 abort ();
9834 prefix_length += strlen (name) + 1;
9835 (*info->fprintf_func) (info->stream, "%s ", name);
9836 }
9837
9838 /* Check maximum code length. */
9839 if ((codep - start_codep) > MAX_CODE_LENGTH)
9840 {
9841 (*info->fprintf_func) (info->stream, "(bad)");
9842 return MAX_CODE_LENGTH;
9843 }
9844
9845 obufp = mnemonicendp;
9846 for (i = strlen (obuf) + prefix_length; i < 6; i++)
9847 oappend (" ");
9848 oappend (" ");
9849 (*info->fprintf_func) (info->stream, "%s", obuf);
9850
9851 /* The enter and bound instructions are printed with operands in the same
9852 order as the intel book; everything else is printed in reverse order. */
9853 if (intel_syntax || two_source_ops)
9854 {
9855 bfd_vma riprel;
9856
9857 for (i = 0; i < MAX_OPERANDS; ++i)
9858 op_txt[i] = op_out[i];
9859
9860 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9861 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9862 {
9863 op_txt[2] = op_out[3];
9864 op_txt[3] = op_out[2];
9865 }
9866
9867 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9868 {
9869 op_ad = op_index[i];
9870 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9871 op_index[MAX_OPERANDS - 1 - i] = op_ad;
9872 riprel = op_riprel[i];
9873 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9874 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9875 }
9876 }
9877 else
9878 {
9879 for (i = 0; i < MAX_OPERANDS; ++i)
9880 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9881 }
9882
9883 needcomma = 0;
9884 for (i = 0; i < MAX_OPERANDS; ++i)
9885 if (*op_txt[i])
9886 {
9887 if (needcomma)
9888 (*info->fprintf_func) (info->stream, ",");
9889 if (op_index[i] != -1 && !op_riprel[i])
9890 {
9891 bfd_vma target = (bfd_vma) op_address[op_index[i]];
9892
9893 if (the_info && op_is_jump)
9894 {
9895 the_info->insn_info_valid = 1;
9896 the_info->branch_delay_insns = 0;
9897 the_info->data_size = 0;
9898 the_info->target = target;
9899 the_info->target2 = 0;
9900 }
9901 (*info->print_address_func) (target, info);
9902 }
9903 else
9904 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9905 needcomma = 1;
9906 }
9907
9908 for (i = 0; i < MAX_OPERANDS; i++)
9909 if (op_index[i] != -1 && op_riprel[i])
9910 {
9911 (*info->fprintf_func) (info->stream, " # ");
9912 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
9913 + op_address[op_index[i]]), info);
9914 break;
9915 }
9916 return codep - priv.the_buffer;
9917 }
9918
9919 static const char *float_mem[] = {
9920 /* d8 */
9921 "fadd{s|}",
9922 "fmul{s|}",
9923 "fcom{s|}",
9924 "fcomp{s|}",
9925 "fsub{s|}",
9926 "fsubr{s|}",
9927 "fdiv{s|}",
9928 "fdivr{s|}",
9929 /* d9 */
9930 "fld{s|}",
9931 "(bad)",
9932 "fst{s|}",
9933 "fstp{s|}",
9934 "fldenv{C|C}",
9935 "fldcw",
9936 "fNstenv{C|C}",
9937 "fNstcw",
9938 /* da */
9939 "fiadd{l|}",
9940 "fimul{l|}",
9941 "ficom{l|}",
9942 "ficomp{l|}",
9943 "fisub{l|}",
9944 "fisubr{l|}",
9945 "fidiv{l|}",
9946 "fidivr{l|}",
9947 /* db */
9948 "fild{l|}",
9949 "fisttp{l|}",
9950 "fist{l|}",
9951 "fistp{l|}",
9952 "(bad)",
9953 "fld{t|}",
9954 "(bad)",
9955 "fstp{t|}",
9956 /* dc */
9957 "fadd{l|}",
9958 "fmul{l|}",
9959 "fcom{l|}",
9960 "fcomp{l|}",
9961 "fsub{l|}",
9962 "fsubr{l|}",
9963 "fdiv{l|}",
9964 "fdivr{l|}",
9965 /* dd */
9966 "fld{l|}",
9967 "fisttp{ll|}",
9968 "fst{l||}",
9969 "fstp{l|}",
9970 "frstor{C|C}",
9971 "(bad)",
9972 "fNsave{C|C}",
9973 "fNstsw",
9974 /* de */
9975 "fiadd{s|}",
9976 "fimul{s|}",
9977 "ficom{s|}",
9978 "ficomp{s|}",
9979 "fisub{s|}",
9980 "fisubr{s|}",
9981 "fidiv{s|}",
9982 "fidivr{s|}",
9983 /* df */
9984 "fild{s|}",
9985 "fisttp{s|}",
9986 "fist{s|}",
9987 "fistp{s|}",
9988 "fbld",
9989 "fild{ll|}",
9990 "fbstp",
9991 "fistp{ll|}",
9992 };
9993
9994 static const unsigned char float_mem_mode[] = {
9995 /* d8 */
9996 d_mode,
9997 d_mode,
9998 d_mode,
9999 d_mode,
10000 d_mode,
10001 d_mode,
10002 d_mode,
10003 d_mode,
10004 /* d9 */
10005 d_mode,
10006 0,
10007 d_mode,
10008 d_mode,
10009 0,
10010 w_mode,
10011 0,
10012 w_mode,
10013 /* da */
10014 d_mode,
10015 d_mode,
10016 d_mode,
10017 d_mode,
10018 d_mode,
10019 d_mode,
10020 d_mode,
10021 d_mode,
10022 /* db */
10023 d_mode,
10024 d_mode,
10025 d_mode,
10026 d_mode,
10027 0,
10028 t_mode,
10029 0,
10030 t_mode,
10031 /* dc */
10032 q_mode,
10033 q_mode,
10034 q_mode,
10035 q_mode,
10036 q_mode,
10037 q_mode,
10038 q_mode,
10039 q_mode,
10040 /* dd */
10041 q_mode,
10042 q_mode,
10043 q_mode,
10044 q_mode,
10045 0,
10046 0,
10047 0,
10048 w_mode,
10049 /* de */
10050 w_mode,
10051 w_mode,
10052 w_mode,
10053 w_mode,
10054 w_mode,
10055 w_mode,
10056 w_mode,
10057 w_mode,
10058 /* df */
10059 w_mode,
10060 w_mode,
10061 w_mode,
10062 w_mode,
10063 t_mode,
10064 q_mode,
10065 t_mode,
10066 q_mode
10067 };
10068
10069 #define ST { OP_ST, 0 }
10070 #define STi { OP_STi, 0 }
10071
10072 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10073 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10074 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10075 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10076 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10077 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10078 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10079 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10080 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10081
10082 static const struct dis386 float_reg[][8] = {
10083 /* d8 */
10084 {
10085 { "fadd", { ST, STi }, 0 },
10086 { "fmul", { ST, STi }, 0 },
10087 { "fcom", { STi }, 0 },
10088 { "fcomp", { STi }, 0 },
10089 { "fsub", { ST, STi }, 0 },
10090 { "fsubr", { ST, STi }, 0 },
10091 { "fdiv", { ST, STi }, 0 },
10092 { "fdivr", { ST, STi }, 0 },
10093 },
10094 /* d9 */
10095 {
10096 { "fld", { STi }, 0 },
10097 { "fxch", { STi }, 0 },
10098 { FGRPd9_2 },
10099 { Bad_Opcode },
10100 { FGRPd9_4 },
10101 { FGRPd9_5 },
10102 { FGRPd9_6 },
10103 { FGRPd9_7 },
10104 },
10105 /* da */
10106 {
10107 { "fcmovb", { ST, STi }, 0 },
10108 { "fcmove", { ST, STi }, 0 },
10109 { "fcmovbe",{ ST, STi }, 0 },
10110 { "fcmovu", { ST, STi }, 0 },
10111 { Bad_Opcode },
10112 { FGRPda_5 },
10113 { Bad_Opcode },
10114 { Bad_Opcode },
10115 },
10116 /* db */
10117 {
10118 { "fcmovnb",{ ST, STi }, 0 },
10119 { "fcmovne",{ ST, STi }, 0 },
10120 { "fcmovnbe",{ ST, STi }, 0 },
10121 { "fcmovnu",{ ST, STi }, 0 },
10122 { FGRPdb_4 },
10123 { "fucomi", { ST, STi }, 0 },
10124 { "fcomi", { ST, STi }, 0 },
10125 { Bad_Opcode },
10126 },
10127 /* dc */
10128 {
10129 { "fadd", { STi, ST }, 0 },
10130 { "fmul", { STi, ST }, 0 },
10131 { Bad_Opcode },
10132 { Bad_Opcode },
10133 { "fsub{!M|r}", { STi, ST }, 0 },
10134 { "fsub{M|}", { STi, ST }, 0 },
10135 { "fdiv{!M|r}", { STi, ST }, 0 },
10136 { "fdiv{M|}", { STi, ST }, 0 },
10137 },
10138 /* dd */
10139 {
10140 { "ffree", { STi }, 0 },
10141 { Bad_Opcode },
10142 { "fst", { STi }, 0 },
10143 { "fstp", { STi }, 0 },
10144 { "fucom", { STi }, 0 },
10145 { "fucomp", { STi }, 0 },
10146 { Bad_Opcode },
10147 { Bad_Opcode },
10148 },
10149 /* de */
10150 {
10151 { "faddp", { STi, ST }, 0 },
10152 { "fmulp", { STi, ST }, 0 },
10153 { Bad_Opcode },
10154 { FGRPde_3 },
10155 { "fsub{!M|r}p", { STi, ST }, 0 },
10156 { "fsub{M|}p", { STi, ST }, 0 },
10157 { "fdiv{!M|r}p", { STi, ST }, 0 },
10158 { "fdiv{M|}p", { STi, ST }, 0 },
10159 },
10160 /* df */
10161 {
10162 { "ffreep", { STi }, 0 },
10163 { Bad_Opcode },
10164 { Bad_Opcode },
10165 { Bad_Opcode },
10166 { FGRPdf_4 },
10167 { "fucomip", { ST, STi }, 0 },
10168 { "fcomip", { ST, STi }, 0 },
10169 { Bad_Opcode },
10170 },
10171 };
10172
10173 static char *fgrps[][8] = {
10174 /* Bad opcode 0 */
10175 {
10176 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10177 },
10178
10179 /* d9_2 1 */
10180 {
10181 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10182 },
10183
10184 /* d9_4 2 */
10185 {
10186 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10187 },
10188
10189 /* d9_5 3 */
10190 {
10191 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10192 },
10193
10194 /* d9_6 4 */
10195 {
10196 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10197 },
10198
10199 /* d9_7 5 */
10200 {
10201 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10202 },
10203
10204 /* da_5 6 */
10205 {
10206 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10207 },
10208
10209 /* db_4 7 */
10210 {
10211 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10212 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10213 },
10214
10215 /* de_3 8 */
10216 {
10217 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10218 },
10219
10220 /* df_4 9 */
10221 {
10222 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10223 },
10224 };
10225
10226 static void
10227 swap_operand (void)
10228 {
10229 mnemonicendp[0] = '.';
10230 mnemonicendp[1] = 's';
10231 mnemonicendp += 2;
10232 }
10233
10234 static void
10235 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10236 int sizeflag ATTRIBUTE_UNUSED)
10237 {
10238 /* Skip mod/rm byte. */
10239 MODRM_CHECK;
10240 codep++;
10241 }
10242
10243 static void
10244 dofloat (int sizeflag)
10245 {
10246 const struct dis386 *dp;
10247 unsigned char floatop;
10248
10249 floatop = codep[-1];
10250
10251 if (modrm.mod != 3)
10252 {
10253 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10254
10255 putop (float_mem[fp_indx], sizeflag);
10256 obufp = op_out[0];
10257 op_ad = 2;
10258 OP_E (float_mem_mode[fp_indx], sizeflag);
10259 return;
10260 }
10261 /* Skip mod/rm byte. */
10262 MODRM_CHECK;
10263 codep++;
10264
10265 dp = &float_reg[floatop - 0xd8][modrm.reg];
10266 if (dp->name == NULL)
10267 {
10268 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10269
10270 /* Instruction fnstsw is only one with strange arg. */
10271 if (floatop == 0xdf && codep[-1] == 0xe0)
10272 strcpy (op_out[0], names16[0]);
10273 }
10274 else
10275 {
10276 putop (dp->name, sizeflag);
10277
10278 obufp = op_out[0];
10279 op_ad = 2;
10280 if (dp->op[0].rtn)
10281 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10282
10283 obufp = op_out[1];
10284 op_ad = 1;
10285 if (dp->op[1].rtn)
10286 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10287 }
10288 }
10289
10290 /* Like oappend (below), but S is a string starting with '%'.
10291 In Intel syntax, the '%' is elided. */
10292 static void
10293 oappend_maybe_intel (const char *s)
10294 {
10295 oappend (s + intel_syntax);
10296 }
10297
10298 static void
10299 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10300 {
10301 oappend_maybe_intel ("%st");
10302 }
10303
10304 static void
10305 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10306 {
10307 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10308 oappend_maybe_intel (scratchbuf);
10309 }
10310
10311 /* Capital letters in template are macros. */
10312 static int
10313 putop (const char *in_template, int sizeflag)
10314 {
10315 const char *p;
10316 int alt = 0;
10317 int cond = 1;
10318 unsigned int l = 0, len = 0;
10319 char last[4];
10320
10321 for (p = in_template; *p; p++)
10322 {
10323 if (len > l)
10324 {
10325 if (l >= sizeof (last) || !ISUPPER (*p))
10326 abort ();
10327 last[l++] = *p;
10328 continue;
10329 }
10330 switch (*p)
10331 {
10332 default:
10333 *obufp++ = *p;
10334 break;
10335 case '%':
10336 len++;
10337 break;
10338 case '!':
10339 cond = 0;
10340 break;
10341 case '{':
10342 if (intel_syntax)
10343 {
10344 while (*++p != '|')
10345 if (*p == '}' || *p == '\0')
10346 abort ();
10347 alt = 1;
10348 }
10349 break;
10350 case '|':
10351 while (*++p != '}')
10352 {
10353 if (*p == '\0')
10354 abort ();
10355 }
10356 break;
10357 case '}':
10358 alt = 0;
10359 break;
10360 case 'A':
10361 if (intel_syntax)
10362 break;
10363 if ((need_modrm && modrm.mod != 3)
10364 || (sizeflag & SUFFIX_ALWAYS))
10365 *obufp++ = 'b';
10366 break;
10367 case 'B':
10368 if (l == 0)
10369 {
10370 case_B:
10371 if (intel_syntax)
10372 break;
10373 if (sizeflag & SUFFIX_ALWAYS)
10374 *obufp++ = 'b';
10375 }
10376 else if (l == 1 && last[0] == 'L')
10377 {
10378 if (address_mode == mode_64bit
10379 && !(prefixes & PREFIX_ADDR))
10380 {
10381 *obufp++ = 'a';
10382 *obufp++ = 'b';
10383 *obufp++ = 's';
10384 }
10385
10386 goto case_B;
10387 }
10388 else
10389 abort ();
10390 break;
10391 case 'C':
10392 if (intel_syntax && !alt)
10393 break;
10394 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10395 {
10396 if (sizeflag & DFLAG)
10397 *obufp++ = intel_syntax ? 'd' : 'l';
10398 else
10399 *obufp++ = intel_syntax ? 'w' : 's';
10400 used_prefixes |= (prefixes & PREFIX_DATA);
10401 }
10402 break;
10403 case 'D':
10404 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10405 break;
10406 USED_REX (REX_W);
10407 if (modrm.mod == 3)
10408 {
10409 if (rex & REX_W)
10410 *obufp++ = 'q';
10411 else
10412 {
10413 if (sizeflag & DFLAG)
10414 *obufp++ = intel_syntax ? 'd' : 'l';
10415 else
10416 *obufp++ = 'w';
10417 used_prefixes |= (prefixes & PREFIX_DATA);
10418 }
10419 }
10420 else
10421 *obufp++ = 'w';
10422 break;
10423 case 'E': /* For jcxz/jecxz */
10424 if (address_mode == mode_64bit)
10425 {
10426 if (sizeflag & AFLAG)
10427 *obufp++ = 'r';
10428 else
10429 *obufp++ = 'e';
10430 }
10431 else
10432 if (sizeflag & AFLAG)
10433 *obufp++ = 'e';
10434 used_prefixes |= (prefixes & PREFIX_ADDR);
10435 break;
10436 case 'F':
10437 if (intel_syntax)
10438 break;
10439 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10440 {
10441 if (sizeflag & AFLAG)
10442 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10443 else
10444 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10445 used_prefixes |= (prefixes & PREFIX_ADDR);
10446 }
10447 break;
10448 case 'G':
10449 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10450 break;
10451 if ((rex & REX_W) || (sizeflag & DFLAG))
10452 *obufp++ = 'l';
10453 else
10454 *obufp++ = 'w';
10455 if (!(rex & REX_W))
10456 used_prefixes |= (prefixes & PREFIX_DATA);
10457 break;
10458 case 'H':
10459 if (intel_syntax)
10460 break;
10461 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10462 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10463 {
10464 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10465 *obufp++ = ',';
10466 *obufp++ = 'p';
10467
10468 /* Set active_seg_prefix even if not set in 64-bit mode
10469 because here it is a valid branch hint. */
10470 if (prefixes & PREFIX_DS)
10471 {
10472 active_seg_prefix = PREFIX_DS;
10473 *obufp++ = 't';
10474 }
10475 else
10476 {
10477 active_seg_prefix = PREFIX_CS;
10478 *obufp++ = 'n';
10479 }
10480 }
10481 break;
10482 case 'K':
10483 USED_REX (REX_W);
10484 if (rex & REX_W)
10485 *obufp++ = 'q';
10486 else
10487 *obufp++ = 'd';
10488 break;
10489 case 'L':
10490 abort ();
10491 case 'M':
10492 if (intel_mnemonic != cond)
10493 *obufp++ = 'r';
10494 break;
10495 case 'N':
10496 if ((prefixes & PREFIX_FWAIT) == 0)
10497 *obufp++ = 'n';
10498 else
10499 used_prefixes |= PREFIX_FWAIT;
10500 break;
10501 case 'O':
10502 USED_REX (REX_W);
10503 if (rex & REX_W)
10504 *obufp++ = 'o';
10505 else if (intel_syntax && (sizeflag & DFLAG))
10506 *obufp++ = 'q';
10507 else
10508 *obufp++ = 'd';
10509 if (!(rex & REX_W))
10510 used_prefixes |= (prefixes & PREFIX_DATA);
10511 break;
10512 case '@':
10513 if (address_mode == mode_64bit
10514 && (isa64 == intel64 || (rex & REX_W)
10515 || !(prefixes & PREFIX_DATA)))
10516 {
10517 if (sizeflag & SUFFIX_ALWAYS)
10518 *obufp++ = 'q';
10519 break;
10520 }
10521 /* Fall through. */
10522 case 'P':
10523 if (l == 0)
10524 {
10525 if ((modrm.mod == 3 || !cond)
10526 && !(sizeflag & SUFFIX_ALWAYS))
10527 break;
10528 /* Fall through. */
10529 case 'T':
10530 if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10531 || ((sizeflag & SUFFIX_ALWAYS)
10532 && address_mode != mode_64bit))
10533 {
10534 *obufp++ = (sizeflag & DFLAG) ?
10535 intel_syntax ? 'd' : 'l' : 'w';
10536 used_prefixes |= (prefixes & PREFIX_DATA);
10537 }
10538 else if (sizeflag & SUFFIX_ALWAYS)
10539 *obufp++ = 'q';
10540 }
10541 else if (l == 1 && last[0] == 'L')
10542 {
10543 if ((prefixes & PREFIX_DATA)
10544 || (rex & REX_W)
10545 || (sizeflag & SUFFIX_ALWAYS))
10546 {
10547 USED_REX (REX_W);
10548 if (rex & REX_W)
10549 *obufp++ = 'q';
10550 else
10551 {
10552 if (sizeflag & DFLAG)
10553 *obufp++ = intel_syntax ? 'd' : 'l';
10554 else
10555 *obufp++ = 'w';
10556 used_prefixes |= (prefixes & PREFIX_DATA);
10557 }
10558 }
10559 }
10560 else
10561 abort ();
10562 break;
10563 case 'Q':
10564 if (l == 0)
10565 {
10566 if (intel_syntax && !alt)
10567 break;
10568 USED_REX (REX_W);
10569 if ((need_modrm && modrm.mod != 3)
10570 || (sizeflag & SUFFIX_ALWAYS))
10571 {
10572 if (rex & REX_W)
10573 *obufp++ = 'q';
10574 else
10575 {
10576 if (sizeflag & DFLAG)
10577 *obufp++ = intel_syntax ? 'd' : 'l';
10578 else
10579 *obufp++ = 'w';
10580 used_prefixes |= (prefixes & PREFIX_DATA);
10581 }
10582 }
10583 }
10584 else if (l == 1 && last[0] == 'D')
10585 *obufp++ = vex.w ? 'q' : 'd';
10586 else if (l == 1 && last[0] == 'L')
10587 {
10588 if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10589 : address_mode != mode_64bit)
10590 break;
10591 if ((rex & REX_W))
10592 {
10593 USED_REX (REX_W);
10594 *obufp++ = 'q';
10595 }
10596 else if((address_mode == mode_64bit && cond)
10597 || (sizeflag & SUFFIX_ALWAYS))
10598 *obufp++ = intel_syntax? 'd' : 'l';
10599 }
10600 else
10601 abort ();
10602 break;
10603 case 'R':
10604 USED_REX (REX_W);
10605 if (rex & REX_W)
10606 *obufp++ = 'q';
10607 else if (sizeflag & DFLAG)
10608 {
10609 if (intel_syntax)
10610 *obufp++ = 'd';
10611 else
10612 *obufp++ = 'l';
10613 }
10614 else
10615 *obufp++ = 'w';
10616 if (intel_syntax && !p[1]
10617 && ((rex & REX_W) || (sizeflag & DFLAG)))
10618 *obufp++ = 'e';
10619 if (!(rex & REX_W))
10620 used_prefixes |= (prefixes & PREFIX_DATA);
10621 break;
10622 case 'S':
10623 if (l == 0)
10624 {
10625 case_S:
10626 if (intel_syntax)
10627 break;
10628 if (sizeflag & SUFFIX_ALWAYS)
10629 {
10630 if (rex & REX_W)
10631 *obufp++ = 'q';
10632 else
10633 {
10634 if (sizeflag & DFLAG)
10635 *obufp++ = 'l';
10636 else
10637 *obufp++ = 'w';
10638 used_prefixes |= (prefixes & PREFIX_DATA);
10639 }
10640 }
10641 }
10642 else if (l == 1 && last[0] == 'L')
10643 {
10644 if (address_mode == mode_64bit
10645 && !(prefixes & PREFIX_ADDR))
10646 {
10647 *obufp++ = 'a';
10648 *obufp++ = 'b';
10649 *obufp++ = 's';
10650 }
10651
10652 goto case_S;
10653 }
10654 else
10655 abort ();
10656 break;
10657 case 'V':
10658 if (l == 0)
10659 abort ();
10660 else if (l == 1
10661 && (last[0] == 'L' || last[0] == 'X'))
10662 {
10663 if (last[0] == 'X')
10664 {
10665 *obufp++ = '{';
10666 *obufp++ = 'v';
10667 *obufp++ = 'e';
10668 *obufp++ = 'x';
10669 *obufp++ = '}';
10670 }
10671 else if (rex & REX_W)
10672 {
10673 *obufp++ = 'a';
10674 *obufp++ = 'b';
10675 *obufp++ = 's';
10676 }
10677 }
10678 else
10679 abort ();
10680 goto case_S;
10681 case 'W':
10682 if (l == 0)
10683 {
10684 /* operand size flag for cwtl, cbtw */
10685 USED_REX (REX_W);
10686 if (rex & REX_W)
10687 {
10688 if (intel_syntax)
10689 *obufp++ = 'd';
10690 else
10691 *obufp++ = 'l';
10692 }
10693 else if (sizeflag & DFLAG)
10694 *obufp++ = 'w';
10695 else
10696 *obufp++ = 'b';
10697 if (!(rex & REX_W))
10698 used_prefixes |= (prefixes & PREFIX_DATA);
10699 }
10700 else if (l == 1)
10701 {
10702 if (!need_vex)
10703 abort ();
10704 if (last[0] == 'X')
10705 *obufp++ = vex.w ? 'd': 's';
10706 else if (last[0] == 'B')
10707 *obufp++ = vex.w ? 'w': 'b';
10708 else
10709 abort ();
10710 }
10711 else
10712 abort ();
10713 break;
10714 case 'X':
10715 if (l != 0)
10716 abort ();
10717 if (need_vex
10718 ? vex.prefix == DATA_PREFIX_OPCODE
10719 : prefixes & PREFIX_DATA)
10720 {
10721 *obufp++ = 'd';
10722 used_prefixes |= PREFIX_DATA;
10723 }
10724 else
10725 *obufp++ = 's';
10726 break;
10727 case 'Y':
10728 if (l == 1 && last[0] == 'X')
10729 {
10730 if (!need_vex)
10731 abort ();
10732 if (intel_syntax
10733 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10734 break;
10735 switch (vex.length)
10736 {
10737 case 128:
10738 *obufp++ = 'x';
10739 break;
10740 case 256:
10741 *obufp++ = 'y';
10742 break;
10743 case 512:
10744 if (!vex.evex)
10745 default:
10746 abort ();
10747 }
10748 }
10749 else
10750 abort ();
10751 break;
10752 case 'Z':
10753 if (l == 0)
10754 {
10755 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10756 modrm.mod = 3;
10757 if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10758 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10759 }
10760 else if (l == 1 && last[0] == 'X')
10761 {
10762 if (!vex.evex)
10763 abort ();
10764 if (intel_syntax
10765 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10766 break;
10767 switch (vex.length)
10768 {
10769 case 128:
10770 *obufp++ = 'x';
10771 break;
10772 case 256:
10773 *obufp++ = 'y';
10774 break;
10775 case 512:
10776 *obufp++ = 'z';
10777 break;
10778 default:
10779 abort ();
10780 }
10781 }
10782 else
10783 abort ();
10784 break;
10785 case '^':
10786 if (intel_syntax)
10787 break;
10788 if (isa64 == intel64 && (rex & REX_W))
10789 {
10790 USED_REX (REX_W);
10791 *obufp++ = 'q';
10792 break;
10793 }
10794 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10795 {
10796 if (sizeflag & DFLAG)
10797 *obufp++ = 'l';
10798 else
10799 *obufp++ = 'w';
10800 used_prefixes |= (prefixes & PREFIX_DATA);
10801 }
10802 break;
10803 }
10804
10805 if (len == l)
10806 len = l = 0;
10807 }
10808 *obufp = 0;
10809 mnemonicendp = obufp;
10810 return 0;
10811 }
10812
10813 static void
10814 oappend (const char *s)
10815 {
10816 obufp = stpcpy (obufp, s);
10817 }
10818
10819 static void
10820 append_seg (void)
10821 {
10822 /* Only print the active segment register. */
10823 if (!active_seg_prefix)
10824 return;
10825
10826 used_prefixes |= active_seg_prefix;
10827 switch (active_seg_prefix)
10828 {
10829 case PREFIX_CS:
10830 oappend_maybe_intel ("%cs:");
10831 break;
10832 case PREFIX_DS:
10833 oappend_maybe_intel ("%ds:");
10834 break;
10835 case PREFIX_SS:
10836 oappend_maybe_intel ("%ss:");
10837 break;
10838 case PREFIX_ES:
10839 oappend_maybe_intel ("%es:");
10840 break;
10841 case PREFIX_FS:
10842 oappend_maybe_intel ("%fs:");
10843 break;
10844 case PREFIX_GS:
10845 oappend_maybe_intel ("%gs:");
10846 break;
10847 default:
10848 break;
10849 }
10850 }
10851
10852 static void
10853 OP_indirE (int bytemode, int sizeflag)
10854 {
10855 if (!intel_syntax)
10856 oappend ("*");
10857 OP_E (bytemode, sizeflag);
10858 }
10859
10860 static void
10861 print_operand_value (char *buf, int hex, bfd_vma disp)
10862 {
10863 if (address_mode == mode_64bit)
10864 {
10865 if (hex)
10866 {
10867 char tmp[30];
10868 int i;
10869 buf[0] = '0';
10870 buf[1] = 'x';
10871 sprintf_vma (tmp, disp);
10872 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10873 strcpy (buf + 2, tmp + i);
10874 }
10875 else
10876 {
10877 bfd_signed_vma v = disp;
10878 char tmp[30];
10879 int i;
10880 if (v < 0)
10881 {
10882 *(buf++) = '-';
10883 v = -disp;
10884 /* Check for possible overflow on 0x8000000000000000. */
10885 if (v < 0)
10886 {
10887 strcpy (buf, "9223372036854775808");
10888 return;
10889 }
10890 }
10891 if (!v)
10892 {
10893 strcpy (buf, "0");
10894 return;
10895 }
10896
10897 i = 0;
10898 tmp[29] = 0;
10899 while (v)
10900 {
10901 tmp[28 - i] = (v % 10) + '0';
10902 v /= 10;
10903 i++;
10904 }
10905 strcpy (buf, tmp + 29 - i);
10906 }
10907 }
10908 else
10909 {
10910 if (hex)
10911 sprintf (buf, "0x%x", (unsigned int) disp);
10912 else
10913 sprintf (buf, "%d", (int) disp);
10914 }
10915 }
10916
10917 /* Put DISP in BUF as signed hex number. */
10918
10919 static void
10920 print_displacement (char *buf, bfd_vma disp)
10921 {
10922 bfd_signed_vma val = disp;
10923 char tmp[30];
10924 int i, j = 0;
10925
10926 if (val < 0)
10927 {
10928 buf[j++] = '-';
10929 val = -disp;
10930
10931 /* Check for possible overflow. */
10932 if (val < 0)
10933 {
10934 switch (address_mode)
10935 {
10936 case mode_64bit:
10937 strcpy (buf + j, "0x8000000000000000");
10938 break;
10939 case mode_32bit:
10940 strcpy (buf + j, "0x80000000");
10941 break;
10942 case mode_16bit:
10943 strcpy (buf + j, "0x8000");
10944 break;
10945 }
10946 return;
10947 }
10948 }
10949
10950 buf[j++] = '0';
10951 buf[j++] = 'x';
10952
10953 sprintf_vma (tmp, (bfd_vma) val);
10954 for (i = 0; tmp[i] == '0'; i++)
10955 continue;
10956 if (tmp[i] == '\0')
10957 i--;
10958 strcpy (buf + j, tmp + i);
10959 }
10960
10961 static void
10962 intel_operand_size (int bytemode, int sizeflag)
10963 {
10964 if (vex.b
10965 && (bytemode == x_mode
10966 || bytemode == evex_half_bcst_xmmq_mode))
10967 {
10968 if (vex.w)
10969 oappend ("QWORD PTR ");
10970 else
10971 oappend ("DWORD PTR ");
10972 return;
10973 }
10974 switch (bytemode)
10975 {
10976 case b_mode:
10977 case b_swap_mode:
10978 case dqb_mode:
10979 case db_mode:
10980 oappend ("BYTE PTR ");
10981 break;
10982 case w_mode:
10983 case dw_mode:
10984 case dqw_mode:
10985 oappend ("WORD PTR ");
10986 break;
10987 case indir_v_mode:
10988 if (address_mode == mode_64bit && isa64 == intel64)
10989 {
10990 oappend ("QWORD PTR ");
10991 break;
10992 }
10993 /* Fall through. */
10994 case stack_v_mode:
10995 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
10996 {
10997 oappend ("QWORD PTR ");
10998 break;
10999 }
11000 /* Fall through. */
11001 case v_mode:
11002 case v_swap_mode:
11003 case dq_mode:
11004 USED_REX (REX_W);
11005 if (rex & REX_W)
11006 oappend ("QWORD PTR ");
11007 else if (bytemode == dq_mode)
11008 oappend ("DWORD PTR ");
11009 else
11010 {
11011 if (sizeflag & DFLAG)
11012 oappend ("DWORD PTR ");
11013 else
11014 oappend ("WORD PTR ");
11015 used_prefixes |= (prefixes & PREFIX_DATA);
11016 }
11017 break;
11018 case z_mode:
11019 if ((rex & REX_W) || (sizeflag & DFLAG))
11020 *obufp++ = 'D';
11021 oappend ("WORD PTR ");
11022 if (!(rex & REX_W))
11023 used_prefixes |= (prefixes & PREFIX_DATA);
11024 break;
11025 case a_mode:
11026 if (sizeflag & DFLAG)
11027 oappend ("QWORD PTR ");
11028 else
11029 oappend ("DWORD PTR ");
11030 used_prefixes |= (prefixes & PREFIX_DATA);
11031 break;
11032 case movsxd_mode:
11033 if (!(sizeflag & DFLAG) && isa64 == intel64)
11034 oappend ("WORD PTR ");
11035 else
11036 oappend ("DWORD PTR ");
11037 used_prefixes |= (prefixes & PREFIX_DATA);
11038 break;
11039 case d_mode:
11040 case d_swap_mode:
11041 case dqd_mode:
11042 oappend ("DWORD PTR ");
11043 break;
11044 case q_mode:
11045 case q_swap_mode:
11046 oappend ("QWORD PTR ");
11047 break;
11048 case m_mode:
11049 if (address_mode == mode_64bit)
11050 oappend ("QWORD PTR ");
11051 else
11052 oappend ("DWORD PTR ");
11053 break;
11054 case f_mode:
11055 if (sizeflag & DFLAG)
11056 oappend ("FWORD PTR ");
11057 else
11058 oappend ("DWORD PTR ");
11059 used_prefixes |= (prefixes & PREFIX_DATA);
11060 break;
11061 case t_mode:
11062 oappend ("TBYTE PTR ");
11063 break;
11064 case x_mode:
11065 case x_swap_mode:
11066 case evex_x_gscat_mode:
11067 case evex_x_nobcst_mode:
11068 case bw_unit_mode:
11069 if (need_vex)
11070 {
11071 switch (vex.length)
11072 {
11073 case 128:
11074 oappend ("XMMWORD PTR ");
11075 break;
11076 case 256:
11077 oappend ("YMMWORD PTR ");
11078 break;
11079 case 512:
11080 oappend ("ZMMWORD PTR ");
11081 break;
11082 default:
11083 abort ();
11084 }
11085 }
11086 else
11087 oappend ("XMMWORD PTR ");
11088 break;
11089 case xmm_mode:
11090 oappend ("XMMWORD PTR ");
11091 break;
11092 case ymm_mode:
11093 oappend ("YMMWORD PTR ");
11094 break;
11095 case xmmq_mode:
11096 case evex_half_bcst_xmmq_mode:
11097 if (!need_vex)
11098 abort ();
11099
11100 switch (vex.length)
11101 {
11102 case 128:
11103 oappend ("QWORD PTR ");
11104 break;
11105 case 256:
11106 oappend ("XMMWORD PTR ");
11107 break;
11108 case 512:
11109 oappend ("YMMWORD PTR ");
11110 break;
11111 default:
11112 abort ();
11113 }
11114 break;
11115 case xmm_mb_mode:
11116 if (!need_vex)
11117 abort ();
11118
11119 switch (vex.length)
11120 {
11121 case 128:
11122 case 256:
11123 case 512:
11124 oappend ("BYTE PTR ");
11125 break;
11126 default:
11127 abort ();
11128 }
11129 break;
11130 case xmm_mw_mode:
11131 if (!need_vex)
11132 abort ();
11133
11134 switch (vex.length)
11135 {
11136 case 128:
11137 case 256:
11138 case 512:
11139 oappend ("WORD PTR ");
11140 break;
11141 default:
11142 abort ();
11143 }
11144 break;
11145 case xmm_md_mode:
11146 if (!need_vex)
11147 abort ();
11148
11149 switch (vex.length)
11150 {
11151 case 128:
11152 case 256:
11153 case 512:
11154 oappend ("DWORD PTR ");
11155 break;
11156 default:
11157 abort ();
11158 }
11159 break;
11160 case xmm_mq_mode:
11161 if (!need_vex)
11162 abort ();
11163
11164 switch (vex.length)
11165 {
11166 case 128:
11167 case 256:
11168 case 512:
11169 oappend ("QWORD PTR ");
11170 break;
11171 default:
11172 abort ();
11173 }
11174 break;
11175 case xmmdw_mode:
11176 if (!need_vex)
11177 abort ();
11178
11179 switch (vex.length)
11180 {
11181 case 128:
11182 oappend ("WORD PTR ");
11183 break;
11184 case 256:
11185 oappend ("DWORD PTR ");
11186 break;
11187 case 512:
11188 oappend ("QWORD PTR ");
11189 break;
11190 default:
11191 abort ();
11192 }
11193 break;
11194 case xmmqd_mode:
11195 if (!need_vex)
11196 abort ();
11197
11198 switch (vex.length)
11199 {
11200 case 128:
11201 oappend ("DWORD PTR ");
11202 break;
11203 case 256:
11204 oappend ("QWORD PTR ");
11205 break;
11206 case 512:
11207 oappend ("XMMWORD PTR ");
11208 break;
11209 default:
11210 abort ();
11211 }
11212 break;
11213 case ymmq_mode:
11214 if (!need_vex)
11215 abort ();
11216
11217 switch (vex.length)
11218 {
11219 case 128:
11220 oappend ("QWORD PTR ");
11221 break;
11222 case 256:
11223 oappend ("YMMWORD PTR ");
11224 break;
11225 case 512:
11226 oappend ("ZMMWORD PTR ");
11227 break;
11228 default:
11229 abort ();
11230 }
11231 break;
11232 case ymmxmm_mode:
11233 if (!need_vex)
11234 abort ();
11235
11236 switch (vex.length)
11237 {
11238 case 128:
11239 case 256:
11240 oappend ("XMMWORD PTR ");
11241 break;
11242 default:
11243 abort ();
11244 }
11245 break;
11246 case o_mode:
11247 oappend ("OWORD PTR ");
11248 break;
11249 case vex_scalar_w_dq_mode:
11250 if (!need_vex)
11251 abort ();
11252
11253 if (vex.w)
11254 oappend ("QWORD PTR ");
11255 else
11256 oappend ("DWORD PTR ");
11257 break;
11258 case vex_vsib_d_w_dq_mode:
11259 case vex_vsib_q_w_dq_mode:
11260 if (!need_vex)
11261 abort ();
11262
11263 if (vex.w)
11264 oappend ("QWORD PTR ");
11265 else
11266 oappend ("DWORD PTR ");
11267 break;
11268 case mask_bd_mode:
11269 if (!need_vex || vex.length != 128)
11270 abort ();
11271 if (vex.w)
11272 oappend ("DWORD PTR ");
11273 else
11274 oappend ("BYTE PTR ");
11275 break;
11276 case mask_mode:
11277 if (!need_vex)
11278 abort ();
11279 if (vex.w)
11280 oappend ("QWORD PTR ");
11281 else
11282 oappend ("WORD PTR ");
11283 break;
11284 case v_bnd_mode:
11285 case v_bndmk_mode:
11286 default:
11287 break;
11288 }
11289 }
11290
11291 static void
11292 print_register (unsigned int reg, unsigned int rexmask, int bytemode, int sizeflag)
11293 {
11294 const char **names;
11295
11296 USED_REX (rexmask);
11297 if (rex & rexmask)
11298 reg += 8;
11299
11300 switch (bytemode)
11301 {
11302 case b_mode:
11303 case b_swap_mode:
11304 if (reg & 4)
11305 USED_REX (0);
11306 if (rex)
11307 names = names8rex;
11308 else
11309 names = names8;
11310 break;
11311 case w_mode:
11312 names = names16;
11313 break;
11314 case d_mode:
11315 case dw_mode:
11316 case db_mode:
11317 names = names32;
11318 break;
11319 case q_mode:
11320 names = names64;
11321 break;
11322 case m_mode:
11323 case v_bnd_mode:
11324 names = address_mode == mode_64bit ? names64 : names32;
11325 break;
11326 case bnd_mode:
11327 case bnd_swap_mode:
11328 if (reg > 0x3)
11329 {
11330 oappend ("(bad)");
11331 return;
11332 }
11333 names = names_bnd;
11334 break;
11335 case indir_v_mode:
11336 if (address_mode == mode_64bit && isa64 == intel64)
11337 {
11338 names = names64;
11339 break;
11340 }
11341 /* Fall through. */
11342 case stack_v_mode:
11343 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11344 {
11345 names = names64;
11346 break;
11347 }
11348 bytemode = v_mode;
11349 /* Fall through. */
11350 case v_mode:
11351 case v_swap_mode:
11352 case dq_mode:
11353 case dqb_mode:
11354 case dqd_mode:
11355 case dqw_mode:
11356 USED_REX (REX_W);
11357 if (rex & REX_W)
11358 names = names64;
11359 else if (bytemode != v_mode && bytemode != v_swap_mode)
11360 names = names32;
11361 else
11362 {
11363 if (sizeflag & DFLAG)
11364 names = names32;
11365 else
11366 names = names16;
11367 used_prefixes |= (prefixes & PREFIX_DATA);
11368 }
11369 break;
11370 case movsxd_mode:
11371 if (!(sizeflag & DFLAG) && isa64 == intel64)
11372 names = names16;
11373 else
11374 names = names32;
11375 used_prefixes |= (prefixes & PREFIX_DATA);
11376 break;
11377 case va_mode:
11378 names = (address_mode == mode_64bit
11379 ? names64 : names32);
11380 if (!(prefixes & PREFIX_ADDR))
11381 names = (address_mode == mode_16bit
11382 ? names16 : names);
11383 else
11384 {
11385 /* Remove "addr16/addr32". */
11386 all_prefixes[last_addr_prefix] = 0;
11387 names = (address_mode != mode_32bit
11388 ? names32 : names16);
11389 used_prefixes |= PREFIX_ADDR;
11390 }
11391 break;
11392 case mask_bd_mode:
11393 case mask_mode:
11394 if (reg > 0x7)
11395 {
11396 oappend ("(bad)");
11397 return;
11398 }
11399 names = names_mask;
11400 break;
11401 case 0:
11402 return;
11403 default:
11404 oappend (INTERNAL_DISASSEMBLER_ERROR);
11405 return;
11406 }
11407 oappend (names[reg]);
11408 }
11409
11410 static void
11411 OP_E_memory (int bytemode, int sizeflag)
11412 {
11413 bfd_vma disp = 0;
11414 int add = (rex & REX_B) ? 8 : 0;
11415 int riprel = 0;
11416 int shift;
11417
11418 if (vex.evex)
11419 {
11420 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11421 if (vex.b
11422 && bytemode != x_mode
11423 && bytemode != evex_half_bcst_xmmq_mode)
11424 {
11425 BadOp ();
11426 return;
11427 }
11428 switch (bytemode)
11429 {
11430 case dqw_mode:
11431 case dw_mode:
11432 case xmm_mw_mode:
11433 shift = 1;
11434 break;
11435 case dqb_mode:
11436 case db_mode:
11437 case xmm_mb_mode:
11438 shift = 0;
11439 break;
11440 case dq_mode:
11441 if (address_mode != mode_64bit)
11442 {
11443 case dqd_mode:
11444 case xmm_md_mode:
11445 case d_mode:
11446 case d_swap_mode:
11447 shift = 2;
11448 break;
11449 }
11450 /* fall through */
11451 case vex_scalar_w_dq_mode:
11452 case vex_vsib_d_w_dq_mode:
11453 case vex_vsib_q_w_dq_mode:
11454 case evex_x_gscat_mode:
11455 shift = vex.w ? 3 : 2;
11456 break;
11457 case x_mode:
11458 case evex_half_bcst_xmmq_mode:
11459 if (vex.b)
11460 {
11461 shift = vex.w ? 3 : 2;
11462 break;
11463 }
11464 /* Fall through. */
11465 case xmmqd_mode:
11466 case xmmdw_mode:
11467 case xmmq_mode:
11468 case ymmq_mode:
11469 case evex_x_nobcst_mode:
11470 case x_swap_mode:
11471 switch (vex.length)
11472 {
11473 case 128:
11474 shift = 4;
11475 break;
11476 case 256:
11477 shift = 5;
11478 break;
11479 case 512:
11480 shift = 6;
11481 break;
11482 default:
11483 abort ();
11484 }
11485 /* Make necessary corrections to shift for modes that need it. */
11486 if (bytemode == xmmq_mode
11487 || bytemode == evex_half_bcst_xmmq_mode
11488 || (bytemode == ymmq_mode && vex.length == 128))
11489 shift -= 1;
11490 else if (bytemode == xmmqd_mode)
11491 shift -= 2;
11492 else if (bytemode == xmmdw_mode)
11493 shift -= 3;
11494 break;
11495 case ymm_mode:
11496 shift = 5;
11497 break;
11498 case xmm_mode:
11499 shift = 4;
11500 break;
11501 case xmm_mq_mode:
11502 case q_mode:
11503 case q_swap_mode:
11504 shift = 3;
11505 break;
11506 case bw_unit_mode:
11507 shift = vex.w ? 1 : 0;
11508 break;
11509 default:
11510 abort ();
11511 }
11512 }
11513 else
11514 shift = 0;
11515
11516 USED_REX (REX_B);
11517 if (intel_syntax)
11518 intel_operand_size (bytemode, sizeflag);
11519 append_seg ();
11520
11521 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11522 {
11523 /* 32/64 bit address mode */
11524 int havedisp;
11525 int havesib;
11526 int havebase;
11527 int haveindex;
11528 int needindex;
11529 int needaddr32;
11530 int base, rbase;
11531 int vindex = 0;
11532 int scale = 0;
11533 int addr32flag = !((sizeflag & AFLAG)
11534 || bytemode == v_bnd_mode
11535 || bytemode == v_bndmk_mode
11536 || bytemode == bnd_mode
11537 || bytemode == bnd_swap_mode);
11538 bool check_gather = false;
11539 const char **indexes64 = names64;
11540 const char **indexes32 = names32;
11541
11542 havesib = 0;
11543 havebase = 1;
11544 haveindex = 0;
11545 base = modrm.rm;
11546
11547 if (base == 4)
11548 {
11549 havesib = 1;
11550 vindex = sib.index;
11551 USED_REX (REX_X);
11552 if (rex & REX_X)
11553 vindex += 8;
11554 switch (bytemode)
11555 {
11556 case vex_vsib_d_w_dq_mode:
11557 case vex_vsib_q_w_dq_mode:
11558 if (!need_vex)
11559 abort ();
11560 if (vex.evex)
11561 {
11562 if (!vex.v)
11563 vindex += 16;
11564 check_gather = obufp == op_out[1];
11565 }
11566
11567 haveindex = 1;
11568 switch (vex.length)
11569 {
11570 case 128:
11571 indexes64 = indexes32 = names_xmm;
11572 break;
11573 case 256:
11574 if (!vex.w
11575 || bytemode == vex_vsib_q_w_dq_mode)
11576 indexes64 = indexes32 = names_ymm;
11577 else
11578 indexes64 = indexes32 = names_xmm;
11579 break;
11580 case 512:
11581 if (!vex.w
11582 || bytemode == vex_vsib_q_w_dq_mode)
11583 indexes64 = indexes32 = names_zmm;
11584 else
11585 indexes64 = indexes32 = names_ymm;
11586 break;
11587 default:
11588 abort ();
11589 }
11590 break;
11591 default:
11592 haveindex = vindex != 4;
11593 break;
11594 }
11595 scale = sib.scale;
11596 base = sib.base;
11597 codep++;
11598 }
11599 else
11600 {
11601 /* Check for mandatory SIB. */
11602 if (bytemode == vex_vsib_d_w_dq_mode
11603 || bytemode == vex_vsib_q_w_dq_mode
11604 || bytemode == vex_sibmem_mode)
11605 {
11606 oappend ("(bad)");
11607 return;
11608 }
11609 }
11610 rbase = base + add;
11611
11612 switch (modrm.mod)
11613 {
11614 case 0:
11615 if (base == 5)
11616 {
11617 havebase = 0;
11618 if (address_mode == mode_64bit && !havesib)
11619 riprel = 1;
11620 disp = get32s ();
11621 if (riprel && bytemode == v_bndmk_mode)
11622 {
11623 oappend ("(bad)");
11624 return;
11625 }
11626 }
11627 break;
11628 case 1:
11629 FETCH_DATA (the_info, codep + 1);
11630 disp = *codep++;
11631 if ((disp & 0x80) != 0)
11632 disp -= 0x100;
11633 if (vex.evex && shift > 0)
11634 disp <<= shift;
11635 break;
11636 case 2:
11637 disp = get32s ();
11638 break;
11639 }
11640
11641 needindex = 0;
11642 needaddr32 = 0;
11643 if (havesib
11644 && !havebase
11645 && !haveindex
11646 && address_mode != mode_16bit)
11647 {
11648 if (address_mode == mode_64bit)
11649 {
11650 if (addr32flag)
11651 {
11652 /* Without base nor index registers, zero-extend the
11653 lower 32-bit displacement to 64 bits. */
11654 disp = (unsigned int) disp;
11655 needindex = 1;
11656 }
11657 needaddr32 = 1;
11658 }
11659 else
11660 {
11661 /* In 32-bit mode, we need index register to tell [offset]
11662 from [eiz*1 + offset]. */
11663 needindex = 1;
11664 }
11665 }
11666
11667 havedisp = (havebase
11668 || needindex
11669 || (havesib && (haveindex || scale != 0)));
11670
11671 if (!intel_syntax)
11672 if (modrm.mod != 0 || base == 5)
11673 {
11674 if (havedisp || riprel)
11675 print_displacement (scratchbuf, disp);
11676 else
11677 print_operand_value (scratchbuf, 1, disp);
11678 oappend (scratchbuf);
11679 if (riprel)
11680 {
11681 set_op (disp, 1);
11682 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11683 }
11684 }
11685
11686 if ((havebase || haveindex || needindex || needaddr32 || riprel)
11687 && (address_mode != mode_64bit
11688 || ((bytemode != v_bnd_mode)
11689 && (bytemode != v_bndmk_mode)
11690 && (bytemode != bnd_mode)
11691 && (bytemode != bnd_swap_mode))))
11692 used_prefixes |= PREFIX_ADDR;
11693
11694 if (havedisp || (intel_syntax && riprel))
11695 {
11696 *obufp++ = open_char;
11697 if (intel_syntax && riprel)
11698 {
11699 set_op (disp, 1);
11700 oappend (!addr32flag ? "rip" : "eip");
11701 }
11702 *obufp = '\0';
11703 if (havebase)
11704 oappend (address_mode == mode_64bit && !addr32flag
11705 ? names64[rbase] : names32[rbase]);
11706 if (havesib)
11707 {
11708 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11709 print index to tell base + index from base. */
11710 if (scale != 0
11711 || needindex
11712 || haveindex
11713 || (havebase && base != ESP_REG_NUM))
11714 {
11715 if (!intel_syntax || havebase)
11716 {
11717 *obufp++ = separator_char;
11718 *obufp = '\0';
11719 }
11720 if (haveindex)
11721 oappend (address_mode == mode_64bit && !addr32flag
11722 ? indexes64[vindex] : indexes32[vindex]);
11723 else
11724 oappend (address_mode == mode_64bit && !addr32flag
11725 ? index64 : index32);
11726
11727 *obufp++ = scale_char;
11728 *obufp = '\0';
11729 sprintf (scratchbuf, "%d", 1 << scale);
11730 oappend (scratchbuf);
11731 }
11732 }
11733 if (intel_syntax
11734 && (disp || modrm.mod != 0 || base == 5))
11735 {
11736 if (!havedisp || (bfd_signed_vma) disp >= 0)
11737 {
11738 *obufp++ = '+';
11739 *obufp = '\0';
11740 }
11741 else if (modrm.mod != 1 && disp != -disp)
11742 {
11743 *obufp++ = '-';
11744 *obufp = '\0';
11745 disp = -disp;
11746 }
11747
11748 if (havedisp)
11749 print_displacement (scratchbuf, disp);
11750 else
11751 print_operand_value (scratchbuf, 1, disp);
11752 oappend (scratchbuf);
11753 }
11754
11755 *obufp++ = close_char;
11756 *obufp = '\0';
11757
11758 if (check_gather)
11759 {
11760 /* Both XMM/YMM/ZMM registers must be distinct. */
11761 int modrm_reg = modrm.reg;
11762
11763 if (rex & REX_R)
11764 modrm_reg += 8;
11765 if (!vex.r)
11766 modrm_reg += 16;
11767 if (vindex == modrm_reg)
11768 oappend ("/(bad)");
11769 }
11770 }
11771 else if (intel_syntax)
11772 {
11773 if (modrm.mod != 0 || base == 5)
11774 {
11775 if (!active_seg_prefix)
11776 {
11777 oappend (names_seg[ds_reg - es_reg]);
11778 oappend (":");
11779 }
11780 print_operand_value (scratchbuf, 1, disp);
11781 oappend (scratchbuf);
11782 }
11783 }
11784 }
11785 else if (bytemode == v_bnd_mode
11786 || bytemode == v_bndmk_mode
11787 || bytemode == bnd_mode
11788 || bytemode == bnd_swap_mode
11789 || bytemode == vex_vsib_d_w_dq_mode
11790 || bytemode == vex_vsib_q_w_dq_mode)
11791 {
11792 oappend ("(bad)");
11793 return;
11794 }
11795 else
11796 {
11797 /* 16 bit address mode */
11798 used_prefixes |= prefixes & PREFIX_ADDR;
11799 switch (modrm.mod)
11800 {
11801 case 0:
11802 if (modrm.rm == 6)
11803 {
11804 disp = get16 ();
11805 if ((disp & 0x8000) != 0)
11806 disp -= 0x10000;
11807 }
11808 break;
11809 case 1:
11810 FETCH_DATA (the_info, codep + 1);
11811 disp = *codep++;
11812 if ((disp & 0x80) != 0)
11813 disp -= 0x100;
11814 if (vex.evex && shift > 0)
11815 disp <<= shift;
11816 break;
11817 case 2:
11818 disp = get16 ();
11819 if ((disp & 0x8000) != 0)
11820 disp -= 0x10000;
11821 break;
11822 }
11823
11824 if (!intel_syntax)
11825 if (modrm.mod != 0 || modrm.rm == 6)
11826 {
11827 print_displacement (scratchbuf, disp);
11828 oappend (scratchbuf);
11829 }
11830
11831 if (modrm.mod != 0 || modrm.rm != 6)
11832 {
11833 *obufp++ = open_char;
11834 *obufp = '\0';
11835 oappend (index16[modrm.rm]);
11836 if (intel_syntax
11837 && (disp || modrm.mod != 0 || modrm.rm == 6))
11838 {
11839 if ((bfd_signed_vma) disp >= 0)
11840 {
11841 *obufp++ = '+';
11842 *obufp = '\0';
11843 }
11844 else if (modrm.mod != 1)
11845 {
11846 *obufp++ = '-';
11847 *obufp = '\0';
11848 disp = -disp;
11849 }
11850
11851 print_displacement (scratchbuf, disp);
11852 oappend (scratchbuf);
11853 }
11854
11855 *obufp++ = close_char;
11856 *obufp = '\0';
11857 }
11858 else if (intel_syntax)
11859 {
11860 if (!active_seg_prefix)
11861 {
11862 oappend (names_seg[ds_reg - es_reg]);
11863 oappend (":");
11864 }
11865 print_operand_value (scratchbuf, 1, disp & 0xffff);
11866 oappend (scratchbuf);
11867 }
11868 }
11869 if (vex.b
11870 && (bytemode == x_mode
11871 || bytemode == evex_half_bcst_xmmq_mode))
11872 {
11873 if (vex.w
11874 || bytemode == evex_half_bcst_xmmq_mode)
11875 {
11876 switch (vex.length)
11877 {
11878 case 128:
11879 oappend ("{1to2}");
11880 break;
11881 case 256:
11882 oappend ("{1to4}");
11883 break;
11884 case 512:
11885 oappend ("{1to8}");
11886 break;
11887 default:
11888 abort ();
11889 }
11890 }
11891 else
11892 {
11893 switch (vex.length)
11894 {
11895 case 128:
11896 oappend ("{1to4}");
11897 break;
11898 case 256:
11899 oappend ("{1to8}");
11900 break;
11901 case 512:
11902 oappend ("{1to16}");
11903 break;
11904 default:
11905 abort ();
11906 }
11907 }
11908 }
11909 }
11910
11911 static void
11912 OP_E (int bytemode, int sizeflag)
11913 {
11914 /* Skip mod/rm byte. */
11915 MODRM_CHECK;
11916 codep++;
11917
11918 if (modrm.mod == 3)
11919 {
11920 if ((sizeflag & SUFFIX_ALWAYS)
11921 && (bytemode == b_swap_mode
11922 || bytemode == bnd_swap_mode
11923 || bytemode == v_swap_mode))
11924 swap_operand ();
11925
11926 print_register (modrm.rm, REX_B, bytemode, sizeflag);
11927 }
11928 else
11929 OP_E_memory (bytemode, sizeflag);
11930 }
11931
11932 static void
11933 OP_G (int bytemode, int sizeflag)
11934 {
11935 if (vex.evex && !vex.r && address_mode == mode_64bit)
11936 {
11937 oappend ("(bad)");
11938 return;
11939 }
11940
11941 print_register (modrm.reg, REX_R, bytemode, sizeflag);
11942 }
11943
11944 static bfd_vma
11945 get64 (void)
11946 {
11947 bfd_vma x;
11948 #ifdef BFD64
11949 unsigned int a;
11950 unsigned int b;
11951
11952 FETCH_DATA (the_info, codep + 8);
11953 a = *codep++ & 0xff;
11954 a |= (*codep++ & 0xff) << 8;
11955 a |= (*codep++ & 0xff) << 16;
11956 a |= (*codep++ & 0xffu) << 24;
11957 b = *codep++ & 0xff;
11958 b |= (*codep++ & 0xff) << 8;
11959 b |= (*codep++ & 0xff) << 16;
11960 b |= (*codep++ & 0xffu) << 24;
11961 x = a + ((bfd_vma) b << 32);
11962 #else
11963 abort ();
11964 x = 0;
11965 #endif
11966 return x;
11967 }
11968
11969 static bfd_signed_vma
11970 get32 (void)
11971 {
11972 bfd_vma x = 0;
11973
11974 FETCH_DATA (the_info, codep + 4);
11975 x = *codep++ & (bfd_vma) 0xff;
11976 x |= (*codep++ & (bfd_vma) 0xff) << 8;
11977 x |= (*codep++ & (bfd_vma) 0xff) << 16;
11978 x |= (*codep++ & (bfd_vma) 0xff) << 24;
11979 return x;
11980 }
11981
11982 static bfd_signed_vma
11983 get32s (void)
11984 {
11985 bfd_vma x = 0;
11986
11987 FETCH_DATA (the_info, codep + 4);
11988 x = *codep++ & (bfd_vma) 0xff;
11989 x |= (*codep++ & (bfd_vma) 0xff) << 8;
11990 x |= (*codep++ & (bfd_vma) 0xff) << 16;
11991 x |= (*codep++ & (bfd_vma) 0xff) << 24;
11992
11993 x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11994
11995 return x;
11996 }
11997
11998 static int
11999 get16 (void)
12000 {
12001 int x = 0;
12002
12003 FETCH_DATA (the_info, codep + 2);
12004 x = *codep++ & 0xff;
12005 x |= (*codep++ & 0xff) << 8;
12006 return x;
12007 }
12008
12009 static void
12010 set_op (bfd_vma op, int riprel)
12011 {
12012 op_index[op_ad] = op_ad;
12013 if (address_mode == mode_64bit)
12014 {
12015 op_address[op_ad] = op;
12016 op_riprel[op_ad] = riprel;
12017 }
12018 else
12019 {
12020 /* Mask to get a 32-bit address. */
12021 op_address[op_ad] = op & 0xffffffff;
12022 op_riprel[op_ad] = riprel & 0xffffffff;
12023 }
12024 }
12025
12026 static void
12027 OP_REG (int code, int sizeflag)
12028 {
12029 const char *s;
12030 int add;
12031
12032 switch (code)
12033 {
12034 case es_reg: case ss_reg: case cs_reg:
12035 case ds_reg: case fs_reg: case gs_reg:
12036 oappend (names_seg[code - es_reg]);
12037 return;
12038 }
12039
12040 USED_REX (REX_B);
12041 if (rex & REX_B)
12042 add = 8;
12043 else
12044 add = 0;
12045
12046 switch (code)
12047 {
12048 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12049 case sp_reg: case bp_reg: case si_reg: case di_reg:
12050 s = names16[code - ax_reg + add];
12051 break;
12052 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12053 USED_REX (0);
12054 /* Fall through. */
12055 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12056 if (rex)
12057 s = names8rex[code - al_reg + add];
12058 else
12059 s = names8[code - al_reg];
12060 break;
12061 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12062 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12063 if (address_mode == mode_64bit
12064 && ((sizeflag & DFLAG) || (rex & REX_W)))
12065 {
12066 s = names64[code - rAX_reg + add];
12067 break;
12068 }
12069 code += eAX_reg - rAX_reg;
12070 /* Fall through. */
12071 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12072 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12073 USED_REX (REX_W);
12074 if (rex & REX_W)
12075 s = names64[code - eAX_reg + add];
12076 else
12077 {
12078 if (sizeflag & DFLAG)
12079 s = names32[code - eAX_reg + add];
12080 else
12081 s = names16[code - eAX_reg + add];
12082 used_prefixes |= (prefixes & PREFIX_DATA);
12083 }
12084 break;
12085 default:
12086 s = INTERNAL_DISASSEMBLER_ERROR;
12087 break;
12088 }
12089 oappend (s);
12090 }
12091
12092 static void
12093 OP_IMREG (int code, int sizeflag)
12094 {
12095 const char *s;
12096
12097 switch (code)
12098 {
12099 case indir_dx_reg:
12100 if (intel_syntax)
12101 s = "dx";
12102 else
12103 s = "(%dx)";
12104 break;
12105 case al_reg: case cl_reg:
12106 s = names8[code - al_reg];
12107 break;
12108 case eAX_reg:
12109 USED_REX (REX_W);
12110 if (rex & REX_W)
12111 {
12112 s = *names64;
12113 break;
12114 }
12115 /* Fall through. */
12116 case z_mode_ax_reg:
12117 if ((rex & REX_W) || (sizeflag & DFLAG))
12118 s = *names32;
12119 else
12120 s = *names16;
12121 if (!(rex & REX_W))
12122 used_prefixes |= (prefixes & PREFIX_DATA);
12123 break;
12124 default:
12125 s = INTERNAL_DISASSEMBLER_ERROR;
12126 break;
12127 }
12128 oappend (s);
12129 }
12130
12131 static void
12132 OP_I (int bytemode, int sizeflag)
12133 {
12134 bfd_signed_vma op;
12135 bfd_signed_vma mask = -1;
12136
12137 switch (bytemode)
12138 {
12139 case b_mode:
12140 FETCH_DATA (the_info, codep + 1);
12141 op = *codep++;
12142 mask = 0xff;
12143 break;
12144 case v_mode:
12145 USED_REX (REX_W);
12146 if (rex & REX_W)
12147 op = get32s ();
12148 else
12149 {
12150 if (sizeflag & DFLAG)
12151 {
12152 op = get32 ();
12153 mask = 0xffffffff;
12154 }
12155 else
12156 {
12157 op = get16 ();
12158 mask = 0xfffff;
12159 }
12160 used_prefixes |= (prefixes & PREFIX_DATA);
12161 }
12162 break;
12163 case d_mode:
12164 mask = 0xffffffff;
12165 op = get32 ();
12166 break;
12167 case w_mode:
12168 mask = 0xfffff;
12169 op = get16 ();
12170 break;
12171 case const_1_mode:
12172 if (intel_syntax)
12173 oappend ("1");
12174 return;
12175 default:
12176 oappend (INTERNAL_DISASSEMBLER_ERROR);
12177 return;
12178 }
12179
12180 op &= mask;
12181 scratchbuf[0] = '$';
12182 print_operand_value (scratchbuf + 1, 1, op);
12183 oappend_maybe_intel (scratchbuf);
12184 scratchbuf[0] = '\0';
12185 }
12186
12187 static void
12188 OP_I64 (int bytemode, int sizeflag)
12189 {
12190 if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12191 {
12192 OP_I (bytemode, sizeflag);
12193 return;
12194 }
12195
12196 USED_REX (REX_W);
12197
12198 scratchbuf[0] = '$';
12199 print_operand_value (scratchbuf + 1, 1, get64 ());
12200 oappend_maybe_intel (scratchbuf);
12201 scratchbuf[0] = '\0';
12202 }
12203
12204 static void
12205 OP_sI (int bytemode, int sizeflag)
12206 {
12207 bfd_signed_vma op;
12208
12209 switch (bytemode)
12210 {
12211 case b_mode:
12212 case b_T_mode:
12213 FETCH_DATA (the_info, codep + 1);
12214 op = *codep++;
12215 if ((op & 0x80) != 0)
12216 op -= 0x100;
12217 if (bytemode == b_T_mode)
12218 {
12219 if (address_mode != mode_64bit
12220 || !((sizeflag & DFLAG) || (rex & REX_W)))
12221 {
12222 /* The operand-size prefix is overridden by a REX prefix. */
12223 if ((sizeflag & DFLAG) || (rex & REX_W))
12224 op &= 0xffffffff;
12225 else
12226 op &= 0xffff;
12227 }
12228 }
12229 else
12230 {
12231 if (!(rex & REX_W))
12232 {
12233 if (sizeflag & DFLAG)
12234 op &= 0xffffffff;
12235 else
12236 op &= 0xffff;
12237 }
12238 }
12239 break;
12240 case v_mode:
12241 /* The operand-size prefix is overridden by a REX prefix. */
12242 if ((sizeflag & DFLAG) || (rex & REX_W))
12243 op = get32s ();
12244 else
12245 op = get16 ();
12246 break;
12247 default:
12248 oappend (INTERNAL_DISASSEMBLER_ERROR);
12249 return;
12250 }
12251
12252 scratchbuf[0] = '$';
12253 print_operand_value (scratchbuf + 1, 1, op);
12254 oappend_maybe_intel (scratchbuf);
12255 }
12256
12257 static void
12258 OP_J (int bytemode, int sizeflag)
12259 {
12260 bfd_vma disp;
12261 bfd_vma mask = -1;
12262 bfd_vma segment = 0;
12263
12264 switch (bytemode)
12265 {
12266 case b_mode:
12267 FETCH_DATA (the_info, codep + 1);
12268 disp = *codep++;
12269 if ((disp & 0x80) != 0)
12270 disp -= 0x100;
12271 break;
12272 case v_mode:
12273 case dqw_mode:
12274 if ((sizeflag & DFLAG)
12275 || (address_mode == mode_64bit
12276 && ((isa64 == intel64 && bytemode != dqw_mode)
12277 || (rex & REX_W))))
12278 disp = get32s ();
12279 else
12280 {
12281 disp = get16 ();
12282 if ((disp & 0x8000) != 0)
12283 disp -= 0x10000;
12284 /* In 16bit mode, address is wrapped around at 64k within
12285 the same segment. Otherwise, a data16 prefix on a jump
12286 instruction means that the pc is masked to 16 bits after
12287 the displacement is added! */
12288 mask = 0xffff;
12289 if ((prefixes & PREFIX_DATA) == 0)
12290 segment = ((start_pc + (codep - start_codep))
12291 & ~((bfd_vma) 0xffff));
12292 }
12293 if (address_mode != mode_64bit
12294 || (isa64 != intel64 && !(rex & REX_W)))
12295 used_prefixes |= (prefixes & PREFIX_DATA);
12296 break;
12297 default:
12298 oappend (INTERNAL_DISASSEMBLER_ERROR);
12299 return;
12300 }
12301 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12302 set_op (disp, 0);
12303 print_operand_value (scratchbuf, 1, disp);
12304 oappend (scratchbuf);
12305 }
12306
12307 static void
12308 OP_SEG (int bytemode, int sizeflag)
12309 {
12310 if (bytemode == w_mode)
12311 oappend (names_seg[modrm.reg]);
12312 else
12313 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12314 }
12315
12316 static void
12317 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12318 {
12319 int seg, offset;
12320
12321 if (sizeflag & DFLAG)
12322 {
12323 offset = get32 ();
12324 seg = get16 ();
12325 }
12326 else
12327 {
12328 offset = get16 ();
12329 seg = get16 ();
12330 }
12331 used_prefixes |= (prefixes & PREFIX_DATA);
12332 if (intel_syntax)
12333 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12334 else
12335 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12336 oappend (scratchbuf);
12337 }
12338
12339 static void
12340 OP_OFF (int bytemode, int sizeflag)
12341 {
12342 bfd_vma off;
12343
12344 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12345 intel_operand_size (bytemode, sizeflag);
12346 append_seg ();
12347
12348 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12349 off = get32 ();
12350 else
12351 off = get16 ();
12352
12353 if (intel_syntax)
12354 {
12355 if (!active_seg_prefix)
12356 {
12357 oappend (names_seg[ds_reg - es_reg]);
12358 oappend (":");
12359 }
12360 }
12361 print_operand_value (scratchbuf, 1, off);
12362 oappend (scratchbuf);
12363 }
12364
12365 static void
12366 OP_OFF64 (int bytemode, int sizeflag)
12367 {
12368 bfd_vma off;
12369
12370 if (address_mode != mode_64bit
12371 || (prefixes & PREFIX_ADDR))
12372 {
12373 OP_OFF (bytemode, sizeflag);
12374 return;
12375 }
12376
12377 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12378 intel_operand_size (bytemode, sizeflag);
12379 append_seg ();
12380
12381 off = get64 ();
12382
12383 if (intel_syntax)
12384 {
12385 if (!active_seg_prefix)
12386 {
12387 oappend (names_seg[ds_reg - es_reg]);
12388 oappend (":");
12389 }
12390 }
12391 print_operand_value (scratchbuf, 1, off);
12392 oappend (scratchbuf);
12393 }
12394
12395 static void
12396 ptr_reg (int code, int sizeflag)
12397 {
12398 const char *s;
12399
12400 *obufp++ = open_char;
12401 used_prefixes |= (prefixes & PREFIX_ADDR);
12402 if (address_mode == mode_64bit)
12403 {
12404 if (!(sizeflag & AFLAG))
12405 s = names32[code - eAX_reg];
12406 else
12407 s = names64[code - eAX_reg];
12408 }
12409 else if (sizeflag & AFLAG)
12410 s = names32[code - eAX_reg];
12411 else
12412 s = names16[code - eAX_reg];
12413 oappend (s);
12414 *obufp++ = close_char;
12415 *obufp = 0;
12416 }
12417
12418 static void
12419 OP_ESreg (int code, int sizeflag)
12420 {
12421 if (intel_syntax)
12422 {
12423 switch (codep[-1])
12424 {
12425 case 0x6d: /* insw/insl */
12426 intel_operand_size (z_mode, sizeflag);
12427 break;
12428 case 0xa5: /* movsw/movsl/movsq */
12429 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12430 case 0xab: /* stosw/stosl */
12431 case 0xaf: /* scasw/scasl */
12432 intel_operand_size (v_mode, sizeflag);
12433 break;
12434 default:
12435 intel_operand_size (b_mode, sizeflag);
12436 }
12437 }
12438 oappend_maybe_intel ("%es:");
12439 ptr_reg (code, sizeflag);
12440 }
12441
12442 static void
12443 OP_DSreg (int code, int sizeflag)
12444 {
12445 if (intel_syntax)
12446 {
12447 switch (codep[-1])
12448 {
12449 case 0x6f: /* outsw/outsl */
12450 intel_operand_size (z_mode, sizeflag);
12451 break;
12452 case 0xa5: /* movsw/movsl/movsq */
12453 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12454 case 0xad: /* lodsw/lodsl/lodsq */
12455 intel_operand_size (v_mode, sizeflag);
12456 break;
12457 default:
12458 intel_operand_size (b_mode, sizeflag);
12459 }
12460 }
12461 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12462 default segment register DS is printed. */
12463 if (!active_seg_prefix)
12464 active_seg_prefix = PREFIX_DS;
12465 append_seg ();
12466 ptr_reg (code, sizeflag);
12467 }
12468
12469 static void
12470 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12471 {
12472 int add;
12473 if (rex & REX_R)
12474 {
12475 USED_REX (REX_R);
12476 add = 8;
12477 }
12478 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12479 {
12480 all_prefixes[last_lock_prefix] = 0;
12481 used_prefixes |= PREFIX_LOCK;
12482 add = 8;
12483 }
12484 else
12485 add = 0;
12486 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12487 oappend_maybe_intel (scratchbuf);
12488 }
12489
12490 static void
12491 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12492 {
12493 int add;
12494 USED_REX (REX_R);
12495 if (rex & REX_R)
12496 add = 8;
12497 else
12498 add = 0;
12499 if (intel_syntax)
12500 sprintf (scratchbuf, "dr%d", modrm.reg + add);
12501 else
12502 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12503 oappend (scratchbuf);
12504 }
12505
12506 static void
12507 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12508 {
12509 sprintf (scratchbuf, "%%tr%d", modrm.reg);
12510 oappend_maybe_intel (scratchbuf);
12511 }
12512
12513 static void
12514 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12515 {
12516 int reg = modrm.reg;
12517 const char **names;
12518
12519 used_prefixes |= (prefixes & PREFIX_DATA);
12520 if (prefixes & PREFIX_DATA)
12521 {
12522 names = names_xmm;
12523 USED_REX (REX_R);
12524 if (rex & REX_R)
12525 reg += 8;
12526 }
12527 else
12528 names = names_mm;
12529 oappend (names[reg]);
12530 }
12531
12532 static void
12533 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12534 {
12535 int reg = modrm.reg;
12536 const char **names;
12537
12538 USED_REX (REX_R);
12539 if (rex & REX_R)
12540 reg += 8;
12541 if (vex.evex)
12542 {
12543 if (!vex.r)
12544 reg += 16;
12545 }
12546
12547 if (bytemode == xmmq_mode
12548 || bytemode == evex_half_bcst_xmmq_mode)
12549 {
12550 switch (vex.length)
12551 {
12552 case 128:
12553 case 256:
12554 names = names_xmm;
12555 break;
12556 case 512:
12557 names = names_ymm;
12558 break;
12559 default:
12560 abort ();
12561 }
12562 }
12563 else if (bytemode == ymm_mode)
12564 names = names_ymm;
12565 else if (bytemode == tmm_mode)
12566 {
12567 modrm.reg = reg;
12568 if (reg >= 8)
12569 {
12570 oappend ("(bad)");
12571 return;
12572 }
12573 names = names_tmm;
12574 }
12575 else if (need_vex
12576 && bytemode != xmm_mode
12577 && bytemode != scalar_mode)
12578 {
12579 switch (vex.length)
12580 {
12581 case 128:
12582 names = names_xmm;
12583 break;
12584 case 256:
12585 if (vex.w
12586 || bytemode != vex_vsib_q_w_dq_mode)
12587 names = names_ymm;
12588 else
12589 names = names_xmm;
12590 break;
12591 case 512:
12592 if (vex.w
12593 || bytemode != vex_vsib_q_w_dq_mode)
12594 names = names_zmm;
12595 else
12596 names = names_ymm;
12597 break;
12598 default:
12599 abort ();
12600 }
12601 }
12602 else
12603 names = names_xmm;
12604 oappend (names[reg]);
12605 }
12606
12607 static void
12608 OP_EM (int bytemode, int sizeflag)
12609 {
12610 int reg;
12611 const char **names;
12612
12613 if (modrm.mod != 3)
12614 {
12615 if (intel_syntax
12616 && (bytemode == v_mode || bytemode == v_swap_mode))
12617 {
12618 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12619 used_prefixes |= (prefixes & PREFIX_DATA);
12620 }
12621 OP_E (bytemode, sizeflag);
12622 return;
12623 }
12624
12625 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12626 swap_operand ();
12627
12628 /* Skip mod/rm byte. */
12629 MODRM_CHECK;
12630 codep++;
12631 used_prefixes |= (prefixes & PREFIX_DATA);
12632 reg = modrm.rm;
12633 if (prefixes & PREFIX_DATA)
12634 {
12635 names = names_xmm;
12636 USED_REX (REX_B);
12637 if (rex & REX_B)
12638 reg += 8;
12639 }
12640 else
12641 names = names_mm;
12642 oappend (names[reg]);
12643 }
12644
12645 /* cvt* are the only instructions in sse2 which have
12646 both SSE and MMX operands and also have 0x66 prefix
12647 in their opcode. 0x66 was originally used to differentiate
12648 between SSE and MMX instruction(operands). So we have to handle the
12649 cvt* separately using OP_EMC and OP_MXC */
12650 static void
12651 OP_EMC (int bytemode, int sizeflag)
12652 {
12653 if (modrm.mod != 3)
12654 {
12655 if (intel_syntax && bytemode == v_mode)
12656 {
12657 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12658 used_prefixes |= (prefixes & PREFIX_DATA);
12659 }
12660 OP_E (bytemode, sizeflag);
12661 return;
12662 }
12663
12664 /* Skip mod/rm byte. */
12665 MODRM_CHECK;
12666 codep++;
12667 used_prefixes |= (prefixes & PREFIX_DATA);
12668 oappend (names_mm[modrm.rm]);
12669 }
12670
12671 static void
12672 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12673 {
12674 used_prefixes |= (prefixes & PREFIX_DATA);
12675 oappend (names_mm[modrm.reg]);
12676 }
12677
12678 static void
12679 OP_EX (int bytemode, int sizeflag)
12680 {
12681 int reg;
12682 const char **names;
12683
12684 /* Skip mod/rm byte. */
12685 MODRM_CHECK;
12686 codep++;
12687
12688 if (modrm.mod != 3)
12689 {
12690 OP_E_memory (bytemode, sizeflag);
12691 return;
12692 }
12693
12694 reg = modrm.rm;
12695 USED_REX (REX_B);
12696 if (rex & REX_B)
12697 reg += 8;
12698 if (vex.evex)
12699 {
12700 USED_REX (REX_X);
12701 if ((rex & REX_X))
12702 reg += 16;
12703 }
12704
12705 if ((sizeflag & SUFFIX_ALWAYS)
12706 && (bytemode == x_swap_mode
12707 || bytemode == d_swap_mode
12708 || bytemode == q_swap_mode))
12709 swap_operand ();
12710
12711 if (need_vex
12712 && bytemode != xmm_mode
12713 && bytemode != xmmdw_mode
12714 && bytemode != xmmqd_mode
12715 && bytemode != xmm_mb_mode
12716 && bytemode != xmm_mw_mode
12717 && bytemode != xmm_md_mode
12718 && bytemode != xmm_mq_mode
12719 && bytemode != xmmq_mode
12720 && bytemode != evex_half_bcst_xmmq_mode
12721 && bytemode != ymm_mode
12722 && bytemode != tmm_mode
12723 && bytemode != vex_scalar_w_dq_mode)
12724 {
12725 switch (vex.length)
12726 {
12727 case 128:
12728 names = names_xmm;
12729 break;
12730 case 256:
12731 names = names_ymm;
12732 break;
12733 case 512:
12734 names = names_zmm;
12735 break;
12736 default:
12737 abort ();
12738 }
12739 }
12740 else if (bytemode == xmmq_mode
12741 || bytemode == evex_half_bcst_xmmq_mode)
12742 {
12743 switch (vex.length)
12744 {
12745 case 128:
12746 case 256:
12747 names = names_xmm;
12748 break;
12749 case 512:
12750 names = names_ymm;
12751 break;
12752 default:
12753 abort ();
12754 }
12755 }
12756 else if (bytemode == tmm_mode)
12757 {
12758 modrm.rm = reg;
12759 if (reg >= 8)
12760 {
12761 oappend ("(bad)");
12762 return;
12763 }
12764 names = names_tmm;
12765 }
12766 else if (bytemode == ymm_mode)
12767 names = names_ymm;
12768 else
12769 names = names_xmm;
12770 oappend (names[reg]);
12771 }
12772
12773 static void
12774 OP_MS (int bytemode, int sizeflag)
12775 {
12776 if (modrm.mod == 3)
12777 OP_EM (bytemode, sizeflag);
12778 else
12779 BadOp ();
12780 }
12781
12782 static void
12783 OP_XS (int bytemode, int sizeflag)
12784 {
12785 if (modrm.mod == 3)
12786 OP_EX (bytemode, sizeflag);
12787 else
12788 BadOp ();
12789 }
12790
12791 static void
12792 OP_M (int bytemode, int sizeflag)
12793 {
12794 if (modrm.mod == 3)
12795 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12796 BadOp ();
12797 else
12798 OP_E (bytemode, sizeflag);
12799 }
12800
12801 static void
12802 OP_0f07 (int bytemode, int sizeflag)
12803 {
12804 if (modrm.mod != 3 || modrm.rm != 0)
12805 BadOp ();
12806 else
12807 OP_E (bytemode, sizeflag);
12808 }
12809
12810 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12811 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12812
12813 static void
12814 NOP_Fixup1 (int bytemode, int sizeflag)
12815 {
12816 if ((prefixes & PREFIX_DATA) != 0
12817 || (rex != 0
12818 && rex != 0x48
12819 && address_mode == mode_64bit))
12820 OP_REG (bytemode, sizeflag);
12821 else
12822 strcpy (obuf, "nop");
12823 }
12824
12825 static void
12826 NOP_Fixup2 (int bytemode, int sizeflag)
12827 {
12828 if ((prefixes & PREFIX_DATA) != 0
12829 || (rex != 0
12830 && rex != 0x48
12831 && address_mode == mode_64bit))
12832 OP_IMREG (bytemode, sizeflag);
12833 }
12834
12835 static const char *const Suffix3DNow[] = {
12836 /* 00 */ NULL, NULL, NULL, NULL,
12837 /* 04 */ NULL, NULL, NULL, NULL,
12838 /* 08 */ NULL, NULL, NULL, NULL,
12839 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
12840 /* 10 */ NULL, NULL, NULL, NULL,
12841 /* 14 */ NULL, NULL, NULL, NULL,
12842 /* 18 */ NULL, NULL, NULL, NULL,
12843 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
12844 /* 20 */ NULL, NULL, NULL, NULL,
12845 /* 24 */ NULL, NULL, NULL, NULL,
12846 /* 28 */ NULL, NULL, NULL, NULL,
12847 /* 2C */ NULL, NULL, NULL, NULL,
12848 /* 30 */ NULL, NULL, NULL, NULL,
12849 /* 34 */ NULL, NULL, NULL, NULL,
12850 /* 38 */ NULL, NULL, NULL, NULL,
12851 /* 3C */ NULL, NULL, NULL, NULL,
12852 /* 40 */ NULL, NULL, NULL, NULL,
12853 /* 44 */ NULL, NULL, NULL, NULL,
12854 /* 48 */ NULL, NULL, NULL, NULL,
12855 /* 4C */ NULL, NULL, NULL, NULL,
12856 /* 50 */ NULL, NULL, NULL, NULL,
12857 /* 54 */ NULL, NULL, NULL, NULL,
12858 /* 58 */ NULL, NULL, NULL, NULL,
12859 /* 5C */ NULL, NULL, NULL, NULL,
12860 /* 60 */ NULL, NULL, NULL, NULL,
12861 /* 64 */ NULL, NULL, NULL, NULL,
12862 /* 68 */ NULL, NULL, NULL, NULL,
12863 /* 6C */ NULL, NULL, NULL, NULL,
12864 /* 70 */ NULL, NULL, NULL, NULL,
12865 /* 74 */ NULL, NULL, NULL, NULL,
12866 /* 78 */ NULL, NULL, NULL, NULL,
12867 /* 7C */ NULL, NULL, NULL, NULL,
12868 /* 80 */ NULL, NULL, NULL, NULL,
12869 /* 84 */ NULL, NULL, NULL, NULL,
12870 /* 88 */ NULL, NULL, "pfnacc", NULL,
12871 /* 8C */ NULL, NULL, "pfpnacc", NULL,
12872 /* 90 */ "pfcmpge", NULL, NULL, NULL,
12873 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12874 /* 98 */ NULL, NULL, "pfsub", NULL,
12875 /* 9C */ NULL, NULL, "pfadd", NULL,
12876 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
12877 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
12878 /* A8 */ NULL, NULL, "pfsubr", NULL,
12879 /* AC */ NULL, NULL, "pfacc", NULL,
12880 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
12881 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
12882 /* B8 */ NULL, NULL, NULL, "pswapd",
12883 /* BC */ NULL, NULL, NULL, "pavgusb",
12884 /* C0 */ NULL, NULL, NULL, NULL,
12885 /* C4 */ NULL, NULL, NULL, NULL,
12886 /* C8 */ NULL, NULL, NULL, NULL,
12887 /* CC */ NULL, NULL, NULL, NULL,
12888 /* D0 */ NULL, NULL, NULL, NULL,
12889 /* D4 */ NULL, NULL, NULL, NULL,
12890 /* D8 */ NULL, NULL, NULL, NULL,
12891 /* DC */ NULL, NULL, NULL, NULL,
12892 /* E0 */ NULL, NULL, NULL, NULL,
12893 /* E4 */ NULL, NULL, NULL, NULL,
12894 /* E8 */ NULL, NULL, NULL, NULL,
12895 /* EC */ NULL, NULL, NULL, NULL,
12896 /* F0 */ NULL, NULL, NULL, NULL,
12897 /* F4 */ NULL, NULL, NULL, NULL,
12898 /* F8 */ NULL, NULL, NULL, NULL,
12899 /* FC */ NULL, NULL, NULL, NULL,
12900 };
12901
12902 static void
12903 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12904 {
12905 const char *mnemonic;
12906
12907 FETCH_DATA (the_info, codep + 1);
12908 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12909 place where an 8-bit immediate would normally go. ie. the last
12910 byte of the instruction. */
12911 obufp = mnemonicendp;
12912 mnemonic = Suffix3DNow[*codep++ & 0xff];
12913 if (mnemonic)
12914 oappend (mnemonic);
12915 else
12916 {
12917 /* Since a variable sized modrm/sib chunk is between the start
12918 of the opcode (0x0f0f) and the opcode suffix, we need to do
12919 all the modrm processing first, and don't know until now that
12920 we have a bad opcode. This necessitates some cleaning up. */
12921 op_out[0][0] = '\0';
12922 op_out[1][0] = '\0';
12923 BadOp ();
12924 }
12925 mnemonicendp = obufp;
12926 }
12927
12928 static const struct op simd_cmp_op[] =
12929 {
12930 { STRING_COMMA_LEN ("eq") },
12931 { STRING_COMMA_LEN ("lt") },
12932 { STRING_COMMA_LEN ("le") },
12933 { STRING_COMMA_LEN ("unord") },
12934 { STRING_COMMA_LEN ("neq") },
12935 { STRING_COMMA_LEN ("nlt") },
12936 { STRING_COMMA_LEN ("nle") },
12937 { STRING_COMMA_LEN ("ord") }
12938 };
12939
12940 static const struct op vex_cmp_op[] =
12941 {
12942 { STRING_COMMA_LEN ("eq_uq") },
12943 { STRING_COMMA_LEN ("nge") },
12944 { STRING_COMMA_LEN ("ngt") },
12945 { STRING_COMMA_LEN ("false") },
12946 { STRING_COMMA_LEN ("neq_oq") },
12947 { STRING_COMMA_LEN ("ge") },
12948 { STRING_COMMA_LEN ("gt") },
12949 { STRING_COMMA_LEN ("true") },
12950 { STRING_COMMA_LEN ("eq_os") },
12951 { STRING_COMMA_LEN ("lt_oq") },
12952 { STRING_COMMA_LEN ("le_oq") },
12953 { STRING_COMMA_LEN ("unord_s") },
12954 { STRING_COMMA_LEN ("neq_us") },
12955 { STRING_COMMA_LEN ("nlt_uq") },
12956 { STRING_COMMA_LEN ("nle_uq") },
12957 { STRING_COMMA_LEN ("ord_s") },
12958 { STRING_COMMA_LEN ("eq_us") },
12959 { STRING_COMMA_LEN ("nge_uq") },
12960 { STRING_COMMA_LEN ("ngt_uq") },
12961 { STRING_COMMA_LEN ("false_os") },
12962 { STRING_COMMA_LEN ("neq_os") },
12963 { STRING_COMMA_LEN ("ge_oq") },
12964 { STRING_COMMA_LEN ("gt_oq") },
12965 { STRING_COMMA_LEN ("true_us") },
12966 };
12967
12968 static void
12969 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12970 {
12971 unsigned int cmp_type;
12972
12973 FETCH_DATA (the_info, codep + 1);
12974 cmp_type = *codep++ & 0xff;
12975 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12976 {
12977 char suffix [3];
12978 char *p = mnemonicendp - 2;
12979 suffix[0] = p[0];
12980 suffix[1] = p[1];
12981 suffix[2] = '\0';
12982 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12983 mnemonicendp += simd_cmp_op[cmp_type].len;
12984 }
12985 else if (need_vex
12986 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
12987 {
12988 char suffix [3];
12989 char *p = mnemonicendp - 2;
12990 suffix[0] = p[0];
12991 suffix[1] = p[1];
12992 suffix[2] = '\0';
12993 cmp_type -= ARRAY_SIZE (simd_cmp_op);
12994 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
12995 mnemonicendp += vex_cmp_op[cmp_type].len;
12996 }
12997 else
12998 {
12999 /* We have a reserved extension byte. Output it directly. */
13000 scratchbuf[0] = '$';
13001 print_operand_value (scratchbuf + 1, 1, cmp_type);
13002 oappend_maybe_intel (scratchbuf);
13003 scratchbuf[0] = '\0';
13004 }
13005 }
13006
13007 static void
13008 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13009 {
13010 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13011 if (!intel_syntax)
13012 {
13013 strcpy (op_out[0], names32[0]);
13014 strcpy (op_out[1], names32[1]);
13015 if (bytemode == eBX_reg)
13016 strcpy (op_out[2], names32[3]);
13017 two_source_ops = 1;
13018 }
13019 /* Skip mod/rm byte. */
13020 MODRM_CHECK;
13021 codep++;
13022 }
13023
13024 static void
13025 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13026 int sizeflag ATTRIBUTE_UNUSED)
13027 {
13028 /* monitor %{e,r,}ax,%ecx,%edx" */
13029 if (!intel_syntax)
13030 {
13031 const char **names = (address_mode == mode_64bit
13032 ? names64 : names32);
13033
13034 if (prefixes & PREFIX_ADDR)
13035 {
13036 /* Remove "addr16/addr32". */
13037 all_prefixes[last_addr_prefix] = 0;
13038 names = (address_mode != mode_32bit
13039 ? names32 : names16);
13040 used_prefixes |= PREFIX_ADDR;
13041 }
13042 else if (address_mode == mode_16bit)
13043 names = names16;
13044 strcpy (op_out[0], names[0]);
13045 strcpy (op_out[1], names32[1]);
13046 strcpy (op_out[2], names32[2]);
13047 two_source_ops = 1;
13048 }
13049 /* Skip mod/rm byte. */
13050 MODRM_CHECK;
13051 codep++;
13052 }
13053
13054 static void
13055 BadOp (void)
13056 {
13057 /* Throw away prefixes and 1st. opcode byte. */
13058 codep = insn_codep + 1;
13059 oappend ("(bad)");
13060 }
13061
13062 static void
13063 REP_Fixup (int bytemode, int sizeflag)
13064 {
13065 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13066 lods and stos. */
13067 if (prefixes & PREFIX_REPZ)
13068 all_prefixes[last_repz_prefix] = REP_PREFIX;
13069
13070 switch (bytemode)
13071 {
13072 case al_reg:
13073 case eAX_reg:
13074 case indir_dx_reg:
13075 OP_IMREG (bytemode, sizeflag);
13076 break;
13077 case eDI_reg:
13078 OP_ESreg (bytemode, sizeflag);
13079 break;
13080 case eSI_reg:
13081 OP_DSreg (bytemode, sizeflag);
13082 break;
13083 default:
13084 abort ();
13085 break;
13086 }
13087 }
13088
13089 static void
13090 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13091 {
13092 if ( isa64 != amd64 )
13093 return;
13094
13095 obufp = obuf;
13096 BadOp ();
13097 mnemonicendp = obufp;
13098 ++codep;
13099 }
13100
13101 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13102 "bnd". */
13103
13104 static void
13105 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13106 {
13107 if (prefixes & PREFIX_REPNZ)
13108 all_prefixes[last_repnz_prefix] = BND_PREFIX;
13109 }
13110
13111 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13112 "notrack". */
13113
13114 static void
13115 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13116 int sizeflag ATTRIBUTE_UNUSED)
13117 {
13118
13119 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13120 we've seen a PREFIX_DS. */
13121 if ((prefixes & PREFIX_DS) != 0
13122 && (address_mode != mode_64bit || last_data_prefix < 0))
13123 {
13124 /* NOTRACK prefix is only valid on indirect branch instructions.
13125 NB: DATA prefix is unsupported for Intel64. */
13126 active_seg_prefix = 0;
13127 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13128 }
13129 }
13130
13131 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13132 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13133 */
13134
13135 static void
13136 HLE_Fixup1 (int bytemode, int sizeflag)
13137 {
13138 if (modrm.mod != 3
13139 && (prefixes & PREFIX_LOCK) != 0)
13140 {
13141 if (prefixes & PREFIX_REPZ)
13142 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13143 if (prefixes & PREFIX_REPNZ)
13144 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13145 }
13146
13147 OP_E (bytemode, sizeflag);
13148 }
13149
13150 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13151 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13152 */
13153
13154 static void
13155 HLE_Fixup2 (int bytemode, int sizeflag)
13156 {
13157 if (modrm.mod != 3)
13158 {
13159 if (prefixes & PREFIX_REPZ)
13160 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13161 if (prefixes & PREFIX_REPNZ)
13162 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13163 }
13164
13165 OP_E (bytemode, sizeflag);
13166 }
13167
13168 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13169 "xrelease" for memory operand. No check for LOCK prefix. */
13170
13171 static void
13172 HLE_Fixup3 (int bytemode, int sizeflag)
13173 {
13174 if (modrm.mod != 3
13175 && last_repz_prefix > last_repnz_prefix
13176 && (prefixes & PREFIX_REPZ) != 0)
13177 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13178
13179 OP_E (bytemode, sizeflag);
13180 }
13181
13182 static void
13183 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13184 {
13185 USED_REX (REX_W);
13186 if (rex & REX_W)
13187 {
13188 /* Change cmpxchg8b to cmpxchg16b. */
13189 char *p = mnemonicendp - 2;
13190 mnemonicendp = stpcpy (p, "16b");
13191 bytemode = o_mode;
13192 }
13193 else if ((prefixes & PREFIX_LOCK) != 0)
13194 {
13195 if (prefixes & PREFIX_REPZ)
13196 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13197 if (prefixes & PREFIX_REPNZ)
13198 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13199 }
13200
13201 OP_M (bytemode, sizeflag);
13202 }
13203
13204 static void
13205 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13206 {
13207 const char **names;
13208
13209 if (need_vex)
13210 {
13211 switch (vex.length)
13212 {
13213 case 128:
13214 names = names_xmm;
13215 break;
13216 case 256:
13217 names = names_ymm;
13218 break;
13219 default:
13220 abort ();
13221 }
13222 }
13223 else
13224 names = names_xmm;
13225 oappend (names[reg]);
13226 }
13227
13228 static void
13229 FXSAVE_Fixup (int bytemode, int sizeflag)
13230 {
13231 /* Add proper suffix to "fxsave" and "fxrstor". */
13232 USED_REX (REX_W);
13233 if (rex & REX_W)
13234 {
13235 char *p = mnemonicendp;
13236 *p++ = '6';
13237 *p++ = '4';
13238 *p = '\0';
13239 mnemonicendp = p;
13240 }
13241 OP_M (bytemode, sizeflag);
13242 }
13243
13244 /* Display the destination register operand for instructions with
13245 VEX. */
13246
13247 static void
13248 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13249 {
13250 int reg, modrm_reg, sib_index = -1;
13251 const char **names;
13252
13253 if (!need_vex)
13254 abort ();
13255
13256 reg = vex.register_specifier;
13257 vex.register_specifier = 0;
13258 if (address_mode != mode_64bit)
13259 reg &= 7;
13260 else if (vex.evex && !vex.v)
13261 reg += 16;
13262
13263 switch (bytemode)
13264 {
13265 case vex_scalar_mode:
13266 oappend (names_xmm[reg]);
13267 return;
13268
13269 case vex_vsib_d_w_dq_mode:
13270 case vex_vsib_q_w_dq_mode:
13271 /* This must be the 3rd operand. */
13272 if (obufp != op_out[2])
13273 abort ();
13274 if (vex.length == 128
13275 || (bytemode != vex_vsib_d_w_dq_mode
13276 && !vex.w))
13277 oappend (names_xmm[reg]);
13278 else
13279 oappend (names_ymm[reg]);
13280
13281 /* All 3 XMM/YMM registers must be distinct. */
13282 modrm_reg = modrm.reg;
13283 if (rex & REX_R)
13284 modrm_reg += 8;
13285
13286 if (modrm.rm == 4)
13287 {
13288 sib_index = sib.index;
13289 if (rex & REX_X)
13290 sib_index += 8;
13291 }
13292
13293 if (reg == modrm_reg || reg == sib_index)
13294 strcpy (obufp, "/(bad)");
13295 if (modrm_reg == sib_index || modrm_reg == reg)
13296 strcat (op_out[0], "/(bad)");
13297 if (sib_index == modrm_reg || sib_index == reg)
13298 strcat (op_out[1], "/(bad)");
13299
13300 return;
13301
13302 case tmm_mode:
13303 /* All 3 TMM registers must be distinct. */
13304 if (reg >= 8)
13305 oappend ("(bad)");
13306 else
13307 {
13308 /* This must be the 3rd operand. */
13309 if (obufp != op_out[2])
13310 abort ();
13311 oappend (names_tmm[reg]);
13312 if (reg == modrm.reg || reg == modrm.rm)
13313 strcpy (obufp, "/(bad)");
13314 }
13315
13316 if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13317 {
13318 if (modrm.reg <= 8
13319 && (modrm.reg == modrm.rm || modrm.reg == reg))
13320 strcat (op_out[0], "/(bad)");
13321 if (modrm.rm <= 8
13322 && (modrm.rm == modrm.reg || modrm.rm == reg))
13323 strcat (op_out[1], "/(bad)");
13324 }
13325
13326 return;
13327 }
13328
13329 switch (vex.length)
13330 {
13331 case 128:
13332 switch (bytemode)
13333 {
13334 case vex_mode:
13335 names = names_xmm;
13336 break;
13337 case dq_mode:
13338 if (rex & REX_W)
13339 names = names64;
13340 else
13341 names = names32;
13342 break;
13343 case mask_bd_mode:
13344 case mask_mode:
13345 if (reg > 0x7)
13346 {
13347 oappend ("(bad)");
13348 return;
13349 }
13350 names = names_mask;
13351 break;
13352 default:
13353 abort ();
13354 return;
13355 }
13356 break;
13357 case 256:
13358 switch (bytemode)
13359 {
13360 case vex_mode:
13361 names = names_ymm;
13362 break;
13363 case mask_bd_mode:
13364 case mask_mode:
13365 if (reg > 0x7)
13366 {
13367 oappend ("(bad)");
13368 return;
13369 }
13370 names = names_mask;
13371 break;
13372 default:
13373 /* See PR binutils/20893 for a reproducer. */
13374 oappend ("(bad)");
13375 return;
13376 }
13377 break;
13378 case 512:
13379 names = names_zmm;
13380 break;
13381 default:
13382 abort ();
13383 break;
13384 }
13385 oappend (names[reg]);
13386 }
13387
13388 static void
13389 OP_VexR (int bytemode, int sizeflag)
13390 {
13391 if (modrm.mod == 3)
13392 OP_VEX (bytemode, sizeflag);
13393 }
13394
13395 static void
13396 OP_VexW (int bytemode, int sizeflag)
13397 {
13398 OP_VEX (bytemode, sizeflag);
13399
13400 if (vex.w)
13401 {
13402 /* Swap 2nd and 3rd operands. */
13403 strcpy (scratchbuf, op_out[2]);
13404 strcpy (op_out[2], op_out[1]);
13405 strcpy (op_out[1], scratchbuf);
13406 }
13407 }
13408
13409 static void
13410 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13411 {
13412 int reg;
13413 const char **names = names_xmm;
13414
13415 FETCH_DATA (the_info, codep + 1);
13416 reg = *codep++;
13417
13418 if (bytemode != x_mode && bytemode != scalar_mode)
13419 abort ();
13420
13421 reg >>= 4;
13422 if (address_mode != mode_64bit)
13423 reg &= 7;
13424
13425 if (bytemode == x_mode && vex.length == 256)
13426 names = names_ymm;
13427
13428 oappend (names[reg]);
13429
13430 if (vex.w)
13431 {
13432 /* Swap 3rd and 4th operands. */
13433 strcpy (scratchbuf, op_out[3]);
13434 strcpy (op_out[3], op_out[2]);
13435 strcpy (op_out[2], scratchbuf);
13436 }
13437 }
13438
13439 static void
13440 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13441 int sizeflag ATTRIBUTE_UNUSED)
13442 {
13443 scratchbuf[0] = '$';
13444 print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13445 oappend_maybe_intel (scratchbuf);
13446 }
13447
13448 static void
13449 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13450 int sizeflag ATTRIBUTE_UNUSED)
13451 {
13452 unsigned int cmp_type;
13453
13454 if (!vex.evex)
13455 abort ();
13456
13457 FETCH_DATA (the_info, codep + 1);
13458 cmp_type = *codep++ & 0xff;
13459 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13460 If it's the case, print suffix, otherwise - print the immediate. */
13461 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13462 && cmp_type != 3
13463 && cmp_type != 7)
13464 {
13465 char suffix [3];
13466 char *p = mnemonicendp - 2;
13467
13468 /* vpcmp* can have both one- and two-lettered suffix. */
13469 if (p[0] == 'p')
13470 {
13471 p++;
13472 suffix[0] = p[0];
13473 suffix[1] = '\0';
13474 }
13475 else
13476 {
13477 suffix[0] = p[0];
13478 suffix[1] = p[1];
13479 suffix[2] = '\0';
13480 }
13481
13482 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13483 mnemonicendp += simd_cmp_op[cmp_type].len;
13484 }
13485 else
13486 {
13487 /* We have a reserved extension byte. Output it directly. */
13488 scratchbuf[0] = '$';
13489 print_operand_value (scratchbuf + 1, 1, cmp_type);
13490 oappend_maybe_intel (scratchbuf);
13491 scratchbuf[0] = '\0';
13492 }
13493 }
13494
13495 static const struct op xop_cmp_op[] =
13496 {
13497 { STRING_COMMA_LEN ("lt") },
13498 { STRING_COMMA_LEN ("le") },
13499 { STRING_COMMA_LEN ("gt") },
13500 { STRING_COMMA_LEN ("ge") },
13501 { STRING_COMMA_LEN ("eq") },
13502 { STRING_COMMA_LEN ("neq") },
13503 { STRING_COMMA_LEN ("false") },
13504 { STRING_COMMA_LEN ("true") }
13505 };
13506
13507 static void
13508 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13509 int sizeflag ATTRIBUTE_UNUSED)
13510 {
13511 unsigned int cmp_type;
13512
13513 FETCH_DATA (the_info, codep + 1);
13514 cmp_type = *codep++ & 0xff;
13515 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13516 {
13517 char suffix[3];
13518 char *p = mnemonicendp - 2;
13519
13520 /* vpcom* can have both one- and two-lettered suffix. */
13521 if (p[0] == 'm')
13522 {
13523 p++;
13524 suffix[0] = p[0];
13525 suffix[1] = '\0';
13526 }
13527 else
13528 {
13529 suffix[0] = p[0];
13530 suffix[1] = p[1];
13531 suffix[2] = '\0';
13532 }
13533
13534 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13535 mnemonicendp += xop_cmp_op[cmp_type].len;
13536 }
13537 else
13538 {
13539 /* We have a reserved extension byte. Output it directly. */
13540 scratchbuf[0] = '$';
13541 print_operand_value (scratchbuf + 1, 1, cmp_type);
13542 oappend_maybe_intel (scratchbuf);
13543 scratchbuf[0] = '\0';
13544 }
13545 }
13546
13547 static const struct op pclmul_op[] =
13548 {
13549 { STRING_COMMA_LEN ("lql") },
13550 { STRING_COMMA_LEN ("hql") },
13551 { STRING_COMMA_LEN ("lqh") },
13552 { STRING_COMMA_LEN ("hqh") }
13553 };
13554
13555 static void
13556 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13557 int sizeflag ATTRIBUTE_UNUSED)
13558 {
13559 unsigned int pclmul_type;
13560
13561 FETCH_DATA (the_info, codep + 1);
13562 pclmul_type = *codep++ & 0xff;
13563 switch (pclmul_type)
13564 {
13565 case 0x10:
13566 pclmul_type = 2;
13567 break;
13568 case 0x11:
13569 pclmul_type = 3;
13570 break;
13571 default:
13572 break;
13573 }
13574 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13575 {
13576 char suffix [4];
13577 char *p = mnemonicendp - 3;
13578 suffix[0] = p[0];
13579 suffix[1] = p[1];
13580 suffix[2] = p[2];
13581 suffix[3] = '\0';
13582 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13583 mnemonicendp += pclmul_op[pclmul_type].len;
13584 }
13585 else
13586 {
13587 /* We have a reserved extension byte. Output it directly. */
13588 scratchbuf[0] = '$';
13589 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13590 oappend_maybe_intel (scratchbuf);
13591 scratchbuf[0] = '\0';
13592 }
13593 }
13594
13595 static void
13596 MOVSXD_Fixup (int bytemode, int sizeflag)
13597 {
13598 /* Add proper suffix to "movsxd". */
13599 char *p = mnemonicendp;
13600
13601 switch (bytemode)
13602 {
13603 case movsxd_mode:
13604 if (!intel_syntax)
13605 {
13606 USED_REX (REX_W);
13607 if (rex & REX_W)
13608 {
13609 *p++ = 'l';
13610 *p++ = 'q';
13611 break;
13612 }
13613 }
13614
13615 *p++ = 'x';
13616 *p++ = 'd';
13617 break;
13618 default:
13619 oappend (INTERNAL_DISASSEMBLER_ERROR);
13620 break;
13621 }
13622
13623 mnemonicendp = p;
13624 *p = '\0';
13625 OP_E (bytemode, sizeflag);
13626 }
13627
13628 static void
13629 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13630 {
13631 if (modrm.mod == 3 && vex.b)
13632 switch (bytemode)
13633 {
13634 case evex_rounding_64_mode:
13635 if (address_mode != mode_64bit || !vex.w)
13636 {
13637 oappend ("(bad)");
13638 break;
13639 }
13640 /* Fall through. */
13641 case evex_rounding_mode:
13642 oappend (names_rounding[vex.ll]);
13643 break;
13644 case evex_sae_mode:
13645 oappend ("{sae}");
13646 break;
13647 default:
13648 abort ();
13649 break;
13650 }
13651 }