opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_VexR (int, int);
  92 static void OP_VexW (int, int);
  93 static void OP_Rounding (int, int);
  94 static void OP_REG_VexI4 (int, int);
  95 static void OP_VexI4 (int, int);
  96 static void PCLMUL_Fixup (int, int);
  97 static void VPCMP_Fixup (int, int);
  98 static void VPCOM_Fixup (int, int);
  99 static void OP_0f07 (int, int);
 100 static void OP_Monitor (int, int);
 101 static void OP_Mwait (int, int);
 102 static void NOP_Fixup1 (int, int);
 103 static void NOP_Fixup2 (int, int);
 104 static void OP_3DNowSuffix (int, int);
 105 static void CMP_Fixup (int, int);
 106 static void BadOp (void);
 107 static void REP_Fixup (int, int);
 108 static void SEP_Fixup (int, int);
 109 static void BND_Fixup (int, int);
 110 static void NOTRACK_Fixup (int, int);
 111 static void HLE_Fixup1 (int, int);
 112 static void HLE_Fixup2 (int, int);
 113 static void HLE_Fixup3 (int, int);
 114 static void CMPXCHG8B_Fixup (int, int);
 115 static void XMM_Fixup (int, int);
 116 static void FXSAVE_Fixup (int, int);
 117
 118 static void MOVSXD_Fixup (int, int);
 119
 120 static void OP_Mask (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   OPCODES_SIGJMP_BUF bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* Mark parts used in the REX prefix.  When we are testing for
 148    empty prefix (for 8bit register REX extension), just mask it
 149    out.  Otherwise test for REX bit is excuse for existence of REX
 150    only in case value is nonzero.  */
 151 #define USED_REX(value)                                 \
 152   {                                                     \
 153     if (value)                                          \
 154       {                                                 \
 155         if ((rex & value))                              \
 156           rex_used |= (value) | REX_OPCODE;             \
 157       }                                                 \
 158     else                                                \
 159       rex_used |= REX_OPCODE;                           \
 160   }
 161
 162 /* Flags for prefixes which we somehow handled when printing the
 163    current instruction.  */
 164 static int used_prefixes;
 165
 166 /* Flags stored in PREFIXES.  */
 167 #define PREFIX_REPZ 1
 168 #define PREFIX_REPNZ 2
 169 #define PREFIX_LOCK 4
 170 #define PREFIX_CS 8
 171 #define PREFIX_SS 0x10
 172 #define PREFIX_DS 0x20
 173 #define PREFIX_ES 0x40
 174 #define PREFIX_FS 0x80
 175 #define PREFIX_GS 0x100
 176 #define PREFIX_DATA 0x200
 177 #define PREFIX_ADDR 0x400
 178 #define PREFIX_FWAIT 0x800
 179
 180 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 181    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 182    on error.  */
 183 #define FETCH_DATA(info, addr) \
 184   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 185    ? 1 : fetch_data ((info), (addr)))
 186
 187 static int
 188 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 189 {
 190   int status;
 191   struct dis_private *priv = (struct dis_private *) info->private_data;
 192   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 193
 194   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 195     status = (*info->read_memory_func) (start,
 196                                         priv->max_fetched,
 197                                         addr - priv->max_fetched,
 198                                         info);
 199   else
 200     status = -1;
 201   if (status != 0)
 202     {
 203       /* If we did manage to read at least one byte, then
 204          print_insn_i386 will do something sensible.  Otherwise, print
 205          an error.  We do that here because this is where we know
 206          STATUS.  */
 207       if (priv->max_fetched == priv->the_buffer)
 208         (*info->memory_error_func) (status, start, info);
 209       OPCODES_SIGLONGJMP (priv->bailout, 1);
 210     }
 211   else
 212     priv->max_fetched = addr;
 213   return 1;
 214 }
 215
 216 /* Possible values for prefix requirement.  */
 217 #define PREFIX_IGNORED_SHIFT    16
 218 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 219 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 222 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 223
 224 /* Opcode prefixes.  */
 225 #define PREFIX_OPCODE           (PREFIX_REPZ \
 226                                  | PREFIX_REPNZ \
 227                                  | PREFIX_DATA)
 228
 229 /* Prefixes ignored.  */
 230 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 231                                  | PREFIX_IGNORED_REPNZ \
 232                                  | PREFIX_IGNORED_DATA)
 233
 234 #define XX { NULL, 0 }
 235 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 236
 237 #define Eb { OP_E, b_mode }
 238 #define Ebnd { OP_E, bnd_mode }
 239 #define EbS { OP_E, b_swap_mode }
 240 #define EbndS { OP_E, bnd_swap_mode }
 241 #define Ev { OP_E, v_mode }
 242 #define Eva { OP_E, va_mode }
 243 #define Ev_bnd { OP_E, v_bnd_mode }
 244 #define EvS { OP_E, v_swap_mode }
 245 #define Ed { OP_E, d_mode }
 246 #define Edq { OP_E, dq_mode }
 247 #define Edqw { OP_E, dqw_mode }
 248 #define Edqb { OP_E, dqb_mode }
 249 #define Edb { OP_E, db_mode }
 250 #define Edw { OP_E, dw_mode }
 251 #define Edqd { OP_E, dqd_mode }
 252 #define Eq { OP_E, q_mode }
 253 #define indirEv { OP_indirE, indir_v_mode }
 254 #define indirEp { OP_indirE, f_mode }
 255 #define stackEv { OP_E, stack_v_mode }
 256 #define Em { OP_E, m_mode }
 257 #define Ew { OP_E, w_mode }
 258 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 259 #define Ma { OP_M, a_mode }
 260 #define Mb { OP_M, b_mode }
 261 #define Md { OP_M, d_mode }
 262 #define Mo { OP_M, o_mode }
 263 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 264 #define Mq { OP_M, q_mode }
 265 #define Mv { OP_M, v_mode }
 266 #define Mv_bnd { OP_M, v_bndmk_mode }
 267 #define Mx { OP_M, x_mode }
 268 #define Mxmm { OP_M, xmm_mode }
 269 #define Gb { OP_G, b_mode }
 270 #define Gbnd { OP_G, bnd_mode }
 271 #define Gv { OP_G, v_mode }
 272 #define Gd { OP_G, d_mode }
 273 #define Gdq { OP_G, dq_mode }
 274 #define Gm { OP_G, m_mode }
 275 #define Gva { OP_G, va_mode }
 276 #define Gw { OP_G, w_mode }
 277 #define Rm { OP_R, m_mode }
 278 #define Ib { OP_I, b_mode }
 279 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 280 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 281 #define Iv { OP_I, v_mode }
 282 #define sIv { OP_sI, v_mode }
 283 #define Iv64 { OP_I64, v_mode }
 284 #define Id { OP_I, d_mode }
 285 #define Iw { OP_I, w_mode }
 286 #define I1 { OP_I, const_1_mode }
 287 #define Jb { OP_J, b_mode }
 288 #define Jv { OP_J, v_mode }
 289 #define Jdqw { OP_J, dqw_mode }
 290 #define Cm { OP_C, m_mode }
 291 #define Dm { OP_D, m_mode }
 292 #define Td { OP_T, d_mode }
 293 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 294
 295 #define RMeAX { OP_REG, eAX_reg }
 296 #define RMeBX { OP_REG, eBX_reg }
 297 #define RMeCX { OP_REG, eCX_reg }
 298 #define RMeDX { OP_REG, eDX_reg }
 299 #define RMeSP { OP_REG, eSP_reg }
 300 #define RMeBP { OP_REG, eBP_reg }
 301 #define RMeSI { OP_REG, eSI_reg }
 302 #define RMeDI { OP_REG, eDI_reg }
 303 #define RMrAX { OP_REG, rAX_reg }
 304 #define RMrBX { OP_REG, rBX_reg }
 305 #define RMrCX { OP_REG, rCX_reg }
 306 #define RMrDX { OP_REG, rDX_reg }
 307 #define RMrSP { OP_REG, rSP_reg }
 308 #define RMrBP { OP_REG, rBP_reg }
 309 #define RMrSI { OP_REG, rSI_reg }
 310 #define RMrDI { OP_REG, rDI_reg }
 311 #define RMAL { OP_REG, al_reg }
 312 #define RMCL { OP_REG, cl_reg }
 313 #define RMDL { OP_REG, dl_reg }
 314 #define RMBL { OP_REG, bl_reg }
 315 #define RMAH { OP_REG, ah_reg }
 316 #define RMCH { OP_REG, ch_reg }
 317 #define RMDH { OP_REG, dh_reg }
 318 #define RMBH { OP_REG, bh_reg }
 319 #define RMAX { OP_REG, ax_reg }
 320 #define RMDX { OP_REG, dx_reg }
 321
 322 #define eAX { OP_IMREG, eAX_reg }
 323 #define AL { OP_IMREG, al_reg }
 324 #define CL { OP_IMREG, cl_reg }
 325 #define zAX { OP_IMREG, z_mode_ax_reg }
 326 #define indirDX { OP_IMREG, indir_dx_reg }
 327
 328 #define Sw { OP_SEG, w_mode }
 329 #define Sv { OP_SEG, v_mode }
 330 #define Ap { OP_DIR, 0 }
 331 #define Ob { OP_OFF64, b_mode }
 332 #define Ov { OP_OFF64, v_mode }
 333 #define Xb { OP_DSreg, eSI_reg }
 334 #define Xv { OP_DSreg, eSI_reg }
 335 #define Xz { OP_DSreg, eSI_reg }
 336 #define Yb { OP_ESreg, eDI_reg }
 337 #define Yv { OP_ESreg, eDI_reg }
 338 #define DSBX { OP_DSreg, eBX_reg }
 339
 340 #define es { OP_REG, es_reg }
 341 #define ss { OP_REG, ss_reg }
 342 #define cs { OP_REG, cs_reg }
 343 #define ds { OP_REG, ds_reg }
 344 #define fs { OP_REG, fs_reg }
 345 #define gs { OP_REG, gs_reg }
 346
 347 #define MX { OP_MMX, 0 }
 348 #define XM { OP_XMM, 0 }
 349 #define XMScalar { OP_XMM, scalar_mode }
 350 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 351 #define XMM { OP_XMM, xmm_mode }
 352 #define TMM { OP_XMM, tmm_mode }
 353 #define XMxmmq { OP_XMM, xmmq_mode }
 354 #define EM { OP_EM, v_mode }
 355 #define EMS { OP_EM, v_swap_mode }
 356 #define EMd { OP_EM, d_mode }
 357 #define EMx { OP_EM, x_mode }
 358 #define EXbwUnit { OP_EX, bw_unit_mode }
 359 #define EXw { OP_EX, w_mode }
 360 #define EXd { OP_EX, d_mode }
 361 #define EXdS { OP_EX, d_swap_mode }
 362 #define EXq { OP_EX, q_mode }
 363 #define EXqS { OP_EX, q_swap_mode }
 364 #define EXx { OP_EX, x_mode }
 365 #define EXxS { OP_EX, x_swap_mode }
 366 #define EXxmm { OP_EX, xmm_mode }
 367 #define EXymm { OP_EX, ymm_mode }
 368 #define EXtmm { OP_EX, tmm_mode }
 369 #define EXxmmq { OP_EX, xmmq_mode }
 370 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 371 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 372 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 373 #define EXxmm_md { OP_EX, xmm_md_mode }
 374 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 375 #define EXxmmdw { OP_EX, xmmdw_mode }
 376 #define EXxmmqd { OP_EX, xmmqd_mode }
 377 #define EXymmq { OP_EX, ymmq_mode }
 378 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 379 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 380 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 381 #define MS { OP_MS, v_mode }
 382 #define XS { OP_XS, v_mode }
 383 #define EMCq { OP_EMC, q_mode }
 384 #define MXC { OP_MXC, 0 }
 385 #define OPSUF { OP_3DNowSuffix, 0 }
 386 #define SEP { SEP_Fixup, 0 }
 387 #define CMP { CMP_Fixup, 0 }
 388 #define XMM0 { XMM_Fixup, 0 }
 389 #define FXSAVE { FXSAVE_Fixup, 0 }
 390
 391 #define Vex { OP_VEX, vex_mode }
 392 #define VexW { OP_VexW, vex_mode }
 393 #define VexScalar { OP_VEX, vex_scalar_mode }
 394 #define VexScalarR { OP_VexR, vex_scalar_mode }
 395 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 396 #define VexGdq { OP_VEX, dq_mode }
 397 #define VexTmm { OP_VEX, tmm_mode }
 398 #define XMVexI4 { OP_REG_VexI4, x_mode }
 399 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 400 #define VexI4 { OP_VexI4, 0 }
 401 #define PCLMUL { PCLMUL_Fixup, 0 }
 402 #define VPCMP { VPCMP_Fixup, 0 }
 403 #define VPCOM { VPCOM_Fixup, 0 }
 404
 405 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 406 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 407 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 408
 409 #define XMask { OP_Mask, mask_mode }
 410 #define MaskG { OP_G, mask_mode }
 411 #define MaskE { OP_E, mask_mode }
 412 #define MaskBDE { OP_E, mask_bd_mode }
 413 #define MaskVex { OP_VEX, mask_mode }
 414
 415 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 416 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 417 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 418 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 419
 420 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 421
 422 /* Used handle "rep" prefix for string instructions.  */
 423 #define Xbr { REP_Fixup, eSI_reg }
 424 #define Xvr { REP_Fixup, eSI_reg }
 425 #define Ybr { REP_Fixup, eDI_reg }
 426 #define Yvr { REP_Fixup, eDI_reg }
 427 #define Yzr { REP_Fixup, eDI_reg }
 428 #define indirDXr { REP_Fixup, indir_dx_reg }
 429 #define ALr { REP_Fixup, al_reg }
 430 #define eAXr { REP_Fixup, eAX_reg }
 431
 432 /* Used handle HLE prefix for lockable instructions.  */
 433 #define Ebh1 { HLE_Fixup1, b_mode }
 434 #define Evh1 { HLE_Fixup1, v_mode }
 435 #define Ebh2 { HLE_Fixup2, b_mode }
 436 #define Evh2 { HLE_Fixup2, v_mode }
 437 #define Ebh3 { HLE_Fixup3, b_mode }
 438 #define Evh3 { HLE_Fixup3, v_mode }
 439
 440 #define BND { BND_Fixup, 0 }
 441 #define NOTRACK { NOTRACK_Fixup, 0 }
 442
 443 #define cond_jump_flag { NULL, cond_jump_mode }
 444 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 445
 446 /* bits in sizeflag */
 447 #define SUFFIX_ALWAYS 4
 448 #define AFLAG 2
 449 #define DFLAG 1
 450
 451 enum
 452 {
 453   /* byte operand */
 454   b_mode = 1,
 455   /* byte operand with operand swapped */
 456   b_swap_mode,
 457   /* byte operand, sign extend like 'T' suffix */
 458   b_T_mode,
 459   /* operand size depends on prefixes */
 460   v_mode,
 461   /* operand size depends on prefixes with operand swapped */
 462   v_swap_mode,
 463   /* operand size depends on address prefix */
 464   va_mode,
 465   /* word operand */
 466   w_mode,
 467   /* double word operand  */
 468   d_mode,
 469   /* double word operand with operand swapped */
 470   d_swap_mode,
 471   /* quad word operand */
 472   q_mode,
 473   /* quad word operand with operand swapped */
 474   q_swap_mode,
 475   /* ten-byte operand */
 476   t_mode,
 477   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 478      broadcast enabled.  */
 479   x_mode,
 480   /* Similar to x_mode, but with different EVEX mem shifts.  */
 481   evex_x_gscat_mode,
 482   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 483   bw_unit_mode,
 484   /* Similar to x_mode, but with disabled broadcast.  */
 485   evex_x_nobcst_mode,
 486   /* Similar to x_mode, but with operands swapped and disabled broadcast
 487      in EVEX.  */
 488   x_swap_mode,
 489   /* 16-byte XMM operand */
 490   xmm_mode,
 491   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 492      memory operand (depending on vector length).  Broadcast isn't
 493      allowed.  */
 494   xmmq_mode,
 495   /* Same as xmmq_mode, but broadcast is allowed.  */
 496   evex_half_bcst_xmmq_mode,
 497   /* XMM register or byte memory operand */
 498   xmm_mb_mode,
 499   /* XMM register or word memory operand */
 500   xmm_mw_mode,
 501   /* XMM register or double word memory operand */
 502   xmm_md_mode,
 503   /* XMM register or quad word memory operand */
 504   xmm_mq_mode,
 505   /* 16-byte XMM, word, double word or quad word operand.  */
 506   xmmdw_mode,
 507   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 508   xmmqd_mode,
 509   /* 32-byte YMM operand */
 510   ymm_mode,
 511   /* quad word, ymmword or zmmword memory operand.  */
 512   ymmq_mode,
 513   /* 32-byte YMM or 16-byte word operand */
 514   ymmxmm_mode,
 515   /* TMM operand */
 516   tmm_mode,
 517   /* d_mode in 32bit, q_mode in 64bit mode.  */
 518   m_mode,
 519   /* pair of v_mode operands */
 520   a_mode,
 521   cond_jump_mode,
 522   loop_jcxz_mode,
 523   movsxd_mode,
 524   v_bnd_mode,
 525   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 526   v_bndmk_mode,
 527   /* operand size depends on REX prefixes.  */
 528   dq_mode,
 529   /* registers like dq_mode, memory like w_mode, displacements like
 530      v_mode without considering Intel64 ISA.  */
 531   dqw_mode,
 532   /* bounds operand */
 533   bnd_mode,
 534   /* bounds operand with operand swapped */
 535   bnd_swap_mode,
 536   /* 4- or 6-byte pointer operand */
 537   f_mode,
 538   const_1_mode,
 539   /* v_mode for indirect branch opcodes.  */
 540   indir_v_mode,
 541   /* v_mode for stack-related opcodes.  */
 542   stack_v_mode,
 543   /* non-quad operand size depends on prefixes */
 544   z_mode,
 545   /* 16-byte operand */
 546   o_mode,
 547   /* registers like dq_mode, memory like b_mode.  */
 548   dqb_mode,
 549   /* registers like d_mode, memory like b_mode.  */
 550   db_mode,
 551   /* registers like d_mode, memory like w_mode.  */
 552   dw_mode,
 553   /* registers like dq_mode, memory like d_mode.  */
 554   dqd_mode,
 555   /* normal vex mode */
 556   vex_mode,
 557
 558   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 559   vex_vsib_d_w_dq_mode,
 560   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 561   vex_vsib_d_w_d_mode,
 562   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 563   vex_vsib_q_w_dq_mode,
 564   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 565   vex_vsib_q_w_d_mode,
 566   /* mandatory non-vector SIB.  */
 567   vex_sibmem_mode,
 568
 569   /* scalar, ignore vector length.  */
 570   scalar_mode,
 571   /* like vex_mode, ignore vector length.  */
 572   vex_scalar_mode,
 573   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 574   vex_scalar_w_dq_mode,
 575
 576   /* Static rounding.  */
 577   evex_rounding_mode,
 578   /* Static rounding, 64-bit mode only.  */
 579   evex_rounding_64_mode,
 580   /* Supress all exceptions.  */
 581   evex_sae_mode,
 582
 583   /* Mask register operand.  */
 584   mask_mode,
 585   /* Mask register operand.  */
 586   mask_bd_mode,
 587
 588   es_reg,
 589   cs_reg,
 590   ss_reg,
 591   ds_reg,
 592   fs_reg,
 593   gs_reg,
 594
 595   eAX_reg,
 596   eCX_reg,
 597   eDX_reg,
 598   eBX_reg,
 599   eSP_reg,
 600   eBP_reg,
 601   eSI_reg,
 602   eDI_reg,
 603
 604   al_reg,
 605   cl_reg,
 606   dl_reg,
 607   bl_reg,
 608   ah_reg,
 609   ch_reg,
 610   dh_reg,
 611   bh_reg,
 612
 613   ax_reg,
 614   cx_reg,
 615   dx_reg,
 616   bx_reg,
 617   sp_reg,
 618   bp_reg,
 619   si_reg,
 620   di_reg,
 621
 622   rAX_reg,
 623   rCX_reg,
 624   rDX_reg,
 625   rBX_reg,
 626   rSP_reg,
 627   rBP_reg,
 628   rSI_reg,
 629   rDI_reg,
 630
 631   z_mode_ax_reg,
 632   indir_dx_reg
 633 };
 634
 635 enum
 636 {
 637   FLOATCODE = 1,
 638   USE_REG_TABLE,
 639   USE_MOD_TABLE,
 640   USE_RM_TABLE,
 641   USE_PREFIX_TABLE,
 642   USE_X86_64_TABLE,
 643   USE_3BYTE_TABLE,
 644   USE_XOP_8F_TABLE,
 645   USE_VEX_C4_TABLE,
 646   USE_VEX_C5_TABLE,
 647   USE_VEX_LEN_TABLE,
 648   USE_VEX_W_TABLE,
 649   USE_EVEX_TABLE,
 650   USE_EVEX_LEN_TABLE
 651 };
 652
 653 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 654
 655 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 656 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 657 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 658 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 659 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 660 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 661 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 662 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 663 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 664 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 665 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 666 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 667 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 668 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 669 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 670 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 671
 672 enum
 673 {
 674   REG_80 = 0,
 675   REG_81,
 676   REG_83,
 677   REG_8F,
 678   REG_C0,
 679   REG_C1,
 680   REG_C6,
 681   REG_C7,
 682   REG_D0,
 683   REG_D1,
 684   REG_D2,
 685   REG_D3,
 686   REG_F6,
 687   REG_F7,
 688   REG_FE,
 689   REG_FF,
 690   REG_0F00,
 691   REG_0F01,
 692   REG_0F0D,
 693   REG_0F18,
 694   REG_0F1C_P_0_MOD_0,
 695   REG_0F1E_P_1_MOD_3,
 696   REG_0F71,
 697   REG_0F72,
 698   REG_0F73,
 699   REG_0FA6,
 700   REG_0FA7,
 701   REG_0FAE,
 702   REG_0FBA,
 703   REG_0FC7,
 704   REG_VEX_0F71,
 705   REG_VEX_0F72,
 706   REG_VEX_0F73,
 707   REG_VEX_0FAE,
 708   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 709   REG_VEX_0F38F3,
 710
 711   REG_0FXOP_09_01_L_0,
 712   REG_0FXOP_09_02_L_0,
 713   REG_0FXOP_09_12_M_1_L_0,
 714   REG_0FXOP_0A_12_L_0,
 715
 716   REG_EVEX_0F71,
 717   REG_EVEX_0F72,
 718   REG_EVEX_0F73,
 719   REG_EVEX_0F38C6,
 720   REG_EVEX_0F38C7
 721 };
 722
 723 enum
 724 {
 725   MOD_8D = 0,
 726   MOD_C6_REG_7,
 727   MOD_C7_REG_7,
 728   MOD_FF_REG_3,
 729   MOD_FF_REG_5,
 730   MOD_0F01_REG_0,
 731   MOD_0F01_REG_1,
 732   MOD_0F01_REG_2,
 733   MOD_0F01_REG_3,
 734   MOD_0F01_REG_5,
 735   MOD_0F01_REG_7,
 736   MOD_0F12_PREFIX_0,
 737   MOD_0F12_PREFIX_2,
 738   MOD_0F13,
 739   MOD_0F16_PREFIX_0,
 740   MOD_0F16_PREFIX_2,
 741   MOD_0F17,
 742   MOD_0F18_REG_0,
 743   MOD_0F18_REG_1,
 744   MOD_0F18_REG_2,
 745   MOD_0F18_REG_3,
 746   MOD_0F18_REG_4,
 747   MOD_0F18_REG_5,
 748   MOD_0F18_REG_6,
 749   MOD_0F18_REG_7,
 750   MOD_0F1A_PREFIX_0,
 751   MOD_0F1B_PREFIX_0,
 752   MOD_0F1B_PREFIX_1,
 753   MOD_0F1C_PREFIX_0,
 754   MOD_0F1E_PREFIX_1,
 755   MOD_0F24,
 756   MOD_0F26,
 757   MOD_0F2B_PREFIX_0,
 758   MOD_0F2B_PREFIX_1,
 759   MOD_0F2B_PREFIX_2,
 760   MOD_0F2B_PREFIX_3,
 761   MOD_0F50,
 762   MOD_0F71_REG_2,
 763   MOD_0F71_REG_4,
 764   MOD_0F71_REG_6,
 765   MOD_0F72_REG_2,
 766   MOD_0F72_REG_4,
 767   MOD_0F72_REG_6,
 768   MOD_0F73_REG_2,
 769   MOD_0F73_REG_3,
 770   MOD_0F73_REG_6,
 771   MOD_0F73_REG_7,
 772   MOD_0FAE_REG_0,
 773   MOD_0FAE_REG_1,
 774   MOD_0FAE_REG_2,
 775   MOD_0FAE_REG_3,
 776   MOD_0FAE_REG_4,
 777   MOD_0FAE_REG_5,
 778   MOD_0FAE_REG_6,
 779   MOD_0FAE_REG_7,
 780   MOD_0FB2,
 781   MOD_0FB4,
 782   MOD_0FB5,
 783   MOD_0FC3,
 784   MOD_0FC7_REG_3,
 785   MOD_0FC7_REG_4,
 786   MOD_0FC7_REG_5,
 787   MOD_0FC7_REG_6,
 788   MOD_0FC7_REG_7,
 789   MOD_0FD7,
 790   MOD_0FE7_PREFIX_2,
 791   MOD_0FF0_PREFIX_3,
 792   MOD_0F382A,
 793   MOD_VEX_0F3849_X86_64_P_0_W_0,
 794   MOD_VEX_0F3849_X86_64_P_2_W_0,
 795   MOD_VEX_0F3849_X86_64_P_3_W_0,
 796   MOD_VEX_0F384B_X86_64_P_1_W_0,
 797   MOD_VEX_0F384B_X86_64_P_2_W_0,
 798   MOD_VEX_0F384B_X86_64_P_3_W_0,
 799   MOD_VEX_0F385C_X86_64_P_1_W_0,
 800   MOD_VEX_0F385E_X86_64_P_0_W_0,
 801   MOD_VEX_0F385E_X86_64_P_1_W_0,
 802   MOD_VEX_0F385E_X86_64_P_2_W_0,
 803   MOD_VEX_0F385E_X86_64_P_3_W_0,
 804   MOD_0F38F5,
 805   MOD_0F38F6_PREFIX_0,
 806   MOD_0F38F8_PREFIX_1,
 807   MOD_0F38F8_PREFIX_2,
 808   MOD_0F38F8_PREFIX_3,
 809   MOD_0F38F9,
 810   MOD_62_32BIT,
 811   MOD_C4_32BIT,
 812   MOD_C5_32BIT,
 813   MOD_VEX_0F12_PREFIX_0,
 814   MOD_VEX_0F12_PREFIX_2,
 815   MOD_VEX_0F13,
 816   MOD_VEX_0F16_PREFIX_0,
 817   MOD_VEX_0F16_PREFIX_2,
 818   MOD_VEX_0F17,
 819   MOD_VEX_0F2B,
 820   MOD_VEX_W_0_0F41_P_0_LEN_1,
 821   MOD_VEX_W_1_0F41_P_0_LEN_1,
 822   MOD_VEX_W_0_0F41_P_2_LEN_1,
 823   MOD_VEX_W_1_0F41_P_2_LEN_1,
 824   MOD_VEX_W_0_0F42_P_0_LEN_1,
 825   MOD_VEX_W_1_0F42_P_0_LEN_1,
 826   MOD_VEX_W_0_0F42_P_2_LEN_1,
 827   MOD_VEX_W_1_0F42_P_2_LEN_1,
 828   MOD_VEX_W_0_0F44_P_0_LEN_1,
 829   MOD_VEX_W_1_0F44_P_0_LEN_1,
 830   MOD_VEX_W_0_0F44_P_2_LEN_1,
 831   MOD_VEX_W_1_0F44_P_2_LEN_1,
 832   MOD_VEX_W_0_0F45_P_0_LEN_1,
 833   MOD_VEX_W_1_0F45_P_0_LEN_1,
 834   MOD_VEX_W_0_0F45_P_2_LEN_1,
 835   MOD_VEX_W_1_0F45_P_2_LEN_1,
 836   MOD_VEX_W_0_0F46_P_0_LEN_1,
 837   MOD_VEX_W_1_0F46_P_0_LEN_1,
 838   MOD_VEX_W_0_0F46_P_2_LEN_1,
 839   MOD_VEX_W_1_0F46_P_2_LEN_1,
 840   MOD_VEX_W_0_0F47_P_0_LEN_1,
 841   MOD_VEX_W_1_0F47_P_0_LEN_1,
 842   MOD_VEX_W_0_0F47_P_2_LEN_1,
 843   MOD_VEX_W_1_0F47_P_2_LEN_1,
 844   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 845   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 846   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 847   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 848   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 849   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 850   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 851   MOD_VEX_0F50,
 852   MOD_VEX_0F71_REG_2,
 853   MOD_VEX_0F71_REG_4,
 854   MOD_VEX_0F71_REG_6,
 855   MOD_VEX_0F72_REG_2,
 856   MOD_VEX_0F72_REG_4,
 857   MOD_VEX_0F72_REG_6,
 858   MOD_VEX_0F73_REG_2,
 859   MOD_VEX_0F73_REG_3,
 860   MOD_VEX_0F73_REG_6,
 861   MOD_VEX_0F73_REG_7,
 862   MOD_VEX_W_0_0F91_P_0_LEN_0,
 863   MOD_VEX_W_1_0F91_P_0_LEN_0,
 864   MOD_VEX_W_0_0F91_P_2_LEN_0,
 865   MOD_VEX_W_1_0F91_P_2_LEN_0,
 866   MOD_VEX_W_0_0F92_P_0_LEN_0,
 867   MOD_VEX_W_0_0F92_P_2_LEN_0,
 868   MOD_VEX_0F92_P_3_LEN_0,
 869   MOD_VEX_W_0_0F93_P_0_LEN_0,
 870   MOD_VEX_W_0_0F93_P_2_LEN_0,
 871   MOD_VEX_0F93_P_3_LEN_0,
 872   MOD_VEX_W_0_0F98_P_0_LEN_0,
 873   MOD_VEX_W_1_0F98_P_0_LEN_0,
 874   MOD_VEX_W_0_0F98_P_2_LEN_0,
 875   MOD_VEX_W_1_0F98_P_2_LEN_0,
 876   MOD_VEX_W_0_0F99_P_0_LEN_0,
 877   MOD_VEX_W_1_0F99_P_0_LEN_0,
 878   MOD_VEX_W_0_0F99_P_2_LEN_0,
 879   MOD_VEX_W_1_0F99_P_2_LEN_0,
 880   MOD_VEX_0FAE_REG_2,
 881   MOD_VEX_0FAE_REG_3,
 882   MOD_VEX_0FD7,
 883   MOD_VEX_0FE7,
 884   MOD_VEX_0FF0_PREFIX_3,
 885   MOD_VEX_0F381A,
 886   MOD_VEX_0F382A,
 887   MOD_VEX_0F382C,
 888   MOD_VEX_0F382D,
 889   MOD_VEX_0F382E,
 890   MOD_VEX_0F382F,
 891   MOD_VEX_0F385A,
 892   MOD_VEX_0F388C,
 893   MOD_VEX_0F388E,
 894   MOD_VEX_0F3A30_L_0,
 895   MOD_VEX_0F3A31_L_0,
 896   MOD_VEX_0F3A32_L_0,
 897   MOD_VEX_0F3A33_L_0,
 898
 899   MOD_VEX_0FXOP_09_12,
 900
 901   MOD_EVEX_0F12_PREFIX_0,
 902   MOD_EVEX_0F12_PREFIX_2,
 903   MOD_EVEX_0F13,
 904   MOD_EVEX_0F16_PREFIX_0,
 905   MOD_EVEX_0F16_PREFIX_2,
 906   MOD_EVEX_0F17,
 907   MOD_EVEX_0F2B,
 908   MOD_EVEX_0F381A_W_0,
 909   MOD_EVEX_0F381A_W_1,
 910   MOD_EVEX_0F381B_W_0,
 911   MOD_EVEX_0F381B_W_1,
 912   MOD_EVEX_0F3828_P_1,
 913   MOD_EVEX_0F382A_P_1_W_1,
 914   MOD_EVEX_0F3838_P_1,
 915   MOD_EVEX_0F383A_P_1_W_0,
 916   MOD_EVEX_0F385A_W_0,
 917   MOD_EVEX_0F385A_W_1,
 918   MOD_EVEX_0F385B_W_0,
 919   MOD_EVEX_0F385B_W_1,
 920   MOD_EVEX_0F387A_W_0,
 921   MOD_EVEX_0F387B_W_0,
 922   MOD_EVEX_0F387C,
 923   MOD_EVEX_0F38C6_REG_1,
 924   MOD_EVEX_0F38C6_REG_2,
 925   MOD_EVEX_0F38C6_REG_5,
 926   MOD_EVEX_0F38C6_REG_6,
 927   MOD_EVEX_0F38C7_REG_1,
 928   MOD_EVEX_0F38C7_REG_2,
 929   MOD_EVEX_0F38C7_REG_5,
 930   MOD_EVEX_0F38C7_REG_6
 931 };
 932
 933 enum
 934 {
 935   RM_C6_REG_7 = 0,
 936   RM_C7_REG_7,
 937   RM_0F01_REG_0,
 938   RM_0F01_REG_1,
 939   RM_0F01_REG_2,
 940   RM_0F01_REG_3,
 941   RM_0F01_REG_5_MOD_3,
 942   RM_0F01_REG_7_MOD_3,
 943   RM_0F1E_P_1_MOD_3_REG_7,
 944   RM_0FAE_REG_6_MOD_3_P_0,
 945   RM_0FAE_REG_7_MOD_3,
 946   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 947 };
 948
 949 enum
 950 {
 951   PREFIX_90 = 0,
 952   PREFIX_0F01_REG_3_RM_1,
 953   PREFIX_0F01_REG_5_MOD_0,
 954   PREFIX_0F01_REG_5_MOD_3_RM_0,
 955   PREFIX_0F01_REG_5_MOD_3_RM_1,
 956   PREFIX_0F01_REG_5_MOD_3_RM_2,
 957   PREFIX_0F01_REG_7_MOD_3_RM_2,
 958   PREFIX_0F09,
 959   PREFIX_0F10,
 960   PREFIX_0F11,
 961   PREFIX_0F12,
 962   PREFIX_0F16,
 963   PREFIX_0F1A,
 964   PREFIX_0F1B,
 965   PREFIX_0F1C,
 966   PREFIX_0F1E,
 967   PREFIX_0F2A,
 968   PREFIX_0F2B,
 969   PREFIX_0F2C,
 970   PREFIX_0F2D,
 971   PREFIX_0F2E,
 972   PREFIX_0F2F,
 973   PREFIX_0F51,
 974   PREFIX_0F52,
 975   PREFIX_0F53,
 976   PREFIX_0F58,
 977   PREFIX_0F59,
 978   PREFIX_0F5A,
 979   PREFIX_0F5B,
 980   PREFIX_0F5C,
 981   PREFIX_0F5D,
 982   PREFIX_0F5E,
 983   PREFIX_0F5F,
 984   PREFIX_0F60,
 985   PREFIX_0F61,
 986   PREFIX_0F62,
 987   PREFIX_0F6F,
 988   PREFIX_0F70,
 989   PREFIX_0F78,
 990   PREFIX_0F79,
 991   PREFIX_0F7C,
 992   PREFIX_0F7D,
 993   PREFIX_0F7E,
 994   PREFIX_0F7F,
 995   PREFIX_0FAE_REG_0_MOD_3,
 996   PREFIX_0FAE_REG_1_MOD_3,
 997   PREFIX_0FAE_REG_2_MOD_3,
 998   PREFIX_0FAE_REG_3_MOD_3,
 999   PREFIX_0FAE_REG_4_MOD_0,
1000   PREFIX_0FAE_REG_4_MOD_3,
1001   PREFIX_0FAE_REG_5_MOD_3,
1002   PREFIX_0FAE_REG_6_MOD_0,
1003   PREFIX_0FAE_REG_6_MOD_3,
1004   PREFIX_0FAE_REG_7_MOD_0,
1005   PREFIX_0FB8,
1006   PREFIX_0FBC,
1007   PREFIX_0FBD,
1008   PREFIX_0FC2,
1009   PREFIX_0FC7_REG_6_MOD_0,
1010   PREFIX_0FC7_REG_6_MOD_3,
1011   PREFIX_0FC7_REG_7_MOD_3,
1012   PREFIX_0FD0,
1013   PREFIX_0FD6,
1014   PREFIX_0FE6,
1015   PREFIX_0FE7,
1016   PREFIX_0FF0,
1017   PREFIX_0FF7,
1018   PREFIX_0F38F0,
1019   PREFIX_0F38F1,
1020   PREFIX_0F38F6,
1021   PREFIX_0F38F8,
1022   PREFIX_VEX_0F10,
1023   PREFIX_VEX_0F11,
1024   PREFIX_VEX_0F12,
1025   PREFIX_VEX_0F16,
1026   PREFIX_VEX_0F2A,
1027   PREFIX_VEX_0F2C,
1028   PREFIX_VEX_0F2D,
1029   PREFIX_VEX_0F2E,
1030   PREFIX_VEX_0F2F,
1031   PREFIX_VEX_0F41,
1032   PREFIX_VEX_0F42,
1033   PREFIX_VEX_0F44,
1034   PREFIX_VEX_0F45,
1035   PREFIX_VEX_0F46,
1036   PREFIX_VEX_0F47,
1037   PREFIX_VEX_0F4A,
1038   PREFIX_VEX_0F4B,
1039   PREFIX_VEX_0F51,
1040   PREFIX_VEX_0F52,
1041   PREFIX_VEX_0F53,
1042   PREFIX_VEX_0F58,
1043   PREFIX_VEX_0F59,
1044   PREFIX_VEX_0F5A,
1045   PREFIX_VEX_0F5B,
1046   PREFIX_VEX_0F5C,
1047   PREFIX_VEX_0F5D,
1048   PREFIX_VEX_0F5E,
1049   PREFIX_VEX_0F5F,
1050   PREFIX_VEX_0F6F,
1051   PREFIX_VEX_0F70,
1052   PREFIX_VEX_0F7C,
1053   PREFIX_VEX_0F7D,
1054   PREFIX_VEX_0F7E,
1055   PREFIX_VEX_0F7F,
1056   PREFIX_VEX_0F90,
1057   PREFIX_VEX_0F91,
1058   PREFIX_VEX_0F92,
1059   PREFIX_VEX_0F93,
1060   PREFIX_VEX_0F98,
1061   PREFIX_VEX_0F99,
1062   PREFIX_VEX_0FC2,
1063   PREFIX_VEX_0FD0,
1064   PREFIX_VEX_0FE6,
1065   PREFIX_VEX_0FF0,
1066   PREFIX_VEX_0F3849_X86_64,
1067   PREFIX_VEX_0F384B_X86_64,
1068   PREFIX_VEX_0F385C_X86_64,
1069   PREFIX_VEX_0F385E_X86_64,
1070   PREFIX_VEX_0F38F5,
1071   PREFIX_VEX_0F38F6,
1072   PREFIX_VEX_0F38F7,
1073   PREFIX_VEX_0F3AF0,
1074
1075   PREFIX_EVEX_0F10,
1076   PREFIX_EVEX_0F11,
1077   PREFIX_EVEX_0F12,
1078   PREFIX_EVEX_0F16,
1079   PREFIX_EVEX_0F2A,
1080   PREFIX_EVEX_0F51,
1081   PREFIX_EVEX_0F58,
1082   PREFIX_EVEX_0F59,
1083   PREFIX_EVEX_0F5A,
1084   PREFIX_EVEX_0F5B,
1085   PREFIX_EVEX_0F5C,
1086   PREFIX_EVEX_0F5D,
1087   PREFIX_EVEX_0F5E,
1088   PREFIX_EVEX_0F5F,
1089   PREFIX_EVEX_0F6F,
1090   PREFIX_EVEX_0F70,
1091   PREFIX_EVEX_0F78,
1092   PREFIX_EVEX_0F79,
1093   PREFIX_EVEX_0F7A,
1094   PREFIX_EVEX_0F7B,
1095   PREFIX_EVEX_0F7E,
1096   PREFIX_EVEX_0F7F,
1097   PREFIX_EVEX_0FC2,
1098   PREFIX_EVEX_0FE6,
1099   PREFIX_EVEX_0F3810,
1100   PREFIX_EVEX_0F3811,
1101   PREFIX_EVEX_0F3812,
1102   PREFIX_EVEX_0F3813,
1103   PREFIX_EVEX_0F3814,
1104   PREFIX_EVEX_0F3815,
1105   PREFIX_EVEX_0F3820,
1106   PREFIX_EVEX_0F3821,
1107   PREFIX_EVEX_0F3822,
1108   PREFIX_EVEX_0F3823,
1109   PREFIX_EVEX_0F3824,
1110   PREFIX_EVEX_0F3825,
1111   PREFIX_EVEX_0F3826,
1112   PREFIX_EVEX_0F3827,
1113   PREFIX_EVEX_0F3828,
1114   PREFIX_EVEX_0F3829,
1115   PREFIX_EVEX_0F382A,
1116   PREFIX_EVEX_0F3830,
1117   PREFIX_EVEX_0F3831,
1118   PREFIX_EVEX_0F3832,
1119   PREFIX_EVEX_0F3833,
1120   PREFIX_EVEX_0F3834,
1121   PREFIX_EVEX_0F3835,
1122   PREFIX_EVEX_0F3838,
1123   PREFIX_EVEX_0F3839,
1124   PREFIX_EVEX_0F383A,
1125   PREFIX_EVEX_0F3852,
1126   PREFIX_EVEX_0F3853,
1127   PREFIX_EVEX_0F3868,
1128   PREFIX_EVEX_0F3872,
1129   PREFIX_EVEX_0F389A,
1130   PREFIX_EVEX_0F389B,
1131   PREFIX_EVEX_0F38AA,
1132   PREFIX_EVEX_0F38AB,
1133 };
1134
1135 enum
1136 {
1137   X86_64_06 = 0,
1138   X86_64_07,
1139   X86_64_0E,
1140   X86_64_16,
1141   X86_64_17,
1142   X86_64_1E,
1143   X86_64_1F,
1144   X86_64_27,
1145   X86_64_2F,
1146   X86_64_37,
1147   X86_64_3F,
1148   X86_64_60,
1149   X86_64_61,
1150   X86_64_62,
1151   X86_64_63,
1152   X86_64_6D,
1153   X86_64_6F,
1154   X86_64_82,
1155   X86_64_9A,
1156   X86_64_C2,
1157   X86_64_C3,
1158   X86_64_C4,
1159   X86_64_C5,
1160   X86_64_CE,
1161   X86_64_D4,
1162   X86_64_D5,
1163   X86_64_E8,
1164   X86_64_E9,
1165   X86_64_EA,
1166   X86_64_0F01_REG_0,
1167   X86_64_0F01_REG_1,
1168   X86_64_0F01_REG_2,
1169   X86_64_0F01_REG_3,
1170   X86_64_VEX_0F3849,
1171   X86_64_VEX_0F384B,
1172   X86_64_VEX_0F385C,
1173   X86_64_VEX_0F385E
1174 };
1175
1176 enum
1177 {
1178   THREE_BYTE_0F38 = 0,
1179   THREE_BYTE_0F3A
1180 };
1181
1182 enum
1183 {
1184   XOP_08 = 0,
1185   XOP_09,
1186   XOP_0A
1187 };
1188
1189 enum
1190 {
1191   VEX_0F = 0,
1192   VEX_0F38,
1193   VEX_0F3A
1194 };
1195
1196 enum
1197 {
1198   EVEX_0F = 0,
1199   EVEX_0F38,
1200   EVEX_0F3A
1201 };
1202
1203 enum
1204 {
1205   VEX_LEN_0F12_P_0_M_0 = 0,
1206   VEX_LEN_0F12_P_0_M_1,
1207 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1208   VEX_LEN_0F13_M_0,
1209   VEX_LEN_0F16_P_0_M_0,
1210   VEX_LEN_0F16_P_0_M_1,
1211 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1212   VEX_LEN_0F17_M_0,
1213   VEX_LEN_0F41_P_0,
1214   VEX_LEN_0F41_P_2,
1215   VEX_LEN_0F42_P_0,
1216   VEX_LEN_0F42_P_2,
1217   VEX_LEN_0F44_P_0,
1218   VEX_LEN_0F44_P_2,
1219   VEX_LEN_0F45_P_0,
1220   VEX_LEN_0F45_P_2,
1221   VEX_LEN_0F46_P_0,
1222   VEX_LEN_0F46_P_2,
1223   VEX_LEN_0F47_P_0,
1224   VEX_LEN_0F47_P_2,
1225   VEX_LEN_0F4A_P_0,
1226   VEX_LEN_0F4A_P_2,
1227   VEX_LEN_0F4B_P_0,
1228   VEX_LEN_0F4B_P_2,
1229   VEX_LEN_0F6E,
1230   VEX_LEN_0F77,
1231   VEX_LEN_0F7E_P_1,
1232   VEX_LEN_0F7E_P_2,
1233   VEX_LEN_0F90_P_0,
1234   VEX_LEN_0F90_P_2,
1235   VEX_LEN_0F91_P_0,
1236   VEX_LEN_0F91_P_2,
1237   VEX_LEN_0F92_P_0,
1238   VEX_LEN_0F92_P_2,
1239   VEX_LEN_0F92_P_3,
1240   VEX_LEN_0F93_P_0,
1241   VEX_LEN_0F93_P_2,
1242   VEX_LEN_0F93_P_3,
1243   VEX_LEN_0F98_P_0,
1244   VEX_LEN_0F98_P_2,
1245   VEX_LEN_0F99_P_0,
1246   VEX_LEN_0F99_P_2,
1247   VEX_LEN_0FAE_R_2_M_0,
1248   VEX_LEN_0FAE_R_3_M_0,
1249   VEX_LEN_0FC4,
1250   VEX_LEN_0FC5,
1251   VEX_LEN_0FD6,
1252   VEX_LEN_0FF7,
1253   VEX_LEN_0F3816,
1254   VEX_LEN_0F3819,
1255   VEX_LEN_0F381A_M_0,
1256   VEX_LEN_0F3836,
1257   VEX_LEN_0F3841,
1258   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1259   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1260   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1261   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1262   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1263   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1264   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1265   VEX_LEN_0F385A_M_0,
1266   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1267   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1268   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1269   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1270   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1271   VEX_LEN_0F38DB,
1272   VEX_LEN_0F38F2,
1273   VEX_LEN_0F38F3_R_1,
1274   VEX_LEN_0F38F3_R_2,
1275   VEX_LEN_0F38F3_R_3,
1276   VEX_LEN_0F38F5_P_0,
1277   VEX_LEN_0F38F5_P_1,
1278   VEX_LEN_0F38F5_P_3,
1279   VEX_LEN_0F38F6_P_3,
1280   VEX_LEN_0F38F7_P_0,
1281   VEX_LEN_0F38F7_P_1,
1282   VEX_LEN_0F38F7_P_2,
1283   VEX_LEN_0F38F7_P_3,
1284   VEX_LEN_0F3A00,
1285   VEX_LEN_0F3A01,
1286   VEX_LEN_0F3A06,
1287   VEX_LEN_0F3A14,
1288   VEX_LEN_0F3A15,
1289   VEX_LEN_0F3A16,
1290   VEX_LEN_0F3A17,
1291   VEX_LEN_0F3A18,
1292   VEX_LEN_0F3A19,
1293   VEX_LEN_0F3A20,
1294   VEX_LEN_0F3A21,
1295   VEX_LEN_0F3A22,
1296   VEX_LEN_0F3A30,
1297   VEX_LEN_0F3A31,
1298   VEX_LEN_0F3A32,
1299   VEX_LEN_0F3A33,
1300   VEX_LEN_0F3A38,
1301   VEX_LEN_0F3A39,
1302   VEX_LEN_0F3A41,
1303   VEX_LEN_0F3A46,
1304   VEX_LEN_0F3A60,
1305   VEX_LEN_0F3A61,
1306   VEX_LEN_0F3A62,
1307   VEX_LEN_0F3A63,
1308   VEX_LEN_0F3ADF,
1309   VEX_LEN_0F3AF0_P_3,
1310   VEX_LEN_0FXOP_08_85,
1311   VEX_LEN_0FXOP_08_86,
1312   VEX_LEN_0FXOP_08_87,
1313   VEX_LEN_0FXOP_08_8E,
1314   VEX_LEN_0FXOP_08_8F,
1315   VEX_LEN_0FXOP_08_95,
1316   VEX_LEN_0FXOP_08_96,
1317   VEX_LEN_0FXOP_08_97,
1318   VEX_LEN_0FXOP_08_9E,
1319   VEX_LEN_0FXOP_08_9F,
1320   VEX_LEN_0FXOP_08_A3,
1321   VEX_LEN_0FXOP_08_A6,
1322   VEX_LEN_0FXOP_08_B6,
1323   VEX_LEN_0FXOP_08_C0,
1324   VEX_LEN_0FXOP_08_C1,
1325   VEX_LEN_0FXOP_08_C2,
1326   VEX_LEN_0FXOP_08_C3,
1327   VEX_LEN_0FXOP_08_CC,
1328   VEX_LEN_0FXOP_08_CD,
1329   VEX_LEN_0FXOP_08_CE,
1330   VEX_LEN_0FXOP_08_CF,
1331   VEX_LEN_0FXOP_08_EC,
1332   VEX_LEN_0FXOP_08_ED,
1333   VEX_LEN_0FXOP_08_EE,
1334   VEX_LEN_0FXOP_08_EF,
1335   VEX_LEN_0FXOP_09_01,
1336   VEX_LEN_0FXOP_09_02,
1337   VEX_LEN_0FXOP_09_12_M_1,
1338   VEX_LEN_0FXOP_09_82_W_0,
1339   VEX_LEN_0FXOP_09_83_W_0,
1340   VEX_LEN_0FXOP_09_90,
1341   VEX_LEN_0FXOP_09_91,
1342   VEX_LEN_0FXOP_09_92,
1343   VEX_LEN_0FXOP_09_93,
1344   VEX_LEN_0FXOP_09_94,
1345   VEX_LEN_0FXOP_09_95,
1346   VEX_LEN_0FXOP_09_96,
1347   VEX_LEN_0FXOP_09_97,
1348   VEX_LEN_0FXOP_09_98,
1349   VEX_LEN_0FXOP_09_99,
1350   VEX_LEN_0FXOP_09_9A,
1351   VEX_LEN_0FXOP_09_9B,
1352   VEX_LEN_0FXOP_09_C1,
1353   VEX_LEN_0FXOP_09_C2,
1354   VEX_LEN_0FXOP_09_C3,
1355   VEX_LEN_0FXOP_09_C6,
1356   VEX_LEN_0FXOP_09_C7,
1357   VEX_LEN_0FXOP_09_CB,
1358   VEX_LEN_0FXOP_09_D1,
1359   VEX_LEN_0FXOP_09_D2,
1360   VEX_LEN_0FXOP_09_D3,
1361   VEX_LEN_0FXOP_09_D6,
1362   VEX_LEN_0FXOP_09_D7,
1363   VEX_LEN_0FXOP_09_DB,
1364   VEX_LEN_0FXOP_09_E1,
1365   VEX_LEN_0FXOP_09_E2,
1366   VEX_LEN_0FXOP_09_E3,
1367   VEX_LEN_0FXOP_0A_12,
1368 };
1369
1370 enum
1371 {
1372   EVEX_LEN_0F6E = 0,
1373   EVEX_LEN_0F7E_P_1,
1374   EVEX_LEN_0F7E_P_2,
1375   EVEX_LEN_0FC4,
1376   EVEX_LEN_0FC5,
1377   EVEX_LEN_0FD6,
1378   EVEX_LEN_0F3816,
1379   EVEX_LEN_0F3819_W_0,
1380   EVEX_LEN_0F3819_W_1,
1381   EVEX_LEN_0F381A_W_0_M_0,
1382   EVEX_LEN_0F381A_W_1_M_0,
1383   EVEX_LEN_0F381B_W_0_M_0,
1384   EVEX_LEN_0F381B_W_1_M_0,
1385   EVEX_LEN_0F3836,
1386   EVEX_LEN_0F385A_W_0_M_0,
1387   EVEX_LEN_0F385A_W_1_M_0,
1388   EVEX_LEN_0F385B_W_0_M_0,
1389   EVEX_LEN_0F385B_W_1_M_0,
1390   EVEX_LEN_0F38C6_R_1_M_0,
1391   EVEX_LEN_0F38C6_R_2_M_0,
1392   EVEX_LEN_0F38C6_R_5_M_0,
1393   EVEX_LEN_0F38C6_R_6_M_0,
1394   EVEX_LEN_0F38C7_R_1_M_0_W_0,
1395   EVEX_LEN_0F38C7_R_1_M_0_W_1,
1396   EVEX_LEN_0F38C7_R_2_M_0_W_0,
1397   EVEX_LEN_0F38C7_R_2_M_0_W_1,
1398   EVEX_LEN_0F38C7_R_5_M_0_W_0,
1399   EVEX_LEN_0F38C7_R_5_M_0_W_1,
1400   EVEX_LEN_0F38C7_R_6_M_0_W_0,
1401   EVEX_LEN_0F38C7_R_6_M_0_W_1,
1402   EVEX_LEN_0F3A00_W_1,
1403   EVEX_LEN_0F3A01_W_1,
1404   EVEX_LEN_0F3A14,
1405   EVEX_LEN_0F3A15,
1406   EVEX_LEN_0F3A16,
1407   EVEX_LEN_0F3A17,
1408   EVEX_LEN_0F3A18_W_0,
1409   EVEX_LEN_0F3A18_W_1,
1410   EVEX_LEN_0F3A19_W_0,
1411   EVEX_LEN_0F3A19_W_1,
1412   EVEX_LEN_0F3A1A_W_0,
1413   EVEX_LEN_0F3A1A_W_1,
1414   EVEX_LEN_0F3A1B_W_0,
1415   EVEX_LEN_0F3A1B_W_1,
1416   EVEX_LEN_0F3A20,
1417   EVEX_LEN_0F3A21_W_0,
1418   EVEX_LEN_0F3A22,
1419   EVEX_LEN_0F3A23_W_0,
1420   EVEX_LEN_0F3A23_W_1,
1421   EVEX_LEN_0F3A38_W_0,
1422   EVEX_LEN_0F3A38_W_1,
1423   EVEX_LEN_0F3A39_W_0,
1424   EVEX_LEN_0F3A39_W_1,
1425   EVEX_LEN_0F3A3A_W_0,
1426   EVEX_LEN_0F3A3A_W_1,
1427   EVEX_LEN_0F3A3B_W_0,
1428   EVEX_LEN_0F3A3B_W_1,
1429   EVEX_LEN_0F3A43_W_0,
1430   EVEX_LEN_0F3A43_W_1
1431 };
1432
1433 enum
1434 {
1435   VEX_W_0F41_P_0_LEN_1 = 0,
1436   VEX_W_0F41_P_2_LEN_1,
1437   VEX_W_0F42_P_0_LEN_1,
1438   VEX_W_0F42_P_2_LEN_1,
1439   VEX_W_0F44_P_0_LEN_0,
1440   VEX_W_0F44_P_2_LEN_0,
1441   VEX_W_0F45_P_0_LEN_1,
1442   VEX_W_0F45_P_2_LEN_1,
1443   VEX_W_0F46_P_0_LEN_1,
1444   VEX_W_0F46_P_2_LEN_1,
1445   VEX_W_0F47_P_0_LEN_1,
1446   VEX_W_0F47_P_2_LEN_1,
1447   VEX_W_0F4A_P_0_LEN_1,
1448   VEX_W_0F4A_P_2_LEN_1,
1449   VEX_W_0F4B_P_0_LEN_1,
1450   VEX_W_0F4B_P_2_LEN_1,
1451   VEX_W_0F90_P_0_LEN_0,
1452   VEX_W_0F90_P_2_LEN_0,
1453   VEX_W_0F91_P_0_LEN_0,
1454   VEX_W_0F91_P_2_LEN_0,
1455   VEX_W_0F92_P_0_LEN_0,
1456   VEX_W_0F92_P_2_LEN_0,
1457   VEX_W_0F93_P_0_LEN_0,
1458   VEX_W_0F93_P_2_LEN_0,
1459   VEX_W_0F98_P_0_LEN_0,
1460   VEX_W_0F98_P_2_LEN_0,
1461   VEX_W_0F99_P_0_LEN_0,
1462   VEX_W_0F99_P_2_LEN_0,
1463   VEX_W_0F380C,
1464   VEX_W_0F380D,
1465   VEX_W_0F380E,
1466   VEX_W_0F380F,
1467   VEX_W_0F3813,
1468   VEX_W_0F3816_L_1,
1469   VEX_W_0F3818,
1470   VEX_W_0F3819_L_1,
1471   VEX_W_0F381A_M_0_L_1,
1472   VEX_W_0F382C_M_0,
1473   VEX_W_0F382D_M_0,
1474   VEX_W_0F382E_M_0,
1475   VEX_W_0F382F_M_0,
1476   VEX_W_0F3836,
1477   VEX_W_0F3846,
1478   VEX_W_0F3849_X86_64_P_0,
1479   VEX_W_0F3849_X86_64_P_2,
1480   VEX_W_0F3849_X86_64_P_3,
1481   VEX_W_0F384B_X86_64_P_1,
1482   VEX_W_0F384B_X86_64_P_2,
1483   VEX_W_0F384B_X86_64_P_3,
1484   VEX_W_0F3858,
1485   VEX_W_0F3859,
1486   VEX_W_0F385A_M_0_L_0,
1487   VEX_W_0F385C_X86_64_P_1,
1488   VEX_W_0F385E_X86_64_P_0,
1489   VEX_W_0F385E_X86_64_P_1,
1490   VEX_W_0F385E_X86_64_P_2,
1491   VEX_W_0F385E_X86_64_P_3,
1492   VEX_W_0F3878,
1493   VEX_W_0F3879,
1494   VEX_W_0F38CF,
1495   VEX_W_0F3A00_L_1,
1496   VEX_W_0F3A01_L_1,
1497   VEX_W_0F3A02,
1498   VEX_W_0F3A04,
1499   VEX_W_0F3A05,
1500   VEX_W_0F3A06_L_1,
1501   VEX_W_0F3A18_L_1,
1502   VEX_W_0F3A19_L_1,
1503   VEX_W_0F3A1D,
1504   VEX_W_0F3A38_L_1,
1505   VEX_W_0F3A39_L_1,
1506   VEX_W_0F3A46_L_1,
1507   VEX_W_0F3A4A,
1508   VEX_W_0F3A4B,
1509   VEX_W_0F3A4C,
1510   VEX_W_0F3ACE,
1511   VEX_W_0F3ACF,
1512
1513   VEX_W_0FXOP_08_85_L_0,
1514   VEX_W_0FXOP_08_86_L_0,
1515   VEX_W_0FXOP_08_87_L_0,
1516   VEX_W_0FXOP_08_8E_L_0,
1517   VEX_W_0FXOP_08_8F_L_0,
1518   VEX_W_0FXOP_08_95_L_0,
1519   VEX_W_0FXOP_08_96_L_0,
1520   VEX_W_0FXOP_08_97_L_0,
1521   VEX_W_0FXOP_08_9E_L_0,
1522   VEX_W_0FXOP_08_9F_L_0,
1523   VEX_W_0FXOP_08_A6_L_0,
1524   VEX_W_0FXOP_08_B6_L_0,
1525   VEX_W_0FXOP_08_C0_L_0,
1526   VEX_W_0FXOP_08_C1_L_0,
1527   VEX_W_0FXOP_08_C2_L_0,
1528   VEX_W_0FXOP_08_C3_L_0,
1529   VEX_W_0FXOP_08_CC_L_0,
1530   VEX_W_0FXOP_08_CD_L_0,
1531   VEX_W_0FXOP_08_CE_L_0,
1532   VEX_W_0FXOP_08_CF_L_0,
1533   VEX_W_0FXOP_08_EC_L_0,
1534   VEX_W_0FXOP_08_ED_L_0,
1535   VEX_W_0FXOP_08_EE_L_0,
1536   VEX_W_0FXOP_08_EF_L_0,
1537
1538   VEX_W_0FXOP_09_80,
1539   VEX_W_0FXOP_09_81,
1540   VEX_W_0FXOP_09_82,
1541   VEX_W_0FXOP_09_83,
1542   VEX_W_0FXOP_09_C1_L_0,
1543   VEX_W_0FXOP_09_C2_L_0,
1544   VEX_W_0FXOP_09_C3_L_0,
1545   VEX_W_0FXOP_09_C6_L_0,
1546   VEX_W_0FXOP_09_C7_L_0,
1547   VEX_W_0FXOP_09_CB_L_0,
1548   VEX_W_0FXOP_09_D1_L_0,
1549   VEX_W_0FXOP_09_D2_L_0,
1550   VEX_W_0FXOP_09_D3_L_0,
1551   VEX_W_0FXOP_09_D6_L_0,
1552   VEX_W_0FXOP_09_D7_L_0,
1553   VEX_W_0FXOP_09_DB_L_0,
1554   VEX_W_0FXOP_09_E1_L_0,
1555   VEX_W_0FXOP_09_E2_L_0,
1556   VEX_W_0FXOP_09_E3_L_0,
1557
1558   EVEX_W_0F10_P_1,
1559   EVEX_W_0F10_P_3,
1560   EVEX_W_0F11_P_1,
1561   EVEX_W_0F11_P_3,
1562   EVEX_W_0F12_P_0_M_1,
1563   EVEX_W_0F12_P_1,
1564   EVEX_W_0F12_P_3,
1565   EVEX_W_0F16_P_0_M_1,
1566   EVEX_W_0F16_P_1,
1567   EVEX_W_0F2A_P_3,
1568   EVEX_W_0F51_P_1,
1569   EVEX_W_0F51_P_3,
1570   EVEX_W_0F58_P_1,
1571   EVEX_W_0F58_P_3,
1572   EVEX_W_0F59_P_1,
1573   EVEX_W_0F59_P_3,
1574   EVEX_W_0F5A_P_0,
1575   EVEX_W_0F5A_P_1,
1576   EVEX_W_0F5A_P_2,
1577   EVEX_W_0F5A_P_3,
1578   EVEX_W_0F5B_P_0,
1579   EVEX_W_0F5B_P_1,
1580   EVEX_W_0F5B_P_2,
1581   EVEX_W_0F5C_P_1,
1582   EVEX_W_0F5C_P_3,
1583   EVEX_W_0F5D_P_1,
1584   EVEX_W_0F5D_P_3,
1585   EVEX_W_0F5E_P_1,
1586   EVEX_W_0F5E_P_3,
1587   EVEX_W_0F5F_P_1,
1588   EVEX_W_0F5F_P_3,
1589   EVEX_W_0F62,
1590   EVEX_W_0F66,
1591   EVEX_W_0F6A,
1592   EVEX_W_0F6B,
1593   EVEX_W_0F6C,
1594   EVEX_W_0F6D,
1595   EVEX_W_0F6F_P_1,
1596   EVEX_W_0F6F_P_2,
1597   EVEX_W_0F6F_P_3,
1598   EVEX_W_0F70_P_2,
1599   EVEX_W_0F72_R_2,
1600   EVEX_W_0F72_R_6,
1601   EVEX_W_0F73_R_2,
1602   EVEX_W_0F73_R_6,
1603   EVEX_W_0F76,
1604   EVEX_W_0F78_P_0,
1605   EVEX_W_0F78_P_2,
1606   EVEX_W_0F79_P_0,
1607   EVEX_W_0F79_P_2,
1608   EVEX_W_0F7A_P_1,
1609   EVEX_W_0F7A_P_2,
1610   EVEX_W_0F7A_P_3,
1611   EVEX_W_0F7B_P_2,
1612   EVEX_W_0F7B_P_3,
1613   EVEX_W_0F7E_P_1,
1614   EVEX_W_0F7F_P_1,
1615   EVEX_W_0F7F_P_2,
1616   EVEX_W_0F7F_P_3,
1617   EVEX_W_0FC2_P_1,
1618   EVEX_W_0FC2_P_3,
1619   EVEX_W_0FD2,
1620   EVEX_W_0FD3,
1621   EVEX_W_0FD4,
1622   EVEX_W_0FD6_L_0,
1623   EVEX_W_0FE6_P_1,
1624   EVEX_W_0FE6_P_2,
1625   EVEX_W_0FE6_P_3,
1626   EVEX_W_0FE7,
1627   EVEX_W_0FF2,
1628   EVEX_W_0FF3,
1629   EVEX_W_0FF4,
1630   EVEX_W_0FFA,
1631   EVEX_W_0FFB,
1632   EVEX_W_0FFE,
1633   EVEX_W_0F380D,
1634   EVEX_W_0F3810_P_1,
1635   EVEX_W_0F3810_P_2,
1636   EVEX_W_0F3811_P_1,
1637   EVEX_W_0F3811_P_2,
1638   EVEX_W_0F3812_P_1,
1639   EVEX_W_0F3812_P_2,
1640   EVEX_W_0F3813_P_1,
1641   EVEX_W_0F3813_P_2,
1642   EVEX_W_0F3814_P_1,
1643   EVEX_W_0F3815_P_1,
1644   EVEX_W_0F3819,
1645   EVEX_W_0F381A,
1646   EVEX_W_0F381B,
1647   EVEX_W_0F381E,
1648   EVEX_W_0F381F,
1649   EVEX_W_0F3820_P_1,
1650   EVEX_W_0F3821_P_1,
1651   EVEX_W_0F3822_P_1,
1652   EVEX_W_0F3823_P_1,
1653   EVEX_W_0F3824_P_1,
1654   EVEX_W_0F3825_P_1,
1655   EVEX_W_0F3825_P_2,
1656   EVEX_W_0F3828_P_2,
1657   EVEX_W_0F3829_P_2,
1658   EVEX_W_0F382A_P_1,
1659   EVEX_W_0F382A_P_2,
1660   EVEX_W_0F382B,
1661   EVEX_W_0F3830_P_1,
1662   EVEX_W_0F3831_P_1,
1663   EVEX_W_0F3832_P_1,
1664   EVEX_W_0F3833_P_1,
1665   EVEX_W_0F3834_P_1,
1666   EVEX_W_0F3835_P_1,
1667   EVEX_W_0F3835_P_2,
1668   EVEX_W_0F3837,
1669   EVEX_W_0F383A_P_1,
1670   EVEX_W_0F3852_P_1,
1671   EVEX_W_0F3859,
1672   EVEX_W_0F385A,
1673   EVEX_W_0F385B,
1674   EVEX_W_0F3870,
1675   EVEX_W_0F3872_P_1,
1676   EVEX_W_0F3872_P_2,
1677   EVEX_W_0F3872_P_3,
1678   EVEX_W_0F387A,
1679   EVEX_W_0F387B,
1680   EVEX_W_0F3883,
1681   EVEX_W_0F3891,
1682   EVEX_W_0F3893,
1683   EVEX_W_0F38A1,
1684   EVEX_W_0F38A3,
1685   EVEX_W_0F38C7_R_1_M_0,
1686   EVEX_W_0F38C7_R_2_M_0,
1687   EVEX_W_0F38C7_R_5_M_0,
1688   EVEX_W_0F38C7_R_6_M_0,
1689
1690   EVEX_W_0F3A00,
1691   EVEX_W_0F3A01,
1692   EVEX_W_0F3A05,
1693   EVEX_W_0F3A08,
1694   EVEX_W_0F3A09,
1695   EVEX_W_0F3A0A,
1696   EVEX_W_0F3A0B,
1697   EVEX_W_0F3A18,
1698   EVEX_W_0F3A19,
1699   EVEX_W_0F3A1A,
1700   EVEX_W_0F3A1B,
1701   EVEX_W_0F3A21,
1702   EVEX_W_0F3A23,
1703   EVEX_W_0F3A38,
1704   EVEX_W_0F3A39,
1705   EVEX_W_0F3A3A,
1706   EVEX_W_0F3A3B,
1707   EVEX_W_0F3A42,
1708   EVEX_W_0F3A43,
1709   EVEX_W_0F3A70,
1710   EVEX_W_0F3A72,
1711 };
1712
1713 typedef void (*op_rtn) (int bytemode, int sizeflag);
1714
1715 struct dis386 {
1716   const char *name;
1717   struct
1718     {
1719       op_rtn rtn;
1720       int bytemode;
1721     } op[MAX_OPERANDS];
1722   unsigned int prefix_requirement;
1723 };
1724
1725 /* Upper case letters in the instruction names here are macros.
1726    'A' => print 'b' if no register operands or suffix_always is true
1727    'B' => print 'b' if suffix_always is true
1728    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1729           size prefix
1730    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1731           suffix_always is true
1732    'E' => print 'e' if 32-bit form of jcxz
1733    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1734    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1735    'H' => print ",pt" or ",pn" branch hint
1736    'I' unused.
1737    'J' unused.
1738    'K' => print 'd' or 'q' if rex prefix is present.
1739    'L' => print 'l' if suffix_always is true
1740    'M' => print 'r' if intel_mnemonic is false.
1741    'N' => print 'n' if instruction has no wait "prefix"
1742    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1743    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1744           or suffix_always is true.  print 'q' if rex prefix is present.
1745    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1746           is true
1747    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1748    'S' => print 'w', 'l' or 'q' if suffix_always is true
1749    'T' => print 'q' in 64bit mode if instruction has no operand size
1750           prefix and behave as 'P' otherwise
1751    'U' => print 'q' in 64bit mode if instruction has no operand size
1752           prefix and behave as 'Q' otherwise
1753    'V' => print 'q' in 64bit mode if instruction has no operand size
1754           prefix and behave as 'S' otherwise
1755    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1756    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1757    'Y' unused.
1758    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1759    '!' => change condition from true to false or from false to true.
1760    '%' => add 1 upper case letter to the macro.
1761    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1762           prefix or suffix_always is true (lcall/ljmp).
1763    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
1764           on operand size prefix.
1765    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
1766           has no operand size prefix for AMD64 ISA, behave as 'P'
1767           otherwise
1768
1769    2 upper case letter macros:
1770    "XY" => print 'x' or 'y' if suffix_always is true or no register
1771            operands and no broadcast.
1772    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1773            register operands and no broadcast.
1774    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1775    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1776            being false, or no operand at all in 64bit mode, or if suffix_always
1777            is true.
1778    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1779    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1780    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1781    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1782    "BW" => print 'b' or 'w' depending on the VEX.W bit
1783    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1784            an operand size prefix, or suffix_always is true.  print
1785            'q' if rex prefix is present.
1786
1787    Many of the above letters print nothing in Intel mode.  See "putop"
1788    for the details.
1789
1790    Braces '{' and '}', and vertical bars '|', indicate alternative
1791    mnemonic strings for AT&T and Intel.  */
1792
1793 static const struct dis386 dis386[] = {
1794   /* 00 */
1795   { "addB",             { Ebh1, Gb }, 0 },
1796   { "addS",             { Evh1, Gv }, 0 },
1797   { "addB",             { Gb, EbS }, 0 },
1798   { "addS",             { Gv, EvS }, 0 },
1799   { "addB",             { AL, Ib }, 0 },
1800   { "addS",             { eAX, Iv }, 0 },
1801   { X86_64_TABLE (X86_64_06) },
1802   { X86_64_TABLE (X86_64_07) },
1803   /* 08 */
1804   { "orB",              { Ebh1, Gb }, 0 },
1805   { "orS",              { Evh1, Gv }, 0 },
1806   { "orB",              { Gb, EbS }, 0 },
1807   { "orS",              { Gv, EvS }, 0 },
1808   { "orB",              { AL, Ib }, 0 },
1809   { "orS",              { eAX, Iv }, 0 },
1810   { X86_64_TABLE (X86_64_0E) },
1811   { Bad_Opcode },       /* 0x0f extended opcode escape */
1812   /* 10 */
1813   { "adcB",             { Ebh1, Gb }, 0 },
1814   { "adcS",             { Evh1, Gv }, 0 },
1815   { "adcB",             { Gb, EbS }, 0 },
1816   { "adcS",             { Gv, EvS }, 0 },
1817   { "adcB",             { AL, Ib }, 0 },
1818   { "adcS",             { eAX, Iv }, 0 },
1819   { X86_64_TABLE (X86_64_16) },
1820   { X86_64_TABLE (X86_64_17) },
1821   /* 18 */
1822   { "sbbB",             { Ebh1, Gb }, 0 },
1823   { "sbbS",             { Evh1, Gv }, 0 },
1824   { "sbbB",             { Gb, EbS }, 0 },
1825   { "sbbS",             { Gv, EvS }, 0 },
1826   { "sbbB",             { AL, Ib }, 0 },
1827   { "sbbS",             { eAX, Iv }, 0 },
1828   { X86_64_TABLE (X86_64_1E) },
1829   { X86_64_TABLE (X86_64_1F) },
1830   /* 20 */
1831   { "andB",             { Ebh1, Gb }, 0 },
1832   { "andS",             { Evh1, Gv }, 0 },
1833   { "andB",             { Gb, EbS }, 0 },
1834   { "andS",             { Gv, EvS }, 0 },
1835   { "andB",             { AL, Ib }, 0 },
1836   { "andS",             { eAX, Iv }, 0 },
1837   { Bad_Opcode },       /* SEG ES prefix */
1838   { X86_64_TABLE (X86_64_27) },
1839   /* 28 */
1840   { "subB",             { Ebh1, Gb }, 0 },
1841   { "subS",             { Evh1, Gv }, 0 },
1842   { "subB",             { Gb, EbS }, 0 },
1843   { "subS",             { Gv, EvS }, 0 },
1844   { "subB",             { AL, Ib }, 0 },
1845   { "subS",             { eAX, Iv }, 0 },
1846   { Bad_Opcode },       /* SEG CS prefix */
1847   { X86_64_TABLE (X86_64_2F) },
1848   /* 30 */
1849   { "xorB",             { Ebh1, Gb }, 0 },
1850   { "xorS",             { Evh1, Gv }, 0 },
1851   { "xorB",             { Gb, EbS }, 0 },
1852   { "xorS",             { Gv, EvS }, 0 },
1853   { "xorB",             { AL, Ib }, 0 },
1854   { "xorS",             { eAX, Iv }, 0 },
1855   { Bad_Opcode },       /* SEG SS prefix */
1856   { X86_64_TABLE (X86_64_37) },
1857   /* 38 */
1858   { "cmpB",             { Eb, Gb }, 0 },
1859   { "cmpS",             { Ev, Gv }, 0 },
1860   { "cmpB",             { Gb, EbS }, 0 },
1861   { "cmpS",             { Gv, EvS }, 0 },
1862   { "cmpB",             { AL, Ib }, 0 },
1863   { "cmpS",             { eAX, Iv }, 0 },
1864   { Bad_Opcode },       /* SEG DS prefix */
1865   { X86_64_TABLE (X86_64_3F) },
1866   /* 40 */
1867   { "inc{S|}",          { RMeAX }, 0 },
1868   { "inc{S|}",          { RMeCX }, 0 },
1869   { "inc{S|}",          { RMeDX }, 0 },
1870   { "inc{S|}",          { RMeBX }, 0 },
1871   { "inc{S|}",          { RMeSP }, 0 },
1872   { "inc{S|}",          { RMeBP }, 0 },
1873   { "inc{S|}",          { RMeSI }, 0 },
1874   { "inc{S|}",          { RMeDI }, 0 },
1875   /* 48 */
1876   { "dec{S|}",          { RMeAX }, 0 },
1877   { "dec{S|}",          { RMeCX }, 0 },
1878   { "dec{S|}",          { RMeDX }, 0 },
1879   { "dec{S|}",          { RMeBX }, 0 },
1880   { "dec{S|}",          { RMeSP }, 0 },
1881   { "dec{S|}",          { RMeBP }, 0 },
1882   { "dec{S|}",          { RMeSI }, 0 },
1883   { "dec{S|}",          { RMeDI }, 0 },
1884   /* 50 */
1885   { "pushV",            { RMrAX }, 0 },
1886   { "pushV",            { RMrCX }, 0 },
1887   { "pushV",            { RMrDX }, 0 },
1888   { "pushV",            { RMrBX }, 0 },
1889   { "pushV",            { RMrSP }, 0 },
1890   { "pushV",            { RMrBP }, 0 },
1891   { "pushV",            { RMrSI }, 0 },
1892   { "pushV",            { RMrDI }, 0 },
1893   /* 58 */
1894   { "popV",             { RMrAX }, 0 },
1895   { "popV",             { RMrCX }, 0 },
1896   { "popV",             { RMrDX }, 0 },
1897   { "popV",             { RMrBX }, 0 },
1898   { "popV",             { RMrSP }, 0 },
1899   { "popV",             { RMrBP }, 0 },
1900   { "popV",             { RMrSI }, 0 },
1901   { "popV",             { RMrDI }, 0 },
1902   /* 60 */
1903   { X86_64_TABLE (X86_64_60) },
1904   { X86_64_TABLE (X86_64_61) },
1905   { X86_64_TABLE (X86_64_62) },
1906   { X86_64_TABLE (X86_64_63) },
1907   { Bad_Opcode },       /* seg fs */
1908   { Bad_Opcode },       /* seg gs */
1909   { Bad_Opcode },       /* op size prefix */
1910   { Bad_Opcode },       /* adr size prefix */
1911   /* 68 */
1912   { "pushT",            { sIv }, 0 },
1913   { "imulS",            { Gv, Ev, Iv }, 0 },
1914   { "pushT",            { sIbT }, 0 },
1915   { "imulS",            { Gv, Ev, sIb }, 0 },
1916   { "ins{b|}",          { Ybr, indirDX }, 0 },
1917   { X86_64_TABLE (X86_64_6D) },
1918   { "outs{b|}",         { indirDXr, Xb }, 0 },
1919   { X86_64_TABLE (X86_64_6F) },
1920   /* 70 */
1921   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1922   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1923   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1924   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1925   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1926   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1927   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1928   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1929   /* 78 */
1930   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1931   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1932   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1933   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1934   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1935   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1936   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1937   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1938   /* 80 */
1939   { REG_TABLE (REG_80) },
1940   { REG_TABLE (REG_81) },
1941   { X86_64_TABLE (X86_64_82) },
1942   { REG_TABLE (REG_83) },
1943   { "testB",            { Eb, Gb }, 0 },
1944   { "testS",            { Ev, Gv }, 0 },
1945   { "xchgB",            { Ebh2, Gb }, 0 },
1946   { "xchgS",            { Evh2, Gv }, 0 },
1947   /* 88 */
1948   { "movB",             { Ebh3, Gb }, 0 },
1949   { "movS",             { Evh3, Gv }, 0 },
1950   { "movB",             { Gb, EbS }, 0 },
1951   { "movS",             { Gv, EvS }, 0 },
1952   { "movD",             { Sv, Sw }, 0 },
1953   { MOD_TABLE (MOD_8D) },
1954   { "movD",             { Sw, Sv }, 0 },
1955   { REG_TABLE (REG_8F) },
1956   /* 90 */
1957   { PREFIX_TABLE (PREFIX_90) },
1958   { "xchgS",            { RMeCX, eAX }, 0 },
1959   { "xchgS",            { RMeDX, eAX }, 0 },
1960   { "xchgS",            { RMeBX, eAX }, 0 },
1961   { "xchgS",            { RMeSP, eAX }, 0 },
1962   { "xchgS",            { RMeBP, eAX }, 0 },
1963   { "xchgS",            { RMeSI, eAX }, 0 },
1964   { "xchgS",            { RMeDI, eAX }, 0 },
1965   /* 98 */
1966   { "cW{t|}R",          { XX }, 0 },
1967   { "cR{t|}O",          { XX }, 0 },
1968   { X86_64_TABLE (X86_64_9A) },
1969   { Bad_Opcode },       /* fwait */
1970   { "pushfT",           { XX }, 0 },
1971   { "popfT",            { XX }, 0 },
1972   { "sahf",             { XX }, 0 },
1973   { "lahf",             { XX }, 0 },
1974   /* a0 */
1975   { "mov%LB",           { AL, Ob }, 0 },
1976   { "mov%LS",           { eAX, Ov }, 0 },
1977   { "mov%LB",           { Ob, AL }, 0 },
1978   { "mov%LS",           { Ov, eAX }, 0 },
1979   { "movs{b|}",         { Ybr, Xb }, 0 },
1980   { "movs{R|}",         { Yvr, Xv }, 0 },
1981   { "cmps{b|}",         { Xb, Yb }, 0 },
1982   { "cmps{R|}",         { Xv, Yv }, 0 },
1983   /* a8 */
1984   { "testB",            { AL, Ib }, 0 },
1985   { "testS",            { eAX, Iv }, 0 },
1986   { "stosB",            { Ybr, AL }, 0 },
1987   { "stosS",            { Yvr, eAX }, 0 },
1988   { "lodsB",            { ALr, Xb }, 0 },
1989   { "lodsS",            { eAXr, Xv }, 0 },
1990   { "scasB",            { AL, Yb }, 0 },
1991   { "scasS",            { eAX, Yv }, 0 },
1992   /* b0 */
1993   { "movB",             { RMAL, Ib }, 0 },
1994   { "movB",             { RMCL, Ib }, 0 },
1995   { "movB",             { RMDL, Ib }, 0 },
1996   { "movB",             { RMBL, Ib }, 0 },
1997   { "movB",             { RMAH, Ib }, 0 },
1998   { "movB",             { RMCH, Ib }, 0 },
1999   { "movB",             { RMDH, Ib }, 0 },
2000   { "movB",             { RMBH, Ib }, 0 },
2001   /* b8 */
2002   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2003   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2004   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2005   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2006   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2007   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2008   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2009   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2010   /* c0 */
2011   { REG_TABLE (REG_C0) },
2012   { REG_TABLE (REG_C1) },
2013   { X86_64_TABLE (X86_64_C2) },
2014   { X86_64_TABLE (X86_64_C3) },
2015   { X86_64_TABLE (X86_64_C4) },
2016   { X86_64_TABLE (X86_64_C5) },
2017   { REG_TABLE (REG_C6) },
2018   { REG_TABLE (REG_C7) },
2019   /* c8 */
2020   { "enterT",           { Iw, Ib }, 0 },
2021   { "leaveT",           { XX }, 0 },
2022   { "{l|}ret{|f}P",     { Iw }, 0 },
2023   { "{l|}ret{|f}P",     { XX }, 0 },
2024   { "int3",             { XX }, 0 },
2025   { "int",              { Ib }, 0 },
2026   { X86_64_TABLE (X86_64_CE) },
2027   { "iret%LP",          { XX }, 0 },
2028   /* d0 */
2029   { REG_TABLE (REG_D0) },
2030   { REG_TABLE (REG_D1) },
2031   { REG_TABLE (REG_D2) },
2032   { REG_TABLE (REG_D3) },
2033   { X86_64_TABLE (X86_64_D4) },
2034   { X86_64_TABLE (X86_64_D5) },
2035   { Bad_Opcode },
2036   { "xlat",             { DSBX }, 0 },
2037   /* d8 */
2038   { FLOAT },
2039   { FLOAT },
2040   { FLOAT },
2041   { FLOAT },
2042   { FLOAT },
2043   { FLOAT },
2044   { FLOAT },
2045   { FLOAT },
2046   /* e0 */
2047   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2048   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2049   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2050   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2051   { "inB",              { AL, Ib }, 0 },
2052   { "inG",              { zAX, Ib }, 0 },
2053   { "outB",             { Ib, AL }, 0 },
2054   { "outG",             { Ib, zAX }, 0 },
2055   /* e8 */
2056   { X86_64_TABLE (X86_64_E8) },
2057   { X86_64_TABLE (X86_64_E9) },
2058   { X86_64_TABLE (X86_64_EA) },
2059   { "jmp",              { Jb, BND }, 0 },
2060   { "inB",              { AL, indirDX }, 0 },
2061   { "inG",              { zAX, indirDX }, 0 },
2062   { "outB",             { indirDX, AL }, 0 },
2063   { "outG",             { indirDX, zAX }, 0 },
2064   /* f0 */
2065   { Bad_Opcode },       /* lock prefix */
2066   { "icebp",            { XX }, 0 },
2067   { Bad_Opcode },       /* repne */
2068   { Bad_Opcode },       /* repz */
2069   { "hlt",              { XX }, 0 },
2070   { "cmc",              { XX }, 0 },
2071   { REG_TABLE (REG_F6) },
2072   { REG_TABLE (REG_F7) },
2073   /* f8 */
2074   { "clc",              { XX }, 0 },
2075   { "stc",              { XX }, 0 },
2076   { "cli",              { XX }, 0 },
2077   { "sti",              { XX }, 0 },
2078   { "cld",              { XX }, 0 },
2079   { "std",              { XX }, 0 },
2080   { REG_TABLE (REG_FE) },
2081   { REG_TABLE (REG_FF) },
2082 };
2083
2084 static const struct dis386 dis386_twobyte[] = {
2085   /* 00 */
2086   { REG_TABLE (REG_0F00 ) },
2087   { REG_TABLE (REG_0F01 ) },
2088   { "larS",             { Gv, Ew }, 0 },
2089   { "lslS",             { Gv, Ew }, 0 },
2090   { Bad_Opcode },
2091   { "syscall",          { XX }, 0 },
2092   { "clts",             { XX }, 0 },
2093   { "sysret%LQ",                { XX }, 0 },
2094   /* 08 */
2095   { "invd",             { XX }, 0 },
2096   { PREFIX_TABLE (PREFIX_0F09) },
2097   { Bad_Opcode },
2098   { "ud2",              { XX }, 0 },
2099   { Bad_Opcode },
2100   { REG_TABLE (REG_0F0D) },
2101   { "femms",            { XX }, 0 },
2102   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2103   /* 10 */
2104   { PREFIX_TABLE (PREFIX_0F10) },
2105   { PREFIX_TABLE (PREFIX_0F11) },
2106   { PREFIX_TABLE (PREFIX_0F12) },
2107   { MOD_TABLE (MOD_0F13) },
2108   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2109   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2110   { PREFIX_TABLE (PREFIX_0F16) },
2111   { MOD_TABLE (MOD_0F17) },
2112   /* 18 */
2113   { REG_TABLE (REG_0F18) },
2114   { "nopQ",             { Ev }, 0 },
2115   { PREFIX_TABLE (PREFIX_0F1A) },
2116   { PREFIX_TABLE (PREFIX_0F1B) },
2117   { PREFIX_TABLE (PREFIX_0F1C) },
2118   { "nopQ",             { Ev }, 0 },
2119   { PREFIX_TABLE (PREFIX_0F1E) },
2120   { "nopQ",             { Ev }, 0 },
2121   /* 20 */
2122   { "movZ",             { Rm, Cm }, 0 },
2123   { "movZ",             { Rm, Dm }, 0 },
2124   { "movZ",             { Cm, Rm }, 0 },
2125   { "movZ",             { Dm, Rm }, 0 },
2126   { MOD_TABLE (MOD_0F24) },
2127   { Bad_Opcode },
2128   { MOD_TABLE (MOD_0F26) },
2129   { Bad_Opcode },
2130   /* 28 */
2131   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2132   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2133   { PREFIX_TABLE (PREFIX_0F2A) },
2134   { PREFIX_TABLE (PREFIX_0F2B) },
2135   { PREFIX_TABLE (PREFIX_0F2C) },
2136   { PREFIX_TABLE (PREFIX_0F2D) },
2137   { PREFIX_TABLE (PREFIX_0F2E) },
2138   { PREFIX_TABLE (PREFIX_0F2F) },
2139   /* 30 */
2140   { "wrmsr",            { XX }, 0 },
2141   { "rdtsc",            { XX }, 0 },
2142   { "rdmsr",            { XX }, 0 },
2143   { "rdpmc",            { XX }, 0 },
2144   { "sysenter",         { SEP }, 0 },
2145   { "sysexit",          { SEP }, 0 },
2146   { Bad_Opcode },
2147   { "getsec",           { XX }, 0 },
2148   /* 38 */
2149   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2150   { Bad_Opcode },
2151   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2152   { Bad_Opcode },
2153   { Bad_Opcode },
2154   { Bad_Opcode },
2155   { Bad_Opcode },
2156   { Bad_Opcode },
2157   /* 40 */
2158   { "cmovoS",           { Gv, Ev }, 0 },
2159   { "cmovnoS",          { Gv, Ev }, 0 },
2160   { "cmovbS",           { Gv, Ev }, 0 },
2161   { "cmovaeS",          { Gv, Ev }, 0 },
2162   { "cmoveS",           { Gv, Ev }, 0 },
2163   { "cmovneS",          { Gv, Ev }, 0 },
2164   { "cmovbeS",          { Gv, Ev }, 0 },
2165   { "cmovaS",           { Gv, Ev }, 0 },
2166   /* 48 */
2167   { "cmovsS",           { Gv, Ev }, 0 },
2168   { "cmovnsS",          { Gv, Ev }, 0 },
2169   { "cmovpS",           { Gv, Ev }, 0 },
2170   { "cmovnpS",          { Gv, Ev }, 0 },
2171   { "cmovlS",           { Gv, Ev }, 0 },
2172   { "cmovgeS",          { Gv, Ev }, 0 },
2173   { "cmovleS",          { Gv, Ev }, 0 },
2174   { "cmovgS",           { Gv, Ev }, 0 },
2175   /* 50 */
2176   { MOD_TABLE (MOD_0F50) },
2177   { PREFIX_TABLE (PREFIX_0F51) },
2178   { PREFIX_TABLE (PREFIX_0F52) },
2179   { PREFIX_TABLE (PREFIX_0F53) },
2180   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2181   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2182   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2183   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2184   /* 58 */
2185   { PREFIX_TABLE (PREFIX_0F58) },
2186   { PREFIX_TABLE (PREFIX_0F59) },
2187   { PREFIX_TABLE (PREFIX_0F5A) },
2188   { PREFIX_TABLE (PREFIX_0F5B) },
2189   { PREFIX_TABLE (PREFIX_0F5C) },
2190   { PREFIX_TABLE (PREFIX_0F5D) },
2191   { PREFIX_TABLE (PREFIX_0F5E) },
2192   { PREFIX_TABLE (PREFIX_0F5F) },
2193   /* 60 */
2194   { PREFIX_TABLE (PREFIX_0F60) },
2195   { PREFIX_TABLE (PREFIX_0F61) },
2196   { PREFIX_TABLE (PREFIX_0F62) },
2197   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2198   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2199   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2200   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2201   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2202   /* 68 */
2203   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2204   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2205   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2206   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2207   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2208   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2209   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2210   { PREFIX_TABLE (PREFIX_0F6F) },
2211   /* 70 */
2212   { PREFIX_TABLE (PREFIX_0F70) },
2213   { REG_TABLE (REG_0F71) },
2214   { REG_TABLE (REG_0F72) },
2215   { REG_TABLE (REG_0F73) },
2216   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2217   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2218   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2219   { "emms",             { XX }, PREFIX_OPCODE },
2220   /* 78 */
2221   { PREFIX_TABLE (PREFIX_0F78) },
2222   { PREFIX_TABLE (PREFIX_0F79) },
2223   { Bad_Opcode },
2224   { Bad_Opcode },
2225   { PREFIX_TABLE (PREFIX_0F7C) },
2226   { PREFIX_TABLE (PREFIX_0F7D) },
2227   { PREFIX_TABLE (PREFIX_0F7E) },
2228   { PREFIX_TABLE (PREFIX_0F7F) },
2229   /* 80 */
2230   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2231   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2232   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2233   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2234   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2235   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2236   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2237   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2238   /* 88 */
2239   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2240   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2241   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2242   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2243   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2244   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2245   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2246   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2247   /* 90 */
2248   { "seto",             { Eb }, 0 },
2249   { "setno",            { Eb }, 0 },
2250   { "setb",             { Eb }, 0 },
2251   { "setae",            { Eb }, 0 },
2252   { "sete",             { Eb }, 0 },
2253   { "setne",            { Eb }, 0 },
2254   { "setbe",            { Eb }, 0 },
2255   { "seta",             { Eb }, 0 },
2256   /* 98 */
2257   { "sets",             { Eb }, 0 },
2258   { "setns",            { Eb }, 0 },
2259   { "setp",             { Eb }, 0 },
2260   { "setnp",            { Eb }, 0 },
2261   { "setl",             { Eb }, 0 },
2262   { "setge",            { Eb }, 0 },
2263   { "setle",            { Eb }, 0 },
2264   { "setg",             { Eb }, 0 },
2265   /* a0 */
2266   { "pushT",            { fs }, 0 },
2267   { "popT",             { fs }, 0 },
2268   { "cpuid",            { XX }, 0 },
2269   { "btS",              { Ev, Gv }, 0 },
2270   { "shldS",            { Ev, Gv, Ib }, 0 },
2271   { "shldS",            { Ev, Gv, CL }, 0 },
2272   { REG_TABLE (REG_0FA6) },
2273   { REG_TABLE (REG_0FA7) },
2274   /* a8 */
2275   { "pushT",            { gs }, 0 },
2276   { "popT",             { gs }, 0 },
2277   { "rsm",              { XX }, 0 },
2278   { "btsS",             { Evh1, Gv }, 0 },
2279   { "shrdS",            { Ev, Gv, Ib }, 0 },
2280   { "shrdS",            { Ev, Gv, CL }, 0 },
2281   { REG_TABLE (REG_0FAE) },
2282   { "imulS",            { Gv, Ev }, 0 },
2283   /* b0 */
2284   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2285   { "cmpxchgS",         { Evh1, Gv }, 0 },
2286   { MOD_TABLE (MOD_0FB2) },
2287   { "btrS",             { Evh1, Gv }, 0 },
2288   { MOD_TABLE (MOD_0FB4) },
2289   { MOD_TABLE (MOD_0FB5) },
2290   { "movz{bR|x}",       { Gv, Eb }, 0 },
2291   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2292   /* b8 */
2293   { PREFIX_TABLE (PREFIX_0FB8) },
2294   { "ud1S",             { Gv, Ev }, 0 },
2295   { REG_TABLE (REG_0FBA) },
2296   { "btcS",             { Evh1, Gv }, 0 },
2297   { PREFIX_TABLE (PREFIX_0FBC) },
2298   { PREFIX_TABLE (PREFIX_0FBD) },
2299   { "movs{bR|x}",       { Gv, Eb }, 0 },
2300   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2301   /* c0 */
2302   { "xaddB",            { Ebh1, Gb }, 0 },
2303   { "xaddS",            { Evh1, Gv }, 0 },
2304   { PREFIX_TABLE (PREFIX_0FC2) },
2305   { MOD_TABLE (MOD_0FC3) },
2306   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2307   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2308   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2309   { REG_TABLE (REG_0FC7) },
2310   /* c8 */
2311   { "bswap",            { RMeAX }, 0 },
2312   { "bswap",            { RMeCX }, 0 },
2313   { "bswap",            { RMeDX }, 0 },
2314   { "bswap",            { RMeBX }, 0 },
2315   { "bswap",            { RMeSP }, 0 },
2316   { "bswap",            { RMeBP }, 0 },
2317   { "bswap",            { RMeSI }, 0 },
2318   { "bswap",            { RMeDI }, 0 },
2319   /* d0 */
2320   { PREFIX_TABLE (PREFIX_0FD0) },
2321   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2322   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2323   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2324   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2325   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2326   { PREFIX_TABLE (PREFIX_0FD6) },
2327   { MOD_TABLE (MOD_0FD7) },
2328   /* d8 */
2329   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2330   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2331   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2332   { "pand",             { MX, EM }, PREFIX_OPCODE },
2333   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2334   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2335   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2336   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2337   /* e0 */
2338   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2339   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2340   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2341   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2342   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2343   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2344   { PREFIX_TABLE (PREFIX_0FE6) },
2345   { PREFIX_TABLE (PREFIX_0FE7) },
2346   /* e8 */
2347   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2348   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2349   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2350   { "por",              { MX, EM }, PREFIX_OPCODE },
2351   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2352   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2353   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2354   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2355   /* f0 */
2356   { PREFIX_TABLE (PREFIX_0FF0) },
2357   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2358   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2359   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2360   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2361   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2362   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2363   { PREFIX_TABLE (PREFIX_0FF7) },
2364   /* f8 */
2365   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2366   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2367   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2368   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2369   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2370   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2371   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2372   { "ud0S",             { Gv, Ev }, 0 },
2373 };
2374
2375 static const unsigned char onebyte_has_modrm[256] = {
2376   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2377   /*       -------------------------------        */
2378   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2379   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2380   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2381   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2382   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2383   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2384   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2385   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2386   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2387   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2388   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2389   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2390   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2391   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2392   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2393   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2394   /*       -------------------------------        */
2395   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2396 };
2397
2398 static const unsigned char twobyte_has_modrm[256] = {
2399   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2400   /*       -------------------------------        */
2401   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2402   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2403   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2404   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2405   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2406   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2407   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2408   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2409   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2410   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2411   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2412   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2413   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2414   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2415   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2416   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2417   /*       -------------------------------        */
2418   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2419 };
2420
2421 static char obuf[100];
2422 static char *obufp;
2423 static char *mnemonicendp;
2424 static char scratchbuf[100];
2425 static unsigned char *start_codep;
2426 static unsigned char *insn_codep;
2427 static unsigned char *codep;
2428 static unsigned char *end_codep;
2429 static int last_lock_prefix;
2430 static int last_repz_prefix;
2431 static int last_repnz_prefix;
2432 static int last_data_prefix;
2433 static int last_addr_prefix;
2434 static int last_rex_prefix;
2435 static int last_seg_prefix;
2436 static int fwait_prefix;
2437 /* The active segment register prefix.  */
2438 static int active_seg_prefix;
2439 #define MAX_CODE_LENGTH 15
2440 /* We can up to 14 prefixes since the maximum instruction length is
2441    15bytes.  */
2442 static int all_prefixes[MAX_CODE_LENGTH - 1];
2443 static disassemble_info *the_info;
2444 static struct
2445   {
2446     int mod;
2447     int reg;
2448     int rm;
2449   }
2450 modrm;
2451 static unsigned char need_modrm;
2452 static struct
2453   {
2454     int scale;
2455     int index;
2456     int base;
2457   }
2458 sib;
2459 static struct
2460   {
2461     int register_specifier;
2462     int length;
2463     int prefix;
2464     int w;
2465     int evex;
2466     int r;
2467     int v;
2468     int mask_register_specifier;
2469     int zeroing;
2470     int ll;
2471     int b;
2472   }
2473 vex;
2474 static unsigned char need_vex;
2475
2476 struct op
2477   {
2478     const char *name;
2479     unsigned int len;
2480   };
2481
2482 /* If we are accessing mod/rm/reg without need_modrm set, then the
2483    values are stale.  Hitting this abort likely indicates that you
2484    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2485 #define MODRM_CHECK  if (!need_modrm) abort ()
2486
2487 static const char **names64;
2488 static const char **names32;
2489 static const char **names16;
2490 static const char **names8;
2491 static const char **names8rex;
2492 static const char **names_seg;
2493 static const char *index64;
2494 static const char *index32;
2495 static const char **index16;
2496 static const char **names_bnd;
2497
2498 static const char *intel_names64[] = {
2499   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2500   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2501 };
2502 static const char *intel_names32[] = {
2503   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2504   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2505 };
2506 static const char *intel_names16[] = {
2507   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2508   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2509 };
2510 static const char *intel_names8[] = {
2511   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2512 };
2513 static const char *intel_names8rex[] = {
2514   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2515   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2516 };
2517 static const char *intel_names_seg[] = {
2518   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2519 };
2520 static const char *intel_index64 = "riz";
2521 static const char *intel_index32 = "eiz";
2522 static const char *intel_index16[] = {
2523   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2524 };
2525
2526 static const char *att_names64[] = {
2527   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2528   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2529 };
2530 static const char *att_names32[] = {
2531   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2532   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2533 };
2534 static const char *att_names16[] = {
2535   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2536   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2537 };
2538 static const char *att_names8[] = {
2539   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2540 };
2541 static const char *att_names8rex[] = {
2542   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2543   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2544 };
2545 static const char *att_names_seg[] = {
2546   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2547 };
2548 static const char *att_index64 = "%riz";
2549 static const char *att_index32 = "%eiz";
2550 static const char *att_index16[] = {
2551   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2552 };
2553
2554 static const char **names_mm;
2555 static const char *intel_names_mm[] = {
2556   "mm0", "mm1", "mm2", "mm3",
2557   "mm4", "mm5", "mm6", "mm7"
2558 };
2559 static const char *att_names_mm[] = {
2560   "%mm0", "%mm1", "%mm2", "%mm3",
2561   "%mm4", "%mm5", "%mm6", "%mm7"
2562 };
2563
2564 static const char *intel_names_bnd[] = {
2565   "bnd0", "bnd1", "bnd2", "bnd3"
2566 };
2567
2568 static const char *att_names_bnd[] = {
2569   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2570 };
2571
2572 static const char **names_xmm;
2573 static const char *intel_names_xmm[] = {
2574   "xmm0", "xmm1", "xmm2", "xmm3",
2575   "xmm4", "xmm5", "xmm6", "xmm7",
2576   "xmm8", "xmm9", "xmm10", "xmm11",
2577   "xmm12", "xmm13", "xmm14", "xmm15",
2578   "xmm16", "xmm17", "xmm18", "xmm19",
2579   "xmm20", "xmm21", "xmm22", "xmm23",
2580   "xmm24", "xmm25", "xmm26", "xmm27",
2581   "xmm28", "xmm29", "xmm30", "xmm31"
2582 };
2583 static const char *att_names_xmm[] = {
2584   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2585   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2586   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2587   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2588   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2589   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2590   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2591   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2592 };
2593
2594 static const char **names_ymm;
2595 static const char *intel_names_ymm[] = {
2596   "ymm0", "ymm1", "ymm2", "ymm3",
2597   "ymm4", "ymm5", "ymm6", "ymm7",
2598   "ymm8", "ymm9", "ymm10", "ymm11",
2599   "ymm12", "ymm13", "ymm14", "ymm15",
2600   "ymm16", "ymm17", "ymm18", "ymm19",
2601   "ymm20", "ymm21", "ymm22", "ymm23",
2602   "ymm24", "ymm25", "ymm26", "ymm27",
2603   "ymm28", "ymm29", "ymm30", "ymm31"
2604 };
2605 static const char *att_names_ymm[] = {
2606   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2607   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2608   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2609   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2610   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2611   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2612   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2613   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2614 };
2615
2616 static const char **names_zmm;
2617 static const char *intel_names_zmm[] = {
2618   "zmm0", "zmm1", "zmm2", "zmm3",
2619   "zmm4", "zmm5", "zmm6", "zmm7",
2620   "zmm8", "zmm9", "zmm10", "zmm11",
2621   "zmm12", "zmm13", "zmm14", "zmm15",
2622   "zmm16", "zmm17", "zmm18", "zmm19",
2623   "zmm20", "zmm21", "zmm22", "zmm23",
2624   "zmm24", "zmm25", "zmm26", "zmm27",
2625   "zmm28", "zmm29", "zmm30", "zmm31"
2626 };
2627 static const char *att_names_zmm[] = {
2628   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2629   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2630   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2631   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2632   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2633   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2634   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2635   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2636 };
2637
2638 static const char **names_tmm;
2639 static const char *intel_names_tmm[] = {
2640   "tmm0", "tmm1", "tmm2", "tmm3",
2641   "tmm4", "tmm5", "tmm6", "tmm7"
2642 };
2643 static const char *att_names_tmm[] = {
2644   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2645   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2646 };
2647
2648 static const char **names_mask;
2649 static const char *intel_names_mask[] = {
2650   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2651 };
2652 static const char *att_names_mask[] = {
2653   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2654 };
2655
2656 static const char *names_rounding[] =
2657 {
2658   "{rn-sae}",
2659   "{rd-sae}",
2660   "{ru-sae}",
2661   "{rz-sae}"
2662 };
2663
2664 static const struct dis386 reg_table[][8] = {
2665   /* REG_80 */
2666   {
2667     { "addA",   { Ebh1, Ib }, 0 },
2668     { "orA",    { Ebh1, Ib }, 0 },
2669     { "adcA",   { Ebh1, Ib }, 0 },
2670     { "sbbA",   { Ebh1, Ib }, 0 },
2671     { "andA",   { Ebh1, Ib }, 0 },
2672     { "subA",   { Ebh1, Ib }, 0 },
2673     { "xorA",   { Ebh1, Ib }, 0 },
2674     { "cmpA",   { Eb, Ib }, 0 },
2675   },
2676   /* REG_81 */
2677   {
2678     { "addQ",   { Evh1, Iv }, 0 },
2679     { "orQ",    { Evh1, Iv }, 0 },
2680     { "adcQ",   { Evh1, Iv }, 0 },
2681     { "sbbQ",   { Evh1, Iv }, 0 },
2682     { "andQ",   { Evh1, Iv }, 0 },
2683     { "subQ",   { Evh1, Iv }, 0 },
2684     { "xorQ",   { Evh1, Iv }, 0 },
2685     { "cmpQ",   { Ev, Iv }, 0 },
2686   },
2687   /* REG_83 */
2688   {
2689     { "addQ",   { Evh1, sIb }, 0 },
2690     { "orQ",    { Evh1, sIb }, 0 },
2691     { "adcQ",   { Evh1, sIb }, 0 },
2692     { "sbbQ",   { Evh1, sIb }, 0 },
2693     { "andQ",   { Evh1, sIb }, 0 },
2694     { "subQ",   { Evh1, sIb }, 0 },
2695     { "xorQ",   { Evh1, sIb }, 0 },
2696     { "cmpQ",   { Ev, sIb }, 0 },
2697   },
2698   /* REG_8F */
2699   {
2700     { "popU",   { stackEv }, 0 },
2701     { XOP_8F_TABLE (XOP_09) },
2702     { Bad_Opcode },
2703     { Bad_Opcode },
2704     { Bad_Opcode },
2705     { XOP_8F_TABLE (XOP_09) },
2706   },
2707   /* REG_C0 */
2708   {
2709     { "rolA",   { Eb, Ib }, 0 },
2710     { "rorA",   { Eb, Ib }, 0 },
2711     { "rclA",   { Eb, Ib }, 0 },
2712     { "rcrA",   { Eb, Ib }, 0 },
2713     { "shlA",   { Eb, Ib }, 0 },
2714     { "shrA",   { Eb, Ib }, 0 },
2715     { "shlA",   { Eb, Ib }, 0 },
2716     { "sarA",   { Eb, Ib }, 0 },
2717   },
2718   /* REG_C1 */
2719   {
2720     { "rolQ",   { Ev, Ib }, 0 },
2721     { "rorQ",   { Ev, Ib }, 0 },
2722     { "rclQ",   { Ev, Ib }, 0 },
2723     { "rcrQ",   { Ev, Ib }, 0 },
2724     { "shlQ",   { Ev, Ib }, 0 },
2725     { "shrQ",   { Ev, Ib }, 0 },
2726     { "shlQ",   { Ev, Ib }, 0 },
2727     { "sarQ",   { Ev, Ib }, 0 },
2728   },
2729   /* REG_C6 */
2730   {
2731     { "movA",   { Ebh3, Ib }, 0 },
2732     { Bad_Opcode },
2733     { Bad_Opcode },
2734     { Bad_Opcode },
2735     { Bad_Opcode },
2736     { Bad_Opcode },
2737     { Bad_Opcode },
2738     { MOD_TABLE (MOD_C6_REG_7) },
2739   },
2740   /* REG_C7 */
2741   {
2742     { "movQ",   { Evh3, Iv }, 0 },
2743     { Bad_Opcode },
2744     { Bad_Opcode },
2745     { Bad_Opcode },
2746     { Bad_Opcode },
2747     { Bad_Opcode },
2748     { Bad_Opcode },
2749     { MOD_TABLE (MOD_C7_REG_7) },
2750   },
2751   /* REG_D0 */
2752   {
2753     { "rolA",   { Eb, I1 }, 0 },
2754     { "rorA",   { Eb, I1 }, 0 },
2755     { "rclA",   { Eb, I1 }, 0 },
2756     { "rcrA",   { Eb, I1 }, 0 },
2757     { "shlA",   { Eb, I1 }, 0 },
2758     { "shrA",   { Eb, I1 }, 0 },
2759     { "shlA",   { Eb, I1 }, 0 },
2760     { "sarA",   { Eb, I1 }, 0 },
2761   },
2762   /* REG_D1 */
2763   {
2764     { "rolQ",   { Ev, I1 }, 0 },
2765     { "rorQ",   { Ev, I1 }, 0 },
2766     { "rclQ",   { Ev, I1 }, 0 },
2767     { "rcrQ",   { Ev, I1 }, 0 },
2768     { "shlQ",   { Ev, I1 }, 0 },
2769     { "shrQ",   { Ev, I1 }, 0 },
2770     { "shlQ",   { Ev, I1 }, 0 },
2771     { "sarQ",   { Ev, I1 }, 0 },
2772   },
2773   /* REG_D2 */
2774   {
2775     { "rolA",   { Eb, CL }, 0 },
2776     { "rorA",   { Eb, CL }, 0 },
2777     { "rclA",   { Eb, CL }, 0 },
2778     { "rcrA",   { Eb, CL }, 0 },
2779     { "shlA",   { Eb, CL }, 0 },
2780     { "shrA",   { Eb, CL }, 0 },
2781     { "shlA",   { Eb, CL }, 0 },
2782     { "sarA",   { Eb, CL }, 0 },
2783   },
2784   /* REG_D3 */
2785   {
2786     { "rolQ",   { Ev, CL }, 0 },
2787     { "rorQ",   { Ev, CL }, 0 },
2788     { "rclQ",   { Ev, CL }, 0 },
2789     { "rcrQ",   { Ev, CL }, 0 },
2790     { "shlQ",   { Ev, CL }, 0 },
2791     { "shrQ",   { Ev, CL }, 0 },
2792     { "shlQ",   { Ev, CL }, 0 },
2793     { "sarQ",   { Ev, CL }, 0 },
2794   },
2795   /* REG_F6 */
2796   {
2797     { "testA",  { Eb, Ib }, 0 },
2798     { "testA",  { Eb, Ib }, 0 },
2799     { "notA",   { Ebh1 }, 0 },
2800     { "negA",   { Ebh1 }, 0 },
2801     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2802     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2803     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2804     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2805   },
2806   /* REG_F7 */
2807   {
2808     { "testQ",  { Ev, Iv }, 0 },
2809     { "testQ",  { Ev, Iv }, 0 },
2810     { "notQ",   { Evh1 }, 0 },
2811     { "negQ",   { Evh1 }, 0 },
2812     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2813     { "imulQ",  { Ev }, 0 },
2814     { "divQ",   { Ev }, 0 },
2815     { "idivQ",  { Ev }, 0 },
2816   },
2817   /* REG_FE */
2818   {
2819     { "incA",   { Ebh1 }, 0 },
2820     { "decA",   { Ebh1 }, 0 },
2821   },
2822   /* REG_FF */
2823   {
2824     { "incQ",   { Evh1 }, 0 },
2825     { "decQ",   { Evh1 }, 0 },
2826     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
2827     { MOD_TABLE (MOD_FF_REG_3) },
2828     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
2829     { MOD_TABLE (MOD_FF_REG_5) },
2830     { "pushU",  { stackEv }, 0 },
2831     { Bad_Opcode },
2832   },
2833   /* REG_0F00 */
2834   {
2835     { "sldtD",  { Sv }, 0 },
2836     { "strD",   { Sv }, 0 },
2837     { "lldt",   { Ew }, 0 },
2838     { "ltr",    { Ew }, 0 },
2839     { "verr",   { Ew }, 0 },
2840     { "verw",   { Ew }, 0 },
2841     { Bad_Opcode },
2842     { Bad_Opcode },
2843   },
2844   /* REG_0F01 */
2845   {
2846     { MOD_TABLE (MOD_0F01_REG_0) },
2847     { MOD_TABLE (MOD_0F01_REG_1) },
2848     { MOD_TABLE (MOD_0F01_REG_2) },
2849     { MOD_TABLE (MOD_0F01_REG_3) },
2850     { "smswD",  { Sv }, 0 },
2851     { MOD_TABLE (MOD_0F01_REG_5) },
2852     { "lmsw",   { Ew }, 0 },
2853     { MOD_TABLE (MOD_0F01_REG_7) },
2854   },
2855   /* REG_0F0D */
2856   {
2857     { "prefetch",       { Mb }, 0 },
2858     { "prefetchw",      { Mb }, 0 },
2859     { "prefetchwt1",    { Mb }, 0 },
2860     { "prefetch",       { Mb }, 0 },
2861     { "prefetch",       { Mb }, 0 },
2862     { "prefetch",       { Mb }, 0 },
2863     { "prefetch",       { Mb }, 0 },
2864     { "prefetch",       { Mb }, 0 },
2865   },
2866   /* REG_0F18 */
2867   {
2868     { MOD_TABLE (MOD_0F18_REG_0) },
2869     { MOD_TABLE (MOD_0F18_REG_1) },
2870     { MOD_TABLE (MOD_0F18_REG_2) },
2871     { MOD_TABLE (MOD_0F18_REG_3) },
2872     { MOD_TABLE (MOD_0F18_REG_4) },
2873     { MOD_TABLE (MOD_0F18_REG_5) },
2874     { MOD_TABLE (MOD_0F18_REG_6) },
2875     { MOD_TABLE (MOD_0F18_REG_7) },
2876   },
2877   /* REG_0F1C_P_0_MOD_0 */
2878   {
2879     { "cldemote",       { Mb }, 0 },
2880     { "nopQ",           { Ev }, 0 },
2881     { "nopQ",           { Ev }, 0 },
2882     { "nopQ",           { Ev }, 0 },
2883     { "nopQ",           { Ev }, 0 },
2884     { "nopQ",           { Ev }, 0 },
2885     { "nopQ",           { Ev }, 0 },
2886     { "nopQ",           { Ev }, 0 },
2887   },
2888   /* REG_0F1E_P_1_MOD_3 */
2889   {
2890     { "nopQ",           { Ev }, 0 },
2891     { "rdsspK",         { Edq }, PREFIX_OPCODE },
2892     { "nopQ",           { Ev }, 0 },
2893     { "nopQ",           { Ev }, 0 },
2894     { "nopQ",           { Ev }, 0 },
2895     { "nopQ",           { Ev }, 0 },
2896     { "nopQ",           { Ev }, 0 },
2897     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2898   },
2899   /* REG_0F71 */
2900   {
2901     { Bad_Opcode },
2902     { Bad_Opcode },
2903     { MOD_TABLE (MOD_0F71_REG_2) },
2904     { Bad_Opcode },
2905     { MOD_TABLE (MOD_0F71_REG_4) },
2906     { Bad_Opcode },
2907     { MOD_TABLE (MOD_0F71_REG_6) },
2908   },
2909   /* REG_0F72 */
2910   {
2911     { Bad_Opcode },
2912     { Bad_Opcode },
2913     { MOD_TABLE (MOD_0F72_REG_2) },
2914     { Bad_Opcode },
2915     { MOD_TABLE (MOD_0F72_REG_4) },
2916     { Bad_Opcode },
2917     { MOD_TABLE (MOD_0F72_REG_6) },
2918   },
2919   /* REG_0F73 */
2920   {
2921     { Bad_Opcode },
2922     { Bad_Opcode },
2923     { MOD_TABLE (MOD_0F73_REG_2) },
2924     { MOD_TABLE (MOD_0F73_REG_3) },
2925     { Bad_Opcode },
2926     { Bad_Opcode },
2927     { MOD_TABLE (MOD_0F73_REG_6) },
2928     { MOD_TABLE (MOD_0F73_REG_7) },
2929   },
2930   /* REG_0FA6 */
2931   {
2932     { "montmul",        { { OP_0f07, 0 } }, 0 },
2933     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2934     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2935   },
2936   /* REG_0FA7 */
2937   {
2938     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2939     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2940     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2941     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2942     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2943     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2944   },
2945   /* REG_0FAE */
2946   {
2947     { MOD_TABLE (MOD_0FAE_REG_0) },
2948     { MOD_TABLE (MOD_0FAE_REG_1) },
2949     { MOD_TABLE (MOD_0FAE_REG_2) },
2950     { MOD_TABLE (MOD_0FAE_REG_3) },
2951     { MOD_TABLE (MOD_0FAE_REG_4) },
2952     { MOD_TABLE (MOD_0FAE_REG_5) },
2953     { MOD_TABLE (MOD_0FAE_REG_6) },
2954     { MOD_TABLE (MOD_0FAE_REG_7) },
2955   },
2956   /* REG_0FBA */
2957   {
2958     { Bad_Opcode },
2959     { Bad_Opcode },
2960     { Bad_Opcode },
2961     { Bad_Opcode },
2962     { "btQ",    { Ev, Ib }, 0 },
2963     { "btsQ",   { Evh1, Ib }, 0 },
2964     { "btrQ",   { Evh1, Ib }, 0 },
2965     { "btcQ",   { Evh1, Ib }, 0 },
2966   },
2967   /* REG_0FC7 */
2968   {
2969     { Bad_Opcode },
2970     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2971     { Bad_Opcode },
2972     { MOD_TABLE (MOD_0FC7_REG_3) },
2973     { MOD_TABLE (MOD_0FC7_REG_4) },
2974     { MOD_TABLE (MOD_0FC7_REG_5) },
2975     { MOD_TABLE (MOD_0FC7_REG_6) },
2976     { MOD_TABLE (MOD_0FC7_REG_7) },
2977   },
2978   /* REG_VEX_0F71 */
2979   {
2980     { Bad_Opcode },
2981     { Bad_Opcode },
2982     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2983     { Bad_Opcode },
2984     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2985     { Bad_Opcode },
2986     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2987   },
2988   /* REG_VEX_0F72 */
2989   {
2990     { Bad_Opcode },
2991     { Bad_Opcode },
2992     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2993     { Bad_Opcode },
2994     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2995     { Bad_Opcode },
2996     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2997   },
2998   /* REG_VEX_0F73 */
2999   {
3000     { Bad_Opcode },
3001     { Bad_Opcode },
3002     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3003     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3004     { Bad_Opcode },
3005     { Bad_Opcode },
3006     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3007     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3008   },
3009   /* REG_VEX_0FAE */
3010   {
3011     { Bad_Opcode },
3012     { Bad_Opcode },
3013     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3014     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3015   },
3016   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3017   {
3018     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3019   },
3020   /* REG_VEX_0F38F3 */
3021   {
3022     { Bad_Opcode },
3023     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
3024     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
3025     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
3026   },
3027   /* REG_0FXOP_09_01_L_0 */
3028   {
3029     { Bad_Opcode },
3030     { "blcfill",        { VexGdq, Edq }, 0 },
3031     { "blsfill",        { VexGdq, Edq }, 0 },
3032     { "blcs",   { VexGdq, Edq }, 0 },
3033     { "tzmsk",  { VexGdq, Edq }, 0 },
3034     { "blcic",  { VexGdq, Edq }, 0 },
3035     { "blsic",  { VexGdq, Edq }, 0 },
3036     { "t1mskc", { VexGdq, Edq }, 0 },
3037   },
3038   /* REG_0FXOP_09_02_L_0 */
3039   {
3040     { Bad_Opcode },
3041     { "blcmsk", { VexGdq, Edq }, 0 },
3042     { Bad_Opcode },
3043     { Bad_Opcode },
3044     { Bad_Opcode },
3045     { Bad_Opcode },
3046     { "blci",   { VexGdq, Edq }, 0 },
3047   },
3048   /* REG_0FXOP_09_12_M_1_L_0 */
3049   {
3050     { "llwpcb", { Edq }, 0 },
3051     { "slwpcb", { Edq }, 0 },
3052   },
3053   /* REG_0FXOP_0A_12_L_0 */
3054   {
3055     { "lwpins", { VexGdq, Ed, Id }, 0 },
3056     { "lwpval", { VexGdq, Ed, Id }, 0 },
3057   },
3058
3059 #include "i386-dis-evex-reg.h"
3060 };
3061
3062 static const struct dis386 prefix_table[][4] = {
3063   /* PREFIX_90 */
3064   {
3065     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3066     { "pause", { XX }, 0 },
3067     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3068     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3069   },
3070
3071   /* PREFIX_0F01_REG_3_RM_1 */
3072   {
3073     { "vmmcall",        { Skip_MODRM }, 0 },
3074     { "vmgexit",        { Skip_MODRM }, 0 },
3075     { Bad_Opcode },
3076     { "vmgexit",        { Skip_MODRM }, 0 },
3077   },
3078
3079   /* PREFIX_0F01_REG_5_MOD_0 */
3080   {
3081     { Bad_Opcode },
3082     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3083   },
3084
3085   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3086   {
3087     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3088     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3089     { Bad_Opcode },
3090     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3091   },
3092
3093   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3094   {
3095     { Bad_Opcode },
3096     { Bad_Opcode },
3097     { Bad_Opcode },
3098     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3099   },
3100
3101   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3102   {
3103     { Bad_Opcode },
3104     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3105   },
3106
3107   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3108   {
3109     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3110     { "mcommit",        { Skip_MODRM }, 0 },
3111   },
3112
3113   /* PREFIX_0F09 */
3114   {
3115     { "wbinvd",   { XX }, 0 },
3116     { "wbnoinvd", { XX }, 0 },
3117   },
3118
3119   /* PREFIX_0F10 */
3120   {
3121     { "movups", { XM, EXx }, PREFIX_OPCODE },
3122     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3123     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3124     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3125   },
3126
3127   /* PREFIX_0F11 */
3128   {
3129     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3130     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3131     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3132     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3133   },
3134
3135   /* PREFIX_0F12 */
3136   {
3137     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3138     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3139     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3140     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3141   },
3142
3143   /* PREFIX_0F16 */
3144   {
3145     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3146     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3147     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3148   },
3149
3150   /* PREFIX_0F1A */
3151   {
3152     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3153     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3154     { "bndmov", { Gbnd, Ebnd }, 0 },
3155     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3156   },
3157
3158   /* PREFIX_0F1B */
3159   {
3160     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3161     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3162     { "bndmov", { EbndS, Gbnd }, 0 },
3163     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3164   },
3165
3166   /* PREFIX_0F1C */
3167   {
3168     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3169     { "nopQ",   { Ev }, PREFIX_OPCODE },
3170     { "nopQ",   { Ev }, PREFIX_OPCODE },
3171     { "nopQ",   { Ev }, PREFIX_OPCODE },
3172   },
3173
3174   /* PREFIX_0F1E */
3175   {
3176     { "nopQ",   { Ev }, PREFIX_OPCODE },
3177     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3178     { "nopQ",   { Ev }, PREFIX_OPCODE },
3179     { "nopQ",   { Ev }, PREFIX_OPCODE },
3180   },
3181
3182   /* PREFIX_0F2A */
3183   {
3184     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3185     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3186     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3187     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3188   },
3189
3190   /* PREFIX_0F2B */
3191   {
3192     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3193     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3194     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3195     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3196   },
3197
3198   /* PREFIX_0F2C */
3199   {
3200     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3201     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3202     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3203     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3204   },
3205
3206   /* PREFIX_0F2D */
3207   {
3208     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3209     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3210     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3211     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3212   },
3213
3214   /* PREFIX_0F2E */
3215   {
3216     { "ucomiss",{ XM, EXd }, 0 },
3217     { Bad_Opcode },
3218     { "ucomisd",{ XM, EXq }, 0 },
3219   },
3220
3221   /* PREFIX_0F2F */
3222   {
3223     { "comiss", { XM, EXd }, 0 },
3224     { Bad_Opcode },
3225     { "comisd", { XM, EXq }, 0 },
3226   },
3227
3228   /* PREFIX_0F51 */
3229   {
3230     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3231     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3232     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3233     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3234   },
3235
3236   /* PREFIX_0F52 */
3237   {
3238     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3239     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3240   },
3241
3242   /* PREFIX_0F53 */
3243   {
3244     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3245     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3246   },
3247
3248   /* PREFIX_0F58 */
3249   {
3250     { "addps", { XM, EXx }, PREFIX_OPCODE },
3251     { "addss", { XM, EXd }, PREFIX_OPCODE },
3252     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3253     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3254   },
3255
3256   /* PREFIX_0F59 */
3257   {
3258     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3259     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3260     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3261     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3262   },
3263
3264   /* PREFIX_0F5A */
3265   {
3266     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3267     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3268     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3269     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3270   },
3271
3272   /* PREFIX_0F5B */
3273   {
3274     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3275     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3276     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3277   },
3278
3279   /* PREFIX_0F5C */
3280   {
3281     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3282     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3283     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3284     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3285   },
3286
3287   /* PREFIX_0F5D */
3288   {
3289     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3290     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3291     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3292     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3293   },
3294
3295   /* PREFIX_0F5E */
3296   {
3297     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3298     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3299     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3300     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3301   },
3302
3303   /* PREFIX_0F5F */
3304   {
3305     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3306     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3307     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3308     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3309   },
3310
3311   /* PREFIX_0F60 */
3312   {
3313     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3314     { Bad_Opcode },
3315     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3316   },
3317
3318   /* PREFIX_0F61 */
3319   {
3320     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3321     { Bad_Opcode },
3322     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3323   },
3324
3325   /* PREFIX_0F62 */
3326   {
3327     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3328     { Bad_Opcode },
3329     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3330   },
3331
3332   /* PREFIX_0F6F */
3333   {
3334     { "movq",   { MX, EM }, PREFIX_OPCODE },
3335     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3336     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3337   },
3338
3339   /* PREFIX_0F70 */
3340   {
3341     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3342     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3343     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3344     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3345   },
3346
3347   /* PREFIX_0F78 */
3348   {
3349     {"vmread",  { Em, Gm }, 0 },
3350     { Bad_Opcode },
3351     {"extrq",   { XS, Ib, Ib }, 0 },
3352     {"insertq", { XM, XS, Ib, Ib }, 0 },
3353   },
3354
3355   /* PREFIX_0F79 */
3356   {
3357     {"vmwrite", { Gm, Em }, 0 },
3358     { Bad_Opcode },
3359     {"extrq",   { XM, XS }, 0 },
3360     {"insertq", { XM, XS }, 0 },
3361   },
3362
3363   /* PREFIX_0F7C */
3364   {
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3368     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3369   },
3370
3371   /* PREFIX_0F7D */
3372   {
3373     { Bad_Opcode },
3374     { Bad_Opcode },
3375     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3376     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3377   },
3378
3379   /* PREFIX_0F7E */
3380   {
3381     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3382     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3383     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3384   },
3385
3386   /* PREFIX_0F7F */
3387   {
3388     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3389     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3390     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3391   },
3392
3393   /* PREFIX_0FAE_REG_0_MOD_3 */
3394   {
3395     { Bad_Opcode },
3396     { "rdfsbase", { Ev }, 0 },
3397   },
3398
3399   /* PREFIX_0FAE_REG_1_MOD_3 */
3400   {
3401     { Bad_Opcode },
3402     { "rdgsbase", { Ev }, 0 },
3403   },
3404
3405   /* PREFIX_0FAE_REG_2_MOD_3 */
3406   {
3407     { Bad_Opcode },
3408     { "wrfsbase", { Ev }, 0 },
3409   },
3410
3411   /* PREFIX_0FAE_REG_3_MOD_3 */
3412   {
3413     { Bad_Opcode },
3414     { "wrgsbase", { Ev }, 0 },
3415   },
3416
3417   /* PREFIX_0FAE_REG_4_MOD_0 */
3418   {
3419     { "xsave",  { FXSAVE }, 0 },
3420     { "ptwrite{%LQ|}", { Edq }, 0 },
3421   },
3422
3423   /* PREFIX_0FAE_REG_4_MOD_3 */
3424   {
3425     { Bad_Opcode },
3426     { "ptwrite{%LQ|}", { Edq }, 0 },
3427   },
3428
3429   /* PREFIX_0FAE_REG_5_MOD_3 */
3430   {
3431     { "lfence",         { Skip_MODRM }, 0 },
3432     { "incsspK",        { Edq }, PREFIX_OPCODE },
3433   },
3434
3435   /* PREFIX_0FAE_REG_6_MOD_0 */
3436   {
3437     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3438     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3439     { "clwb",   { Mb }, PREFIX_OPCODE },
3440   },
3441
3442   /* PREFIX_0FAE_REG_6_MOD_3 */
3443   {
3444     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3445     { "umonitor",       { Eva }, PREFIX_OPCODE },
3446     { "tpause", { Edq }, PREFIX_OPCODE },
3447     { "umwait", { Edq }, PREFIX_OPCODE },
3448   },
3449
3450   /* PREFIX_0FAE_REG_7_MOD_0 */
3451   {
3452     { "clflush",        { Mb }, 0 },
3453     { Bad_Opcode },
3454     { "clflushopt",     { Mb }, 0 },
3455   },
3456
3457   /* PREFIX_0FB8 */
3458   {
3459     { Bad_Opcode },
3460     { "popcntS", { Gv, Ev }, 0 },
3461   },
3462
3463   /* PREFIX_0FBC */
3464   {
3465     { "bsfS",   { Gv, Ev }, 0 },
3466     { "tzcntS", { Gv, Ev }, 0 },
3467     { "bsfS",   { Gv, Ev }, 0 },
3468   },
3469
3470   /* PREFIX_0FBD */
3471   {
3472     { "bsrS",   { Gv, Ev }, 0 },
3473     { "lzcntS", { Gv, Ev }, 0 },
3474     { "bsrS",   { Gv, Ev }, 0 },
3475   },
3476
3477   /* PREFIX_0FC2 */
3478   {
3479     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3480     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3481     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3482     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3483   },
3484
3485   /* PREFIX_0FC7_REG_6_MOD_0 */
3486   {
3487     { "vmptrld",{ Mq }, 0 },
3488     { "vmxon",  { Mq }, 0 },
3489     { "vmclear",{ Mq }, 0 },
3490   },
3491
3492   /* PREFIX_0FC7_REG_6_MOD_3 */
3493   {
3494     { "rdrand", { Ev }, 0 },
3495     { Bad_Opcode },
3496     { "rdrand", { Ev }, 0 }
3497   },
3498
3499   /* PREFIX_0FC7_REG_7_MOD_3 */
3500   {
3501     { "rdseed", { Ev }, 0 },
3502     { "rdpid",  { Em }, 0 },
3503     { "rdseed", { Ev }, 0 },
3504   },
3505
3506   /* PREFIX_0FD0 */
3507   {
3508     { Bad_Opcode },
3509     { Bad_Opcode },
3510     { "addsubpd", { XM, EXx }, 0 },
3511     { "addsubps", { XM, EXx }, 0 },
3512   },
3513
3514   /* PREFIX_0FD6 */
3515   {
3516     { Bad_Opcode },
3517     { "movq2dq",{ XM, MS }, 0 },
3518     { "movq",   { EXqS, XM }, 0 },
3519     { "movdq2q",{ MX, XS }, 0 },
3520   },
3521
3522   /* PREFIX_0FE6 */
3523   {
3524     { Bad_Opcode },
3525     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3526     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3527     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3528   },
3529
3530   /* PREFIX_0FE7 */
3531   {
3532     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3533     { Bad_Opcode },
3534     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3535   },
3536
3537   /* PREFIX_0FF0 */
3538   {
3539     { Bad_Opcode },
3540     { Bad_Opcode },
3541     { Bad_Opcode },
3542     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3543   },
3544
3545   /* PREFIX_0FF7 */
3546   {
3547     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3548     { Bad_Opcode },
3549     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3550   },
3551
3552   /* PREFIX_0F38F0 */
3553   {
3554     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3555     { Bad_Opcode },
3556     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3557     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3558   },
3559
3560   /* PREFIX_0F38F1 */
3561   {
3562     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3563     { Bad_Opcode },
3564     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3565     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3566   },
3567
3568   /* PREFIX_0F38F6 */
3569   {
3570     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3571     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3572     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3573     { Bad_Opcode },
3574   },
3575
3576   /* PREFIX_0F38F8 */
3577   {
3578     { Bad_Opcode },
3579     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3580     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3581     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3582   },
3583
3584   /* PREFIX_VEX_0F10 */
3585   {
3586     { "vmovups",        { XM, EXx }, 0 },
3587     { "vmovss",         { XMScalar, VexScalarR, EXxmm_md }, 0 },
3588     { "vmovupd",        { XM, EXx }, 0 },
3589     { "vmovsd",         { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3590   },
3591
3592   /* PREFIX_VEX_0F11 */
3593   {
3594     { "vmovups",        { EXxS, XM }, 0 },
3595     { "vmovss",         { EXdS, VexScalarR, XMScalar }, 0 },
3596     { "vmovupd",        { EXxS, XM }, 0 },
3597     { "vmovsd",         { EXqS, VexScalarR, XMScalar }, 0 },
3598   },
3599
3600   /* PREFIX_VEX_0F12 */
3601   {
3602     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3603     { "vmovsldup",      { XM, EXx }, 0 },
3604     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3605     { "vmovddup",       { XM, EXymmq }, 0 },
3606   },
3607
3608   /* PREFIX_VEX_0F16 */
3609   {
3610     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3611     { "vmovshdup",      { XM, EXx }, 0 },
3612     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3613   },
3614
3615   /* PREFIX_VEX_0F2A */
3616   {
3617     { Bad_Opcode },
3618     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3619     { Bad_Opcode },
3620     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3621   },
3622
3623   /* PREFIX_VEX_0F2C */
3624   {
3625     { Bad_Opcode },
3626     { "vcvttss2si",     { Gdq, EXxmm_md, EXxEVexS }, 0 },
3627     { Bad_Opcode },
3628     { "vcvttsd2si",     { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3629   },
3630
3631   /* PREFIX_VEX_0F2D */
3632   {
3633     { Bad_Opcode },
3634     { "vcvtss2si",      { Gdq, EXxmm_md, EXxEVexR }, 0 },
3635     { Bad_Opcode },
3636     { "vcvtsd2si",      { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3637   },
3638
3639   /* PREFIX_VEX_0F2E */
3640   {
3641     { "vucomisX",       { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3642     { Bad_Opcode },
3643     { "vucomisX",       { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3644   },
3645
3646   /* PREFIX_VEX_0F2F */
3647   {
3648     { "vcomisX",        { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3649     { Bad_Opcode },
3650     { "vcomisX",        { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3651   },
3652
3653   /* PREFIX_VEX_0F41 */
3654   {
3655     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3656     { Bad_Opcode },
3657     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3658   },
3659
3660   /* PREFIX_VEX_0F42 */
3661   {
3662     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3663     { Bad_Opcode },
3664     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3665   },
3666
3667   /* PREFIX_VEX_0F44 */
3668   {
3669     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3670     { Bad_Opcode },
3671     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3672   },
3673
3674   /* PREFIX_VEX_0F45 */
3675   {
3676     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3677     { Bad_Opcode },
3678     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3679   },
3680
3681   /* PREFIX_VEX_0F46 */
3682   {
3683     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3684     { Bad_Opcode },
3685     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3686   },
3687
3688   /* PREFIX_VEX_0F47 */
3689   {
3690     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3691     { Bad_Opcode },
3692     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3693   },
3694
3695   /* PREFIX_VEX_0F4A */
3696   {
3697     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3698     { Bad_Opcode },
3699     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3700   },
3701
3702   /* PREFIX_VEX_0F4B */
3703   {
3704     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3705     { Bad_Opcode },
3706     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3707   },
3708
3709   /* PREFIX_VEX_0F51 */
3710   {
3711     { "vsqrtps",        { XM, EXx }, 0 },
3712     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
3713     { "vsqrtpd",        { XM, EXx }, 0 },
3714     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
3715   },
3716
3717   /* PREFIX_VEX_0F52 */
3718   {
3719     { "vrsqrtps",       { XM, EXx }, 0 },
3720     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
3721   },
3722
3723   /* PREFIX_VEX_0F53 */
3724   {
3725     { "vrcpps",         { XM, EXx }, 0 },
3726     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3727   },
3728
3729   /* PREFIX_VEX_0F58 */
3730   {
3731     { "vaddps",         { XM, Vex, EXx }, 0 },
3732     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3733     { "vaddpd",         { XM, Vex, EXx }, 0 },
3734     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3735   },
3736
3737   /* PREFIX_VEX_0F59 */
3738   {
3739     { "vmulps",         { XM, Vex, EXx }, 0 },
3740     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3741     { "vmulpd",         { XM, Vex, EXx }, 0 },
3742     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3743   },
3744
3745   /* PREFIX_VEX_0F5A */
3746   {
3747     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
3748     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
3749     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3750     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
3751   },
3752
3753   /* PREFIX_VEX_0F5B */
3754   {
3755     { "vcvtdq2ps",      { XM, EXx }, 0 },
3756     { "vcvttps2dq",     { XM, EXx }, 0 },
3757     { "vcvtps2dq",      { XM, EXx }, 0 },
3758   },
3759
3760   /* PREFIX_VEX_0F5C */
3761   {
3762     { "vsubps",         { XM, Vex, EXx }, 0 },
3763     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3764     { "vsubpd",         { XM, Vex, EXx }, 0 },
3765     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3766   },
3767
3768   /* PREFIX_VEX_0F5D */
3769   {
3770     { "vminps",         { XM, Vex, EXx }, 0 },
3771     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3772     { "vminpd",         { XM, Vex, EXx }, 0 },
3773     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3774   },
3775
3776   /* PREFIX_VEX_0F5E */
3777   {
3778     { "vdivps",         { XM, Vex, EXx }, 0 },
3779     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3780     { "vdivpd",         { XM, Vex, EXx }, 0 },
3781     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3782   },
3783
3784   /* PREFIX_VEX_0F5F */
3785   {
3786     { "vmaxps",         { XM, Vex, EXx }, 0 },
3787     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3788     { "vmaxpd",         { XM, Vex, EXx }, 0 },
3789     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3790   },
3791
3792   /* PREFIX_VEX_0F6F */
3793   {
3794     { Bad_Opcode },
3795     { "vmovdqu",        { XM, EXx }, 0 },
3796     { "vmovdqa",        { XM, EXx }, 0 },
3797   },
3798
3799   /* PREFIX_VEX_0F70 */
3800   {
3801     { Bad_Opcode },
3802     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3803     { "vpshufd",        { XM, EXx, Ib }, 0 },
3804     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3805   },
3806
3807   /* PREFIX_VEX_0F7C */
3808   {
3809     { Bad_Opcode },
3810     { Bad_Opcode },
3811     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3812     { "vhaddps",        { XM, Vex, EXx }, 0 },
3813   },
3814
3815   /* PREFIX_VEX_0F7D */
3816   {
3817     { Bad_Opcode },
3818     { Bad_Opcode },
3819     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3820     { "vhsubps",        { XM, Vex, EXx }, 0 },
3821   },
3822
3823   /* PREFIX_VEX_0F7E */
3824   {
3825     { Bad_Opcode },
3826     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3827     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3828   },
3829
3830   /* PREFIX_VEX_0F7F */
3831   {
3832     { Bad_Opcode },
3833     { "vmovdqu",        { EXxS, XM }, 0 },
3834     { "vmovdqa",        { EXxS, XM }, 0 },
3835   },
3836
3837   /* PREFIX_VEX_0F90 */
3838   {
3839     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
3840     { Bad_Opcode },
3841     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
3842   },
3843
3844   /* PREFIX_VEX_0F91 */
3845   {
3846     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
3847     { Bad_Opcode },
3848     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
3849   },
3850
3851   /* PREFIX_VEX_0F92 */
3852   {
3853     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
3854     { Bad_Opcode },
3855     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
3856     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
3857   },
3858
3859   /* PREFIX_VEX_0F93 */
3860   {
3861     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
3862     { Bad_Opcode },
3863     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
3864     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
3865   },
3866
3867   /* PREFIX_VEX_0F98 */
3868   {
3869     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
3870     { Bad_Opcode },
3871     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
3872   },
3873
3874   /* PREFIX_VEX_0F99 */
3875   {
3876     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
3877     { Bad_Opcode },
3878     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
3879   },
3880
3881   /* PREFIX_VEX_0FC2 */
3882   {
3883     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
3884     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
3885     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
3886     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
3887   },
3888
3889   /* PREFIX_VEX_0FD0 */
3890   {
3891     { Bad_Opcode },
3892     { Bad_Opcode },
3893     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
3894     { "vaddsubps",      { XM, Vex, EXx }, 0 },
3895   },
3896
3897   /* PREFIX_VEX_0FE6 */
3898   {
3899     { Bad_Opcode },
3900     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
3901     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3902     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
3903   },
3904
3905   /* PREFIX_VEX_0FF0 */
3906   {
3907     { Bad_Opcode },
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3911   },
3912
3913   /* PREFIX_VEX_0F3849_X86_64 */
3914   {
3915     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3916     { Bad_Opcode },
3917     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3918     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
3919   },
3920
3921   /* PREFIX_VEX_0F384B_X86_64 */
3922   {
3923     { Bad_Opcode },
3924     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
3925     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
3926     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
3927   },
3928
3929   /* PREFIX_VEX_0F385C_X86_64 */
3930   {
3931     { Bad_Opcode },
3932     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
3933     { Bad_Opcode },
3934   },
3935
3936   /* PREFIX_VEX_0F385E_X86_64 */
3937   {
3938     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
3939     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
3940     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
3941     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
3942   },
3943
3944   /* PREFIX_VEX_0F38F5 */
3945   {
3946     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
3947     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
3948     { Bad_Opcode },
3949     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
3950   },
3951
3952   /* PREFIX_VEX_0F38F6 */
3953   {
3954     { Bad_Opcode },
3955     { Bad_Opcode },
3956     { Bad_Opcode },
3957     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
3958   },
3959
3960   /* PREFIX_VEX_0F38F7 */
3961   {
3962     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
3963     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
3964     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
3965     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
3966   },
3967
3968   /* PREFIX_VEX_0F3AF0 */
3969   {
3970     { Bad_Opcode },
3971     { Bad_Opcode },
3972     { Bad_Opcode },
3973     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
3974   },
3975
3976 #include "i386-dis-evex-prefix.h"
3977 };
3978
3979 static const struct dis386 x86_64_table[][2] = {
3980   /* X86_64_06 */
3981   {
3982     { "pushP", { es }, 0 },
3983   },
3984
3985   /* X86_64_07 */
3986   {
3987     { "popP", { es }, 0 },
3988   },
3989
3990   /* X86_64_0E */
3991   {
3992     { "pushP", { cs }, 0 },
3993   },
3994
3995   /* X86_64_16 */
3996   {
3997     { "pushP", { ss }, 0 },
3998   },
3999
4000   /* X86_64_17 */
4001   {
4002     { "popP", { ss }, 0 },
4003   },
4004
4005   /* X86_64_1E */
4006   {
4007     { "pushP", { ds }, 0 },
4008   },
4009
4010   /* X86_64_1F */
4011   {
4012     { "popP", { ds }, 0 },
4013   },
4014
4015   /* X86_64_27 */
4016   {
4017     { "daa", { XX }, 0 },
4018   },
4019
4020   /* X86_64_2F */
4021   {
4022     { "das", { XX }, 0 },
4023   },
4024
4025   /* X86_64_37 */
4026   {
4027     { "aaa", { XX }, 0 },
4028   },
4029
4030   /* X86_64_3F */
4031   {
4032     { "aas", { XX }, 0 },
4033   },
4034
4035   /* X86_64_60 */
4036   {
4037     { "pushaP", { XX }, 0 },
4038   },
4039
4040   /* X86_64_61 */
4041   {
4042     { "popaP", { XX }, 0 },
4043   },
4044
4045   /* X86_64_62 */
4046   {
4047     { MOD_TABLE (MOD_62_32BIT) },
4048     { EVEX_TABLE (EVEX_0F) },
4049   },
4050
4051   /* X86_64_63 */
4052   {
4053     { "arpl", { Ew, Gw }, 0 },
4054     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4055   },
4056
4057   /* X86_64_6D */
4058   {
4059     { "ins{R|}", { Yzr, indirDX }, 0 },
4060     { "ins{G|}", { Yzr, indirDX }, 0 },
4061   },
4062
4063   /* X86_64_6F */
4064   {
4065     { "outs{R|}", { indirDXr, Xz }, 0 },
4066     { "outs{G|}", { indirDXr, Xz }, 0 },
4067   },
4068
4069   /* X86_64_82 */
4070   {
4071     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4072     { REG_TABLE (REG_80) },
4073   },
4074
4075   /* X86_64_9A */
4076   {
4077     { "{l|}call{T|}", { Ap }, 0 },
4078   },
4079
4080   /* X86_64_C2 */
4081   {
4082     { "retP",           { Iw, BND }, 0 },
4083     { "ret@",           { Iw, BND }, 0 },
4084   },
4085
4086   /* X86_64_C3 */
4087   {
4088     { "retP",           { BND }, 0 },
4089     { "ret@",           { BND }, 0 },
4090   },
4091
4092   /* X86_64_C4 */
4093   {
4094     { MOD_TABLE (MOD_C4_32BIT) },
4095     { VEX_C4_TABLE (VEX_0F) },
4096   },
4097
4098   /* X86_64_C5 */
4099   {
4100     { MOD_TABLE (MOD_C5_32BIT) },
4101     { VEX_C5_TABLE (VEX_0F) },
4102   },
4103
4104   /* X86_64_CE */
4105   {
4106     { "into", { XX }, 0 },
4107   },
4108
4109   /* X86_64_D4 */
4110   {
4111     { "aam", { Ib }, 0 },
4112   },
4113
4114   /* X86_64_D5 */
4115   {
4116     { "aad", { Ib }, 0 },
4117   },
4118
4119   /* X86_64_E8 */
4120   {
4121     { "callP",          { Jv, BND }, 0 },
4122     { "call@",          { Jv, BND }, 0 }
4123   },
4124
4125   /* X86_64_E9 */
4126   {
4127     { "jmpP",           { Jv, BND }, 0 },
4128     { "jmp@",           { Jv, BND }, 0 }
4129   },
4130
4131   /* X86_64_EA */
4132   {
4133     { "{l|}jmp{T|}", { Ap }, 0 },
4134   },
4135
4136   /* X86_64_0F01_REG_0 */
4137   {
4138     { "sgdt{Q|Q}", { M }, 0 },
4139     { "sgdt", { M }, 0 },
4140   },
4141
4142   /* X86_64_0F01_REG_1 */
4143   {
4144     { "sidt{Q|Q}", { M }, 0 },
4145     { "sidt", { M }, 0 },
4146   },
4147
4148   /* X86_64_0F01_REG_2 */
4149   {
4150     { "lgdt{Q|Q}", { M }, 0 },
4151     { "lgdt", { M }, 0 },
4152   },
4153
4154   /* X86_64_0F01_REG_3 */
4155   {
4156     { "lidt{Q|Q}", { M }, 0 },
4157     { "lidt", { M }, 0 },
4158   },
4159
4160   /* X86_64_VEX_0F3849 */
4161   {
4162     { Bad_Opcode },
4163     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4164   },
4165
4166   /* X86_64_VEX_0F384B */
4167   {
4168     { Bad_Opcode },
4169     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4170   },
4171
4172   /* X86_64_VEX_0F385C */
4173   {
4174     { Bad_Opcode },
4175     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4176   },
4177
4178   /* X86_64_VEX_0F385E */
4179   {
4180     { Bad_Opcode },
4181     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4182   },
4183 };
4184
4185 static const struct dis386 three_byte_table[][256] = {
4186
4187   /* THREE_BYTE_0F38 */
4188   {
4189     /* 00 */
4190     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4191     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4192     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4193     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4194     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4195     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4196     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4197     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4198     /* 08 */
4199     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4200     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4201     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4202     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4203     { Bad_Opcode },
4204     { Bad_Opcode },
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     /* 10 */
4208     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4209     { Bad_Opcode },
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4213     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4214     { Bad_Opcode },
4215     { "ptest",  { XM, EXx }, PREFIX_DATA },
4216     /* 18 */
4217     { Bad_Opcode },
4218     { Bad_Opcode },
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4222     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4223     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4224     { Bad_Opcode },
4225     /* 20 */
4226     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4227     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4228     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4229     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4230     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4231     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4232     { Bad_Opcode },
4233     { Bad_Opcode },
4234     /* 28 */
4235     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4236     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4237     { MOD_TABLE (MOD_0F382A) },
4238     { "packusdw", { XM, EXx }, PREFIX_DATA },
4239     { Bad_Opcode },
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     /* 30 */
4244     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4245     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4246     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4247     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4248     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4249     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4250     { Bad_Opcode },
4251     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4252     /* 38 */
4253     { "pminsb", { XM, EXx }, PREFIX_DATA },
4254     { "pminsd", { XM, EXx }, PREFIX_DATA },
4255     { "pminuw", { XM, EXx }, PREFIX_DATA },
4256     { "pminud", { XM, EXx }, PREFIX_DATA },
4257     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4258     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4259     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4260     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4261     /* 40 */
4262     { "pmulld", { XM, EXx }, PREFIX_DATA },
4263     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     /* 48 */
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     /* 50 */
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     /* 58 */
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { Bad_Opcode },
4297     /* 60 */
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     /* 68 */
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     /* 70 */
4316     { Bad_Opcode },
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     /* 78 */
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     /* 80 */
4334     { "invept", { Gm, Mo }, PREFIX_DATA },
4335     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4336     { "invpcid", { Gm, M }, PREFIX_DATA },
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     /* 88 */
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     /* 90 */
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { Bad_Opcode },
4360     /* 98 */
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     /* a0 */
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     /* a8 */
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     /* b0 */
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     /* b8 */
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { Bad_Opcode },
4405     /* c0 */
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     /* c8 */
4415     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4416     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4417     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4418     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4419     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4420     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4421     { Bad_Opcode },
4422     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4423     /* d0 */
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     /* d8 */
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { "aesimc", { XM, EXx }, PREFIX_DATA },
4437     { "aesenc", { XM, EXx }, PREFIX_DATA },
4438     { "aesenclast", { XM, EXx }, PREFIX_DATA },
4439     { "aesdec", { XM, EXx }, PREFIX_DATA },
4440     { "aesdeclast", { XM, EXx }, PREFIX_DATA },
4441     /* e0 */
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     /* e8 */
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     /* f0 */
4460     { PREFIX_TABLE (PREFIX_0F38F0) },
4461     { PREFIX_TABLE (PREFIX_0F38F1) },
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { MOD_TABLE (MOD_0F38F5) },
4466     { PREFIX_TABLE (PREFIX_0F38F6) },
4467     { Bad_Opcode },
4468     /* f8 */
4469     { PREFIX_TABLE (PREFIX_0F38F8) },
4470     { MOD_TABLE (MOD_0F38F9) },
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477   },
4478   /* THREE_BYTE_0F3A */
4479   {
4480     /* 00 */
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     /* 08 */
4490     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4491     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4492     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4493     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4494     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4495     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4496     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4497     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4498     /* 10 */
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4504     { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4505     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4506     { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4507     /* 18 */
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     /* 20 */
4517     { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4518     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4519     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     /* 28 */
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     /* 30 */
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     /* 38 */
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     /* 40 */
4553     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4554     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4555     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4556     { Bad_Opcode },
4557     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     /* 48 */
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     /* 50 */
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     /* 58 */
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     /* 60 */
4589     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4590     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4591     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4592     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     /* 68 */
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     /* 70 */
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     /* 78 */
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     /* 80 */
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     /* 88 */
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     /* 90 */
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { Bad_Opcode },
4651     /* 98 */
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     /* a0 */
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     /* a8 */
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     /* b0 */
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     /* b8 */
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     /* c0 */
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     /* c8 */
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4711     { Bad_Opcode },
4712     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4713     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4714     /* d0 */
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     /* d8 */
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4732     /* e0 */
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     /* e8 */
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     /* f0 */
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     /* f8 */
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768   },
4769 };
4770
4771 static const struct dis386 xop_table[][256] = {
4772   /* XOP_08 */
4773   {
4774     /* 00 */
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     /* 08 */
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     /* 10 */
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     /* 18 */
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     /* 20 */
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     /* 28 */
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     /* 30 */
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     /* 38 */
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     /* 40 */
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     /* 48 */
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     /* 50 */
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     /* 58 */
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     /* 60 */
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     /* 68 */
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     /* 70 */
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     /* 78 */
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     /* 80 */
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
4925     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
4926     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
4927     /* 88 */
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
4935     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
4936     /* 90 */
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
4943     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
4944     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
4945     /* 98 */
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
4953     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
4954     /* a0 */
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
4958     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
4962     { Bad_Opcode },
4963     /* a8 */
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     /* b0 */
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
4980     { Bad_Opcode },
4981     /* b8 */
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     /* c0 */
4991     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
4992     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
4993     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
4994     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     /* c8 */
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5005     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5006     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5007     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5008     /* d0 */
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     /* d8 */
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     /* e0 */
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     /* e8 */
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5041     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5042     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5043     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5044     /* f0 */
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     /* f8 */
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062   },
5063   /* XOP_09 */
5064   {
5065     /* 00 */
5066     { Bad_Opcode },
5067     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5068     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     /* 08 */
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     /* 10 */
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     /* 18 */
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     /* 20 */
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     /* 28 */
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     /* 30 */
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     /* 38 */
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     /* 40 */
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     /* 48 */
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     /* 50 */
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     /* 58 */
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     /* 60 */
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     /* 68 */
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     /* 70 */
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     /* 78 */
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     /* 80 */
5210     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5211     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5212     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5213     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     /* 88 */
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     /* 90 */
5228     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5229     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5230     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5231     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5232     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5233     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5234     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5235     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5236     /* 98 */
5237     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5238     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5239     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5240     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     /* a0 */
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     /* a8 */
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     /* b0 */
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     /* b8 */
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     /* c0 */
5282     { Bad_Opcode },
5283     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5284     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5285     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5289     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5290     /* c8 */
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     /* d0 */
5300     { Bad_Opcode },
5301     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5302     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5303     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5307     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5308     /* d8 */
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     /* e0 */
5318     { Bad_Opcode },
5319     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5320     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5321     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     /* e8 */
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     /* f0 */
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     /* f8 */
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353   },
5354   /* XOP_0A */
5355   {
5356     /* 00 */
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     /* 08 */
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     /* 10 */
5375     { "bextrS", { Gdq, Edq, Id }, 0 },
5376     { Bad_Opcode },
5377     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     /* 18 */
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     /* 20 */
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     /* 28 */
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     /* 30 */
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     /* 38 */
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     /* 40 */
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     /* 48 */
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     /* 50 */
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     /* 58 */
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     /* 60 */
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     /* 68 */
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     /* 70 */
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     /* 78 */
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     /* 80 */
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     /* 88 */
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     /* 90 */
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     /* 98 */
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     /* a0 */
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     /* a8 */
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     /* b0 */
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     /* b8 */
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     /* c0 */
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     /* c8 */
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     /* d0 */
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     /* d8 */
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     /* e0 */
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     /* e8 */
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     /* f0 */
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     /* f8 */
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644   },
5645 };
5646
5647 static const struct dis386 vex_table[][256] = {
5648   /* VEX_0F */
5649   {
5650     /* 00 */
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     /* 08 */
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     /* 10 */
5669     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5670     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5671     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5672     { MOD_TABLE (MOD_VEX_0F13) },
5673     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5674     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5675     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5676     { MOD_TABLE (MOD_VEX_0F17) },
5677     /* 18 */
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     /* 20 */
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     /* 28 */
5696     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5697     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5698     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5699     { MOD_TABLE (MOD_VEX_0F2B) },
5700     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5701     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5702     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5703     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5704     /* 30 */
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     /* 38 */
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     /* 40 */
5723     { Bad_Opcode },
5724     { PREFIX_TABLE (PREFIX_VEX_0F41) },
5725     { PREFIX_TABLE (PREFIX_VEX_0F42) },
5726     { Bad_Opcode },
5727     { PREFIX_TABLE (PREFIX_VEX_0F44) },
5728     { PREFIX_TABLE (PREFIX_VEX_0F45) },
5729     { PREFIX_TABLE (PREFIX_VEX_0F46) },
5730     { PREFIX_TABLE (PREFIX_VEX_0F47) },
5731     /* 48 */
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5735     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     /* 50 */
5741     { MOD_TABLE (MOD_VEX_0F50) },
5742     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5743     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5744     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5745     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5746     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5747     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5748     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5749     /* 58 */
5750     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5751     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5752     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5753     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5754     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5755     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5756     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5757     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5758     /* 60 */
5759     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5760     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5761     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5762     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5763     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5764     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5765     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5766     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5767     /* 68 */
5768     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5769     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
5770     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
5771     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
5772     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5773     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5774     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5775     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5776     /* 70 */
5777     { PREFIX_TABLE (PREFIX_VEX_0F70) },
5778     { REG_TABLE (REG_VEX_0F71) },
5779     { REG_TABLE (REG_VEX_0F72) },
5780     { REG_TABLE (REG_VEX_0F73) },
5781     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
5782     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
5783     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
5784     { VEX_LEN_TABLE (VEX_LEN_0F77) },
5785     /* 78 */
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5791     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5792     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5793     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5794     /* 80 */
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     /* 88 */
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     /* 90 */
5813     { PREFIX_TABLE (PREFIX_VEX_0F90) },
5814     { PREFIX_TABLE (PREFIX_VEX_0F91) },
5815     { PREFIX_TABLE (PREFIX_VEX_0F92) },
5816     { PREFIX_TABLE (PREFIX_VEX_0F93) },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     /* 98 */
5822     { PREFIX_TABLE (PREFIX_VEX_0F98) },
5823     { PREFIX_TABLE (PREFIX_VEX_0F99) },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     /* a0 */
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     /* a8 */
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { REG_TABLE (REG_VEX_0FAE) },
5847     { Bad_Opcode },
5848     /* b0 */
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     /* b8 */
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     /* c0 */
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
5870     { Bad_Opcode },
5871     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
5872     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
5873     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
5874     { Bad_Opcode },
5875     /* c8 */
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     /* d0 */
5885     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
5886     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
5887     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
5888     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
5889     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
5890     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
5891     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
5892     { MOD_TABLE (MOD_VEX_0FD7) },
5893     /* d8 */
5894     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
5895     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
5896     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
5897     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
5898     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
5899     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
5900     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
5901     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
5902     /* e0 */
5903     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
5904     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
5905     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
5906     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
5907     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
5908     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
5909     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
5910     { MOD_TABLE (MOD_VEX_0FE7) },
5911     /* e8 */
5912     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
5913     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
5914     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
5915     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
5916     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
5917     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
5918     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
5919     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
5920     /* f0 */
5921     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
5922     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
5923     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
5924     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
5925     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
5926     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
5927     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
5928     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
5929     /* f8 */
5930     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
5931     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
5932     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
5933     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
5934     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
5935     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
5936     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
5937     { Bad_Opcode },
5938   },
5939   /* VEX_0F38 */
5940   {
5941     /* 00 */
5942     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
5943     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
5944     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
5945     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
5946     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
5947     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
5948     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
5949     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
5950     /* 08 */
5951     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
5952     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
5953     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
5954     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
5955     { VEX_W_TABLE (VEX_W_0F380C) },
5956     { VEX_W_TABLE (VEX_W_0F380D) },
5957     { VEX_W_TABLE (VEX_W_0F380E) },
5958     { VEX_W_TABLE (VEX_W_0F380F) },
5959     /* 10 */
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { VEX_W_TABLE (VEX_W_0F3813) },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
5967     { "vptest",         { XM, EXx }, PREFIX_DATA },
5968     /* 18 */
5969     { VEX_W_TABLE (VEX_W_0F3818) },
5970     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
5971     { MOD_TABLE (MOD_VEX_0F381A) },
5972     { Bad_Opcode },
5973     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
5974     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
5975     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
5976     { Bad_Opcode },
5977     /* 20 */
5978     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
5979     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
5980     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
5981     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
5982     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
5983     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     /* 28 */
5987     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
5988     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
5989     { MOD_TABLE (MOD_VEX_0F382A) },
5990     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
5991     { MOD_TABLE (MOD_VEX_0F382C) },
5992     { MOD_TABLE (MOD_VEX_0F382D) },
5993     { MOD_TABLE (MOD_VEX_0F382E) },
5994     { MOD_TABLE (MOD_VEX_0F382F) },
5995     /* 30 */
5996     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
5997     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
5998     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
5999     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6000     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6001     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6002     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6003     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6004     /* 38 */
6005     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6006     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6007     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6008     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6009     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6010     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6011     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6012     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6013     /* 40 */
6014     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6015     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6020     { VEX_W_TABLE (VEX_W_0F3846) },
6021     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6022     /* 48 */
6023     { Bad_Opcode },
6024     { X86_64_TABLE (X86_64_VEX_0F3849) },
6025     { Bad_Opcode },
6026     { X86_64_TABLE (X86_64_VEX_0F384B) },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     /* 50 */
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     /* 58 */
6041     { VEX_W_TABLE (VEX_W_0F3858) },
6042     { VEX_W_TABLE (VEX_W_0F3859) },
6043     { MOD_TABLE (MOD_VEX_0F385A) },
6044     { Bad_Opcode },
6045     { X86_64_TABLE (X86_64_VEX_0F385C) },
6046     { Bad_Opcode },
6047     { X86_64_TABLE (X86_64_VEX_0F385E) },
6048     { Bad_Opcode },
6049     /* 60 */
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     /* 68 */
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     /* 70 */
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     /* 78 */
6077     { VEX_W_TABLE (VEX_W_0F3878) },
6078     { VEX_W_TABLE (VEX_W_0F3879) },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     /* 80 */
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     /* 88 */
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { MOD_TABLE (MOD_VEX_0F388C) },
6100     { Bad_Opcode },
6101     { MOD_TABLE (MOD_VEX_0F388E) },
6102     { Bad_Opcode },
6103     /* 90 */
6104     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6105     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6106     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6107     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6111     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6112     /* 98 */
6113     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6114     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6115     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6116     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6117     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6118     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6119     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6120     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6121     /* a0 */
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6129     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6130     /* a8 */
6131     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6132     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6133     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6134     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6135     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6136     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6137     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6138     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6139     /* b0 */
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6147     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6148     /* b8 */
6149     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6150     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6151     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6152     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6153     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6154     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6155     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6156     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6157     /* c0 */
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     /* c8 */
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { VEX_W_TABLE (VEX_W_0F38CF) },
6175     /* d0 */
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     /* d8 */
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6189     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6190     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6191     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6192     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6193     /* e0 */
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     /* e8 */
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     /* f0 */
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6215     { REG_TABLE (REG_VEX_0F38F3) },
6216     { Bad_Opcode },
6217     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6218     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6219     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6220     /* f8 */
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229   },
6230   /* VEX_0F3A */
6231   {
6232     /* 00 */
6233     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6234     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6235     { VEX_W_TABLE (VEX_W_0F3A02) },
6236     { Bad_Opcode },
6237     { VEX_W_TABLE (VEX_W_0F3A04) },
6238     { VEX_W_TABLE (VEX_W_0F3A05) },
6239     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6240     { Bad_Opcode },
6241     /* 08 */
6242     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6243     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6244     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6245     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6246     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6247     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6248     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6249     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6250     /* 10 */
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6256     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6257     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6258     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6259     /* 18 */
6260     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6261     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { VEX_W_TABLE (VEX_W_0F3A1D) },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     /* 20 */
6269     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6270     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6271     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     /* 28 */
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     /* 30 */
6287     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6288     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6289     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6290     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     /* 38 */
6296     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6297     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     /* 40 */
6305     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6306     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6307     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6308     { Bad_Opcode },
6309     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6310     { Bad_Opcode },
6311     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6312     { Bad_Opcode },
6313     /* 48 */
6314     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6315     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6316     { VEX_W_TABLE (VEX_W_0F3A4A) },
6317     { VEX_W_TABLE (VEX_W_0F3A4B) },
6318     { VEX_W_TABLE (VEX_W_0F3A4C) },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     /* 50 */
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     /* 58 */
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6337     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6338     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6339     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6340     /* 60 */
6341     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6342     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6343     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6344     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     /* 68 */
6350     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6351     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6352     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6353     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6354     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6355     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6356     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6357     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6358     /* 70 */
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     /* 78 */
6368     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6369     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6370     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6371     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6372     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6373     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6374     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6375     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6376     /* 80 */
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     /* 88 */
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     /* 90 */
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     /* 98 */
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     /* a0 */
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     /* a8 */
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     /* b0 */
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     /* b8 */
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     /* c0 */
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     /* c8 */
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { VEX_W_TABLE (VEX_W_0F3ACE) },
6465     { VEX_W_TABLE (VEX_W_0F3ACF) },
6466     /* d0 */
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     /* d8 */
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6484     /* e0 */
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     /* e8 */
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     /* f0 */
6503     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     /* f8 */
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520   },
6521 };
6522
6523 #include "i386-dis-evex.h"
6524
6525 static const struct dis386 vex_len_table[][2] = {
6526   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6527   {
6528     { "vmovlpX",        { XM, Vex, EXq }, 0 },
6529   },
6530
6531   /* VEX_LEN_0F12_P_0_M_1 */
6532   {
6533     { "vmovhlps",       { XM, Vex, EXq }, 0 },
6534   },
6535
6536   /* VEX_LEN_0F13_M_0 */
6537   {
6538     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6539   },
6540
6541   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6542   {
6543     { "vmovhpX",        { XM, Vex, EXq }, 0 },
6544   },
6545
6546   /* VEX_LEN_0F16_P_0_M_1 */
6547   {
6548     { "vmovlhps",       { XM, Vex, EXq }, 0 },
6549   },
6550
6551   /* VEX_LEN_0F17_M_0 */
6552   {
6553     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6554   },
6555
6556   /* VEX_LEN_0F41_P_0 */
6557   {
6558     { Bad_Opcode },
6559     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6560   },
6561   /* VEX_LEN_0F41_P_2 */
6562   {
6563     { Bad_Opcode },
6564     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6565   },
6566   /* VEX_LEN_0F42_P_0 */
6567   {
6568     { Bad_Opcode },
6569     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6570   },
6571   /* VEX_LEN_0F42_P_2 */
6572   {
6573     { Bad_Opcode },
6574     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6575   },
6576   /* VEX_LEN_0F44_P_0 */
6577   {
6578     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6579   },
6580   /* VEX_LEN_0F44_P_2 */
6581   {
6582     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6583   },
6584   /* VEX_LEN_0F45_P_0 */
6585   {
6586     { Bad_Opcode },
6587     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6588   },
6589   /* VEX_LEN_0F45_P_2 */
6590   {
6591     { Bad_Opcode },
6592     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6593   },
6594   /* VEX_LEN_0F46_P_0 */
6595   {
6596     { Bad_Opcode },
6597     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6598   },
6599   /* VEX_LEN_0F46_P_2 */
6600   {
6601     { Bad_Opcode },
6602     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6603   },
6604   /* VEX_LEN_0F47_P_0 */
6605   {
6606     { Bad_Opcode },
6607     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6608   },
6609   /* VEX_LEN_0F47_P_2 */
6610   {
6611     { Bad_Opcode },
6612     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6613   },
6614   /* VEX_LEN_0F4A_P_0 */
6615   {
6616     { Bad_Opcode },
6617     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6618   },
6619   /* VEX_LEN_0F4A_P_2 */
6620   {
6621     { Bad_Opcode },
6622     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6623   },
6624   /* VEX_LEN_0F4B_P_0 */
6625   {
6626     { Bad_Opcode },
6627     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6628   },
6629   /* VEX_LEN_0F4B_P_2 */
6630   {
6631     { Bad_Opcode },
6632     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6633   },
6634
6635   /* VEX_LEN_0F6E */
6636   {
6637     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6638   },
6639
6640   /* VEX_LEN_0F77 */
6641   {
6642     { "vzeroupper",     { XX }, 0 },
6643     { "vzeroall",       { XX }, 0 },
6644   },
6645
6646   /* VEX_LEN_0F7E_P_1 */
6647   {
6648     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
6649   },
6650
6651   /* VEX_LEN_0F7E_P_2 */
6652   {
6653     { "vmovK",          { Edq, XMScalar }, 0 },
6654   },
6655
6656   /* VEX_LEN_0F90_P_0 */
6657   {
6658     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6659   },
6660
6661   /* VEX_LEN_0F90_P_2 */
6662   {
6663     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6664   },
6665
6666   /* VEX_LEN_0F91_P_0 */
6667   {
6668     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6669   },
6670
6671   /* VEX_LEN_0F91_P_2 */
6672   {
6673     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6674   },
6675
6676   /* VEX_LEN_0F92_P_0 */
6677   {
6678     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6679   },
6680
6681   /* VEX_LEN_0F92_P_2 */
6682   {
6683     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6684   },
6685
6686   /* VEX_LEN_0F92_P_3 */
6687   {
6688     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6689   },
6690
6691   /* VEX_LEN_0F93_P_0 */
6692   {
6693     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6694   },
6695
6696   /* VEX_LEN_0F93_P_2 */
6697   {
6698     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6699   },
6700
6701   /* VEX_LEN_0F93_P_3 */
6702   {
6703     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6704   },
6705
6706   /* VEX_LEN_0F98_P_0 */
6707   {
6708     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6709   },
6710
6711   /* VEX_LEN_0F98_P_2 */
6712   {
6713     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6714   },
6715
6716   /* VEX_LEN_0F99_P_0 */
6717   {
6718     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6719   },
6720
6721   /* VEX_LEN_0F99_P_2 */
6722   {
6723     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6724   },
6725
6726   /* VEX_LEN_0FAE_R_2_M_0 */
6727   {
6728     { "vldmxcsr",       { Md }, 0 },
6729   },
6730
6731   /* VEX_LEN_0FAE_R_3_M_0 */
6732   {
6733     { "vstmxcsr",       { Md }, 0 },
6734   },
6735
6736   /* VEX_LEN_0FC4 */
6737   {
6738     { "vpinsrw",        { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6739   },
6740
6741   /* VEX_LEN_0FC5 */
6742   {
6743     { "vpextrw",        { Gdq, XS, Ib }, PREFIX_DATA },
6744   },
6745
6746   /* VEX_LEN_0FD6 */
6747   {
6748     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6749   },
6750
6751   /* VEX_LEN_0FF7 */
6752   {
6753     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6754   },
6755
6756   /* VEX_LEN_0F3816 */
6757   {
6758     { Bad_Opcode },
6759     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6760   },
6761
6762   /* VEX_LEN_0F3819 */
6763   {
6764     { Bad_Opcode },
6765     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6766   },
6767
6768   /* VEX_LEN_0F381A_M_0 */
6769   {
6770     { Bad_Opcode },
6771     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6772   },
6773
6774   /* VEX_LEN_0F3836 */
6775   {
6776     { Bad_Opcode },
6777     { VEX_W_TABLE (VEX_W_0F3836) },
6778   },
6779
6780   /* VEX_LEN_0F3841 */
6781   {
6782     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6783   },
6784
6785    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6786   {
6787     { "ldtilecfg", { M }, 0 },
6788   },
6789
6790   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6791   {
6792     { "tilerelease", { Skip_MODRM }, 0 },
6793   },
6794
6795   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6796   {
6797     { "sttilecfg", { M }, 0 },
6798   },
6799
6800   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6801   {
6802     { "tilezero", { TMM, Skip_MODRM }, 0 },
6803   },
6804
6805   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6806   {
6807     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6808   },
6809   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6810   {
6811     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6812   },
6813
6814   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6815   {
6816     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6817   },
6818
6819   /* VEX_LEN_0F385A_M_0 */
6820   {
6821     { Bad_Opcode },
6822     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6823   },
6824
6825   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6826   {
6827     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6828   },
6829
6830   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6831   {
6832     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6833   },
6834
6835   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6836   {
6837     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6838   },
6839
6840   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6841   {
6842     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6843   },
6844
6845   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6846   {
6847     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6848   },
6849
6850   /* VEX_LEN_0F38DB */
6851   {
6852     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
6853   },
6854
6855   /* VEX_LEN_0F38F2 */
6856   {
6857     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6858   },
6859
6860   /* VEX_LEN_0F38F3_R_1 */
6861   {
6862     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
6863   },
6864
6865   /* VEX_LEN_0F38F3_R_2 */
6866   {
6867     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
6868   },
6869
6870   /* VEX_LEN_0F38F3_R_3 */
6871   {
6872     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
6873   },
6874
6875   /* VEX_LEN_0F38F5_P_0 */
6876   {
6877     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
6878   },
6879
6880   /* VEX_LEN_0F38F5_P_1 */
6881   {
6882     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
6883   },
6884
6885   /* VEX_LEN_0F38F5_P_3 */
6886   {
6887     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
6888   },
6889
6890   /* VEX_LEN_0F38F6_P_3 */
6891   {
6892     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
6893   },
6894
6895   /* VEX_LEN_0F38F7_P_0 */
6896   {
6897     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
6898   },
6899
6900   /* VEX_LEN_0F38F7_P_1 */
6901   {
6902     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
6903   },
6904
6905   /* VEX_LEN_0F38F7_P_2 */
6906   {
6907     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
6908   },
6909
6910   /* VEX_LEN_0F38F7_P_3 */
6911   {
6912     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
6913   },
6914
6915   /* VEX_LEN_0F3A00 */
6916   {
6917     { Bad_Opcode },
6918     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
6919   },
6920
6921   /* VEX_LEN_0F3A01 */
6922   {
6923     { Bad_Opcode },
6924     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
6925   },
6926
6927   /* VEX_LEN_0F3A06 */
6928   {
6929     { Bad_Opcode },
6930     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
6931   },
6932
6933   /* VEX_LEN_0F3A14 */
6934   {
6935     { "vpextrb",        { Edqb, XM, Ib }, PREFIX_DATA },
6936   },
6937
6938   /* VEX_LEN_0F3A15 */
6939   {
6940     { "vpextrw",        { Edqw, XM, Ib }, PREFIX_DATA },
6941   },
6942
6943   /* VEX_LEN_0F3A16  */
6944   {
6945     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
6946   },
6947
6948   /* VEX_LEN_0F3A17 */
6949   {
6950     { "vextractps",     { Edqd, XM, Ib }, PREFIX_DATA },
6951   },
6952
6953   /* VEX_LEN_0F3A18 */
6954   {
6955     { Bad_Opcode },
6956     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
6957   },
6958
6959   /* VEX_LEN_0F3A19 */
6960   {
6961     { Bad_Opcode },
6962     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
6963   },
6964
6965   /* VEX_LEN_0F3A20 */
6966   {
6967     { "vpinsrb",        { XM, Vex, Edqb, Ib }, PREFIX_DATA },
6968   },
6969
6970   /* VEX_LEN_0F3A21 */
6971   {
6972     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
6973   },
6974
6975   /* VEX_LEN_0F3A22 */
6976   {
6977     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
6978   },
6979
6980   /* VEX_LEN_0F3A30 */
6981   {
6982     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
6983   },
6984
6985   /* VEX_LEN_0F3A31 */
6986   {
6987     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
6988   },
6989
6990   /* VEX_LEN_0F3A32 */
6991   {
6992     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
6993   },
6994
6995   /* VEX_LEN_0F3A33 */
6996   {
6997     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
6998   },
6999
7000   /* VEX_LEN_0F3A38 */
7001   {
7002     { Bad_Opcode },
7003     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7004   },
7005
7006   /* VEX_LEN_0F3A39 */
7007   {
7008     { Bad_Opcode },
7009     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7010   },
7011
7012   /* VEX_LEN_0F3A41 */
7013   {
7014     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7015   },
7016
7017   /* VEX_LEN_0F3A46 */
7018   {
7019     { Bad_Opcode },
7020     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7021   },
7022
7023   /* VEX_LEN_0F3A60 */
7024   {
7025     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7026   },
7027
7028   /* VEX_LEN_0F3A61 */
7029   {
7030     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7031   },
7032
7033   /* VEX_LEN_0F3A62 */
7034   {
7035     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7036   },
7037
7038   /* VEX_LEN_0F3A63 */
7039   {
7040     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7041   },
7042
7043   /* VEX_LEN_0F3ADF */
7044   {
7045     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7046   },
7047
7048   /* VEX_LEN_0F3AF0_P_3 */
7049   {
7050     { "rorxS",          { Gdq, Edq, Ib }, 0 },
7051   },
7052
7053   /* VEX_LEN_0FXOP_08_85 */
7054   {
7055     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7056   },
7057
7058   /* VEX_LEN_0FXOP_08_86 */
7059   {
7060     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7061   },
7062
7063   /* VEX_LEN_0FXOP_08_87 */
7064   {
7065     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7066   },
7067
7068   /* VEX_LEN_0FXOP_08_8E */
7069   {
7070     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7071   },
7072
7073   /* VEX_LEN_0FXOP_08_8F */
7074   {
7075     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7076   },
7077
7078   /* VEX_LEN_0FXOP_08_95 */
7079   {
7080     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7081   },
7082
7083   /* VEX_LEN_0FXOP_08_96 */
7084   {
7085     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7086   },
7087
7088   /* VEX_LEN_0FXOP_08_97 */
7089   {
7090     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7091   },
7092
7093   /* VEX_LEN_0FXOP_08_9E */
7094   {
7095     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7096   },
7097
7098   /* VEX_LEN_0FXOP_08_9F */
7099   {
7100     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7101   },
7102
7103   /* VEX_LEN_0FXOP_08_A3 */
7104   {
7105     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7106   },
7107
7108   /* VEX_LEN_0FXOP_08_A6 */
7109   {
7110     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7111   },
7112
7113   /* VEX_LEN_0FXOP_08_B6 */
7114   {
7115     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7116   },
7117
7118   /* VEX_LEN_0FXOP_08_C0 */
7119   {
7120     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7121   },
7122
7123   /* VEX_LEN_0FXOP_08_C1 */
7124   {
7125     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7126   },
7127
7128   /* VEX_LEN_0FXOP_08_C2 */
7129   {
7130     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7131   },
7132
7133   /* VEX_LEN_0FXOP_08_C3 */
7134   {
7135     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7136   },
7137
7138   /* VEX_LEN_0FXOP_08_CC */
7139   {
7140     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7141   },
7142
7143   /* VEX_LEN_0FXOP_08_CD */
7144   {
7145     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7146   },
7147
7148   /* VEX_LEN_0FXOP_08_CE */
7149   {
7150     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7151   },
7152
7153   /* VEX_LEN_0FXOP_08_CF */
7154   {
7155     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7156   },
7157
7158   /* VEX_LEN_0FXOP_08_EC */
7159   {
7160     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7161   },
7162
7163   /* VEX_LEN_0FXOP_08_ED */
7164   {
7165     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7166   },
7167
7168   /* VEX_LEN_0FXOP_08_EE */
7169   {
7170     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7171   },
7172
7173   /* VEX_LEN_0FXOP_08_EF */
7174   {
7175     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7176   },
7177
7178   /* VEX_LEN_0FXOP_09_01 */
7179   {
7180     { REG_TABLE (REG_0FXOP_09_01_L_0) },
7181   },
7182
7183   /* VEX_LEN_0FXOP_09_02 */
7184   {
7185     { REG_TABLE (REG_0FXOP_09_02_L_0) },
7186   },
7187
7188   /* VEX_LEN_0FXOP_09_12_M_1 */
7189   {
7190     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7191   },
7192
7193   /* VEX_LEN_0FXOP_09_82_W_0 */
7194   {
7195     { "vfrczss",        { XM, EXd }, 0 },
7196   },
7197
7198   /* VEX_LEN_0FXOP_09_83_W_0 */
7199   {
7200     { "vfrczsd",        { XM, EXq }, 0 },
7201   },
7202
7203   /* VEX_LEN_0FXOP_09_90 */
7204   {
7205     { "vprotb",         { XM, EXx, VexW }, 0 },
7206   },
7207
7208   /* VEX_LEN_0FXOP_09_91 */
7209   {
7210     { "vprotw",         { XM, EXx, VexW }, 0 },
7211   },
7212
7213   /* VEX_LEN_0FXOP_09_92 */
7214   {
7215     { "vprotd",         { XM, EXx, VexW }, 0 },
7216   },
7217
7218   /* VEX_LEN_0FXOP_09_93 */
7219   {
7220     { "vprotq",         { XM, EXx, VexW }, 0 },
7221   },
7222
7223   /* VEX_LEN_0FXOP_09_94 */
7224   {
7225     { "vpshlb",         { XM, EXx, VexW }, 0 },
7226   },
7227
7228   /* VEX_LEN_0FXOP_09_95 */
7229   {
7230     { "vpshlw",         { XM, EXx, VexW }, 0 },
7231   },
7232
7233   /* VEX_LEN_0FXOP_09_96 */
7234   {
7235     { "vpshld",         { XM, EXx, VexW }, 0 },
7236   },
7237
7238   /* VEX_LEN_0FXOP_09_97 */
7239   {
7240     { "vpshlq",         { XM, EXx, VexW }, 0 },
7241   },
7242
7243   /* VEX_LEN_0FXOP_09_98 */
7244   {
7245     { "vpshab",         { XM, EXx, VexW }, 0 },
7246   },
7247
7248   /* VEX_LEN_0FXOP_09_99 */
7249   {
7250     { "vpshaw",         { XM, EXx, VexW }, 0 },
7251   },
7252
7253   /* VEX_LEN_0FXOP_09_9A */
7254   {
7255     { "vpshad",         { XM, EXx, VexW }, 0 },
7256   },
7257
7258   /* VEX_LEN_0FXOP_09_9B */
7259   {
7260     { "vpshaq",         { XM, EXx, VexW }, 0 },
7261   },
7262
7263   /* VEX_LEN_0FXOP_09_C1 */
7264   {
7265     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7266   },
7267
7268   /* VEX_LEN_0FXOP_09_C2 */
7269   {
7270     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7271   },
7272
7273   /* VEX_LEN_0FXOP_09_C3 */
7274   {
7275     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7276   },
7277
7278   /* VEX_LEN_0FXOP_09_C6 */
7279   {
7280     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7281   },
7282
7283   /* VEX_LEN_0FXOP_09_C7 */
7284   {
7285     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7286   },
7287
7288   /* VEX_LEN_0FXOP_09_CB */
7289   {
7290     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7291   },
7292
7293   /* VEX_LEN_0FXOP_09_D1 */
7294   {
7295     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7296   },
7297
7298   /* VEX_LEN_0FXOP_09_D2 */
7299   {
7300     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7301   },
7302
7303   /* VEX_LEN_0FXOP_09_D3 */
7304   {
7305     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7306   },
7307
7308   /* VEX_LEN_0FXOP_09_D6 */
7309   {
7310     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7311   },
7312
7313   /* VEX_LEN_0FXOP_09_D7 */
7314   {
7315     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7316   },
7317
7318   /* VEX_LEN_0FXOP_09_DB */
7319   {
7320     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7321   },
7322
7323   /* VEX_LEN_0FXOP_09_E1 */
7324   {
7325     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7326   },
7327
7328   /* VEX_LEN_0FXOP_09_E2 */
7329   {
7330     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7331   },
7332
7333   /* VEX_LEN_0FXOP_09_E3 */
7334   {
7335     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7336   },
7337
7338   /* VEX_LEN_0FXOP_0A_12 */
7339   {
7340     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7341   },
7342 };
7343
7344 #include "i386-dis-evex-len.h"
7345
7346 static const struct dis386 vex_w_table[][2] = {
7347   {
7348     /* VEX_W_0F41_P_0_LEN_1 */
7349     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7350     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7351   },
7352   {
7353     /* VEX_W_0F41_P_2_LEN_1 */
7354     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7355     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7356   },
7357   {
7358     /* VEX_W_0F42_P_0_LEN_1 */
7359     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7360     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7361   },
7362   {
7363     /* VEX_W_0F42_P_2_LEN_1 */
7364     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7365     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7366   },
7367   {
7368     /* VEX_W_0F44_P_0_LEN_0 */
7369     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7370     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7371   },
7372   {
7373     /* VEX_W_0F44_P_2_LEN_0 */
7374     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7375     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7376   },
7377   {
7378     /* VEX_W_0F45_P_0_LEN_1 */
7379     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7380     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7381   },
7382   {
7383     /* VEX_W_0F45_P_2_LEN_1 */
7384     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7385     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7386   },
7387   {
7388     /* VEX_W_0F46_P_0_LEN_1 */
7389     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7390     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7391   },
7392   {
7393     /* VEX_W_0F46_P_2_LEN_1 */
7394     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7395     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7396   },
7397   {
7398     /* VEX_W_0F47_P_0_LEN_1 */
7399     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7400     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7401   },
7402   {
7403     /* VEX_W_0F47_P_2_LEN_1 */
7404     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7405     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7406   },
7407   {
7408     /* VEX_W_0F4A_P_0_LEN_1 */
7409     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7410     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7411   },
7412   {
7413     /* VEX_W_0F4A_P_2_LEN_1 */
7414     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7415     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7416   },
7417   {
7418     /* VEX_W_0F4B_P_0_LEN_1 */
7419     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7420     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7421   },
7422   {
7423     /* VEX_W_0F4B_P_2_LEN_1 */
7424     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7425   },
7426   {
7427     /* VEX_W_0F90_P_0_LEN_0 */
7428     { "kmovw",          { MaskG, MaskE }, 0 },
7429     { "kmovq",          { MaskG, MaskE }, 0 },
7430   },
7431   {
7432     /* VEX_W_0F90_P_2_LEN_0 */
7433     { "kmovb",          { MaskG, MaskBDE }, 0 },
7434     { "kmovd",          { MaskG, MaskBDE }, 0 },
7435   },
7436   {
7437     /* VEX_W_0F91_P_0_LEN_0 */
7438     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7439     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7440   },
7441   {
7442     /* VEX_W_0F91_P_2_LEN_0 */
7443     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7444     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7445   },
7446   {
7447     /* VEX_W_0F92_P_0_LEN_0 */
7448     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7449   },
7450   {
7451     /* VEX_W_0F92_P_2_LEN_0 */
7452     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7453   },
7454   {
7455     /* VEX_W_0F93_P_0_LEN_0 */
7456     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7457   },
7458   {
7459     /* VEX_W_0F93_P_2_LEN_0 */
7460     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7461   },
7462   {
7463     /* VEX_W_0F98_P_0_LEN_0 */
7464     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7465     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7466   },
7467   {
7468     /* VEX_W_0F98_P_2_LEN_0 */
7469     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7470     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7471   },
7472   {
7473     /* VEX_W_0F99_P_0_LEN_0 */
7474     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7475     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7476   },
7477   {
7478     /* VEX_W_0F99_P_2_LEN_0 */
7479     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7480     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7481   },
7482   {
7483     /* VEX_W_0F380C  */
7484     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7485   },
7486   {
7487     /* VEX_W_0F380D  */
7488     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7489   },
7490   {
7491     /* VEX_W_0F380E  */
7492     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7493   },
7494   {
7495     /* VEX_W_0F380F  */
7496     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7497   },
7498   {
7499     /* VEX_W_0F3813 */
7500     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7501   },
7502   {
7503     /* VEX_W_0F3816_L_1  */
7504     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7505   },
7506   {
7507     /* VEX_W_0F3818 */
7508     { "vbroadcastss",   { XM, EXxmm_md }, PREFIX_DATA },
7509   },
7510   {
7511     /* VEX_W_0F3819_L_1 */
7512     { "vbroadcastsd",   { XM, EXxmm_mq }, PREFIX_DATA },
7513   },
7514   {
7515     /* VEX_W_0F381A_M_0_L_1 */
7516     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7517   },
7518   {
7519     /* VEX_W_0F382C_M_0 */
7520     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7521   },
7522   {
7523     /* VEX_W_0F382D_M_0 */
7524     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7525   },
7526   {
7527     /* VEX_W_0F382E_M_0 */
7528     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7529   },
7530   {
7531     /* VEX_W_0F382F_M_0 */
7532     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7533   },
7534   {
7535     /* VEX_W_0F3836  */
7536     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7537   },
7538   {
7539     /* VEX_W_0F3846 */
7540     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7541   },
7542   {
7543     /* VEX_W_0F3849_X86_64_P_0 */
7544     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7545   },
7546   {
7547     /* VEX_W_0F3849_X86_64_P_2 */
7548     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7549   },
7550   {
7551     /* VEX_W_0F3849_X86_64_P_3 */
7552     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7553   },
7554   {
7555     /* VEX_W_0F384B_X86_64_P_1 */
7556     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7557   },
7558   {
7559     /* VEX_W_0F384B_X86_64_P_2 */
7560     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7561   },
7562   {
7563     /* VEX_W_0F384B_X86_64_P_3 */
7564     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7565   },
7566   {
7567     /* VEX_W_0F3858 */
7568     { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7569   },
7570   {
7571     /* VEX_W_0F3859 */
7572     { "vpbroadcastq",   { XM, EXxmm_mq }, PREFIX_DATA },
7573   },
7574   {
7575     /* VEX_W_0F385A_M_0_L_0 */
7576     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7577   },
7578   {
7579     /* VEX_W_0F385C_X86_64_P_1 */
7580     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7581   },
7582   {
7583     /* VEX_W_0F385E_X86_64_P_0 */
7584     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7585   },
7586   {
7587     /* VEX_W_0F385E_X86_64_P_1 */
7588     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7589   },
7590   {
7591     /* VEX_W_0F385E_X86_64_P_2 */
7592     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7593   },
7594   {
7595     /* VEX_W_0F385E_X86_64_P_3 */
7596     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7597   },
7598   {
7599     /* VEX_W_0F3878 */
7600     { "vpbroadcastb",   { XM, EXxmm_mb }, PREFIX_DATA },
7601   },
7602   {
7603     /* VEX_W_0F3879 */
7604     { "vpbroadcastw",   { XM, EXxmm_mw }, PREFIX_DATA },
7605   },
7606   {
7607     /* VEX_W_0F38CF */
7608     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7609   },
7610   {
7611     /* VEX_W_0F3A00_L_1 */
7612     { Bad_Opcode },
7613     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7614   },
7615   {
7616     /* VEX_W_0F3A01_L_1 */
7617     { Bad_Opcode },
7618     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7619   },
7620   {
7621     /* VEX_W_0F3A02 */
7622     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7623   },
7624   {
7625     /* VEX_W_0F3A04 */
7626     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7627   },
7628   {
7629     /* VEX_W_0F3A05 */
7630     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7631   },
7632   {
7633     /* VEX_W_0F3A06_L_1 */
7634     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7635   },
7636   {
7637     /* VEX_W_0F3A18_L_1 */
7638     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7639   },
7640   {
7641     /* VEX_W_0F3A19_L_1 */
7642     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7643   },
7644   {
7645     /* VEX_W_0F3A1D */
7646     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7647   },
7648   {
7649     /* VEX_W_0F3A38_L_1 */
7650     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7651   },
7652   {
7653     /* VEX_W_0F3A39_L_1 */
7654     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7655   },
7656   {
7657     /* VEX_W_0F3A46_L_1 */
7658     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7659   },
7660   {
7661     /* VEX_W_0F3A4A */
7662     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7663   },
7664   {
7665     /* VEX_W_0F3A4B */
7666     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7667   },
7668   {
7669     /* VEX_W_0F3A4C */
7670     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7671   },
7672   {
7673     /* VEX_W_0F3ACE */
7674     { Bad_Opcode },
7675     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7676   },
7677   {
7678     /* VEX_W_0F3ACF */
7679     { Bad_Opcode },
7680     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7681   },
7682   /* VEX_W_0FXOP_08_85_L_0 */
7683   {
7684     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7685   },
7686   /* VEX_W_0FXOP_08_86_L_0 */
7687   {
7688     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7689   },
7690   /* VEX_W_0FXOP_08_87_L_0 */
7691   {
7692     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7693   },
7694   /* VEX_W_0FXOP_08_8E_L_0 */
7695   {
7696     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7697   },
7698   /* VEX_W_0FXOP_08_8F_L_0 */
7699   {
7700     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7701   },
7702   /* VEX_W_0FXOP_08_95_L_0 */
7703   {
7704     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7705   },
7706   /* VEX_W_0FXOP_08_96_L_0 */
7707   {
7708     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7709   },
7710   /* VEX_W_0FXOP_08_97_L_0 */
7711   {
7712     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7713   },
7714   /* VEX_W_0FXOP_08_9E_L_0 */
7715   {
7716     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7717   },
7718   /* VEX_W_0FXOP_08_9F_L_0 */
7719   {
7720     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7721   },
7722   /* VEX_W_0FXOP_08_A6_L_0 */
7723   {
7724     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7725   },
7726   /* VEX_W_0FXOP_08_B6_L_0 */
7727   {
7728     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7729   },
7730   /* VEX_W_0FXOP_08_C0_L_0 */
7731   {
7732     { "vprotb",         { XM, EXx, Ib }, 0 },
7733   },
7734   /* VEX_W_0FXOP_08_C1_L_0 */
7735   {
7736     { "vprotw",         { XM, EXx, Ib }, 0 },
7737   },
7738   /* VEX_W_0FXOP_08_C2_L_0 */
7739   {
7740     { "vprotd",         { XM, EXx, Ib }, 0 },
7741   },
7742   /* VEX_W_0FXOP_08_C3_L_0 */
7743   {
7744     { "vprotq",         { XM, EXx, Ib }, 0 },
7745   },
7746   /* VEX_W_0FXOP_08_CC_L_0 */
7747   {
7748      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7749   },
7750   /* VEX_W_0FXOP_08_CD_L_0 */
7751   {
7752      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7753   },
7754   /* VEX_W_0FXOP_08_CE_L_0 */
7755   {
7756      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7757   },
7758   /* VEX_W_0FXOP_08_CF_L_0 */
7759   {
7760      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7761   },
7762   /* VEX_W_0FXOP_08_EC_L_0 */
7763   {
7764      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7765   },
7766   /* VEX_W_0FXOP_08_ED_L_0 */
7767   {
7768      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7769   },
7770   /* VEX_W_0FXOP_08_EE_L_0 */
7771   {
7772      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7773   },
7774   /* VEX_W_0FXOP_08_EF_L_0 */
7775   {
7776      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7777   },
7778   /* VEX_W_0FXOP_09_80 */
7779   {
7780     { "vfrczps",        { XM, EXx }, 0 },
7781   },
7782   /* VEX_W_0FXOP_09_81 */
7783   {
7784     { "vfrczpd",        { XM, EXx }, 0 },
7785   },
7786   /* VEX_W_0FXOP_09_82 */
7787   {
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7789   },
7790   /* VEX_W_0FXOP_09_83 */
7791   {
7792     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7793   },
7794   /* VEX_W_0FXOP_09_C1_L_0 */
7795   {
7796     { "vphaddbw",       { XM, EXxmm }, 0 },
7797   },
7798   /* VEX_W_0FXOP_09_C2_L_0 */
7799   {
7800     { "vphaddbd",       { XM, EXxmm }, 0 },
7801   },
7802   /* VEX_W_0FXOP_09_C3_L_0 */
7803   {
7804     { "vphaddbq",       { XM, EXxmm }, 0 },
7805   },
7806   /* VEX_W_0FXOP_09_C6_L_0 */
7807   {
7808     { "vphaddwd",       { XM, EXxmm }, 0 },
7809   },
7810   /* VEX_W_0FXOP_09_C7_L_0 */
7811   {
7812     { "vphaddwq",       { XM, EXxmm }, 0 },
7813   },
7814   /* VEX_W_0FXOP_09_CB_L_0 */
7815   {
7816     { "vphadddq",       { XM, EXxmm }, 0 },
7817   },
7818   /* VEX_W_0FXOP_09_D1_L_0 */
7819   {
7820     { "vphaddubw",      { XM, EXxmm }, 0 },
7821   },
7822   /* VEX_W_0FXOP_09_D2_L_0 */
7823   {
7824     { "vphaddubd",      { XM, EXxmm }, 0 },
7825   },
7826   /* VEX_W_0FXOP_09_D3_L_0 */
7827   {
7828     { "vphaddubq",      { XM, EXxmm }, 0 },
7829   },
7830   /* VEX_W_0FXOP_09_D6_L_0 */
7831   {
7832     { "vphadduwd",      { XM, EXxmm }, 0 },
7833   },
7834   /* VEX_W_0FXOP_09_D7_L_0 */
7835   {
7836     { "vphadduwq",      { XM, EXxmm }, 0 },
7837   },
7838   /* VEX_W_0FXOP_09_DB_L_0 */
7839   {
7840     { "vphaddudq",      { XM, EXxmm }, 0 },
7841   },
7842   /* VEX_W_0FXOP_09_E1_L_0 */
7843   {
7844     { "vphsubbw",       { XM, EXxmm }, 0 },
7845   },
7846   /* VEX_W_0FXOP_09_E2_L_0 */
7847   {
7848     { "vphsubwd",       { XM, EXxmm }, 0 },
7849   },
7850   /* VEX_W_0FXOP_09_E3_L_0 */
7851   {
7852     { "vphsubdq",       { XM, EXxmm }, 0 },
7853   },
7854
7855 #include "i386-dis-evex-w.h"
7856 };
7857
7858 static const struct dis386 mod_table[][2] = {
7859   {
7860     /* MOD_8D */
7861     { "leaS",           { Gv, M }, 0 },
7862   },
7863   {
7864     /* MOD_C6_REG_7 */
7865     { Bad_Opcode },
7866     { RM_TABLE (RM_C6_REG_7) },
7867   },
7868   {
7869     /* MOD_C7_REG_7 */
7870     { Bad_Opcode },
7871     { RM_TABLE (RM_C7_REG_7) },
7872   },
7873   {
7874     /* MOD_FF_REG_3 */
7875     { "{l|}call^", { indirEp }, 0 },
7876   },
7877   {
7878     /* MOD_FF_REG_5 */
7879     { "{l|}jmp^", { indirEp }, 0 },
7880   },
7881   {
7882     /* MOD_0F01_REG_0 */
7883     { X86_64_TABLE (X86_64_0F01_REG_0) },
7884     { RM_TABLE (RM_0F01_REG_0) },
7885   },
7886   {
7887     /* MOD_0F01_REG_1 */
7888     { X86_64_TABLE (X86_64_0F01_REG_1) },
7889     { RM_TABLE (RM_0F01_REG_1) },
7890   },
7891   {
7892     /* MOD_0F01_REG_2 */
7893     { X86_64_TABLE (X86_64_0F01_REG_2) },
7894     { RM_TABLE (RM_0F01_REG_2) },
7895   },
7896   {
7897     /* MOD_0F01_REG_3 */
7898     { X86_64_TABLE (X86_64_0F01_REG_3) },
7899     { RM_TABLE (RM_0F01_REG_3) },
7900   },
7901   {
7902     /* MOD_0F01_REG_5 */
7903     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7904     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7905   },
7906   {
7907     /* MOD_0F01_REG_7 */
7908     { "invlpg",         { Mb }, 0 },
7909     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7910   },
7911   {
7912     /* MOD_0F12_PREFIX_0 */
7913     { "movlpX",         { XM, EXq }, 0 },
7914     { "movhlps",        { XM, EXq }, 0 },
7915   },
7916   {
7917     /* MOD_0F12_PREFIX_2 */
7918     { "movlpX", { XM, EXq }, 0 },
7919   },
7920   {
7921     /* MOD_0F13 */
7922     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
7923   },
7924   {
7925     /* MOD_0F16_PREFIX_0 */
7926     { "movhpX",         { XM, EXq }, 0 },
7927     { "movlhps",        { XM, EXq }, 0 },
7928   },
7929   {
7930     /* MOD_0F16_PREFIX_2 */
7931     { "movhpX", { XM, EXq }, 0 },
7932   },
7933   {
7934     /* MOD_0F17 */
7935     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
7936   },
7937   {
7938     /* MOD_0F18_REG_0 */
7939     { "prefetchnta",    { Mb }, 0 },
7940   },
7941   {
7942     /* MOD_0F18_REG_1 */
7943     { "prefetcht0",     { Mb }, 0 },
7944   },
7945   {
7946     /* MOD_0F18_REG_2 */
7947     { "prefetcht1",     { Mb }, 0 },
7948   },
7949   {
7950     /* MOD_0F18_REG_3 */
7951     { "prefetcht2",     { Mb }, 0 },
7952   },
7953   {
7954     /* MOD_0F18_REG_4 */
7955     { "nop/reserved",   { Mb }, 0 },
7956   },
7957   {
7958     /* MOD_0F18_REG_5 */
7959     { "nop/reserved",   { Mb }, 0 },
7960   },
7961   {
7962     /* MOD_0F18_REG_6 */
7963     { "nop/reserved",   { Mb }, 0 },
7964   },
7965   {
7966     /* MOD_0F18_REG_7 */
7967     { "nop/reserved",   { Mb }, 0 },
7968   },
7969   {
7970     /* MOD_0F1A_PREFIX_0 */
7971     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
7972     { "nopQ",           { Ev }, 0 },
7973   },
7974   {
7975     /* MOD_0F1B_PREFIX_0 */
7976     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
7977     { "nopQ",           { Ev }, 0 },
7978   },
7979   {
7980     /* MOD_0F1B_PREFIX_1 */
7981     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
7982     { "nopQ",           { Ev }, 0 },
7983   },
7984   {
7985     /* MOD_0F1C_PREFIX_0 */
7986     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
7987     { "nopQ",           { Ev }, 0 },
7988   },
7989   {
7990     /* MOD_0F1E_PREFIX_1 */
7991     { "nopQ",           { Ev }, 0 },
7992     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
7993   },
7994   {
7995     /* MOD_0F24 */
7996     { Bad_Opcode },
7997     { "movL",           { Rm, Td }, 0 },
7998   },
7999   {
8000     /* MOD_0F26 */
8001     { Bad_Opcode },
8002     { "movL",           { Td, Rm }, 0 },
8003   },
8004   {
8005     /* MOD_0F2B_PREFIX_0 */
8006     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8007   },
8008   {
8009     /* MOD_0F2B_PREFIX_1 */
8010     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8011   },
8012   {
8013     /* MOD_0F2B_PREFIX_2 */
8014     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8015   },
8016   {
8017     /* MOD_0F2B_PREFIX_3 */
8018     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8019   },
8020   {
8021     /* MOD_0F50 */
8022     { Bad_Opcode },
8023     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8024   },
8025   {
8026     /* MOD_0F71_REG_2 */
8027     { Bad_Opcode },
8028     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
8029   },
8030   {
8031     /* MOD_0F71_REG_4 */
8032     { Bad_Opcode },
8033     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
8034   },
8035   {
8036     /* MOD_0F71_REG_6 */
8037     { Bad_Opcode },
8038     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
8039   },
8040   {
8041     /* MOD_0F72_REG_2 */
8042     { Bad_Opcode },
8043     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
8044   },
8045   {
8046     /* MOD_0F72_REG_4 */
8047     { Bad_Opcode },
8048     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
8049   },
8050   {
8051     /* MOD_0F72_REG_6 */
8052     { Bad_Opcode },
8053     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
8054   },
8055   {
8056     /* MOD_0F73_REG_2 */
8057     { Bad_Opcode },
8058     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
8059   },
8060   {
8061     /* MOD_0F73_REG_3 */
8062     { Bad_Opcode },
8063     { "psrldq",         { XS, Ib }, PREFIX_DATA },
8064   },
8065   {
8066     /* MOD_0F73_REG_6 */
8067     { Bad_Opcode },
8068     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
8069   },
8070   {
8071     /* MOD_0F73_REG_7 */
8072     { Bad_Opcode },
8073     { "pslldq",         { XS, Ib }, PREFIX_DATA },
8074   },
8075   {
8076     /* MOD_0FAE_REG_0 */
8077     { "fxsave",         { FXSAVE }, 0 },
8078     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8079   },
8080   {
8081     /* MOD_0FAE_REG_1 */
8082     { "fxrstor",        { FXSAVE }, 0 },
8083     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8084   },
8085   {
8086     /* MOD_0FAE_REG_2 */
8087     { "ldmxcsr",        { Md }, 0 },
8088     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8089   },
8090   {
8091     /* MOD_0FAE_REG_3 */
8092     { "stmxcsr",        { Md }, 0 },
8093     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8094   },
8095   {
8096     /* MOD_0FAE_REG_4 */
8097     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8098     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8099   },
8100   {
8101     /* MOD_0FAE_REG_5 */
8102     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8103     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8104   },
8105   {
8106     /* MOD_0FAE_REG_6 */
8107     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8108     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8109   },
8110   {
8111     /* MOD_0FAE_REG_7 */
8112     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8113     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8114   },
8115   {
8116     /* MOD_0FB2 */
8117     { "lssS",           { Gv, Mp }, 0 },
8118   },
8119   {
8120     /* MOD_0FB4 */
8121     { "lfsS",           { Gv, Mp }, 0 },
8122   },
8123   {
8124     /* MOD_0FB5 */
8125     { "lgsS",           { Gv, Mp }, 0 },
8126   },
8127   {
8128     /* MOD_0FC3 */
8129     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8130   },
8131   {
8132     /* MOD_0FC7_REG_3 */
8133     { "xrstors",        { FXSAVE }, 0 },
8134   },
8135   {
8136     /* MOD_0FC7_REG_4 */
8137     { "xsavec",         { FXSAVE }, 0 },
8138   },
8139   {
8140     /* MOD_0FC7_REG_5 */
8141     { "xsaves",         { FXSAVE }, 0 },
8142   },
8143   {
8144     /* MOD_0FC7_REG_6 */
8145     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8146     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8147   },
8148   {
8149     /* MOD_0FC7_REG_7 */
8150     { "vmptrst",        { Mq }, 0 },
8151     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8152   },
8153   {
8154     /* MOD_0FD7 */
8155     { Bad_Opcode },
8156     { "pmovmskb",       { Gdq, MS }, 0 },
8157   },
8158   {
8159     /* MOD_0FE7_PREFIX_2 */
8160     { "movntdq",        { Mx, XM }, 0 },
8161   },
8162   {
8163     /* MOD_0FF0_PREFIX_3 */
8164     { "lddqu",          { XM, M }, 0 },
8165   },
8166   {
8167     /* MOD_0F382A */
8168     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8169   },
8170   {
8171     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8172     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8173     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8174   },
8175   {
8176     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8177     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8178   },
8179   {
8180     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8181     { Bad_Opcode },
8182     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8183   },
8184   {
8185     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8186     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8187   },
8188   {
8189     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8190     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8191   },
8192   {
8193     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8194     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8195   },
8196   {
8197     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8198     { Bad_Opcode },
8199     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8200   },
8201   {
8202     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8203     { Bad_Opcode },
8204     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8205   },
8206   {
8207     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8208     { Bad_Opcode },
8209     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8210   },
8211   {
8212     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8213     { Bad_Opcode },
8214     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8215   },
8216   {
8217     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8218     { Bad_Opcode },
8219     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8220   },
8221   {
8222     /* MOD_0F38F5 */
8223     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8224   },
8225   {
8226     /* MOD_0F38F6_PREFIX_0 */
8227     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8228   },
8229   {
8230     /* MOD_0F38F8_PREFIX_1 */
8231     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8232   },
8233   {
8234     /* MOD_0F38F8_PREFIX_2 */
8235     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8236   },
8237   {
8238     /* MOD_0F38F8_PREFIX_3 */
8239     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8240   },
8241   {
8242     /* MOD_0F38F9 */
8243     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8244   },
8245   {
8246     /* MOD_62_32BIT */
8247     { "bound{S|}",      { Gv, Ma }, 0 },
8248     { EVEX_TABLE (EVEX_0F) },
8249   },
8250   {
8251     /* MOD_C4_32BIT */
8252     { "lesS",           { Gv, Mp }, 0 },
8253     { VEX_C4_TABLE (VEX_0F) },
8254   },
8255   {
8256     /* MOD_C5_32BIT */
8257     { "ldsS",           { Gv, Mp }, 0 },
8258     { VEX_C5_TABLE (VEX_0F) },
8259   },
8260   {
8261     /* MOD_VEX_0F12_PREFIX_0 */
8262     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8263     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8264   },
8265   {
8266     /* MOD_VEX_0F12_PREFIX_2 */
8267     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8268   },
8269   {
8270     /* MOD_VEX_0F13 */
8271     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8272   },
8273   {
8274     /* MOD_VEX_0F16_PREFIX_0 */
8275     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8276     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8277   },
8278   {
8279     /* MOD_VEX_0F16_PREFIX_2 */
8280     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8281   },
8282   {
8283     /* MOD_VEX_0F17 */
8284     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8285   },
8286   {
8287     /* MOD_VEX_0F2B */
8288     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8289   },
8290   {
8291     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8292     { Bad_Opcode },
8293     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
8294   },
8295   {
8296     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8297     { Bad_Opcode },
8298     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
8299   },
8300   {
8301     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8302     { Bad_Opcode },
8303     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
8304   },
8305   {
8306     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8307     { Bad_Opcode },
8308     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
8309   },
8310   {
8311     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8312     { Bad_Opcode },
8313     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
8314   },
8315   {
8316     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8317     { Bad_Opcode },
8318     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
8319   },
8320   {
8321     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8322     { Bad_Opcode },
8323     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
8324   },
8325   {
8326     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8327     { Bad_Opcode },
8328     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
8329   },
8330   {
8331     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8332     { Bad_Opcode },
8333     { "knotw",          { MaskG, MaskE }, 0 },
8334   },
8335   {
8336     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8337     { Bad_Opcode },
8338     { "knotq",          { MaskG, MaskE }, 0 },
8339   },
8340   {
8341     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8342     { Bad_Opcode },
8343     { "knotb",          { MaskG, MaskE }, 0 },
8344   },
8345   {
8346     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8347     { Bad_Opcode },
8348     { "knotd",          { MaskG, MaskE }, 0 },
8349   },
8350   {
8351     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8352     { Bad_Opcode },
8353     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
8354   },
8355   {
8356     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8357     { Bad_Opcode },
8358     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
8359   },
8360   {
8361     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8362     { Bad_Opcode },
8363     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
8364   },
8365   {
8366     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8367     { Bad_Opcode },
8368     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
8369   },
8370  {
8371     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8372     { Bad_Opcode },
8373     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
8374   },
8375   {
8376     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8377     { Bad_Opcode },
8378     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
8379   },
8380   {
8381     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8382     { Bad_Opcode },
8383     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
8384   },
8385   {
8386     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8387     { Bad_Opcode },
8388     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
8389   },
8390   {
8391     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8392     { Bad_Opcode },
8393     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
8394   },
8395   {
8396     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8397     { Bad_Opcode },
8398     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
8399   },
8400   {
8401     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8402     { Bad_Opcode },
8403     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
8404   },
8405   {
8406     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8407     { Bad_Opcode },
8408     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
8409   },
8410   {
8411     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8412     { Bad_Opcode },
8413     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
8414   },
8415   {
8416     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8417     { Bad_Opcode },
8418     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
8419   },
8420   {
8421     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8422     { Bad_Opcode },
8423     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
8424   },
8425   {
8426     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8427     { Bad_Opcode },
8428     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
8429   },
8430   {
8431     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8432     { Bad_Opcode },
8433     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
8434   },
8435   {
8436     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8437     { Bad_Opcode },
8438     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
8439   },
8440   {
8441     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8442     { Bad_Opcode },
8443     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
8444   },
8445   {
8446     /* MOD_VEX_0F50 */
8447     { Bad_Opcode },
8448     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8449   },
8450   {
8451     /* MOD_VEX_0F71_REG_2 */
8452     { Bad_Opcode },
8453     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
8454   },
8455   {
8456     /* MOD_VEX_0F71_REG_4 */
8457     { Bad_Opcode },
8458     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
8459   },
8460   {
8461     /* MOD_VEX_0F71_REG_6 */
8462     { Bad_Opcode },
8463     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
8464   },
8465   {
8466     /* MOD_VEX_0F72_REG_2 */
8467     { Bad_Opcode },
8468     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
8469   },
8470   {
8471     /* MOD_VEX_0F72_REG_4 */
8472     { Bad_Opcode },
8473     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
8474   },
8475   {
8476     /* MOD_VEX_0F72_REG_6 */
8477     { Bad_Opcode },
8478     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
8479   },
8480   {
8481     /* MOD_VEX_0F73_REG_2 */
8482     { Bad_Opcode },
8483     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
8484   },
8485   {
8486     /* MOD_VEX_0F73_REG_3 */
8487     { Bad_Opcode },
8488     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
8489   },
8490   {
8491     /* MOD_VEX_0F73_REG_6 */
8492     { Bad_Opcode },
8493     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
8494   },
8495   {
8496     /* MOD_VEX_0F73_REG_7 */
8497     { Bad_Opcode },
8498     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
8499   },
8500   {
8501     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8502     { "kmovw",          { Ew, MaskG }, 0 },
8503     { Bad_Opcode },
8504   },
8505   {
8506     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8507     { "kmovq",          { Eq, MaskG }, 0 },
8508     { Bad_Opcode },
8509   },
8510   {
8511     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8512     { "kmovb",          { Eb, MaskG }, 0 },
8513     { Bad_Opcode },
8514   },
8515   {
8516     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8517     { "kmovd",          { Ed, MaskG }, 0 },
8518     { Bad_Opcode },
8519   },
8520   {
8521     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8522     { Bad_Opcode },
8523     { "kmovw",          { MaskG, Edq }, 0 },
8524   },
8525   {
8526     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8527     { Bad_Opcode },
8528     { "kmovb",          { MaskG, Edq }, 0 },
8529   },
8530   {
8531     /* MOD_VEX_0F92_P_3_LEN_0 */
8532     { Bad_Opcode },
8533     { "kmovK",          { MaskG, Edq }, 0 },
8534   },
8535   {
8536     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8537     { Bad_Opcode },
8538     { "kmovw",          { Gdq, MaskE }, 0 },
8539   },
8540   {
8541     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8542     { Bad_Opcode },
8543     { "kmovb",          { Gdq, MaskE }, 0 },
8544   },
8545   {
8546     /* MOD_VEX_0F93_P_3_LEN_0 */
8547     { Bad_Opcode },
8548     { "kmovK",          { Gdq, MaskE }, 0 },
8549   },
8550   {
8551     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8552     { Bad_Opcode },
8553     { "kortestw", { MaskG, MaskE }, 0 },
8554   },
8555   {
8556     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8557     { Bad_Opcode },
8558     { "kortestq", { MaskG, MaskE }, 0 },
8559   },
8560   {
8561     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8562     { Bad_Opcode },
8563     { "kortestb", { MaskG, MaskE }, 0 },
8564   },
8565   {
8566     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8567     { Bad_Opcode },
8568     { "kortestd", { MaskG, MaskE }, 0 },
8569   },
8570   {
8571     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8572     { Bad_Opcode },
8573     { "ktestw", { MaskG, MaskE }, 0 },
8574   },
8575   {
8576     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8577     { Bad_Opcode },
8578     { "ktestq", { MaskG, MaskE }, 0 },
8579   },
8580   {
8581     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8582     { Bad_Opcode },
8583     { "ktestb", { MaskG, MaskE }, 0 },
8584   },
8585   {
8586     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8587     { Bad_Opcode },
8588     { "ktestd", { MaskG, MaskE }, 0 },
8589   },
8590   {
8591     /* MOD_VEX_0FAE_REG_2 */
8592     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8593   },
8594   {
8595     /* MOD_VEX_0FAE_REG_3 */
8596     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8597   },
8598   {
8599     /* MOD_VEX_0FD7 */
8600     { Bad_Opcode },
8601     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8602   },
8603   {
8604     /* MOD_VEX_0FE7 */
8605     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8606   },
8607   {
8608     /* MOD_VEX_0FF0_PREFIX_3 */
8609     { "vlddqu",         { XM, M }, 0 },
8610   },
8611   {
8612     /* MOD_VEX_0F381A */
8613     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8614   },
8615   {
8616     /* MOD_VEX_0F382A */
8617     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8618   },
8619   {
8620     /* MOD_VEX_0F382C */
8621     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8622   },
8623   {
8624     /* MOD_VEX_0F382D */
8625     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8626   },
8627   {
8628     /* MOD_VEX_0F382E */
8629     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8630   },
8631   {
8632     /* MOD_VEX_0F382F */
8633     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8634   },
8635   {
8636     /* MOD_VEX_0F385A */
8637     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8638   },
8639   {
8640     /* MOD_VEX_0F388C */
8641     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8642   },
8643   {
8644     /* MOD_VEX_0F388E */
8645     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8646   },
8647   {
8648     /* MOD_VEX_0F3A30_L_0 */
8649     { Bad_Opcode },
8650     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8651   },
8652   {
8653     /* MOD_VEX_0F3A31_L_0 */
8654     { Bad_Opcode },
8655     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8656   },
8657   {
8658     /* MOD_VEX_0F3A32_L_0 */
8659     { Bad_Opcode },
8660     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8661   },
8662   {
8663     /* MOD_VEX_0F3A33_L_0 */
8664     { Bad_Opcode },
8665     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8666   },
8667   {
8668     /* MOD_VEX_0FXOP_09_12 */
8669     { Bad_Opcode },
8670     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8671   },
8672
8673 #include "i386-dis-evex-mod.h"
8674 };
8675
8676 static const struct dis386 rm_table[][8] = {
8677   {
8678     /* RM_C6_REG_7 */
8679     { "xabort",         { Skip_MODRM, Ib }, 0 },
8680   },
8681   {
8682     /* RM_C7_REG_7 */
8683     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8684   },
8685   {
8686     /* RM_0F01_REG_0 */
8687     { "enclv",          { Skip_MODRM }, 0 },
8688     { "vmcall",         { Skip_MODRM }, 0 },
8689     { "vmlaunch",       { Skip_MODRM }, 0 },
8690     { "vmresume",       { Skip_MODRM }, 0 },
8691     { "vmxoff",         { Skip_MODRM }, 0 },
8692     { "pconfig",        { Skip_MODRM }, 0 },
8693   },
8694   {
8695     /* RM_0F01_REG_1 */
8696     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8697     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8698     { "clac",           { Skip_MODRM }, 0 },
8699     { "stac",           { Skip_MODRM }, 0 },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { "encls",          { Skip_MODRM }, 0 },
8704   },
8705   {
8706     /* RM_0F01_REG_2 */
8707     { "xgetbv",         { Skip_MODRM }, 0 },
8708     { "xsetbv",         { Skip_MODRM }, 0 },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { "vmfunc",         { Skip_MODRM }, 0 },
8712     { "xend",           { Skip_MODRM }, 0 },
8713     { "xtest",          { Skip_MODRM }, 0 },
8714     { "enclu",          { Skip_MODRM }, 0 },
8715   },
8716   {
8717     /* RM_0F01_REG_3 */
8718     { "vmrun",          { Skip_MODRM }, 0 },
8719     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8720     { "vmload",         { Skip_MODRM }, 0 },
8721     { "vmsave",         { Skip_MODRM }, 0 },
8722     { "stgi",           { Skip_MODRM }, 0 },
8723     { "clgi",           { Skip_MODRM }, 0 },
8724     { "skinit",         { Skip_MODRM }, 0 },
8725     { "invlpga",        { Skip_MODRM }, 0 },
8726   },
8727   {
8728     /* RM_0F01_REG_5_MOD_3 */
8729     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8730     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8731     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { "rdpkru",         { Skip_MODRM }, 0 },
8736     { "wrpkru",         { Skip_MODRM }, 0 },
8737   },
8738   {
8739     /* RM_0F01_REG_7_MOD_3 */
8740     { "swapgs",         { Skip_MODRM }, 0  },
8741     { "rdtscp",         { Skip_MODRM }, 0  },
8742     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8743     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8744     { "clzero",         { Skip_MODRM }, 0  },
8745     { "rdpru",          { Skip_MODRM }, 0  },
8746   },
8747   {
8748     /* RM_0F1E_P_1_MOD_3_REG_7 */
8749     { "nopQ",           { Ev }, 0 },
8750     { "nopQ",           { Ev }, 0 },
8751     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
8752     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
8753     { "nopQ",           { Ev }, 0 },
8754     { "nopQ",           { Ev }, 0 },
8755     { "nopQ",           { Ev }, 0 },
8756     { "nopQ",           { Ev }, 0 },
8757   },
8758   {
8759     /* RM_0FAE_REG_6_MOD_3 */
8760     { "mfence",         { Skip_MODRM }, 0 },
8761   },
8762   {
8763     /* RM_0FAE_REG_7_MOD_3 */
8764     { "sfence",         { Skip_MODRM }, 0 },
8765
8766   },
8767   {
8768     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8769     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8770   },
8771 };
8772
8773 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8774
8775 /* We use the high bit to indicate different name for the same
8776    prefix.  */
8777 #define REP_PREFIX      (0xf3 | 0x100)
8778 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8779 #define XRELEASE_PREFIX (0xf3 | 0x400)
8780 #define BND_PREFIX      (0xf2 | 0x400)
8781 #define NOTRACK_PREFIX  (0x3e | 0x100)
8782
8783 /* Remember if the current op is a jump instruction.  */
8784 static bfd_boolean op_is_jump = FALSE;
8785
8786 static int
8787 ckprefix (void)
8788 {
8789   int newrex, i, length;
8790   rex = 0;
8791   prefixes = 0;
8792   used_prefixes = 0;
8793   rex_used = 0;
8794   last_lock_prefix = -1;
8795   last_repz_prefix = -1;
8796   last_repnz_prefix = -1;
8797   last_data_prefix = -1;
8798   last_addr_prefix = -1;
8799   last_rex_prefix = -1;
8800   last_seg_prefix = -1;
8801   fwait_prefix = -1;
8802   active_seg_prefix = 0;
8803   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8804     all_prefixes[i] = 0;
8805   i = 0;
8806   length = 0;
8807   /* The maximum instruction length is 15bytes.  */
8808   while (length < MAX_CODE_LENGTH - 1)
8809     {
8810       FETCH_DATA (the_info, codep + 1);
8811       newrex = 0;
8812       switch (*codep)
8813         {
8814         /* REX prefixes family.  */
8815         case 0x40:
8816         case 0x41:
8817         case 0x42:
8818         case 0x43:
8819         case 0x44:
8820         case 0x45:
8821         case 0x46:
8822         case 0x47:
8823         case 0x48:
8824         case 0x49:
8825         case 0x4a:
8826         case 0x4b:
8827         case 0x4c:
8828         case 0x4d:
8829         case 0x4e:
8830         case 0x4f:
8831           if (address_mode == mode_64bit)
8832             newrex = *codep;
8833           else
8834             return 1;
8835           last_rex_prefix = i;
8836           break;
8837         case 0xf3:
8838           prefixes |= PREFIX_REPZ;
8839           last_repz_prefix = i;
8840           break;
8841         case 0xf2:
8842           prefixes |= PREFIX_REPNZ;
8843           last_repnz_prefix = i;
8844           break;
8845         case 0xf0:
8846           prefixes |= PREFIX_LOCK;
8847           last_lock_prefix = i;
8848           break;
8849         case 0x2e:
8850           prefixes |= PREFIX_CS;
8851           last_seg_prefix = i;
8852           active_seg_prefix = PREFIX_CS;
8853           break;
8854         case 0x36:
8855           prefixes |= PREFIX_SS;
8856           last_seg_prefix = i;
8857           active_seg_prefix = PREFIX_SS;
8858           break;
8859         case 0x3e:
8860           prefixes |= PREFIX_DS;
8861           last_seg_prefix = i;
8862           active_seg_prefix = PREFIX_DS;
8863           break;
8864         case 0x26:
8865           prefixes |= PREFIX_ES;
8866           last_seg_prefix = i;
8867           active_seg_prefix = PREFIX_ES;
8868           break;
8869         case 0x64:
8870           prefixes |= PREFIX_FS;
8871           last_seg_prefix = i;
8872           active_seg_prefix = PREFIX_FS;
8873           break;
8874         case 0x65:
8875           prefixes |= PREFIX_GS;
8876           last_seg_prefix = i;
8877           active_seg_prefix = PREFIX_GS;
8878           break;
8879         case 0x66:
8880           prefixes |= PREFIX_DATA;
8881           last_data_prefix = i;
8882           break;
8883         case 0x67:
8884           prefixes |= PREFIX_ADDR;
8885           last_addr_prefix = i;
8886           break;
8887         case FWAIT_OPCODE:
8888           /* fwait is really an instruction.  If there are prefixes
8889              before the fwait, they belong to the fwait, *not* to the
8890              following instruction.  */
8891           fwait_prefix = i;
8892           if (prefixes || rex)
8893             {
8894               prefixes |= PREFIX_FWAIT;
8895               codep++;
8896               /* This ensures that the previous REX prefixes are noticed
8897                  as unused prefixes, as in the return case below.  */
8898               rex_used = rex;
8899               return 1;
8900             }
8901           prefixes = PREFIX_FWAIT;
8902           break;
8903         default:
8904           return 1;
8905         }
8906       /* Rex is ignored when followed by another prefix.  */
8907       if (rex)
8908         {
8909           rex_used = rex;
8910           return 1;
8911         }
8912       if (*codep != FWAIT_OPCODE)
8913         all_prefixes[i++] = *codep;
8914       rex = newrex;
8915       codep++;
8916       length++;
8917     }
8918   return 0;
8919 }
8920
8921 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8922    prefix byte.  */
8923
8924 static const char *
8925 prefix_name (int pref, int sizeflag)
8926 {
8927   static const char *rexes [16] =
8928     {
8929       "rex",            /* 0x40 */
8930       "rex.B",          /* 0x41 */
8931       "rex.X",          /* 0x42 */
8932       "rex.XB",         /* 0x43 */
8933       "rex.R",          /* 0x44 */
8934       "rex.RB",         /* 0x45 */
8935       "rex.RX",         /* 0x46 */
8936       "rex.RXB",        /* 0x47 */
8937       "rex.W",          /* 0x48 */
8938       "rex.WB",         /* 0x49 */
8939       "rex.WX",         /* 0x4a */
8940       "rex.WXB",        /* 0x4b */
8941       "rex.WR",         /* 0x4c */
8942       "rex.WRB",        /* 0x4d */
8943       "rex.WRX",        /* 0x4e */
8944       "rex.WRXB",       /* 0x4f */
8945     };
8946
8947   switch (pref)
8948     {
8949     /* REX prefixes family.  */
8950     case 0x40:
8951     case 0x41:
8952     case 0x42:
8953     case 0x43:
8954     case 0x44:
8955     case 0x45:
8956     case 0x46:
8957     case 0x47:
8958     case 0x48:
8959     case 0x49:
8960     case 0x4a:
8961     case 0x4b:
8962     case 0x4c:
8963     case 0x4d:
8964     case 0x4e:
8965     case 0x4f:
8966       return rexes [pref - 0x40];
8967     case 0xf3:
8968       return "repz";
8969     case 0xf2:
8970       return "repnz";
8971     case 0xf0:
8972       return "lock";
8973     case 0x2e:
8974       return "cs";
8975     case 0x36:
8976       return "ss";
8977     case 0x3e:
8978       return "ds";
8979     case 0x26:
8980       return "es";
8981     case 0x64:
8982       return "fs";
8983     case 0x65:
8984       return "gs";
8985     case 0x66:
8986       return (sizeflag & DFLAG) ? "data16" : "data32";
8987     case 0x67:
8988       if (address_mode == mode_64bit)
8989         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8990       else
8991         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8992     case FWAIT_OPCODE:
8993       return "fwait";
8994     case REP_PREFIX:
8995       return "rep";
8996     case XACQUIRE_PREFIX:
8997       return "xacquire";
8998     case XRELEASE_PREFIX:
8999       return "xrelease";
9000     case BND_PREFIX:
9001       return "bnd";
9002     case NOTRACK_PREFIX:
9003       return "notrack";
9004     default:
9005       return NULL;
9006     }
9007 }
9008
9009 static char op_out[MAX_OPERANDS][100];
9010 static int op_ad, op_index[MAX_OPERANDS];
9011 static int two_source_ops;
9012 static bfd_vma op_address[MAX_OPERANDS];
9013 static bfd_vma op_riprel[MAX_OPERANDS];
9014 static bfd_vma start_pc;
9015
9016 /*
9017  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9018  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9019  *   section of the "Virtual 8086 Mode" chapter.)
9020  * 'pc' should be the address of this instruction, it will
9021  *   be used to print the target address if this is a relative jump or call
9022  * The function returns the length of this instruction in bytes.
9023  */
9024
9025 static char intel_syntax;
9026 static char intel_mnemonic = !SYSV386_COMPAT;
9027 static char open_char;
9028 static char close_char;
9029 static char separator_char;
9030 static char scale_char;
9031
9032 enum x86_64_isa
9033 {
9034   amd64 = 1,
9035   intel64
9036 };
9037
9038 static enum x86_64_isa isa64;
9039
9040 /* Here for backwards compatibility.  When gdb stops using
9041    print_insn_i386_att and print_insn_i386_intel these functions can
9042    disappear, and print_insn_i386 be merged into print_insn.  */
9043 int
9044 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9045 {
9046   intel_syntax = 0;
9047
9048   return print_insn (pc, info);
9049 }
9050
9051 int
9052 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9053 {
9054   intel_syntax = 1;
9055
9056   return print_insn (pc, info);
9057 }
9058
9059 int
9060 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9061 {
9062   intel_syntax = -1;
9063
9064   return print_insn (pc, info);
9065 }
9066
9067 void
9068 print_i386_disassembler_options (FILE *stream)
9069 {
9070   fprintf (stream, _("\n\
9071 The following i386/x86-64 specific disassembler options are supported for use\n\
9072 with the -M switch (multiple options should be separated by commas):\n"));
9073
9074   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9075   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9076   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9077   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9078   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9079   fprintf (stream, _("  att-mnemonic\n"
9080                      "              Display instruction in AT&T mnemonic\n"));
9081   fprintf (stream, _("  intel-mnemonic\n"
9082                      "              Display instruction in Intel mnemonic\n"));
9083   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9084   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9085   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9086   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9087   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9088   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9089   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
9090   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
9091 }
9092
9093 /* Bad opcode.  */
9094 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9095
9096 /* Get a pointer to struct dis386 with a valid name.  */
9097
9098 static const struct dis386 *
9099 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9100 {
9101   int vindex, vex_table_index;
9102
9103   if (dp->name != NULL)
9104     return dp;
9105
9106   switch (dp->op[0].bytemode)
9107     {
9108     case USE_REG_TABLE:
9109       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9110       break;
9111
9112     case USE_MOD_TABLE:
9113       vindex = modrm.mod == 0x3 ? 1 : 0;
9114       dp = &mod_table[dp->op[1].bytemode][vindex];
9115       break;
9116
9117     case USE_RM_TABLE:
9118       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9119       break;
9120
9121     case USE_PREFIX_TABLE:
9122       if (need_vex)
9123         {
9124           /* The prefix in VEX is implicit.  */
9125           switch (vex.prefix)
9126             {
9127             case 0:
9128               vindex = 0;
9129               break;
9130             case REPE_PREFIX_OPCODE:
9131               vindex = 1;
9132               break;
9133             case DATA_PREFIX_OPCODE:
9134               vindex = 2;
9135               break;
9136             case REPNE_PREFIX_OPCODE:
9137               vindex = 3;
9138               break;
9139             default:
9140               abort ();
9141               break;
9142             }
9143         }
9144       else
9145         {
9146           int last_prefix = -1;
9147           int prefix = 0;
9148           vindex = 0;
9149           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9150              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9151              last one wins.  */
9152           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9153             {
9154               if (last_repz_prefix > last_repnz_prefix)
9155                 {
9156                   vindex = 1;
9157                   prefix = PREFIX_REPZ;
9158                   last_prefix = last_repz_prefix;
9159                 }
9160               else
9161                 {
9162                   vindex = 3;
9163                   prefix = PREFIX_REPNZ;
9164                   last_prefix = last_repnz_prefix;
9165                 }
9166
9167               /* Check if prefix should be ignored.  */
9168               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9169                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9170                    & prefix) != 0)
9171                 vindex = 0;
9172             }
9173
9174           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9175             {
9176               vindex = 2;
9177               prefix = PREFIX_DATA;
9178               last_prefix = last_data_prefix;
9179             }
9180
9181           if (vindex != 0)
9182             {
9183               used_prefixes |= prefix;
9184               all_prefixes[last_prefix] = 0;
9185             }
9186         }
9187       dp = &prefix_table[dp->op[1].bytemode][vindex];
9188       break;
9189
9190     case USE_X86_64_TABLE:
9191       vindex = address_mode == mode_64bit ? 1 : 0;
9192       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9193       break;
9194
9195     case USE_3BYTE_TABLE:
9196       FETCH_DATA (info, codep + 2);
9197       vindex = *codep++;
9198       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9199       end_codep = codep;
9200       modrm.mod = (*codep >> 6) & 3;
9201       modrm.reg = (*codep >> 3) & 7;
9202       modrm.rm = *codep & 7;
9203       break;
9204
9205     case USE_VEX_LEN_TABLE:
9206       if (!need_vex)
9207         abort ();
9208
9209       switch (vex.length)
9210         {
9211         case 128:
9212           vindex = 0;
9213           break;
9214         case 256:
9215           vindex = 1;
9216           break;
9217         default:
9218           abort ();
9219           break;
9220         }
9221
9222       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9223       break;
9224
9225     case USE_EVEX_LEN_TABLE:
9226       if (!vex.evex)
9227         abort ();
9228
9229       switch (vex.length)
9230         {
9231         case 128:
9232           vindex = 0;
9233           break;
9234         case 256:
9235           vindex = 1;
9236           break;
9237         case 512:
9238           vindex = 2;
9239           break;
9240         default:
9241           abort ();
9242           break;
9243         }
9244
9245       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9246       break;
9247
9248     case USE_XOP_8F_TABLE:
9249       FETCH_DATA (info, codep + 3);
9250       rex = ~(*codep >> 5) & 0x7;
9251
9252       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9253       switch ((*codep & 0x1f))
9254         {
9255         default:
9256           dp = &bad_opcode;
9257           return dp;
9258         case 0x8:
9259           vex_table_index = XOP_08;
9260           break;
9261         case 0x9:
9262           vex_table_index = XOP_09;
9263           break;
9264         case 0xa:
9265           vex_table_index = XOP_0A;
9266           break;
9267         }
9268       codep++;
9269       vex.w = *codep & 0x80;
9270       if (vex.w && address_mode == mode_64bit)
9271         rex |= REX_W;
9272
9273       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9274       if (address_mode != mode_64bit)
9275         {
9276           /* In 16/32-bit mode REX_B is silently ignored.  */
9277           rex &= ~REX_B;
9278         }
9279
9280       vex.length = (*codep & 0x4) ? 256 : 128;
9281       switch ((*codep & 0x3))
9282         {
9283         case 0:
9284           break;
9285         case 1:
9286           vex.prefix = DATA_PREFIX_OPCODE;
9287           break;
9288         case 2:
9289           vex.prefix = REPE_PREFIX_OPCODE;
9290           break;
9291         case 3:
9292           vex.prefix = REPNE_PREFIX_OPCODE;
9293           break;
9294         }
9295       need_vex = 1;
9296       codep++;
9297       vindex = *codep++;
9298       dp = &xop_table[vex_table_index][vindex];
9299
9300       end_codep = codep;
9301       FETCH_DATA (info, codep + 1);
9302       modrm.mod = (*codep >> 6) & 3;
9303       modrm.reg = (*codep >> 3) & 7;
9304       modrm.rm = *codep & 7;
9305
9306       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9307          having to decode the bits for every otherwise valid encoding.  */
9308       if (vex.prefix)
9309         return &bad_opcode;
9310       break;
9311
9312     case USE_VEX_C4_TABLE:
9313       /* VEX prefix.  */
9314       FETCH_DATA (info, codep + 3);
9315       rex = ~(*codep >> 5) & 0x7;
9316       switch ((*codep & 0x1f))
9317         {
9318         default:
9319           dp = &bad_opcode;
9320           return dp;
9321         case 0x1:
9322           vex_table_index = VEX_0F;
9323           break;
9324         case 0x2:
9325           vex_table_index = VEX_0F38;
9326           break;
9327         case 0x3:
9328           vex_table_index = VEX_0F3A;
9329           break;
9330         }
9331       codep++;
9332       vex.w = *codep & 0x80;
9333       if (address_mode == mode_64bit)
9334         {
9335           if (vex.w)
9336             rex |= REX_W;
9337         }
9338       else
9339         {
9340           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9341              is ignored, other REX bits are 0 and the highest bit in
9342              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9343           rex = 0;
9344         }
9345       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9346       vex.length = (*codep & 0x4) ? 256 : 128;
9347       switch ((*codep & 0x3))
9348         {
9349         case 0:
9350           break;
9351         case 1:
9352           vex.prefix = DATA_PREFIX_OPCODE;
9353           break;
9354         case 2:
9355           vex.prefix = REPE_PREFIX_OPCODE;
9356           break;
9357         case 3:
9358           vex.prefix = REPNE_PREFIX_OPCODE;
9359           break;
9360         }
9361       need_vex = 1;
9362       codep++;
9363       vindex = *codep++;
9364       dp = &vex_table[vex_table_index][vindex];
9365       end_codep = codep;
9366       /* There is no MODRM byte for VEX0F 77.  */
9367       if (vex_table_index != VEX_0F || vindex != 0x77)
9368         {
9369           FETCH_DATA (info, codep + 1);
9370           modrm.mod = (*codep >> 6) & 3;
9371           modrm.reg = (*codep >> 3) & 7;
9372           modrm.rm = *codep & 7;
9373         }
9374       break;
9375
9376     case USE_VEX_C5_TABLE:
9377       /* VEX prefix.  */
9378       FETCH_DATA (info, codep + 2);
9379       rex = (*codep & 0x80) ? 0 : REX_R;
9380
9381       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9382          VEX.vvvv is 1.  */
9383       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9384       vex.length = (*codep & 0x4) ? 256 : 128;
9385       switch ((*codep & 0x3))
9386         {
9387         case 0:
9388           break;
9389         case 1:
9390           vex.prefix = DATA_PREFIX_OPCODE;
9391           break;
9392         case 2:
9393           vex.prefix = REPE_PREFIX_OPCODE;
9394           break;
9395         case 3:
9396           vex.prefix = REPNE_PREFIX_OPCODE;
9397           break;
9398         }
9399       need_vex = 1;
9400       codep++;
9401       vindex = *codep++;
9402       dp = &vex_table[dp->op[1].bytemode][vindex];
9403       end_codep = codep;
9404       /* There is no MODRM byte for VEX 77.  */
9405       if (vindex != 0x77)
9406         {
9407           FETCH_DATA (info, codep + 1);
9408           modrm.mod = (*codep >> 6) & 3;
9409           modrm.reg = (*codep >> 3) & 7;
9410           modrm.rm = *codep & 7;
9411         }
9412       break;
9413
9414     case USE_VEX_W_TABLE:
9415       if (!need_vex)
9416         abort ();
9417
9418       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9419       break;
9420
9421     case USE_EVEX_TABLE:
9422       two_source_ops = 0;
9423       /* EVEX prefix.  */
9424       vex.evex = 1;
9425       FETCH_DATA (info, codep + 4);
9426       /* The first byte after 0x62.  */
9427       rex = ~(*codep >> 5) & 0x7;
9428       vex.r = *codep & 0x10;
9429       switch ((*codep & 0xf))
9430         {
9431         default:
9432           return &bad_opcode;
9433         case 0x1:
9434           vex_table_index = EVEX_0F;
9435           break;
9436         case 0x2:
9437           vex_table_index = EVEX_0F38;
9438           break;
9439         case 0x3:
9440           vex_table_index = EVEX_0F3A;
9441           break;
9442         }
9443
9444       /* The second byte after 0x62.  */
9445       codep++;
9446       vex.w = *codep & 0x80;
9447       if (vex.w && address_mode == mode_64bit)
9448         rex |= REX_W;
9449
9450       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9451
9452       /* The U bit.  */
9453       if (!(*codep & 0x4))
9454         return &bad_opcode;
9455
9456       switch ((*codep & 0x3))
9457         {
9458         case 0:
9459           break;
9460         case 1:
9461           vex.prefix = DATA_PREFIX_OPCODE;
9462           break;
9463         case 2:
9464           vex.prefix = REPE_PREFIX_OPCODE;
9465           break;
9466         case 3:
9467           vex.prefix = REPNE_PREFIX_OPCODE;
9468           break;
9469         }
9470
9471       /* The third byte after 0x62.  */
9472       codep++;
9473
9474       /* Remember the static rounding bits.  */
9475       vex.ll = (*codep >> 5) & 3;
9476       vex.b = (*codep & 0x10) != 0;
9477
9478       vex.v = *codep & 0x8;
9479       vex.mask_register_specifier = *codep & 0x7;
9480       vex.zeroing = *codep & 0x80;
9481
9482       if (address_mode != mode_64bit)
9483         {
9484           /* In 16/32-bit mode silently ignore following bits.  */
9485           rex &= ~REX_B;
9486           vex.r = 1;
9487           vex.v = 1;
9488         }
9489
9490       need_vex = 1;
9491       codep++;
9492       vindex = *codep++;
9493       dp = &evex_table[vex_table_index][vindex];
9494       end_codep = codep;
9495       FETCH_DATA (info, codep + 1);
9496       modrm.mod = (*codep >> 6) & 3;
9497       modrm.reg = (*codep >> 3) & 7;
9498       modrm.rm = *codep & 7;
9499
9500       /* Set vector length.  */
9501       if (modrm.mod == 3 && vex.b)
9502         vex.length = 512;
9503       else
9504         {
9505           switch (vex.ll)
9506             {
9507             case 0x0:
9508               vex.length = 128;
9509               break;
9510             case 0x1:
9511               vex.length = 256;
9512               break;
9513             case 0x2:
9514               vex.length = 512;
9515               break;
9516             default:
9517               return &bad_opcode;
9518             }
9519         }
9520       break;
9521
9522     case 0:
9523       dp = &bad_opcode;
9524       break;
9525
9526     default:
9527       abort ();
9528     }
9529
9530   if (dp->name != NULL)
9531     return dp;
9532   else
9533     return get_valid_dis386 (dp, info);
9534 }
9535
9536 static void
9537 get_sib (disassemble_info *info, int sizeflag)
9538 {
9539   /* If modrm.mod == 3, operand must be register.  */
9540   if (need_modrm
9541       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9542       && modrm.mod != 3
9543       && modrm.rm == 4)
9544     {
9545       FETCH_DATA (info, codep + 2);
9546       sib.index = (codep [1] >> 3) & 7;
9547       sib.scale = (codep [1] >> 6) & 3;
9548       sib.base = codep [1] & 7;
9549     }
9550 }
9551
9552 static int
9553 print_insn (bfd_vma pc, disassemble_info *info)
9554 {
9555   const struct dis386 *dp;
9556   int i;
9557   char *op_txt[MAX_OPERANDS];
9558   int needcomma;
9559   int sizeflag, orig_sizeflag;
9560   const char *p;
9561   struct dis_private priv;
9562   int prefix_length;
9563
9564   priv.orig_sizeflag = AFLAG | DFLAG;
9565   if ((info->mach & bfd_mach_i386_i386) != 0)
9566     address_mode = mode_32bit;
9567   else if (info->mach == bfd_mach_i386_i8086)
9568     {
9569       address_mode = mode_16bit;
9570       priv.orig_sizeflag = 0;
9571     }
9572   else
9573     address_mode = mode_64bit;
9574
9575   if (intel_syntax == (char) -1)
9576     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9577
9578   for (p = info->disassembler_options; p != NULL; )
9579     {
9580       if (CONST_STRNEQ (p, "amd64"))
9581         isa64 = amd64;
9582       else if (CONST_STRNEQ (p, "intel64"))
9583         isa64 = intel64;
9584       else if (CONST_STRNEQ (p, "x86-64"))
9585         {
9586           address_mode = mode_64bit;
9587           priv.orig_sizeflag |= AFLAG | DFLAG;
9588         }
9589       else if (CONST_STRNEQ (p, "i386"))
9590         {
9591           address_mode = mode_32bit;
9592           priv.orig_sizeflag |= AFLAG | DFLAG;
9593         }
9594       else if (CONST_STRNEQ (p, "i8086"))
9595         {
9596           address_mode = mode_16bit;
9597           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9598         }
9599       else if (CONST_STRNEQ (p, "intel"))
9600         {
9601           intel_syntax = 1;
9602           if (CONST_STRNEQ (p + 5, "-mnemonic"))
9603             intel_mnemonic = 1;
9604         }
9605       else if (CONST_STRNEQ (p, "att"))
9606         {
9607           intel_syntax = 0;
9608           if (CONST_STRNEQ (p + 3, "-mnemonic"))
9609             intel_mnemonic = 0;
9610         }
9611       else if (CONST_STRNEQ (p, "addr"))
9612         {
9613           if (address_mode == mode_64bit)
9614             {
9615               if (p[4] == '3' && p[5] == '2')
9616                 priv.orig_sizeflag &= ~AFLAG;
9617               else if (p[4] == '6' && p[5] == '4')
9618                 priv.orig_sizeflag |= AFLAG;
9619             }
9620           else
9621             {
9622               if (p[4] == '1' && p[5] == '6')
9623                 priv.orig_sizeflag &= ~AFLAG;
9624               else if (p[4] == '3' && p[5] == '2')
9625                 priv.orig_sizeflag |= AFLAG;
9626             }
9627         }
9628       else if (CONST_STRNEQ (p, "data"))
9629         {
9630           if (p[4] == '1' && p[5] == '6')
9631             priv.orig_sizeflag &= ~DFLAG;
9632           else if (p[4] == '3' && p[5] == '2')
9633             priv.orig_sizeflag |= DFLAG;
9634         }
9635       else if (CONST_STRNEQ (p, "suffix"))
9636         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9637
9638       p = strchr (p, ',');
9639       if (p != NULL)
9640         p++;
9641     }
9642
9643   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9644     {
9645       (*info->fprintf_func) (info->stream,
9646                              _("64-bit address is disabled"));
9647       return -1;
9648     }
9649
9650   if (intel_syntax)
9651     {
9652       names64 = intel_names64;
9653       names32 = intel_names32;
9654       names16 = intel_names16;
9655       names8 = intel_names8;
9656       names8rex = intel_names8rex;
9657       names_seg = intel_names_seg;
9658       names_mm = intel_names_mm;
9659       names_bnd = intel_names_bnd;
9660       names_xmm = intel_names_xmm;
9661       names_ymm = intel_names_ymm;
9662       names_zmm = intel_names_zmm;
9663       names_tmm = intel_names_tmm;
9664       index64 = intel_index64;
9665       index32 = intel_index32;
9666       names_mask = intel_names_mask;
9667       index16 = intel_index16;
9668       open_char = '[';
9669       close_char = ']';
9670       separator_char = '+';
9671       scale_char = '*';
9672     }
9673   else
9674     {
9675       names64 = att_names64;
9676       names32 = att_names32;
9677       names16 = att_names16;
9678       names8 = att_names8;
9679       names8rex = att_names8rex;
9680       names_seg = att_names_seg;
9681       names_mm = att_names_mm;
9682       names_bnd = att_names_bnd;
9683       names_xmm = att_names_xmm;
9684       names_ymm = att_names_ymm;
9685       names_zmm = att_names_zmm;
9686       names_tmm = att_names_tmm;
9687       index64 = att_index64;
9688       index32 = att_index32;
9689       names_mask = att_names_mask;
9690       index16 = att_index16;
9691       open_char = '(';
9692       close_char =  ')';
9693       separator_char = ',';
9694       scale_char = ',';
9695     }
9696
9697   /* The output looks better if we put 7 bytes on a line, since that
9698      puts most long word instructions on a single line.  Use 8 bytes
9699      for Intel L1OM.  */
9700   if ((info->mach & bfd_mach_l1om) != 0)
9701     info->bytes_per_line = 8;
9702   else
9703     info->bytes_per_line = 7;
9704
9705   info->private_data = &priv;
9706   priv.max_fetched = priv.the_buffer;
9707   priv.insn_start = pc;
9708
9709   obuf[0] = 0;
9710   for (i = 0; i < MAX_OPERANDS; ++i)
9711     {
9712       op_out[i][0] = 0;
9713       op_index[i] = -1;
9714     }
9715
9716   the_info = info;
9717   start_pc = pc;
9718   start_codep = priv.the_buffer;
9719   codep = priv.the_buffer;
9720
9721   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9722     {
9723       const char *name;
9724
9725       /* Getting here means we tried for data but didn't get it.  That
9726          means we have an incomplete instruction of some sort.  Just
9727          print the first byte as a prefix or a .byte pseudo-op.  */
9728       if (codep > priv.the_buffer)
9729         {
9730           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9731           if (name != NULL)
9732             (*info->fprintf_func) (info->stream, "%s", name);
9733           else
9734             {
9735               /* Just print the first byte as a .byte instruction.  */
9736               (*info->fprintf_func) (info->stream, ".byte 0x%x",
9737                                      (unsigned int) priv.the_buffer[0]);
9738             }
9739
9740           return 1;
9741         }
9742
9743       return -1;
9744     }
9745
9746   obufp = obuf;
9747   sizeflag = priv.orig_sizeflag;
9748
9749   if (!ckprefix () || rex_used)
9750     {
9751       /* Too many prefixes or unused REX prefixes.  */
9752       for (i = 0;
9753            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9754            i++)
9755         (*info->fprintf_func) (info->stream, "%s%s",
9756                                i == 0 ? "" : " ",
9757                                prefix_name (all_prefixes[i], sizeflag));
9758       return i;
9759     }
9760
9761   insn_codep = codep;
9762
9763   FETCH_DATA (info, codep + 1);
9764   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9765
9766   if (((prefixes & PREFIX_FWAIT)
9767        && ((*codep < 0xd8) || (*codep > 0xdf))))
9768     {
9769       /* Handle prefixes before fwait.  */
9770       for (i = 0; i < fwait_prefix && all_prefixes[i];
9771            i++)
9772         (*info->fprintf_func) (info->stream, "%s ",
9773                                prefix_name (all_prefixes[i], sizeflag));
9774       (*info->fprintf_func) (info->stream, "fwait");
9775       return i + 1;
9776     }
9777
9778   if (*codep == 0x0f)
9779     {
9780       unsigned char threebyte;
9781
9782       codep++;
9783       FETCH_DATA (info, codep + 1);
9784       threebyte = *codep;
9785       dp = &dis386_twobyte[threebyte];
9786       need_modrm = twobyte_has_modrm[*codep];
9787       codep++;
9788     }
9789   else
9790     {
9791       dp = &dis386[*codep];
9792       need_modrm = onebyte_has_modrm[*codep];
9793       codep++;
9794     }
9795
9796   /* Save sizeflag for printing the extra prefixes later before updating
9797      it for mnemonic and operand processing.  The prefix names depend
9798      only on the address mode.  */
9799   orig_sizeflag = sizeflag;
9800   if (prefixes & PREFIX_ADDR)
9801     sizeflag ^= AFLAG;
9802   if ((prefixes & PREFIX_DATA))
9803     sizeflag ^= DFLAG;
9804
9805   end_codep = codep;
9806   if (need_modrm)
9807     {
9808       FETCH_DATA (info, codep + 1);
9809       modrm.mod = (*codep >> 6) & 3;
9810       modrm.reg = (*codep >> 3) & 7;
9811       modrm.rm = *codep & 7;
9812     }
9813
9814   need_vex = 0;
9815   memset (&vex, 0, sizeof (vex));
9816
9817   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9818     {
9819       get_sib (info, sizeflag);
9820       dofloat (sizeflag);
9821     }
9822   else
9823     {
9824       dp = get_valid_dis386 (dp, info);
9825       if (dp != NULL && putop (dp->name, sizeflag) == 0)
9826         {
9827           get_sib (info, sizeflag);
9828           for (i = 0; i < MAX_OPERANDS; ++i)
9829             {
9830               obufp = op_out[i];
9831               op_ad = MAX_OPERANDS - 1 - i;
9832               if (dp->op[i].rtn)
9833                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9834               /* For EVEX instruction after the last operand masking
9835                  should be printed.  */
9836               if (i == 0 && vex.evex)
9837                 {
9838                   /* Don't print {%k0}.  */
9839                   if (vex.mask_register_specifier)
9840                     {
9841                       oappend ("{");
9842                       oappend (names_mask[vex.mask_register_specifier]);
9843                       oappend ("}");
9844                     }
9845                   if (vex.zeroing)
9846                     oappend ("{z}");
9847                 }
9848             }
9849         }
9850     }
9851
9852   /* Clear instruction information.  */
9853   if (the_info)
9854     {
9855       the_info->insn_info_valid = 0;
9856       the_info->branch_delay_insns = 0;
9857       the_info->data_size = 0;
9858       the_info->insn_type = dis_noninsn;
9859       the_info->target = 0;
9860       the_info->target2 = 0;
9861     }
9862
9863   /* Reset jump operation indicator.  */
9864   op_is_jump = FALSE;
9865
9866   {
9867     int jump_detection = 0;
9868
9869     /* Extract flags.  */
9870     for (i = 0; i < MAX_OPERANDS; ++i)
9871       {
9872         if ((dp->op[i].rtn == OP_J)
9873             || (dp->op[i].rtn == OP_indirE))
9874           jump_detection |= 1;
9875         else if ((dp->op[i].rtn == BND_Fixup)
9876                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9877           jump_detection |= 2;
9878         else if ((dp->op[i].bytemode == cond_jump_mode)
9879                  || (dp->op[i].bytemode == loop_jcxz_mode))
9880           jump_detection |= 4;
9881       }
9882
9883     /* Determine if this is a jump or branch.  */
9884     if ((jump_detection & 0x3) == 0x3)
9885       {
9886         op_is_jump = TRUE;
9887         if (jump_detection & 0x4)
9888           the_info->insn_type = dis_condbranch;
9889         else
9890           the_info->insn_type =
9891             (dp->name && !strncmp(dp->name, "call", 4))
9892             ? dis_jsr : dis_branch;
9893       }
9894   }
9895
9896   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9897      are all 0s in inverted form.  */
9898   if (need_vex && vex.register_specifier != 0)
9899     {
9900       (*info->fprintf_func) (info->stream, "(bad)");
9901       return end_codep - priv.the_buffer;
9902     }
9903
9904   switch (dp->prefix_requirement)
9905     {
9906     case PREFIX_DATA:
9907       /* If only the data prefix is marked as mandatory, its absence renders
9908          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9909       if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9910         {
9911           (*info->fprintf_func) (info->stream, "(bad)");
9912           return end_codep - priv.the_buffer;
9913         }
9914       used_prefixes |= PREFIX_DATA;
9915       /* Fall through.  */
9916     case PREFIX_OPCODE:
9917       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9918          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9919          used by putop and MMX/SSE operand and may be overridden by the
9920          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9921          separately.  */
9922       if (((need_vex
9923             ? vex.prefix == REPE_PREFIX_OPCODE
9924               || vex.prefix == REPNE_PREFIX_OPCODE
9925             : (prefixes
9926                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9927            && (used_prefixes
9928                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9929           || (((need_vex
9930                 ? vex.prefix == DATA_PREFIX_OPCODE
9931                 : ((prefixes
9932                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9933                    == PREFIX_DATA))
9934                && (used_prefixes & PREFIX_DATA) == 0))
9935           || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9936               && !vex.w != !(used_prefixes & PREFIX_DATA)))
9937         {
9938           (*info->fprintf_func) (info->stream, "(bad)");
9939           return end_codep - priv.the_buffer;
9940         }
9941       break;
9942     }
9943
9944   /* Check if the REX prefix is used.  */
9945   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9946     all_prefixes[last_rex_prefix] = 0;
9947
9948   /* Check if the SEG prefix is used.  */
9949   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9950                    | PREFIX_FS | PREFIX_GS)) != 0
9951       && (used_prefixes & active_seg_prefix) != 0)
9952     all_prefixes[last_seg_prefix] = 0;
9953
9954   /* Check if the ADDR prefix is used.  */
9955   if ((prefixes & PREFIX_ADDR) != 0
9956       && (used_prefixes & PREFIX_ADDR) != 0)
9957     all_prefixes[last_addr_prefix] = 0;
9958
9959   /* Check if the DATA prefix is used.  */
9960   if ((prefixes & PREFIX_DATA) != 0
9961       && (used_prefixes & PREFIX_DATA) != 0
9962       && !need_vex)
9963     all_prefixes[last_data_prefix] = 0;
9964
9965   /* Print the extra prefixes.  */
9966   prefix_length = 0;
9967   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9968     if (all_prefixes[i])
9969       {
9970         const char *name;
9971         name = prefix_name (all_prefixes[i], orig_sizeflag);
9972         if (name == NULL)
9973           abort ();
9974         prefix_length += strlen (name) + 1;
9975         (*info->fprintf_func) (info->stream, "%s ", name);
9976       }
9977
9978   /* Check maximum code length.  */
9979   if ((codep - start_codep) > MAX_CODE_LENGTH)
9980     {
9981       (*info->fprintf_func) (info->stream, "(bad)");
9982       return MAX_CODE_LENGTH;
9983     }
9984
9985   obufp = mnemonicendp;
9986   for (i = strlen (obuf) + prefix_length; i < 6; i++)
9987     oappend (" ");
9988   oappend (" ");
9989   (*info->fprintf_func) (info->stream, "%s", obuf);
9990
9991   /* The enter and bound instructions are printed with operands in the same
9992      order as the intel book; everything else is printed in reverse order.  */
9993   if (intel_syntax || two_source_ops)
9994     {
9995       bfd_vma riprel;
9996
9997       for (i = 0; i < MAX_OPERANDS; ++i)
9998         op_txt[i] = op_out[i];
9999
10000       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10001           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10002         {
10003           op_txt[2] = op_out[3];
10004           op_txt[3] = op_out[2];
10005         }
10006
10007       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10008         {
10009           op_ad = op_index[i];
10010           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10011           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10012           riprel = op_riprel[i];
10013           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10014           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10015         }
10016     }
10017   else
10018     {
10019       for (i = 0; i < MAX_OPERANDS; ++i)
10020         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10021     }
10022
10023   needcomma = 0;
10024   for (i = 0; i < MAX_OPERANDS; ++i)
10025     if (*op_txt[i])
10026       {
10027         if (needcomma)
10028           (*info->fprintf_func) (info->stream, ",");
10029         if (op_index[i] != -1 && !op_riprel[i])
10030           {
10031             bfd_vma target = (bfd_vma) op_address[op_index[i]];
10032
10033             if (the_info && op_is_jump)
10034               {
10035                 the_info->insn_info_valid = 1;
10036                 the_info->branch_delay_insns = 0;
10037                 the_info->data_size = 0;
10038                 the_info->target = target;
10039                 the_info->target2 = 0;
10040               }
10041             (*info->print_address_func) (target, info);
10042           }
10043         else
10044           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10045         needcomma = 1;
10046       }
10047
10048   for (i = 0; i < MAX_OPERANDS; i++)
10049     if (op_index[i] != -1 && op_riprel[i])
10050       {
10051         (*info->fprintf_func) (info->stream, "        # ");
10052         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10053                                                 + op_address[op_index[i]]), info);
10054         break;
10055       }
10056   return codep - priv.the_buffer;
10057 }
10058
10059 static const char *float_mem[] = {
10060   /* d8 */
10061   "fadd{s|}",
10062   "fmul{s|}",
10063   "fcom{s|}",
10064   "fcomp{s|}",
10065   "fsub{s|}",
10066   "fsubr{s|}",
10067   "fdiv{s|}",
10068   "fdivr{s|}",
10069   /* d9 */
10070   "fld{s|}",
10071   "(bad)",
10072   "fst{s|}",
10073   "fstp{s|}",
10074   "fldenv{C|C}",
10075   "fldcw",
10076   "fNstenv{C|C}",
10077   "fNstcw",
10078   /* da */
10079   "fiadd{l|}",
10080   "fimul{l|}",
10081   "ficom{l|}",
10082   "ficomp{l|}",
10083   "fisub{l|}",
10084   "fisubr{l|}",
10085   "fidiv{l|}",
10086   "fidivr{l|}",
10087   /* db */
10088   "fild{l|}",
10089   "fisttp{l|}",
10090   "fist{l|}",
10091   "fistp{l|}",
10092   "(bad)",
10093   "fld{t|}",
10094   "(bad)",
10095   "fstp{t|}",
10096   /* dc */
10097   "fadd{l|}",
10098   "fmul{l|}",
10099   "fcom{l|}",
10100   "fcomp{l|}",
10101   "fsub{l|}",
10102   "fsubr{l|}",
10103   "fdiv{l|}",
10104   "fdivr{l|}",
10105   /* dd */
10106   "fld{l|}",
10107   "fisttp{ll|}",
10108   "fst{l||}",
10109   "fstp{l|}",
10110   "frstor{C|C}",
10111   "(bad)",
10112   "fNsave{C|C}",
10113   "fNstsw",
10114   /* de */
10115   "fiadd{s|}",
10116   "fimul{s|}",
10117   "ficom{s|}",
10118   "ficomp{s|}",
10119   "fisub{s|}",
10120   "fisubr{s|}",
10121   "fidiv{s|}",
10122   "fidivr{s|}",
10123   /* df */
10124   "fild{s|}",
10125   "fisttp{s|}",
10126   "fist{s|}",
10127   "fistp{s|}",
10128   "fbld",
10129   "fild{ll|}",
10130   "fbstp",
10131   "fistp{ll|}",
10132 };
10133
10134 static const unsigned char float_mem_mode[] = {
10135   /* d8 */
10136   d_mode,
10137   d_mode,
10138   d_mode,
10139   d_mode,
10140   d_mode,
10141   d_mode,
10142   d_mode,
10143   d_mode,
10144   /* d9 */
10145   d_mode,
10146   0,
10147   d_mode,
10148   d_mode,
10149   0,
10150   w_mode,
10151   0,
10152   w_mode,
10153   /* da */
10154   d_mode,
10155   d_mode,
10156   d_mode,
10157   d_mode,
10158   d_mode,
10159   d_mode,
10160   d_mode,
10161   d_mode,
10162   /* db */
10163   d_mode,
10164   d_mode,
10165   d_mode,
10166   d_mode,
10167   0,
10168   t_mode,
10169   0,
10170   t_mode,
10171   /* dc */
10172   q_mode,
10173   q_mode,
10174   q_mode,
10175   q_mode,
10176   q_mode,
10177   q_mode,
10178   q_mode,
10179   q_mode,
10180   /* dd */
10181   q_mode,
10182   q_mode,
10183   q_mode,
10184   q_mode,
10185   0,
10186   0,
10187   0,
10188   w_mode,
10189   /* de */
10190   w_mode,
10191   w_mode,
10192   w_mode,
10193   w_mode,
10194   w_mode,
10195   w_mode,
10196   w_mode,
10197   w_mode,
10198   /* df */
10199   w_mode,
10200   w_mode,
10201   w_mode,
10202   w_mode,
10203   t_mode,
10204   q_mode,
10205   t_mode,
10206   q_mode
10207 };
10208
10209 #define ST { OP_ST, 0 }
10210 #define STi { OP_STi, 0 }
10211
10212 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10213 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10214 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10215 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10216 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10217 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10218 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10219 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10220 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10221
10222 static const struct dis386 float_reg[][8] = {
10223   /* d8 */
10224   {
10225     { "fadd",   { ST, STi }, 0 },
10226     { "fmul",   { ST, STi }, 0 },
10227     { "fcom",   { STi }, 0 },
10228     { "fcomp",  { STi }, 0 },
10229     { "fsub",   { ST, STi }, 0 },
10230     { "fsubr",  { ST, STi }, 0 },
10231     { "fdiv",   { ST, STi }, 0 },
10232     { "fdivr",  { ST, STi }, 0 },
10233   },
10234   /* d9 */
10235   {
10236     { "fld",    { STi }, 0 },
10237     { "fxch",   { STi }, 0 },
10238     { FGRPd9_2 },
10239     { Bad_Opcode },
10240     { FGRPd9_4 },
10241     { FGRPd9_5 },
10242     { FGRPd9_6 },
10243     { FGRPd9_7 },
10244   },
10245   /* da */
10246   {
10247     { "fcmovb", { ST, STi }, 0 },
10248     { "fcmove", { ST, STi }, 0 },
10249     { "fcmovbe",{ ST, STi }, 0 },
10250     { "fcmovu", { ST, STi }, 0 },
10251     { Bad_Opcode },
10252     { FGRPda_5 },
10253     { Bad_Opcode },
10254     { Bad_Opcode },
10255   },
10256   /* db */
10257   {
10258     { "fcmovnb",{ ST, STi }, 0 },
10259     { "fcmovne",{ ST, STi }, 0 },
10260     { "fcmovnbe",{ ST, STi }, 0 },
10261     { "fcmovnu",{ ST, STi }, 0 },
10262     { FGRPdb_4 },
10263     { "fucomi", { ST, STi }, 0 },
10264     { "fcomi",  { ST, STi }, 0 },
10265     { Bad_Opcode },
10266   },
10267   /* dc */
10268   {
10269     { "fadd",   { STi, ST }, 0 },
10270     { "fmul",   { STi, ST }, 0 },
10271     { Bad_Opcode },
10272     { Bad_Opcode },
10273     { "fsub{!M|r}",     { STi, ST }, 0 },
10274     { "fsub{M|}",       { STi, ST }, 0 },
10275     { "fdiv{!M|r}",     { STi, ST }, 0 },
10276     { "fdiv{M|}",       { STi, ST }, 0 },
10277   },
10278   /* dd */
10279   {
10280     { "ffree",  { STi }, 0 },
10281     { Bad_Opcode },
10282     { "fst",    { STi }, 0 },
10283     { "fstp",   { STi }, 0 },
10284     { "fucom",  { STi }, 0 },
10285     { "fucomp", { STi }, 0 },
10286     { Bad_Opcode },
10287     { Bad_Opcode },
10288   },
10289   /* de */
10290   {
10291     { "faddp",  { STi, ST }, 0 },
10292     { "fmulp",  { STi, ST }, 0 },
10293     { Bad_Opcode },
10294     { FGRPde_3 },
10295     { "fsub{!M|r}p",    { STi, ST }, 0 },
10296     { "fsub{M|}p",      { STi, ST }, 0 },
10297     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10298     { "fdiv{M|}p",      { STi, ST }, 0 },
10299   },
10300   /* df */
10301   {
10302     { "ffreep", { STi }, 0 },
10303     { Bad_Opcode },
10304     { Bad_Opcode },
10305     { Bad_Opcode },
10306     { FGRPdf_4 },
10307     { "fucomip", { ST, STi }, 0 },
10308     { "fcomip", { ST, STi }, 0 },
10309     { Bad_Opcode },
10310   },
10311 };
10312
10313 static char *fgrps[][8] = {
10314   /* Bad opcode 0 */
10315   {
10316     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10317   },
10318
10319   /* d9_2  1 */
10320   {
10321     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10322   },
10323
10324   /* d9_4  2 */
10325   {
10326     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10327   },
10328
10329   /* d9_5  3 */
10330   {
10331     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10332   },
10333
10334   /* d9_6  4 */
10335   {
10336     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10337   },
10338
10339   /* d9_7  5 */
10340   {
10341     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10342   },
10343
10344   /* da_5  6 */
10345   {
10346     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10347   },
10348
10349   /* db_4  7 */
10350   {
10351     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10352     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10353   },
10354
10355   /* de_3  8 */
10356   {
10357     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10358   },
10359
10360   /* df_4  9 */
10361   {
10362     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10363   },
10364 };
10365
10366 static void
10367 swap_operand (void)
10368 {
10369   mnemonicendp[0] = '.';
10370   mnemonicendp[1] = 's';
10371   mnemonicendp += 2;
10372 }
10373
10374 static void
10375 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10376                int sizeflag ATTRIBUTE_UNUSED)
10377 {
10378   /* Skip mod/rm byte.  */
10379   MODRM_CHECK;
10380   codep++;
10381 }
10382
10383 static void
10384 dofloat (int sizeflag)
10385 {
10386   const struct dis386 *dp;
10387   unsigned char floatop;
10388
10389   floatop = codep[-1];
10390
10391   if (modrm.mod != 3)
10392     {
10393       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10394
10395       putop (float_mem[fp_indx], sizeflag);
10396       obufp = op_out[0];
10397       op_ad = 2;
10398       OP_E (float_mem_mode[fp_indx], sizeflag);
10399       return;
10400     }
10401   /* Skip mod/rm byte.  */
10402   MODRM_CHECK;
10403   codep++;
10404
10405   dp = &float_reg[floatop - 0xd8][modrm.reg];
10406   if (dp->name == NULL)
10407     {
10408       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10409
10410       /* Instruction fnstsw is only one with strange arg.  */
10411       if (floatop == 0xdf && codep[-1] == 0xe0)
10412         strcpy (op_out[0], names16[0]);
10413     }
10414   else
10415     {
10416       putop (dp->name, sizeflag);
10417
10418       obufp = op_out[0];
10419       op_ad = 2;
10420       if (dp->op[0].rtn)
10421         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10422
10423       obufp = op_out[1];
10424       op_ad = 1;
10425       if (dp->op[1].rtn)
10426         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10427     }
10428 }
10429
10430 /* Like oappend (below), but S is a string starting with '%'.
10431    In Intel syntax, the '%' is elided.  */
10432 static void
10433 oappend_maybe_intel (const char *s)
10434 {
10435   oappend (s + intel_syntax);
10436 }
10437
10438 static void
10439 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10440 {
10441   oappend_maybe_intel ("%st");
10442 }
10443
10444 static void
10445 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10446 {
10447   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10448   oappend_maybe_intel (scratchbuf);
10449 }
10450
10451 /* Capital letters in template are macros.  */
10452 static int
10453 putop (const char *in_template, int sizeflag)
10454 {
10455   const char *p;
10456   int alt = 0;
10457   int cond = 1;
10458   unsigned int l = 0, len = 0;
10459   char last[4];
10460
10461   for (p = in_template; *p; p++)
10462     {
10463       if (len > l)
10464         {
10465           if (l >= sizeof (last) || !ISUPPER (*p))
10466             abort ();
10467           last[l++] = *p;
10468           continue;
10469         }
10470       switch (*p)
10471         {
10472         default:
10473           *obufp++ = *p;
10474           break;
10475         case '%':
10476           len++;
10477           break;
10478         case '!':
10479           cond = 0;
10480           break;
10481         case '{':
10482           if (intel_syntax)
10483             {
10484               while (*++p != '|')
10485                 if (*p == '}' || *p == '\0')
10486                   abort ();
10487               alt = 1;
10488             }
10489           break;
10490         case '|':
10491           while (*++p != '}')
10492             {
10493               if (*p == '\0')
10494                 abort ();
10495             }
10496           break;
10497         case '}':
10498           alt = 0;
10499           break;
10500         case 'A':
10501           if (intel_syntax)
10502             break;
10503           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10504             *obufp++ = 'b';
10505           break;
10506         case 'B':
10507           if (l == 0)
10508             {
10509             case_B:
10510               if (intel_syntax)
10511                 break;
10512               if (sizeflag & SUFFIX_ALWAYS)
10513                 *obufp++ = 'b';
10514             }
10515           else if (l == 1 && last[0] == 'L')
10516             {
10517               if (address_mode == mode_64bit
10518                   && !(prefixes & PREFIX_ADDR))
10519                 {
10520                   *obufp++ = 'a';
10521                   *obufp++ = 'b';
10522                   *obufp++ = 's';
10523                 }
10524
10525               goto case_B;
10526             }
10527           else
10528             abort ();
10529           break;
10530         case 'C':
10531           if (intel_syntax && !alt)
10532             break;
10533           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10534             {
10535               if (sizeflag & DFLAG)
10536                 *obufp++ = intel_syntax ? 'd' : 'l';
10537               else
10538                 *obufp++ = intel_syntax ? 'w' : 's';
10539               used_prefixes |= (prefixes & PREFIX_DATA);
10540             }
10541           break;
10542         case 'D':
10543           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10544             break;
10545           USED_REX (REX_W);
10546           if (modrm.mod == 3)
10547             {
10548               if (rex & REX_W)
10549                 *obufp++ = 'q';
10550               else
10551                 {
10552                   if (sizeflag & DFLAG)
10553                     *obufp++ = intel_syntax ? 'd' : 'l';
10554                   else
10555                     *obufp++ = 'w';
10556                   used_prefixes |= (prefixes & PREFIX_DATA);
10557                 }
10558             }
10559           else
10560             *obufp++ = 'w';
10561           break;
10562         case 'E':               /* For jcxz/jecxz */
10563           if (address_mode == mode_64bit)
10564             {
10565               if (sizeflag & AFLAG)
10566                 *obufp++ = 'r';
10567               else
10568                 *obufp++ = 'e';
10569             }
10570           else
10571             if (sizeflag & AFLAG)
10572               *obufp++ = 'e';
10573           used_prefixes |= (prefixes & PREFIX_ADDR);
10574           break;
10575         case 'F':
10576           if (intel_syntax)
10577             break;
10578           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10579             {
10580               if (sizeflag & AFLAG)
10581                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10582               else
10583                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10584               used_prefixes |= (prefixes & PREFIX_ADDR);
10585             }
10586           break;
10587         case 'G':
10588           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10589             break;
10590           if ((rex & REX_W) || (sizeflag & DFLAG))
10591             *obufp++ = 'l';
10592           else
10593             *obufp++ = 'w';
10594           if (!(rex & REX_W))
10595             used_prefixes |= (prefixes & PREFIX_DATA);
10596           break;
10597         case 'H':
10598           if (intel_syntax)
10599             break;
10600           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10601               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10602             {
10603               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10604               *obufp++ = ',';
10605               *obufp++ = 'p';
10606               if (prefixes & PREFIX_DS)
10607                 *obufp++ = 't';
10608               else
10609                 *obufp++ = 'n';
10610             }
10611           break;
10612         case 'K':
10613           USED_REX (REX_W);
10614           if (rex & REX_W)
10615             *obufp++ = 'q';
10616           else
10617             *obufp++ = 'd';
10618           break;
10619         case 'Z':
10620           if (l != 0)
10621             {
10622               if (l != 1 || last[0] != 'X')
10623                 abort ();
10624               if (!need_vex || !vex.evex)
10625                 abort ();
10626               if (intel_syntax
10627                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10628                 break;
10629               switch (vex.length)
10630                 {
10631                 case 128:
10632                   *obufp++ = 'x';
10633                   break;
10634                 case 256:
10635                   *obufp++ = 'y';
10636                   break;
10637                 case 512:
10638                   *obufp++ = 'z';
10639                   break;
10640                 default:
10641                   abort ();
10642                 }
10643               break;
10644             }
10645           if (intel_syntax)
10646             break;
10647           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10648             {
10649               *obufp++ = 'q';
10650               break;
10651             }
10652           /* Fall through.  */
10653           goto case_L;
10654         case 'L':
10655           if (l != 0)
10656             abort ();
10657         case_L:
10658           if (intel_syntax)
10659             break;
10660           if (sizeflag & SUFFIX_ALWAYS)
10661             *obufp++ = 'l';
10662           break;
10663         case 'M':
10664           if (intel_mnemonic != cond)
10665             *obufp++ = 'r';
10666           break;
10667         case 'N':
10668           if ((prefixes & PREFIX_FWAIT) == 0)
10669             *obufp++ = 'n';
10670           else
10671             used_prefixes |= PREFIX_FWAIT;
10672           break;
10673         case 'O':
10674           USED_REX (REX_W);
10675           if (rex & REX_W)
10676             *obufp++ = 'o';
10677           else if (intel_syntax && (sizeflag & DFLAG))
10678             *obufp++ = 'q';
10679           else
10680             *obufp++ = 'd';
10681           if (!(rex & REX_W))
10682             used_prefixes |= (prefixes & PREFIX_DATA);
10683           break;
10684         case '&':
10685           if (!intel_syntax
10686               && address_mode == mode_64bit
10687               && isa64 == intel64)
10688             {
10689               *obufp++ = 'q';
10690               break;
10691             }
10692           /* Fall through.  */
10693         case 'T':
10694           if (!intel_syntax
10695               && address_mode == mode_64bit
10696               && ((sizeflag & DFLAG) || (rex & REX_W)))
10697             {
10698               *obufp++ = 'q';
10699               break;
10700             }
10701           /* Fall through.  */
10702           goto case_P;
10703         case 'P':
10704           if (l == 0)
10705             {
10706             case_P:
10707               if (intel_syntax)
10708                 {
10709                   if ((rex & REX_W) == 0
10710                       && (prefixes & PREFIX_DATA))
10711                     {
10712                       if ((sizeflag & DFLAG) == 0)
10713                         *obufp++ = 'w';
10714                       used_prefixes |= (prefixes & PREFIX_DATA);
10715                     }
10716                   break;
10717                 }
10718               if ((prefixes & PREFIX_DATA)
10719                   || (rex & REX_W)
10720                   || (sizeflag & SUFFIX_ALWAYS))
10721                 {
10722                   USED_REX (REX_W);
10723                   if (rex & REX_W)
10724                     *obufp++ = 'q';
10725                   else
10726                     {
10727                       if (sizeflag & DFLAG)
10728                         *obufp++ = 'l';
10729                       else
10730                         *obufp++ = 'w';
10731                       used_prefixes |= (prefixes & PREFIX_DATA);
10732                     }
10733                 }
10734             }
10735           else if (l == 1 && last[0] == 'L')
10736             {
10737               if ((prefixes & PREFIX_DATA)
10738                   || (rex & REX_W)
10739                   || (sizeflag & SUFFIX_ALWAYS))
10740                 {
10741                   USED_REX (REX_W);
10742                   if (rex & REX_W)
10743                     *obufp++ = 'q';
10744                   else
10745                     {
10746                       if (sizeflag & DFLAG)
10747                         *obufp++ = intel_syntax ? 'd' : 'l';
10748                       else
10749                         *obufp++ = 'w';
10750                       used_prefixes |= (prefixes & PREFIX_DATA);
10751                     }
10752                 }
10753             }
10754           else
10755             abort ();
10756           break;
10757         case 'U':
10758           if (intel_syntax)
10759             break;
10760           if (address_mode == mode_64bit
10761               && ((sizeflag & DFLAG) || (rex & REX_W)))
10762             {
10763               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10764                 *obufp++ = 'q';
10765               break;
10766             }
10767           /* Fall through.  */
10768           goto case_Q;
10769         case 'Q':
10770           if (l == 0)
10771             {
10772             case_Q:
10773               if (intel_syntax && !alt)
10774                 break;
10775               USED_REX (REX_W);
10776               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10777                 {
10778                   if (rex & REX_W)
10779                     *obufp++ = 'q';
10780                   else
10781                     {
10782                       if (sizeflag & DFLAG)
10783                         *obufp++ = intel_syntax ? 'd' : 'l';
10784                       else
10785                         *obufp++ = 'w';
10786                       used_prefixes |= (prefixes & PREFIX_DATA);
10787                     }
10788                 }
10789             }
10790           else if (l == 1 && last[0] == 'D')
10791             *obufp++ = vex.w ? 'q' : 'd';
10792           else if (l == 1 && last[0] == 'L')
10793             {
10794               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10795                        : address_mode != mode_64bit)
10796                 break;
10797               if ((rex & REX_W))
10798                 {
10799                   USED_REX (REX_W);
10800                   *obufp++ = 'q';
10801                 }
10802               else if((address_mode == mode_64bit && need_modrm && cond)
10803                       || (sizeflag & SUFFIX_ALWAYS))
10804                 *obufp++ = intel_syntax? 'd' : 'l';
10805             }
10806           else
10807             abort ();
10808           break;
10809         case 'R':
10810           USED_REX (REX_W);
10811           if (rex & REX_W)
10812             *obufp++ = 'q';
10813           else if (sizeflag & DFLAG)
10814             {
10815               if (intel_syntax)
10816                   *obufp++ = 'd';
10817               else
10818                   *obufp++ = 'l';
10819             }
10820           else
10821             *obufp++ = 'w';
10822           if (intel_syntax && !p[1]
10823               && ((rex & REX_W) || (sizeflag & DFLAG)))
10824             *obufp++ = 'e';
10825           if (!(rex & REX_W))
10826             used_prefixes |= (prefixes & PREFIX_DATA);
10827           break;
10828         case 'V':
10829           if (l == 0)
10830             {
10831               if (intel_syntax)
10832                 break;
10833               if (address_mode == mode_64bit
10834                   && ((sizeflag & DFLAG) || (rex & REX_W)))
10835                 {
10836                   if (sizeflag & SUFFIX_ALWAYS)
10837                     *obufp++ = 'q';
10838                   break;
10839                 }
10840             }
10841           else if (l == 1 && last[0] == 'L')
10842             {
10843               if (rex & REX_W)
10844                 {
10845                   *obufp++ = 'a';
10846                   *obufp++ = 'b';
10847                   *obufp++ = 's';
10848                 }
10849             }
10850           else
10851             abort ();
10852           /* Fall through.  */
10853           goto case_S;
10854         case 'S':
10855           if (l == 0)
10856             {
10857             case_S:
10858               if (intel_syntax)
10859                 break;
10860               if (sizeflag & SUFFIX_ALWAYS)
10861                 {
10862                   if (rex & REX_W)
10863                     *obufp++ = 'q';
10864                   else
10865                     {
10866                       if (sizeflag & DFLAG)
10867                         *obufp++ = 'l';
10868                       else
10869                         *obufp++ = 'w';
10870                       used_prefixes |= (prefixes & PREFIX_DATA);
10871                     }
10872                 }
10873             }
10874           else if (l == 1 && last[0] == 'L')
10875             {
10876               if (address_mode == mode_64bit
10877                   && !(prefixes & PREFIX_ADDR))
10878                 {
10879                   *obufp++ = 'a';
10880                   *obufp++ = 'b';
10881                   *obufp++ = 's';
10882                 }
10883
10884               goto case_S;
10885             }
10886           else
10887             abort ();
10888           break;
10889         case 'X':
10890           if (l != 0)
10891             abort ();
10892           if (need_vex
10893               ? vex.prefix == DATA_PREFIX_OPCODE
10894               : prefixes & PREFIX_DATA)
10895             {
10896               *obufp++ = 'd';
10897               used_prefixes |= PREFIX_DATA;
10898             }
10899           else
10900             *obufp++ = 's';
10901           break;
10902         case 'Y':
10903           if (l == 1 && last[0] == 'X')
10904             {
10905               if (!need_vex)
10906                 abort ();
10907               if (intel_syntax
10908                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10909                 break;
10910               switch (vex.length)
10911                 {
10912                 case 128:
10913                   *obufp++ = 'x';
10914                   break;
10915                 case 256:
10916                   *obufp++ = 'y';
10917                   break;
10918                 case 512:
10919                   if (!vex.evex)
10920                 default:
10921                     abort ();
10922                 }
10923             }
10924           else
10925             abort ();
10926           break;
10927         case 'W':
10928           if (l == 0)
10929             {
10930               /* operand size flag for cwtl, cbtw */
10931               USED_REX (REX_W);
10932               if (rex & REX_W)
10933                 {
10934                   if (intel_syntax)
10935                     *obufp++ = 'd';
10936                   else
10937                     *obufp++ = 'l';
10938                 }
10939               else if (sizeflag & DFLAG)
10940                 *obufp++ = 'w';
10941               else
10942                 *obufp++ = 'b';
10943               if (!(rex & REX_W))
10944                 used_prefixes |= (prefixes & PREFIX_DATA);
10945             }
10946           else if (l == 1)
10947             {
10948               if (!need_vex)
10949                 abort ();
10950               if (last[0] == 'X')
10951                 *obufp++ = vex.w ? 'd': 's';
10952               else if (last[0] == 'B')
10953                 *obufp++ = vex.w ? 'w': 'b';
10954               else
10955                 abort ();
10956             }
10957           else
10958             abort ();
10959           break;
10960         case '^':
10961           if (intel_syntax)
10962             break;
10963           if (isa64 == intel64 && (rex & REX_W))
10964             {
10965               USED_REX (REX_W);
10966               *obufp++ = 'q';
10967               break;
10968             }
10969           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10970             {
10971               if (sizeflag & DFLAG)
10972                 *obufp++ = 'l';
10973               else
10974                 *obufp++ = 'w';
10975               used_prefixes |= (prefixes & PREFIX_DATA);
10976             }
10977           break;
10978         case '@':
10979           if (intel_syntax)
10980             break;
10981           if (address_mode == mode_64bit
10982               && (isa64 == intel64
10983                   || ((sizeflag & DFLAG) || (rex & REX_W))))
10984               *obufp++ = 'q';
10985           else if ((prefixes & PREFIX_DATA))
10986             {
10987               if (!(sizeflag & DFLAG))
10988                 *obufp++ = 'w';
10989               used_prefixes |= (prefixes & PREFIX_DATA);
10990             }
10991           break;
10992         }
10993
10994       if (len == l)
10995         len = l = 0;
10996     }
10997   *obufp = 0;
10998   mnemonicendp = obufp;
10999   return 0;
11000 }
11001
11002 static void
11003 oappend (const char *s)
11004 {
11005   obufp = stpcpy (obufp, s);
11006 }
11007
11008 static void
11009 append_seg (void)
11010 {
11011   /* Only print the active segment register.  */
11012   if (!active_seg_prefix)
11013     return;
11014
11015   used_prefixes |= active_seg_prefix;
11016   switch (active_seg_prefix)
11017     {
11018     case PREFIX_CS:
11019       oappend_maybe_intel ("%cs:");
11020       break;
11021     case PREFIX_DS:
11022       oappend_maybe_intel ("%ds:");
11023       break;
11024     case PREFIX_SS:
11025       oappend_maybe_intel ("%ss:");
11026       break;
11027     case PREFIX_ES:
11028       oappend_maybe_intel ("%es:");
11029       break;
11030     case PREFIX_FS:
11031       oappend_maybe_intel ("%fs:");
11032       break;
11033     case PREFIX_GS:
11034       oappend_maybe_intel ("%gs:");
11035       break;
11036     default:
11037       break;
11038     }
11039 }
11040
11041 static void
11042 OP_indirE (int bytemode, int sizeflag)
11043 {
11044   if (!intel_syntax)
11045     oappend ("*");
11046   OP_E (bytemode, sizeflag);
11047 }
11048
11049 static void
11050 print_operand_value (char *buf, int hex, bfd_vma disp)
11051 {
11052   if (address_mode == mode_64bit)
11053     {
11054       if (hex)
11055         {
11056           char tmp[30];
11057           int i;
11058           buf[0] = '0';
11059           buf[1] = 'x';
11060           sprintf_vma (tmp, disp);
11061           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11062           strcpy (buf + 2, tmp + i);
11063         }
11064       else
11065         {
11066           bfd_signed_vma v = disp;
11067           char tmp[30];
11068           int i;
11069           if (v < 0)
11070             {
11071               *(buf++) = '-';
11072               v = -disp;
11073               /* Check for possible overflow on 0x8000000000000000.  */
11074               if (v < 0)
11075                 {
11076                   strcpy (buf, "9223372036854775808");
11077                   return;
11078                 }
11079             }
11080           if (!v)
11081             {
11082               strcpy (buf, "0");
11083               return;
11084             }
11085
11086           i = 0;
11087           tmp[29] = 0;
11088           while (v)
11089             {
11090               tmp[28 - i] = (v % 10) + '0';
11091               v /= 10;
11092               i++;
11093             }
11094           strcpy (buf, tmp + 29 - i);
11095         }
11096     }
11097   else
11098     {
11099       if (hex)
11100         sprintf (buf, "0x%x", (unsigned int) disp);
11101       else
11102         sprintf (buf, "%d", (int) disp);
11103     }
11104 }
11105
11106 /* Put DISP in BUF as signed hex number.  */
11107
11108 static void
11109 print_displacement (char *buf, bfd_vma disp)
11110 {
11111   bfd_signed_vma val = disp;
11112   char tmp[30];
11113   int i, j = 0;
11114
11115   if (val < 0)
11116     {
11117       buf[j++] = '-';
11118       val = -disp;
11119
11120       /* Check for possible overflow.  */
11121       if (val < 0)
11122         {
11123           switch (address_mode)
11124             {
11125             case mode_64bit:
11126               strcpy (buf + j, "0x8000000000000000");
11127               break;
11128             case mode_32bit:
11129               strcpy (buf + j, "0x80000000");
11130               break;
11131             case mode_16bit:
11132               strcpy (buf + j, "0x8000");
11133               break;
11134             }
11135           return;
11136         }
11137     }
11138
11139   buf[j++] = '0';
11140   buf[j++] = 'x';
11141
11142   sprintf_vma (tmp, (bfd_vma) val);
11143   for (i = 0; tmp[i] == '0'; i++)
11144     continue;
11145   if (tmp[i] == '\0')
11146     i--;
11147   strcpy (buf + j, tmp + i);
11148 }
11149
11150 static void
11151 intel_operand_size (int bytemode, int sizeflag)
11152 {
11153   if (vex.evex
11154       && vex.b
11155       && (bytemode == x_mode
11156           || bytemode == evex_half_bcst_xmmq_mode))
11157     {
11158       if (vex.w)
11159         oappend ("QWORD PTR ");
11160       else
11161         oappend ("DWORD PTR ");
11162       return;
11163     }
11164   switch (bytemode)
11165     {
11166     case b_mode:
11167     case b_swap_mode:
11168     case dqb_mode:
11169     case db_mode:
11170       oappend ("BYTE PTR ");
11171       break;
11172     case w_mode:
11173     case dw_mode:
11174     case dqw_mode:
11175       oappend ("WORD PTR ");
11176       break;
11177     case indir_v_mode:
11178       if (address_mode == mode_64bit && isa64 == intel64)
11179         {
11180           oappend ("QWORD PTR ");
11181           break;
11182         }
11183       /* Fall through.  */
11184     case stack_v_mode:
11185       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11186         {
11187           oappend ("QWORD PTR ");
11188           break;
11189         }
11190       /* Fall through.  */
11191     case v_mode:
11192     case v_swap_mode:
11193     case dq_mode:
11194       USED_REX (REX_W);
11195       if (rex & REX_W)
11196         oappend ("QWORD PTR ");
11197       else if (bytemode == dq_mode)
11198         oappend ("DWORD PTR ");
11199       else
11200         {
11201           if (sizeflag & DFLAG)
11202             oappend ("DWORD PTR ");
11203           else
11204             oappend ("WORD PTR ");
11205           used_prefixes |= (prefixes & PREFIX_DATA);
11206         }
11207       break;
11208     case z_mode:
11209       if ((rex & REX_W) || (sizeflag & DFLAG))
11210         *obufp++ = 'D';
11211       oappend ("WORD PTR ");
11212       if (!(rex & REX_W))
11213         used_prefixes |= (prefixes & PREFIX_DATA);
11214       break;
11215     case a_mode:
11216       if (sizeflag & DFLAG)
11217         oappend ("QWORD PTR ");
11218       else
11219         oappend ("DWORD PTR ");
11220       used_prefixes |= (prefixes & PREFIX_DATA);
11221       break;
11222     case movsxd_mode:
11223       if (!(sizeflag & DFLAG) && isa64 == intel64)
11224         oappend ("WORD PTR ");
11225       else
11226         oappend ("DWORD PTR ");
11227       used_prefixes |= (prefixes & PREFIX_DATA);
11228       break;
11229     case d_mode:
11230     case d_swap_mode:
11231     case dqd_mode:
11232       oappend ("DWORD PTR ");
11233       break;
11234     case q_mode:
11235     case q_swap_mode:
11236       oappend ("QWORD PTR ");
11237       break;
11238     case m_mode:
11239       if (address_mode == mode_64bit)
11240         oappend ("QWORD PTR ");
11241       else
11242         oappend ("DWORD PTR ");
11243       break;
11244     case f_mode:
11245       if (sizeflag & DFLAG)
11246         oappend ("FWORD PTR ");
11247       else
11248         oappend ("DWORD PTR ");
11249       used_prefixes |= (prefixes & PREFIX_DATA);
11250       break;
11251     case t_mode:
11252       oappend ("TBYTE PTR ");
11253       break;
11254     case x_mode:
11255     case x_swap_mode:
11256     case evex_x_gscat_mode:
11257     case evex_x_nobcst_mode:
11258     case bw_unit_mode:
11259       if (need_vex)
11260         {
11261           switch (vex.length)
11262             {
11263             case 128:
11264               oappend ("XMMWORD PTR ");
11265               break;
11266             case 256:
11267               oappend ("YMMWORD PTR ");
11268               break;
11269             case 512:
11270               oappend ("ZMMWORD PTR ");
11271               break;
11272             default:
11273               abort ();
11274             }
11275         }
11276       else
11277         oappend ("XMMWORD PTR ");
11278       break;
11279     case xmm_mode:
11280       oappend ("XMMWORD PTR ");
11281       break;
11282     case ymm_mode:
11283       oappend ("YMMWORD PTR ");
11284       break;
11285     case xmmq_mode:
11286     case evex_half_bcst_xmmq_mode:
11287       if (!need_vex)
11288         abort ();
11289
11290       switch (vex.length)
11291         {
11292         case 128:
11293           oappend ("QWORD PTR ");
11294           break;
11295         case 256:
11296           oappend ("XMMWORD PTR ");
11297           break;
11298         case 512:
11299           oappend ("YMMWORD PTR ");
11300           break;
11301         default:
11302           abort ();
11303         }
11304       break;
11305     case xmm_mb_mode:
11306       if (!need_vex)
11307         abort ();
11308
11309       switch (vex.length)
11310         {
11311         case 128:
11312         case 256:
11313         case 512:
11314           oappend ("BYTE PTR ");
11315           break;
11316         default:
11317           abort ();
11318         }
11319       break;
11320     case xmm_mw_mode:
11321       if (!need_vex)
11322         abort ();
11323
11324       switch (vex.length)
11325         {
11326         case 128:
11327         case 256:
11328         case 512:
11329           oappend ("WORD PTR ");
11330           break;
11331         default:
11332           abort ();
11333         }
11334       break;
11335     case xmm_md_mode:
11336       if (!need_vex)
11337         abort ();
11338
11339       switch (vex.length)
11340         {
11341         case 128:
11342         case 256:
11343         case 512:
11344           oappend ("DWORD PTR ");
11345           break;
11346         default:
11347           abort ();
11348         }
11349       break;
11350     case xmm_mq_mode:
11351       if (!need_vex)
11352         abort ();
11353
11354       switch (vex.length)
11355         {
11356         case 128:
11357         case 256:
11358         case 512:
11359           oappend ("QWORD PTR ");
11360           break;
11361         default:
11362           abort ();
11363         }
11364       break;
11365     case xmmdw_mode:
11366       if (!need_vex)
11367         abort ();
11368
11369       switch (vex.length)
11370         {
11371         case 128:
11372           oappend ("WORD PTR ");
11373           break;
11374         case 256:
11375           oappend ("DWORD PTR ");
11376           break;
11377         case 512:
11378           oappend ("QWORD PTR ");
11379           break;
11380         default:
11381           abort ();
11382         }
11383       break;
11384     case xmmqd_mode:
11385       if (!need_vex)
11386         abort ();
11387
11388       switch (vex.length)
11389         {
11390         case 128:
11391           oappend ("DWORD PTR ");
11392           break;
11393         case 256:
11394           oappend ("QWORD PTR ");
11395           break;
11396         case 512:
11397           oappend ("XMMWORD PTR ");
11398           break;
11399         default:
11400           abort ();
11401         }
11402       break;
11403     case ymmq_mode:
11404       if (!need_vex)
11405         abort ();
11406
11407       switch (vex.length)
11408         {
11409         case 128:
11410           oappend ("QWORD PTR ");
11411           break;
11412         case 256:
11413           oappend ("YMMWORD PTR ");
11414           break;
11415         case 512:
11416           oappend ("ZMMWORD PTR ");
11417           break;
11418         default:
11419           abort ();
11420         }
11421       break;
11422     case ymmxmm_mode:
11423       if (!need_vex)
11424         abort ();
11425
11426       switch (vex.length)
11427         {
11428         case 128:
11429         case 256:
11430           oappend ("XMMWORD PTR ");
11431           break;
11432         default:
11433           abort ();
11434         }
11435       break;
11436     case o_mode:
11437       oappend ("OWORD PTR ");
11438       break;
11439     case vex_scalar_w_dq_mode:
11440       if (!need_vex)
11441         abort ();
11442
11443       if (vex.w)
11444         oappend ("QWORD PTR ");
11445       else
11446         oappend ("DWORD PTR ");
11447       break;
11448     case vex_vsib_d_w_dq_mode:
11449     case vex_vsib_q_w_dq_mode:
11450       if (!need_vex)
11451         abort ();
11452
11453       if (!vex.evex)
11454         {
11455           if (vex.w)
11456             oappend ("QWORD PTR ");
11457           else
11458             oappend ("DWORD PTR ");
11459         }
11460       else
11461         {
11462           switch (vex.length)
11463             {
11464             case 128:
11465               oappend ("XMMWORD PTR ");
11466               break;
11467             case 256:
11468               oappend ("YMMWORD PTR ");
11469               break;
11470             case 512:
11471               oappend ("ZMMWORD PTR ");
11472               break;
11473             default:
11474               abort ();
11475             }
11476         }
11477       break;
11478     case vex_vsib_q_w_d_mode:
11479     case vex_vsib_d_w_d_mode:
11480       if (!need_vex || !vex.evex)
11481         abort ();
11482
11483       switch (vex.length)
11484         {
11485         case 128:
11486           oappend ("QWORD PTR ");
11487           break;
11488         case 256:
11489           oappend ("XMMWORD PTR ");
11490           break;
11491         case 512:
11492           oappend ("YMMWORD PTR ");
11493           break;
11494         default:
11495           abort ();
11496         }
11497
11498       break;
11499     case mask_bd_mode:
11500       if (!need_vex || vex.length != 128)
11501         abort ();
11502       if (vex.w)
11503         oappend ("DWORD PTR ");
11504       else
11505         oappend ("BYTE PTR ");
11506       break;
11507     case mask_mode:
11508       if (!need_vex)
11509         abort ();
11510       if (vex.w)
11511         oappend ("QWORD PTR ");
11512       else
11513         oappend ("WORD PTR ");
11514       break;
11515     case v_bnd_mode:
11516     case v_bndmk_mode:
11517     default:
11518       break;
11519     }
11520 }
11521
11522 static void
11523 OP_E_register (int bytemode, int sizeflag)
11524 {
11525   int reg = modrm.rm;
11526   const char **names;
11527
11528   USED_REX (REX_B);
11529   if ((rex & REX_B))
11530     reg += 8;
11531
11532   if ((sizeflag & SUFFIX_ALWAYS)
11533       && (bytemode == b_swap_mode
11534           || bytemode == bnd_swap_mode
11535           || bytemode == v_swap_mode))
11536     swap_operand ();
11537
11538   switch (bytemode)
11539     {
11540     case b_mode:
11541     case b_swap_mode:
11542       if (reg & 4)
11543         USED_REX (0);
11544       if (rex)
11545         names = names8rex;
11546       else
11547         names = names8;
11548       break;
11549     case w_mode:
11550       names = names16;
11551       break;
11552     case d_mode:
11553     case dw_mode:
11554     case db_mode:
11555       names = names32;
11556       break;
11557     case q_mode:
11558       names = names64;
11559       break;
11560     case m_mode:
11561     case v_bnd_mode:
11562       names = address_mode == mode_64bit ? names64 : names32;
11563       break;
11564     case bnd_mode:
11565     case bnd_swap_mode:
11566       if (reg > 0x3)
11567         {
11568           oappend ("(bad)");
11569           return;
11570         }
11571       names = names_bnd;
11572       break;
11573     case indir_v_mode:
11574       if (address_mode == mode_64bit && isa64 == intel64)
11575         {
11576           names = names64;
11577           break;
11578         }
11579       /* Fall through.  */
11580     case stack_v_mode:
11581       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11582         {
11583           names = names64;
11584           break;
11585         }
11586       bytemode = v_mode;
11587       /* Fall through.  */
11588     case v_mode:
11589     case v_swap_mode:
11590     case dq_mode:
11591     case dqb_mode:
11592     case dqd_mode:
11593     case dqw_mode:
11594       USED_REX (REX_W);
11595       if (rex & REX_W)
11596         names = names64;
11597       else if (bytemode != v_mode && bytemode != v_swap_mode)
11598         names = names32;
11599       else
11600         {
11601           if (sizeflag & DFLAG)
11602             names = names32;
11603           else
11604             names = names16;
11605           used_prefixes |= (prefixes & PREFIX_DATA);
11606         }
11607       break;
11608     case movsxd_mode:
11609       if (!(sizeflag & DFLAG) && isa64 == intel64)
11610         names = names16;
11611       else
11612         names = names32;
11613       used_prefixes |= (prefixes & PREFIX_DATA);
11614       break;
11615     case va_mode:
11616       names = (address_mode == mode_64bit
11617                ? names64 : names32);
11618       if (!(prefixes & PREFIX_ADDR))
11619         names = (address_mode == mode_16bit
11620                      ? names16 : names);
11621       else
11622         {
11623           /* Remove "addr16/addr32".  */
11624           all_prefixes[last_addr_prefix] = 0;
11625           names = (address_mode != mode_32bit
11626                        ? names32 : names16);
11627           used_prefixes |= PREFIX_ADDR;
11628         }
11629       break;
11630     case mask_bd_mode:
11631     case mask_mode:
11632       if (reg > 0x7)
11633         {
11634           oappend ("(bad)");
11635           return;
11636         }
11637       names = names_mask;
11638       break;
11639     case 0:
11640       return;
11641     default:
11642       oappend (INTERNAL_DISASSEMBLER_ERROR);
11643       return;
11644     }
11645   oappend (names[reg]);
11646 }
11647
11648 static void
11649 OP_E_memory (int bytemode, int sizeflag)
11650 {
11651   bfd_vma disp = 0;
11652   int add = (rex & REX_B) ? 8 : 0;
11653   int riprel = 0;
11654   int shift;
11655
11656   if (vex.evex)
11657     {
11658       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
11659       if (vex.b
11660           && bytemode != x_mode
11661           && bytemode != xmmq_mode
11662           && bytemode != evex_half_bcst_xmmq_mode)
11663         {
11664           BadOp ();
11665           return;
11666         }
11667       switch (bytemode)
11668         {
11669         case dqw_mode:
11670         case dw_mode:
11671         case xmm_mw_mode:
11672           shift = 1;
11673           break;
11674         case dqb_mode:
11675         case db_mode:
11676         case xmm_mb_mode:
11677           shift = 0;
11678           break;
11679         case dq_mode:
11680           if (address_mode != mode_64bit)
11681             {
11682         case dqd_mode:
11683         case xmm_md_mode:
11684         case d_mode:
11685         case d_swap_mode:
11686               shift = 2;
11687               break;
11688             }
11689             /* fall through */
11690         case vex_scalar_w_dq_mode:
11691         case vex_vsib_d_w_dq_mode:
11692         case vex_vsib_d_w_d_mode:
11693         case vex_vsib_q_w_dq_mode:
11694         case vex_vsib_q_w_d_mode:
11695         case evex_x_gscat_mode:
11696           shift = vex.w ? 3 : 2;
11697           break;
11698         case x_mode:
11699         case evex_half_bcst_xmmq_mode:
11700         case xmmq_mode:
11701           if (vex.b)
11702             {
11703               shift = vex.w ? 3 : 2;
11704               break;
11705             }
11706           /* Fall through.  */
11707         case xmmqd_mode:
11708         case xmmdw_mode:
11709         case ymmq_mode:
11710         case evex_x_nobcst_mode:
11711         case x_swap_mode:
11712           switch (vex.length)
11713             {
11714             case 128:
11715               shift = 4;
11716               break;
11717             case 256:
11718               shift = 5;
11719               break;
11720             case 512:
11721               shift = 6;
11722               break;
11723             default:
11724               abort ();
11725             }
11726           /* Make necessary corrections to shift for modes that need it.  */
11727           if (bytemode == xmmq_mode
11728               || bytemode == evex_half_bcst_xmmq_mode
11729               || (bytemode == ymmq_mode && vex.length == 128))
11730             shift -= 1;
11731           else if (bytemode == xmmqd_mode)
11732             shift -= 2;
11733           else if (bytemode == xmmdw_mode)
11734             shift -= 3;
11735           break;
11736         case ymm_mode:
11737           shift = 5;
11738           break;
11739         case xmm_mode:
11740           shift = 4;
11741           break;
11742         case xmm_mq_mode:
11743         case q_mode:
11744         case q_swap_mode:
11745           shift = 3;
11746           break;
11747         case bw_unit_mode:
11748           shift = vex.w ? 1 : 0;
11749           break;
11750         default:
11751           abort ();
11752         }
11753     }
11754   else
11755     shift = 0;
11756
11757   USED_REX (REX_B);
11758   if (intel_syntax)
11759     intel_operand_size (bytemode, sizeflag);
11760   append_seg ();
11761
11762   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11763     {
11764       /* 32/64 bit address mode */
11765       int havedisp;
11766       int havesib;
11767       int havebase;
11768       int haveindex;
11769       int needindex;
11770       int needaddr32;
11771       int base, rbase;
11772       int vindex = 0;
11773       int scale = 0;
11774       int addr32flag = !((sizeflag & AFLAG)
11775                          || bytemode == v_bnd_mode
11776                          || bytemode == v_bndmk_mode
11777                          || bytemode == bnd_mode
11778                          || bytemode == bnd_swap_mode);
11779       const char **indexes64 = names64;
11780       const char **indexes32 = names32;
11781
11782       havesib = 0;
11783       havebase = 1;
11784       haveindex = 0;
11785       base = modrm.rm;
11786
11787       if (base == 4)
11788         {
11789           havesib = 1;
11790           vindex = sib.index;
11791           USED_REX (REX_X);
11792           if (rex & REX_X)
11793             vindex += 8;
11794           switch (bytemode)
11795             {
11796             case vex_vsib_d_w_dq_mode:
11797             case vex_vsib_d_w_d_mode:
11798             case vex_vsib_q_w_dq_mode:
11799             case vex_vsib_q_w_d_mode:
11800               if (!need_vex)
11801                 abort ();
11802               if (vex.evex)
11803                 {
11804                   if (!vex.v)
11805                     vindex += 16;
11806                 }
11807
11808               haveindex = 1;
11809               switch (vex.length)
11810                 {
11811                 case 128:
11812                   indexes64 = indexes32 = names_xmm;
11813                   break;
11814                 case 256:
11815                   if (!vex.w
11816                       || bytemode == vex_vsib_q_w_dq_mode
11817                       || bytemode == vex_vsib_q_w_d_mode)
11818                     indexes64 = indexes32 = names_ymm;
11819                   else
11820                     indexes64 = indexes32 = names_xmm;
11821                   break;
11822                 case 512:
11823                   if (!vex.w
11824                       || bytemode == vex_vsib_q_w_dq_mode
11825                       || bytemode == vex_vsib_q_w_d_mode)
11826                     indexes64 = indexes32 = names_zmm;
11827                   else
11828                     indexes64 = indexes32 = names_ymm;
11829                   break;
11830                 default:
11831                   abort ();
11832                 }
11833               break;
11834             default:
11835               haveindex = vindex != 4;
11836               break;
11837             }
11838           scale = sib.scale;
11839           base = sib.base;
11840           codep++;
11841         }
11842       else
11843         {
11844           /* mandatory non-vector SIB must have sib */
11845           if (bytemode == vex_sibmem_mode)
11846             {
11847               oappend ("(bad)");
11848               return;
11849             }
11850         }
11851       rbase = base + add;
11852
11853       switch (modrm.mod)
11854         {
11855         case 0:
11856           if (base == 5)
11857             {
11858               havebase = 0;
11859               if (address_mode == mode_64bit && !havesib)
11860                 riprel = 1;
11861               disp = get32s ();
11862               if (riprel && bytemode == v_bndmk_mode)
11863                 {
11864                   oappend ("(bad)");
11865                   return;
11866                 }
11867             }
11868           break;
11869         case 1:
11870           FETCH_DATA (the_info, codep + 1);
11871           disp = *codep++;
11872           if ((disp & 0x80) != 0)
11873             disp -= 0x100;
11874           if (vex.evex && shift > 0)
11875             disp <<= shift;
11876           break;
11877         case 2:
11878           disp = get32s ();
11879           break;
11880         }
11881
11882       needindex = 0;
11883       needaddr32 = 0;
11884       if (havesib
11885           && !havebase
11886           && !haveindex
11887           && address_mode != mode_16bit)
11888         {
11889           if (address_mode == mode_64bit)
11890             {
11891               /* Display eiz instead of addr32.  */
11892               needindex = addr32flag;
11893               needaddr32 = 1;
11894             }
11895           else
11896             {
11897               /* In 32-bit mode, we need index register to tell [offset]
11898                  from [eiz*1 + offset].  */
11899               needindex = 1;
11900             }
11901         }
11902
11903       havedisp = (havebase
11904                   || needindex
11905                   || (havesib && (haveindex || scale != 0)));
11906
11907       if (!intel_syntax)
11908         if (modrm.mod != 0 || base == 5)
11909           {
11910             if (havedisp || riprel)
11911               print_displacement (scratchbuf, disp);
11912             else
11913               print_operand_value (scratchbuf, 1, disp);
11914             oappend (scratchbuf);
11915             if (riprel)
11916               {
11917                 set_op (disp, 1);
11918                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11919               }
11920           }
11921
11922       if ((havebase || haveindex || needindex || needaddr32 || riprel)
11923           && (address_mode != mode_64bit
11924               || ((bytemode != v_bnd_mode)
11925                   && (bytemode != v_bndmk_mode)
11926                   && (bytemode != bnd_mode)
11927                   && (bytemode != bnd_swap_mode))))
11928         used_prefixes |= PREFIX_ADDR;
11929
11930       if (havedisp || (intel_syntax && riprel))
11931         {
11932           *obufp++ = open_char;
11933           if (intel_syntax && riprel)
11934             {
11935               set_op (disp, 1);
11936               oappend (!addr32flag ? "rip" : "eip");
11937             }
11938           *obufp = '\0';
11939           if (havebase)
11940             oappend (address_mode == mode_64bit && !addr32flag
11941                      ? names64[rbase] : names32[rbase]);
11942           if (havesib)
11943             {
11944               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11945                  print index to tell base + index from base.  */
11946               if (scale != 0
11947                   || needindex
11948                   || haveindex
11949                   || (havebase && base != ESP_REG_NUM))
11950                 {
11951                   if (!intel_syntax || havebase)
11952                     {
11953                       *obufp++ = separator_char;
11954                       *obufp = '\0';
11955                     }
11956                   if (haveindex)
11957                     oappend (address_mode == mode_64bit && !addr32flag
11958                              ? indexes64[vindex] : indexes32[vindex]);
11959                   else
11960                     oappend (address_mode == mode_64bit && !addr32flag
11961                              ? index64 : index32);
11962
11963                   *obufp++ = scale_char;
11964                   *obufp = '\0';
11965                   sprintf (scratchbuf, "%d", 1 << scale);
11966                   oappend (scratchbuf);
11967                 }
11968             }
11969           if (intel_syntax
11970               && (disp || modrm.mod != 0 || base == 5))
11971             {
11972               if (!havedisp || (bfd_signed_vma) disp >= 0)
11973                 {
11974                   *obufp++ = '+';
11975                   *obufp = '\0';
11976                 }
11977               else if (modrm.mod != 1 && disp != -disp)
11978                 {
11979                   *obufp++ = '-';
11980                   *obufp = '\0';
11981                   disp = - (bfd_signed_vma) disp;
11982                 }
11983
11984               if (havedisp)
11985                 print_displacement (scratchbuf, disp);
11986               else
11987                 print_operand_value (scratchbuf, 1, disp);
11988               oappend (scratchbuf);
11989             }
11990
11991           *obufp++ = close_char;
11992           *obufp = '\0';
11993         }
11994       else if (intel_syntax)
11995         {
11996           if (modrm.mod != 0 || base == 5)
11997             {
11998               if (!active_seg_prefix)
11999                 {
12000                   oappend (names_seg[ds_reg - es_reg]);
12001                   oappend (":");
12002                 }
12003               print_operand_value (scratchbuf, 1, disp);
12004               oappend (scratchbuf);
12005             }
12006         }
12007     }
12008   else if (bytemode == v_bnd_mode
12009            || bytemode == v_bndmk_mode
12010            || bytemode == bnd_mode
12011            || bytemode == bnd_swap_mode)
12012     {
12013       oappend ("(bad)");
12014       return;
12015     }
12016   else
12017     {
12018       /* 16 bit address mode */
12019       used_prefixes |= prefixes & PREFIX_ADDR;
12020       switch (modrm.mod)
12021         {
12022         case 0:
12023           if (modrm.rm == 6)
12024             {
12025               disp = get16 ();
12026               if ((disp & 0x8000) != 0)
12027                 disp -= 0x10000;
12028             }
12029           break;
12030         case 1:
12031           FETCH_DATA (the_info, codep + 1);
12032           disp = *codep++;
12033           if ((disp & 0x80) != 0)
12034             disp -= 0x100;
12035           if (vex.evex && shift > 0)
12036             disp <<= shift;
12037           break;
12038         case 2:
12039           disp = get16 ();
12040           if ((disp & 0x8000) != 0)
12041             disp -= 0x10000;
12042           break;
12043         }
12044
12045       if (!intel_syntax)
12046         if (modrm.mod != 0 || modrm.rm == 6)
12047           {
12048             print_displacement (scratchbuf, disp);
12049             oappend (scratchbuf);
12050           }
12051
12052       if (modrm.mod != 0 || modrm.rm != 6)
12053         {
12054           *obufp++ = open_char;
12055           *obufp = '\0';
12056           oappend (index16[modrm.rm]);
12057           if (intel_syntax
12058               && (disp || modrm.mod != 0 || modrm.rm == 6))
12059             {
12060               if ((bfd_signed_vma) disp >= 0)
12061                 {
12062                   *obufp++ = '+';
12063                   *obufp = '\0';
12064                 }
12065               else if (modrm.mod != 1)
12066                 {
12067                   *obufp++ = '-';
12068                   *obufp = '\0';
12069                   disp = - (bfd_signed_vma) disp;
12070                 }
12071
12072               print_displacement (scratchbuf, disp);
12073               oappend (scratchbuf);
12074             }
12075
12076           *obufp++ = close_char;
12077           *obufp = '\0';
12078         }
12079       else if (intel_syntax)
12080         {
12081           if (!active_seg_prefix)
12082             {
12083               oappend (names_seg[ds_reg - es_reg]);
12084               oappend (":");
12085             }
12086           print_operand_value (scratchbuf, 1, disp & 0xffff);
12087           oappend (scratchbuf);
12088         }
12089     }
12090   if (vex.evex && vex.b
12091       && (bytemode == x_mode
12092           || bytemode == xmmq_mode
12093           || bytemode == evex_half_bcst_xmmq_mode))
12094     {
12095       if (vex.w
12096           || bytemode == xmmq_mode
12097           || bytemode == evex_half_bcst_xmmq_mode)
12098         {
12099           switch (vex.length)
12100             {
12101             case 128:
12102               oappend ("{1to2}");
12103               break;
12104             case 256:
12105               oappend ("{1to4}");
12106               break;
12107             case 512:
12108               oappend ("{1to8}");
12109               break;
12110             default:
12111               abort ();
12112             }
12113         }
12114       else
12115         {
12116           switch (vex.length)
12117             {
12118             case 128:
12119               oappend ("{1to4}");
12120               break;
12121             case 256:
12122               oappend ("{1to8}");
12123               break;
12124             case 512:
12125               oappend ("{1to16}");
12126               break;
12127             default:
12128               abort ();
12129             }
12130         }
12131     }
12132 }
12133
12134 static void
12135 OP_E (int bytemode, int sizeflag)
12136 {
12137   /* Skip mod/rm byte.  */
12138   MODRM_CHECK;
12139   codep++;
12140
12141   if (modrm.mod == 3)
12142     OP_E_register (bytemode, sizeflag);
12143   else
12144     OP_E_memory (bytemode, sizeflag);
12145 }
12146
12147 static void
12148 OP_G (int bytemode, int sizeflag)
12149 {
12150   int add = 0;
12151   const char **names;
12152   USED_REX (REX_R);
12153   if (rex & REX_R)
12154     add += 8;
12155   switch (bytemode)
12156     {
12157     case b_mode:
12158       if (modrm.reg & 4)
12159         USED_REX (0);
12160       if (rex)
12161         oappend (names8rex[modrm.reg + add]);
12162       else
12163         oappend (names8[modrm.reg + add]);
12164       break;
12165     case w_mode:
12166       oappend (names16[modrm.reg + add]);
12167       break;
12168     case d_mode:
12169     case db_mode:
12170     case dw_mode:
12171       oappend (names32[modrm.reg + add]);
12172       break;
12173     case q_mode:
12174       oappend (names64[modrm.reg + add]);
12175       break;
12176     case bnd_mode:
12177       if (modrm.reg > 0x3)
12178         {
12179           oappend ("(bad)");
12180           return;
12181         }
12182       oappend (names_bnd[modrm.reg]);
12183       break;
12184     case v_mode:
12185     case dq_mode:
12186     case dqb_mode:
12187     case dqd_mode:
12188     case dqw_mode:
12189     case movsxd_mode:
12190       USED_REX (REX_W);
12191       if (rex & REX_W)
12192         oappend (names64[modrm.reg + add]);
12193       else if (bytemode != v_mode && bytemode != movsxd_mode)
12194         oappend (names32[modrm.reg + add]);
12195       else
12196         {
12197           if (sizeflag & DFLAG)
12198             oappend (names32[modrm.reg + add]);
12199           else
12200             oappend (names16[modrm.reg + add]);
12201           used_prefixes |= (prefixes & PREFIX_DATA);
12202         }
12203       break;
12204     case va_mode:
12205       names = (address_mode == mode_64bit
12206                ? names64 : names32);
12207       if (!(prefixes & PREFIX_ADDR))
12208         {
12209           if (address_mode == mode_16bit)
12210             names = names16;
12211         }
12212       else
12213         {
12214           /* Remove "addr16/addr32".  */
12215           all_prefixes[last_addr_prefix] = 0;
12216           names = (address_mode != mode_32bit
12217                        ? names32 : names16);
12218           used_prefixes |= PREFIX_ADDR;
12219         }
12220       oappend (names[modrm.reg + add]);
12221       break;
12222     case m_mode:
12223       if (address_mode == mode_64bit)
12224         oappend (names64[modrm.reg + add]);
12225       else
12226         oappend (names32[modrm.reg + add]);
12227       break;
12228     case mask_bd_mode:
12229     case mask_mode:
12230       if ((modrm.reg + add) > 0x7)
12231         {
12232           oappend ("(bad)");
12233           return;
12234         }
12235       oappend (names_mask[modrm.reg + add]);
12236       break;
12237     default:
12238       oappend (INTERNAL_DISASSEMBLER_ERROR);
12239       break;
12240     }
12241 }
12242
12243 static bfd_vma
12244 get64 (void)
12245 {
12246   bfd_vma x;
12247 #ifdef BFD64
12248   unsigned int a;
12249   unsigned int b;
12250
12251   FETCH_DATA (the_info, codep + 8);
12252   a = *codep++ & 0xff;
12253   a |= (*codep++ & 0xff) << 8;
12254   a |= (*codep++ & 0xff) << 16;
12255   a |= (*codep++ & 0xffu) << 24;
12256   b = *codep++ & 0xff;
12257   b |= (*codep++ & 0xff) << 8;
12258   b |= (*codep++ & 0xff) << 16;
12259   b |= (*codep++ & 0xffu) << 24;
12260   x = a + ((bfd_vma) b << 32);
12261 #else
12262   abort ();
12263   x = 0;
12264 #endif
12265   return x;
12266 }
12267
12268 static bfd_signed_vma
12269 get32 (void)
12270 {
12271   bfd_signed_vma x = 0;
12272
12273   FETCH_DATA (the_info, codep + 4);
12274   x = *codep++ & (bfd_signed_vma) 0xff;
12275   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12276   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12277   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12278   return x;
12279 }
12280
12281 static bfd_signed_vma
12282 get32s (void)
12283 {
12284   bfd_signed_vma x = 0;
12285
12286   FETCH_DATA (the_info, codep + 4);
12287   x = *codep++ & (bfd_signed_vma) 0xff;
12288   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12289   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12290   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12291
12292   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12293
12294   return x;
12295 }
12296
12297 static int
12298 get16 (void)
12299 {
12300   int x = 0;
12301
12302   FETCH_DATA (the_info, codep + 2);
12303   x = *codep++ & 0xff;
12304   x |= (*codep++ & 0xff) << 8;
12305   return x;
12306 }
12307
12308 static void
12309 set_op (bfd_vma op, int riprel)
12310 {
12311   op_index[op_ad] = op_ad;
12312   if (address_mode == mode_64bit)
12313     {
12314       op_address[op_ad] = op;
12315       op_riprel[op_ad] = riprel;
12316     }
12317   else
12318     {
12319       /* Mask to get a 32-bit address.  */
12320       op_address[op_ad] = op & 0xffffffff;
12321       op_riprel[op_ad] = riprel & 0xffffffff;
12322     }
12323 }
12324
12325 static void
12326 OP_REG (int code, int sizeflag)
12327 {
12328   const char *s;
12329   int add;
12330
12331   switch (code)
12332     {
12333     case es_reg: case ss_reg: case cs_reg:
12334     case ds_reg: case fs_reg: case gs_reg:
12335       oappend (names_seg[code - es_reg]);
12336       return;
12337     }
12338
12339   USED_REX (REX_B);
12340   if (rex & REX_B)
12341     add = 8;
12342   else
12343     add = 0;
12344
12345   switch (code)
12346     {
12347     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12348     case sp_reg: case bp_reg: case si_reg: case di_reg:
12349       s = names16[code - ax_reg + add];
12350       break;
12351     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12352       USED_REX (0);
12353       /* Fall through.  */
12354     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12355       if (rex)
12356         s = names8rex[code - al_reg + add];
12357       else
12358         s = names8[code - al_reg];
12359       break;
12360     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12361     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12362       if (address_mode == mode_64bit
12363           && ((sizeflag & DFLAG) || (rex & REX_W)))
12364         {
12365           s = names64[code - rAX_reg + add];
12366           break;
12367         }
12368       code += eAX_reg - rAX_reg;
12369       /* Fall through.  */
12370     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12371     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12372       USED_REX (REX_W);
12373       if (rex & REX_W)
12374         s = names64[code - eAX_reg + add];
12375       else
12376         {
12377           if (sizeflag & DFLAG)
12378             s = names32[code - eAX_reg + add];
12379           else
12380             s = names16[code - eAX_reg + add];
12381           used_prefixes |= (prefixes & PREFIX_DATA);
12382         }
12383       break;
12384     default:
12385       s = INTERNAL_DISASSEMBLER_ERROR;
12386       break;
12387     }
12388   oappend (s);
12389 }
12390
12391 static void
12392 OP_IMREG (int code, int sizeflag)
12393 {
12394   const char *s;
12395
12396   switch (code)
12397     {
12398     case indir_dx_reg:
12399       if (intel_syntax)
12400         s = "dx";
12401       else
12402         s = "(%dx)";
12403       break;
12404     case al_reg: case cl_reg:
12405       s = names8[code - al_reg];
12406       break;
12407     case eAX_reg:
12408       USED_REX (REX_W);
12409       if (rex & REX_W)
12410         {
12411           s = *names64;
12412           break;
12413         }
12414       /* Fall through.  */
12415     case z_mode_ax_reg:
12416       if ((rex & REX_W) || (sizeflag & DFLAG))
12417         s = *names32;
12418       else
12419         s = *names16;
12420       if (!(rex & REX_W))
12421         used_prefixes |= (prefixes & PREFIX_DATA);
12422       break;
12423     default:
12424       s = INTERNAL_DISASSEMBLER_ERROR;
12425       break;
12426     }
12427   oappend (s);
12428 }
12429
12430 static void
12431 OP_I (int bytemode, int sizeflag)
12432 {
12433   bfd_signed_vma op;
12434   bfd_signed_vma mask = -1;
12435
12436   switch (bytemode)
12437     {
12438     case b_mode:
12439       FETCH_DATA (the_info, codep + 1);
12440       op = *codep++;
12441       mask = 0xff;
12442       break;
12443     case v_mode:
12444       USED_REX (REX_W);
12445       if (rex & REX_W)
12446         op = get32s ();
12447       else
12448         {
12449           if (sizeflag & DFLAG)
12450             {
12451               op = get32 ();
12452               mask = 0xffffffff;
12453             }
12454           else
12455             {
12456               op = get16 ();
12457               mask = 0xfffff;
12458             }
12459           used_prefixes |= (prefixes & PREFIX_DATA);
12460         }
12461       break;
12462     case d_mode:
12463       mask = 0xffffffff;
12464       op = get32 ();
12465       break;
12466     case w_mode:
12467       mask = 0xfffff;
12468       op = get16 ();
12469       break;
12470     case const_1_mode:
12471       if (intel_syntax)
12472         oappend ("1");
12473       return;
12474     default:
12475       oappend (INTERNAL_DISASSEMBLER_ERROR);
12476       return;
12477     }
12478
12479   op &= mask;
12480   scratchbuf[0] = '$';
12481   print_operand_value (scratchbuf + 1, 1, op);
12482   oappend_maybe_intel (scratchbuf);
12483   scratchbuf[0] = '\0';
12484 }
12485
12486 static void
12487 OP_I64 (int bytemode, int sizeflag)
12488 {
12489   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12490     {
12491       OP_I (bytemode, sizeflag);
12492       return;
12493     }
12494
12495   USED_REX (REX_W);
12496
12497   scratchbuf[0] = '$';
12498   print_operand_value (scratchbuf + 1, 1, get64 ());
12499   oappend_maybe_intel (scratchbuf);
12500   scratchbuf[0] = '\0';
12501 }
12502
12503 static void
12504 OP_sI (int bytemode, int sizeflag)
12505 {
12506   bfd_signed_vma op;
12507
12508   switch (bytemode)
12509     {
12510     case b_mode:
12511     case b_T_mode:
12512       FETCH_DATA (the_info, codep + 1);
12513       op = *codep++;
12514       if ((op & 0x80) != 0)
12515         op -= 0x100;
12516       if (bytemode == b_T_mode)
12517         {
12518           if (address_mode != mode_64bit
12519               || !((sizeflag & DFLAG) || (rex & REX_W)))
12520             {
12521               /* The operand-size prefix is overridden by a REX prefix.  */
12522               if ((sizeflag & DFLAG) || (rex & REX_W))
12523                 op &= 0xffffffff;
12524               else
12525                 op &= 0xffff;
12526           }
12527         }
12528       else
12529         {
12530           if (!(rex & REX_W))
12531             {
12532               if (sizeflag & DFLAG)
12533                 op &= 0xffffffff;
12534               else
12535                 op &= 0xffff;
12536             }
12537         }
12538       break;
12539     case v_mode:
12540       /* The operand-size prefix is overridden by a REX prefix.  */
12541       if ((sizeflag & DFLAG) || (rex & REX_W))
12542         op = get32s ();
12543       else
12544         op = get16 ();
12545       break;
12546     default:
12547       oappend (INTERNAL_DISASSEMBLER_ERROR);
12548       return;
12549     }
12550
12551   scratchbuf[0] = '$';
12552   print_operand_value (scratchbuf + 1, 1, op);
12553   oappend_maybe_intel (scratchbuf);
12554 }
12555
12556 static void
12557 OP_J (int bytemode, int sizeflag)
12558 {
12559   bfd_vma disp;
12560   bfd_vma mask = -1;
12561   bfd_vma segment = 0;
12562
12563   switch (bytemode)
12564     {
12565     case b_mode:
12566       FETCH_DATA (the_info, codep + 1);
12567       disp = *codep++;
12568       if ((disp & 0x80) != 0)
12569         disp -= 0x100;
12570       break;
12571     case v_mode:
12572       if (isa64 != intel64)
12573     case dqw_mode:
12574         USED_REX (REX_W);
12575       if ((sizeflag & DFLAG)
12576           || (address_mode == mode_64bit
12577               && ((isa64 == intel64 && bytemode != dqw_mode)
12578                   || (rex & REX_W))))
12579         disp = get32s ();
12580       else
12581         {
12582           disp = get16 ();
12583           if ((disp & 0x8000) != 0)
12584             disp -= 0x10000;
12585           /* In 16bit mode, address is wrapped around at 64k within
12586              the same segment.  Otherwise, a data16 prefix on a jump
12587              instruction means that the pc is masked to 16 bits after
12588              the displacement is added!  */
12589           mask = 0xffff;
12590           if ((prefixes & PREFIX_DATA) == 0)
12591             segment = ((start_pc + (codep - start_codep))
12592                        & ~((bfd_vma) 0xffff));
12593         }
12594       if (address_mode != mode_64bit
12595           || (isa64 != intel64 && !(rex & REX_W)))
12596         used_prefixes |= (prefixes & PREFIX_DATA);
12597       break;
12598     default:
12599       oappend (INTERNAL_DISASSEMBLER_ERROR);
12600       return;
12601     }
12602   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12603   set_op (disp, 0);
12604   print_operand_value (scratchbuf, 1, disp);
12605   oappend (scratchbuf);
12606 }
12607
12608 static void
12609 OP_SEG (int bytemode, int sizeflag)
12610 {
12611   if (bytemode == w_mode)
12612     oappend (names_seg[modrm.reg]);
12613   else
12614     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12615 }
12616
12617 static void
12618 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12619 {
12620   int seg, offset;
12621
12622   if (sizeflag & DFLAG)
12623     {
12624       offset = get32 ();
12625       seg = get16 ();
12626     }
12627   else
12628     {
12629       offset = get16 ();
12630       seg = get16 ();
12631     }
12632   used_prefixes |= (prefixes & PREFIX_DATA);
12633   if (intel_syntax)
12634     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12635   else
12636     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12637   oappend (scratchbuf);
12638 }
12639
12640 static void
12641 OP_OFF (int bytemode, int sizeflag)
12642 {
12643   bfd_vma off;
12644
12645   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12646     intel_operand_size (bytemode, sizeflag);
12647   append_seg ();
12648
12649   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12650     off = get32 ();
12651   else
12652     off = get16 ();
12653
12654   if (intel_syntax)
12655     {
12656       if (!active_seg_prefix)
12657         {
12658           oappend (names_seg[ds_reg - es_reg]);
12659           oappend (":");
12660         }
12661     }
12662   print_operand_value (scratchbuf, 1, off);
12663   oappend (scratchbuf);
12664 }
12665
12666 static void
12667 OP_OFF64 (int bytemode, int sizeflag)
12668 {
12669   bfd_vma off;
12670
12671   if (address_mode != mode_64bit
12672       || (prefixes & PREFIX_ADDR))
12673     {
12674       OP_OFF (bytemode, sizeflag);
12675       return;
12676     }
12677
12678   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12679     intel_operand_size (bytemode, sizeflag);
12680   append_seg ();
12681
12682   off = get64 ();
12683
12684   if (intel_syntax)
12685     {
12686       if (!active_seg_prefix)
12687         {
12688           oappend (names_seg[ds_reg - es_reg]);
12689           oappend (":");
12690         }
12691     }
12692   print_operand_value (scratchbuf, 1, off);
12693   oappend (scratchbuf);
12694 }
12695
12696 static void
12697 ptr_reg (int code, int sizeflag)
12698 {
12699   const char *s;
12700
12701   *obufp++ = open_char;
12702   used_prefixes |= (prefixes & PREFIX_ADDR);
12703   if (address_mode == mode_64bit)
12704     {
12705       if (!(sizeflag & AFLAG))
12706         s = names32[code - eAX_reg];
12707       else
12708         s = names64[code - eAX_reg];
12709     }
12710   else if (sizeflag & AFLAG)
12711     s = names32[code - eAX_reg];
12712   else
12713     s = names16[code - eAX_reg];
12714   oappend (s);
12715   *obufp++ = close_char;
12716   *obufp = 0;
12717 }
12718
12719 static void
12720 OP_ESreg (int code, int sizeflag)
12721 {
12722   if (intel_syntax)
12723     {
12724       switch (codep[-1])
12725         {
12726         case 0x6d:      /* insw/insl */
12727           intel_operand_size (z_mode, sizeflag);
12728           break;
12729         case 0xa5:      /* movsw/movsl/movsq */
12730         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12731         case 0xab:      /* stosw/stosl */
12732         case 0xaf:      /* scasw/scasl */
12733           intel_operand_size (v_mode, sizeflag);
12734           break;
12735         default:
12736           intel_operand_size (b_mode, sizeflag);
12737         }
12738     }
12739   oappend_maybe_intel ("%es:");
12740   ptr_reg (code, sizeflag);
12741 }
12742
12743 static void
12744 OP_DSreg (int code, int sizeflag)
12745 {
12746   if (intel_syntax)
12747     {
12748       switch (codep[-1])
12749         {
12750         case 0x6f:      /* outsw/outsl */
12751           intel_operand_size (z_mode, sizeflag);
12752           break;
12753         case 0xa5:      /* movsw/movsl/movsq */
12754         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12755         case 0xad:      /* lodsw/lodsl/lodsq */
12756           intel_operand_size (v_mode, sizeflag);
12757           break;
12758         default:
12759           intel_operand_size (b_mode, sizeflag);
12760         }
12761     }
12762   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12763      default segment register DS is printed.  */
12764   if (!active_seg_prefix)
12765     active_seg_prefix = PREFIX_DS;
12766   append_seg ();
12767   ptr_reg (code, sizeflag);
12768 }
12769
12770 static void
12771 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12772 {
12773   int add;
12774   if (rex & REX_R)
12775     {
12776       USED_REX (REX_R);
12777       add = 8;
12778     }
12779   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12780     {
12781       all_prefixes[last_lock_prefix] = 0;
12782       used_prefixes |= PREFIX_LOCK;
12783       add = 8;
12784     }
12785   else
12786     add = 0;
12787   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12788   oappend_maybe_intel (scratchbuf);
12789 }
12790
12791 static void
12792 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12793 {
12794   int add;
12795   USED_REX (REX_R);
12796   if (rex & REX_R)
12797     add = 8;
12798   else
12799     add = 0;
12800   if (intel_syntax)
12801     sprintf (scratchbuf, "db%d", modrm.reg + add);
12802   else
12803     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12804   oappend (scratchbuf);
12805 }
12806
12807 static void
12808 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12809 {
12810   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12811   oappend_maybe_intel (scratchbuf);
12812 }
12813
12814 static void
12815 OP_R (int bytemode, int sizeflag)
12816 {
12817   /* Skip mod/rm byte.  */
12818   MODRM_CHECK;
12819   codep++;
12820   OP_E_register (bytemode, sizeflag);
12821 }
12822
12823 static void
12824 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12825 {
12826   int reg = modrm.reg;
12827   const char **names;
12828
12829   used_prefixes |= (prefixes & PREFIX_DATA);
12830   if (prefixes & PREFIX_DATA)
12831     {
12832       names = names_xmm;
12833       USED_REX (REX_R);
12834       if (rex & REX_R)
12835         reg += 8;
12836     }
12837   else
12838     names = names_mm;
12839   oappend (names[reg]);
12840 }
12841
12842 static void
12843 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12844 {
12845   int reg = modrm.reg;
12846   const char **names;
12847
12848   USED_REX (REX_R);
12849   if (rex & REX_R)
12850     reg += 8;
12851   if (vex.evex)
12852     {
12853       if (!vex.r)
12854         reg += 16;
12855     }
12856
12857   if (need_vex
12858       && bytemode != xmm_mode
12859       && bytemode != xmmq_mode
12860       && bytemode != evex_half_bcst_xmmq_mode
12861       && bytemode != ymm_mode
12862       && bytemode != tmm_mode
12863       && bytemode != scalar_mode)
12864     {
12865       switch (vex.length)
12866         {
12867         case 128:
12868           names = names_xmm;
12869           break;
12870         case 256:
12871           if (vex.w
12872               || (bytemode != vex_vsib_q_w_dq_mode
12873                   && bytemode != vex_vsib_q_w_d_mode))
12874             names = names_ymm;
12875           else
12876             names = names_xmm;
12877           break;
12878         case 512:
12879           names = names_zmm;
12880           break;
12881         default:
12882           abort ();
12883         }
12884     }
12885   else if (bytemode == xmmq_mode
12886            || bytemode == evex_half_bcst_xmmq_mode)
12887     {
12888       switch (vex.length)
12889         {
12890         case 128:
12891         case 256:
12892           names = names_xmm;
12893           break;
12894         case 512:
12895           names = names_ymm;
12896           break;
12897         default:
12898           abort ();
12899         }
12900     }
12901   else if (bytemode == tmm_mode)
12902     {
12903       modrm.reg = reg;
12904       if (reg >= 8)
12905         {
12906           oappend ("(bad)");
12907           return;
12908         }
12909       names = names_tmm;
12910     }
12911   else if (bytemode == ymm_mode)
12912     names = names_ymm;
12913   else
12914     names = names_xmm;
12915   oappend (names[reg]);
12916 }
12917
12918 static void
12919 OP_EM (int bytemode, int sizeflag)
12920 {
12921   int reg;
12922   const char **names;
12923
12924   if (modrm.mod != 3)
12925     {
12926       if (intel_syntax
12927           && (bytemode == v_mode || bytemode == v_swap_mode))
12928         {
12929           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12930           used_prefixes |= (prefixes & PREFIX_DATA);
12931         }
12932       OP_E (bytemode, sizeflag);
12933       return;
12934     }
12935
12936   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12937     swap_operand ();
12938
12939   /* Skip mod/rm byte.  */
12940   MODRM_CHECK;
12941   codep++;
12942   used_prefixes |= (prefixes & PREFIX_DATA);
12943   reg = modrm.rm;
12944   if (prefixes & PREFIX_DATA)
12945     {
12946       names = names_xmm;
12947       USED_REX (REX_B);
12948       if (rex & REX_B)
12949         reg += 8;
12950     }
12951   else
12952     names = names_mm;
12953   oappend (names[reg]);
12954 }
12955
12956 /* cvt* are the only instructions in sse2 which have
12957    both SSE and MMX operands and also have 0x66 prefix
12958    in their opcode. 0x66 was originally used to differentiate
12959    between SSE and MMX instruction(operands). So we have to handle the
12960    cvt* separately using OP_EMC and OP_MXC */
12961 static void
12962 OP_EMC (int bytemode, int sizeflag)
12963 {
12964   if (modrm.mod != 3)
12965     {
12966       if (intel_syntax && bytemode == v_mode)
12967         {
12968           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12969           used_prefixes |= (prefixes & PREFIX_DATA);
12970         }
12971       OP_E (bytemode, sizeflag);
12972       return;
12973     }
12974
12975   /* Skip mod/rm byte.  */
12976   MODRM_CHECK;
12977   codep++;
12978   used_prefixes |= (prefixes & PREFIX_DATA);
12979   oappend (names_mm[modrm.rm]);
12980 }
12981
12982 static void
12983 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12984 {
12985   used_prefixes |= (prefixes & PREFIX_DATA);
12986   oappend (names_mm[modrm.reg]);
12987 }
12988
12989 static void
12990 OP_EX (int bytemode, int sizeflag)
12991 {
12992   int reg;
12993   const char **names;
12994
12995   /* Skip mod/rm byte.  */
12996   MODRM_CHECK;
12997   codep++;
12998
12999   if (modrm.mod != 3)
13000     {
13001       OP_E_memory (bytemode, sizeflag);
13002       return;
13003     }
13004
13005   reg = modrm.rm;
13006   USED_REX (REX_B);
13007   if (rex & REX_B)
13008     reg += 8;
13009   if (vex.evex)
13010     {
13011       USED_REX (REX_X);
13012       if ((rex & REX_X))
13013         reg += 16;
13014     }
13015
13016   if ((sizeflag & SUFFIX_ALWAYS)
13017       && (bytemode == x_swap_mode
13018           || bytemode == d_swap_mode
13019           || bytemode == q_swap_mode))
13020     swap_operand ();
13021
13022   if (need_vex
13023       && bytemode != xmm_mode
13024       && bytemode != xmmdw_mode
13025       && bytemode != xmmqd_mode
13026       && bytemode != xmm_mb_mode
13027       && bytemode != xmm_mw_mode
13028       && bytemode != xmm_md_mode
13029       && bytemode != xmm_mq_mode
13030       && bytemode != xmmq_mode
13031       && bytemode != evex_half_bcst_xmmq_mode
13032       && bytemode != ymm_mode
13033       && bytemode != tmm_mode
13034       && bytemode != vex_scalar_w_dq_mode)
13035     {
13036       switch (vex.length)
13037         {
13038         case 128:
13039           names = names_xmm;
13040           break;
13041         case 256:
13042           names = names_ymm;
13043           break;
13044         case 512:
13045           names = names_zmm;
13046           break;
13047         default:
13048           abort ();
13049         }
13050     }
13051   else if (bytemode == xmmq_mode
13052            || bytemode == evex_half_bcst_xmmq_mode)
13053     {
13054       switch (vex.length)
13055         {
13056         case 128:
13057         case 256:
13058           names = names_xmm;
13059           break;
13060         case 512:
13061           names = names_ymm;
13062           break;
13063         default:
13064           abort ();
13065         }
13066     }
13067   else if (bytemode == tmm_mode)
13068     {
13069       modrm.rm = reg;
13070       if (reg >= 8)
13071         {
13072           oappend ("(bad)");
13073           return;
13074         }
13075       names = names_tmm;
13076     }
13077   else if (bytemode == ymm_mode)
13078     names = names_ymm;
13079   else
13080     names = names_xmm;
13081   oappend (names[reg]);
13082 }
13083
13084 static void
13085 OP_MS (int bytemode, int sizeflag)
13086 {
13087   if (modrm.mod == 3)
13088     OP_EM (bytemode, sizeflag);
13089   else
13090     BadOp ();
13091 }
13092
13093 static void
13094 OP_XS (int bytemode, int sizeflag)
13095 {
13096   if (modrm.mod == 3)
13097     OP_EX (bytemode, sizeflag);
13098   else
13099     BadOp ();
13100 }
13101
13102 static void
13103 OP_M (int bytemode, int sizeflag)
13104 {
13105   if (modrm.mod == 3)
13106     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13107     BadOp ();
13108   else
13109     OP_E (bytemode, sizeflag);
13110 }
13111
13112 static void
13113 OP_0f07 (int bytemode, int sizeflag)
13114 {
13115   if (modrm.mod != 3 || modrm.rm != 0)
13116     BadOp ();
13117   else
13118     OP_E (bytemode, sizeflag);
13119 }
13120
13121 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13122    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13123
13124 static void
13125 NOP_Fixup1 (int bytemode, int sizeflag)
13126 {
13127   if ((prefixes & PREFIX_DATA) != 0
13128       || (rex != 0
13129           && rex != 0x48
13130           && address_mode == mode_64bit))
13131     OP_REG (bytemode, sizeflag);
13132   else
13133     strcpy (obuf, "nop");
13134 }
13135
13136 static void
13137 NOP_Fixup2 (int bytemode, int sizeflag)
13138 {
13139   if ((prefixes & PREFIX_DATA) != 0
13140       || (rex != 0
13141           && rex != 0x48
13142           && address_mode == mode_64bit))
13143     OP_IMREG (bytemode, sizeflag);
13144 }
13145
13146 static const char *const Suffix3DNow[] = {
13147 /* 00 */        NULL,           NULL,           NULL,           NULL,
13148 /* 04 */        NULL,           NULL,           NULL,           NULL,
13149 /* 08 */        NULL,           NULL,           NULL,           NULL,
13150 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13151 /* 10 */        NULL,           NULL,           NULL,           NULL,
13152 /* 14 */        NULL,           NULL,           NULL,           NULL,
13153 /* 18 */        NULL,           NULL,           NULL,           NULL,
13154 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13155 /* 20 */        NULL,           NULL,           NULL,           NULL,
13156 /* 24 */        NULL,           NULL,           NULL,           NULL,
13157 /* 28 */        NULL,           NULL,           NULL,           NULL,
13158 /* 2C */        NULL,           NULL,           NULL,           NULL,
13159 /* 30 */        NULL,           NULL,           NULL,           NULL,
13160 /* 34 */        NULL,           NULL,           NULL,           NULL,
13161 /* 38 */        NULL,           NULL,           NULL,           NULL,
13162 /* 3C */        NULL,           NULL,           NULL,           NULL,
13163 /* 40 */        NULL,           NULL,           NULL,           NULL,
13164 /* 44 */        NULL,           NULL,           NULL,           NULL,
13165 /* 48 */        NULL,           NULL,           NULL,           NULL,
13166 /* 4C */        NULL,           NULL,           NULL,           NULL,
13167 /* 50 */        NULL,           NULL,           NULL,           NULL,
13168 /* 54 */        NULL,           NULL,           NULL,           NULL,
13169 /* 58 */        NULL,           NULL,           NULL,           NULL,
13170 /* 5C */        NULL,           NULL,           NULL,           NULL,
13171 /* 60 */        NULL,           NULL,           NULL,           NULL,
13172 /* 64 */        NULL,           NULL,           NULL,           NULL,
13173 /* 68 */        NULL,           NULL,           NULL,           NULL,
13174 /* 6C */        NULL,           NULL,           NULL,           NULL,
13175 /* 70 */        NULL,           NULL,           NULL,           NULL,
13176 /* 74 */        NULL,           NULL,           NULL,           NULL,
13177 /* 78 */        NULL,           NULL,           NULL,           NULL,
13178 /* 7C */        NULL,           NULL,           NULL,           NULL,
13179 /* 80 */        NULL,           NULL,           NULL,           NULL,
13180 /* 84 */        NULL,           NULL,           NULL,           NULL,
13181 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13182 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13183 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13184 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13185 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13186 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13187 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13188 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13189 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13190 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13191 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13192 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13193 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13194 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13195 /* C0 */        NULL,           NULL,           NULL,           NULL,
13196 /* C4 */        NULL,           NULL,           NULL,           NULL,
13197 /* C8 */        NULL,           NULL,           NULL,           NULL,
13198 /* CC */        NULL,           NULL,           NULL,           NULL,
13199 /* D0 */        NULL,           NULL,           NULL,           NULL,
13200 /* D4 */        NULL,           NULL,           NULL,           NULL,
13201 /* D8 */        NULL,           NULL,           NULL,           NULL,
13202 /* DC */        NULL,           NULL,           NULL,           NULL,
13203 /* E0 */        NULL,           NULL,           NULL,           NULL,
13204 /* E4 */        NULL,           NULL,           NULL,           NULL,
13205 /* E8 */        NULL,           NULL,           NULL,           NULL,
13206 /* EC */        NULL,           NULL,           NULL,           NULL,
13207 /* F0 */        NULL,           NULL,           NULL,           NULL,
13208 /* F4 */        NULL,           NULL,           NULL,           NULL,
13209 /* F8 */        NULL,           NULL,           NULL,           NULL,
13210 /* FC */        NULL,           NULL,           NULL,           NULL,
13211 };
13212
13213 static void
13214 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13215 {
13216   const char *mnemonic;
13217
13218   FETCH_DATA (the_info, codep + 1);
13219   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13220      place where an 8-bit immediate would normally go.  ie. the last
13221      byte of the instruction.  */
13222   obufp = mnemonicendp;
13223   mnemonic = Suffix3DNow[*codep++ & 0xff];
13224   if (mnemonic)
13225     oappend (mnemonic);
13226   else
13227     {
13228       /* Since a variable sized modrm/sib chunk is between the start
13229          of the opcode (0x0f0f) and the opcode suffix, we need to do
13230          all the modrm processing first, and don't know until now that
13231          we have a bad opcode.  This necessitates some cleaning up.  */
13232       op_out[0][0] = '\0';
13233       op_out[1][0] = '\0';
13234       BadOp ();
13235     }
13236   mnemonicendp = obufp;
13237 }
13238
13239 static const struct op simd_cmp_op[] =
13240 {
13241   { STRING_COMMA_LEN ("eq") },
13242   { STRING_COMMA_LEN ("lt") },
13243   { STRING_COMMA_LEN ("le") },
13244   { STRING_COMMA_LEN ("unord") },
13245   { STRING_COMMA_LEN ("neq") },
13246   { STRING_COMMA_LEN ("nlt") },
13247   { STRING_COMMA_LEN ("nle") },
13248   { STRING_COMMA_LEN ("ord") }
13249 };
13250
13251 static const struct op vex_cmp_op[] =
13252 {
13253   { STRING_COMMA_LEN ("eq_uq") },
13254   { STRING_COMMA_LEN ("nge") },
13255   { STRING_COMMA_LEN ("ngt") },
13256   { STRING_COMMA_LEN ("false") },
13257   { STRING_COMMA_LEN ("neq_oq") },
13258   { STRING_COMMA_LEN ("ge") },
13259   { STRING_COMMA_LEN ("gt") },
13260   { STRING_COMMA_LEN ("true") },
13261   { STRING_COMMA_LEN ("eq_os") },
13262   { STRING_COMMA_LEN ("lt_oq") },
13263   { STRING_COMMA_LEN ("le_oq") },
13264   { STRING_COMMA_LEN ("unord_s") },
13265   { STRING_COMMA_LEN ("neq_us") },
13266   { STRING_COMMA_LEN ("nlt_uq") },
13267   { STRING_COMMA_LEN ("nle_uq") },
13268   { STRING_COMMA_LEN ("ord_s") },
13269   { STRING_COMMA_LEN ("eq_us") },
13270   { STRING_COMMA_LEN ("nge_uq") },
13271   { STRING_COMMA_LEN ("ngt_uq") },
13272   { STRING_COMMA_LEN ("false_os") },
13273   { STRING_COMMA_LEN ("neq_os") },
13274   { STRING_COMMA_LEN ("ge_oq") },
13275   { STRING_COMMA_LEN ("gt_oq") },
13276   { STRING_COMMA_LEN ("true_us") },
13277 };
13278
13279 static void
13280 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13281 {
13282   unsigned int cmp_type;
13283
13284   FETCH_DATA (the_info, codep + 1);
13285   cmp_type = *codep++ & 0xff;
13286   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13287     {
13288       char suffix [3];
13289       char *p = mnemonicendp - 2;
13290       suffix[0] = p[0];
13291       suffix[1] = p[1];
13292       suffix[2] = '\0';
13293       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13294       mnemonicendp += simd_cmp_op[cmp_type].len;
13295     }
13296   else if (need_vex
13297            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13298     {
13299       char suffix [3];
13300       char *p = mnemonicendp - 2;
13301       suffix[0] = p[0];
13302       suffix[1] = p[1];
13303       suffix[2] = '\0';
13304       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13305       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13306       mnemonicendp += vex_cmp_op[cmp_type].len;
13307     }
13308   else
13309     {
13310       /* We have a reserved extension byte.  Output it directly.  */
13311       scratchbuf[0] = '$';
13312       print_operand_value (scratchbuf + 1, 1, cmp_type);
13313       oappend_maybe_intel (scratchbuf);
13314       scratchbuf[0] = '\0';
13315     }
13316 }
13317
13318 static void
13319 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13320 {
13321   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13322   if (!intel_syntax)
13323     {
13324       strcpy (op_out[0], names32[0]);
13325       strcpy (op_out[1], names32[1]);
13326       if (bytemode == eBX_reg)
13327         strcpy (op_out[2], names32[3]);
13328       two_source_ops = 1;
13329     }
13330   /* Skip mod/rm byte.  */
13331   MODRM_CHECK;
13332   codep++;
13333 }
13334
13335 static void
13336 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13337             int sizeflag ATTRIBUTE_UNUSED)
13338 {
13339   /* monitor %{e,r,}ax,%ecx,%edx"  */
13340   if (!intel_syntax)
13341     {
13342       const char **names = (address_mode == mode_64bit
13343                             ? names64 : names32);
13344
13345       if (prefixes & PREFIX_ADDR)
13346         {
13347           /* Remove "addr16/addr32".  */
13348           all_prefixes[last_addr_prefix] = 0;
13349           names = (address_mode != mode_32bit
13350                    ? names32 : names16);
13351           used_prefixes |= PREFIX_ADDR;
13352         }
13353       else if (address_mode == mode_16bit)
13354         names = names16;
13355       strcpy (op_out[0], names[0]);
13356       strcpy (op_out[1], names32[1]);
13357       strcpy (op_out[2], names32[2]);
13358       two_source_ops = 1;
13359     }
13360   /* Skip mod/rm byte.  */
13361   MODRM_CHECK;
13362   codep++;
13363 }
13364
13365 static void
13366 BadOp (void)
13367 {
13368   /* Throw away prefixes and 1st. opcode byte.  */
13369   codep = insn_codep + 1;
13370   oappend ("(bad)");
13371 }
13372
13373 static void
13374 REP_Fixup (int bytemode, int sizeflag)
13375 {
13376   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13377      lods and stos.  */
13378   if (prefixes & PREFIX_REPZ)
13379     all_prefixes[last_repz_prefix] = REP_PREFIX;
13380
13381   switch (bytemode)
13382     {
13383     case al_reg:
13384     case eAX_reg:
13385     case indir_dx_reg:
13386       OP_IMREG (bytemode, sizeflag);
13387       break;
13388     case eDI_reg:
13389       OP_ESreg (bytemode, sizeflag);
13390       break;
13391     case eSI_reg:
13392       OP_DSreg (bytemode, sizeflag);
13393       break;
13394     default:
13395       abort ();
13396       break;
13397     }
13398 }
13399
13400 static void
13401 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13402 {
13403   if ( isa64 != amd64 )
13404     return;
13405
13406   obufp = obuf;
13407   BadOp ();
13408   mnemonicendp = obufp;
13409   ++codep;
13410 }
13411
13412 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13413    "bnd".  */
13414
13415 static void
13416 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13417 {
13418   if (prefixes & PREFIX_REPNZ)
13419     all_prefixes[last_repnz_prefix] = BND_PREFIX;
13420 }
13421
13422 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13423    "notrack".  */
13424
13425 static void
13426 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13427                int sizeflag ATTRIBUTE_UNUSED)
13428 {
13429   if (active_seg_prefix == PREFIX_DS
13430       && (address_mode != mode_64bit || last_data_prefix < 0))
13431     {
13432       /* NOTRACK prefix is only valid on indirect branch instructions.
13433          NB: DATA prefix is unsupported for Intel64.  */
13434       active_seg_prefix = 0;
13435       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13436     }
13437 }
13438
13439 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13440    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13441  */
13442
13443 static void
13444 HLE_Fixup1 (int bytemode, int sizeflag)
13445 {
13446   if (modrm.mod != 3
13447       && (prefixes & PREFIX_LOCK) != 0)
13448     {
13449       if (prefixes & PREFIX_REPZ)
13450         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13451       if (prefixes & PREFIX_REPNZ)
13452         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13453     }
13454
13455   OP_E (bytemode, sizeflag);
13456 }
13457
13458 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13459    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13460  */
13461
13462 static void
13463 HLE_Fixup2 (int bytemode, int sizeflag)
13464 {
13465   if (modrm.mod != 3)
13466     {
13467       if (prefixes & PREFIX_REPZ)
13468         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13469       if (prefixes & PREFIX_REPNZ)
13470         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13471     }
13472
13473   OP_E (bytemode, sizeflag);
13474 }
13475
13476 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13477    "xrelease" for memory operand.  No check for LOCK prefix.   */
13478
13479 static void
13480 HLE_Fixup3 (int bytemode, int sizeflag)
13481 {
13482   if (modrm.mod != 3
13483       && last_repz_prefix > last_repnz_prefix
13484       && (prefixes & PREFIX_REPZ) != 0)
13485     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13486
13487   OP_E (bytemode, sizeflag);
13488 }
13489
13490 static void
13491 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13492 {
13493   USED_REX (REX_W);
13494   if (rex & REX_W)
13495     {
13496       /* Change cmpxchg8b to cmpxchg16b.  */
13497       char *p = mnemonicendp - 2;
13498       mnemonicendp = stpcpy (p, "16b");
13499       bytemode = o_mode;
13500     }
13501   else if ((prefixes & PREFIX_LOCK) != 0)
13502     {
13503       if (prefixes & PREFIX_REPZ)
13504         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13505       if (prefixes & PREFIX_REPNZ)
13506         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13507     }
13508
13509   OP_M (bytemode, sizeflag);
13510 }
13511
13512 static void
13513 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13514 {
13515   const char **names;
13516
13517   if (need_vex)
13518     {
13519       switch (vex.length)
13520         {
13521         case 128:
13522           names = names_xmm;
13523           break;
13524         case 256:
13525           names = names_ymm;
13526           break;
13527         default:
13528           abort ();
13529         }
13530     }
13531   else
13532     names = names_xmm;
13533   oappend (names[reg]);
13534 }
13535
13536 static void
13537 FXSAVE_Fixup (int bytemode, int sizeflag)
13538 {
13539   /* Add proper suffix to "fxsave" and "fxrstor".  */
13540   USED_REX (REX_W);
13541   if (rex & REX_W)
13542     {
13543       char *p = mnemonicendp;
13544       *p++ = '6';
13545       *p++ = '4';
13546       *p = '\0';
13547       mnemonicendp = p;
13548     }
13549   OP_M (bytemode, sizeflag);
13550 }
13551
13552 /* Display the destination register operand for instructions with
13553    VEX. */
13554
13555 static void
13556 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13557 {
13558   int reg;
13559   const char **names;
13560
13561   if (!need_vex)
13562     abort ();
13563
13564   reg = vex.register_specifier;
13565   vex.register_specifier = 0;
13566   if (address_mode != mode_64bit)
13567     reg &= 7;
13568   else if (vex.evex && !vex.v)
13569     reg += 16;
13570
13571   if (bytemode == vex_scalar_mode)
13572     {
13573       oappend (names_xmm[reg]);
13574       return;
13575     }
13576
13577   if (bytemode == tmm_mode)
13578     {
13579       /* All 3 TMM registers must be distinct.  */
13580       if (reg >= 8)
13581         oappend ("(bad)");
13582       else
13583         {
13584           /* This must be the 3rd operand.  */
13585           if (obufp != op_out[2])
13586             abort ();
13587           oappend (names_tmm[reg]);
13588           if (reg == modrm.reg || reg == modrm.rm)
13589             strcpy (obufp, "/(bad)");
13590         }
13591
13592       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13593         {
13594           if (modrm.reg <= 8
13595               && (modrm.reg == modrm.rm || modrm.reg == reg))
13596             strcat (op_out[0], "/(bad)");
13597           if (modrm.rm <= 8
13598               && (modrm.rm == modrm.reg || modrm.rm == reg))
13599             strcat (op_out[1], "/(bad)");
13600         }
13601
13602       return;
13603     }
13604
13605   switch (vex.length)
13606     {
13607     case 128:
13608       switch (bytemode)
13609         {
13610         case vex_mode:
13611         case vex_vsib_q_w_dq_mode:
13612         case vex_vsib_q_w_d_mode:
13613           names = names_xmm;
13614           break;
13615         case dq_mode:
13616           if (rex & REX_W)
13617             names = names64;
13618           else
13619             names = names32;
13620           break;
13621         case mask_bd_mode:
13622         case mask_mode:
13623           if (reg > 0x7)
13624             {
13625               oappend ("(bad)");
13626               return;
13627             }
13628           names = names_mask;
13629           break;
13630         default:
13631           abort ();
13632           return;
13633         }
13634       break;
13635     case 256:
13636       switch (bytemode)
13637         {
13638         case vex_mode:
13639           names = names_ymm;
13640           break;
13641         case vex_vsib_q_w_dq_mode:
13642         case vex_vsib_q_w_d_mode:
13643           names = vex.w ? names_ymm : names_xmm;
13644           break;
13645         case mask_bd_mode:
13646         case mask_mode:
13647           if (reg > 0x7)
13648             {
13649               oappend ("(bad)");
13650               return;
13651             }
13652           names = names_mask;
13653           break;
13654         default:
13655           /* See PR binutils/20893 for a reproducer.  */
13656           oappend ("(bad)");
13657           return;
13658         }
13659       break;
13660     case 512:
13661       names = names_zmm;
13662       break;
13663     default:
13664       abort ();
13665       break;
13666     }
13667   oappend (names[reg]);
13668 }
13669
13670 static void
13671 OP_VexR (int bytemode, int sizeflag)
13672 {
13673   if (modrm.mod == 3)
13674     OP_VEX (bytemode, sizeflag);
13675 }
13676
13677 static void
13678 OP_VexW (int bytemode, int sizeflag)
13679 {
13680   OP_VEX (bytemode, sizeflag);
13681
13682   if (vex.w)
13683     {
13684       /* Swap 2nd and 3rd operands.  */
13685       strcpy (scratchbuf, op_out[2]);
13686       strcpy (op_out[2], op_out[1]);
13687       strcpy (op_out[1], scratchbuf);
13688     }
13689 }
13690
13691 static void
13692 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13693 {
13694   int reg;
13695   const char **names = names_xmm;
13696
13697   FETCH_DATA (the_info, codep + 1);
13698   reg = *codep++;
13699
13700   if (bytemode != x_mode && bytemode != scalar_mode)
13701     abort ();
13702
13703   reg >>= 4;
13704   if (address_mode != mode_64bit)
13705     reg &= 7;
13706
13707   if (bytemode == x_mode && vex.length == 256)
13708     names = names_ymm;
13709
13710   oappend (names[reg]);
13711
13712   if (vex.w)
13713     {
13714       /* Swap 3rd and 4th operands.  */
13715       strcpy (scratchbuf, op_out[3]);
13716       strcpy (op_out[3], op_out[2]);
13717       strcpy (op_out[2], scratchbuf);
13718     }
13719 }
13720
13721 static void
13722 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13723           int sizeflag ATTRIBUTE_UNUSED)
13724 {
13725   scratchbuf[0] = '$';
13726   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13727   oappend_maybe_intel (scratchbuf);
13728 }
13729
13730 static void
13731 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13732              int sizeflag ATTRIBUTE_UNUSED)
13733 {
13734   unsigned int cmp_type;
13735
13736   if (!vex.evex)
13737     abort ();
13738
13739   FETCH_DATA (the_info, codep + 1);
13740   cmp_type = *codep++ & 0xff;
13741   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13742      If it's the case, print suffix, otherwise - print the immediate.  */
13743   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13744       && cmp_type != 3
13745       && cmp_type != 7)
13746     {
13747       char suffix [3];
13748       char *p = mnemonicendp - 2;
13749
13750       /* vpcmp* can have both one- and two-lettered suffix.  */
13751       if (p[0] == 'p')
13752         {
13753           p++;
13754           suffix[0] = p[0];
13755           suffix[1] = '\0';
13756         }
13757       else
13758         {
13759           suffix[0] = p[0];
13760           suffix[1] = p[1];
13761           suffix[2] = '\0';
13762         }
13763
13764       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13765       mnemonicendp += simd_cmp_op[cmp_type].len;
13766     }
13767   else
13768     {
13769       /* We have a reserved extension byte.  Output it directly.  */
13770       scratchbuf[0] = '$';
13771       print_operand_value (scratchbuf + 1, 1, cmp_type);
13772       oappend_maybe_intel (scratchbuf);
13773       scratchbuf[0] = '\0';
13774     }
13775 }
13776
13777 static const struct op xop_cmp_op[] =
13778 {
13779   { STRING_COMMA_LEN ("lt") },
13780   { STRING_COMMA_LEN ("le") },
13781   { STRING_COMMA_LEN ("gt") },
13782   { STRING_COMMA_LEN ("ge") },
13783   { STRING_COMMA_LEN ("eq") },
13784   { STRING_COMMA_LEN ("neq") },
13785   { STRING_COMMA_LEN ("false") },
13786   { STRING_COMMA_LEN ("true") }
13787 };
13788
13789 static void
13790 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13791              int sizeflag ATTRIBUTE_UNUSED)
13792 {
13793   unsigned int cmp_type;
13794
13795   FETCH_DATA (the_info, codep + 1);
13796   cmp_type = *codep++ & 0xff;
13797   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13798     {
13799       char suffix[3];
13800       char *p = mnemonicendp - 2;
13801
13802       /* vpcom* can have both one- and two-lettered suffix.  */
13803       if (p[0] == 'm')
13804         {
13805           p++;
13806           suffix[0] = p[0];
13807           suffix[1] = '\0';
13808         }
13809       else
13810         {
13811           suffix[0] = p[0];
13812           suffix[1] = p[1];
13813           suffix[2] = '\0';
13814         }
13815
13816       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13817       mnemonicendp += xop_cmp_op[cmp_type].len;
13818     }
13819   else
13820     {
13821       /* We have a reserved extension byte.  Output it directly.  */
13822       scratchbuf[0] = '$';
13823       print_operand_value (scratchbuf + 1, 1, cmp_type);
13824       oappend_maybe_intel (scratchbuf);
13825       scratchbuf[0] = '\0';
13826     }
13827 }
13828
13829 static const struct op pclmul_op[] =
13830 {
13831   { STRING_COMMA_LEN ("lql") },
13832   { STRING_COMMA_LEN ("hql") },
13833   { STRING_COMMA_LEN ("lqh") },
13834   { STRING_COMMA_LEN ("hqh") }
13835 };
13836
13837 static void
13838 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13839               int sizeflag ATTRIBUTE_UNUSED)
13840 {
13841   unsigned int pclmul_type;
13842
13843   FETCH_DATA (the_info, codep + 1);
13844   pclmul_type = *codep++ & 0xff;
13845   switch (pclmul_type)
13846     {
13847     case 0x10:
13848       pclmul_type = 2;
13849       break;
13850     case 0x11:
13851       pclmul_type = 3;
13852       break;
13853     default:
13854       break;
13855     }
13856   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13857     {
13858       char suffix [4];
13859       char *p = mnemonicendp - 3;
13860       suffix[0] = p[0];
13861       suffix[1] = p[1];
13862       suffix[2] = p[2];
13863       suffix[3] = '\0';
13864       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13865       mnemonicendp += pclmul_op[pclmul_type].len;
13866     }
13867   else
13868     {
13869       /* We have a reserved extension byte.  Output it directly.  */
13870       scratchbuf[0] = '$';
13871       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13872       oappend_maybe_intel (scratchbuf);
13873       scratchbuf[0] = '\0';
13874     }
13875 }
13876
13877 static void
13878 MOVSXD_Fixup (int bytemode, int sizeflag)
13879 {
13880   /* Add proper suffix to "movsxd".  */
13881   char *p = mnemonicendp;
13882
13883   switch (bytemode)
13884     {
13885     case movsxd_mode:
13886       if (intel_syntax)
13887         {
13888           *p++ = 'x';
13889           *p++ = 'd';
13890           goto skip;
13891         }
13892
13893       USED_REX (REX_W);
13894       if (rex & REX_W)
13895         {
13896           *p++ = 'l';
13897           *p++ = 'q';
13898         }
13899       else
13900         {
13901           *p++ = 'x';
13902           *p++ = 'd';
13903         }
13904       break;
13905     default:
13906       oappend (INTERNAL_DISASSEMBLER_ERROR);
13907       break;
13908     }
13909
13910  skip:
13911   mnemonicendp = p;
13912   *p = '\0';
13913   OP_E (bytemode, sizeflag);
13914 }
13915
13916 static void
13917 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13918 {
13919   if (!vex.evex
13920       || (bytemode != mask_mode && bytemode != mask_bd_mode))
13921     abort ();
13922
13923   USED_REX (REX_R);
13924   if ((rex & REX_R) != 0 || !vex.r)
13925     {
13926       BadOp ();
13927       return;
13928     }
13929
13930   oappend (names_mask [modrm.reg]);
13931 }
13932
13933 static void
13934 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13935 {
13936   if (modrm.mod == 3 && vex.b)
13937     switch (bytemode)
13938       {
13939       case evex_rounding_64_mode:
13940         if (address_mode != mode_64bit)
13941           {
13942             oappend ("(bad)");
13943             break;
13944           }
13945         /* Fall through.  */
13946       case evex_rounding_mode:
13947         oappend (names_rounding[vex.ll]);
13948         break;
13949       case evex_sae_mode:
13950         oappend ("{sae}");
13951         break;
13952       default:
13953         abort ();
13954         break;
13955       }
13956 }