opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void CMPXCHG8B_Fixup (int, int);
 112 static void XMM_Fixup (int, int);
 113 static void CRC32_Fixup (int, int);
 114 static void FXSAVE_Fixup (int, int);
 115 static void OP_LWPCB_E (int, int);
 116 static void OP_LWP_E (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* REX bits in original REX prefix ignored.  */
 148 static int rex_ignored;
 149 /* Mark parts used in the REX prefix.  When we are testing for
 150    empty prefix (for 8bit register REX extension), just mask it
 151    out.  Otherwise test for REX bit is excuse for existence of REX
 152    only in case value is nonzero.  */
 153 #define USED_REX(value)                                 \
 154   {                                                     \
 155     if (value)                                          \
 156       {                                                 \
 157         if ((rex & value))                              \
 158           rex_used |= (value) | REX_OPCODE;             \
 159       }                                                 \
 160     else                                                \
 161       rex_used |= REX_OPCODE;                           \
 162   }
 163
 164 /* Flags for prefixes which we somehow handled when printing the
 165    current instruction.  */
 166 static int used_prefixes;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       longjmp (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 #define XX { NULL, 0 }
 219 #define Bad_Opcode NULL, { { NULL, 0 } }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 256 #define Iv { OP_I, v_mode }
 257 #define sIv { OP_sI, v_mode }
 258 #define Iq { OP_I, q_mode }
 259 #define Iv64 { OP_I64, v_mode }
 260 #define Iw { OP_I, w_mode }
 261 #define I1 { OP_I, const_1_mode }
 262 #define Jb { OP_J, b_mode }
 263 #define Jv { OP_J, v_mode }
 264 #define Cm { OP_C, m_mode }
 265 #define Dm { OP_D, m_mode }
 266 #define Td { OP_T, d_mode }
 267 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 268
 269 #define RMeAX { OP_REG, eAX_reg }
 270 #define RMeBX { OP_REG, eBX_reg }
 271 #define RMeCX { OP_REG, eCX_reg }
 272 #define RMeDX { OP_REG, eDX_reg }
 273 #define RMeSP { OP_REG, eSP_reg }
 274 #define RMeBP { OP_REG, eBP_reg }
 275 #define RMeSI { OP_REG, eSI_reg }
 276 #define RMeDI { OP_REG, eDI_reg }
 277 #define RMrAX { OP_REG, rAX_reg }
 278 #define RMrBX { OP_REG, rBX_reg }
 279 #define RMrCX { OP_REG, rCX_reg }
 280 #define RMrDX { OP_REG, rDX_reg }
 281 #define RMrSP { OP_REG, rSP_reg }
 282 #define RMrBP { OP_REG, rBP_reg }
 283 #define RMrSI { OP_REG, rSI_reg }
 284 #define RMrDI { OP_REG, rDI_reg }
 285 #define RMAL { OP_REG, al_reg }
 286 #define RMCL { OP_REG, cl_reg }
 287 #define RMDL { OP_REG, dl_reg }
 288 #define RMBL { OP_REG, bl_reg }
 289 #define RMAH { OP_REG, ah_reg }
 290 #define RMCH { OP_REG, ch_reg }
 291 #define RMDH { OP_REG, dh_reg }
 292 #define RMBH { OP_REG, bh_reg }
 293 #define RMAX { OP_REG, ax_reg }
 294 #define RMDX { OP_REG, dx_reg }
 295
 296 #define eAX { OP_IMREG, eAX_reg }
 297 #define eBX { OP_IMREG, eBX_reg }
 298 #define eCX { OP_IMREG, eCX_reg }
 299 #define eDX { OP_IMREG, eDX_reg }
 300 #define eSP { OP_IMREG, eSP_reg }
 301 #define eBP { OP_IMREG, eBP_reg }
 302 #define eSI { OP_IMREG, eSI_reg }
 303 #define eDI { OP_IMREG, eDI_reg }
 304 #define AL { OP_IMREG, al_reg }
 305 #define CL { OP_IMREG, cl_reg }
 306 #define DL { OP_IMREG, dl_reg }
 307 #define BL { OP_IMREG, bl_reg }
 308 #define AH { OP_IMREG, ah_reg }
 309 #define CH { OP_IMREG, ch_reg }
 310 #define DH { OP_IMREG, dh_reg }
 311 #define BH { OP_IMREG, bh_reg }
 312 #define AX { OP_IMREG, ax_reg }
 313 #define DX { OP_IMREG, dx_reg }
 314 #define zAX { OP_IMREG, z_mode_ax_reg }
 315 #define indirDX { OP_IMREG, indir_dx_reg }
 316
 317 #define Sw { OP_SEG, w_mode }
 318 #define Sv { OP_SEG, v_mode }
 319 #define Ap { OP_DIR, 0 }
 320 #define Ob { OP_OFF64, b_mode }
 321 #define Ov { OP_OFF64, v_mode }
 322 #define Xb { OP_DSreg, eSI_reg }
 323 #define Xv { OP_DSreg, eSI_reg }
 324 #define Xz { OP_DSreg, eSI_reg }
 325 #define Yb { OP_ESreg, eDI_reg }
 326 #define Yv { OP_ESreg, eDI_reg }
 327 #define DSBX { OP_DSreg, eBX_reg }
 328
 329 #define es { OP_REG, es_reg }
 330 #define ss { OP_REG, ss_reg }
 331 #define cs { OP_REG, cs_reg }
 332 #define ds { OP_REG, ds_reg }
 333 #define fs { OP_REG, fs_reg }
 334 #define gs { OP_REG, gs_reg }
 335
 336 #define MX { OP_MMX, 0 }
 337 #define XM { OP_XMM, 0 }
 338 #define XMScalar { OP_XMM, scalar_mode }
 339 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 340 #define XMM { OP_XMM, xmm_mode }
 341 #define EM { OP_EM, v_mode }
 342 #define EMS { OP_EM, v_swap_mode }
 343 #define EMd { OP_EM, d_mode }
 344 #define EMx { OP_EM, x_mode }
 345 #define EXw { OP_EX, w_mode }
 346 #define EXd { OP_EX, d_mode }
 347 #define EXdScalar { OP_EX, d_scalar_mode }
 348 #define EXdS { OP_EX, d_swap_mode }
 349 #define EXq { OP_EX, q_mode }
 350 #define EXqScalar { OP_EX, q_scalar_mode }
 351 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 352 #define EXqS { OP_EX, q_swap_mode }
 353 #define EXx { OP_EX, x_mode }
 354 #define EXxS { OP_EX, x_swap_mode }
 355 #define EXxmm { OP_EX, xmm_mode }
 356 #define EXxmmq { OP_EX, xmmq_mode }
 357 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 358 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 359 #define EXxmm_md { OP_EX, xmm_md_mode }
 360 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 361 #define EXxmmdw { OP_EX, xmmdw_mode }
 362 #define EXxmmqd { OP_EX, xmmqd_mode }
 363 #define EXymmq { OP_EX, ymmq_mode }
 364 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 365 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 366 #define MS { OP_MS, v_mode }
 367 #define XS { OP_XS, v_mode }
 368 #define EMCq { OP_EMC, q_mode }
 369 #define MXC { OP_MXC, 0 }
 370 #define OPSUF { OP_3DNowSuffix, 0 }
 371 #define CMP { CMP_Fixup, 0 }
 372 #define XMM0 { XMM_Fixup, 0 }
 373 #define FXSAVE { FXSAVE_Fixup, 0 }
 374 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 375 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 376
 377 #define Vex { OP_VEX, vex_mode }
 378 #define VexScalar { OP_VEX, vex_scalar_mode }
 379 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 380 #define Vex128 { OP_VEX, vex128_mode }
 381 #define Vex256 { OP_VEX, vex256_mode }
 382 #define VexGdq { OP_VEX, dq_mode }
 383 #define VexI4 { VEXI4_Fixup, 0}
 384 #define EXdVex { OP_EX_Vex, d_mode }
 385 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 386 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 387 #define EXqVex { OP_EX_Vex, q_mode }
 388 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 389 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 390 #define EXVexW { OP_EX_VexW, x_mode }
 391 #define EXdVexW { OP_EX_VexW, d_mode }
 392 #define EXqVexW { OP_EX_VexW, q_mode }
 393 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 394 #define XMVex { OP_XMM_Vex, 0 }
 395 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 396 #define XMVexW { OP_XMM_VexW, 0 }
 397 #define XMVexI4 { OP_REG_VexI4, x_mode }
 398 #define PCLMUL { PCLMUL_Fixup, 0 }
 399 #define VZERO { VZERO_Fixup, 0 }
 400 #define VCMP { VCMP_Fixup, 0 }
 401
 402 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 403 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 404
 405 /* Used handle "rep" prefix for string instructions.  */
 406 #define Xbr { REP_Fixup, eSI_reg }
 407 #define Xvr { REP_Fixup, eSI_reg }
 408 #define Ybr { REP_Fixup, eDI_reg }
 409 #define Yvr { REP_Fixup, eDI_reg }
 410 #define Yzr { REP_Fixup, eDI_reg }
 411 #define indirDXr { REP_Fixup, indir_dx_reg }
 412 #define ALr { REP_Fixup, al_reg }
 413 #define eAXr { REP_Fixup, eAX_reg }
 414
 415 #define cond_jump_flag { NULL, cond_jump_mode }
 416 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 417
 418 /* bits in sizeflag */
 419 #define SUFFIX_ALWAYS 4
 420 #define AFLAG 2
 421 #define DFLAG 1
 422
 423 enum
 424 {
 425   /* byte operand */
 426   b_mode = 1,
 427   /* byte operand with operand swapped */
 428   b_swap_mode,
 429   /* byte operand, sign extend like 'T' suffix */
 430   b_T_mode,
 431   /* operand size depends on prefixes */
 432   v_mode,
 433   /* operand size depends on prefixes with operand swapped */
 434   v_swap_mode,
 435   /* word operand */
 436   w_mode,
 437   /* double word operand  */
 438   d_mode,
 439   /* double word operand with operand swapped */
 440   d_swap_mode,
 441   /* quad word operand */
 442   q_mode,
 443   /* quad word operand with operand swapped */
 444   q_swap_mode,
 445   /* ten-byte operand */
 446   t_mode,
 447   /* 16-byte XMM or 32-byte YMM operand */
 448   x_mode,
 449   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 450   x_swap_mode,
 451   /* 16-byte XMM operand */
 452   xmm_mode,
 453   /* 16-byte XMM or quad word operand */
 454   xmmq_mode,
 455   /* XMM register or byte memory operand */
 456   xmm_mb_mode,
 457   /* XMM register or word memory operand */
 458   xmm_mw_mode,
 459   /* XMM register or double word memory operand */
 460   xmm_md_mode,
 461   /* XMM register or quad word memory operand */
 462   xmm_mq_mode,
 463   /* 16-byte XMM, word or double word operand  */
 464   xmmdw_mode,
 465   /* 16-byte XMM, double word or quad word operand */
 466   xmmqd_mode,
 467   /* 32-byte YMM or quad word operand */
 468   ymmq_mode,
 469   /* 32-byte YMM or 16-byte word operand */
 470   ymmxmm_mode,
 471   /* d_mode in 32bit, q_mode in 64bit mode.  */
 472   m_mode,
 473   /* pair of v_mode operands */
 474   a_mode,
 475   cond_jump_mode,
 476   loop_jcxz_mode,
 477   /* operand size depends on REX prefixes.  */
 478   dq_mode,
 479   /* registers like dq_mode, memory like w_mode.  */
 480   dqw_mode,
 481   /* 4- or 6-byte pointer operand */
 482   f_mode,
 483   const_1_mode,
 484   /* v_mode for stack-related opcodes.  */
 485   stack_v_mode,
 486   /* non-quad operand size depends on prefixes */
 487   z_mode,
 488   /* 16-byte operand */
 489   o_mode,
 490   /* registers like dq_mode, memory like b_mode.  */
 491   dqb_mode,
 492   /* registers like dq_mode, memory like d_mode.  */
 493   dqd_mode,
 494   /* normal vex mode */
 495   vex_mode,
 496   /* 128bit vex mode */
 497   vex128_mode,
 498   /* 256bit vex mode */
 499   vex256_mode,
 500   /* operand size depends on the VEX.W bit.  */
 501   vex_w_dq_mode,
 502
 503   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 504   vex_vsib_d_w_dq_mode,
 505   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 506   vex_vsib_q_w_dq_mode,
 507
 508   /* scalar, ignore vector length.  */
 509   scalar_mode,
 510   /* like d_mode, ignore vector length.  */
 511   d_scalar_mode,
 512   /* like d_swap_mode, ignore vector length.  */
 513   d_scalar_swap_mode,
 514   /* like q_mode, ignore vector length.  */
 515   q_scalar_mode,
 516   /* like q_swap_mode, ignore vector length.  */
 517   q_scalar_swap_mode,
 518   /* like vex_mode, ignore vector length.  */
 519   vex_scalar_mode,
 520   /* like vex_w_dq_mode, ignore vector length.  */
 521   vex_scalar_w_dq_mode,
 522
 523   es_reg,
 524   cs_reg,
 525   ss_reg,
 526   ds_reg,
 527   fs_reg,
 528   gs_reg,
 529
 530   eAX_reg,
 531   eCX_reg,
 532   eDX_reg,
 533   eBX_reg,
 534   eSP_reg,
 535   eBP_reg,
 536   eSI_reg,
 537   eDI_reg,
 538
 539   al_reg,
 540   cl_reg,
 541   dl_reg,
 542   bl_reg,
 543   ah_reg,
 544   ch_reg,
 545   dh_reg,
 546   bh_reg,
 547
 548   ax_reg,
 549   cx_reg,
 550   dx_reg,
 551   bx_reg,
 552   sp_reg,
 553   bp_reg,
 554   si_reg,
 555   di_reg,
 556
 557   rAX_reg,
 558   rCX_reg,
 559   rDX_reg,
 560   rBX_reg,
 561   rSP_reg,
 562   rBP_reg,
 563   rSI_reg,
 564   rDI_reg,
 565
 566   z_mode_ax_reg,
 567   indir_dx_reg
 568 };
 569
 570 enum
 571 {
 572   FLOATCODE = 1,
 573   USE_REG_TABLE,
 574   USE_MOD_TABLE,
 575   USE_RM_TABLE,
 576   USE_PREFIX_TABLE,
 577   USE_X86_64_TABLE,
 578   USE_3BYTE_TABLE,
 579   USE_XOP_8F_TABLE,
 580   USE_VEX_C4_TABLE,
 581   USE_VEX_C5_TABLE,
 582   USE_VEX_LEN_TABLE,
 583   USE_VEX_W_TABLE
 584 };
 585
 586 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 587
 588 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 589 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 590 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 591 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 592 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 593 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 594 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 595 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 596 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 597 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 598 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 599 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 600
 601 enum
 602 {
 603   REG_80 = 0,
 604   REG_81,
 605   REG_82,
 606   REG_8F,
 607   REG_C0,
 608   REG_C1,
 609   REG_C6,
 610   REG_C7,
 611   REG_D0,
 612   REG_D1,
 613   REG_D2,
 614   REG_D3,
 615   REG_F6,
 616   REG_F7,
 617   REG_FE,
 618   REG_FF,
 619   REG_0F00,
 620   REG_0F01,
 621   REG_0F0D,
 622   REG_0F18,
 623   REG_0F71,
 624   REG_0F72,
 625   REG_0F73,
 626   REG_0FA6,
 627   REG_0FA7,
 628   REG_0FAE,
 629   REG_0FBA,
 630   REG_0FC7,
 631   REG_VEX_0F71,
 632   REG_VEX_0F72,
 633   REG_VEX_0F73,
 634   REG_VEX_0FAE,
 635   REG_VEX_0F38F3,
 636   REG_XOP_LWPCB,
 637   REG_XOP_LWP,
 638   REG_XOP_TBM_01,
 639   REG_XOP_TBM_02
 640 };
 641
 642 enum
 643 {
 644   MOD_8D = 0,
 645   MOD_0F01_REG_0,
 646   MOD_0F01_REG_1,
 647   MOD_0F01_REG_2,
 648   MOD_0F01_REG_3,
 649   MOD_0F01_REG_7,
 650   MOD_0F12_PREFIX_0,
 651   MOD_0F13,
 652   MOD_0F16_PREFIX_0,
 653   MOD_0F17,
 654   MOD_0F18_REG_0,
 655   MOD_0F18_REG_1,
 656   MOD_0F18_REG_2,
 657   MOD_0F18_REG_3,
 658   MOD_0F20,
 659   MOD_0F21,
 660   MOD_0F22,
 661   MOD_0F23,
 662   MOD_0F24,
 663   MOD_0F26,
 664   MOD_0F2B_PREFIX_0,
 665   MOD_0F2B_PREFIX_1,
 666   MOD_0F2B_PREFIX_2,
 667   MOD_0F2B_PREFIX_3,
 668   MOD_0F51,
 669   MOD_0F71_REG_2,
 670   MOD_0F71_REG_4,
 671   MOD_0F71_REG_6,
 672   MOD_0F72_REG_2,
 673   MOD_0F72_REG_4,
 674   MOD_0F72_REG_6,
 675   MOD_0F73_REG_2,
 676   MOD_0F73_REG_3,
 677   MOD_0F73_REG_6,
 678   MOD_0F73_REG_7,
 679   MOD_0FAE_REG_0,
 680   MOD_0FAE_REG_1,
 681   MOD_0FAE_REG_2,
 682   MOD_0FAE_REG_3,
 683   MOD_0FAE_REG_4,
 684   MOD_0FAE_REG_5,
 685   MOD_0FAE_REG_6,
 686   MOD_0FAE_REG_7,
 687   MOD_0FB2,
 688   MOD_0FB4,
 689   MOD_0FB5,
 690   MOD_0FC7_REG_6,
 691   MOD_0FC7_REG_7,
 692   MOD_0FD7,
 693   MOD_0FE7_PREFIX_2,
 694   MOD_0FF0_PREFIX_3,
 695   MOD_0F382A_PREFIX_2,
 696   MOD_62_32BIT,
 697   MOD_C4_32BIT,
 698   MOD_C5_32BIT,
 699   MOD_VEX_0F12_PREFIX_0,
 700   MOD_VEX_0F13,
 701   MOD_VEX_0F16_PREFIX_0,
 702   MOD_VEX_0F17,
 703   MOD_VEX_0F2B,
 704   MOD_VEX_0F50,
 705   MOD_VEX_0F71_REG_2,
 706   MOD_VEX_0F71_REG_4,
 707   MOD_VEX_0F71_REG_6,
 708   MOD_VEX_0F72_REG_2,
 709   MOD_VEX_0F72_REG_4,
 710   MOD_VEX_0F72_REG_6,
 711   MOD_VEX_0F73_REG_2,
 712   MOD_VEX_0F73_REG_3,
 713   MOD_VEX_0F73_REG_6,
 714   MOD_VEX_0F73_REG_7,
 715   MOD_VEX_0FAE_REG_2,
 716   MOD_VEX_0FAE_REG_3,
 717   MOD_VEX_0FD7_PREFIX_2,
 718   MOD_VEX_0FE7_PREFIX_2,
 719   MOD_VEX_0FF0_PREFIX_3,
 720   MOD_VEX_0F381A_PREFIX_2,
 721   MOD_VEX_0F382A_PREFIX_2,
 722   MOD_VEX_0F382C_PREFIX_2,
 723   MOD_VEX_0F382D_PREFIX_2,
 724   MOD_VEX_0F382E_PREFIX_2,
 725   MOD_VEX_0F382F_PREFIX_2,
 726   MOD_VEX_0F385A_PREFIX_2,
 727   MOD_VEX_0F388C_PREFIX_2,
 728   MOD_VEX_0F388E_PREFIX_2,
 729 };
 730
 731 enum
 732 {
 733   RM_0F01_REG_0 = 0,
 734   RM_0F01_REG_1,
 735   RM_0F01_REG_2,
 736   RM_0F01_REG_3,
 737   RM_0F01_REG_7,
 738   RM_0FAE_REG_5,
 739   RM_0FAE_REG_6,
 740   RM_0FAE_REG_7
 741 };
 742
 743 enum
 744 {
 745   PREFIX_90 = 0,
 746   PREFIX_0F10,
 747   PREFIX_0F11,
 748   PREFIX_0F12,
 749   PREFIX_0F16,
 750   PREFIX_0F2A,
 751   PREFIX_0F2B,
 752   PREFIX_0F2C,
 753   PREFIX_0F2D,
 754   PREFIX_0F2E,
 755   PREFIX_0F2F,
 756   PREFIX_0F51,
 757   PREFIX_0F52,
 758   PREFIX_0F53,
 759   PREFIX_0F58,
 760   PREFIX_0F59,
 761   PREFIX_0F5A,
 762   PREFIX_0F5B,
 763   PREFIX_0F5C,
 764   PREFIX_0F5D,
 765   PREFIX_0F5E,
 766   PREFIX_0F5F,
 767   PREFIX_0F60,
 768   PREFIX_0F61,
 769   PREFIX_0F62,
 770   PREFIX_0F6C,
 771   PREFIX_0F6D,
 772   PREFIX_0F6F,
 773   PREFIX_0F70,
 774   PREFIX_0F73_REG_3,
 775   PREFIX_0F73_REG_7,
 776   PREFIX_0F78,
 777   PREFIX_0F79,
 778   PREFIX_0F7C,
 779   PREFIX_0F7D,
 780   PREFIX_0F7E,
 781   PREFIX_0F7F,
 782   PREFIX_0FAE_REG_0,
 783   PREFIX_0FAE_REG_1,
 784   PREFIX_0FAE_REG_2,
 785   PREFIX_0FAE_REG_3,
 786   PREFIX_0FB8,
 787   PREFIX_0FBC,
 788   PREFIX_0FBD,
 789   PREFIX_0FC2,
 790   PREFIX_0FC3,
 791   PREFIX_0FC7_REG_6,
 792   PREFIX_0FD0,
 793   PREFIX_0FD6,
 794   PREFIX_0FE6,
 795   PREFIX_0FE7,
 796   PREFIX_0FF0,
 797   PREFIX_0FF7,
 798   PREFIX_0F3810,
 799   PREFIX_0F3814,
 800   PREFIX_0F3815,
 801   PREFIX_0F3817,
 802   PREFIX_0F3820,
 803   PREFIX_0F3821,
 804   PREFIX_0F3822,
 805   PREFIX_0F3823,
 806   PREFIX_0F3824,
 807   PREFIX_0F3825,
 808   PREFIX_0F3828,
 809   PREFIX_0F3829,
 810   PREFIX_0F382A,
 811   PREFIX_0F382B,
 812   PREFIX_0F3830,
 813   PREFIX_0F3831,
 814   PREFIX_0F3832,
 815   PREFIX_0F3833,
 816   PREFIX_0F3834,
 817   PREFIX_0F3835,
 818   PREFIX_0F3837,
 819   PREFIX_0F3838,
 820   PREFIX_0F3839,
 821   PREFIX_0F383A,
 822   PREFIX_0F383B,
 823   PREFIX_0F383C,
 824   PREFIX_0F383D,
 825   PREFIX_0F383E,
 826   PREFIX_0F383F,
 827   PREFIX_0F3840,
 828   PREFIX_0F3841,
 829   PREFIX_0F3880,
 830   PREFIX_0F3881,
 831   PREFIX_0F3882,
 832   PREFIX_0F38DB,
 833   PREFIX_0F38DC,
 834   PREFIX_0F38DD,
 835   PREFIX_0F38DE,
 836   PREFIX_0F38DF,
 837   PREFIX_0F38F0,
 838   PREFIX_0F38F1,
 839   PREFIX_0F3A08,
 840   PREFIX_0F3A09,
 841   PREFIX_0F3A0A,
 842   PREFIX_0F3A0B,
 843   PREFIX_0F3A0C,
 844   PREFIX_0F3A0D,
 845   PREFIX_0F3A0E,
 846   PREFIX_0F3A14,
 847   PREFIX_0F3A15,
 848   PREFIX_0F3A16,
 849   PREFIX_0F3A17,
 850   PREFIX_0F3A20,
 851   PREFIX_0F3A21,
 852   PREFIX_0F3A22,
 853   PREFIX_0F3A40,
 854   PREFIX_0F3A41,
 855   PREFIX_0F3A42,
 856   PREFIX_0F3A44,
 857   PREFIX_0F3A60,
 858   PREFIX_0F3A61,
 859   PREFIX_0F3A62,
 860   PREFIX_0F3A63,
 861   PREFIX_0F3ADF,
 862   PREFIX_VEX_0F10,
 863   PREFIX_VEX_0F11,
 864   PREFIX_VEX_0F12,
 865   PREFIX_VEX_0F16,
 866   PREFIX_VEX_0F2A,
 867   PREFIX_VEX_0F2C,
 868   PREFIX_VEX_0F2D,
 869   PREFIX_VEX_0F2E,
 870   PREFIX_VEX_0F2F,
 871   PREFIX_VEX_0F51,
 872   PREFIX_VEX_0F52,
 873   PREFIX_VEX_0F53,
 874   PREFIX_VEX_0F58,
 875   PREFIX_VEX_0F59,
 876   PREFIX_VEX_0F5A,
 877   PREFIX_VEX_0F5B,
 878   PREFIX_VEX_0F5C,
 879   PREFIX_VEX_0F5D,
 880   PREFIX_VEX_0F5E,
 881   PREFIX_VEX_0F5F,
 882   PREFIX_VEX_0F60,
 883   PREFIX_VEX_0F61,
 884   PREFIX_VEX_0F62,
 885   PREFIX_VEX_0F63,
 886   PREFIX_VEX_0F64,
 887   PREFIX_VEX_0F65,
 888   PREFIX_VEX_0F66,
 889   PREFIX_VEX_0F67,
 890   PREFIX_VEX_0F68,
 891   PREFIX_VEX_0F69,
 892   PREFIX_VEX_0F6A,
 893   PREFIX_VEX_0F6B,
 894   PREFIX_VEX_0F6C,
 895   PREFIX_VEX_0F6D,
 896   PREFIX_VEX_0F6E,
 897   PREFIX_VEX_0F6F,
 898   PREFIX_VEX_0F70,
 899   PREFIX_VEX_0F71_REG_2,
 900   PREFIX_VEX_0F71_REG_4,
 901   PREFIX_VEX_0F71_REG_6,
 902   PREFIX_VEX_0F72_REG_2,
 903   PREFIX_VEX_0F72_REG_4,
 904   PREFIX_VEX_0F72_REG_6,
 905   PREFIX_VEX_0F73_REG_2,
 906   PREFIX_VEX_0F73_REG_3,
 907   PREFIX_VEX_0F73_REG_6,
 908   PREFIX_VEX_0F73_REG_7,
 909   PREFIX_VEX_0F74,
 910   PREFIX_VEX_0F75,
 911   PREFIX_VEX_0F76,
 912   PREFIX_VEX_0F77,
 913   PREFIX_VEX_0F7C,
 914   PREFIX_VEX_0F7D,
 915   PREFIX_VEX_0F7E,
 916   PREFIX_VEX_0F7F,
 917   PREFIX_VEX_0FC2,
 918   PREFIX_VEX_0FC4,
 919   PREFIX_VEX_0FC5,
 920   PREFIX_VEX_0FD0,
 921   PREFIX_VEX_0FD1,
 922   PREFIX_VEX_0FD2,
 923   PREFIX_VEX_0FD3,
 924   PREFIX_VEX_0FD4,
 925   PREFIX_VEX_0FD5,
 926   PREFIX_VEX_0FD6,
 927   PREFIX_VEX_0FD7,
 928   PREFIX_VEX_0FD8,
 929   PREFIX_VEX_0FD9,
 930   PREFIX_VEX_0FDA,
 931   PREFIX_VEX_0FDB,
 932   PREFIX_VEX_0FDC,
 933   PREFIX_VEX_0FDD,
 934   PREFIX_VEX_0FDE,
 935   PREFIX_VEX_0FDF,
 936   PREFIX_VEX_0FE0,
 937   PREFIX_VEX_0FE1,
 938   PREFIX_VEX_0FE2,
 939   PREFIX_VEX_0FE3,
 940   PREFIX_VEX_0FE4,
 941   PREFIX_VEX_0FE5,
 942   PREFIX_VEX_0FE6,
 943   PREFIX_VEX_0FE7,
 944   PREFIX_VEX_0FE8,
 945   PREFIX_VEX_0FE9,
 946   PREFIX_VEX_0FEA,
 947   PREFIX_VEX_0FEB,
 948   PREFIX_VEX_0FEC,
 949   PREFIX_VEX_0FED,
 950   PREFIX_VEX_0FEE,
 951   PREFIX_VEX_0FEF,
 952   PREFIX_VEX_0FF0,
 953   PREFIX_VEX_0FF1,
 954   PREFIX_VEX_0FF2,
 955   PREFIX_VEX_0FF3,
 956   PREFIX_VEX_0FF4,
 957   PREFIX_VEX_0FF5,
 958   PREFIX_VEX_0FF6,
 959   PREFIX_VEX_0FF7,
 960   PREFIX_VEX_0FF8,
 961   PREFIX_VEX_0FF9,
 962   PREFIX_VEX_0FFA,
 963   PREFIX_VEX_0FFB,
 964   PREFIX_VEX_0FFC,
 965   PREFIX_VEX_0FFD,
 966   PREFIX_VEX_0FFE,
 967   PREFIX_VEX_0F3800,
 968   PREFIX_VEX_0F3801,
 969   PREFIX_VEX_0F3802,
 970   PREFIX_VEX_0F3803,
 971   PREFIX_VEX_0F3804,
 972   PREFIX_VEX_0F3805,
 973   PREFIX_VEX_0F3806,
 974   PREFIX_VEX_0F3807,
 975   PREFIX_VEX_0F3808,
 976   PREFIX_VEX_0F3809,
 977   PREFIX_VEX_0F380A,
 978   PREFIX_VEX_0F380B,
 979   PREFIX_VEX_0F380C,
 980   PREFIX_VEX_0F380D,
 981   PREFIX_VEX_0F380E,
 982   PREFIX_VEX_0F380F,
 983   PREFIX_VEX_0F3813,
 984   PREFIX_VEX_0F3816,
 985   PREFIX_VEX_0F3817,
 986   PREFIX_VEX_0F3818,
 987   PREFIX_VEX_0F3819,
 988   PREFIX_VEX_0F381A,
 989   PREFIX_VEX_0F381C,
 990   PREFIX_VEX_0F381D,
 991   PREFIX_VEX_0F381E,
 992   PREFIX_VEX_0F3820,
 993   PREFIX_VEX_0F3821,
 994   PREFIX_VEX_0F3822,
 995   PREFIX_VEX_0F3823,
 996   PREFIX_VEX_0F3824,
 997   PREFIX_VEX_0F3825,
 998   PREFIX_VEX_0F3828,
 999   PREFIX_VEX_0F3829,
1000   PREFIX_VEX_0F382A,
1001   PREFIX_VEX_0F382B,
1002   PREFIX_VEX_0F382C,
1003   PREFIX_VEX_0F382D,
1004   PREFIX_VEX_0F382E,
1005   PREFIX_VEX_0F382F,
1006   PREFIX_VEX_0F3830,
1007   PREFIX_VEX_0F3831,
1008   PREFIX_VEX_0F3832,
1009   PREFIX_VEX_0F3833,
1010   PREFIX_VEX_0F3834,
1011   PREFIX_VEX_0F3835,
1012   PREFIX_VEX_0F3836,
1013   PREFIX_VEX_0F3837,
1014   PREFIX_VEX_0F3838,
1015   PREFIX_VEX_0F3839,
1016   PREFIX_VEX_0F383A,
1017   PREFIX_VEX_0F383B,
1018   PREFIX_VEX_0F383C,
1019   PREFIX_VEX_0F383D,
1020   PREFIX_VEX_0F383E,
1021   PREFIX_VEX_0F383F,
1022   PREFIX_VEX_0F3840,
1023   PREFIX_VEX_0F3841,
1024   PREFIX_VEX_0F3845,
1025   PREFIX_VEX_0F3846,
1026   PREFIX_VEX_0F3847,
1027   PREFIX_VEX_0F3858,
1028   PREFIX_VEX_0F3859,
1029   PREFIX_VEX_0F385A,
1030   PREFIX_VEX_0F3878,
1031   PREFIX_VEX_0F3879,
1032   PREFIX_VEX_0F388C,
1033   PREFIX_VEX_0F388E,
1034   PREFIX_VEX_0F3890,
1035   PREFIX_VEX_0F3891,
1036   PREFIX_VEX_0F3892,
1037   PREFIX_VEX_0F3893,
1038   PREFIX_VEX_0F3896,
1039   PREFIX_VEX_0F3897,
1040   PREFIX_VEX_0F3898,
1041   PREFIX_VEX_0F3899,
1042   PREFIX_VEX_0F389A,
1043   PREFIX_VEX_0F389B,
1044   PREFIX_VEX_0F389C,
1045   PREFIX_VEX_0F389D,
1046   PREFIX_VEX_0F389E,
1047   PREFIX_VEX_0F389F,
1048   PREFIX_VEX_0F38A6,
1049   PREFIX_VEX_0F38A7,
1050   PREFIX_VEX_0F38A8,
1051   PREFIX_VEX_0F38A9,
1052   PREFIX_VEX_0F38AA,
1053   PREFIX_VEX_0F38AB,
1054   PREFIX_VEX_0F38AC,
1055   PREFIX_VEX_0F38AD,
1056   PREFIX_VEX_0F38AE,
1057   PREFIX_VEX_0F38AF,
1058   PREFIX_VEX_0F38B6,
1059   PREFIX_VEX_0F38B7,
1060   PREFIX_VEX_0F38B8,
1061   PREFIX_VEX_0F38B9,
1062   PREFIX_VEX_0F38BA,
1063   PREFIX_VEX_0F38BB,
1064   PREFIX_VEX_0F38BC,
1065   PREFIX_VEX_0F38BD,
1066   PREFIX_VEX_0F38BE,
1067   PREFIX_VEX_0F38BF,
1068   PREFIX_VEX_0F38DB,
1069   PREFIX_VEX_0F38DC,
1070   PREFIX_VEX_0F38DD,
1071   PREFIX_VEX_0F38DE,
1072   PREFIX_VEX_0F38DF,
1073   PREFIX_VEX_0F38F2,
1074   PREFIX_VEX_0F38F3_REG_1,
1075   PREFIX_VEX_0F38F3_REG_2,
1076   PREFIX_VEX_0F38F3_REG_3,
1077   PREFIX_VEX_0F38F5,
1078   PREFIX_VEX_0F38F6,
1079   PREFIX_VEX_0F38F7,
1080   PREFIX_VEX_0F3A00,
1081   PREFIX_VEX_0F3A01,
1082   PREFIX_VEX_0F3A02,
1083   PREFIX_VEX_0F3A04,
1084   PREFIX_VEX_0F3A05,
1085   PREFIX_VEX_0F3A06,
1086   PREFIX_VEX_0F3A08,
1087   PREFIX_VEX_0F3A09,
1088   PREFIX_VEX_0F3A0A,
1089   PREFIX_VEX_0F3A0B,
1090   PREFIX_VEX_0F3A0C,
1091   PREFIX_VEX_0F3A0D,
1092   PREFIX_VEX_0F3A0E,
1093   PREFIX_VEX_0F3A0F,
1094   PREFIX_VEX_0F3A14,
1095   PREFIX_VEX_0F3A15,
1096   PREFIX_VEX_0F3A16,
1097   PREFIX_VEX_0F3A17,
1098   PREFIX_VEX_0F3A18,
1099   PREFIX_VEX_0F3A19,
1100   PREFIX_VEX_0F3A1D,
1101   PREFIX_VEX_0F3A20,
1102   PREFIX_VEX_0F3A21,
1103   PREFIX_VEX_0F3A22,
1104   PREFIX_VEX_0F3A38,
1105   PREFIX_VEX_0F3A39,
1106   PREFIX_VEX_0F3A40,
1107   PREFIX_VEX_0F3A41,
1108   PREFIX_VEX_0F3A42,
1109   PREFIX_VEX_0F3A44,
1110   PREFIX_VEX_0F3A46,
1111   PREFIX_VEX_0F3A48,
1112   PREFIX_VEX_0F3A49,
1113   PREFIX_VEX_0F3A4A,
1114   PREFIX_VEX_0F3A4B,
1115   PREFIX_VEX_0F3A4C,
1116   PREFIX_VEX_0F3A5C,
1117   PREFIX_VEX_0F3A5D,
1118   PREFIX_VEX_0F3A5E,
1119   PREFIX_VEX_0F3A5F,
1120   PREFIX_VEX_0F3A60,
1121   PREFIX_VEX_0F3A61,
1122   PREFIX_VEX_0F3A62,
1123   PREFIX_VEX_0F3A63,
1124   PREFIX_VEX_0F3A68,
1125   PREFIX_VEX_0F3A69,
1126   PREFIX_VEX_0F3A6A,
1127   PREFIX_VEX_0F3A6B,
1128   PREFIX_VEX_0F3A6C,
1129   PREFIX_VEX_0F3A6D,
1130   PREFIX_VEX_0F3A6E,
1131   PREFIX_VEX_0F3A6F,
1132   PREFIX_VEX_0F3A78,
1133   PREFIX_VEX_0F3A79,
1134   PREFIX_VEX_0F3A7A,
1135   PREFIX_VEX_0F3A7B,
1136   PREFIX_VEX_0F3A7C,
1137   PREFIX_VEX_0F3A7D,
1138   PREFIX_VEX_0F3A7E,
1139   PREFIX_VEX_0F3A7F,
1140   PREFIX_VEX_0F3ADF,
1141   PREFIX_VEX_0F3AF0
1142 };
1143
1144 enum
1145 {
1146   X86_64_06 = 0,
1147   X86_64_07,
1148   X86_64_0D,
1149   X86_64_16,
1150   X86_64_17,
1151   X86_64_1E,
1152   X86_64_1F,
1153   X86_64_27,
1154   X86_64_2F,
1155   X86_64_37,
1156   X86_64_3F,
1157   X86_64_60,
1158   X86_64_61,
1159   X86_64_62,
1160   X86_64_63,
1161   X86_64_6D,
1162   X86_64_6F,
1163   X86_64_9A,
1164   X86_64_C4,
1165   X86_64_C5,
1166   X86_64_CE,
1167   X86_64_D4,
1168   X86_64_D5,
1169   X86_64_EA,
1170   X86_64_0F01_REG_0,
1171   X86_64_0F01_REG_1,
1172   X86_64_0F01_REG_2,
1173   X86_64_0F01_REG_3
1174 };
1175
1176 enum
1177 {
1178   THREE_BYTE_0F38 = 0,
1179   THREE_BYTE_0F3A,
1180   THREE_BYTE_0F7A
1181 };
1182
1183 enum
1184 {
1185   XOP_08 = 0,
1186   XOP_09,
1187   XOP_0A
1188 };
1189
1190 enum
1191 {
1192   VEX_0F = 0,
1193   VEX_0F38,
1194   VEX_0F3A
1195 };
1196
1197 enum
1198 {
1199   VEX_LEN_0F10_P_1 = 0,
1200   VEX_LEN_0F10_P_3,
1201   VEX_LEN_0F11_P_1,
1202   VEX_LEN_0F11_P_3,
1203   VEX_LEN_0F12_P_0_M_0,
1204   VEX_LEN_0F12_P_0_M_1,
1205   VEX_LEN_0F12_P_2,
1206   VEX_LEN_0F13_M_0,
1207   VEX_LEN_0F16_P_0_M_0,
1208   VEX_LEN_0F16_P_0_M_1,
1209   VEX_LEN_0F16_P_2,
1210   VEX_LEN_0F17_M_0,
1211   VEX_LEN_0F2A_P_1,
1212   VEX_LEN_0F2A_P_3,
1213   VEX_LEN_0F2C_P_1,
1214   VEX_LEN_0F2C_P_3,
1215   VEX_LEN_0F2D_P_1,
1216   VEX_LEN_0F2D_P_3,
1217   VEX_LEN_0F2E_P_0,
1218   VEX_LEN_0F2E_P_2,
1219   VEX_LEN_0F2F_P_0,
1220   VEX_LEN_0F2F_P_2,
1221   VEX_LEN_0F51_P_1,
1222   VEX_LEN_0F51_P_3,
1223   VEX_LEN_0F52_P_1,
1224   VEX_LEN_0F53_P_1,
1225   VEX_LEN_0F58_P_1,
1226   VEX_LEN_0F58_P_3,
1227   VEX_LEN_0F59_P_1,
1228   VEX_LEN_0F59_P_3,
1229   VEX_LEN_0F5A_P_1,
1230   VEX_LEN_0F5A_P_3,
1231   VEX_LEN_0F5C_P_1,
1232   VEX_LEN_0F5C_P_3,
1233   VEX_LEN_0F5D_P_1,
1234   VEX_LEN_0F5D_P_3,
1235   VEX_LEN_0F5E_P_1,
1236   VEX_LEN_0F5E_P_3,
1237   VEX_LEN_0F5F_P_1,
1238   VEX_LEN_0F5F_P_3,
1239   VEX_LEN_0F6E_P_2,
1240   VEX_LEN_0F7E_P_1,
1241   VEX_LEN_0F7E_P_2,
1242   VEX_LEN_0FAE_R_2_M_0,
1243   VEX_LEN_0FAE_R_3_M_0,
1244   VEX_LEN_0FC2_P_1,
1245   VEX_LEN_0FC2_P_3,
1246   VEX_LEN_0FC4_P_2,
1247   VEX_LEN_0FC5_P_2,
1248   VEX_LEN_0FD6_P_2,
1249   VEX_LEN_0FF7_P_2,
1250   VEX_LEN_0F3816_P_2,
1251   VEX_LEN_0F3819_P_2,
1252   VEX_LEN_0F381A_P_2_M_0,
1253   VEX_LEN_0F3836_P_2,
1254   VEX_LEN_0F3841_P_2,
1255   VEX_LEN_0F385A_P_2_M_0,
1256   VEX_LEN_0F38DB_P_2,
1257   VEX_LEN_0F38DC_P_2,
1258   VEX_LEN_0F38DD_P_2,
1259   VEX_LEN_0F38DE_P_2,
1260   VEX_LEN_0F38DF_P_2,
1261   VEX_LEN_0F38F2_P_0,
1262   VEX_LEN_0F38F3_R_1_P_0,
1263   VEX_LEN_0F38F3_R_2_P_0,
1264   VEX_LEN_0F38F3_R_3_P_0,
1265   VEX_LEN_0F38F5_P_0,
1266   VEX_LEN_0F38F5_P_1,
1267   VEX_LEN_0F38F5_P_3,
1268   VEX_LEN_0F38F6_P_3,
1269   VEX_LEN_0F38F7_P_0,
1270   VEX_LEN_0F38F7_P_1,
1271   VEX_LEN_0F38F7_P_2,
1272   VEX_LEN_0F38F7_P_3,
1273   VEX_LEN_0F3A00_P_2,
1274   VEX_LEN_0F3A01_P_2,
1275   VEX_LEN_0F3A06_P_2,
1276   VEX_LEN_0F3A0A_P_2,
1277   VEX_LEN_0F3A0B_P_2,
1278   VEX_LEN_0F3A14_P_2,
1279   VEX_LEN_0F3A15_P_2,
1280   VEX_LEN_0F3A16_P_2,
1281   VEX_LEN_0F3A17_P_2,
1282   VEX_LEN_0F3A18_P_2,
1283   VEX_LEN_0F3A19_P_2,
1284   VEX_LEN_0F3A20_P_2,
1285   VEX_LEN_0F3A21_P_2,
1286   VEX_LEN_0F3A22_P_2,
1287   VEX_LEN_0F3A38_P_2,
1288   VEX_LEN_0F3A39_P_2,
1289   VEX_LEN_0F3A41_P_2,
1290   VEX_LEN_0F3A44_P_2,
1291   VEX_LEN_0F3A46_P_2,
1292   VEX_LEN_0F3A60_P_2,
1293   VEX_LEN_0F3A61_P_2,
1294   VEX_LEN_0F3A62_P_2,
1295   VEX_LEN_0F3A63_P_2,
1296   VEX_LEN_0F3A6A_P_2,
1297   VEX_LEN_0F3A6B_P_2,
1298   VEX_LEN_0F3A6E_P_2,
1299   VEX_LEN_0F3A6F_P_2,
1300   VEX_LEN_0F3A7A_P_2,
1301   VEX_LEN_0F3A7B_P_2,
1302   VEX_LEN_0F3A7E_P_2,
1303   VEX_LEN_0F3A7F_P_2,
1304   VEX_LEN_0F3ADF_P_2,
1305   VEX_LEN_0F3AF0_P_3,
1306   VEX_LEN_0FXOP_09_80,
1307   VEX_LEN_0FXOP_09_81
1308 };
1309
1310 enum
1311 {
1312   VEX_W_0F10_P_0 = 0,
1313   VEX_W_0F10_P_1,
1314   VEX_W_0F10_P_2,
1315   VEX_W_0F10_P_3,
1316   VEX_W_0F11_P_0,
1317   VEX_W_0F11_P_1,
1318   VEX_W_0F11_P_2,
1319   VEX_W_0F11_P_3,
1320   VEX_W_0F12_P_0_M_0,
1321   VEX_W_0F12_P_0_M_1,
1322   VEX_W_0F12_P_1,
1323   VEX_W_0F12_P_2,
1324   VEX_W_0F12_P_3,
1325   VEX_W_0F13_M_0,
1326   VEX_W_0F14,
1327   VEX_W_0F15,
1328   VEX_W_0F16_P_0_M_0,
1329   VEX_W_0F16_P_0_M_1,
1330   VEX_W_0F16_P_1,
1331   VEX_W_0F16_P_2,
1332   VEX_W_0F17_M_0,
1333   VEX_W_0F28,
1334   VEX_W_0F29,
1335   VEX_W_0F2B_M_0,
1336   VEX_W_0F2E_P_0,
1337   VEX_W_0F2E_P_2,
1338   VEX_W_0F2F_P_0,
1339   VEX_W_0F2F_P_2,
1340   VEX_W_0F50_M_0,
1341   VEX_W_0F51_P_0,
1342   VEX_W_0F51_P_1,
1343   VEX_W_0F51_P_2,
1344   VEX_W_0F51_P_3,
1345   VEX_W_0F52_P_0,
1346   VEX_W_0F52_P_1,
1347   VEX_W_0F53_P_0,
1348   VEX_W_0F53_P_1,
1349   VEX_W_0F58_P_0,
1350   VEX_W_0F58_P_1,
1351   VEX_W_0F58_P_2,
1352   VEX_W_0F58_P_3,
1353   VEX_W_0F59_P_0,
1354   VEX_W_0F59_P_1,
1355   VEX_W_0F59_P_2,
1356   VEX_W_0F59_P_3,
1357   VEX_W_0F5A_P_0,
1358   VEX_W_0F5A_P_1,
1359   VEX_W_0F5A_P_3,
1360   VEX_W_0F5B_P_0,
1361   VEX_W_0F5B_P_1,
1362   VEX_W_0F5B_P_2,
1363   VEX_W_0F5C_P_0,
1364   VEX_W_0F5C_P_1,
1365   VEX_W_0F5C_P_2,
1366   VEX_W_0F5C_P_3,
1367   VEX_W_0F5D_P_0,
1368   VEX_W_0F5D_P_1,
1369   VEX_W_0F5D_P_2,
1370   VEX_W_0F5D_P_3,
1371   VEX_W_0F5E_P_0,
1372   VEX_W_0F5E_P_1,
1373   VEX_W_0F5E_P_2,
1374   VEX_W_0F5E_P_3,
1375   VEX_W_0F5F_P_0,
1376   VEX_W_0F5F_P_1,
1377   VEX_W_0F5F_P_2,
1378   VEX_W_0F5F_P_3,
1379   VEX_W_0F60_P_2,
1380   VEX_W_0F61_P_2,
1381   VEX_W_0F62_P_2,
1382   VEX_W_0F63_P_2,
1383   VEX_W_0F64_P_2,
1384   VEX_W_0F65_P_2,
1385   VEX_W_0F66_P_2,
1386   VEX_W_0F67_P_2,
1387   VEX_W_0F68_P_2,
1388   VEX_W_0F69_P_2,
1389   VEX_W_0F6A_P_2,
1390   VEX_W_0F6B_P_2,
1391   VEX_W_0F6C_P_2,
1392   VEX_W_0F6D_P_2,
1393   VEX_W_0F6F_P_1,
1394   VEX_W_0F6F_P_2,
1395   VEX_W_0F70_P_1,
1396   VEX_W_0F70_P_2,
1397   VEX_W_0F70_P_3,
1398   VEX_W_0F71_R_2_P_2,
1399   VEX_W_0F71_R_4_P_2,
1400   VEX_W_0F71_R_6_P_2,
1401   VEX_W_0F72_R_2_P_2,
1402   VEX_W_0F72_R_4_P_2,
1403   VEX_W_0F72_R_6_P_2,
1404   VEX_W_0F73_R_2_P_2,
1405   VEX_W_0F73_R_3_P_2,
1406   VEX_W_0F73_R_6_P_2,
1407   VEX_W_0F73_R_7_P_2,
1408   VEX_W_0F74_P_2,
1409   VEX_W_0F75_P_2,
1410   VEX_W_0F76_P_2,
1411   VEX_W_0F77_P_0,
1412   VEX_W_0F7C_P_2,
1413   VEX_W_0F7C_P_3,
1414   VEX_W_0F7D_P_2,
1415   VEX_W_0F7D_P_3,
1416   VEX_W_0F7E_P_1,
1417   VEX_W_0F7F_P_1,
1418   VEX_W_0F7F_P_2,
1419   VEX_W_0FAE_R_2_M_0,
1420   VEX_W_0FAE_R_3_M_0,
1421   VEX_W_0FC2_P_0,
1422   VEX_W_0FC2_P_1,
1423   VEX_W_0FC2_P_2,
1424   VEX_W_0FC2_P_3,
1425   VEX_W_0FC4_P_2,
1426   VEX_W_0FC5_P_2,
1427   VEX_W_0FD0_P_2,
1428   VEX_W_0FD0_P_3,
1429   VEX_W_0FD1_P_2,
1430   VEX_W_0FD2_P_2,
1431   VEX_W_0FD3_P_2,
1432   VEX_W_0FD4_P_2,
1433   VEX_W_0FD5_P_2,
1434   VEX_W_0FD6_P_2,
1435   VEX_W_0FD7_P_2_M_1,
1436   VEX_W_0FD8_P_2,
1437   VEX_W_0FD9_P_2,
1438   VEX_W_0FDA_P_2,
1439   VEX_W_0FDB_P_2,
1440   VEX_W_0FDC_P_2,
1441   VEX_W_0FDD_P_2,
1442   VEX_W_0FDE_P_2,
1443   VEX_W_0FDF_P_2,
1444   VEX_W_0FE0_P_2,
1445   VEX_W_0FE1_P_2,
1446   VEX_W_0FE2_P_2,
1447   VEX_W_0FE3_P_2,
1448   VEX_W_0FE4_P_2,
1449   VEX_W_0FE5_P_2,
1450   VEX_W_0FE6_P_1,
1451   VEX_W_0FE6_P_2,
1452   VEX_W_0FE6_P_3,
1453   VEX_W_0FE7_P_2_M_0,
1454   VEX_W_0FE8_P_2,
1455   VEX_W_0FE9_P_2,
1456   VEX_W_0FEA_P_2,
1457   VEX_W_0FEB_P_2,
1458   VEX_W_0FEC_P_2,
1459   VEX_W_0FED_P_2,
1460   VEX_W_0FEE_P_2,
1461   VEX_W_0FEF_P_2,
1462   VEX_W_0FF0_P_3_M_0,
1463   VEX_W_0FF1_P_2,
1464   VEX_W_0FF2_P_2,
1465   VEX_W_0FF3_P_2,
1466   VEX_W_0FF4_P_2,
1467   VEX_W_0FF5_P_2,
1468   VEX_W_0FF6_P_2,
1469   VEX_W_0FF7_P_2,
1470   VEX_W_0FF8_P_2,
1471   VEX_W_0FF9_P_2,
1472   VEX_W_0FFA_P_2,
1473   VEX_W_0FFB_P_2,
1474   VEX_W_0FFC_P_2,
1475   VEX_W_0FFD_P_2,
1476   VEX_W_0FFE_P_2,
1477   VEX_W_0F3800_P_2,
1478   VEX_W_0F3801_P_2,
1479   VEX_W_0F3802_P_2,
1480   VEX_W_0F3803_P_2,
1481   VEX_W_0F3804_P_2,
1482   VEX_W_0F3805_P_2,
1483   VEX_W_0F3806_P_2,
1484   VEX_W_0F3807_P_2,
1485   VEX_W_0F3808_P_2,
1486   VEX_W_0F3809_P_2,
1487   VEX_W_0F380A_P_2,
1488   VEX_W_0F380B_P_2,
1489   VEX_W_0F380C_P_2,
1490   VEX_W_0F380D_P_2,
1491   VEX_W_0F380E_P_2,
1492   VEX_W_0F380F_P_2,
1493   VEX_W_0F3816_P_2,
1494   VEX_W_0F3817_P_2,
1495   VEX_W_0F3818_P_2,
1496   VEX_W_0F3819_P_2,
1497   VEX_W_0F381A_P_2_M_0,
1498   VEX_W_0F381C_P_2,
1499   VEX_W_0F381D_P_2,
1500   VEX_W_0F381E_P_2,
1501   VEX_W_0F3820_P_2,
1502   VEX_W_0F3821_P_2,
1503   VEX_W_0F3822_P_2,
1504   VEX_W_0F3823_P_2,
1505   VEX_W_0F3824_P_2,
1506   VEX_W_0F3825_P_2,
1507   VEX_W_0F3828_P_2,
1508   VEX_W_0F3829_P_2,
1509   VEX_W_0F382A_P_2_M_0,
1510   VEX_W_0F382B_P_2,
1511   VEX_W_0F382C_P_2_M_0,
1512   VEX_W_0F382D_P_2_M_0,
1513   VEX_W_0F382E_P_2_M_0,
1514   VEX_W_0F382F_P_2_M_0,
1515   VEX_W_0F3830_P_2,
1516   VEX_W_0F3831_P_2,
1517   VEX_W_0F3832_P_2,
1518   VEX_W_0F3833_P_2,
1519   VEX_W_0F3834_P_2,
1520   VEX_W_0F3835_P_2,
1521   VEX_W_0F3836_P_2,
1522   VEX_W_0F3837_P_2,
1523   VEX_W_0F3838_P_2,
1524   VEX_W_0F3839_P_2,
1525   VEX_W_0F383A_P_2,
1526   VEX_W_0F383B_P_2,
1527   VEX_W_0F383C_P_2,
1528   VEX_W_0F383D_P_2,
1529   VEX_W_0F383E_P_2,
1530   VEX_W_0F383F_P_2,
1531   VEX_W_0F3840_P_2,
1532   VEX_W_0F3841_P_2,
1533   VEX_W_0F3846_P_2,
1534   VEX_W_0F3858_P_2,
1535   VEX_W_0F3859_P_2,
1536   VEX_W_0F385A_P_2_M_0,
1537   VEX_W_0F3878_P_2,
1538   VEX_W_0F3879_P_2,
1539   VEX_W_0F38DB_P_2,
1540   VEX_W_0F38DC_P_2,
1541   VEX_W_0F38DD_P_2,
1542   VEX_W_0F38DE_P_2,
1543   VEX_W_0F38DF_P_2,
1544   VEX_W_0F3A00_P_2,
1545   VEX_W_0F3A01_P_2,
1546   VEX_W_0F3A02_P_2,
1547   VEX_W_0F3A04_P_2,
1548   VEX_W_0F3A05_P_2,
1549   VEX_W_0F3A06_P_2,
1550   VEX_W_0F3A08_P_2,
1551   VEX_W_0F3A09_P_2,
1552   VEX_W_0F3A0A_P_2,
1553   VEX_W_0F3A0B_P_2,
1554   VEX_W_0F3A0C_P_2,
1555   VEX_W_0F3A0D_P_2,
1556   VEX_W_0F3A0E_P_2,
1557   VEX_W_0F3A0F_P_2,
1558   VEX_W_0F3A14_P_2,
1559   VEX_W_0F3A15_P_2,
1560   VEX_W_0F3A18_P_2,
1561   VEX_W_0F3A19_P_2,
1562   VEX_W_0F3A20_P_2,
1563   VEX_W_0F3A21_P_2,
1564   VEX_W_0F3A38_P_2,
1565   VEX_W_0F3A39_P_2,
1566   VEX_W_0F3A40_P_2,
1567   VEX_W_0F3A41_P_2,
1568   VEX_W_0F3A42_P_2,
1569   VEX_W_0F3A44_P_2,
1570   VEX_W_0F3A46_P_2,
1571   VEX_W_0F3A48_P_2,
1572   VEX_W_0F3A49_P_2,
1573   VEX_W_0F3A4A_P_2,
1574   VEX_W_0F3A4B_P_2,
1575   VEX_W_0F3A4C_P_2,
1576   VEX_W_0F3A60_P_2,
1577   VEX_W_0F3A61_P_2,
1578   VEX_W_0F3A62_P_2,
1579   VEX_W_0F3A63_P_2,
1580   VEX_W_0F3ADF_P_2
1581 };
1582
1583 typedef void (*op_rtn) (int bytemode, int sizeflag);
1584
1585 struct dis386 {
1586   const char *name;
1587   struct
1588     {
1589       op_rtn rtn;
1590       int bytemode;
1591     } op[MAX_OPERANDS];
1592 };
1593
1594 /* Upper case letters in the instruction names here are macros.
1595    'A' => print 'b' if no register operands or suffix_always is true
1596    'B' => print 'b' if suffix_always is true
1597    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1598           size prefix
1599    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1600           suffix_always is true
1601    'E' => print 'e' if 32-bit form of jcxz
1602    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1603    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1604    'H' => print ",pt" or ",pn" branch hint
1605    'I' => honor following macro letter even in Intel mode (implemented only
1606           for some of the macro letters)
1607    'J' => print 'l'
1608    'K' => print 'd' or 'q' if rex prefix is present.
1609    'L' => print 'l' if suffix_always is true
1610    'M' => print 'r' if intel_mnemonic is false.
1611    'N' => print 'n' if instruction has no wait "prefix"
1612    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1613    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1614           or suffix_always is true.  print 'q' if rex prefix is present.
1615    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1616           is true
1617    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1618    'S' => print 'w', 'l' or 'q' if suffix_always is true
1619    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1620    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1621    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1622    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1623    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1624    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1625           suffix_always is true.
1626    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1627    '!' => change condition from true to false or from false to true.
1628    '%' => add 1 upper case letter to the macro.
1629
1630    2 upper case letter macros:
1631    "XY" => print 'x' or 'y' if no register operands or suffix_always
1632            is true.
1633    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1634    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1635            or suffix_always is true
1636    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1637    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1638    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1639    "LW" => print 'd', 'q' depending on the VEX.W bit
1640
1641    Many of the above letters print nothing in Intel mode.  See "putop"
1642    for the details.
1643
1644    Braces '{' and '}', and vertical bars '|', indicate alternative
1645    mnemonic strings for AT&T and Intel.  */
1646
1647 static const struct dis386 dis386[] = {
1648   /* 00 */
1649   { "addB",             { Eb, Gb } },
1650   { "addS",             { Ev, Gv } },
1651   { "addB",             { Gb, EbS } },
1652   { "addS",             { Gv, EvS } },
1653   { "addB",             { AL, Ib } },
1654   { "addS",             { eAX, Iv } },
1655   { X86_64_TABLE (X86_64_06) },
1656   { X86_64_TABLE (X86_64_07) },
1657   /* 08 */
1658   { "orB",              { Eb, Gb } },
1659   { "orS",              { Ev, Gv } },
1660   { "orB",              { Gb, EbS } },
1661   { "orS",              { Gv, EvS } },
1662   { "orB",              { AL, Ib } },
1663   { "orS",              { eAX, Iv } },
1664   { X86_64_TABLE (X86_64_0D) },
1665   { Bad_Opcode },       /* 0x0f extended opcode escape */
1666   /* 10 */
1667   { "adcB",             { Eb, Gb } },
1668   { "adcS",             { Ev, Gv } },
1669   { "adcB",             { Gb, EbS } },
1670   { "adcS",             { Gv, EvS } },
1671   { "adcB",             { AL, Ib } },
1672   { "adcS",             { eAX, Iv } },
1673   { X86_64_TABLE (X86_64_16) },
1674   { X86_64_TABLE (X86_64_17) },
1675   /* 18 */
1676   { "sbbB",             { Eb, Gb } },
1677   { "sbbS",             { Ev, Gv } },
1678   { "sbbB",             { Gb, EbS } },
1679   { "sbbS",             { Gv, EvS } },
1680   { "sbbB",             { AL, Ib } },
1681   { "sbbS",             { eAX, Iv } },
1682   { X86_64_TABLE (X86_64_1E) },
1683   { X86_64_TABLE (X86_64_1F) },
1684   /* 20 */
1685   { "andB",             { Eb, Gb } },
1686   { "andS",             { Ev, Gv } },
1687   { "andB",             { Gb, EbS } },
1688   { "andS",             { Gv, EvS } },
1689   { "andB",             { AL, Ib } },
1690   { "andS",             { eAX, Iv } },
1691   { Bad_Opcode },       /* SEG ES prefix */
1692   { X86_64_TABLE (X86_64_27) },
1693   /* 28 */
1694   { "subB",             { Eb, Gb } },
1695   { "subS",             { Ev, Gv } },
1696   { "subB",             { Gb, EbS } },
1697   { "subS",             { Gv, EvS } },
1698   { "subB",             { AL, Ib } },
1699   { "subS",             { eAX, Iv } },
1700   { Bad_Opcode },       /* SEG CS prefix */
1701   { X86_64_TABLE (X86_64_2F) },
1702   /* 30 */
1703   { "xorB",             { Eb, Gb } },
1704   { "xorS",             { Ev, Gv } },
1705   { "xorB",             { Gb, EbS } },
1706   { "xorS",             { Gv, EvS } },
1707   { "xorB",             { AL, Ib } },
1708   { "xorS",             { eAX, Iv } },
1709   { Bad_Opcode },       /* SEG SS prefix */
1710   { X86_64_TABLE (X86_64_37) },
1711   /* 38 */
1712   { "cmpB",             { Eb, Gb } },
1713   { "cmpS",             { Ev, Gv } },
1714   { "cmpB",             { Gb, EbS } },
1715   { "cmpS",             { Gv, EvS } },
1716   { "cmpB",             { AL, Ib } },
1717   { "cmpS",             { eAX, Iv } },
1718   { Bad_Opcode },       /* SEG DS prefix */
1719   { X86_64_TABLE (X86_64_3F) },
1720   /* 40 */
1721   { "inc{S|}",          { RMeAX } },
1722   { "inc{S|}",          { RMeCX } },
1723   { "inc{S|}",          { RMeDX } },
1724   { "inc{S|}",          { RMeBX } },
1725   { "inc{S|}",          { RMeSP } },
1726   { "inc{S|}",          { RMeBP } },
1727   { "inc{S|}",          { RMeSI } },
1728   { "inc{S|}",          { RMeDI } },
1729   /* 48 */
1730   { "dec{S|}",          { RMeAX } },
1731   { "dec{S|}",          { RMeCX } },
1732   { "dec{S|}",          { RMeDX } },
1733   { "dec{S|}",          { RMeBX } },
1734   { "dec{S|}",          { RMeSP } },
1735   { "dec{S|}",          { RMeBP } },
1736   { "dec{S|}",          { RMeSI } },
1737   { "dec{S|}",          { RMeDI } },
1738   /* 50 */
1739   { "pushV",            { RMrAX } },
1740   { "pushV",            { RMrCX } },
1741   { "pushV",            { RMrDX } },
1742   { "pushV",            { RMrBX } },
1743   { "pushV",            { RMrSP } },
1744   { "pushV",            { RMrBP } },
1745   { "pushV",            { RMrSI } },
1746   { "pushV",            { RMrDI } },
1747   /* 58 */
1748   { "popV",             { RMrAX } },
1749   { "popV",             { RMrCX } },
1750   { "popV",             { RMrDX } },
1751   { "popV",             { RMrBX } },
1752   { "popV",             { RMrSP } },
1753   { "popV",             { RMrBP } },
1754   { "popV",             { RMrSI } },
1755   { "popV",             { RMrDI } },
1756   /* 60 */
1757   { X86_64_TABLE (X86_64_60) },
1758   { X86_64_TABLE (X86_64_61) },
1759   { X86_64_TABLE (X86_64_62) },
1760   { X86_64_TABLE (X86_64_63) },
1761   { Bad_Opcode },       /* seg fs */
1762   { Bad_Opcode },       /* seg gs */
1763   { Bad_Opcode },       /* op size prefix */
1764   { Bad_Opcode },       /* adr size prefix */
1765   /* 68 */
1766   { "pushT",            { sIv } },
1767   { "imulS",            { Gv, Ev, Iv } },
1768   { "pushT",            { sIbT } },
1769   { "imulS",            { Gv, Ev, sIb } },
1770   { "ins{b|}",          { Ybr, indirDX } },
1771   { X86_64_TABLE (X86_64_6D) },
1772   { "outs{b|}",         { indirDXr, Xb } },
1773   { X86_64_TABLE (X86_64_6F) },
1774   /* 70 */
1775   { "joH",              { Jb, XX, cond_jump_flag } },
1776   { "jnoH",             { Jb, XX, cond_jump_flag } },
1777   { "jbH",              { Jb, XX, cond_jump_flag } },
1778   { "jaeH",             { Jb, XX, cond_jump_flag } },
1779   { "jeH",              { Jb, XX, cond_jump_flag } },
1780   { "jneH",             { Jb, XX, cond_jump_flag } },
1781   { "jbeH",             { Jb, XX, cond_jump_flag } },
1782   { "jaH",              { Jb, XX, cond_jump_flag } },
1783   /* 78 */
1784   { "jsH",              { Jb, XX, cond_jump_flag } },
1785   { "jnsH",             { Jb, XX, cond_jump_flag } },
1786   { "jpH",              { Jb, XX, cond_jump_flag } },
1787   { "jnpH",             { Jb, XX, cond_jump_flag } },
1788   { "jlH",              { Jb, XX, cond_jump_flag } },
1789   { "jgeH",             { Jb, XX, cond_jump_flag } },
1790   { "jleH",             { Jb, XX, cond_jump_flag } },
1791   { "jgH",              { Jb, XX, cond_jump_flag } },
1792   /* 80 */
1793   { REG_TABLE (REG_80) },
1794   { REG_TABLE (REG_81) },
1795   { Bad_Opcode },
1796   { REG_TABLE (REG_82) },
1797   { "testB",            { Eb, Gb } },
1798   { "testS",            { Ev, Gv } },
1799   { "xchgB",            { Eb, Gb } },
1800   { "xchgS",            { Ev, Gv } },
1801   /* 88 */
1802   { "movB",             { Eb, Gb } },
1803   { "movS",             { Ev, Gv } },
1804   { "movB",             { Gb, EbS } },
1805   { "movS",             { Gv, EvS } },
1806   { "movD",             { Sv, Sw } },
1807   { MOD_TABLE (MOD_8D) },
1808   { "movD",             { Sw, Sv } },
1809   { REG_TABLE (REG_8F) },
1810   /* 90 */
1811   { PREFIX_TABLE (PREFIX_90) },
1812   { "xchgS",            { RMeCX, eAX } },
1813   { "xchgS",            { RMeDX, eAX } },
1814   { "xchgS",            { RMeBX, eAX } },
1815   { "xchgS",            { RMeSP, eAX } },
1816   { "xchgS",            { RMeBP, eAX } },
1817   { "xchgS",            { RMeSI, eAX } },
1818   { "xchgS",            { RMeDI, eAX } },
1819   /* 98 */
1820   { "cW{t|}R",          { XX } },
1821   { "cR{t|}O",          { XX } },
1822   { X86_64_TABLE (X86_64_9A) },
1823   { Bad_Opcode },       /* fwait */
1824   { "pushfT",           { XX } },
1825   { "popfT",            { XX } },
1826   { "sahf",             { XX } },
1827   { "lahf",             { XX } },
1828   /* a0 */
1829   { "mov%LB",           { AL, Ob } },
1830   { "mov%LS",           { eAX, Ov } },
1831   { "mov%LB",           { Ob, AL } },
1832   { "mov%LS",           { Ov, eAX } },
1833   { "movs{b|}",         { Ybr, Xb } },
1834   { "movs{R|}",         { Yvr, Xv } },
1835   { "cmps{b|}",         { Xb, Yb } },
1836   { "cmps{R|}",         { Xv, Yv } },
1837   /* a8 */
1838   { "testB",            { AL, Ib } },
1839   { "testS",            { eAX, Iv } },
1840   { "stosB",            { Ybr, AL } },
1841   { "stosS",            { Yvr, eAX } },
1842   { "lodsB",            { ALr, Xb } },
1843   { "lodsS",            { eAXr, Xv } },
1844   { "scasB",            { AL, Yb } },
1845   { "scasS",            { eAX, Yv } },
1846   /* b0 */
1847   { "movB",             { RMAL, Ib } },
1848   { "movB",             { RMCL, Ib } },
1849   { "movB",             { RMDL, Ib } },
1850   { "movB",             { RMBL, Ib } },
1851   { "movB",             { RMAH, Ib } },
1852   { "movB",             { RMCH, Ib } },
1853   { "movB",             { RMDH, Ib } },
1854   { "movB",             { RMBH, Ib } },
1855   /* b8 */
1856   { "mov%LV",           { RMeAX, Iv64 } },
1857   { "mov%LV",           { RMeCX, Iv64 } },
1858   { "mov%LV",           { RMeDX, Iv64 } },
1859   { "mov%LV",           { RMeBX, Iv64 } },
1860   { "mov%LV",           { RMeSP, Iv64 } },
1861   { "mov%LV",           { RMeBP, Iv64 } },
1862   { "mov%LV",           { RMeSI, Iv64 } },
1863   { "mov%LV",           { RMeDI, Iv64 } },
1864   /* c0 */
1865   { REG_TABLE (REG_C0) },
1866   { REG_TABLE (REG_C1) },
1867   { "retT",             { Iw } },
1868   { "retT",             { XX } },
1869   { X86_64_TABLE (X86_64_C4) },
1870   { X86_64_TABLE (X86_64_C5) },
1871   { REG_TABLE (REG_C6) },
1872   { REG_TABLE (REG_C7) },
1873   /* c8 */
1874   { "enterT",           { Iw, Ib } },
1875   { "leaveT",           { XX } },
1876   { "Jret{|f}P",        { Iw } },
1877   { "Jret{|f}P",        { XX } },
1878   { "int3",             { XX } },
1879   { "int",              { Ib } },
1880   { X86_64_TABLE (X86_64_CE) },
1881   { "iretP",            { XX } },
1882   /* d0 */
1883   { REG_TABLE (REG_D0) },
1884   { REG_TABLE (REG_D1) },
1885   { REG_TABLE (REG_D2) },
1886   { REG_TABLE (REG_D3) },
1887   { X86_64_TABLE (X86_64_D4) },
1888   { X86_64_TABLE (X86_64_D5) },
1889   { Bad_Opcode },
1890   { "xlat",             { DSBX } },
1891   /* d8 */
1892   { FLOAT },
1893   { FLOAT },
1894   { FLOAT },
1895   { FLOAT },
1896   { FLOAT },
1897   { FLOAT },
1898   { FLOAT },
1899   { FLOAT },
1900   /* e0 */
1901   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1902   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1903   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1904   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1905   { "inB",              { AL, Ib } },
1906   { "inG",              { zAX, Ib } },
1907   { "outB",             { Ib, AL } },
1908   { "outG",             { Ib, zAX } },
1909   /* e8 */
1910   { "callT",            { Jv } },
1911   { "jmpT",             { Jv } },
1912   { X86_64_TABLE (X86_64_EA) },
1913   { "jmp",              { Jb } },
1914   { "inB",              { AL, indirDX } },
1915   { "inG",              { zAX, indirDX } },
1916   { "outB",             { indirDX, AL } },
1917   { "outG",             { indirDX, zAX } },
1918   /* f0 */
1919   { Bad_Opcode },       /* lock prefix */
1920   { "icebp",            { XX } },
1921   { Bad_Opcode },       /* repne */
1922   { Bad_Opcode },       /* repz */
1923   { "hlt",              { XX } },
1924   { "cmc",              { XX } },
1925   { REG_TABLE (REG_F6) },
1926   { REG_TABLE (REG_F7) },
1927   /* f8 */
1928   { "clc",              { XX } },
1929   { "stc",              { XX } },
1930   { "cli",              { XX } },
1931   { "sti",              { XX } },
1932   { "cld",              { XX } },
1933   { "std",              { XX } },
1934   { REG_TABLE (REG_FE) },
1935   { REG_TABLE (REG_FF) },
1936 };
1937
1938 static const struct dis386 dis386_twobyte[] = {
1939   /* 00 */
1940   { REG_TABLE (REG_0F00 ) },
1941   { REG_TABLE (REG_0F01 ) },
1942   { "larS",             { Gv, Ew } },
1943   { "lslS",             { Gv, Ew } },
1944   { Bad_Opcode },
1945   { "syscall",          { XX } },
1946   { "clts",             { XX } },
1947   { "sysretP",          { XX } },
1948   /* 08 */
1949   { "invd",             { XX } },
1950   { "wbinvd",           { XX } },
1951   { Bad_Opcode },
1952   { "ud2",              { XX } },
1953   { Bad_Opcode },
1954   { REG_TABLE (REG_0F0D) },
1955   { "femms",            { XX } },
1956   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1957   /* 10 */
1958   { PREFIX_TABLE (PREFIX_0F10) },
1959   { PREFIX_TABLE (PREFIX_0F11) },
1960   { PREFIX_TABLE (PREFIX_0F12) },
1961   { MOD_TABLE (MOD_0F13) },
1962   { "unpcklpX",         { XM, EXx } },
1963   { "unpckhpX",         { XM, EXx } },
1964   { PREFIX_TABLE (PREFIX_0F16) },
1965   { MOD_TABLE (MOD_0F17) },
1966   /* 18 */
1967   { REG_TABLE (REG_0F18) },
1968   { "nopQ",             { Ev } },
1969   { "nopQ",             { Ev } },
1970   { "nopQ",             { Ev } },
1971   { "nopQ",             { Ev } },
1972   { "nopQ",             { Ev } },
1973   { "nopQ",             { Ev } },
1974   { "nopQ",             { Ev } },
1975   /* 20 */
1976   { MOD_TABLE (MOD_0F20) },
1977   { MOD_TABLE (MOD_0F21) },
1978   { MOD_TABLE (MOD_0F22) },
1979   { MOD_TABLE (MOD_0F23) },
1980   { MOD_TABLE (MOD_0F24) },
1981   { Bad_Opcode },
1982   { MOD_TABLE (MOD_0F26) },
1983   { Bad_Opcode },
1984   /* 28 */
1985   { "movapX",           { XM, EXx } },
1986   { "movapX",           { EXxS, XM } },
1987   { PREFIX_TABLE (PREFIX_0F2A) },
1988   { PREFIX_TABLE (PREFIX_0F2B) },
1989   { PREFIX_TABLE (PREFIX_0F2C) },
1990   { PREFIX_TABLE (PREFIX_0F2D) },
1991   { PREFIX_TABLE (PREFIX_0F2E) },
1992   { PREFIX_TABLE (PREFIX_0F2F) },
1993   /* 30 */
1994   { "wrmsr",            { XX } },
1995   { "rdtsc",            { XX } },
1996   { "rdmsr",            { XX } },
1997   { "rdpmc",            { XX } },
1998   { "sysenter",         { XX } },
1999   { "sysexit",          { XX } },
2000   { Bad_Opcode },
2001   { "getsec",           { XX } },
2002   /* 38 */
2003   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2004   { Bad_Opcode },
2005   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2006   { Bad_Opcode },
2007   { Bad_Opcode },
2008   { Bad_Opcode },
2009   { Bad_Opcode },
2010   { Bad_Opcode },
2011   /* 40 */
2012   { "cmovoS",           { Gv, Ev } },
2013   { "cmovnoS",          { Gv, Ev } },
2014   { "cmovbS",           { Gv, Ev } },
2015   { "cmovaeS",          { Gv, Ev } },
2016   { "cmoveS",           { Gv, Ev } },
2017   { "cmovneS",          { Gv, Ev } },
2018   { "cmovbeS",          { Gv, Ev } },
2019   { "cmovaS",           { Gv, Ev } },
2020   /* 48 */
2021   { "cmovsS",           { Gv, Ev } },
2022   { "cmovnsS",          { Gv, Ev } },
2023   { "cmovpS",           { Gv, Ev } },
2024   { "cmovnpS",          { Gv, Ev } },
2025   { "cmovlS",           { Gv, Ev } },
2026   { "cmovgeS",          { Gv, Ev } },
2027   { "cmovleS",          { Gv, Ev } },
2028   { "cmovgS",           { Gv, Ev } },
2029   /* 50 */
2030   { MOD_TABLE (MOD_0F51) },
2031   { PREFIX_TABLE (PREFIX_0F51) },
2032   { PREFIX_TABLE (PREFIX_0F52) },
2033   { PREFIX_TABLE (PREFIX_0F53) },
2034   { "andpX",            { XM, EXx } },
2035   { "andnpX",           { XM, EXx } },
2036   { "orpX",             { XM, EXx } },
2037   { "xorpX",            { XM, EXx } },
2038   /* 58 */
2039   { PREFIX_TABLE (PREFIX_0F58) },
2040   { PREFIX_TABLE (PREFIX_0F59) },
2041   { PREFIX_TABLE (PREFIX_0F5A) },
2042   { PREFIX_TABLE (PREFIX_0F5B) },
2043   { PREFIX_TABLE (PREFIX_0F5C) },
2044   { PREFIX_TABLE (PREFIX_0F5D) },
2045   { PREFIX_TABLE (PREFIX_0F5E) },
2046   { PREFIX_TABLE (PREFIX_0F5F) },
2047   /* 60 */
2048   { PREFIX_TABLE (PREFIX_0F60) },
2049   { PREFIX_TABLE (PREFIX_0F61) },
2050   { PREFIX_TABLE (PREFIX_0F62) },
2051   { "packsswb",         { MX, EM } },
2052   { "pcmpgtb",          { MX, EM } },
2053   { "pcmpgtw",          { MX, EM } },
2054   { "pcmpgtd",          { MX, EM } },
2055   { "packuswb",         { MX, EM } },
2056   /* 68 */
2057   { "punpckhbw",        { MX, EM } },
2058   { "punpckhwd",        { MX, EM } },
2059   { "punpckhdq",        { MX, EM } },
2060   { "packssdw",         { MX, EM } },
2061   { PREFIX_TABLE (PREFIX_0F6C) },
2062   { PREFIX_TABLE (PREFIX_0F6D) },
2063   { "movK",             { MX, Edq } },
2064   { PREFIX_TABLE (PREFIX_0F6F) },
2065   /* 70 */
2066   { PREFIX_TABLE (PREFIX_0F70) },
2067   { REG_TABLE (REG_0F71) },
2068   { REG_TABLE (REG_0F72) },
2069   { REG_TABLE (REG_0F73) },
2070   { "pcmpeqb",          { MX, EM } },
2071   { "pcmpeqw",          { MX, EM } },
2072   { "pcmpeqd",          { MX, EM } },
2073   { "emms",             { XX } },
2074   /* 78 */
2075   { PREFIX_TABLE (PREFIX_0F78) },
2076   { PREFIX_TABLE (PREFIX_0F79) },
2077   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2078   { Bad_Opcode },
2079   { PREFIX_TABLE (PREFIX_0F7C) },
2080   { PREFIX_TABLE (PREFIX_0F7D) },
2081   { PREFIX_TABLE (PREFIX_0F7E) },
2082   { PREFIX_TABLE (PREFIX_0F7F) },
2083   /* 80 */
2084   { "joH",              { Jv, XX, cond_jump_flag } },
2085   { "jnoH",             { Jv, XX, cond_jump_flag } },
2086   { "jbH",              { Jv, XX, cond_jump_flag } },
2087   { "jaeH",             { Jv, XX, cond_jump_flag } },
2088   { "jeH",              { Jv, XX, cond_jump_flag } },
2089   { "jneH",             { Jv, XX, cond_jump_flag } },
2090   { "jbeH",             { Jv, XX, cond_jump_flag } },
2091   { "jaH",              { Jv, XX, cond_jump_flag } },
2092   /* 88 */
2093   { "jsH",              { Jv, XX, cond_jump_flag } },
2094   { "jnsH",             { Jv, XX, cond_jump_flag } },
2095   { "jpH",              { Jv, XX, cond_jump_flag } },
2096   { "jnpH",             { Jv, XX, cond_jump_flag } },
2097   { "jlH",              { Jv, XX, cond_jump_flag } },
2098   { "jgeH",             { Jv, XX, cond_jump_flag } },
2099   { "jleH",             { Jv, XX, cond_jump_flag } },
2100   { "jgH",              { Jv, XX, cond_jump_flag } },
2101   /* 90 */
2102   { "seto",             { Eb } },
2103   { "setno",            { Eb } },
2104   { "setb",             { Eb } },
2105   { "setae",            { Eb } },
2106   { "sete",             { Eb } },
2107   { "setne",            { Eb } },
2108   { "setbe",            { Eb } },
2109   { "seta",             { Eb } },
2110   /* 98 */
2111   { "sets",             { Eb } },
2112   { "setns",            { Eb } },
2113   { "setp",             { Eb } },
2114   { "setnp",            { Eb } },
2115   { "setl",             { Eb } },
2116   { "setge",            { Eb } },
2117   { "setle",            { Eb } },
2118   { "setg",             { Eb } },
2119   /* a0 */
2120   { "pushT",            { fs } },
2121   { "popT",             { fs } },
2122   { "cpuid",            { XX } },
2123   { "btS",              { Ev, Gv } },
2124   { "shldS",            { Ev, Gv, Ib } },
2125   { "shldS",            { Ev, Gv, CL } },
2126   { REG_TABLE (REG_0FA6) },
2127   { REG_TABLE (REG_0FA7) },
2128   /* a8 */
2129   { "pushT",            { gs } },
2130   { "popT",             { gs } },
2131   { "rsm",              { XX } },
2132   { "btsS",             { Ev, Gv } },
2133   { "shrdS",            { Ev, Gv, Ib } },
2134   { "shrdS",            { Ev, Gv, CL } },
2135   { REG_TABLE (REG_0FAE) },
2136   { "imulS",            { Gv, Ev } },
2137   /* b0 */
2138   { "cmpxchgB",         { Eb, Gb } },
2139   { "cmpxchgS",         { Ev, Gv } },
2140   { MOD_TABLE (MOD_0FB2) },
2141   { "btrS",             { Ev, Gv } },
2142   { MOD_TABLE (MOD_0FB4) },
2143   { MOD_TABLE (MOD_0FB5) },
2144   { "movz{bR|x}",       { Gv, Eb } },
2145   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2146   /* b8 */
2147   { PREFIX_TABLE (PREFIX_0FB8) },
2148   { "ud1",              { XX } },
2149   { REG_TABLE (REG_0FBA) },
2150   { "btcS",             { Ev, Gv } },
2151   { PREFIX_TABLE (PREFIX_0FBC) },
2152   { PREFIX_TABLE (PREFIX_0FBD) },
2153   { "movs{bR|x}",       { Gv, Eb } },
2154   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2155   /* c0 */
2156   { "xaddB",            { Eb, Gb } },
2157   { "xaddS",            { Ev, Gv } },
2158   { PREFIX_TABLE (PREFIX_0FC2) },
2159   { PREFIX_TABLE (PREFIX_0FC3) },
2160   { "pinsrw",           { MX, Edqw, Ib } },
2161   { "pextrw",           { Gdq, MS, Ib } },
2162   { "shufpX",           { XM, EXx, Ib } },
2163   { REG_TABLE (REG_0FC7) },
2164   /* c8 */
2165   { "bswap",            { RMeAX } },
2166   { "bswap",            { RMeCX } },
2167   { "bswap",            { RMeDX } },
2168   { "bswap",            { RMeBX } },
2169   { "bswap",            { RMeSP } },
2170   { "bswap",            { RMeBP } },
2171   { "bswap",            { RMeSI } },
2172   { "bswap",            { RMeDI } },
2173   /* d0 */
2174   { PREFIX_TABLE (PREFIX_0FD0) },
2175   { "psrlw",            { MX, EM } },
2176   { "psrld",            { MX, EM } },
2177   { "psrlq",            { MX, EM } },
2178   { "paddq",            { MX, EM } },
2179   { "pmullw",           { MX, EM } },
2180   { PREFIX_TABLE (PREFIX_0FD6) },
2181   { MOD_TABLE (MOD_0FD7) },
2182   /* d8 */
2183   { "psubusb",          { MX, EM } },
2184   { "psubusw",          { MX, EM } },
2185   { "pminub",           { MX, EM } },
2186   { "pand",             { MX, EM } },
2187   { "paddusb",          { MX, EM } },
2188   { "paddusw",          { MX, EM } },
2189   { "pmaxub",           { MX, EM } },
2190   { "pandn",            { MX, EM } },
2191   /* e0 */
2192   { "pavgb",            { MX, EM } },
2193   { "psraw",            { MX, EM } },
2194   { "psrad",            { MX, EM } },
2195   { "pavgw",            { MX, EM } },
2196   { "pmulhuw",          { MX, EM } },
2197   { "pmulhw",           { MX, EM } },
2198   { PREFIX_TABLE (PREFIX_0FE6) },
2199   { PREFIX_TABLE (PREFIX_0FE7) },
2200   /* e8 */
2201   { "psubsb",           { MX, EM } },
2202   { "psubsw",           { MX, EM } },
2203   { "pminsw",           { MX, EM } },
2204   { "por",              { MX, EM } },
2205   { "paddsb",           { MX, EM } },
2206   { "paddsw",           { MX, EM } },
2207   { "pmaxsw",           { MX, EM } },
2208   { "pxor",             { MX, EM } },
2209   /* f0 */
2210   { PREFIX_TABLE (PREFIX_0FF0) },
2211   { "psllw",            { MX, EM } },
2212   { "pslld",            { MX, EM } },
2213   { "psllq",            { MX, EM } },
2214   { "pmuludq",          { MX, EM } },
2215   { "pmaddwd",          { MX, EM } },
2216   { "psadbw",           { MX, EM } },
2217   { PREFIX_TABLE (PREFIX_0FF7) },
2218   /* f8 */
2219   { "psubb",            { MX, EM } },
2220   { "psubw",            { MX, EM } },
2221   { "psubd",            { MX, EM } },
2222   { "psubq",            { MX, EM } },
2223   { "paddb",            { MX, EM } },
2224   { "paddw",            { MX, EM } },
2225   { "paddd",            { MX, EM } },
2226   { Bad_Opcode },
2227 };
2228
2229 static const unsigned char onebyte_has_modrm[256] = {
2230   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2231   /*       -------------------------------        */
2232   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2233   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2234   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2235   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2236   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2237   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2238   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2239   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2240   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2241   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2242   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2243   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2244   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2245   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2246   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2247   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2248   /*       -------------------------------        */
2249   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2250 };
2251
2252 static const unsigned char twobyte_has_modrm[256] = {
2253   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2254   /*       -------------------------------        */
2255   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2256   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2257   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2258   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2259   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2260   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2261   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2262   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2263   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2264   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2265   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2266   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2267   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2268   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2269   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2270   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2271   /*       -------------------------------        */
2272   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2273 };
2274
2275 static char obuf[100];
2276 static char *obufp;
2277 static char *mnemonicendp;
2278 static char scratchbuf[100];
2279 static unsigned char *start_codep;
2280 static unsigned char *insn_codep;
2281 static unsigned char *codep;
2282 static int last_lock_prefix;
2283 static int last_repz_prefix;
2284 static int last_repnz_prefix;
2285 static int last_data_prefix;
2286 static int last_addr_prefix;
2287 static int last_rex_prefix;
2288 static int last_seg_prefix;
2289 #define MAX_CODE_LENGTH 15
2290 /* We can up to 14 prefixes since the maximum instruction length is
2291    15bytes.  */
2292 static int all_prefixes[MAX_CODE_LENGTH - 1];
2293 static disassemble_info *the_info;
2294 static struct
2295   {
2296     int mod;
2297     int reg;
2298     int rm;
2299   }
2300 modrm;
2301 static unsigned char need_modrm;
2302 static struct
2303   {
2304     int scale;
2305     int index;
2306     int base;
2307   }
2308 sib;
2309 static struct
2310   {
2311     int register_specifier;
2312     int length;
2313     int prefix;
2314     int w;
2315   }
2316 vex;
2317 static unsigned char need_vex;
2318 static unsigned char need_vex_reg;
2319 static unsigned char vex_w_done;
2320
2321 struct op
2322   {
2323     const char *name;
2324     unsigned int len;
2325   };
2326
2327 /* If we are accessing mod/rm/reg without need_modrm set, then the
2328    values are stale.  Hitting this abort likely indicates that you
2329    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2330 #define MODRM_CHECK  if (!need_modrm) abort ()
2331
2332 static const char **names64;
2333 static const char **names32;
2334 static const char **names16;
2335 static const char **names8;
2336 static const char **names8rex;
2337 static const char **names_seg;
2338 static const char *index64;
2339 static const char *index32;
2340 static const char **index16;
2341
2342 static const char *intel_names64[] = {
2343   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2344   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2345 };
2346 static const char *intel_names32[] = {
2347   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2348   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2349 };
2350 static const char *intel_names16[] = {
2351   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2352   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2353 };
2354 static const char *intel_names8[] = {
2355   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2356 };
2357 static const char *intel_names8rex[] = {
2358   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2359   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2360 };
2361 static const char *intel_names_seg[] = {
2362   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2363 };
2364 static const char *intel_index64 = "riz";
2365 static const char *intel_index32 = "eiz";
2366 static const char *intel_index16[] = {
2367   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2368 };
2369
2370 static const char *att_names64[] = {
2371   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2372   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2373 };
2374 static const char *att_names32[] = {
2375   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2376   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2377 };
2378 static const char *att_names16[] = {
2379   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2380   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2381 };
2382 static const char *att_names8[] = {
2383   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2384 };
2385 static const char *att_names8rex[] = {
2386   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2387   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2388 };
2389 static const char *att_names_seg[] = {
2390   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2391 };
2392 static const char *att_index64 = "%riz";
2393 static const char *att_index32 = "%eiz";
2394 static const char *att_index16[] = {
2395   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2396 };
2397
2398 static const char **names_mm;
2399 static const char *intel_names_mm[] = {
2400   "mm0", "mm1", "mm2", "mm3",
2401   "mm4", "mm5", "mm6", "mm7"
2402 };
2403 static const char *att_names_mm[] = {
2404   "%mm0", "%mm1", "%mm2", "%mm3",
2405   "%mm4", "%mm5", "%mm6", "%mm7"
2406 };
2407
2408 static const char **names_xmm;
2409 static const char *intel_names_xmm[] = {
2410   "xmm0", "xmm1", "xmm2", "xmm3",
2411   "xmm4", "xmm5", "xmm6", "xmm7",
2412   "xmm8", "xmm9", "xmm10", "xmm11",
2413   "xmm12", "xmm13", "xmm14", "xmm15"
2414 };
2415 static const char *att_names_xmm[] = {
2416   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2417   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2418   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2419   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2420 };
2421
2422 static const char **names_ymm;
2423 static const char *intel_names_ymm[] = {
2424   "ymm0", "ymm1", "ymm2", "ymm3",
2425   "ymm4", "ymm5", "ymm6", "ymm7",
2426   "ymm8", "ymm9", "ymm10", "ymm11",
2427   "ymm12", "ymm13", "ymm14", "ymm15"
2428 };
2429 static const char *att_names_ymm[] = {
2430   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2431   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2432   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2433   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2434 };
2435
2436 static const struct dis386 reg_table[][8] = {
2437   /* REG_80 */
2438   {
2439     { "addA",   { Eb, Ib } },
2440     { "orA",    { Eb, Ib } },
2441     { "adcA",   { Eb, Ib } },
2442     { "sbbA",   { Eb, Ib } },
2443     { "andA",   { Eb, Ib } },
2444     { "subA",   { Eb, Ib } },
2445     { "xorA",   { Eb, Ib } },
2446     { "cmpA",   { Eb, Ib } },
2447   },
2448   /* REG_81 */
2449   {
2450     { "addQ",   { Ev, Iv } },
2451     { "orQ",    { Ev, Iv } },
2452     { "adcQ",   { Ev, Iv } },
2453     { "sbbQ",   { Ev, Iv } },
2454     { "andQ",   { Ev, Iv } },
2455     { "subQ",   { Ev, Iv } },
2456     { "xorQ",   { Ev, Iv } },
2457     { "cmpQ",   { Ev, Iv } },
2458   },
2459   /* REG_82 */
2460   {
2461     { "addQ",   { Ev, sIb } },
2462     { "orQ",    { Ev, sIb } },
2463     { "adcQ",   { Ev, sIb } },
2464     { "sbbQ",   { Ev, sIb } },
2465     { "andQ",   { Ev, sIb } },
2466     { "subQ",   { Ev, sIb } },
2467     { "xorQ",   { Ev, sIb } },
2468     { "cmpQ",   { Ev, sIb } },
2469   },
2470   /* REG_8F */
2471   {
2472     { "popU",   { stackEv } },
2473     { XOP_8F_TABLE (XOP_09) },
2474     { Bad_Opcode },
2475     { Bad_Opcode },
2476     { Bad_Opcode },
2477     { XOP_8F_TABLE (XOP_09) },
2478   },
2479   /* REG_C0 */
2480   {
2481     { "rolA",   { Eb, Ib } },
2482     { "rorA",   { Eb, Ib } },
2483     { "rclA",   { Eb, Ib } },
2484     { "rcrA",   { Eb, Ib } },
2485     { "shlA",   { Eb, Ib } },
2486     { "shrA",   { Eb, Ib } },
2487     { Bad_Opcode },
2488     { "sarA",   { Eb, Ib } },
2489   },
2490   /* REG_C1 */
2491   {
2492     { "rolQ",   { Ev, Ib } },
2493     { "rorQ",   { Ev, Ib } },
2494     { "rclQ",   { Ev, Ib } },
2495     { "rcrQ",   { Ev, Ib } },
2496     { "shlQ",   { Ev, Ib } },
2497     { "shrQ",   { Ev, Ib } },
2498     { Bad_Opcode },
2499     { "sarQ",   { Ev, Ib } },
2500   },
2501   /* REG_C6 */
2502   {
2503     { "movA",   { Eb, Ib } },
2504   },
2505   /* REG_C7 */
2506   {
2507     { "movQ",   { Ev, Iv } },
2508   },
2509   /* REG_D0 */
2510   {
2511     { "rolA",   { Eb, I1 } },
2512     { "rorA",   { Eb, I1 } },
2513     { "rclA",   { Eb, I1 } },
2514     { "rcrA",   { Eb, I1 } },
2515     { "shlA",   { Eb, I1 } },
2516     { "shrA",   { Eb, I1 } },
2517     { Bad_Opcode },
2518     { "sarA",   { Eb, I1 } },
2519   },
2520   /* REG_D1 */
2521   {
2522     { "rolQ",   { Ev, I1 } },
2523     { "rorQ",   { Ev, I1 } },
2524     { "rclQ",   { Ev, I1 } },
2525     { "rcrQ",   { Ev, I1 } },
2526     { "shlQ",   { Ev, I1 } },
2527     { "shrQ",   { Ev, I1 } },
2528     { Bad_Opcode },
2529     { "sarQ",   { Ev, I1 } },
2530   },
2531   /* REG_D2 */
2532   {
2533     { "rolA",   { Eb, CL } },
2534     { "rorA",   { Eb, CL } },
2535     { "rclA",   { Eb, CL } },
2536     { "rcrA",   { Eb, CL } },
2537     { "shlA",   { Eb, CL } },
2538     { "shrA",   { Eb, CL } },
2539     { Bad_Opcode },
2540     { "sarA",   { Eb, CL } },
2541   },
2542   /* REG_D3 */
2543   {
2544     { "rolQ",   { Ev, CL } },
2545     { "rorQ",   { Ev, CL } },
2546     { "rclQ",   { Ev, CL } },
2547     { "rcrQ",   { Ev, CL } },
2548     { "shlQ",   { Ev, CL } },
2549     { "shrQ",   { Ev, CL } },
2550     { Bad_Opcode },
2551     { "sarQ",   { Ev, CL } },
2552   },
2553   /* REG_F6 */
2554   {
2555     { "testA",  { Eb, Ib } },
2556     { Bad_Opcode },
2557     { "notA",   { Eb } },
2558     { "negA",   { Eb } },
2559     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2560     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2561     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2562     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2563   },
2564   /* REG_F7 */
2565   {
2566     { "testQ",  { Ev, Iv } },
2567     { Bad_Opcode },
2568     { "notQ",   { Ev } },
2569     { "negQ",   { Ev } },
2570     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2571     { "imulQ",  { Ev } },
2572     { "divQ",   { Ev } },
2573     { "idivQ",  { Ev } },
2574   },
2575   /* REG_FE */
2576   {
2577     { "incA",   { Eb } },
2578     { "decA",   { Eb } },
2579   },
2580   /* REG_FF */
2581   {
2582     { "incQ",   { Ev } },
2583     { "decQ",   { Ev } },
2584     { "call{T|}", { indirEv } },
2585     { "Jcall{T|}", { indirEp } },
2586     { "jmp{T|}", { indirEv } },
2587     { "Jjmp{T|}", { indirEp } },
2588     { "pushU",  { stackEv } },
2589     { Bad_Opcode },
2590   },
2591   /* REG_0F00 */
2592   {
2593     { "sldtD",  { Sv } },
2594     { "strD",   { Sv } },
2595     { "lldt",   { Ew } },
2596     { "ltr",    { Ew } },
2597     { "verr",   { Ew } },
2598     { "verw",   { Ew } },
2599     { Bad_Opcode },
2600     { Bad_Opcode },
2601   },
2602   /* REG_0F01 */
2603   {
2604     { MOD_TABLE (MOD_0F01_REG_0) },
2605     { MOD_TABLE (MOD_0F01_REG_1) },
2606     { MOD_TABLE (MOD_0F01_REG_2) },
2607     { MOD_TABLE (MOD_0F01_REG_3) },
2608     { "smswD",  { Sv } },
2609     { Bad_Opcode },
2610     { "lmsw",   { Ew } },
2611     { MOD_TABLE (MOD_0F01_REG_7) },
2612   },
2613   /* REG_0F0D */
2614   {
2615     { "prefetch",       { Mb } },
2616     { "prefetchw",      { Mb } },
2617   },
2618   /* REG_0F18 */
2619   {
2620     { MOD_TABLE (MOD_0F18_REG_0) },
2621     { MOD_TABLE (MOD_0F18_REG_1) },
2622     { MOD_TABLE (MOD_0F18_REG_2) },
2623     { MOD_TABLE (MOD_0F18_REG_3) },
2624   },
2625   /* REG_0F71 */
2626   {
2627     { Bad_Opcode },
2628     { Bad_Opcode },
2629     { MOD_TABLE (MOD_0F71_REG_2) },
2630     { Bad_Opcode },
2631     { MOD_TABLE (MOD_0F71_REG_4) },
2632     { Bad_Opcode },
2633     { MOD_TABLE (MOD_0F71_REG_6) },
2634   },
2635   /* REG_0F72 */
2636   {
2637     { Bad_Opcode },
2638     { Bad_Opcode },
2639     { MOD_TABLE (MOD_0F72_REG_2) },
2640     { Bad_Opcode },
2641     { MOD_TABLE (MOD_0F72_REG_4) },
2642     { Bad_Opcode },
2643     { MOD_TABLE (MOD_0F72_REG_6) },
2644   },
2645   /* REG_0F73 */
2646   {
2647     { Bad_Opcode },
2648     { Bad_Opcode },
2649     { MOD_TABLE (MOD_0F73_REG_2) },
2650     { MOD_TABLE (MOD_0F73_REG_3) },
2651     { Bad_Opcode },
2652     { Bad_Opcode },
2653     { MOD_TABLE (MOD_0F73_REG_6) },
2654     { MOD_TABLE (MOD_0F73_REG_7) },
2655   },
2656   /* REG_0FA6 */
2657   {
2658     { "montmul",        { { OP_0f07, 0 } } },
2659     { "xsha1",          { { OP_0f07, 0 } } },
2660     { "xsha256",        { { OP_0f07, 0 } } },
2661   },
2662   /* REG_0FA7 */
2663   {
2664     { "xstore-rng",     { { OP_0f07, 0 } } },
2665     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2666     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2667     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2668     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2669     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2670   },
2671   /* REG_0FAE */
2672   {
2673     { MOD_TABLE (MOD_0FAE_REG_0) },
2674     { MOD_TABLE (MOD_0FAE_REG_1) },
2675     { MOD_TABLE (MOD_0FAE_REG_2) },
2676     { MOD_TABLE (MOD_0FAE_REG_3) },
2677     { MOD_TABLE (MOD_0FAE_REG_4) },
2678     { MOD_TABLE (MOD_0FAE_REG_5) },
2679     { MOD_TABLE (MOD_0FAE_REG_6) },
2680     { MOD_TABLE (MOD_0FAE_REG_7) },
2681   },
2682   /* REG_0FBA */
2683   {
2684     { Bad_Opcode },
2685     { Bad_Opcode },
2686     { Bad_Opcode },
2687     { Bad_Opcode },
2688     { "btQ",    { Ev, Ib } },
2689     { "btsQ",   { Ev, Ib } },
2690     { "btrQ",   { Ev, Ib } },
2691     { "btcQ",   { Ev, Ib } },
2692   },
2693   /* REG_0FC7 */
2694   {
2695     { Bad_Opcode },
2696     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2697     { Bad_Opcode },
2698     { Bad_Opcode },
2699     { Bad_Opcode },
2700     { Bad_Opcode },
2701     { MOD_TABLE (MOD_0FC7_REG_6) },
2702     { MOD_TABLE (MOD_0FC7_REG_7) },
2703   },
2704   /* REG_VEX_0F71 */
2705   {
2706     { Bad_Opcode },
2707     { Bad_Opcode },
2708     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2709     { Bad_Opcode },
2710     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2711     { Bad_Opcode },
2712     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2713   },
2714   /* REG_VEX_0F72 */
2715   {
2716     { Bad_Opcode },
2717     { Bad_Opcode },
2718     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2719     { Bad_Opcode },
2720     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2721     { Bad_Opcode },
2722     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2723   },
2724   /* REG_VEX_0F73 */
2725   {
2726     { Bad_Opcode },
2727     { Bad_Opcode },
2728     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2729     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2730     { Bad_Opcode },
2731     { Bad_Opcode },
2732     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2733     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2734   },
2735   /* REG_VEX_0FAE */
2736   {
2737     { Bad_Opcode },
2738     { Bad_Opcode },
2739     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2740     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2741   },
2742   /* REG_VEX_0F38F3 */
2743   {
2744     { Bad_Opcode },
2745     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2746     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2747     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2748   },
2749   /* REG_XOP_LWPCB */
2750   {
2751     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2752     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2753   },
2754   /* REG_XOP_LWP */
2755   {
2756     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2757     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2758   },
2759   /* REG_XOP_TBM_01 */
2760   {
2761     { Bad_Opcode },
2762     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
2763     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
2764     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
2765     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
2766     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
2767     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
2768     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2769   },
2770   /* REG_XOP_TBM_02 */
2771   {
2772     { Bad_Opcode },
2773     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2774     { Bad_Opcode },
2775     { Bad_Opcode },
2776     { Bad_Opcode },
2777     { Bad_Opcode },
2778     { "blci",   { { OP_LWP_E, 0 }, Ev } },
2779   },
2780 };
2781
2782 static const struct dis386 prefix_table[][4] = {
2783   /* PREFIX_90 */
2784   {
2785     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2786     { "pause", { XX } },
2787     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2788   },
2789
2790   /* PREFIX_0F10 */
2791   {
2792     { "movups", { XM, EXx } },
2793     { "movss",  { XM, EXd } },
2794     { "movupd", { XM, EXx } },
2795     { "movsd",  { XM, EXq } },
2796   },
2797
2798   /* PREFIX_0F11 */
2799   {
2800     { "movups", { EXxS, XM } },
2801     { "movss",  { EXdS, XM } },
2802     { "movupd", { EXxS, XM } },
2803     { "movsd",  { EXqS, XM } },
2804   },
2805
2806   /* PREFIX_0F12 */
2807   {
2808     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2809     { "movsldup", { XM, EXx } },
2810     { "movlpd", { XM, EXq } },
2811     { "movddup", { XM, EXq } },
2812   },
2813
2814   /* PREFIX_0F16 */
2815   {
2816     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2817     { "movshdup", { XM, EXx } },
2818     { "movhpd", { XM, EXq } },
2819   },
2820
2821   /* PREFIX_0F2A */
2822   {
2823     { "cvtpi2ps", { XM, EMCq } },
2824     { "cvtsi2ss%LQ", { XM, Ev } },
2825     { "cvtpi2pd", { XM, EMCq } },
2826     { "cvtsi2sd%LQ", { XM, Ev } },
2827   },
2828
2829   /* PREFIX_0F2B */
2830   {
2831     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2832     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2833     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2834     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2835   },
2836
2837   /* PREFIX_0F2C */
2838   {
2839     { "cvttps2pi", { MXC, EXq } },
2840     { "cvttss2siY", { Gv, EXd } },
2841     { "cvttpd2pi", { MXC, EXx } },
2842     { "cvttsd2siY", { Gv, EXq } },
2843   },
2844
2845   /* PREFIX_0F2D */
2846   {
2847     { "cvtps2pi", { MXC, EXq } },
2848     { "cvtss2siY", { Gv, EXd } },
2849     { "cvtpd2pi", { MXC, EXx } },
2850     { "cvtsd2siY", { Gv, EXq } },
2851   },
2852
2853   /* PREFIX_0F2E */
2854   {
2855     { "ucomiss",{ XM, EXd } },
2856     { Bad_Opcode },
2857     { "ucomisd",{ XM, EXq } },
2858   },
2859
2860   /* PREFIX_0F2F */
2861   {
2862     { "comiss", { XM, EXd } },
2863     { Bad_Opcode },
2864     { "comisd", { XM, EXq } },
2865   },
2866
2867   /* PREFIX_0F51 */
2868   {
2869     { "sqrtps", { XM, EXx } },
2870     { "sqrtss", { XM, EXd } },
2871     { "sqrtpd", { XM, EXx } },
2872     { "sqrtsd", { XM, EXq } },
2873   },
2874
2875   /* PREFIX_0F52 */
2876   {
2877     { "rsqrtps",{ XM, EXx } },
2878     { "rsqrtss",{ XM, EXd } },
2879   },
2880
2881   /* PREFIX_0F53 */
2882   {
2883     { "rcpps",  { XM, EXx } },
2884     { "rcpss",  { XM, EXd } },
2885   },
2886
2887   /* PREFIX_0F58 */
2888   {
2889     { "addps", { XM, EXx } },
2890     { "addss", { XM, EXd } },
2891     { "addpd", { XM, EXx } },
2892     { "addsd", { XM, EXq } },
2893   },
2894
2895   /* PREFIX_0F59 */
2896   {
2897     { "mulps",  { XM, EXx } },
2898     { "mulss",  { XM, EXd } },
2899     { "mulpd",  { XM, EXx } },
2900     { "mulsd",  { XM, EXq } },
2901   },
2902
2903   /* PREFIX_0F5A */
2904   {
2905     { "cvtps2pd", { XM, EXq } },
2906     { "cvtss2sd", { XM, EXd } },
2907     { "cvtpd2ps", { XM, EXx } },
2908     { "cvtsd2ss", { XM, EXq } },
2909   },
2910
2911   /* PREFIX_0F5B */
2912   {
2913     { "cvtdq2ps", { XM, EXx } },
2914     { "cvttps2dq", { XM, EXx } },
2915     { "cvtps2dq", { XM, EXx } },
2916   },
2917
2918   /* PREFIX_0F5C */
2919   {
2920     { "subps",  { XM, EXx } },
2921     { "subss",  { XM, EXd } },
2922     { "subpd",  { XM, EXx } },
2923     { "subsd",  { XM, EXq } },
2924   },
2925
2926   /* PREFIX_0F5D */
2927   {
2928     { "minps",  { XM, EXx } },
2929     { "minss",  { XM, EXd } },
2930     { "minpd",  { XM, EXx } },
2931     { "minsd",  { XM, EXq } },
2932   },
2933
2934   /* PREFIX_0F5E */
2935   {
2936     { "divps",  { XM, EXx } },
2937     { "divss",  { XM, EXd } },
2938     { "divpd",  { XM, EXx } },
2939     { "divsd",  { XM, EXq } },
2940   },
2941
2942   /* PREFIX_0F5F */
2943   {
2944     { "maxps",  { XM, EXx } },
2945     { "maxss",  { XM, EXd } },
2946     { "maxpd",  { XM, EXx } },
2947     { "maxsd",  { XM, EXq } },
2948   },
2949
2950   /* PREFIX_0F60 */
2951   {
2952     { "punpcklbw",{ MX, EMd } },
2953     { Bad_Opcode },
2954     { "punpcklbw",{ MX, EMx } },
2955   },
2956
2957   /* PREFIX_0F61 */
2958   {
2959     { "punpcklwd",{ MX, EMd } },
2960     { Bad_Opcode },
2961     { "punpcklwd",{ MX, EMx } },
2962   },
2963
2964   /* PREFIX_0F62 */
2965   {
2966     { "punpckldq",{ MX, EMd } },
2967     { Bad_Opcode },
2968     { "punpckldq",{ MX, EMx } },
2969   },
2970
2971   /* PREFIX_0F6C */
2972   {
2973     { Bad_Opcode },
2974     { Bad_Opcode },
2975     { "punpcklqdq", { XM, EXx } },
2976   },
2977
2978   /* PREFIX_0F6D */
2979   {
2980     { Bad_Opcode },
2981     { Bad_Opcode },
2982     { "punpckhqdq", { XM, EXx } },
2983   },
2984
2985   /* PREFIX_0F6F */
2986   {
2987     { "movq",   { MX, EM } },
2988     { "movdqu", { XM, EXx } },
2989     { "movdqa", { XM, EXx } },
2990   },
2991
2992   /* PREFIX_0F70 */
2993   {
2994     { "pshufw", { MX, EM, Ib } },
2995     { "pshufhw",{ XM, EXx, Ib } },
2996     { "pshufd", { XM, EXx, Ib } },
2997     { "pshuflw",{ XM, EXx, Ib } },
2998   },
2999
3000   /* PREFIX_0F73_REG_3 */
3001   {
3002     { Bad_Opcode },
3003     { Bad_Opcode },
3004     { "psrldq", { XS, Ib } },
3005   },
3006
3007   /* PREFIX_0F73_REG_7 */
3008   {
3009     { Bad_Opcode },
3010     { Bad_Opcode },
3011     { "pslldq", { XS, Ib } },
3012   },
3013
3014   /* PREFIX_0F78 */
3015   {
3016     {"vmread",  { Em, Gm } },
3017     { Bad_Opcode },
3018     {"extrq",   { XS, Ib, Ib } },
3019     {"insertq", { XM, XS, Ib, Ib } },
3020   },
3021
3022   /* PREFIX_0F79 */
3023   {
3024     {"vmwrite", { Gm, Em } },
3025     { Bad_Opcode },
3026     {"extrq",   { XM, XS } },
3027     {"insertq", { XM, XS } },
3028   },
3029
3030   /* PREFIX_0F7C */
3031   {
3032     { Bad_Opcode },
3033     { Bad_Opcode },
3034     { "haddpd", { XM, EXx } },
3035     { "haddps", { XM, EXx } },
3036   },
3037
3038   /* PREFIX_0F7D */
3039   {
3040     { Bad_Opcode },
3041     { Bad_Opcode },
3042     { "hsubpd", { XM, EXx } },
3043     { "hsubps", { XM, EXx } },
3044   },
3045
3046   /* PREFIX_0F7E */
3047   {
3048     { "movK",   { Edq, MX } },
3049     { "movq",   { XM, EXq } },
3050     { "movK",   { Edq, XM } },
3051   },
3052
3053   /* PREFIX_0F7F */
3054   {
3055     { "movq",   { EMS, MX } },
3056     { "movdqu", { EXxS, XM } },
3057     { "movdqa", { EXxS, XM } },
3058   },
3059
3060   /* PREFIX_0FAE_REG_0 */
3061   {
3062     { Bad_Opcode },
3063     { "rdfsbase", { Ev } },
3064   },
3065
3066   /* PREFIX_0FAE_REG_1 */
3067   {
3068     { Bad_Opcode },
3069     { "rdgsbase", { Ev } },
3070   },
3071
3072   /* PREFIX_0FAE_REG_2 */
3073   {
3074     { Bad_Opcode },
3075     { "wrfsbase", { Ev } },
3076   },
3077
3078   /* PREFIX_0FAE_REG_3 */
3079   {
3080     { Bad_Opcode },
3081     { "wrgsbase", { Ev } },
3082   },
3083
3084   /* PREFIX_0FB8 */
3085   {
3086     { Bad_Opcode },
3087     { "popcntS", { Gv, Ev } },
3088   },
3089
3090   /* PREFIX_0FBC */
3091   {
3092     { "bsfS",   { Gv, Ev } },
3093     { "tzcntS", { Gv, Ev } },
3094     { "bsfS",   { Gv, Ev } },
3095   },
3096
3097   /* PREFIX_0FBD */
3098   {
3099     { "bsrS",   { Gv, Ev } },
3100     { "lzcntS", { Gv, Ev } },
3101     { "bsrS",   { Gv, Ev } },
3102   },
3103
3104   /* PREFIX_0FC2 */
3105   {
3106     { "cmpps",  { XM, EXx, CMP } },
3107     { "cmpss",  { XM, EXd, CMP } },
3108     { "cmppd",  { XM, EXx, CMP } },
3109     { "cmpsd",  { XM, EXq, CMP } },
3110   },
3111
3112   /* PREFIX_0FC3 */
3113   {
3114     { "movntiS", { Ma, Gv } },
3115   },
3116
3117   /* PREFIX_0FC7_REG_6 */
3118   {
3119     { "vmptrld",{ Mq } },
3120     { "vmxon",  { Mq } },
3121     { "vmclear",{ Mq } },
3122   },
3123
3124   /* PREFIX_0FD0 */
3125   {
3126     { Bad_Opcode },
3127     { Bad_Opcode },
3128     { "addsubpd", { XM, EXx } },
3129     { "addsubps", { XM, EXx } },
3130   },
3131
3132   /* PREFIX_0FD6 */
3133   {
3134     { Bad_Opcode },
3135     { "movq2dq",{ XM, MS } },
3136     { "movq",   { EXqS, XM } },
3137     { "movdq2q",{ MX, XS } },
3138   },
3139
3140   /* PREFIX_0FE6 */
3141   {
3142     { Bad_Opcode },
3143     { "cvtdq2pd", { XM, EXq } },
3144     { "cvttpd2dq", { XM, EXx } },
3145     { "cvtpd2dq", { XM, EXx } },
3146   },
3147
3148   /* PREFIX_0FE7 */
3149   {
3150     { "movntq", { Mq, MX } },
3151     { Bad_Opcode },
3152     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3153   },
3154
3155   /* PREFIX_0FF0 */
3156   {
3157     { Bad_Opcode },
3158     { Bad_Opcode },
3159     { Bad_Opcode },
3160     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3161   },
3162
3163   /* PREFIX_0FF7 */
3164   {
3165     { "maskmovq", { MX, MS } },
3166     { Bad_Opcode },
3167     { "maskmovdqu", { XM, XS } },
3168   },
3169
3170   /* PREFIX_0F3810 */
3171   {
3172     { Bad_Opcode },
3173     { Bad_Opcode },
3174     { "pblendvb", { XM, EXx, XMM0 } },
3175   },
3176
3177   /* PREFIX_0F3814 */
3178   {
3179     { Bad_Opcode },
3180     { Bad_Opcode },
3181     { "blendvps", { XM, EXx, XMM0 } },
3182   },
3183
3184   /* PREFIX_0F3815 */
3185   {
3186     { Bad_Opcode },
3187     { Bad_Opcode },
3188     { "blendvpd", { XM, EXx, XMM0 } },
3189   },
3190
3191   /* PREFIX_0F3817 */
3192   {
3193     { Bad_Opcode },
3194     { Bad_Opcode },
3195     { "ptest",  { XM, EXx } },
3196   },
3197
3198   /* PREFIX_0F3820 */
3199   {
3200     { Bad_Opcode },
3201     { Bad_Opcode },
3202     { "pmovsxbw", { XM, EXq } },
3203   },
3204
3205   /* PREFIX_0F3821 */
3206   {
3207     { Bad_Opcode },
3208     { Bad_Opcode },
3209     { "pmovsxbd", { XM, EXd } },
3210   },
3211
3212   /* PREFIX_0F3822 */
3213   {
3214     { Bad_Opcode },
3215     { Bad_Opcode },
3216     { "pmovsxbq", { XM, EXw } },
3217   },
3218
3219   /* PREFIX_0F3823 */
3220   {
3221     { Bad_Opcode },
3222     { Bad_Opcode },
3223     { "pmovsxwd", { XM, EXq } },
3224   },
3225
3226   /* PREFIX_0F3824 */
3227   {
3228     { Bad_Opcode },
3229     { Bad_Opcode },
3230     { "pmovsxwq", { XM, EXd } },
3231   },
3232
3233   /* PREFIX_0F3825 */
3234   {
3235     { Bad_Opcode },
3236     { Bad_Opcode },
3237     { "pmovsxdq", { XM, EXq } },
3238   },
3239
3240   /* PREFIX_0F3828 */
3241   {
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { "pmuldq", { XM, EXx } },
3245   },
3246
3247   /* PREFIX_0F3829 */
3248   {
3249     { Bad_Opcode },
3250     { Bad_Opcode },
3251     { "pcmpeqq", { XM, EXx } },
3252   },
3253
3254   /* PREFIX_0F382A */
3255   {
3256     { Bad_Opcode },
3257     { Bad_Opcode },
3258     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3259   },
3260
3261   /* PREFIX_0F382B */
3262   {
3263     { Bad_Opcode },
3264     { Bad_Opcode },
3265     { "packusdw", { XM, EXx } },
3266   },
3267
3268   /* PREFIX_0F3830 */
3269   {
3270     { Bad_Opcode },
3271     { Bad_Opcode },
3272     { "pmovzxbw", { XM, EXq } },
3273   },
3274
3275   /* PREFIX_0F3831 */
3276   {
3277     { Bad_Opcode },
3278     { Bad_Opcode },
3279     { "pmovzxbd", { XM, EXd } },
3280   },
3281
3282   /* PREFIX_0F3832 */
3283   {
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { "pmovzxbq", { XM, EXw } },
3287   },
3288
3289   /* PREFIX_0F3833 */
3290   {
3291     { Bad_Opcode },
3292     { Bad_Opcode },
3293     { "pmovzxwd", { XM, EXq } },
3294   },
3295
3296   /* PREFIX_0F3834 */
3297   {
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { "pmovzxwq", { XM, EXd } },
3301   },
3302
3303   /* PREFIX_0F3835 */
3304   {
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { "pmovzxdq", { XM, EXq } },
3308   },
3309
3310   /* PREFIX_0F3837 */
3311   {
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { "pcmpgtq", { XM, EXx } },
3315   },
3316
3317   /* PREFIX_0F3838 */
3318   {
3319     { Bad_Opcode },
3320     { Bad_Opcode },
3321     { "pminsb", { XM, EXx } },
3322   },
3323
3324   /* PREFIX_0F3839 */
3325   {
3326     { Bad_Opcode },
3327     { Bad_Opcode },
3328     { "pminsd", { XM, EXx } },
3329   },
3330
3331   /* PREFIX_0F383A */
3332   {
3333     { Bad_Opcode },
3334     { Bad_Opcode },
3335     { "pminuw", { XM, EXx } },
3336   },
3337
3338   /* PREFIX_0F383B */
3339   {
3340     { Bad_Opcode },
3341     { Bad_Opcode },
3342     { "pminud", { XM, EXx } },
3343   },
3344
3345   /* PREFIX_0F383C */
3346   {
3347     { Bad_Opcode },
3348     { Bad_Opcode },
3349     { "pmaxsb", { XM, EXx } },
3350   },
3351
3352   /* PREFIX_0F383D */
3353   {
3354     { Bad_Opcode },
3355     { Bad_Opcode },
3356     { "pmaxsd", { XM, EXx } },
3357   },
3358
3359   /* PREFIX_0F383E */
3360   {
3361     { Bad_Opcode },
3362     { Bad_Opcode },
3363     { "pmaxuw", { XM, EXx } },
3364   },
3365
3366   /* PREFIX_0F383F */
3367   {
3368     { Bad_Opcode },
3369     { Bad_Opcode },
3370     { "pmaxud", { XM, EXx } },
3371   },
3372
3373   /* PREFIX_0F3840 */
3374   {
3375     { Bad_Opcode },
3376     { Bad_Opcode },
3377     { "pmulld", { XM, EXx } },
3378   },
3379
3380   /* PREFIX_0F3841 */
3381   {
3382     { Bad_Opcode },
3383     { Bad_Opcode },
3384     { "phminposuw", { XM, EXx } },
3385   },
3386
3387   /* PREFIX_0F3880 */
3388   {
3389     { Bad_Opcode },
3390     { Bad_Opcode },
3391     { "invept", { Gm, Mo } },
3392   },
3393
3394   /* PREFIX_0F3881 */
3395   {
3396     { Bad_Opcode },
3397     { Bad_Opcode },
3398     { "invvpid", { Gm, Mo } },
3399   },
3400
3401   /* PREFIX_0F3882 */
3402   {
3403     { Bad_Opcode },
3404     { Bad_Opcode },
3405     { "invpcid", { Gm, M } },
3406   },
3407
3408   /* PREFIX_0F38DB */
3409   {
3410     { Bad_Opcode },
3411     { Bad_Opcode },
3412     { "aesimc", { XM, EXx } },
3413   },
3414
3415   /* PREFIX_0F38DC */
3416   {
3417     { Bad_Opcode },
3418     { Bad_Opcode },
3419     { "aesenc", { XM, EXx } },
3420   },
3421
3422   /* PREFIX_0F38DD */
3423   {
3424     { Bad_Opcode },
3425     { Bad_Opcode },
3426     { "aesenclast", { XM, EXx } },
3427   },
3428
3429   /* PREFIX_0F38DE */
3430   {
3431     { Bad_Opcode },
3432     { Bad_Opcode },
3433     { "aesdec", { XM, EXx } },
3434   },
3435
3436   /* PREFIX_0F38DF */
3437   {
3438     { Bad_Opcode },
3439     { Bad_Opcode },
3440     { "aesdeclast", { XM, EXx } },
3441   },
3442
3443   /* PREFIX_0F38F0 */
3444   {
3445     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3446     { Bad_Opcode },
3447     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3448     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3449   },
3450
3451   /* PREFIX_0F38F1 */
3452   {
3453     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3454     { Bad_Opcode },
3455     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3456     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3457   },
3458
3459   /* PREFIX_0F3A08 */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { "roundps", { XM, EXx, Ib } },
3464   },
3465
3466   /* PREFIX_0F3A09 */
3467   {
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { "roundpd", { XM, EXx, Ib } },
3471   },
3472
3473   /* PREFIX_0F3A0A */
3474   {
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { "roundss", { XM, EXd, Ib } },
3478   },
3479
3480   /* PREFIX_0F3A0B */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { "roundsd", { XM, EXq, Ib } },
3485   },
3486
3487   /* PREFIX_0F3A0C */
3488   {
3489     { Bad_Opcode },
3490     { Bad_Opcode },
3491     { "blendps", { XM, EXx, Ib } },
3492   },
3493
3494   /* PREFIX_0F3A0D */
3495   {
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { "blendpd", { XM, EXx, Ib } },
3499   },
3500
3501   /* PREFIX_0F3A0E */
3502   {
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { "pblendw", { XM, EXx, Ib } },
3506   },
3507
3508   /* PREFIX_0F3A14 */
3509   {
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { "pextrb", { Edqb, XM, Ib } },
3513   },
3514
3515   /* PREFIX_0F3A15 */
3516   {
3517     { Bad_Opcode },
3518     { Bad_Opcode },
3519     { "pextrw", { Edqw, XM, Ib } },
3520   },
3521
3522   /* PREFIX_0F3A16 */
3523   {
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { "pextrK", { Edq, XM, Ib } },
3527   },
3528
3529   /* PREFIX_0F3A17 */
3530   {
3531     { Bad_Opcode },
3532     { Bad_Opcode },
3533     { "extractps", { Edqd, XM, Ib } },
3534   },
3535
3536   /* PREFIX_0F3A20 */
3537   {
3538     { Bad_Opcode },
3539     { Bad_Opcode },
3540     { "pinsrb", { XM, Edqb, Ib } },
3541   },
3542
3543   /* PREFIX_0F3A21 */
3544   {
3545     { Bad_Opcode },
3546     { Bad_Opcode },
3547     { "insertps", { XM, EXd, Ib } },
3548   },
3549
3550   /* PREFIX_0F3A22 */
3551   {
3552     { Bad_Opcode },
3553     { Bad_Opcode },
3554     { "pinsrK", { XM, Edq, Ib } },
3555   },
3556
3557   /* PREFIX_0F3A40 */
3558   {
3559     { Bad_Opcode },
3560     { Bad_Opcode },
3561     { "dpps",   { XM, EXx, Ib } },
3562   },
3563
3564   /* PREFIX_0F3A41 */
3565   {
3566     { Bad_Opcode },
3567     { Bad_Opcode },
3568     { "dppd",   { XM, EXx, Ib } },
3569   },
3570
3571   /* PREFIX_0F3A42 */
3572   {
3573     { Bad_Opcode },
3574     { Bad_Opcode },
3575     { "mpsadbw", { XM, EXx, Ib } },
3576   },
3577
3578   /* PREFIX_0F3A44 */
3579   {
3580     { Bad_Opcode },
3581     { Bad_Opcode },
3582     { "pclmulqdq", { XM, EXx, PCLMUL } },
3583   },
3584
3585   /* PREFIX_0F3A60 */
3586   {
3587     { Bad_Opcode },
3588     { Bad_Opcode },
3589     { "pcmpestrm", { XM, EXx, Ib } },
3590   },
3591
3592   /* PREFIX_0F3A61 */
3593   {
3594     { Bad_Opcode },
3595     { Bad_Opcode },
3596     { "pcmpestri", { XM, EXx, Ib } },
3597   },
3598
3599   /* PREFIX_0F3A62 */
3600   {
3601     { Bad_Opcode },
3602     { Bad_Opcode },
3603     { "pcmpistrm", { XM, EXx, Ib } },
3604   },
3605
3606   /* PREFIX_0F3A63 */
3607   {
3608     { Bad_Opcode },
3609     { Bad_Opcode },
3610     { "pcmpistri", { XM, EXx, Ib } },
3611   },
3612
3613   /* PREFIX_0F3ADF */
3614   {
3615     { Bad_Opcode },
3616     { Bad_Opcode },
3617     { "aeskeygenassist", { XM, EXx, Ib } },
3618   },
3619
3620   /* PREFIX_VEX_0F10 */
3621   {
3622     { VEX_W_TABLE (VEX_W_0F10_P_0) },
3623     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3624     { VEX_W_TABLE (VEX_W_0F10_P_2) },
3625     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3626   },
3627
3628   /* PREFIX_VEX_0F11 */
3629   {
3630     { VEX_W_TABLE (VEX_W_0F11_P_0) },
3631     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3632     { VEX_W_TABLE (VEX_W_0F11_P_2) },
3633     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3634   },
3635
3636   /* PREFIX_VEX_0F12 */
3637   {
3638     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3639     { VEX_W_TABLE (VEX_W_0F12_P_1) },
3640     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3641     { VEX_W_TABLE (VEX_W_0F12_P_3) },
3642   },
3643
3644   /* PREFIX_VEX_0F16 */
3645   {
3646     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3647     { VEX_W_TABLE (VEX_W_0F16_P_1) },
3648     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3649   },
3650
3651   /* PREFIX_VEX_0F2A */
3652   {
3653     { Bad_Opcode },
3654     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3655     { Bad_Opcode },
3656     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3657   },
3658
3659   /* PREFIX_VEX_0F2C */
3660   {
3661     { Bad_Opcode },
3662     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3663     { Bad_Opcode },
3664     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3665   },
3666
3667   /* PREFIX_VEX_0F2D */
3668   {
3669     { Bad_Opcode },
3670     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3671     { Bad_Opcode },
3672     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3673   },
3674
3675   /* PREFIX_VEX_0F2E */
3676   {
3677     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3678     { Bad_Opcode },
3679     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3680   },
3681
3682   /* PREFIX_VEX_0F2F */
3683   {
3684     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3685     { Bad_Opcode },
3686     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3687   },
3688
3689   /* PREFIX_VEX_0F51 */
3690   {
3691     { VEX_W_TABLE (VEX_W_0F51_P_0) },
3692     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3693     { VEX_W_TABLE (VEX_W_0F51_P_2) },
3694     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3695   },
3696
3697   /* PREFIX_VEX_0F52 */
3698   {
3699     { VEX_W_TABLE (VEX_W_0F52_P_0) },
3700     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3701   },
3702
3703   /* PREFIX_VEX_0F53 */
3704   {
3705     { VEX_W_TABLE (VEX_W_0F53_P_0) },
3706     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3707   },
3708
3709   /* PREFIX_VEX_0F58 */
3710   {
3711     { VEX_W_TABLE (VEX_W_0F58_P_0) },
3712     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3713     { VEX_W_TABLE (VEX_W_0F58_P_2) },
3714     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3715   },
3716
3717   /* PREFIX_VEX_0F59 */
3718   {
3719     { VEX_W_TABLE (VEX_W_0F59_P_0) },
3720     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3721     { VEX_W_TABLE (VEX_W_0F59_P_2) },
3722     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3723   },
3724
3725   /* PREFIX_VEX_0F5A */
3726   {
3727     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3728     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3729     { "vcvtpd2ps%XY", { XMM, EXx } },
3730     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3731   },
3732
3733   /* PREFIX_VEX_0F5B */
3734   {
3735     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3736     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3737     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3738   },
3739
3740   /* PREFIX_VEX_0F5C */
3741   {
3742     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3743     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3744     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3745     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3746   },
3747
3748   /* PREFIX_VEX_0F5D */
3749   {
3750     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3751     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3752     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3753     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3754   },
3755
3756   /* PREFIX_VEX_0F5E */
3757   {
3758     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3759     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3760     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3761     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3762   },
3763
3764   /* PREFIX_VEX_0F5F */
3765   {
3766     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3767     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3768     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3769     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3770   },
3771
3772   /* PREFIX_VEX_0F60 */
3773   {
3774     { Bad_Opcode },
3775     { Bad_Opcode },
3776     { VEX_W_TABLE (VEX_W_0F60_P_2) },
3777   },
3778
3779   /* PREFIX_VEX_0F61 */
3780   {
3781     { Bad_Opcode },
3782     { Bad_Opcode },
3783     { VEX_W_TABLE (VEX_W_0F61_P_2) },
3784   },
3785
3786   /* PREFIX_VEX_0F62 */
3787   {
3788     { Bad_Opcode },
3789     { Bad_Opcode },
3790     { VEX_W_TABLE (VEX_W_0F62_P_2) },
3791   },
3792
3793   /* PREFIX_VEX_0F63 */
3794   {
3795     { Bad_Opcode },
3796     { Bad_Opcode },
3797     { VEX_W_TABLE (VEX_W_0F63_P_2) },
3798   },
3799
3800   /* PREFIX_VEX_0F64 */
3801   {
3802     { Bad_Opcode },
3803     { Bad_Opcode },
3804     { VEX_W_TABLE (VEX_W_0F64_P_2) },
3805   },
3806
3807   /* PREFIX_VEX_0F65 */
3808   {
3809     { Bad_Opcode },
3810     { Bad_Opcode },
3811     { VEX_W_TABLE (VEX_W_0F65_P_2) },
3812   },
3813
3814   /* PREFIX_VEX_0F66 */
3815   {
3816     { Bad_Opcode },
3817     { Bad_Opcode },
3818     { VEX_W_TABLE (VEX_W_0F66_P_2) },
3819   },
3820
3821   /* PREFIX_VEX_0F67 */
3822   {
3823     { Bad_Opcode },
3824     { Bad_Opcode },
3825     { VEX_W_TABLE (VEX_W_0F67_P_2) },
3826   },
3827
3828   /* PREFIX_VEX_0F68 */
3829   {
3830     { Bad_Opcode },
3831     { Bad_Opcode },
3832     { VEX_W_TABLE (VEX_W_0F68_P_2) },
3833   },
3834
3835   /* PREFIX_VEX_0F69 */
3836   {
3837     { Bad_Opcode },
3838     { Bad_Opcode },
3839     { VEX_W_TABLE (VEX_W_0F69_P_2) },
3840   },
3841
3842   /* PREFIX_VEX_0F6A */
3843   {
3844     { Bad_Opcode },
3845     { Bad_Opcode },
3846     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
3847   },
3848
3849   /* PREFIX_VEX_0F6B */
3850   {
3851     { Bad_Opcode },
3852     { Bad_Opcode },
3853     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
3854   },
3855
3856   /* PREFIX_VEX_0F6C */
3857   {
3858     { Bad_Opcode },
3859     { Bad_Opcode },
3860     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
3861   },
3862
3863   /* PREFIX_VEX_0F6D */
3864   {
3865     { Bad_Opcode },
3866     { Bad_Opcode },
3867     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
3868   },
3869
3870   /* PREFIX_VEX_0F6E */
3871   {
3872     { Bad_Opcode },
3873     { Bad_Opcode },
3874     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3875   },
3876
3877   /* PREFIX_VEX_0F6F */
3878   {
3879     { Bad_Opcode },
3880     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3881     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3882   },
3883
3884   /* PREFIX_VEX_0F70 */
3885   {
3886     { Bad_Opcode },
3887     { VEX_W_TABLE (VEX_W_0F70_P_1) },
3888     { VEX_W_TABLE (VEX_W_0F70_P_2) },
3889     { VEX_W_TABLE (VEX_W_0F70_P_3) },
3890   },
3891
3892   /* PREFIX_VEX_0F71_REG_2 */
3893   {
3894     { Bad_Opcode },
3895     { Bad_Opcode },
3896     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
3897   },
3898
3899   /* PREFIX_VEX_0F71_REG_4 */
3900   {
3901     { Bad_Opcode },
3902     { Bad_Opcode },
3903     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
3904   },
3905
3906   /* PREFIX_VEX_0F71_REG_6 */
3907   {
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
3911   },
3912
3913   /* PREFIX_VEX_0F72_REG_2 */
3914   {
3915     { Bad_Opcode },
3916     { Bad_Opcode },
3917     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
3918   },
3919
3920   /* PREFIX_VEX_0F72_REG_4 */
3921   {
3922     { Bad_Opcode },
3923     { Bad_Opcode },
3924     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
3925   },
3926
3927   /* PREFIX_VEX_0F72_REG_6 */
3928   {
3929     { Bad_Opcode },
3930     { Bad_Opcode },
3931     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
3932   },
3933
3934   /* PREFIX_VEX_0F73_REG_2 */
3935   {
3936     { Bad_Opcode },
3937     { Bad_Opcode },
3938     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
3939   },
3940
3941   /* PREFIX_VEX_0F73_REG_3 */
3942   {
3943     { Bad_Opcode },
3944     { Bad_Opcode },
3945     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
3946   },
3947
3948   /* PREFIX_VEX_0F73_REG_6 */
3949   {
3950     { Bad_Opcode },
3951     { Bad_Opcode },
3952     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
3953   },
3954
3955   /* PREFIX_VEX_0F73_REG_7 */
3956   {
3957     { Bad_Opcode },
3958     { Bad_Opcode },
3959     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
3960   },
3961
3962   /* PREFIX_VEX_0F74 */
3963   {
3964     { Bad_Opcode },
3965     { Bad_Opcode },
3966     { VEX_W_TABLE (VEX_W_0F74_P_2) },
3967   },
3968
3969   /* PREFIX_VEX_0F75 */
3970   {
3971     { Bad_Opcode },
3972     { Bad_Opcode },
3973     { VEX_W_TABLE (VEX_W_0F75_P_2) },
3974   },
3975
3976   /* PREFIX_VEX_0F76 */
3977   {
3978     { Bad_Opcode },
3979     { Bad_Opcode },
3980     { VEX_W_TABLE (VEX_W_0F76_P_2) },
3981   },
3982
3983   /* PREFIX_VEX_0F77 */
3984   {
3985     { VEX_W_TABLE (VEX_W_0F77_P_0) },
3986   },
3987
3988   /* PREFIX_VEX_0F7C */
3989   {
3990     { Bad_Opcode },
3991     { Bad_Opcode },
3992     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
3993     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
3994   },
3995
3996   /* PREFIX_VEX_0F7D */
3997   {
3998     { Bad_Opcode },
3999     { Bad_Opcode },
4000     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4001     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4002   },
4003
4004   /* PREFIX_VEX_0F7E */
4005   {
4006     { Bad_Opcode },
4007     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4008     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4009   },
4010
4011   /* PREFIX_VEX_0F7F */
4012   {
4013     { Bad_Opcode },
4014     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4015     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4016   },
4017
4018   /* PREFIX_VEX_0FC2 */
4019   {
4020     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4021     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4022     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4023     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4024   },
4025
4026   /* PREFIX_VEX_0FC4 */
4027   {
4028     { Bad_Opcode },
4029     { Bad_Opcode },
4030     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4031   },
4032
4033   /* PREFIX_VEX_0FC5 */
4034   {
4035     { Bad_Opcode },
4036     { Bad_Opcode },
4037     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4038   },
4039
4040   /* PREFIX_VEX_0FD0 */
4041   {
4042     { Bad_Opcode },
4043     { Bad_Opcode },
4044     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4045     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4046   },
4047
4048   /* PREFIX_VEX_0FD1 */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4053   },
4054
4055   /* PREFIX_VEX_0FD2 */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4060   },
4061
4062   /* PREFIX_VEX_0FD3 */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4067   },
4068
4069   /* PREFIX_VEX_0FD4 */
4070   {
4071     { Bad_Opcode },
4072     { Bad_Opcode },
4073     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4074   },
4075
4076   /* PREFIX_VEX_0FD5 */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4081   },
4082
4083   /* PREFIX_VEX_0FD6 */
4084   {
4085     { Bad_Opcode },
4086     { Bad_Opcode },
4087     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4088   },
4089
4090   /* PREFIX_VEX_0FD7 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4095   },
4096
4097   /* PREFIX_VEX_0FD8 */
4098   {
4099     { Bad_Opcode },
4100     { Bad_Opcode },
4101     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4102   },
4103
4104   /* PREFIX_VEX_0FD9 */
4105   {
4106     { Bad_Opcode },
4107     { Bad_Opcode },
4108     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4109   },
4110
4111   /* PREFIX_VEX_0FDA */
4112   {
4113     { Bad_Opcode },
4114     { Bad_Opcode },
4115     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4116   },
4117
4118   /* PREFIX_VEX_0FDB */
4119   {
4120     { Bad_Opcode },
4121     { Bad_Opcode },
4122     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4123   },
4124
4125   /* PREFIX_VEX_0FDC */
4126   {
4127     { Bad_Opcode },
4128     { Bad_Opcode },
4129     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4130   },
4131
4132   /* PREFIX_VEX_0FDD */
4133   {
4134     { Bad_Opcode },
4135     { Bad_Opcode },
4136     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4137   },
4138
4139   /* PREFIX_VEX_0FDE */
4140   {
4141     { Bad_Opcode },
4142     { Bad_Opcode },
4143     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4144   },
4145
4146   /* PREFIX_VEX_0FDF */
4147   {
4148     { Bad_Opcode },
4149     { Bad_Opcode },
4150     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4151   },
4152
4153   /* PREFIX_VEX_0FE0 */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4158   },
4159
4160   /* PREFIX_VEX_0FE1 */
4161   {
4162     { Bad_Opcode },
4163     { Bad_Opcode },
4164     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4165   },
4166
4167   /* PREFIX_VEX_0FE2 */
4168   {
4169     { Bad_Opcode },
4170     { Bad_Opcode },
4171     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4172   },
4173
4174   /* PREFIX_VEX_0FE3 */
4175   {
4176     { Bad_Opcode },
4177     { Bad_Opcode },
4178     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4179   },
4180
4181   /* PREFIX_VEX_0FE4 */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4186   },
4187
4188   /* PREFIX_VEX_0FE5 */
4189   {
4190     { Bad_Opcode },
4191     { Bad_Opcode },
4192     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4193   },
4194
4195   /* PREFIX_VEX_0FE6 */
4196   {
4197     { Bad_Opcode },
4198     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4199     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4200     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4201   },
4202
4203   /* PREFIX_VEX_0FE7 */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4208   },
4209
4210   /* PREFIX_VEX_0FE8 */
4211   {
4212     { Bad_Opcode },
4213     { Bad_Opcode },
4214     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4215   },
4216
4217   /* PREFIX_VEX_0FE9 */
4218   {
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
4222   },
4223
4224   /* PREFIX_VEX_0FEA */
4225   {
4226     { Bad_Opcode },
4227     { Bad_Opcode },
4228     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
4229   },
4230
4231   /* PREFIX_VEX_0FEB */
4232   {
4233     { Bad_Opcode },
4234     { Bad_Opcode },
4235     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
4236   },
4237
4238   /* PREFIX_VEX_0FEC */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
4243   },
4244
4245   /* PREFIX_VEX_0FED */
4246   {
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { VEX_W_TABLE (VEX_W_0FED_P_2) },
4250   },
4251
4252   /* PREFIX_VEX_0FEE */
4253   {
4254     { Bad_Opcode },
4255     { Bad_Opcode },
4256     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
4257   },
4258
4259   /* PREFIX_VEX_0FEF */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
4264   },
4265
4266   /* PREFIX_VEX_0FF0 */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4272   },
4273
4274   /* PREFIX_VEX_0FF1 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
4279   },
4280
4281   /* PREFIX_VEX_0FF2 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
4286   },
4287
4288   /* PREFIX_VEX_0FF3 */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
4293   },
4294
4295   /* PREFIX_VEX_0FF4 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
4300   },
4301
4302   /* PREFIX_VEX_0FF5 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
4307   },
4308
4309   /* PREFIX_VEX_0FF6 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
4314   },
4315
4316   /* PREFIX_VEX_0FF7 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4321   },
4322
4323   /* PREFIX_VEX_0FF8 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
4328   },
4329
4330   /* PREFIX_VEX_0FF9 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
4335   },
4336
4337   /* PREFIX_VEX_0FFA */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
4342   },
4343
4344   /* PREFIX_VEX_0FFB */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
4349   },
4350
4351   /* PREFIX_VEX_0FFC */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
4356   },
4357
4358   /* PREFIX_VEX_0FFD */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
4363   },
4364
4365   /* PREFIX_VEX_0FFE */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
4370   },
4371
4372   /* PREFIX_VEX_0F3800 */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
4377   },
4378
4379   /* PREFIX_VEX_0F3801 */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
4384   },
4385
4386   /* PREFIX_VEX_0F3802 */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
4391   },
4392
4393   /* PREFIX_VEX_0F3803 */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
4398   },
4399
4400   /* PREFIX_VEX_0F3804 */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
4405   },
4406
4407   /* PREFIX_VEX_0F3805 */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
4412   },
4413
4414   /* PREFIX_VEX_0F3806 */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
4419   },
4420
4421   /* PREFIX_VEX_0F3807 */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
4426   },
4427
4428   /* PREFIX_VEX_0F3808 */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
4433   },
4434
4435   /* PREFIX_VEX_0F3809 */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
4440   },
4441
4442   /* PREFIX_VEX_0F380A */
4443   {
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
4447   },
4448
4449   /* PREFIX_VEX_0F380B */
4450   {
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
4454   },
4455
4456   /* PREFIX_VEX_0F380C */
4457   {
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4461   },
4462
4463   /* PREFIX_VEX_0F380D */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4468   },
4469
4470   /* PREFIX_VEX_0F380E */
4471   {
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4475   },
4476
4477   /* PREFIX_VEX_0F380F */
4478   {
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4482   },
4483
4484   /* PREFIX_VEX_0F3813 */
4485   {
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { "vcvtph2ps", { XM, EXxmmq } },
4489   },
4490
4491   /* PREFIX_VEX_0F3816 */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
4496   },
4497
4498   /* PREFIX_VEX_0F3817 */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4503   },
4504
4505   /* PREFIX_VEX_0F3818 */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
4510   },
4511
4512   /* PREFIX_VEX_0F3819 */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
4517   },
4518
4519   /* PREFIX_VEX_0F381A */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4524   },
4525
4526   /* PREFIX_VEX_0F381C */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
4531   },
4532
4533   /* PREFIX_VEX_0F381D */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
4538   },
4539
4540   /* PREFIX_VEX_0F381E */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
4545   },
4546
4547   /* PREFIX_VEX_0F3820 */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
4552   },
4553
4554   /* PREFIX_VEX_0F3821 */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
4559   },
4560
4561   /* PREFIX_VEX_0F3822 */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
4566   },
4567
4568   /* PREFIX_VEX_0F3823 */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
4573   },
4574
4575   /* PREFIX_VEX_0F3824 */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
4580   },
4581
4582   /* PREFIX_VEX_0F3825 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
4587   },
4588
4589   /* PREFIX_VEX_0F3828 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
4594   },
4595
4596   /* PREFIX_VEX_0F3829 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
4601   },
4602
4603   /* PREFIX_VEX_0F382A */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4608   },
4609
4610   /* PREFIX_VEX_0F382B */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
4615   },
4616
4617   /* PREFIX_VEX_0F382C */
4618   {
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4622   },
4623
4624   /* PREFIX_VEX_0F382D */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4629   },
4630
4631   /* PREFIX_VEX_0F382E */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4636   },
4637
4638   /* PREFIX_VEX_0F382F */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4643   },
4644
4645   /* PREFIX_VEX_0F3830 */
4646   {
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
4650   },
4651
4652   /* PREFIX_VEX_0F3831 */
4653   {
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
4657   },
4658
4659   /* PREFIX_VEX_0F3832 */
4660   {
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
4664   },
4665
4666   /* PREFIX_VEX_0F3833 */
4667   {
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
4671   },
4672
4673   /* PREFIX_VEX_0F3834 */
4674   {
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
4678   },
4679
4680   /* PREFIX_VEX_0F3835 */
4681   {
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
4685   },
4686
4687   /* PREFIX_VEX_0F3836 */
4688   {
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
4692   },
4693
4694   /* PREFIX_VEX_0F3837 */
4695   {
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
4699   },
4700
4701   /* PREFIX_VEX_0F3838 */
4702   {
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
4706   },
4707
4708   /* PREFIX_VEX_0F3839 */
4709   {
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
4713   },
4714
4715   /* PREFIX_VEX_0F383A */
4716   {
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
4720   },
4721
4722   /* PREFIX_VEX_0F383B */
4723   {
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
4727   },
4728
4729   /* PREFIX_VEX_0F383C */
4730   {
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
4734   },
4735
4736   /* PREFIX_VEX_0F383D */
4737   {
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
4741   },
4742
4743   /* PREFIX_VEX_0F383E */
4744   {
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
4748   },
4749
4750   /* PREFIX_VEX_0F383F */
4751   {
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
4755   },
4756
4757   /* PREFIX_VEX_0F3840 */
4758   {
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
4762   },
4763
4764   /* PREFIX_VEX_0F3841 */
4765   {
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4769   },
4770
4771   /* PREFIX_VEX_0F3845 */
4772   {
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { "vpsrlv%LW", { XM, Vex, EXx } },
4776   },
4777
4778   /* PREFIX_VEX_0F3846 */
4779   {
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
4783   },
4784
4785   /* PREFIX_VEX_0F3847 */
4786   {
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { "vpsllv%LW", { XM, Vex, EXx } },
4790   },
4791
4792   /* PREFIX_VEX_0F3858 */
4793   {
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
4797   },
4798
4799   /* PREFIX_VEX_0F3859 */
4800   {
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
4804   },
4805
4806   /* PREFIX_VEX_0F385A */
4807   {
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
4811   },
4812
4813   /* PREFIX_VEX_0F3878 */
4814   {
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
4818   },
4819
4820   /* PREFIX_VEX_0F3879 */
4821   {
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
4825   },
4826
4827   /* PREFIX_VEX_0F388C */
4828   {
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
4832   },
4833
4834   /* PREFIX_VEX_0F388E */
4835   {
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
4839   },
4840
4841   /* PREFIX_VEX_0F3890 */
4842   {
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
4846   },
4847
4848   /* PREFIX_VEX_0F3891 */
4849   {
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4853   },
4854
4855   /* PREFIX_VEX_0F3892 */
4856   {
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
4860   },
4861
4862   /* PREFIX_VEX_0F3893 */
4863   {
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4867   },
4868
4869   /* PREFIX_VEX_0F3896 */
4870   {
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4874   },
4875
4876   /* PREFIX_VEX_0F3897 */
4877   {
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4881   },
4882
4883   /* PREFIX_VEX_0F3898 */
4884   {
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { "vfmadd132p%XW", { XM, Vex, EXx } },
4888   },
4889
4890   /* PREFIX_VEX_0F3899 */
4891   {
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4895   },
4896
4897   /* PREFIX_VEX_0F389A */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { "vfmsub132p%XW", { XM, Vex, EXx } },
4902   },
4903
4904   /* PREFIX_VEX_0F389B */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4909   },
4910
4911   /* PREFIX_VEX_0F389C */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4916   },
4917
4918   /* PREFIX_VEX_0F389D */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4923   },
4924
4925   /* PREFIX_VEX_0F389E */
4926   {
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4930   },
4931
4932   /* PREFIX_VEX_0F389F */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4937   },
4938
4939   /* PREFIX_VEX_0F38A6 */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4944     { Bad_Opcode },
4945   },
4946
4947   /* PREFIX_VEX_0F38A7 */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4952   },
4953
4954   /* PREFIX_VEX_0F38A8 */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { "vfmadd213p%XW", { XM, Vex, EXx } },
4959   },
4960
4961   /* PREFIX_VEX_0F38A9 */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4966   },
4967
4968   /* PREFIX_VEX_0F38AA */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { "vfmsub213p%XW", { XM, Vex, EXx } },
4973   },
4974
4975   /* PREFIX_VEX_0F38AB */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4980   },
4981
4982   /* PREFIX_VEX_0F38AC */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4987   },
4988
4989   /* PREFIX_VEX_0F38AD */
4990   {
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4994   },
4995
4996   /* PREFIX_VEX_0F38AE */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5001   },
5002
5003   /* PREFIX_VEX_0F38AF */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5008   },
5009
5010   /* PREFIX_VEX_0F38B6 */
5011   {
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5015   },
5016
5017   /* PREFIX_VEX_0F38B7 */
5018   {
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5022   },
5023
5024   /* PREFIX_VEX_0F38B8 */
5025   {
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { "vfmadd231p%XW", { XM, Vex, EXx } },
5029   },
5030
5031   /* PREFIX_VEX_0F38B9 */
5032   {
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5036   },
5037
5038   /* PREFIX_VEX_0F38BA */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { "vfmsub231p%XW", { XM, Vex, EXx } },
5043   },
5044
5045   /* PREFIX_VEX_0F38BB */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5050   },
5051
5052   /* PREFIX_VEX_0F38BC */
5053   {
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5057   },
5058
5059   /* PREFIX_VEX_0F38BD */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5064   },
5065
5066   /* PREFIX_VEX_0F38BE */
5067   {
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5071   },
5072
5073   /* PREFIX_VEX_0F38BF */
5074   {
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5078   },
5079
5080   /* PREFIX_VEX_0F38DB */
5081   {
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5085   },
5086
5087   /* PREFIX_VEX_0F38DC */
5088   {
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_0F38DD */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0F38DE */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0F38DF */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5113   },
5114
5115   /* PREFIX_VEX_0F38F2 */
5116   {
5117     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5118   },
5119
5120   /* PREFIX_VEX_0F38F3_REG_1 */
5121   {
5122     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5123   },
5124
5125   /* PREFIX_VEX_0F38F3_REG_2 */
5126   {
5127     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5128   },
5129
5130   /* PREFIX_VEX_0F38F3_REG_3 */
5131   {
5132     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5133   },
5134
5135   /* PREFIX_VEX_0F38F5 */
5136   {
5137     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5138     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5139     { Bad_Opcode },
5140     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5141   },
5142
5143   /* PREFIX_VEX_0F38F6 */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5149   },
5150
5151   /* PREFIX_VEX_0F38F7 */
5152   {
5153     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5154     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5155     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5156     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5157   },
5158
5159   /* PREFIX_VEX_0F3A00 */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_0F3A01 */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5171   },
5172
5173   /* PREFIX_VEX_0F3A02 */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5178   },
5179
5180   /* PREFIX_VEX_0F3A04 */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5185   },
5186
5187   /* PREFIX_VEX_0F3A05 */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5192   },
5193
5194   /* PREFIX_VEX_0F3A06 */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5199   },
5200
5201   /* PREFIX_VEX_0F3A08 */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5206   },
5207
5208   /* PREFIX_VEX_0F3A09 */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5213   },
5214
5215   /* PREFIX_VEX_0F3A0A */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5220   },
5221
5222   /* PREFIX_VEX_0F3A0B */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5227   },
5228
5229   /* PREFIX_VEX_0F3A0C */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5234   },
5235
5236   /* PREFIX_VEX_0F3A0D */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5241   },
5242
5243   /* PREFIX_VEX_0F3A0E */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
5248   },
5249
5250   /* PREFIX_VEX_0F3A0F */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
5255   },
5256
5257   /* PREFIX_VEX_0F3A14 */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5262   },
5263
5264   /* PREFIX_VEX_0F3A15 */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5269   },
5270
5271   /* PREFIX_VEX_0F3A16 */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5276   },
5277
5278   /* PREFIX_VEX_0F3A17 */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5283   },
5284
5285   /* PREFIX_VEX_0F3A18 */
5286   {
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5290   },
5291
5292   /* PREFIX_VEX_0F3A19 */
5293   {
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5297   },
5298
5299   /* PREFIX_VEX_0F3A1D */
5300   {
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { "vcvtps2ph", { EXxmmq, XM, Ib } },
5304   },
5305
5306   /* PREFIX_VEX_0F3A20 */
5307   {
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5311   },
5312
5313   /* PREFIX_VEX_0F3A21 */
5314   {
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5318   },
5319
5320   /* PREFIX_VEX_0F3A22 */
5321   {
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5325   },
5326
5327   /* PREFIX_VEX_0F3A38 */
5328   {
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
5332   },
5333
5334   /* PREFIX_VEX_0F3A39 */
5335   {
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
5339   },
5340
5341   /* PREFIX_VEX_0F3A40 */
5342   {
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5346   },
5347
5348   /* PREFIX_VEX_0F3A41 */
5349   {
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5353   },
5354
5355   /* PREFIX_VEX_0F3A42 */
5356   {
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
5360   },
5361
5362   /* PREFIX_VEX_0F3A44 */
5363   {
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5367   },
5368
5369   /* PREFIX_VEX_0F3A46 */
5370   {
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
5374   },
5375
5376   /* PREFIX_VEX_0F3A48 */
5377   {
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5381   },
5382
5383   /* PREFIX_VEX_0F3A49 */
5384   {
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5388   },
5389
5390   /* PREFIX_VEX_0F3A4A */
5391   {
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5395   },
5396
5397   /* PREFIX_VEX_0F3A4B */
5398   {
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5402   },
5403
5404   /* PREFIX_VEX_0F3A4C */
5405   {
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
5409   },
5410
5411   /* PREFIX_VEX_0F3A5C */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5416   },
5417
5418   /* PREFIX_VEX_0F3A5D */
5419   {
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5423   },
5424
5425   /* PREFIX_VEX_0F3A5E */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5430   },
5431
5432   /* PREFIX_VEX_0F3A5F */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5437   },
5438
5439   /* PREFIX_VEX_0F3A60 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5444     { Bad_Opcode },
5445   },
5446
5447   /* PREFIX_VEX_0F3A61 */
5448   {
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5452   },
5453
5454   /* PREFIX_VEX_0F3A62 */
5455   {
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5459   },
5460
5461   /* PREFIX_VEX_0F3A63 */
5462   {
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5466   },
5467
5468   /* PREFIX_VEX_0F3A68 */
5469   {
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5473   },
5474
5475   /* PREFIX_VEX_0F3A69 */
5476   {
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5480   },
5481
5482   /* PREFIX_VEX_0F3A6A */
5483   {
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5487   },
5488
5489   /* PREFIX_VEX_0F3A6B */
5490   {
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5494   },
5495
5496   /* PREFIX_VEX_0F3A6C */
5497   {
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5501   },
5502
5503   /* PREFIX_VEX_0F3A6D */
5504   {
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5508   },
5509
5510   /* PREFIX_VEX_0F3A6E */
5511   {
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5515   },
5516
5517   /* PREFIX_VEX_0F3A6F */
5518   {
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5522   },
5523
5524   /* PREFIX_VEX_0F3A78 */
5525   {
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5529   },
5530
5531   /* PREFIX_VEX_0F3A79 */
5532   {
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5536   },
5537
5538   /* PREFIX_VEX_0F3A7A */
5539   {
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5543   },
5544
5545   /* PREFIX_VEX_0F3A7B */
5546   {
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5550   },
5551
5552   /* PREFIX_VEX_0F3A7C */
5553   {
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5557     { Bad_Opcode },
5558   },
5559
5560   /* PREFIX_VEX_0F3A7D */
5561   {
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5565   },
5566
5567   /* PREFIX_VEX_0F3A7E */
5568   {
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5572   },
5573
5574   /* PREFIX_VEX_0F3A7F */
5575   {
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5579   },
5580
5581   /* PREFIX_VEX_0F3ADF */
5582   {
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5586   },
5587
5588   /* PREFIX_VEX_0F3AF0 */
5589   {
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
5594   },
5595 };
5596
5597 static const struct dis386 x86_64_table[][2] = {
5598   /* X86_64_06 */
5599   {
5600     { "pushP", { es } },
5601   },
5602
5603   /* X86_64_07 */
5604   {
5605     { "popP", { es } },
5606   },
5607
5608   /* X86_64_0D */
5609   {
5610     { "pushP", { cs } },
5611   },
5612
5613   /* X86_64_16 */
5614   {
5615     { "pushP", { ss } },
5616   },
5617
5618   /* X86_64_17 */
5619   {
5620     { "popP", { ss } },
5621   },
5622
5623   /* X86_64_1E */
5624   {
5625     { "pushP", { ds } },
5626   },
5627
5628   /* X86_64_1F */
5629   {
5630     { "popP", { ds } },
5631   },
5632
5633   /* X86_64_27 */
5634   {
5635     { "daa", { XX } },
5636   },
5637
5638   /* X86_64_2F */
5639   {
5640     { "das", { XX } },
5641   },
5642
5643   /* X86_64_37 */
5644   {
5645     { "aaa", { XX } },
5646   },
5647
5648   /* X86_64_3F */
5649   {
5650     { "aas", { XX } },
5651   },
5652
5653   /* X86_64_60 */
5654   {
5655     { "pushaP", { XX } },
5656   },
5657
5658   /* X86_64_61 */
5659   {
5660     { "popaP", { XX } },
5661   },
5662
5663   /* X86_64_62 */
5664   {
5665     { MOD_TABLE (MOD_62_32BIT) },
5666   },
5667
5668   /* X86_64_63 */
5669   {
5670     { "arpl", { Ew, Gw } },
5671     { "movs{lq|xd}", { Gv, Ed } },
5672   },
5673
5674   /* X86_64_6D */
5675   {
5676     { "ins{R|}", { Yzr, indirDX } },
5677     { "ins{G|}", { Yzr, indirDX } },
5678   },
5679
5680   /* X86_64_6F */
5681   {
5682     { "outs{R|}", { indirDXr, Xz } },
5683     { "outs{G|}", { indirDXr, Xz } },
5684   },
5685
5686   /* X86_64_9A */
5687   {
5688     { "Jcall{T|}", { Ap } },
5689   },
5690
5691   /* X86_64_C4 */
5692   {
5693     { MOD_TABLE (MOD_C4_32BIT) },
5694     { VEX_C4_TABLE (VEX_0F) },
5695   },
5696
5697   /* X86_64_C5 */
5698   {
5699     { MOD_TABLE (MOD_C5_32BIT) },
5700     { VEX_C5_TABLE (VEX_0F) },
5701   },
5702
5703   /* X86_64_CE */
5704   {
5705     { "into", { XX } },
5706   },
5707
5708   /* X86_64_D4 */
5709   {
5710     { "aam", { Ib } },
5711   },
5712
5713   /* X86_64_D5 */
5714   {
5715     { "aad", { Ib } },
5716   },
5717
5718   /* X86_64_EA */
5719   {
5720     { "Jjmp{T|}", { Ap } },
5721   },
5722
5723   /* X86_64_0F01_REG_0 */
5724   {
5725     { "sgdt{Q|IQ}", { M } },
5726     { "sgdt", { M } },
5727   },
5728
5729   /* X86_64_0F01_REG_1 */
5730   {
5731     { "sidt{Q|IQ}", { M } },
5732     { "sidt", { M } },
5733   },
5734
5735   /* X86_64_0F01_REG_2 */
5736   {
5737     { "lgdt{Q|Q}", { M } },
5738     { "lgdt", { M } },
5739   },
5740
5741   /* X86_64_0F01_REG_3 */
5742   {
5743     { "lidt{Q|Q}", { M } },
5744     { "lidt", { M } },
5745   },
5746 };
5747
5748 static const struct dis386 three_byte_table[][256] = {
5749
5750   /* THREE_BYTE_0F38 */
5751   {
5752     /* 00 */
5753     { "pshufb",         { MX, EM } },
5754     { "phaddw",         { MX, EM } },
5755     { "phaddd",         { MX, EM } },
5756     { "phaddsw",        { MX, EM } },
5757     { "pmaddubsw",      { MX, EM } },
5758     { "phsubw",         { MX, EM } },
5759     { "phsubd",         { MX, EM } },
5760     { "phsubsw",        { MX, EM } },
5761     /* 08 */
5762     { "psignb",         { MX, EM } },
5763     { "psignw",         { MX, EM } },
5764     { "psignd",         { MX, EM } },
5765     { "pmulhrsw",       { MX, EM } },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     /* 10 */
5771     { PREFIX_TABLE (PREFIX_0F3810) },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { PREFIX_TABLE (PREFIX_0F3814) },
5776     { PREFIX_TABLE (PREFIX_0F3815) },
5777     { Bad_Opcode },
5778     { PREFIX_TABLE (PREFIX_0F3817) },
5779     /* 18 */
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { "pabsb",          { MX, EM } },
5785     { "pabsw",          { MX, EM } },
5786     { "pabsd",          { MX, EM } },
5787     { Bad_Opcode },
5788     /* 20 */
5789     { PREFIX_TABLE (PREFIX_0F3820) },
5790     { PREFIX_TABLE (PREFIX_0F3821) },
5791     { PREFIX_TABLE (PREFIX_0F3822) },
5792     { PREFIX_TABLE (PREFIX_0F3823) },
5793     { PREFIX_TABLE (PREFIX_0F3824) },
5794     { PREFIX_TABLE (PREFIX_0F3825) },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     /* 28 */
5798     { PREFIX_TABLE (PREFIX_0F3828) },
5799     { PREFIX_TABLE (PREFIX_0F3829) },
5800     { PREFIX_TABLE (PREFIX_0F382A) },
5801     { PREFIX_TABLE (PREFIX_0F382B) },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     /* 30 */
5807     { PREFIX_TABLE (PREFIX_0F3830) },
5808     { PREFIX_TABLE (PREFIX_0F3831) },
5809     { PREFIX_TABLE (PREFIX_0F3832) },
5810     { PREFIX_TABLE (PREFIX_0F3833) },
5811     { PREFIX_TABLE (PREFIX_0F3834) },
5812     { PREFIX_TABLE (PREFIX_0F3835) },
5813     { Bad_Opcode },
5814     { PREFIX_TABLE (PREFIX_0F3837) },
5815     /* 38 */
5816     { PREFIX_TABLE (PREFIX_0F3838) },
5817     { PREFIX_TABLE (PREFIX_0F3839) },
5818     { PREFIX_TABLE (PREFIX_0F383A) },
5819     { PREFIX_TABLE (PREFIX_0F383B) },
5820     { PREFIX_TABLE (PREFIX_0F383C) },
5821     { PREFIX_TABLE (PREFIX_0F383D) },
5822     { PREFIX_TABLE (PREFIX_0F383E) },
5823     { PREFIX_TABLE (PREFIX_0F383F) },
5824     /* 40 */
5825     { PREFIX_TABLE (PREFIX_0F3840) },
5826     { PREFIX_TABLE (PREFIX_0F3841) },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     /* 48 */
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     /* 50 */
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     /* 58 */
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     /* 60 */
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     /* 68 */
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     /* 70 */
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     /* 78 */
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     /* 80 */
5897     { PREFIX_TABLE (PREFIX_0F3880) },
5898     { PREFIX_TABLE (PREFIX_0F3881) },
5899     { PREFIX_TABLE (PREFIX_0F3882) },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     /* 88 */
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     /* 90 */
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     /* 98 */
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     /* a0 */
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     /* a8 */
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     /* b0 */
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     /* b8 */
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     /* c0 */
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     /* c8 */
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     /* d0 */
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     /* d8 */
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { PREFIX_TABLE (PREFIX_0F38DB) },
6000     { PREFIX_TABLE (PREFIX_0F38DC) },
6001     { PREFIX_TABLE (PREFIX_0F38DD) },
6002     { PREFIX_TABLE (PREFIX_0F38DE) },
6003     { PREFIX_TABLE (PREFIX_0F38DF) },
6004     /* e0 */
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     /* e8 */
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     /* f0 */
6023     { PREFIX_TABLE (PREFIX_0F38F0) },
6024     { PREFIX_TABLE (PREFIX_0F38F1) },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     /* f8 */
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040   },
6041   /* THREE_BYTE_0F3A */
6042   {
6043     /* 00 */
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     /* 08 */
6053     { PREFIX_TABLE (PREFIX_0F3A08) },
6054     { PREFIX_TABLE (PREFIX_0F3A09) },
6055     { PREFIX_TABLE (PREFIX_0F3A0A) },
6056     { PREFIX_TABLE (PREFIX_0F3A0B) },
6057     { PREFIX_TABLE (PREFIX_0F3A0C) },
6058     { PREFIX_TABLE (PREFIX_0F3A0D) },
6059     { PREFIX_TABLE (PREFIX_0F3A0E) },
6060     { "palignr",        { MX, EM, Ib } },
6061     /* 10 */
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { PREFIX_TABLE (PREFIX_0F3A14) },
6067     { PREFIX_TABLE (PREFIX_0F3A15) },
6068     { PREFIX_TABLE (PREFIX_0F3A16) },
6069     { PREFIX_TABLE (PREFIX_0F3A17) },
6070     /* 18 */
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     /* 20 */
6080     { PREFIX_TABLE (PREFIX_0F3A20) },
6081     { PREFIX_TABLE (PREFIX_0F3A21) },
6082     { PREFIX_TABLE (PREFIX_0F3A22) },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     /* 28 */
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     /* 30 */
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     /* 38 */
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     /* 40 */
6116     { PREFIX_TABLE (PREFIX_0F3A40) },
6117     { PREFIX_TABLE (PREFIX_0F3A41) },
6118     { PREFIX_TABLE (PREFIX_0F3A42) },
6119     { Bad_Opcode },
6120     { PREFIX_TABLE (PREFIX_0F3A44) },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     /* 48 */
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     /* 50 */
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     /* 58 */
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     /* 60 */
6152     { PREFIX_TABLE (PREFIX_0F3A60) },
6153     { PREFIX_TABLE (PREFIX_0F3A61) },
6154     { PREFIX_TABLE (PREFIX_0F3A62) },
6155     { PREFIX_TABLE (PREFIX_0F3A63) },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     /* 68 */
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     /* 70 */
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     /* 78 */
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     /* 80 */
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     /* 88 */
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     /* 90 */
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     /* 98 */
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     /* a0 */
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     /* a8 */
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     /* b0 */
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     /* b8 */
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     /* c0 */
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     /* c8 */
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     /* d0 */
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     /* d8 */
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { PREFIX_TABLE (PREFIX_0F3ADF) },
6295     /* e0 */
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     /* e8 */
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     /* f0 */
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     /* f8 */
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331   },
6332
6333   /* THREE_BYTE_0F7A */
6334   {
6335     /* 00 */
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     /* 08 */
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     /* 10 */
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     /* 18 */
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     /* 20 */
6372     { "ptest",          { XX } },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     /* 28 */
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     /* 30 */
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     /* 38 */
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     /* 40 */
6408     { Bad_Opcode },
6409     { "phaddbw",        { XM, EXq } },
6410     { "phaddbd",        { XM, EXq } },
6411     { "phaddbq",        { XM, EXq } },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { "phaddwd",        { XM, EXq } },
6415     { "phaddwq",        { XM, EXq } },
6416     /* 48 */
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { "phadddq",        { XM, EXq } },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     /* 50 */
6426     { Bad_Opcode },
6427     { "phaddubw",       { XM, EXq } },
6428     { "phaddubd",       { XM, EXq } },
6429     { "phaddubq",       { XM, EXq } },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { "phadduwd",       { XM, EXq } },
6433     { "phadduwq",       { XM, EXq } },
6434     /* 58 */
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { "phaddudq",       { XM, EXq } },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     /* 60 */
6444     { Bad_Opcode },
6445     { "phsubbw",        { XM, EXq } },
6446     { "phsubbd",        { XM, EXq } },
6447     { "phsubbq",        { XM, EXq } },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     /* 68 */
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     /* 70 */
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     /* 78 */
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     /* 80 */
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     /* 88 */
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     /* 90 */
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     /* 98 */
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     /* a0 */
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     /* a8 */
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     /* b0 */
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     /* b8 */
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     /* c0 */
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     /* c8 */
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     /* d0 */
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     /* d8 */
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     /* e0 */
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     /* e8 */
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     /* f0 */
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     /* f8 */
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623   },
6624 };
6625
6626 static const struct dis386 xop_table[][256] = {
6627   /* XOP_08 */
6628   {
6629     /* 00 */
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     /* 08 */
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     /* 10 */
6648     { "bextr",  { Gv, Ev, Iq } },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     /* 18 */
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     /* 20 */
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     /* 28 */
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     /* 30 */
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     /* 38 */
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     /* 40 */
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     /* 48 */
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     /* 50 */
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     /* 58 */
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     /* 60 */
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     /* 68 */
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     /* 70 */
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     /* 78 */
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     /* 80 */
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6780     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6781     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6782     /* 88 */
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6790     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6791     /* 90 */
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6798     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6799     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6800     /* 98 */
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6808     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6809     /* a0 */
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6813     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6817     { Bad_Opcode },
6818     /* a8 */
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     /* b0 */
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6835     { Bad_Opcode },
6836     /* b8 */
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     /* c0 */
6846     { "vprotb",         { XM, Vex_2src_1, Ib } },
6847     { "vprotw",         { XM, Vex_2src_1, Ib } },
6848     { "vprotd",         { XM, Vex_2src_1, Ib } },
6849     { "vprotq",         { XM, Vex_2src_1, Ib } },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     /* c8 */
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6860     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6861     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6862     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6863     /* d0 */
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     /* d8 */
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     /* e0 */
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     /* e8 */
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6896     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6897     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6898     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6899     /* f0 */
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     /* f8 */
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917   },
6918   /* XOP_09 */
6919   {
6920     /* 00 */
6921     { Bad_Opcode },
6922     { REG_TABLE (REG_XOP_TBM_01) },
6923     { REG_TABLE (REG_XOP_TBM_02) },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     /* 08 */
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     /* 10 */
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { REG_TABLE (REG_XOP_LWPCB) },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     /* 18 */
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     /* 20 */
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     /* 28 */
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     /* 30 */
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     /* 38 */
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     /* 40 */
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     /* 48 */
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     /* 50 */
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     /* 58 */
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     /* 60 */
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     /* 68 */
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     /* 70 */
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     /* 78 */
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     /* 80 */
7065     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7066     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7067     { "vfrczss",        { XM, EXd } },
7068     { "vfrczsd",        { XM, EXq } },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     /* 88 */
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* 90 */
7083     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7084     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7085     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7086     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7087     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7088     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7089     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7090     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7091     /* 98 */
7092     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7093     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7094     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7095     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     /* a0 */
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     /* a8 */
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     /* b0 */
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     /* b8 */
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     /* c0 */
7137     { Bad_Opcode },
7138     { "vphaddbw",       { XM, EXxmm } },
7139     { "vphaddbd",       { XM, EXxmm } },
7140     { "vphaddbq",       { XM, EXxmm } },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { "vphaddwd",       { XM, EXxmm } },
7144     { "vphaddwq",       { XM, EXxmm } },
7145     /* c8 */
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { "vphadddq",       { XM, EXxmm } },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     /* d0 */
7155     { Bad_Opcode },
7156     { "vphaddubw",      { XM, EXxmm } },
7157     { "vphaddubd",      { XM, EXxmm } },
7158     { "vphaddubq",      { XM, EXxmm } },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { "vphadduwd",      { XM, EXxmm } },
7162     { "vphadduwq",      { XM, EXxmm } },
7163     /* d8 */
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { "vphaddudq",      { XM, EXxmm } },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     /* e0 */
7173     { Bad_Opcode },
7174     { "vphsubbw",       { XM, EXxmm } },
7175     { "vphsubwd",       { XM, EXxmm } },
7176     { "vphsubdq",       { XM, EXxmm } },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     /* e8 */
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* f0 */
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     /* f8 */
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208   },
7209   /* XOP_0A */
7210   {
7211     /* 00 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 08 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* 10 */
7230     { "bextr",  { Gv, Ev, Iq } },
7231     { Bad_Opcode },
7232     { REG_TABLE (REG_XOP_LWP) },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 18 */
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* 20 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* 28 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* 30 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 38 */
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* 40 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* 48 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* 50 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* 58 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* 60 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* 68 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* 70 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* 78 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* 80 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* 88 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* 90 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* 98 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* a0 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* a8 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* b0 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     /* b8 */
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     /* c0 */
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     /* c8 */
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     /* d0 */
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     /* d8 */
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     /* e0 */
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     /* e8 */
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     /* f0 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* f8 */
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499   },
7500 };
7501
7502 static const struct dis386 vex_table[][256] = {
7503   /* VEX_0F */
7504   {
7505     /* 00 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* 08 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* 10 */
7524     { PREFIX_TABLE (PREFIX_VEX_0F10) },
7525     { PREFIX_TABLE (PREFIX_VEX_0F11) },
7526     { PREFIX_TABLE (PREFIX_VEX_0F12) },
7527     { MOD_TABLE (MOD_VEX_0F13) },
7528     { VEX_W_TABLE (VEX_W_0F14) },
7529     { VEX_W_TABLE (VEX_W_0F15) },
7530     { PREFIX_TABLE (PREFIX_VEX_0F16) },
7531     { MOD_TABLE (MOD_VEX_0F17) },
7532     /* 18 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* 20 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* 28 */
7551     { VEX_W_TABLE (VEX_W_0F28) },
7552     { VEX_W_TABLE (VEX_W_0F29) },
7553     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7554     { MOD_TABLE (MOD_VEX_0F2B) },
7555     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7556     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7557     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7558     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7559     /* 30 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     /* 38 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     /* 40 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     /* 48 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     /* 50 */
7596     { MOD_TABLE (MOD_VEX_0F50) },
7597     { PREFIX_TABLE (PREFIX_VEX_0F51) },
7598     { PREFIX_TABLE (PREFIX_VEX_0F52) },
7599     { PREFIX_TABLE (PREFIX_VEX_0F53) },
7600     { "vandpX",         { XM, Vex, EXx } },
7601     { "vandnpX",        { XM, Vex, EXx } },
7602     { "vorpX",          { XM, Vex, EXx } },
7603     { "vxorpX",         { XM, Vex, EXx } },
7604     /* 58 */
7605     { PREFIX_TABLE (PREFIX_VEX_0F58) },
7606     { PREFIX_TABLE (PREFIX_VEX_0F59) },
7607     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7608     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7609     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7610     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7611     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7612     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7613     /* 60 */
7614     { PREFIX_TABLE (PREFIX_VEX_0F60) },
7615     { PREFIX_TABLE (PREFIX_VEX_0F61) },
7616     { PREFIX_TABLE (PREFIX_VEX_0F62) },
7617     { PREFIX_TABLE (PREFIX_VEX_0F63) },
7618     { PREFIX_TABLE (PREFIX_VEX_0F64) },
7619     { PREFIX_TABLE (PREFIX_VEX_0F65) },
7620     { PREFIX_TABLE (PREFIX_VEX_0F66) },
7621     { PREFIX_TABLE (PREFIX_VEX_0F67) },
7622     /* 68 */
7623     { PREFIX_TABLE (PREFIX_VEX_0F68) },
7624     { PREFIX_TABLE (PREFIX_VEX_0F69) },
7625     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7626     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7627     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7628     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7629     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7630     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7631     /* 70 */
7632     { PREFIX_TABLE (PREFIX_VEX_0F70) },
7633     { REG_TABLE (REG_VEX_0F71) },
7634     { REG_TABLE (REG_VEX_0F72) },
7635     { REG_TABLE (REG_VEX_0F73) },
7636     { PREFIX_TABLE (PREFIX_VEX_0F74) },
7637     { PREFIX_TABLE (PREFIX_VEX_0F75) },
7638     { PREFIX_TABLE (PREFIX_VEX_0F76) },
7639     { PREFIX_TABLE (PREFIX_VEX_0F77) },
7640     /* 78 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7646     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7647     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7648     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7649     /* 80 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     /* 88 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* 90 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     /* 98 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* a0 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* a8 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { REG_TABLE (REG_VEX_0FAE) },
7702     { Bad_Opcode },
7703     /* b0 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     /* b8 */
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     /* c0 */
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7725     { Bad_Opcode },
7726     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7727     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7728     { "vshufpX",        { XM, Vex, EXx, Ib } },
7729     { Bad_Opcode },
7730     /* c8 */
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     /* d0 */
7740     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7741     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7742     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7743     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7744     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7745     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7746     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7747     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7748     /* d8 */
7749     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7750     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7751     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7752     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7753     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7754     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7755     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7756     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7757     /* e0 */
7758     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7759     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7760     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7761     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7762     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7763     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7764     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7765     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7766     /* e8 */
7767     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7768     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7769     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7770     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7771     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7772     { PREFIX_TABLE (PREFIX_VEX_0FED) },
7773     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7774     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7775     /* f0 */
7776     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7777     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7778     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7779     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7780     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7781     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7782     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7783     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7784     /* f8 */
7785     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7786     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7787     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7788     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7789     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7790     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7791     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7792     { Bad_Opcode },
7793   },
7794   /* VEX_0F38 */
7795   {
7796     /* 00 */
7797     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7798     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7799     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7800     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7801     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7802     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7803     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7804     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7805     /* 08 */
7806     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7807     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7808     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7809     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7810     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7811     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7812     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7813     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7814     /* 10 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
7822     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7823     /* 18 */
7824     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7825     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7826     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7827     { Bad_Opcode },
7828     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7829     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7830     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7831     { Bad_Opcode },
7832     /* 20 */
7833     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7834     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7835     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7836     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7837     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7838     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 28 */
7842     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7843     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7844     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7845     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7846     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7847     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7848     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7849     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7850     /* 30 */
7851     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7852     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7853     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7854     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7855     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7856     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7857     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
7858     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7859     /* 38 */
7860     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7861     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7862     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7863     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7864     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7865     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7866     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7867     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7868     /* 40 */
7869     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7870     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
7875     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
7876     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
7877     /* 48 */
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* 50 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* 58 */
7896     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
7897     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
7898     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* 60 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* 68 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* 70 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* 78 */
7932     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
7933     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* 80 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     /* 88 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
7955     { Bad_Opcode },
7956     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
7957     { Bad_Opcode },
7958     /* 90 */
7959     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
7960     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
7961     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
7962     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
7966     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
7967     /* 98 */
7968     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
7969     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
7970     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
7971     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
7972     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
7973     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
7974     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
7975     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
7976     /* a0 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
7984     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
7985     /* a8 */
7986     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
7987     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
7988     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
7989     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
7990     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
7991     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
7992     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
7993     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
7994     /* b0 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8002     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8003     /* b8 */
8004     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8005     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8006     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8007     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8008     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8009     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8010     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8011     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8012     /* c0 */
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     /* c8 */
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* d0 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     /* d8 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8044     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8045     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8046     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8047     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8048     /* e0 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     /* e8 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     /* f0 */
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8070     { REG_TABLE (REG_VEX_0F38F3) },
8071     { Bad_Opcode },
8072     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8073     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8074     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8075     /* f8 */
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084   },
8085   /* VEX_0F3A */
8086   {
8087     /* 00 */
8088     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8089     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8090     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8091     { Bad_Opcode },
8092     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8093     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8094     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8095     { Bad_Opcode },
8096     /* 08 */
8097     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8098     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8099     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8100     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8101     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8102     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8103     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8104     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8105     /* 10 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8111     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8112     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8113     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8114     /* 18 */
8115     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8116     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* 20 */
8124     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8125     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8126     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 28 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 30 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 38 */
8151     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8152     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 40 */
8160     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8161     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8162     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8163     { Bad_Opcode },
8164     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8165     { Bad_Opcode },
8166     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8167     { Bad_Opcode },
8168     /* 48 */
8169     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8170     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8171     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8172     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8173     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* 50 */
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* 58 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8192     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8193     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8194     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8195     /* 60 */
8196     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8197     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8198     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8199     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* 68 */
8205     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8206     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8207     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8208     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8209     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8210     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8211     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8212     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8213     /* 70 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* 78 */
8223     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8224     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8225     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8226     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8227     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8228     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8229     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8230     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8231     /* 80 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* 88 */
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* 90 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* 98 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* a0 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* a8 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* b0 */
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     /* b8 */
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     /* c0 */
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     /* c8 */
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     /* d0 */
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     /* d8 */
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8339     /* e0 */
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     /* e8 */
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     /* f0 */
8358     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     /* f8 */
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375   },
8376 };
8377
8378 static const struct dis386 vex_len_table[][2] = {
8379   /* VEX_LEN_0F10_P_1 */
8380   {
8381     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8382     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8383   },
8384
8385   /* VEX_LEN_0F10_P_3 */
8386   {
8387     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8388     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8389   },
8390
8391   /* VEX_LEN_0F11_P_1 */
8392   {
8393     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8394     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8395   },
8396
8397   /* VEX_LEN_0F11_P_3 */
8398   {
8399     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8400     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8401   },
8402
8403   /* VEX_LEN_0F12_P_0_M_0 */
8404   {
8405     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8406   },
8407
8408   /* VEX_LEN_0F12_P_0_M_1 */
8409   {
8410     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8411   },
8412
8413   /* VEX_LEN_0F12_P_2 */
8414   {
8415     { VEX_W_TABLE (VEX_W_0F12_P_2) },
8416   },
8417
8418   /* VEX_LEN_0F13_M_0 */
8419   {
8420     { VEX_W_TABLE (VEX_W_0F13_M_0) },
8421   },
8422
8423   /* VEX_LEN_0F16_P_0_M_0 */
8424   {
8425     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8426   },
8427
8428   /* VEX_LEN_0F16_P_0_M_1 */
8429   {
8430     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8431   },
8432
8433   /* VEX_LEN_0F16_P_2 */
8434   {
8435     { VEX_W_TABLE (VEX_W_0F16_P_2) },
8436   },
8437
8438   /* VEX_LEN_0F17_M_0 */
8439   {
8440     { VEX_W_TABLE (VEX_W_0F17_M_0) },
8441   },
8442
8443   /* VEX_LEN_0F2A_P_1 */
8444   {
8445     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8446     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8447   },
8448
8449   /* VEX_LEN_0F2A_P_3 */
8450   {
8451     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8452     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8453   },
8454
8455   /* VEX_LEN_0F2C_P_1 */
8456   {
8457     { "vcvttss2siY",    { Gv, EXdScalar } },
8458     { "vcvttss2siY",    { Gv, EXdScalar } },
8459   },
8460
8461   /* VEX_LEN_0F2C_P_3 */
8462   {
8463     { "vcvttsd2siY",    { Gv, EXqScalar } },
8464     { "vcvttsd2siY",    { Gv, EXqScalar } },
8465   },
8466
8467   /* VEX_LEN_0F2D_P_1 */
8468   {
8469     { "vcvtss2siY",     { Gv, EXdScalar } },
8470     { "vcvtss2siY",     { Gv, EXdScalar } },
8471   },
8472
8473   /* VEX_LEN_0F2D_P_3 */
8474   {
8475     { "vcvtsd2siY",     { Gv, EXqScalar } },
8476     { "vcvtsd2siY",     { Gv, EXqScalar } },
8477   },
8478
8479   /* VEX_LEN_0F2E_P_0 */
8480   {
8481     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8482     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8483   },
8484
8485   /* VEX_LEN_0F2E_P_2 */
8486   {
8487     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8488     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8489   },
8490
8491   /* VEX_LEN_0F2F_P_0 */
8492   {
8493     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8494     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8495   },
8496
8497   /* VEX_LEN_0F2F_P_2 */
8498   {
8499     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8500     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8501   },
8502
8503   /* VEX_LEN_0F51_P_1 */
8504   {
8505     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8506     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8507   },
8508
8509   /* VEX_LEN_0F51_P_3 */
8510   {
8511     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8512     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8513   },
8514
8515   /* VEX_LEN_0F52_P_1 */
8516   {
8517     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8518     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8519   },
8520
8521   /* VEX_LEN_0F53_P_1 */
8522   {
8523     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8524     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8525   },
8526
8527   /* VEX_LEN_0F58_P_1 */
8528   {
8529     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8530     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8531   },
8532
8533   /* VEX_LEN_0F58_P_3 */
8534   {
8535     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8536     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8537   },
8538
8539   /* VEX_LEN_0F59_P_1 */
8540   {
8541     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8542     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8543   },
8544
8545   /* VEX_LEN_0F59_P_3 */
8546   {
8547     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8548     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8549   },
8550
8551   /* VEX_LEN_0F5A_P_1 */
8552   {
8553     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8554     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8555   },
8556
8557   /* VEX_LEN_0F5A_P_3 */
8558   {
8559     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8560     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8561   },
8562
8563   /* VEX_LEN_0F5C_P_1 */
8564   {
8565     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8566     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8567   },
8568
8569   /* VEX_LEN_0F5C_P_3 */
8570   {
8571     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8572     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8573   },
8574
8575   /* VEX_LEN_0F5D_P_1 */
8576   {
8577     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8578     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8579   },
8580
8581   /* VEX_LEN_0F5D_P_3 */
8582   {
8583     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8584     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8585   },
8586
8587   /* VEX_LEN_0F5E_P_1 */
8588   {
8589     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8590     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8591   },
8592
8593   /* VEX_LEN_0F5E_P_3 */
8594   {
8595     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8596     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8597   },
8598
8599   /* VEX_LEN_0F5F_P_1 */
8600   {
8601     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8602     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8603   },
8604
8605   /* VEX_LEN_0F5F_P_3 */
8606   {
8607     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8608     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8609   },
8610
8611   /* VEX_LEN_0F6E_P_2 */
8612   {
8613     { "vmovK",          { XMScalar, Edq } },
8614     { "vmovK",          { XMScalar, Edq } },
8615   },
8616
8617   /* VEX_LEN_0F7E_P_1 */
8618   {
8619     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8620     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8621   },
8622
8623   /* VEX_LEN_0F7E_P_2 */
8624   {
8625     { "vmovK",          { Edq, XMScalar } },
8626     { "vmovK",          { Edq, XMScalar } },
8627   },
8628
8629   /* VEX_LEN_0FAE_R_2_M_0 */
8630   {
8631     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8632   },
8633
8634   /* VEX_LEN_0FAE_R_3_M_0 */
8635   {
8636     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8637   },
8638
8639   /* VEX_LEN_0FC2_P_1 */
8640   {
8641     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8642     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8643   },
8644
8645   /* VEX_LEN_0FC2_P_3 */
8646   {
8647     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8648     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8649   },
8650
8651   /* VEX_LEN_0FC4_P_2 */
8652   {
8653     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8654   },
8655
8656   /* VEX_LEN_0FC5_P_2 */
8657   {
8658     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8659   },
8660
8661   /* VEX_LEN_0FD6_P_2 */
8662   {
8663     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8664     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8665   },
8666
8667   /* VEX_LEN_0FF7_P_2 */
8668   {
8669     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8670   },
8671
8672   /* VEX_LEN_0F3816_P_2 */
8673   {
8674     { Bad_Opcode },
8675     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
8676   },
8677
8678   /* VEX_LEN_0F3819_P_2 */
8679   {
8680     { Bad_Opcode },
8681     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
8682   },
8683
8684   /* VEX_LEN_0F381A_P_2_M_0 */
8685   {
8686     { Bad_Opcode },
8687     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8688   },
8689
8690   /* VEX_LEN_0F3836_P_2 */
8691   {
8692     { Bad_Opcode },
8693     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
8694   },
8695
8696   /* VEX_LEN_0F3841_P_2 */
8697   {
8698     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
8699   },
8700
8701   /* VEX_LEN_0F385A_P_2_M_0 */
8702   {
8703     { Bad_Opcode },
8704     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
8705   },
8706
8707   /* VEX_LEN_0F38DB_P_2 */
8708   {
8709     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
8710   },
8711
8712   /* VEX_LEN_0F38DC_P_2 */
8713   {
8714     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
8715   },
8716
8717   /* VEX_LEN_0F38DD_P_2 */
8718   {
8719     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
8720   },
8721
8722   /* VEX_LEN_0F38DE_P_2 */
8723   {
8724     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
8725   },
8726
8727   /* VEX_LEN_0F38DF_P_2 */
8728   {
8729     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
8730   },
8731
8732   /* VEX_LEN_0F38F2_P_0 */
8733   {
8734     { "andnS",          { Gdq, VexGdq, Edq } },
8735   },
8736
8737   /* VEX_LEN_0F38F3_R_1_P_0 */
8738   {
8739     { "blsrS",          { VexGdq, Edq } },
8740   },
8741
8742   /* VEX_LEN_0F38F3_R_2_P_0 */
8743   {
8744     { "blsmskS",        { VexGdq, Edq } },
8745   },
8746
8747   /* VEX_LEN_0F38F3_R_3_P_0 */
8748   {
8749     { "blsiS",          { VexGdq, Edq } },
8750   },
8751
8752   /* VEX_LEN_0F38F5_P_0 */
8753   {
8754     { "bzhiS",          { Gdq, Edq, VexGdq } },
8755   },
8756
8757   /* VEX_LEN_0F38F5_P_1 */
8758   {
8759     { "pextS",          { Gdq, VexGdq, Edq } },
8760   },
8761
8762   /* VEX_LEN_0F38F5_P_3 */
8763   {
8764     { "pdepS",          { Gdq, VexGdq, Edq } },
8765   },
8766
8767   /* VEX_LEN_0F38F6_P_3 */
8768   {
8769     { "mulxS",          { Gdq, VexGdq, Edq } },
8770   },
8771
8772   /* VEX_LEN_0F38F7_P_0 */
8773   {
8774     { "bextrS",         { Gdq, Edq, VexGdq } },
8775   },
8776
8777   /* VEX_LEN_0F38F7_P_1 */
8778   {
8779     { "sarxS",          { Gdq, Edq, VexGdq } },
8780   },
8781
8782   /* VEX_LEN_0F38F7_P_2 */
8783   {
8784     { "shlxS",          { Gdq, Edq, VexGdq } },
8785   },
8786
8787   /* VEX_LEN_0F38F7_P_3 */
8788   {
8789     { "shrxS",          { Gdq, Edq, VexGdq } },
8790   },
8791
8792   /* VEX_LEN_0F3A00_P_2 */
8793   {
8794     { Bad_Opcode },
8795     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
8796   },
8797
8798   /* VEX_LEN_0F3A01_P_2 */
8799   {
8800     { Bad_Opcode },
8801     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
8802   },
8803
8804   /* VEX_LEN_0F3A06_P_2 */
8805   {
8806     { Bad_Opcode },
8807     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
8808   },
8809
8810   /* VEX_LEN_0F3A0A_P_2 */
8811   {
8812     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8813     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8814   },
8815
8816   /* VEX_LEN_0F3A0B_P_2 */
8817   {
8818     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8819     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8820   },
8821
8822   /* VEX_LEN_0F3A14_P_2 */
8823   {
8824     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
8825   },
8826
8827   /* VEX_LEN_0F3A15_P_2 */
8828   {
8829     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
8830   },
8831
8832   /* VEX_LEN_0F3A16_P_2  */
8833   {
8834     { "vpextrK",        { Edq, XM, Ib } },
8835   },
8836
8837   /* VEX_LEN_0F3A17_P_2 */
8838   {
8839     { "vextractps",     { Edqd, XM, Ib } },
8840   },
8841
8842   /* VEX_LEN_0F3A18_P_2 */
8843   {
8844     { Bad_Opcode },
8845     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
8846   },
8847
8848   /* VEX_LEN_0F3A19_P_2 */
8849   {
8850     { Bad_Opcode },
8851     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
8852   },
8853
8854   /* VEX_LEN_0F3A20_P_2 */
8855   {
8856     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
8857   },
8858
8859   /* VEX_LEN_0F3A21_P_2 */
8860   {
8861     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
8862   },
8863
8864   /* VEX_LEN_0F3A22_P_2 */
8865   {
8866     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8867   },
8868
8869   /* VEX_LEN_0F3A38_P_2 */
8870   {
8871     { Bad_Opcode },
8872     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
8873   },
8874
8875   /* VEX_LEN_0F3A39_P_2 */
8876   {
8877     { Bad_Opcode },
8878     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
8879   },
8880
8881   /* VEX_LEN_0F3A41_P_2 */
8882   {
8883     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
8884   },
8885
8886   /* VEX_LEN_0F3A44_P_2 */
8887   {
8888     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
8889   },
8890
8891   /* VEX_LEN_0F3A46_P_2 */
8892   {
8893     { Bad_Opcode },
8894     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
8895   },
8896
8897   /* VEX_LEN_0F3A60_P_2 */
8898   {
8899     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
8900   },
8901
8902   /* VEX_LEN_0F3A61_P_2 */
8903   {
8904     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
8905   },
8906
8907   /* VEX_LEN_0F3A62_P_2 */
8908   {
8909     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
8910   },
8911
8912   /* VEX_LEN_0F3A63_P_2 */
8913   {
8914     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
8915   },
8916
8917   /* VEX_LEN_0F3A6A_P_2 */
8918   {
8919     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8920   },
8921
8922   /* VEX_LEN_0F3A6B_P_2 */
8923   {
8924     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8925   },
8926
8927   /* VEX_LEN_0F3A6E_P_2 */
8928   {
8929     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8930   },
8931
8932   /* VEX_LEN_0F3A6F_P_2 */
8933   {
8934     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8935   },
8936
8937   /* VEX_LEN_0F3A7A_P_2 */
8938   {
8939     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8940   },
8941
8942   /* VEX_LEN_0F3A7B_P_2 */
8943   {
8944     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8945   },
8946
8947   /* VEX_LEN_0F3A7E_P_2 */
8948   {
8949     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8950   },
8951
8952   /* VEX_LEN_0F3A7F_P_2 */
8953   {
8954     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8955   },
8956
8957   /* VEX_LEN_0F3ADF_P_2 */
8958   {
8959     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
8960   },
8961
8962   /* VEX_LEN_0F3AF0_P_3 */
8963   {
8964     { "rorxS",          { Gdq, Edq, Ib } },
8965   },
8966
8967   /* VEX_LEN_0FXOP_09_80 */
8968   {
8969     { "vfrczps",        { XM, EXxmm } },
8970     { "vfrczps",        { XM, EXymmq } },
8971   },
8972
8973   /* VEX_LEN_0FXOP_09_81 */
8974   {
8975     { "vfrczpd",        { XM, EXxmm } },
8976     { "vfrczpd",        { XM, EXymmq } },
8977   },
8978 };
8979
8980 static const struct dis386 vex_w_table[][2] = {
8981   {
8982     /* VEX_W_0F10_P_0 */
8983     { "vmovups",        { XM, EXx } },
8984   },
8985   {
8986     /* VEX_W_0F10_P_1 */
8987     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
8988   },
8989   {
8990     /* VEX_W_0F10_P_2 */
8991     { "vmovupd",        { XM, EXx } },
8992   },
8993   {
8994     /* VEX_W_0F10_P_3 */
8995     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
8996   },
8997   {
8998     /* VEX_W_0F11_P_0 */
8999     { "vmovups",        { EXxS, XM } },
9000   },
9001   {
9002     /* VEX_W_0F11_P_1 */
9003     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9004   },
9005   {
9006     /* VEX_W_0F11_P_2 */
9007     { "vmovupd",        { EXxS, XM } },
9008   },
9009   {
9010     /* VEX_W_0F11_P_3 */
9011     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9012   },
9013   {
9014     /* VEX_W_0F12_P_0_M_0 */
9015     { "vmovlps",        { XM, Vex128, EXq } },
9016   },
9017   {
9018     /* VEX_W_0F12_P_0_M_1 */
9019     { "vmovhlps",       { XM, Vex128, EXq } },
9020   },
9021   {
9022     /* VEX_W_0F12_P_1 */
9023     { "vmovsldup",      { XM, EXx } },
9024   },
9025   {
9026     /* VEX_W_0F12_P_2 */
9027     { "vmovlpd",        { XM, Vex128, EXq } },
9028   },
9029   {
9030     /* VEX_W_0F12_P_3 */
9031     { "vmovddup",       { XM, EXymmq } },
9032   },
9033   {
9034     /* VEX_W_0F13_M_0 */
9035     { "vmovlpX",        { EXq, XM } },
9036   },
9037   {
9038     /* VEX_W_0F14 */
9039     { "vunpcklpX",      { XM, Vex, EXx } },
9040   },
9041   {
9042     /* VEX_W_0F15 */
9043     { "vunpckhpX",      { XM, Vex, EXx } },
9044   },
9045   {
9046     /* VEX_W_0F16_P_0_M_0 */
9047     { "vmovhps",        { XM, Vex128, EXq } },
9048   },
9049   {
9050     /* VEX_W_0F16_P_0_M_1 */
9051     { "vmovlhps",       { XM, Vex128, EXq } },
9052   },
9053   {
9054     /* VEX_W_0F16_P_1 */
9055     { "vmovshdup",      { XM, EXx } },
9056   },
9057   {
9058     /* VEX_W_0F16_P_2 */
9059     { "vmovhpd",        { XM, Vex128, EXq } },
9060   },
9061   {
9062     /* VEX_W_0F17_M_0 */
9063     { "vmovhpX",        { EXq, XM } },
9064   },
9065   {
9066     /* VEX_W_0F28 */
9067     { "vmovapX",        { XM, EXx } },
9068   },
9069   {
9070     /* VEX_W_0F29 */
9071     { "vmovapX",        { EXxS, XM } },
9072   },
9073   {
9074     /* VEX_W_0F2B_M_0 */
9075     { "vmovntpX",       { Mx, XM } },
9076   },
9077   {
9078     /* VEX_W_0F2E_P_0 */
9079     { "vucomiss",       { XMScalar, EXdScalar } },
9080   },
9081   {
9082     /* VEX_W_0F2E_P_2 */
9083     { "vucomisd",       { XMScalar, EXqScalar } },
9084   },
9085   {
9086     /* VEX_W_0F2F_P_0 */
9087     { "vcomiss",        { XMScalar, EXdScalar } },
9088   },
9089   {
9090     /* VEX_W_0F2F_P_2 */
9091     { "vcomisd",        { XMScalar, EXqScalar } },
9092   },
9093   {
9094     /* VEX_W_0F50_M_0 */
9095     { "vmovmskpX",      { Gdq, XS } },
9096   },
9097   {
9098     /* VEX_W_0F51_P_0 */
9099     { "vsqrtps",        { XM, EXx } },
9100   },
9101   {
9102     /* VEX_W_0F51_P_1 */
9103     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9104   },
9105   {
9106     /* VEX_W_0F51_P_2  */
9107     { "vsqrtpd",        { XM, EXx } },
9108   },
9109   {
9110     /* VEX_W_0F51_P_3 */
9111     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9112   },
9113   {
9114     /* VEX_W_0F52_P_0 */
9115     { "vrsqrtps",       { XM, EXx } },
9116   },
9117   {
9118     /* VEX_W_0F52_P_1 */
9119     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9120   },
9121   {
9122     /* VEX_W_0F53_P_0  */
9123     { "vrcpps",         { XM, EXx } },
9124   },
9125   {
9126     /* VEX_W_0F53_P_1  */
9127     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9128   },
9129   {
9130     /* VEX_W_0F58_P_0  */
9131     { "vaddps",         { XM, Vex, EXx } },
9132   },
9133   {
9134     /* VEX_W_0F58_P_1  */
9135     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9136   },
9137   {
9138     /* VEX_W_0F58_P_2  */
9139     { "vaddpd",         { XM, Vex, EXx } },
9140   },
9141   {
9142     /* VEX_W_0F58_P_3  */
9143     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9144   },
9145   {
9146     /* VEX_W_0F59_P_0  */
9147     { "vmulps",         { XM, Vex, EXx } },
9148   },
9149   {
9150     /* VEX_W_0F59_P_1  */
9151     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9152   },
9153   {
9154     /* VEX_W_0F59_P_2  */
9155     { "vmulpd",         { XM, Vex, EXx } },
9156   },
9157   {
9158     /* VEX_W_0F59_P_3  */
9159     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9160   },
9161   {
9162     /* VEX_W_0F5A_P_0  */
9163     { "vcvtps2pd",      { XM, EXxmmq } },
9164   },
9165   {
9166     /* VEX_W_0F5A_P_1  */
9167     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9168   },
9169   {
9170     /* VEX_W_0F5A_P_3  */
9171     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9172   },
9173   {
9174     /* VEX_W_0F5B_P_0  */
9175     { "vcvtdq2ps",      { XM, EXx } },
9176   },
9177   {
9178     /* VEX_W_0F5B_P_1  */
9179     { "vcvttps2dq",     { XM, EXx } },
9180   },
9181   {
9182     /* VEX_W_0F5B_P_2  */
9183     { "vcvtps2dq",      { XM, EXx } },
9184   },
9185   {
9186     /* VEX_W_0F5C_P_0  */
9187     { "vsubps",         { XM, Vex, EXx } },
9188   },
9189   {
9190     /* VEX_W_0F5C_P_1  */
9191     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9192   },
9193   {
9194     /* VEX_W_0F5C_P_2  */
9195     { "vsubpd",         { XM, Vex, EXx } },
9196   },
9197   {
9198     /* VEX_W_0F5C_P_3  */
9199     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9200   },
9201   {
9202     /* VEX_W_0F5D_P_0  */
9203     { "vminps",         { XM, Vex, EXx } },
9204   },
9205   {
9206     /* VEX_W_0F5D_P_1  */
9207     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9208   },
9209   {
9210     /* VEX_W_0F5D_P_2  */
9211     { "vminpd",         { XM, Vex, EXx } },
9212   },
9213   {
9214     /* VEX_W_0F5D_P_3  */
9215     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9216   },
9217   {
9218     /* VEX_W_0F5E_P_0  */
9219     { "vdivps",         { XM, Vex, EXx } },
9220   },
9221   {
9222     /* VEX_W_0F5E_P_1  */
9223     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9224   },
9225   {
9226     /* VEX_W_0F5E_P_2  */
9227     { "vdivpd",         { XM, Vex, EXx } },
9228   },
9229   {
9230     /* VEX_W_0F5E_P_3  */
9231     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9232   },
9233   {
9234     /* VEX_W_0F5F_P_0  */
9235     { "vmaxps",         { XM, Vex, EXx } },
9236   },
9237   {
9238     /* VEX_W_0F5F_P_1  */
9239     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9240   },
9241   {
9242     /* VEX_W_0F5F_P_2  */
9243     { "vmaxpd",         { XM, Vex, EXx } },
9244   },
9245   {
9246     /* VEX_W_0F5F_P_3  */
9247     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9248   },
9249   {
9250     /* VEX_W_0F60_P_2  */
9251     { "vpunpcklbw",     { XM, Vex, EXx } },
9252   },
9253   {
9254     /* VEX_W_0F61_P_2  */
9255     { "vpunpcklwd",     { XM, Vex, EXx } },
9256   },
9257   {
9258     /* VEX_W_0F62_P_2  */
9259     { "vpunpckldq",     { XM, Vex, EXx } },
9260   },
9261   {
9262     /* VEX_W_0F63_P_2  */
9263     { "vpacksswb",      { XM, Vex, EXx } },
9264   },
9265   {
9266     /* VEX_W_0F64_P_2  */
9267     { "vpcmpgtb",       { XM, Vex, EXx } },
9268   },
9269   {
9270     /* VEX_W_0F65_P_2  */
9271     { "vpcmpgtw",       { XM, Vex, EXx } },
9272   },
9273   {
9274     /* VEX_W_0F66_P_2  */
9275     { "vpcmpgtd",       { XM, Vex, EXx } },
9276   },
9277   {
9278     /* VEX_W_0F67_P_2  */
9279     { "vpackuswb",      { XM, Vex, EXx } },
9280   },
9281   {
9282     /* VEX_W_0F68_P_2  */
9283     { "vpunpckhbw",     { XM, Vex, EXx } },
9284   },
9285   {
9286     /* VEX_W_0F69_P_2  */
9287     { "vpunpckhwd",     { XM, Vex, EXx } },
9288   },
9289   {
9290     /* VEX_W_0F6A_P_2  */
9291     { "vpunpckhdq",     { XM, Vex, EXx } },
9292   },
9293   {
9294     /* VEX_W_0F6B_P_2  */
9295     { "vpackssdw",      { XM, Vex, EXx } },
9296   },
9297   {
9298     /* VEX_W_0F6C_P_2  */
9299     { "vpunpcklqdq",    { XM, Vex, EXx } },
9300   },
9301   {
9302     /* VEX_W_0F6D_P_2  */
9303     { "vpunpckhqdq",    { XM, Vex, EXx } },
9304   },
9305   {
9306     /* VEX_W_0F6F_P_1  */
9307     { "vmovdqu",        { XM, EXx } },
9308   },
9309   {
9310     /* VEX_W_0F6F_P_2  */
9311     { "vmovdqa",        { XM, EXx } },
9312   },
9313   {
9314     /* VEX_W_0F70_P_1 */
9315     { "vpshufhw",       { XM, EXx, Ib } },
9316   },
9317   {
9318     /* VEX_W_0F70_P_2 */
9319     { "vpshufd",        { XM, EXx, Ib } },
9320   },
9321   {
9322     /* VEX_W_0F70_P_3 */
9323     { "vpshuflw",       { XM, EXx, Ib } },
9324   },
9325   {
9326     /* VEX_W_0F71_R_2_P_2  */
9327     { "vpsrlw",         { Vex, XS, Ib } },
9328   },
9329   {
9330     /* VEX_W_0F71_R_4_P_2  */
9331     { "vpsraw",         { Vex, XS, Ib } },
9332   },
9333   {
9334     /* VEX_W_0F71_R_6_P_2  */
9335     { "vpsllw",         { Vex, XS, Ib } },
9336   },
9337   {
9338     /* VEX_W_0F72_R_2_P_2  */
9339     { "vpsrld",         { Vex, XS, Ib } },
9340   },
9341   {
9342     /* VEX_W_0F72_R_4_P_2  */
9343     { "vpsrad",         { Vex, XS, Ib } },
9344   },
9345   {
9346     /* VEX_W_0F72_R_6_P_2  */
9347     { "vpslld",         { Vex, XS, Ib } },
9348   },
9349   {
9350     /* VEX_W_0F73_R_2_P_2  */
9351     { "vpsrlq",         { Vex, XS, Ib } },
9352   },
9353   {
9354     /* VEX_W_0F73_R_3_P_2  */
9355     { "vpsrldq",        { Vex, XS, Ib } },
9356   },
9357   {
9358     /* VEX_W_0F73_R_6_P_2  */
9359     { "vpsllq",         { Vex, XS, Ib } },
9360   },
9361   {
9362     /* VEX_W_0F73_R_7_P_2  */
9363     { "vpslldq",        { Vex, XS, Ib } },
9364   },
9365   {
9366     /* VEX_W_0F74_P_2 */
9367     { "vpcmpeqb",       { XM, Vex, EXx } },
9368   },
9369   {
9370     /* VEX_W_0F75_P_2 */
9371     { "vpcmpeqw",       { XM, Vex, EXx } },
9372   },
9373   {
9374     /* VEX_W_0F76_P_2 */
9375     { "vpcmpeqd",       { XM, Vex, EXx } },
9376   },
9377   {
9378     /* VEX_W_0F77_P_0 */
9379     { "",               { VZERO } },
9380   },
9381   {
9382     /* VEX_W_0F7C_P_2 */
9383     { "vhaddpd",        { XM, Vex, EXx } },
9384   },
9385   {
9386     /* VEX_W_0F7C_P_3 */
9387     { "vhaddps",        { XM, Vex, EXx } },
9388   },
9389   {
9390     /* VEX_W_0F7D_P_2 */
9391     { "vhsubpd",        { XM, Vex, EXx } },
9392   },
9393   {
9394     /* VEX_W_0F7D_P_3 */
9395     { "vhsubps",        { XM, Vex, EXx } },
9396   },
9397   {
9398     /* VEX_W_0F7E_P_1 */
9399     { "vmovq",          { XMScalar, EXqScalar } },
9400   },
9401   {
9402     /* VEX_W_0F7F_P_1 */
9403     { "vmovdqu",        { EXxS, XM } },
9404   },
9405   {
9406     /* VEX_W_0F7F_P_2 */
9407     { "vmovdqa",        { EXxS, XM } },
9408   },
9409   {
9410     /* VEX_W_0FAE_R_2_M_0 */
9411     { "vldmxcsr",       { Md } },
9412   },
9413   {
9414     /* VEX_W_0FAE_R_3_M_0 */
9415     { "vstmxcsr",       { Md } },
9416   },
9417   {
9418     /* VEX_W_0FC2_P_0 */
9419     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9420   },
9421   {
9422     /* VEX_W_0FC2_P_1 */
9423     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9424   },
9425   {
9426     /* VEX_W_0FC2_P_2 */
9427     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9428   },
9429   {
9430     /* VEX_W_0FC2_P_3 */
9431     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9432   },
9433   {
9434     /* VEX_W_0FC4_P_2 */
9435     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9436   },
9437   {
9438     /* VEX_W_0FC5_P_2 */
9439     { "vpextrw",        { Gdq, XS, Ib } },
9440   },
9441   {
9442     /* VEX_W_0FD0_P_2 */
9443     { "vaddsubpd",      { XM, Vex, EXx } },
9444   },
9445   {
9446     /* VEX_W_0FD0_P_3 */
9447     { "vaddsubps",      { XM, Vex, EXx } },
9448   },
9449   {
9450     /* VEX_W_0FD1_P_2 */
9451     { "vpsrlw",         { XM, Vex, EXxmm } },
9452   },
9453   {
9454     /* VEX_W_0FD2_P_2 */
9455     { "vpsrld",         { XM, Vex, EXxmm } },
9456   },
9457   {
9458     /* VEX_W_0FD3_P_2 */
9459     { "vpsrlq",         { XM, Vex, EXxmm } },
9460   },
9461   {
9462     /* VEX_W_0FD4_P_2 */
9463     { "vpaddq",         { XM, Vex, EXx } },
9464   },
9465   {
9466     /* VEX_W_0FD5_P_2 */
9467     { "vpmullw",        { XM, Vex, EXx } },
9468   },
9469   {
9470     /* VEX_W_0FD6_P_2 */
9471     { "vmovq",          { EXqScalarS, XMScalar } },
9472   },
9473   {
9474     /* VEX_W_0FD7_P_2_M_1 */
9475     { "vpmovmskb",      { Gdq, XS } },
9476   },
9477   {
9478     /* VEX_W_0FD8_P_2 */
9479     { "vpsubusb",       { XM, Vex, EXx } },
9480   },
9481   {
9482     /* VEX_W_0FD9_P_2 */
9483     { "vpsubusw",       { XM, Vex, EXx } },
9484   },
9485   {
9486     /* VEX_W_0FDA_P_2 */
9487     { "vpminub",        { XM, Vex, EXx } },
9488   },
9489   {
9490     /* VEX_W_0FDB_P_2 */
9491     { "vpand",          { XM, Vex, EXx } },
9492   },
9493   {
9494     /* VEX_W_0FDC_P_2 */
9495     { "vpaddusb",       { XM, Vex, EXx } },
9496   },
9497   {
9498     /* VEX_W_0FDD_P_2 */
9499     { "vpaddusw",       { XM, Vex, EXx } },
9500   },
9501   {
9502     /* VEX_W_0FDE_P_2 */
9503     { "vpmaxub",        { XM, Vex, EXx } },
9504   },
9505   {
9506     /* VEX_W_0FDF_P_2 */
9507     { "vpandn",         { XM, Vex, EXx } },
9508   },
9509   {
9510     /* VEX_W_0FE0_P_2  */
9511     { "vpavgb",         { XM, Vex, EXx } },
9512   },
9513   {
9514     /* VEX_W_0FE1_P_2  */
9515     { "vpsraw",         { XM, Vex, EXxmm } },
9516   },
9517   {
9518     /* VEX_W_0FE2_P_2  */
9519     { "vpsrad",         { XM, Vex, EXxmm } },
9520   },
9521   {
9522     /* VEX_W_0FE3_P_2  */
9523     { "vpavgw",         { XM, Vex, EXx } },
9524   },
9525   {
9526     /* VEX_W_0FE4_P_2  */
9527     { "vpmulhuw",       { XM, Vex, EXx } },
9528   },
9529   {
9530     /* VEX_W_0FE5_P_2  */
9531     { "vpmulhw",        { XM, Vex, EXx } },
9532   },
9533   {
9534     /* VEX_W_0FE6_P_1  */
9535     { "vcvtdq2pd",      { XM, EXxmmq } },
9536   },
9537   {
9538     /* VEX_W_0FE6_P_2  */
9539     { "vcvttpd2dq%XY",  { XMM, EXx } },
9540   },
9541   {
9542     /* VEX_W_0FE6_P_3  */
9543     { "vcvtpd2dq%XY",   { XMM, EXx } },
9544   },
9545   {
9546     /* VEX_W_0FE7_P_2_M_0 */
9547     { "vmovntdq",       { Mx, XM } },
9548   },
9549   {
9550     /* VEX_W_0FE8_P_2  */
9551     { "vpsubsb",        { XM, Vex, EXx } },
9552   },
9553   {
9554     /* VEX_W_0FE9_P_2  */
9555     { "vpsubsw",        { XM, Vex, EXx } },
9556   },
9557   {
9558     /* VEX_W_0FEA_P_2  */
9559     { "vpminsw",        { XM, Vex, EXx } },
9560   },
9561   {
9562     /* VEX_W_0FEB_P_2  */
9563     { "vpor",           { XM, Vex, EXx } },
9564   },
9565   {
9566     /* VEX_W_0FEC_P_2  */
9567     { "vpaddsb",        { XM, Vex, EXx } },
9568   },
9569   {
9570     /* VEX_W_0FED_P_2  */
9571     { "vpaddsw",        { XM, Vex, EXx } },
9572   },
9573   {
9574     /* VEX_W_0FEE_P_2  */
9575     { "vpmaxsw",        { XM, Vex, EXx } },
9576   },
9577   {
9578     /* VEX_W_0FEF_P_2  */
9579     { "vpxor",          { XM, Vex, EXx } },
9580   },
9581   {
9582     /* VEX_W_0FF0_P_3_M_0 */
9583     { "vlddqu",         { XM, M } },
9584   },
9585   {
9586     /* VEX_W_0FF1_P_2 */
9587     { "vpsllw",         { XM, Vex, EXxmm } },
9588   },
9589   {
9590     /* VEX_W_0FF2_P_2 */
9591     { "vpslld",         { XM, Vex, EXxmm } },
9592   },
9593   {
9594     /* VEX_W_0FF3_P_2 */
9595     { "vpsllq",         { XM, Vex, EXxmm } },
9596   },
9597   {
9598     /* VEX_W_0FF4_P_2 */
9599     { "vpmuludq",       { XM, Vex, EXx } },
9600   },
9601   {
9602     /* VEX_W_0FF5_P_2 */
9603     { "vpmaddwd",       { XM, Vex, EXx } },
9604   },
9605   {
9606     /* VEX_W_0FF6_P_2 */
9607     { "vpsadbw",        { XM, Vex, EXx } },
9608   },
9609   {
9610     /* VEX_W_0FF7_P_2 */
9611     { "vmaskmovdqu",    { XM, XS } },
9612   },
9613   {
9614     /* VEX_W_0FF8_P_2 */
9615     { "vpsubb",         { XM, Vex, EXx } },
9616   },
9617   {
9618     /* VEX_W_0FF9_P_2 */
9619     { "vpsubw",         { XM, Vex, EXx } },
9620   },
9621   {
9622     /* VEX_W_0FFA_P_2 */
9623     { "vpsubd",         { XM, Vex, EXx } },
9624   },
9625   {
9626     /* VEX_W_0FFB_P_2 */
9627     { "vpsubq",         { XM, Vex, EXx } },
9628   },
9629   {
9630     /* VEX_W_0FFC_P_2 */
9631     { "vpaddb",         { XM, Vex, EXx } },
9632   },
9633   {
9634     /* VEX_W_0FFD_P_2 */
9635     { "vpaddw",         { XM, Vex, EXx } },
9636   },
9637   {
9638     /* VEX_W_0FFE_P_2 */
9639     { "vpaddd",         { XM, Vex, EXx } },
9640   },
9641   {
9642     /* VEX_W_0F3800_P_2  */
9643     { "vpshufb",        { XM, Vex, EXx } },
9644   },
9645   {
9646     /* VEX_W_0F3801_P_2  */
9647     { "vphaddw",        { XM, Vex, EXx } },
9648   },
9649   {
9650     /* VEX_W_0F3802_P_2  */
9651     { "vphaddd",        { XM, Vex, EXx } },
9652   },
9653   {
9654     /* VEX_W_0F3803_P_2  */
9655     { "vphaddsw",       { XM, Vex, EXx } },
9656   },
9657   {
9658     /* VEX_W_0F3804_P_2  */
9659     { "vpmaddubsw",     { XM, Vex, EXx } },
9660   },
9661   {
9662     /* VEX_W_0F3805_P_2  */
9663     { "vphsubw",        { XM, Vex, EXx } },
9664   },
9665   {
9666     /* VEX_W_0F3806_P_2  */
9667     { "vphsubd",        { XM, Vex, EXx } },
9668   },
9669   {
9670     /* VEX_W_0F3807_P_2  */
9671     { "vphsubsw",       { XM, Vex, EXx } },
9672   },
9673   {
9674     /* VEX_W_0F3808_P_2  */
9675     { "vpsignb",        { XM, Vex, EXx } },
9676   },
9677   {
9678     /* VEX_W_0F3809_P_2  */
9679     { "vpsignw",        { XM, Vex, EXx } },
9680   },
9681   {
9682     /* VEX_W_0F380A_P_2  */
9683     { "vpsignd",        { XM, Vex, EXx } },
9684   },
9685   {
9686     /* VEX_W_0F380B_P_2  */
9687     { "vpmulhrsw",      { XM, Vex, EXx } },
9688   },
9689   {
9690     /* VEX_W_0F380C_P_2  */
9691     { "vpermilps",      { XM, Vex, EXx } },
9692   },
9693   {
9694     /* VEX_W_0F380D_P_2  */
9695     { "vpermilpd",      { XM, Vex, EXx } },
9696   },
9697   {
9698     /* VEX_W_0F380E_P_2  */
9699     { "vtestps",        { XM, EXx } },
9700   },
9701   {
9702     /* VEX_W_0F380F_P_2  */
9703     { "vtestpd",        { XM, EXx } },
9704   },
9705   {
9706     /* VEX_W_0F3816_P_2  */
9707     { "vpermps",        { XM, Vex, EXx } },
9708   },
9709   {
9710     /* VEX_W_0F3817_P_2 */
9711     { "vptest",         { XM, EXx } },
9712   },
9713   {
9714     /* VEX_W_0F3818_P_2 */
9715     { "vbroadcastss",   { XM, EXxmm_md } },
9716   },
9717   {
9718     /* VEX_W_0F3819_P_2 */
9719     { "vbroadcastsd",   { XM, EXxmm_mq } },
9720   },
9721   {
9722     /* VEX_W_0F381A_P_2_M_0 */
9723     { "vbroadcastf128", { XM, Mxmm } },
9724   },
9725   {
9726     /* VEX_W_0F381C_P_2 */
9727     { "vpabsb",         { XM, EXx } },
9728   },
9729   {
9730     /* VEX_W_0F381D_P_2 */
9731     { "vpabsw",         { XM, EXx } },
9732   },
9733   {
9734     /* VEX_W_0F381E_P_2 */
9735     { "vpabsd",         { XM, EXx } },
9736   },
9737   {
9738     /* VEX_W_0F3820_P_2 */
9739     { "vpmovsxbw",      { XM, EXxmmq } },
9740   },
9741   {
9742     /* VEX_W_0F3821_P_2 */
9743     { "vpmovsxbd",      { XM, EXxmmqd } },
9744   },
9745   {
9746     /* VEX_W_0F3822_P_2 */
9747     { "vpmovsxbq",      { XM, EXxmmdw } },
9748   },
9749   {
9750     /* VEX_W_0F3823_P_2 */
9751     { "vpmovsxwd",      { XM, EXxmmq } },
9752   },
9753   {
9754     /* VEX_W_0F3824_P_2 */
9755     { "vpmovsxwq",      { XM, EXxmmqd } },
9756   },
9757   {
9758     /* VEX_W_0F3825_P_2 */
9759     { "vpmovsxdq",      { XM, EXxmmq } },
9760   },
9761   {
9762     /* VEX_W_0F3828_P_2 */
9763     { "vpmuldq",        { XM, Vex, EXx } },
9764   },
9765   {
9766     /* VEX_W_0F3829_P_2 */
9767     { "vpcmpeqq",       { XM, Vex, EXx } },
9768   },
9769   {
9770     /* VEX_W_0F382A_P_2_M_0 */
9771     { "vmovntdqa",      { XM, Mx } },
9772   },
9773   {
9774     /* VEX_W_0F382B_P_2 */
9775     { "vpackusdw",      { XM, Vex, EXx } },
9776   },
9777   {
9778     /* VEX_W_0F382C_P_2_M_0 */
9779     { "vmaskmovps",     { XM, Vex, Mx } },
9780   },
9781   {
9782     /* VEX_W_0F382D_P_2_M_0 */
9783     { "vmaskmovpd",     { XM, Vex, Mx } },
9784   },
9785   {
9786     /* VEX_W_0F382E_P_2_M_0 */
9787     { "vmaskmovps",     { Mx, Vex, XM } },
9788   },
9789   {
9790     /* VEX_W_0F382F_P_2_M_0 */
9791     { "vmaskmovpd",     { Mx, Vex, XM } },
9792   },
9793   {
9794     /* VEX_W_0F3830_P_2 */
9795     { "vpmovzxbw",      { XM, EXxmmq } },
9796   },
9797   {
9798     /* VEX_W_0F3831_P_2 */
9799     { "vpmovzxbd",      { XM, EXxmmqd } },
9800   },
9801   {
9802     /* VEX_W_0F3832_P_2 */
9803     { "vpmovzxbq",      { XM, EXxmmdw } },
9804   },
9805   {
9806     /* VEX_W_0F3833_P_2 */
9807     { "vpmovzxwd",      { XM, EXxmmq } },
9808   },
9809   {
9810     /* VEX_W_0F3834_P_2 */
9811     { "vpmovzxwq",      { XM, EXxmmqd } },
9812   },
9813   {
9814     /* VEX_W_0F3835_P_2 */
9815     { "vpmovzxdq",      { XM, EXxmmq } },
9816   },
9817   {
9818     /* VEX_W_0F3836_P_2  */
9819     { "vpermd",         { XM, Vex, EXx } },
9820   },
9821   {
9822     /* VEX_W_0F3837_P_2 */
9823     { "vpcmpgtq",       { XM, Vex, EXx } },
9824   },
9825   {
9826     /* VEX_W_0F3838_P_2 */
9827     { "vpminsb",        { XM, Vex, EXx } },
9828   },
9829   {
9830     /* VEX_W_0F3839_P_2 */
9831     { "vpminsd",        { XM, Vex, EXx } },
9832   },
9833   {
9834     /* VEX_W_0F383A_P_2 */
9835     { "vpminuw",        { XM, Vex, EXx } },
9836   },
9837   {
9838     /* VEX_W_0F383B_P_2 */
9839     { "vpminud",        { XM, Vex, EXx } },
9840   },
9841   {
9842     /* VEX_W_0F383C_P_2 */
9843     { "vpmaxsb",        { XM, Vex, EXx } },
9844   },
9845   {
9846     /* VEX_W_0F383D_P_2 */
9847     { "vpmaxsd",        { XM, Vex, EXx } },
9848   },
9849   {
9850     /* VEX_W_0F383E_P_2 */
9851     { "vpmaxuw",        { XM, Vex, EXx } },
9852   },
9853   {
9854     /* VEX_W_0F383F_P_2 */
9855     { "vpmaxud",        { XM, Vex, EXx } },
9856   },
9857   {
9858     /* VEX_W_0F3840_P_2 */
9859     { "vpmulld",        { XM, Vex, EXx } },
9860   },
9861   {
9862     /* VEX_W_0F3841_P_2 */
9863     { "vphminposuw",    { XM, EXx } },
9864   },
9865   {
9866     /* VEX_W_0F3846_P_2 */
9867     { "vpsravd",        { XM, Vex, EXx } },
9868   },
9869   {
9870     /* VEX_W_0F3858_P_2 */
9871     { "vpbroadcastd", { XM, EXxmm_md } },
9872   },
9873   {
9874     /* VEX_W_0F3859_P_2 */
9875     { "vpbroadcastq",   { XM, EXxmm_mq } },
9876   },
9877   {
9878     /* VEX_W_0F385A_P_2_M_0 */
9879     { "vbroadcasti128", { XM, Mxmm } },
9880   },
9881   {
9882     /* VEX_W_0F3878_P_2 */
9883     { "vpbroadcastb",   { XM, EXxmm_mb } },
9884   },
9885   {
9886     /* VEX_W_0F3879_P_2 */
9887     { "vpbroadcastw",   { XM, EXxmm_mw } },
9888   },
9889   {
9890     /* VEX_W_0F38DB_P_2 */
9891     { "vaesimc",        { XM, EXx } },
9892   },
9893   {
9894     /* VEX_W_0F38DC_P_2 */
9895     { "vaesenc",        { XM, Vex128, EXx } },
9896   },
9897   {
9898     /* VEX_W_0F38DD_P_2 */
9899     { "vaesenclast",    { XM, Vex128, EXx } },
9900   },
9901   {
9902     /* VEX_W_0F38DE_P_2 */
9903     { "vaesdec",        { XM, Vex128, EXx } },
9904   },
9905   {
9906     /* VEX_W_0F38DF_P_2 */
9907     { "vaesdeclast",    { XM, Vex128, EXx } },
9908   },
9909   {
9910     /* VEX_W_0F3A00_P_2 */
9911     { Bad_Opcode },
9912     { "vpermq",         { XM, EXx, Ib } },
9913   },
9914   {
9915     /* VEX_W_0F3A01_P_2 */
9916     { Bad_Opcode },
9917     { "vpermpd",        { XM, EXx, Ib } },
9918   },
9919   {
9920     /* VEX_W_0F3A02_P_2 */
9921     { "vpblendd",       { XM, Vex, EXx, Ib } },
9922   },
9923   {
9924     /* VEX_W_0F3A04_P_2 */
9925     { "vpermilps",      { XM, EXx, Ib } },
9926   },
9927   {
9928     /* VEX_W_0F3A05_P_2 */
9929     { "vpermilpd",      { XM, EXx, Ib } },
9930   },
9931   {
9932     /* VEX_W_0F3A06_P_2 */
9933     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
9934   },
9935   {
9936     /* VEX_W_0F3A08_P_2 */
9937     { "vroundps",       { XM, EXx, Ib } },
9938   },
9939   {
9940     /* VEX_W_0F3A09_P_2 */
9941     { "vroundpd",       { XM, EXx, Ib } },
9942   },
9943   {
9944     /* VEX_W_0F3A0A_P_2 */
9945     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
9946   },
9947   {
9948     /* VEX_W_0F3A0B_P_2 */
9949     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
9950   },
9951   {
9952     /* VEX_W_0F3A0C_P_2 */
9953     { "vblendps",       { XM, Vex, EXx, Ib } },
9954   },
9955   {
9956     /* VEX_W_0F3A0D_P_2 */
9957     { "vblendpd",       { XM, Vex, EXx, Ib } },
9958   },
9959   {
9960     /* VEX_W_0F3A0E_P_2 */
9961     { "vpblendw",       { XM, Vex, EXx, Ib } },
9962   },
9963   {
9964     /* VEX_W_0F3A0F_P_2 */
9965     { "vpalignr",       { XM, Vex, EXx, Ib } },
9966   },
9967   {
9968     /* VEX_W_0F3A14_P_2 */
9969     { "vpextrb",        { Edqb, XM, Ib } },
9970   },
9971   {
9972     /* VEX_W_0F3A15_P_2 */
9973     { "vpextrw",        { Edqw, XM, Ib } },
9974   },
9975   {
9976     /* VEX_W_0F3A18_P_2 */
9977     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
9978   },
9979   {
9980     /* VEX_W_0F3A19_P_2 */
9981     { "vextractf128",   { EXxmm, XM, Ib } },
9982   },
9983   {
9984     /* VEX_W_0F3A20_P_2 */
9985     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
9986   },
9987   {
9988     /* VEX_W_0F3A21_P_2 */
9989     { "vinsertps",      { XM, Vex128, EXd, Ib } },
9990   },
9991   {
9992     /* VEX_W_0F3A38_P_2 */
9993     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
9994   },
9995   {
9996     /* VEX_W_0F3A39_P_2 */
9997     { "vextracti128",   { EXxmm, XM, Ib } },
9998   },
9999   {
10000     /* VEX_W_0F3A40_P_2 */
10001     { "vdpps",          { XM, Vex, EXx, Ib } },
10002   },
10003   {
10004     /* VEX_W_0F3A41_P_2 */
10005     { "vdppd",          { XM, Vex128, EXx, Ib } },
10006   },
10007   {
10008     /* VEX_W_0F3A42_P_2 */
10009     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10010   },
10011   {
10012     /* VEX_W_0F3A44_P_2 */
10013     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10014   },
10015   {
10016     /* VEX_W_0F3A46_P_2 */
10017     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
10018   },
10019   {
10020     /* VEX_W_0F3A48_P_2 */
10021     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10022     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10023   },
10024   {
10025     /* VEX_W_0F3A49_P_2 */
10026     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10027     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10028   },
10029   {
10030     /* VEX_W_0F3A4A_P_2 */
10031     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10032   },
10033   {
10034     /* VEX_W_0F3A4B_P_2 */
10035     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10036   },
10037   {
10038     /* VEX_W_0F3A4C_P_2 */
10039     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
10040   },
10041   {
10042     /* VEX_W_0F3A60_P_2 */
10043     { "vpcmpestrm",     { XM, EXx, Ib } },
10044   },
10045   {
10046     /* VEX_W_0F3A61_P_2 */
10047     { "vpcmpestri",     { XM, EXx, Ib } },
10048   },
10049   {
10050     /* VEX_W_0F3A62_P_2 */
10051     { "vpcmpistrm",     { XM, EXx, Ib } },
10052   },
10053   {
10054     /* VEX_W_0F3A63_P_2 */
10055     { "vpcmpistri",     { XM, EXx, Ib } },
10056   },
10057   {
10058     /* VEX_W_0F3ADF_P_2 */
10059     { "vaeskeygenassist", { XM, EXx, Ib } },
10060   },
10061 };
10062
10063 static const struct dis386 mod_table[][2] = {
10064   {
10065     /* MOD_8D */
10066     { "leaS",           { Gv, M } },
10067   },
10068   {
10069     /* MOD_0F01_REG_0 */
10070     { X86_64_TABLE (X86_64_0F01_REG_0) },
10071     { RM_TABLE (RM_0F01_REG_0) },
10072   },
10073   {
10074     /* MOD_0F01_REG_1 */
10075     { X86_64_TABLE (X86_64_0F01_REG_1) },
10076     { RM_TABLE (RM_0F01_REG_1) },
10077   },
10078   {
10079     /* MOD_0F01_REG_2 */
10080     { X86_64_TABLE (X86_64_0F01_REG_2) },
10081     { RM_TABLE (RM_0F01_REG_2) },
10082   },
10083   {
10084     /* MOD_0F01_REG_3 */
10085     { X86_64_TABLE (X86_64_0F01_REG_3) },
10086     { RM_TABLE (RM_0F01_REG_3) },
10087   },
10088   {
10089     /* MOD_0F01_REG_7 */
10090     { "invlpg",         { Mb } },
10091     { RM_TABLE (RM_0F01_REG_7) },
10092   },
10093   {
10094     /* MOD_0F12_PREFIX_0 */
10095     { "movlps",         { XM, EXq } },
10096     { "movhlps",        { XM, EXq } },
10097   },
10098   {
10099     /* MOD_0F13 */
10100     { "movlpX",         { EXq, XM } },
10101   },
10102   {
10103     /* MOD_0F16_PREFIX_0 */
10104     { "movhps",         { XM, EXq } },
10105     { "movlhps",        { XM, EXq } },
10106   },
10107   {
10108     /* MOD_0F17 */
10109     { "movhpX",         { EXq, XM } },
10110   },
10111   {
10112     /* MOD_0F18_REG_0 */
10113     { "prefetchnta",    { Mb } },
10114   },
10115   {
10116     /* MOD_0F18_REG_1 */
10117     { "prefetcht0",     { Mb } },
10118   },
10119   {
10120     /* MOD_0F18_REG_2 */
10121     { "prefetcht1",     { Mb } },
10122   },
10123   {
10124     /* MOD_0F18_REG_3 */
10125     { "prefetcht2",     { Mb } },
10126   },
10127   {
10128     /* MOD_0F20 */
10129     { Bad_Opcode },
10130     { "movZ",           { Rm, Cm } },
10131   },
10132   {
10133     /* MOD_0F21 */
10134     { Bad_Opcode },
10135     { "movZ",           { Rm, Dm } },
10136   },
10137   {
10138     /* MOD_0F22 */
10139     { Bad_Opcode },
10140     { "movZ",           { Cm, Rm } },
10141   },
10142   {
10143     /* MOD_0F23 */
10144     { Bad_Opcode },
10145     { "movZ",           { Dm, Rm } },
10146   },
10147   {
10148     /* MOD_0F24 */
10149     { Bad_Opcode },
10150     { "movL",           { Rd, Td } },
10151   },
10152   {
10153     /* MOD_0F26 */
10154     { Bad_Opcode },
10155     { "movL",           { Td, Rd } },
10156   },
10157   {
10158     /* MOD_0F2B_PREFIX_0 */
10159     {"movntps",         { Mx, XM } },
10160   },
10161   {
10162     /* MOD_0F2B_PREFIX_1 */
10163     {"movntss",         { Md, XM } },
10164   },
10165   {
10166     /* MOD_0F2B_PREFIX_2 */
10167     {"movntpd",         { Mx, XM } },
10168   },
10169   {
10170     /* MOD_0F2B_PREFIX_3 */
10171     {"movntsd",         { Mq, XM } },
10172   },
10173   {
10174     /* MOD_0F51 */
10175     { Bad_Opcode },
10176     { "movmskpX",       { Gdq, XS } },
10177   },
10178   {
10179     /* MOD_0F71_REG_2 */
10180     { Bad_Opcode },
10181     { "psrlw",          { MS, Ib } },
10182   },
10183   {
10184     /* MOD_0F71_REG_4 */
10185     { Bad_Opcode },
10186     { "psraw",          { MS, Ib } },
10187   },
10188   {
10189     /* MOD_0F71_REG_6 */
10190     { Bad_Opcode },
10191     { "psllw",          { MS, Ib } },
10192   },
10193   {
10194     /* MOD_0F72_REG_2 */
10195     { Bad_Opcode },
10196     { "psrld",          { MS, Ib } },
10197   },
10198   {
10199     /* MOD_0F72_REG_4 */
10200     { Bad_Opcode },
10201     { "psrad",          { MS, Ib } },
10202   },
10203   {
10204     /* MOD_0F72_REG_6 */
10205     { Bad_Opcode },
10206     { "pslld",          { MS, Ib } },
10207   },
10208   {
10209     /* MOD_0F73_REG_2 */
10210     { Bad_Opcode },
10211     { "psrlq",          { MS, Ib } },
10212   },
10213   {
10214     /* MOD_0F73_REG_3 */
10215     { Bad_Opcode },
10216     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10217   },
10218   {
10219     /* MOD_0F73_REG_6 */
10220     { Bad_Opcode },
10221     { "psllq",          { MS, Ib } },
10222   },
10223   {
10224     /* MOD_0F73_REG_7 */
10225     { Bad_Opcode },
10226     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10227   },
10228   {
10229     /* MOD_0FAE_REG_0 */
10230     { "fxsave",         { FXSAVE } },
10231     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10232   },
10233   {
10234     /* MOD_0FAE_REG_1 */
10235     { "fxrstor",        { FXSAVE } },
10236     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10237   },
10238   {
10239     /* MOD_0FAE_REG_2 */
10240     { "ldmxcsr",        { Md } },
10241     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10242   },
10243   {
10244     /* MOD_0FAE_REG_3 */
10245     { "stmxcsr",        { Md } },
10246     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10247   },
10248   {
10249     /* MOD_0FAE_REG_4 */
10250     { "xsave",          { FXSAVE } },
10251   },
10252   {
10253     /* MOD_0FAE_REG_5 */
10254     { "xrstor",         { FXSAVE } },
10255     { RM_TABLE (RM_0FAE_REG_5) },
10256   },
10257   {
10258     /* MOD_0FAE_REG_6 */
10259     { "xsaveopt",       { FXSAVE } },
10260     { RM_TABLE (RM_0FAE_REG_6) },
10261   },
10262   {
10263     /* MOD_0FAE_REG_7 */
10264     { "clflush",        { Mb } },
10265     { RM_TABLE (RM_0FAE_REG_7) },
10266   },
10267   {
10268     /* MOD_0FB2 */
10269     { "lssS",           { Gv, Mp } },
10270   },
10271   {
10272     /* MOD_0FB4 */
10273     { "lfsS",           { Gv, Mp } },
10274   },
10275   {
10276     /* MOD_0FB5 */
10277     { "lgsS",           { Gv, Mp } },
10278   },
10279   {
10280     /* MOD_0FC7_REG_6 */
10281     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10282     { "rdrand",         { Ev } },
10283   },
10284   {
10285     /* MOD_0FC7_REG_7 */
10286     { "vmptrst",        { Mq } },
10287   },
10288   {
10289     /* MOD_0FD7 */
10290     { Bad_Opcode },
10291     { "pmovmskb",       { Gdq, MS } },
10292   },
10293   {
10294     /* MOD_0FE7_PREFIX_2 */
10295     { "movntdq",        { Mx, XM } },
10296   },
10297   {
10298     /* MOD_0FF0_PREFIX_3 */
10299     { "lddqu",          { XM, M } },
10300   },
10301   {
10302     /* MOD_0F382A_PREFIX_2 */
10303     { "movntdqa",       { XM, Mx } },
10304   },
10305   {
10306     /* MOD_62_32BIT */
10307     { "bound{S|}",      { Gv, Ma } },
10308   },
10309   {
10310     /* MOD_C4_32BIT */
10311     { "lesS",           { Gv, Mp } },
10312     { VEX_C4_TABLE (VEX_0F) },
10313   },
10314   {
10315     /* MOD_C5_32BIT */
10316     { "ldsS",           { Gv, Mp } },
10317     { VEX_C5_TABLE (VEX_0F) },
10318   },
10319   {
10320     /* MOD_VEX_0F12_PREFIX_0 */
10321     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10322     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10323   },
10324   {
10325     /* MOD_VEX_0F13 */
10326     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10327   },
10328   {
10329     /* MOD_VEX_0F16_PREFIX_0 */
10330     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10331     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10332   },
10333   {
10334     /* MOD_VEX_0F17 */
10335     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10336   },
10337   {
10338     /* MOD_VEX_0F2B */
10339     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10340   },
10341   {
10342     /* MOD_VEX_0F50 */
10343     { Bad_Opcode },
10344     { VEX_W_TABLE (VEX_W_0F50_M_0) },
10345   },
10346   {
10347     /* MOD_VEX_0F71_REG_2 */
10348     { Bad_Opcode },
10349     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10350   },
10351   {
10352     /* MOD_VEX_0F71_REG_4 */
10353     { Bad_Opcode },
10354     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10355   },
10356   {
10357     /* MOD_VEX_0F71_REG_6 */
10358     { Bad_Opcode },
10359     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10360   },
10361   {
10362     /* MOD_VEX_0F72_REG_2 */
10363     { Bad_Opcode },
10364     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10365   },
10366   {
10367     /* MOD_VEX_0F72_REG_4 */
10368     { Bad_Opcode },
10369     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10370   },
10371   {
10372     /* MOD_VEX_0F72_REG_6 */
10373     { Bad_Opcode },
10374     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10375   },
10376   {
10377     /* MOD_VEX_0F73_REG_2 */
10378     { Bad_Opcode },
10379     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10380   },
10381   {
10382     /* MOD_VEX_0F73_REG_3 */
10383     { Bad_Opcode },
10384     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10385   },
10386   {
10387     /* MOD_VEX_0F73_REG_6 */
10388     { Bad_Opcode },
10389     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10390   },
10391   {
10392     /* MOD_VEX_0F73_REG_7 */
10393     { Bad_Opcode },
10394     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10395   },
10396   {
10397     /* MOD_VEX_0FAE_REG_2 */
10398     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10399   },
10400   {
10401     /* MOD_VEX_0FAE_REG_3 */
10402     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10403   },
10404   {
10405     /* MOD_VEX_0FD7_PREFIX_2 */
10406     { Bad_Opcode },
10407     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
10408   },
10409   {
10410     /* MOD_VEX_0FE7_PREFIX_2 */
10411     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10412   },
10413   {
10414     /* MOD_VEX_0FF0_PREFIX_3 */
10415     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10416   },
10417   {
10418     /* MOD_VEX_0F381A_PREFIX_2 */
10419     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10420   },
10421   {
10422     /* MOD_VEX_0F382A_PREFIX_2 */
10423     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
10424   },
10425   {
10426     /* MOD_VEX_0F382C_PREFIX_2 */
10427     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10428   },
10429   {
10430     /* MOD_VEX_0F382D_PREFIX_2 */
10431     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10432   },
10433   {
10434     /* MOD_VEX_0F382E_PREFIX_2 */
10435     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10436   },
10437   {
10438     /* MOD_VEX_0F382F_PREFIX_2 */
10439     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10440   },
10441   {
10442     /* MOD_VEX_0F385A_PREFIX_2 */
10443     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10444   },
10445   {
10446     /* MOD_VEX_0F388C_PREFIX_2 */
10447     { "vpmaskmov%LW",   { XM, Vex, Mx } },
10448   },
10449   {
10450     /* MOD_VEX_0F388E_PREFIX_2 */
10451     { "vpmaskmov%LW",   { Mx, Vex, XM } },
10452   },
10453 };
10454
10455 static const struct dis386 rm_table[][8] = {
10456   {
10457     /* RM_0F01_REG_0 */
10458     { Bad_Opcode },
10459     { "vmcall",         { Skip_MODRM } },
10460     { "vmlaunch",       { Skip_MODRM } },
10461     { "vmresume",       { Skip_MODRM } },
10462     { "vmxoff",         { Skip_MODRM } },
10463   },
10464   {
10465     /* RM_0F01_REG_1 */
10466     { "monitor",        { { OP_Monitor, 0 } } },
10467     { "mwait",          { { OP_Mwait, 0 } } },
10468   },
10469   {
10470     /* RM_0F01_REG_2 */
10471     { "xgetbv",         { Skip_MODRM } },
10472     { "xsetbv",         { Skip_MODRM } },
10473   },
10474   {
10475     /* RM_0F01_REG_3 */
10476     { "vmrun",          { Skip_MODRM } },
10477     { "vmmcall",        { Skip_MODRM } },
10478     { "vmload",         { Skip_MODRM } },
10479     { "vmsave",         { Skip_MODRM } },
10480     { "stgi",           { Skip_MODRM } },
10481     { "clgi",           { Skip_MODRM } },
10482     { "skinit",         { Skip_MODRM } },
10483     { "invlpga",        { Skip_MODRM } },
10484   },
10485   {
10486     /* RM_0F01_REG_7 */
10487     { "swapgs",         { Skip_MODRM } },
10488     { "rdtscp",         { Skip_MODRM } },
10489   },
10490   {
10491     /* RM_0FAE_REG_5 */
10492     { "lfence",         { Skip_MODRM } },
10493   },
10494   {
10495     /* RM_0FAE_REG_6 */
10496     { "mfence",         { Skip_MODRM } },
10497   },
10498   {
10499     /* RM_0FAE_REG_7 */
10500     { "sfence",         { Skip_MODRM } },
10501   },
10502 };
10503
10504 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10505
10506 /* We use the high bit to indicate different name for the same
10507    prefix.  */
10508 #define ADDR16_PREFIX   (0x67 | 0x100)
10509 #define ADDR32_PREFIX   (0x67 | 0x200)
10510 #define DATA16_PREFIX   (0x66 | 0x100)
10511 #define DATA32_PREFIX   (0x66 | 0x200)
10512 #define REP_PREFIX      (0xf3 | 0x100)
10513
10514 static int
10515 ckprefix (void)
10516 {
10517   int newrex, i, length;
10518   rex = 0;
10519   rex_ignored = 0;
10520   prefixes = 0;
10521   used_prefixes = 0;
10522   rex_used = 0;
10523   last_lock_prefix = -1;
10524   last_repz_prefix = -1;
10525   last_repnz_prefix = -1;
10526   last_data_prefix = -1;
10527   last_addr_prefix = -1;
10528   last_rex_prefix = -1;
10529   last_seg_prefix = -1;
10530   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10531     all_prefixes[i] = 0;
10532   i = 0;
10533   length = 0;
10534   /* The maximum instruction length is 15bytes.  */
10535   while (length < MAX_CODE_LENGTH - 1)
10536     {
10537       FETCH_DATA (the_info, codep + 1);
10538       newrex = 0;
10539       switch (*codep)
10540         {
10541         /* REX prefixes family.  */
10542         case 0x40:
10543         case 0x41:
10544         case 0x42:
10545         case 0x43:
10546         case 0x44:
10547         case 0x45:
10548         case 0x46:
10549         case 0x47:
10550         case 0x48:
10551         case 0x49:
10552         case 0x4a:
10553         case 0x4b:
10554         case 0x4c:
10555         case 0x4d:
10556         case 0x4e:
10557         case 0x4f:
10558           if (address_mode == mode_64bit)
10559             newrex = *codep;
10560           else
10561             return 1;
10562           last_rex_prefix = i;
10563           break;
10564         case 0xf3:
10565           prefixes |= PREFIX_REPZ;
10566           last_repz_prefix = i;
10567           break;
10568         case 0xf2:
10569           prefixes |= PREFIX_REPNZ;
10570           last_repnz_prefix = i;
10571           break;
10572         case 0xf0:
10573           prefixes |= PREFIX_LOCK;
10574           last_lock_prefix = i;
10575           break;
10576         case 0x2e:
10577           prefixes |= PREFIX_CS;
10578           last_seg_prefix = i;
10579           break;
10580         case 0x36:
10581           prefixes |= PREFIX_SS;
10582           last_seg_prefix = i;
10583           break;
10584         case 0x3e:
10585           prefixes |= PREFIX_DS;
10586           last_seg_prefix = i;
10587           break;
10588         case 0x26:
10589           prefixes |= PREFIX_ES;
10590           last_seg_prefix = i;
10591           break;
10592         case 0x64:
10593           prefixes |= PREFIX_FS;
10594           last_seg_prefix = i;
10595           break;
10596         case 0x65:
10597           prefixes |= PREFIX_GS;
10598           last_seg_prefix = i;
10599           break;
10600         case 0x66:
10601           prefixes |= PREFIX_DATA;
10602           last_data_prefix = i;
10603           break;
10604         case 0x67:
10605           prefixes |= PREFIX_ADDR;
10606           last_addr_prefix = i;
10607           break;
10608         case FWAIT_OPCODE:
10609           /* fwait is really an instruction.  If there are prefixes
10610              before the fwait, they belong to the fwait, *not* to the
10611              following instruction.  */
10612           if (prefixes || rex)
10613             {
10614               prefixes |= PREFIX_FWAIT;
10615               codep++;
10616               return 1;
10617             }
10618           prefixes = PREFIX_FWAIT;
10619           break;
10620         default:
10621           return 1;
10622         }
10623       /* Rex is ignored when followed by another prefix.  */
10624       if (rex)
10625         {
10626           rex_used = rex;
10627           return 1;
10628         }
10629       if (*codep != FWAIT_OPCODE)
10630         all_prefixes[i++] = *codep;
10631       rex = newrex;
10632       codep++;
10633       length++;
10634     }
10635   return 0;
10636 }
10637
10638 static int
10639 seg_prefix (int pref)
10640 {
10641   switch (pref)
10642     {
10643     case 0x2e:
10644       return PREFIX_CS;
10645     case 0x36:
10646       return PREFIX_SS;
10647     case 0x3e:
10648       return PREFIX_DS;
10649     case 0x26:
10650       return PREFIX_ES;
10651     case 0x64:
10652       return PREFIX_FS;
10653     case 0x65:
10654       return PREFIX_GS;
10655     default:
10656       return 0;
10657     }
10658 }
10659
10660 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10661    prefix byte.  */
10662
10663 static const char *
10664 prefix_name (int pref, int sizeflag)
10665 {
10666   static const char *rexes [16] =
10667     {
10668       "rex",            /* 0x40 */
10669       "rex.B",          /* 0x41 */
10670       "rex.X",          /* 0x42 */
10671       "rex.XB",         /* 0x43 */
10672       "rex.R",          /* 0x44 */
10673       "rex.RB",         /* 0x45 */
10674       "rex.RX",         /* 0x46 */
10675       "rex.RXB",        /* 0x47 */
10676       "rex.W",          /* 0x48 */
10677       "rex.WB",         /* 0x49 */
10678       "rex.WX",         /* 0x4a */
10679       "rex.WXB",        /* 0x4b */
10680       "rex.WR",         /* 0x4c */
10681       "rex.WRB",        /* 0x4d */
10682       "rex.WRX",        /* 0x4e */
10683       "rex.WRXB",       /* 0x4f */
10684     };
10685
10686   switch (pref)
10687     {
10688     /* REX prefixes family.  */
10689     case 0x40:
10690     case 0x41:
10691     case 0x42:
10692     case 0x43:
10693     case 0x44:
10694     case 0x45:
10695     case 0x46:
10696     case 0x47:
10697     case 0x48:
10698     case 0x49:
10699     case 0x4a:
10700     case 0x4b:
10701     case 0x4c:
10702     case 0x4d:
10703     case 0x4e:
10704     case 0x4f:
10705       return rexes [pref - 0x40];
10706     case 0xf3:
10707       return "repz";
10708     case 0xf2:
10709       return "repnz";
10710     case 0xf0:
10711       return "lock";
10712     case 0x2e:
10713       return "cs";
10714     case 0x36:
10715       return "ss";
10716     case 0x3e:
10717       return "ds";
10718     case 0x26:
10719       return "es";
10720     case 0x64:
10721       return "fs";
10722     case 0x65:
10723       return "gs";
10724     case 0x66:
10725       return (sizeflag & DFLAG) ? "data16" : "data32";
10726     case 0x67:
10727       if (address_mode == mode_64bit)
10728         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10729       else
10730         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10731     case FWAIT_OPCODE:
10732       return "fwait";
10733     case ADDR16_PREFIX:
10734       return "addr16";
10735     case ADDR32_PREFIX:
10736       return "addr32";
10737     case DATA16_PREFIX:
10738       return "data16";
10739     case DATA32_PREFIX:
10740       return "data32";
10741     case REP_PREFIX:
10742       return "rep";
10743     default:
10744       return NULL;
10745     }
10746 }
10747
10748 static char op_out[MAX_OPERANDS][100];
10749 static int op_ad, op_index[MAX_OPERANDS];
10750 static int two_source_ops;
10751 static bfd_vma op_address[MAX_OPERANDS];
10752 static bfd_vma op_riprel[MAX_OPERANDS];
10753 static bfd_vma start_pc;
10754
10755 /*
10756  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10757  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10758  *   section of the "Virtual 8086 Mode" chapter.)
10759  * 'pc' should be the address of this instruction, it will
10760  *   be used to print the target address if this is a relative jump or call
10761  * The function returns the length of this instruction in bytes.
10762  */
10763
10764 static char intel_syntax;
10765 static char intel_mnemonic = !SYSV386_COMPAT;
10766 static char open_char;
10767 static char close_char;
10768 static char separator_char;
10769 static char scale_char;
10770
10771 /* Here for backwards compatibility.  When gdb stops using
10772    print_insn_i386_att and print_insn_i386_intel these functions can
10773    disappear, and print_insn_i386 be merged into print_insn.  */
10774 int
10775 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10776 {
10777   intel_syntax = 0;
10778
10779   return print_insn (pc, info);
10780 }
10781
10782 int
10783 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10784 {
10785   intel_syntax = 1;
10786
10787   return print_insn (pc, info);
10788 }
10789
10790 int
10791 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10792 {
10793   intel_syntax = -1;
10794
10795   return print_insn (pc, info);
10796 }
10797
10798 void
10799 print_i386_disassembler_options (FILE *stream)
10800 {
10801   fprintf (stream, _("\n\
10802 The following i386/x86-64 specific disassembler options are supported for use\n\
10803 with the -M switch (multiple options should be separated by commas):\n"));
10804
10805   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10806   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10807   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10808   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10809   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10810   fprintf (stream, _("  att-mnemonic\n"
10811                      "              Display instruction in AT&T mnemonic\n"));
10812   fprintf (stream, _("  intel-mnemonic\n"
10813                      "              Display instruction in Intel mnemonic\n"));
10814   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10815   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10816   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10817   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10818   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10819   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10820 }
10821
10822 /* Bad opcode.  */
10823 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10824
10825 /* Get a pointer to struct dis386 with a valid name.  */
10826
10827 static const struct dis386 *
10828 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10829 {
10830   int vindex, vex_table_index;
10831
10832   if (dp->name != NULL)
10833     return dp;
10834
10835   switch (dp->op[0].bytemode)
10836     {
10837     case USE_REG_TABLE:
10838       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10839       break;
10840
10841     case USE_MOD_TABLE:
10842       vindex = modrm.mod == 0x3 ? 1 : 0;
10843       dp = &mod_table[dp->op[1].bytemode][vindex];
10844       break;
10845
10846     case USE_RM_TABLE:
10847       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10848       break;
10849
10850     case USE_PREFIX_TABLE:
10851       if (need_vex)
10852         {
10853           /* The prefix in VEX is implicit.  */
10854           switch (vex.prefix)
10855             {
10856             case 0:
10857               vindex = 0;
10858               break;
10859             case REPE_PREFIX_OPCODE:
10860               vindex = 1;
10861               break;
10862             case DATA_PREFIX_OPCODE:
10863               vindex = 2;
10864               break;
10865             case REPNE_PREFIX_OPCODE:
10866               vindex = 3;
10867               break;
10868             default:
10869               abort ();
10870               break;
10871             }
10872         }
10873       else
10874         {
10875           vindex = 0;
10876           used_prefixes |= (prefixes & PREFIX_REPZ);
10877           if (prefixes & PREFIX_REPZ)
10878             {
10879               vindex = 1;
10880               all_prefixes[last_repz_prefix] = 0;
10881             }
10882           else
10883             {
10884               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10885                  PREFIX_DATA.  */
10886               used_prefixes |= (prefixes & PREFIX_REPNZ);
10887               if (prefixes & PREFIX_REPNZ)
10888                 {
10889                   vindex = 3;
10890                   all_prefixes[last_repnz_prefix] = 0;
10891                 }
10892               else
10893                 {
10894                   used_prefixes |= (prefixes & PREFIX_DATA);
10895                   if (prefixes & PREFIX_DATA)
10896                     {
10897                       vindex = 2;
10898                       all_prefixes[last_data_prefix] = 0;
10899                     }
10900                 }
10901             }
10902         }
10903       dp = &prefix_table[dp->op[1].bytemode][vindex];
10904       break;
10905
10906     case USE_X86_64_TABLE:
10907       vindex = address_mode == mode_64bit ? 1 : 0;
10908       dp = &x86_64_table[dp->op[1].bytemode][vindex];
10909       break;
10910
10911     case USE_3BYTE_TABLE:
10912       FETCH_DATA (info, codep + 2);
10913       vindex = *codep++;
10914       dp = &three_byte_table[dp->op[1].bytemode][vindex];
10915       modrm.mod = (*codep >> 6) & 3;
10916       modrm.reg = (*codep >> 3) & 7;
10917       modrm.rm = *codep & 7;
10918       break;
10919
10920     case USE_VEX_LEN_TABLE:
10921       if (!need_vex)
10922         abort ();
10923
10924       switch (vex.length)
10925         {
10926         case 128:
10927           vindex = 0;
10928           break;
10929         case 256:
10930           vindex = 1;
10931           break;
10932         default:
10933           abort ();
10934           break;
10935         }
10936
10937       dp = &vex_len_table[dp->op[1].bytemode][vindex];
10938       break;
10939
10940     case USE_XOP_8F_TABLE:
10941       FETCH_DATA (info, codep + 3);
10942       /* All bits in the REX prefix are ignored.  */
10943       rex_ignored = rex;
10944       rex = ~(*codep >> 5) & 0x7;
10945
10946       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
10947       switch ((*codep & 0x1f))
10948         {
10949         default:
10950           dp = &bad_opcode;
10951           return dp;
10952         case 0x8:
10953           vex_table_index = XOP_08;
10954           break;
10955         case 0x9:
10956           vex_table_index = XOP_09;
10957           break;
10958         case 0xa:
10959           vex_table_index = XOP_0A;
10960           break;
10961         }
10962       codep++;
10963       vex.w = *codep & 0x80;
10964       if (vex.w && address_mode == mode_64bit)
10965         rex |= REX_W;
10966
10967       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10968       if (address_mode != mode_64bit
10969           && vex.register_specifier > 0x7)
10970         {
10971           dp = &bad_opcode;
10972           return dp;
10973         }
10974
10975       vex.length = (*codep & 0x4) ? 256 : 128;
10976       switch ((*codep & 0x3))
10977         {
10978         case 0:
10979           vex.prefix = 0;
10980           break;
10981         case 1:
10982           vex.prefix = DATA_PREFIX_OPCODE;
10983           break;
10984         case 2:
10985           vex.prefix = REPE_PREFIX_OPCODE;
10986           break;
10987         case 3:
10988           vex.prefix = REPNE_PREFIX_OPCODE;
10989           break;
10990         }
10991       need_vex = 1;
10992       need_vex_reg = 1;
10993       codep++;
10994       vindex = *codep++;
10995       dp = &xop_table[vex_table_index][vindex];
10996
10997       FETCH_DATA (info, codep + 1);
10998       modrm.mod = (*codep >> 6) & 3;
10999       modrm.reg = (*codep >> 3) & 7;
11000       modrm.rm = *codep & 7;
11001       break;
11002
11003     case USE_VEX_C4_TABLE:
11004       FETCH_DATA (info, codep + 3);
11005       /* All bits in the REX prefix are ignored.  */
11006       rex_ignored = rex;
11007       rex = ~(*codep >> 5) & 0x7;
11008       switch ((*codep & 0x1f))
11009         {
11010         default:
11011           dp = &bad_opcode;
11012           return dp;
11013         case 0x1:
11014           vex_table_index = VEX_0F;
11015           break;
11016         case 0x2:
11017           vex_table_index = VEX_0F38;
11018           break;
11019         case 0x3:
11020           vex_table_index = VEX_0F3A;
11021           break;
11022         }
11023       codep++;
11024       vex.w = *codep & 0x80;
11025       if (vex.w && address_mode == mode_64bit)
11026         rex |= REX_W;
11027
11028       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11029       if (address_mode != mode_64bit
11030           && vex.register_specifier > 0x7)
11031         {
11032           dp = &bad_opcode;
11033           return dp;
11034         }
11035
11036       vex.length = (*codep & 0x4) ? 256 : 128;
11037       switch ((*codep & 0x3))
11038         {
11039         case 0:
11040           vex.prefix = 0;
11041           break;
11042         case 1:
11043           vex.prefix = DATA_PREFIX_OPCODE;
11044           break;
11045         case 2:
11046           vex.prefix = REPE_PREFIX_OPCODE;
11047           break;
11048         case 3:
11049           vex.prefix = REPNE_PREFIX_OPCODE;
11050           break;
11051         }
11052       need_vex = 1;
11053       need_vex_reg = 1;
11054       codep++;
11055       vindex = *codep++;
11056       dp = &vex_table[vex_table_index][vindex];
11057       /* There is no MODRM byte for VEX [82|77].  */
11058       if (vindex != 0x77 && vindex != 0x82)
11059         {
11060           FETCH_DATA (info, codep + 1);
11061           modrm.mod = (*codep >> 6) & 3;
11062           modrm.reg = (*codep >> 3) & 7;
11063           modrm.rm = *codep & 7;
11064         }
11065       break;
11066
11067     case USE_VEX_C5_TABLE:
11068       FETCH_DATA (info, codep + 2);
11069       /* All bits in the REX prefix are ignored.  */
11070       rex_ignored = rex;
11071       rex = (*codep & 0x80) ? 0 : REX_R;
11072
11073       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11074       if (address_mode != mode_64bit
11075           && vex.register_specifier > 0x7)
11076         {
11077           dp = &bad_opcode;
11078           return dp;
11079         }
11080
11081       vex.w = 0;
11082
11083       vex.length = (*codep & 0x4) ? 256 : 128;
11084       switch ((*codep & 0x3))
11085         {
11086         case 0:
11087           vex.prefix = 0;
11088           break;
11089         case 1:
11090           vex.prefix = DATA_PREFIX_OPCODE;
11091           break;
11092         case 2:
11093           vex.prefix = REPE_PREFIX_OPCODE;
11094           break;
11095         case 3:
11096           vex.prefix = REPNE_PREFIX_OPCODE;
11097           break;
11098         }
11099       need_vex = 1;
11100       need_vex_reg = 1;
11101       codep++;
11102       vindex = *codep++;
11103       dp = &vex_table[dp->op[1].bytemode][vindex];
11104       /* There is no MODRM byte for VEX [82|77].  */
11105       if (vindex != 0x77 && vindex != 0x82)
11106         {
11107           FETCH_DATA (info, codep + 1);
11108           modrm.mod = (*codep >> 6) & 3;
11109           modrm.reg = (*codep >> 3) & 7;
11110           modrm.rm = *codep & 7;
11111         }
11112       break;
11113
11114     case USE_VEX_W_TABLE:
11115       if (!need_vex)
11116         abort ();
11117
11118       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11119       break;
11120
11121     case 0:
11122       dp = &bad_opcode;
11123       break;
11124
11125     default:
11126       abort ();
11127     }
11128
11129   if (dp->name != NULL)
11130     return dp;
11131   else
11132     return get_valid_dis386 (dp, info);
11133 }
11134
11135 static void
11136 get_sib (disassemble_info *info)
11137 {
11138   /* If modrm.mod == 3, operand must be register.  */
11139   if (need_modrm
11140       && address_mode != mode_16bit
11141       && modrm.mod != 3
11142       && modrm.rm == 4)
11143     {
11144       FETCH_DATA (info, codep + 2);
11145       sib.index = (codep [1] >> 3) & 7;
11146       sib.scale = (codep [1] >> 6) & 3;
11147       sib.base = codep [1] & 7;
11148     }
11149 }
11150
11151 static int
11152 print_insn (bfd_vma pc, disassemble_info *info)
11153 {
11154   const struct dis386 *dp;
11155   int i;
11156   char *op_txt[MAX_OPERANDS];
11157   int needcomma;
11158   int sizeflag;
11159   const char *p;
11160   struct dis_private priv;
11161   int prefix_length;
11162   int default_prefixes;
11163
11164   if (info->mach == bfd_mach_x86_64_intel_syntax
11165       || info->mach == bfd_mach_x86_64
11166       || info->mach == bfd_mach_x64_32_intel_syntax
11167       || info->mach == bfd_mach_x64_32
11168       || info->mach == bfd_mach_l1om
11169       || info->mach == bfd_mach_l1om_intel_syntax
11170       || info->mach == bfd_mach_k1om
11171       || info->mach == bfd_mach_k1om_intel_syntax)
11172     address_mode = mode_64bit;
11173   else
11174     address_mode = mode_32bit;
11175
11176   if (intel_syntax == (char) -1)
11177     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11178                     || info->mach == bfd_mach_x86_64_intel_syntax
11179                     || info->mach == bfd_mach_x64_32_intel_syntax
11180                     || info->mach == bfd_mach_l1om_intel_syntax
11181                     || info->mach == bfd_mach_k1om_intel_syntax);
11182
11183   if (info->mach == bfd_mach_i386_i386
11184       || info->mach == bfd_mach_x86_64
11185       || info->mach == bfd_mach_x64_32
11186       || info->mach == bfd_mach_l1om
11187       || info->mach == bfd_mach_k1om
11188       || info->mach == bfd_mach_i386_i386_intel_syntax
11189       || info->mach == bfd_mach_x86_64_intel_syntax
11190       || info->mach == bfd_mach_x64_32_intel_syntax
11191       || info->mach == bfd_mach_l1om_intel_syntax
11192       || info->mach == bfd_mach_k1om_intel_syntax)
11193     priv.orig_sizeflag = AFLAG | DFLAG;
11194   else if (info->mach == bfd_mach_i386_i8086)
11195     priv.orig_sizeflag = 0;
11196   else
11197     abort ();
11198
11199   for (p = info->disassembler_options; p != NULL; )
11200     {
11201       if (CONST_STRNEQ (p, "x86-64"))
11202         {
11203           address_mode = mode_64bit;
11204           priv.orig_sizeflag = AFLAG | DFLAG;
11205         }
11206       else if (CONST_STRNEQ (p, "i386"))
11207         {
11208           address_mode = mode_32bit;
11209           priv.orig_sizeflag = AFLAG | DFLAG;
11210         }
11211       else if (CONST_STRNEQ (p, "i8086"))
11212         {
11213           address_mode = mode_16bit;
11214           priv.orig_sizeflag = 0;
11215         }
11216       else if (CONST_STRNEQ (p, "intel"))
11217         {
11218           intel_syntax = 1;
11219           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11220             intel_mnemonic = 1;
11221         }
11222       else if (CONST_STRNEQ (p, "att"))
11223         {
11224           intel_syntax = 0;
11225           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11226             intel_mnemonic = 0;
11227         }
11228       else if (CONST_STRNEQ (p, "addr"))
11229         {
11230           if (address_mode == mode_64bit)
11231             {
11232               if (p[4] == '3' && p[5] == '2')
11233                 priv.orig_sizeflag &= ~AFLAG;
11234               else if (p[4] == '6' && p[5] == '4')
11235                 priv.orig_sizeflag |= AFLAG;
11236             }
11237           else
11238             {
11239               if (p[4] == '1' && p[5] == '6')
11240                 priv.orig_sizeflag &= ~AFLAG;
11241               else if (p[4] == '3' && p[5] == '2')
11242                 priv.orig_sizeflag |= AFLAG;
11243             }
11244         }
11245       else if (CONST_STRNEQ (p, "data"))
11246         {
11247           if (p[4] == '1' && p[5] == '6')
11248             priv.orig_sizeflag &= ~DFLAG;
11249           else if (p[4] == '3' && p[5] == '2')
11250             priv.orig_sizeflag |= DFLAG;
11251         }
11252       else if (CONST_STRNEQ (p, "suffix"))
11253         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11254
11255       p = strchr (p, ',');
11256       if (p != NULL)
11257         p++;
11258     }
11259
11260   if (intel_syntax)
11261     {
11262       names64 = intel_names64;
11263       names32 = intel_names32;
11264       names16 = intel_names16;
11265       names8 = intel_names8;
11266       names8rex = intel_names8rex;
11267       names_seg = intel_names_seg;
11268       names_mm = intel_names_mm;
11269       names_xmm = intel_names_xmm;
11270       names_ymm = intel_names_ymm;
11271       index64 = intel_index64;
11272       index32 = intel_index32;
11273       index16 = intel_index16;
11274       open_char = '[';
11275       close_char = ']';
11276       separator_char = '+';
11277       scale_char = '*';
11278     }
11279   else
11280     {
11281       names64 = att_names64;
11282       names32 = att_names32;
11283       names16 = att_names16;
11284       names8 = att_names8;
11285       names8rex = att_names8rex;
11286       names_seg = att_names_seg;
11287       names_mm = att_names_mm;
11288       names_xmm = att_names_xmm;
11289       names_ymm = att_names_ymm;
11290       index64 = att_index64;
11291       index32 = att_index32;
11292       index16 = att_index16;
11293       open_char = '(';
11294       close_char =  ')';
11295       separator_char = ',';
11296       scale_char = ',';
11297     }
11298
11299   /* The output looks better if we put 7 bytes on a line, since that
11300      puts most long word instructions on a single line.  Use 8 bytes
11301      for Intel L1OM.  */
11302   if (info->mach == bfd_mach_l1om
11303       || info->mach == bfd_mach_l1om_intel_syntax)
11304     info->bytes_per_line = 8;
11305   else
11306     info->bytes_per_line = 7;
11307
11308   info->private_data = &priv;
11309   priv.max_fetched = priv.the_buffer;
11310   priv.insn_start = pc;
11311
11312   obuf[0] = 0;
11313   for (i = 0; i < MAX_OPERANDS; ++i)
11314     {
11315       op_out[i][0] = 0;
11316       op_index[i] = -1;
11317     }
11318
11319   the_info = info;
11320   start_pc = pc;
11321   start_codep = priv.the_buffer;
11322   codep = priv.the_buffer;
11323
11324   if (setjmp (priv.bailout) != 0)
11325     {
11326       const char *name;
11327
11328       /* Getting here means we tried for data but didn't get it.  That
11329          means we have an incomplete instruction of some sort.  Just
11330          print the first byte as a prefix or a .byte pseudo-op.  */
11331       if (codep > priv.the_buffer)
11332         {
11333           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11334           if (name != NULL)
11335             (*info->fprintf_func) (info->stream, "%s", name);
11336           else
11337             {
11338               /* Just print the first byte as a .byte instruction.  */
11339               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11340                                      (unsigned int) priv.the_buffer[0]);
11341             }
11342
11343           return 1;
11344         }
11345
11346       return -1;
11347     }
11348
11349   obufp = obuf;
11350   sizeflag = priv.orig_sizeflag;
11351
11352   if (!ckprefix () || rex_used)
11353     {
11354       /* Too many prefixes or unused REX prefixes.  */
11355       for (i = 0;
11356            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11357            i++)
11358         (*info->fprintf_func) (info->stream, "%s",
11359                                prefix_name (all_prefixes[i], sizeflag));
11360       return 1;
11361     }
11362
11363   insn_codep = codep;
11364
11365   FETCH_DATA (info, codep + 1);
11366   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11367
11368   if (((prefixes & PREFIX_FWAIT)
11369        && ((*codep < 0xd8) || (*codep > 0xdf))))
11370     {
11371       (*info->fprintf_func) (info->stream, "fwait");
11372       return 1;
11373     }
11374
11375   if (*codep == 0x0f)
11376     {
11377       unsigned char threebyte;
11378       FETCH_DATA (info, codep + 2);
11379       threebyte = *++codep;
11380       dp = &dis386_twobyte[threebyte];
11381       need_modrm = twobyte_has_modrm[*codep];
11382       codep++;
11383     }
11384   else
11385     {
11386       dp = &dis386[*codep];
11387       need_modrm = onebyte_has_modrm[*codep];
11388       codep++;
11389     }
11390
11391   if ((prefixes & PREFIX_REPZ))
11392     used_prefixes |= PREFIX_REPZ;
11393   if ((prefixes & PREFIX_REPNZ))
11394     used_prefixes |= PREFIX_REPNZ;
11395   if ((prefixes & PREFIX_LOCK))
11396     used_prefixes |= PREFIX_LOCK;
11397
11398   default_prefixes = 0;
11399   if (prefixes & PREFIX_ADDR)
11400     {
11401       sizeflag ^= AFLAG;
11402       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11403         {
11404           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11405             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11406           else
11407             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11408           default_prefixes |= PREFIX_ADDR;
11409         }
11410     }
11411
11412   if ((prefixes & PREFIX_DATA))
11413     {
11414       sizeflag ^= DFLAG;
11415       if (dp->op[2].bytemode == cond_jump_mode
11416           && dp->op[0].bytemode == v_mode
11417           && !intel_syntax)
11418         {
11419           if (sizeflag & DFLAG)
11420             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11421           else
11422             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11423           default_prefixes |= PREFIX_DATA;
11424         }
11425       else if (rex & REX_W)
11426         {
11427           /* REX_W will override PREFIX_DATA.  */
11428           default_prefixes |= PREFIX_DATA;
11429         }
11430     }
11431
11432   if (need_modrm)
11433     {
11434       FETCH_DATA (info, codep + 1);
11435       modrm.mod = (*codep >> 6) & 3;
11436       modrm.reg = (*codep >> 3) & 7;
11437       modrm.rm = *codep & 7;
11438     }
11439
11440   need_vex = 0;
11441   need_vex_reg = 0;
11442   vex_w_done = 0;
11443
11444   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11445     {
11446       get_sib (info);
11447       dofloat (sizeflag);
11448     }
11449   else
11450     {
11451       dp = get_valid_dis386 (dp, info);
11452       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11453         {
11454           get_sib (info);
11455           for (i = 0; i < MAX_OPERANDS; ++i)
11456             {
11457               obufp = op_out[i];
11458               op_ad = MAX_OPERANDS - 1 - i;
11459               if (dp->op[i].rtn)
11460                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11461             }
11462         }
11463     }
11464
11465   /* See if any prefixes were not used.  If so, print the first one
11466      separately.  If we don't do this, we'll wind up printing an
11467      instruction stream which does not precisely correspond to the
11468      bytes we are disassembling.  */
11469   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11470     {
11471       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11472         if (all_prefixes[i])
11473           {
11474             const char *name;
11475             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11476             if (name == NULL)
11477               name = INTERNAL_DISASSEMBLER_ERROR;
11478             (*info->fprintf_func) (info->stream, "%s", name);
11479             return 1;
11480           }
11481     }
11482
11483   /* Check if the REX prefix is used.  */
11484   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11485     all_prefixes[last_rex_prefix] = 0;
11486
11487   /* Check if the SEG prefix is used.  */
11488   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11489                    | PREFIX_FS | PREFIX_GS)) != 0
11490       && (used_prefixes
11491           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11492     all_prefixes[last_seg_prefix] = 0;
11493
11494   /* Check if the ADDR prefix is used.  */
11495   if ((prefixes & PREFIX_ADDR) != 0
11496       && (used_prefixes & PREFIX_ADDR) != 0)
11497     all_prefixes[last_addr_prefix] = 0;
11498
11499   /* Check if the DATA prefix is used.  */
11500   if ((prefixes & PREFIX_DATA) != 0
11501       && (used_prefixes & PREFIX_DATA) != 0)
11502     all_prefixes[last_data_prefix] = 0;
11503
11504   prefix_length = 0;
11505   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11506     if (all_prefixes[i])
11507       {
11508         const char *name;
11509         name = prefix_name (all_prefixes[i], sizeflag);
11510         if (name == NULL)
11511           abort ();
11512         prefix_length += strlen (name) + 1;
11513         (*info->fprintf_func) (info->stream, "%s ", name);
11514       }
11515
11516   /* Check maximum code length.  */
11517   if ((codep - start_codep) > MAX_CODE_LENGTH)
11518     {
11519       (*info->fprintf_func) (info->stream, "(bad)");
11520       return MAX_CODE_LENGTH;
11521     }
11522
11523   obufp = mnemonicendp;
11524   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11525     oappend (" ");
11526   oappend (" ");
11527   (*info->fprintf_func) (info->stream, "%s", obuf);
11528
11529   /* The enter and bound instructions are printed with operands in the same
11530      order as the intel book; everything else is printed in reverse order.  */
11531   if (intel_syntax || two_source_ops)
11532     {
11533       bfd_vma riprel;
11534
11535       for (i = 0; i < MAX_OPERANDS; ++i)
11536         op_txt[i] = op_out[i];
11537
11538       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11539         {
11540           op_ad = op_index[i];
11541           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11542           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11543           riprel = op_riprel[i];
11544           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11545           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11546         }
11547     }
11548   else
11549     {
11550       for (i = 0; i < MAX_OPERANDS; ++i)
11551         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11552     }
11553
11554   needcomma = 0;
11555   for (i = 0; i < MAX_OPERANDS; ++i)
11556     if (*op_txt[i])
11557       {
11558         if (needcomma)
11559           (*info->fprintf_func) (info->stream, ",");
11560         if (op_index[i] != -1 && !op_riprel[i])
11561           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11562         else
11563           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11564         needcomma = 1;
11565       }
11566
11567   for (i = 0; i < MAX_OPERANDS; i++)
11568     if (op_index[i] != -1 && op_riprel[i])
11569       {
11570         (*info->fprintf_func) (info->stream, "        # ");
11571         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11572                                                 + op_address[op_index[i]]), info);
11573         break;
11574       }
11575   return codep - priv.the_buffer;
11576 }
11577
11578 static const char *float_mem[] = {
11579   /* d8 */
11580   "fadd{s|}",
11581   "fmul{s|}",
11582   "fcom{s|}",
11583   "fcomp{s|}",
11584   "fsub{s|}",
11585   "fsubr{s|}",
11586   "fdiv{s|}",
11587   "fdivr{s|}",
11588   /* d9 */
11589   "fld{s|}",
11590   "(bad)",
11591   "fst{s|}",
11592   "fstp{s|}",
11593   "fldenvIC",
11594   "fldcw",
11595   "fNstenvIC",
11596   "fNstcw",
11597   /* da */
11598   "fiadd{l|}",
11599   "fimul{l|}",
11600   "ficom{l|}",
11601   "ficomp{l|}",
11602   "fisub{l|}",
11603   "fisubr{l|}",
11604   "fidiv{l|}",
11605   "fidivr{l|}",
11606   /* db */
11607   "fild{l|}",
11608   "fisttp{l|}",
11609   "fist{l|}",
11610   "fistp{l|}",
11611   "(bad)",
11612   "fld{t||t|}",
11613   "(bad)",
11614   "fstp{t||t|}",
11615   /* dc */
11616   "fadd{l|}",
11617   "fmul{l|}",
11618   "fcom{l|}",
11619   "fcomp{l|}",
11620   "fsub{l|}",
11621   "fsubr{l|}",
11622   "fdiv{l|}",
11623   "fdivr{l|}",
11624   /* dd */
11625   "fld{l|}",
11626   "fisttp{ll|}",
11627   "fst{l||}",
11628   "fstp{l|}",
11629   "frstorIC",
11630   "(bad)",
11631   "fNsaveIC",
11632   "fNstsw",
11633   /* de */
11634   "fiadd",
11635   "fimul",
11636   "ficom",
11637   "ficomp",
11638   "fisub",
11639   "fisubr",
11640   "fidiv",
11641   "fidivr",
11642   /* df */
11643   "fild",
11644   "fisttp",
11645   "fist",
11646   "fistp",
11647   "fbld",
11648   "fild{ll|}",
11649   "fbstp",
11650   "fistp{ll|}",
11651 };
11652
11653 static const unsigned char float_mem_mode[] = {
11654   /* d8 */
11655   d_mode,
11656   d_mode,
11657   d_mode,
11658   d_mode,
11659   d_mode,
11660   d_mode,
11661   d_mode,
11662   d_mode,
11663   /* d9 */
11664   d_mode,
11665   0,
11666   d_mode,
11667   d_mode,
11668   0,
11669   w_mode,
11670   0,
11671   w_mode,
11672   /* da */
11673   d_mode,
11674   d_mode,
11675   d_mode,
11676   d_mode,
11677   d_mode,
11678   d_mode,
11679   d_mode,
11680   d_mode,
11681   /* db */
11682   d_mode,
11683   d_mode,
11684   d_mode,
11685   d_mode,
11686   0,
11687   t_mode,
11688   0,
11689   t_mode,
11690   /* dc */
11691   q_mode,
11692   q_mode,
11693   q_mode,
11694   q_mode,
11695   q_mode,
11696   q_mode,
11697   q_mode,
11698   q_mode,
11699   /* dd */
11700   q_mode,
11701   q_mode,
11702   q_mode,
11703   q_mode,
11704   0,
11705   0,
11706   0,
11707   w_mode,
11708   /* de */
11709   w_mode,
11710   w_mode,
11711   w_mode,
11712   w_mode,
11713   w_mode,
11714   w_mode,
11715   w_mode,
11716   w_mode,
11717   /* df */
11718   w_mode,
11719   w_mode,
11720   w_mode,
11721   w_mode,
11722   t_mode,
11723   q_mode,
11724   t_mode,
11725   q_mode
11726 };
11727
11728 #define ST { OP_ST, 0 }
11729 #define STi { OP_STi, 0 }
11730
11731 #define FGRPd9_2 NULL, { { NULL, 0 } }
11732 #define FGRPd9_4 NULL, { { NULL, 1 } }
11733 #define FGRPd9_5 NULL, { { NULL, 2 } }
11734 #define FGRPd9_6 NULL, { { NULL, 3 } }
11735 #define FGRPd9_7 NULL, { { NULL, 4 } }
11736 #define FGRPda_5 NULL, { { NULL, 5 } }
11737 #define FGRPdb_4 NULL, { { NULL, 6 } }
11738 #define FGRPde_3 NULL, { { NULL, 7 } }
11739 #define FGRPdf_4 NULL, { { NULL, 8 } }
11740
11741 static const struct dis386 float_reg[][8] = {
11742   /* d8 */
11743   {
11744     { "fadd",   { ST, STi } },
11745     { "fmul",   { ST, STi } },
11746     { "fcom",   { STi } },
11747     { "fcomp",  { STi } },
11748     { "fsub",   { ST, STi } },
11749     { "fsubr",  { ST, STi } },
11750     { "fdiv",   { ST, STi } },
11751     { "fdivr",  { ST, STi } },
11752   },
11753   /* d9 */
11754   {
11755     { "fld",    { STi } },
11756     { "fxch",   { STi } },
11757     { FGRPd9_2 },
11758     { Bad_Opcode },
11759     { FGRPd9_4 },
11760     { FGRPd9_5 },
11761     { FGRPd9_6 },
11762     { FGRPd9_7 },
11763   },
11764   /* da */
11765   {
11766     { "fcmovb", { ST, STi } },
11767     { "fcmove", { ST, STi } },
11768     { "fcmovbe",{ ST, STi } },
11769     { "fcmovu", { ST, STi } },
11770     { Bad_Opcode },
11771     { FGRPda_5 },
11772     { Bad_Opcode },
11773     { Bad_Opcode },
11774   },
11775   /* db */
11776   {
11777     { "fcmovnb",{ ST, STi } },
11778     { "fcmovne",{ ST, STi } },
11779     { "fcmovnbe",{ ST, STi } },
11780     { "fcmovnu",{ ST, STi } },
11781     { FGRPdb_4 },
11782     { "fucomi", { ST, STi } },
11783     { "fcomi",  { ST, STi } },
11784     { Bad_Opcode },
11785   },
11786   /* dc */
11787   {
11788     { "fadd",   { STi, ST } },
11789     { "fmul",   { STi, ST } },
11790     { Bad_Opcode },
11791     { Bad_Opcode },
11792     { "fsub!M", { STi, ST } },
11793     { "fsubM",  { STi, ST } },
11794     { "fdiv!M", { STi, ST } },
11795     { "fdivM",  { STi, ST } },
11796   },
11797   /* dd */
11798   {
11799     { "ffree",  { STi } },
11800     { Bad_Opcode },
11801     { "fst",    { STi } },
11802     { "fstp",   { STi } },
11803     { "fucom",  { STi } },
11804     { "fucomp", { STi } },
11805     { Bad_Opcode },
11806     { Bad_Opcode },
11807   },
11808   /* de */
11809   {
11810     { "faddp",  { STi, ST } },
11811     { "fmulp",  { STi, ST } },
11812     { Bad_Opcode },
11813     { FGRPde_3 },
11814     { "fsub!Mp", { STi, ST } },
11815     { "fsubMp", { STi, ST } },
11816     { "fdiv!Mp", { STi, ST } },
11817     { "fdivMp", { STi, ST } },
11818   },
11819   /* df */
11820   {
11821     { "ffreep", { STi } },
11822     { Bad_Opcode },
11823     { Bad_Opcode },
11824     { Bad_Opcode },
11825     { FGRPdf_4 },
11826     { "fucomip", { ST, STi } },
11827     { "fcomip", { ST, STi } },
11828     { Bad_Opcode },
11829   },
11830 };
11831
11832 static char *fgrps[][8] = {
11833   /* d9_2  0 */
11834   {
11835     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11836   },
11837
11838   /* d9_4  1 */
11839   {
11840     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11841   },
11842
11843   /* d9_5  2 */
11844   {
11845     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11846   },
11847
11848   /* d9_6  3 */
11849   {
11850     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11851   },
11852
11853   /* d9_7  4 */
11854   {
11855     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11856   },
11857
11858   /* da_5  5 */
11859   {
11860     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11861   },
11862
11863   /* db_4  6 */
11864   {
11865     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11866     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11867   },
11868
11869   /* de_3  7 */
11870   {
11871     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11872   },
11873
11874   /* df_4  8 */
11875   {
11876     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11877   },
11878 };
11879
11880 static void
11881 swap_operand (void)
11882 {
11883   mnemonicendp[0] = '.';
11884   mnemonicendp[1] = 's';
11885   mnemonicendp += 2;
11886 }
11887
11888 static void
11889 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11890                int sizeflag ATTRIBUTE_UNUSED)
11891 {
11892   /* Skip mod/rm byte.  */
11893   MODRM_CHECK;
11894   codep++;
11895 }
11896
11897 static void
11898 dofloat (int sizeflag)
11899 {
11900   const struct dis386 *dp;
11901   unsigned char floatop;
11902
11903   floatop = codep[-1];
11904
11905   if (modrm.mod != 3)
11906     {
11907       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11908
11909       putop (float_mem[fp_indx], sizeflag);
11910       obufp = op_out[0];
11911       op_ad = 2;
11912       OP_E (float_mem_mode[fp_indx], sizeflag);
11913       return;
11914     }
11915   /* Skip mod/rm byte.  */
11916   MODRM_CHECK;
11917   codep++;
11918
11919   dp = &float_reg[floatop - 0xd8][modrm.reg];
11920   if (dp->name == NULL)
11921     {
11922       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11923
11924       /* Instruction fnstsw is only one with strange arg.  */
11925       if (floatop == 0xdf && codep[-1] == 0xe0)
11926         strcpy (op_out[0], names16[0]);
11927     }
11928   else
11929     {
11930       putop (dp->name, sizeflag);
11931
11932       obufp = op_out[0];
11933       op_ad = 2;
11934       if (dp->op[0].rtn)
11935         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
11936
11937       obufp = op_out[1];
11938       op_ad = 1;
11939       if (dp->op[1].rtn)
11940         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
11941     }
11942 }
11943
11944 static void
11945 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11946 {
11947   oappend ("%st" + intel_syntax);
11948 }
11949
11950 static void
11951 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11952 {
11953   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
11954   oappend (scratchbuf + intel_syntax);
11955 }
11956
11957 /* Capital letters in template are macros.  */
11958 static int
11959 putop (const char *in_template, int sizeflag)
11960 {
11961   const char *p;
11962   int alt = 0;
11963   int cond = 1;
11964   unsigned int l = 0, len = 1;
11965   char last[4];
11966
11967 #define SAVE_LAST(c)                    \
11968   if (l < len && l < sizeof (last))     \
11969     last[l++] = c;                      \
11970   else                                  \
11971     abort ();
11972
11973   for (p = in_template; *p; p++)
11974     {
11975       switch (*p)
11976         {
11977         default:
11978           *obufp++ = *p;
11979           break;
11980         case '%':
11981           len++;
11982           break;
11983         case '!':
11984           cond = 0;
11985           break;
11986         case '{':
11987           alt = 0;
11988           if (intel_syntax)
11989             {
11990               while (*++p != '|')
11991                 if (*p == '}' || *p == '\0')
11992                   abort ();
11993             }
11994           /* Fall through.  */
11995         case 'I':
11996           alt = 1;
11997           continue;
11998         case '|':
11999           while (*++p != '}')
12000             {
12001               if (*p == '\0')
12002                 abort ();
12003             }
12004           break;
12005         case '}':
12006           break;
12007         case 'A':
12008           if (intel_syntax)
12009             break;
12010           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12011             *obufp++ = 'b';
12012           break;
12013         case 'B':
12014           if (l == 0 && len == 1)
12015             {
12016 case_B:
12017               if (intel_syntax)
12018                 break;
12019               if (sizeflag & SUFFIX_ALWAYS)
12020                 *obufp++ = 'b';
12021             }
12022           else
12023             {
12024               if (l != 1
12025                   || len != 2
12026                   || last[0] != 'L')
12027                 {
12028                   SAVE_LAST (*p);
12029                   break;
12030                 }
12031
12032               if (address_mode == mode_64bit
12033                   && !(prefixes & PREFIX_ADDR))
12034                 {
12035                   *obufp++ = 'a';
12036                   *obufp++ = 'b';
12037                   *obufp++ = 's';
12038                 }
12039
12040               goto case_B;
12041             }
12042           break;
12043         case 'C':
12044           if (intel_syntax && !alt)
12045             break;
12046           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12047             {
12048               if (sizeflag & DFLAG)
12049                 *obufp++ = intel_syntax ? 'd' : 'l';
12050               else
12051                 *obufp++ = intel_syntax ? 'w' : 's';
12052               used_prefixes |= (prefixes & PREFIX_DATA);
12053             }
12054           break;
12055         case 'D':
12056           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12057             break;
12058           USED_REX (REX_W);
12059           if (modrm.mod == 3)
12060             {
12061               if (rex & REX_W)
12062                 *obufp++ = 'q';
12063               else
12064                 {
12065                   if (sizeflag & DFLAG)
12066                     *obufp++ = intel_syntax ? 'd' : 'l';
12067                   else
12068                     *obufp++ = 'w';
12069                   used_prefixes |= (prefixes & PREFIX_DATA);
12070                 }
12071             }
12072           else
12073             *obufp++ = 'w';
12074           break;
12075         case 'E':               /* For jcxz/jecxz */
12076           if (address_mode == mode_64bit)
12077             {
12078               if (sizeflag & AFLAG)
12079                 *obufp++ = 'r';
12080               else
12081                 *obufp++ = 'e';
12082             }
12083           else
12084             if (sizeflag & AFLAG)
12085               *obufp++ = 'e';
12086           used_prefixes |= (prefixes & PREFIX_ADDR);
12087           break;
12088         case 'F':
12089           if (intel_syntax)
12090             break;
12091           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12092             {
12093               if (sizeflag & AFLAG)
12094                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12095               else
12096                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12097               used_prefixes |= (prefixes & PREFIX_ADDR);
12098             }
12099           break;
12100         case 'G':
12101           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12102             break;
12103           if ((rex & REX_W) || (sizeflag & DFLAG))
12104             *obufp++ = 'l';
12105           else
12106             *obufp++ = 'w';
12107           if (!(rex & REX_W))
12108             used_prefixes |= (prefixes & PREFIX_DATA);
12109           break;
12110         case 'H':
12111           if (intel_syntax)
12112             break;
12113           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12114               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12115             {
12116               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12117               *obufp++ = ',';
12118               *obufp++ = 'p';
12119               if (prefixes & PREFIX_DS)
12120                 *obufp++ = 't';
12121               else
12122                 *obufp++ = 'n';
12123             }
12124           break;
12125         case 'J':
12126           if (intel_syntax)
12127             break;
12128           *obufp++ = 'l';
12129           break;
12130         case 'K':
12131           USED_REX (REX_W);
12132           if (rex & REX_W)
12133             *obufp++ = 'q';
12134           else
12135             *obufp++ = 'd';
12136           break;
12137         case 'Z':
12138           if (intel_syntax)
12139             break;
12140           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12141             {
12142               *obufp++ = 'q';
12143               break;
12144             }
12145           /* Fall through.  */
12146           goto case_L;
12147         case 'L':
12148           if (l != 0 || len != 1)
12149             {
12150               SAVE_LAST (*p);
12151               break;
12152             }
12153 case_L:
12154           if (intel_syntax)
12155             break;
12156           if (sizeflag & SUFFIX_ALWAYS)
12157             *obufp++ = 'l';
12158           break;
12159         case 'M':
12160           if (intel_mnemonic != cond)
12161             *obufp++ = 'r';
12162           break;
12163         case 'N':
12164           if ((prefixes & PREFIX_FWAIT) == 0)
12165             *obufp++ = 'n';
12166           else
12167             used_prefixes |= PREFIX_FWAIT;
12168           break;
12169         case 'O':
12170           USED_REX (REX_W);
12171           if (rex & REX_W)
12172             *obufp++ = 'o';
12173           else if (intel_syntax && (sizeflag & DFLAG))
12174             *obufp++ = 'q';
12175           else
12176             *obufp++ = 'd';
12177           if (!(rex & REX_W))
12178             used_prefixes |= (prefixes & PREFIX_DATA);
12179           break;
12180         case 'T':
12181           if (!intel_syntax
12182               && address_mode == mode_64bit
12183               && (sizeflag & DFLAG))
12184             {
12185               *obufp++ = 'q';
12186               break;
12187             }
12188           /* Fall through.  */
12189         case 'P':
12190           if (intel_syntax)
12191             {
12192               if ((rex & REX_W) == 0
12193                   && (prefixes & PREFIX_DATA))
12194                 {
12195                   if ((sizeflag & DFLAG) == 0)
12196                     *obufp++ = 'w';
12197                    used_prefixes |= (prefixes & PREFIX_DATA);
12198                 }
12199               break;
12200             }
12201           if ((prefixes & PREFIX_DATA)
12202               || (rex & REX_W)
12203               || (sizeflag & SUFFIX_ALWAYS))
12204             {
12205               USED_REX (REX_W);
12206               if (rex & REX_W)
12207                 *obufp++ = 'q';
12208               else
12209                 {
12210                    if (sizeflag & DFLAG)
12211                       *obufp++ = 'l';
12212                    else
12213                      *obufp++ = 'w';
12214                    used_prefixes |= (prefixes & PREFIX_DATA);
12215                 }
12216             }
12217           break;
12218         case 'U':
12219           if (intel_syntax)
12220             break;
12221           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12222             {
12223               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12224                 *obufp++ = 'q';
12225               break;
12226             }
12227           /* Fall through.  */
12228           goto case_Q;
12229         case 'Q':
12230           if (l == 0 && len == 1)
12231             {
12232 case_Q:
12233               if (intel_syntax && !alt)
12234                 break;
12235               USED_REX (REX_W);
12236               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12237                 {
12238                   if (rex & REX_W)
12239                     *obufp++ = 'q';
12240                   else
12241                     {
12242                       if (sizeflag & DFLAG)
12243                         *obufp++ = intel_syntax ? 'd' : 'l';
12244                       else
12245                         *obufp++ = 'w';
12246                       used_prefixes |= (prefixes & PREFIX_DATA);
12247                     }
12248                 }
12249             }
12250           else
12251             {
12252               if (l != 1 || len != 2 || last[0] != 'L')
12253                 {
12254                   SAVE_LAST (*p);
12255                   break;
12256                 }
12257               if (intel_syntax
12258                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12259                 break;
12260               if ((rex & REX_W))
12261                 {
12262                   USED_REX (REX_W);
12263                   *obufp++ = 'q';
12264                 }
12265               else
12266                 *obufp++ = 'l';
12267             }
12268           break;
12269         case 'R':
12270           USED_REX (REX_W);
12271           if (rex & REX_W)
12272             *obufp++ = 'q';
12273           else if (sizeflag & DFLAG)
12274             {
12275               if (intel_syntax)
12276                   *obufp++ = 'd';
12277               else
12278                   *obufp++ = 'l';
12279             }
12280           else
12281             *obufp++ = 'w';
12282           if (intel_syntax && !p[1]
12283               && ((rex & REX_W) || (sizeflag & DFLAG)))
12284             *obufp++ = 'e';
12285           if (!(rex & REX_W))
12286             used_prefixes |= (prefixes & PREFIX_DATA);
12287           break;
12288         case 'V':
12289           if (l == 0 && len == 1)
12290             {
12291               if (intel_syntax)
12292                 break;
12293               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12294                 {
12295                   if (sizeflag & SUFFIX_ALWAYS)
12296                     *obufp++ = 'q';
12297                   break;
12298                 }
12299             }
12300           else
12301             {
12302               if (l != 1
12303                   || len != 2
12304                   || last[0] != 'L')
12305                 {
12306                   SAVE_LAST (*p);
12307                   break;
12308                 }
12309
12310               if (rex & REX_W)
12311                 {
12312                   *obufp++ = 'a';
12313                   *obufp++ = 'b';
12314                   *obufp++ = 's';
12315                 }
12316             }
12317           /* Fall through.  */
12318           goto case_S;
12319         case 'S':
12320           if (l == 0 && len == 1)
12321             {
12322 case_S:
12323               if (intel_syntax)
12324                 break;
12325               if (sizeflag & SUFFIX_ALWAYS)
12326                 {
12327                   if (rex & REX_W)
12328                     *obufp++ = 'q';
12329                   else
12330                     {
12331                       if (sizeflag & DFLAG)
12332                         *obufp++ = 'l';
12333                       else
12334                         *obufp++ = 'w';
12335                       used_prefixes |= (prefixes & PREFIX_DATA);
12336                     }
12337                 }
12338             }
12339           else
12340             {
12341               if (l != 1
12342                   || len != 2
12343                   || last[0] != 'L')
12344                 {
12345                   SAVE_LAST (*p);
12346                   break;
12347                 }
12348
12349               if (address_mode == mode_64bit
12350                   && !(prefixes & PREFIX_ADDR))
12351                 {
12352                   *obufp++ = 'a';
12353                   *obufp++ = 'b';
12354                   *obufp++ = 's';
12355                 }
12356
12357               goto case_S;
12358             }
12359           break;
12360         case 'X':
12361           if (l != 0 || len != 1)
12362             {
12363               SAVE_LAST (*p);
12364               break;
12365             }
12366           if (need_vex && vex.prefix)
12367             {
12368               if (vex.prefix == DATA_PREFIX_OPCODE)
12369                 *obufp++ = 'd';
12370               else
12371                 *obufp++ = 's';
12372             }
12373           else
12374             {
12375               if (prefixes & PREFIX_DATA)
12376                 *obufp++ = 'd';
12377               else
12378                 *obufp++ = 's';
12379               used_prefixes |= (prefixes & PREFIX_DATA);
12380             }
12381           break;
12382         case 'Y':
12383           if (l == 0 && len == 1)
12384             {
12385               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12386                 break;
12387               if (rex & REX_W)
12388                 {
12389                   USED_REX (REX_W);
12390                   *obufp++ = 'q';
12391                 }
12392               break;
12393             }
12394           else
12395             {
12396               if (l != 1 || len != 2 || last[0] != 'X')
12397                 {
12398                   SAVE_LAST (*p);
12399                   break;
12400                 }
12401               if (!need_vex)
12402                 abort ();
12403               if (intel_syntax
12404                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12405                 break;
12406               switch (vex.length)
12407                 {
12408                 case 128:
12409                   *obufp++ = 'x';
12410                   break;
12411                 case 256:
12412                   *obufp++ = 'y';
12413                   break;
12414                 default:
12415                   abort ();
12416                 }
12417             }
12418           break;
12419         case 'W':
12420           if (l == 0 && len == 1)
12421             {
12422               /* operand size flag for cwtl, cbtw */
12423               USED_REX (REX_W);
12424               if (rex & REX_W)
12425                 {
12426                   if (intel_syntax)
12427                     *obufp++ = 'd';
12428                   else
12429                     *obufp++ = 'l';
12430                 }
12431               else if (sizeflag & DFLAG)
12432                 *obufp++ = 'w';
12433               else
12434                 *obufp++ = 'b';
12435               if (!(rex & REX_W))
12436                 used_prefixes |= (prefixes & PREFIX_DATA);
12437             }
12438           else
12439             {
12440               if (l != 1
12441                   || len != 2
12442                   || (last[0] != 'X'
12443                       && last[0] != 'L'))
12444                 {
12445                   SAVE_LAST (*p);
12446                   break;
12447                 }
12448               if (!need_vex)
12449                 abort ();
12450               if (last[0] == 'X')
12451                 *obufp++ = vex.w ? 'd': 's';
12452               else
12453                 *obufp++ = vex.w ? 'q': 'd';
12454             }
12455           break;
12456         }
12457       alt = 0;
12458     }
12459   *obufp = 0;
12460   mnemonicendp = obufp;
12461   return 0;
12462 }
12463
12464 static void
12465 oappend (const char *s)
12466 {
12467   obufp = stpcpy (obufp, s);
12468 }
12469
12470 static void
12471 append_seg (void)
12472 {
12473   if (prefixes & PREFIX_CS)
12474     {
12475       used_prefixes |= PREFIX_CS;
12476       oappend ("%cs:" + intel_syntax);
12477     }
12478   if (prefixes & PREFIX_DS)
12479     {
12480       used_prefixes |= PREFIX_DS;
12481       oappend ("%ds:" + intel_syntax);
12482     }
12483   if (prefixes & PREFIX_SS)
12484     {
12485       used_prefixes |= PREFIX_SS;
12486       oappend ("%ss:" + intel_syntax);
12487     }
12488   if (prefixes & PREFIX_ES)
12489     {
12490       used_prefixes |= PREFIX_ES;
12491       oappend ("%es:" + intel_syntax);
12492     }
12493   if (prefixes & PREFIX_FS)
12494     {
12495       used_prefixes |= PREFIX_FS;
12496       oappend ("%fs:" + intel_syntax);
12497     }
12498   if (prefixes & PREFIX_GS)
12499     {
12500       used_prefixes |= PREFIX_GS;
12501       oappend ("%gs:" + intel_syntax);
12502     }
12503 }
12504
12505 static void
12506 OP_indirE (int bytemode, int sizeflag)
12507 {
12508   if (!intel_syntax)
12509     oappend ("*");
12510   OP_E (bytemode, sizeflag);
12511 }
12512
12513 static void
12514 print_operand_value (char *buf, int hex, bfd_vma disp)
12515 {
12516   if (address_mode == mode_64bit)
12517     {
12518       if (hex)
12519         {
12520           char tmp[30];
12521           int i;
12522           buf[0] = '0';
12523           buf[1] = 'x';
12524           sprintf_vma (tmp, disp);
12525           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12526           strcpy (buf + 2, tmp + i);
12527         }
12528       else
12529         {
12530           bfd_signed_vma v = disp;
12531           char tmp[30];
12532           int i;
12533           if (v < 0)
12534             {
12535               *(buf++) = '-';
12536               v = -disp;
12537               /* Check for possible overflow on 0x8000000000000000.  */
12538               if (v < 0)
12539                 {
12540                   strcpy (buf, "9223372036854775808");
12541                   return;
12542                 }
12543             }
12544           if (!v)
12545             {
12546               strcpy (buf, "0");
12547               return;
12548             }
12549
12550           i = 0;
12551           tmp[29] = 0;
12552           while (v)
12553             {
12554               tmp[28 - i] = (v % 10) + '0';
12555               v /= 10;
12556               i++;
12557             }
12558           strcpy (buf, tmp + 29 - i);
12559         }
12560     }
12561   else
12562     {
12563       if (hex)
12564         sprintf (buf, "0x%x", (unsigned int) disp);
12565       else
12566         sprintf (buf, "%d", (int) disp);
12567     }
12568 }
12569
12570 /* Put DISP in BUF as signed hex number.  */
12571
12572 static void
12573 print_displacement (char *buf, bfd_vma disp)
12574 {
12575   bfd_signed_vma val = disp;
12576   char tmp[30];
12577   int i, j = 0;
12578
12579   if (val < 0)
12580     {
12581       buf[j++] = '-';
12582       val = -disp;
12583
12584       /* Check for possible overflow.  */
12585       if (val < 0)
12586         {
12587           switch (address_mode)
12588             {
12589             case mode_64bit:
12590               strcpy (buf + j, "0x8000000000000000");
12591               break;
12592             case mode_32bit:
12593               strcpy (buf + j, "0x80000000");
12594               break;
12595             case mode_16bit:
12596               strcpy (buf + j, "0x8000");
12597               break;
12598             }
12599           return;
12600         }
12601     }
12602
12603   buf[j++] = '0';
12604   buf[j++] = 'x';
12605
12606   sprintf_vma (tmp, (bfd_vma) val);
12607   for (i = 0; tmp[i] == '0'; i++)
12608     continue;
12609   if (tmp[i] == '\0')
12610     i--;
12611   strcpy (buf + j, tmp + i);
12612 }
12613
12614 static void
12615 intel_operand_size (int bytemode, int sizeflag)
12616 {
12617   switch (bytemode)
12618     {
12619     case b_mode:
12620     case b_swap_mode:
12621     case dqb_mode:
12622       oappend ("BYTE PTR ");
12623       break;
12624     case w_mode:
12625     case dqw_mode:
12626       oappend ("WORD PTR ");
12627       break;
12628     case stack_v_mode:
12629       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12630         {
12631           oappend ("QWORD PTR ");
12632           break;
12633         }
12634       /* FALLTHRU */
12635     case v_mode:
12636     case v_swap_mode:
12637     case dq_mode:
12638       USED_REX (REX_W);
12639       if (rex & REX_W)
12640         oappend ("QWORD PTR ");
12641       else
12642         {
12643           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12644             oappend ("DWORD PTR ");
12645           else
12646             oappend ("WORD PTR ");
12647           used_prefixes |= (prefixes & PREFIX_DATA);
12648         }
12649       break;
12650     case z_mode:
12651       if ((rex & REX_W) || (sizeflag & DFLAG))
12652         *obufp++ = 'D';
12653       oappend ("WORD PTR ");
12654       if (!(rex & REX_W))
12655         used_prefixes |= (prefixes & PREFIX_DATA);
12656       break;
12657     case a_mode:
12658       if (sizeflag & DFLAG)
12659         oappend ("QWORD PTR ");
12660       else
12661         oappend ("DWORD PTR ");
12662       used_prefixes |= (prefixes & PREFIX_DATA);
12663       break;
12664     case d_mode:
12665     case d_scalar_mode:
12666     case d_scalar_swap_mode:
12667     case d_swap_mode:
12668     case dqd_mode:
12669       oappend ("DWORD PTR ");
12670       break;
12671     case q_mode:
12672     case q_scalar_mode:
12673     case q_scalar_swap_mode:
12674     case q_swap_mode:
12675       oappend ("QWORD PTR ");
12676       break;
12677     case m_mode:
12678       if (address_mode == mode_64bit)
12679         oappend ("QWORD PTR ");
12680       else
12681         oappend ("DWORD PTR ");
12682       break;
12683     case f_mode:
12684       if (sizeflag & DFLAG)
12685         oappend ("FWORD PTR ");
12686       else
12687         oappend ("DWORD PTR ");
12688       used_prefixes |= (prefixes & PREFIX_DATA);
12689       break;
12690     case t_mode:
12691       oappend ("TBYTE PTR ");
12692       break;
12693     case x_mode:
12694     case x_swap_mode:
12695       if (need_vex)
12696         {
12697           switch (vex.length)
12698             {
12699             case 128:
12700               oappend ("XMMWORD PTR ");
12701               break;
12702             case 256:
12703               oappend ("YMMWORD PTR ");
12704               break;
12705             default:
12706               abort ();
12707             }
12708         }
12709       else
12710         oappend ("XMMWORD PTR ");
12711       break;
12712     case xmm_mode:
12713       oappend ("XMMWORD PTR ");
12714       break;
12715     case xmmq_mode:
12716       if (!need_vex)
12717         abort ();
12718
12719       switch (vex.length)
12720         {
12721         case 128:
12722           oappend ("QWORD PTR ");
12723           break;
12724         case 256:
12725           oappend ("XMMWORD PTR ");
12726           break;
12727         default:
12728           abort ();
12729         }
12730       break;
12731     case xmm_mb_mode:
12732       if (!need_vex)
12733         abort ();
12734
12735       switch (vex.length)
12736         {
12737         case 128:
12738         case 256:
12739           oappend ("BYTE PTR ");
12740           break;
12741         default:
12742           abort ();
12743         }
12744       break;
12745     case xmm_mw_mode:
12746       if (!need_vex)
12747         abort ();
12748
12749       switch (vex.length)
12750         {
12751         case 128:
12752         case 256:
12753           oappend ("WORD PTR ");
12754           break;
12755         default:
12756           abort ();
12757         }
12758       break;
12759     case xmm_md_mode:
12760       if (!need_vex)
12761         abort ();
12762
12763       switch (vex.length)
12764         {
12765         case 128:
12766         case 256:
12767           oappend ("DWORD PTR ");
12768           break;
12769         default:
12770           abort ();
12771         }
12772       break;
12773     case xmm_mq_mode:
12774       if (!need_vex)
12775         abort ();
12776
12777       switch (vex.length)
12778         {
12779         case 128:
12780         case 256:
12781           oappend ("QWORD PTR ");
12782           break;
12783         default:
12784           abort ();
12785         }
12786       break;
12787     case xmmdw_mode:
12788       if (!need_vex)
12789         abort ();
12790
12791       switch (vex.length)
12792         {
12793         case 128:
12794           oappend ("WORD PTR ");
12795           break;
12796         case 256:
12797           oappend ("DWORD PTR ");
12798           break;
12799         default:
12800           abort ();
12801         }
12802       break;
12803     case xmmqd_mode:
12804       if (!need_vex)
12805         abort ();
12806
12807       switch (vex.length)
12808         {
12809         case 128:
12810           oappend ("DWORD PTR ");
12811           break;
12812         case 256:
12813           oappend ("QWORD PTR ");
12814           break;
12815         default:
12816           abort ();
12817         }
12818       break;
12819     case ymmq_mode:
12820       if (!need_vex)
12821         abort ();
12822
12823       switch (vex.length)
12824         {
12825         case 128:
12826           oappend ("QWORD PTR ");
12827           break;
12828         case 256:
12829           oappend ("YMMWORD PTR ");
12830           break;
12831         default:
12832           abort ();
12833         }
12834       break;
12835     case ymmxmm_mode:
12836       if (!need_vex)
12837         abort ();
12838
12839       switch (vex.length)
12840         {
12841         case 128:
12842         case 256:
12843           oappend ("XMMWORD PTR ");
12844           break;
12845         default:
12846           abort ();
12847         }
12848       break;
12849     case o_mode:
12850       oappend ("OWORD PTR ");
12851       break;
12852     case vex_w_dq_mode:
12853     case vex_scalar_w_dq_mode:
12854     case vex_vsib_d_w_dq_mode:
12855     case vex_vsib_q_w_dq_mode:
12856       if (!need_vex)
12857         abort ();
12858
12859       if (vex.w)
12860         oappend ("QWORD PTR ");
12861       else
12862         oappend ("DWORD PTR ");
12863       break;
12864     default:
12865       break;
12866     }
12867 }
12868
12869 static void
12870 OP_E_register (int bytemode, int sizeflag)
12871 {
12872   int reg = modrm.rm;
12873   const char **names;
12874
12875   USED_REX (REX_B);
12876   if ((rex & REX_B))
12877     reg += 8;
12878
12879   if ((sizeflag & SUFFIX_ALWAYS)
12880       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12881     swap_operand ();
12882
12883   switch (bytemode)
12884     {
12885     case b_mode:
12886     case b_swap_mode:
12887       USED_REX (0);
12888       if (rex)
12889         names = names8rex;
12890       else
12891         names = names8;
12892       break;
12893     case w_mode:
12894       names = names16;
12895       break;
12896     case d_mode:
12897       names = names32;
12898       break;
12899     case q_mode:
12900       names = names64;
12901       break;
12902     case m_mode:
12903       names = address_mode == mode_64bit ? names64 : names32;
12904       break;
12905     case stack_v_mode:
12906       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12907         {
12908           names = names64;
12909           break;
12910         }
12911       bytemode = v_mode;
12912       /* FALLTHRU */
12913     case v_mode:
12914     case v_swap_mode:
12915     case dq_mode:
12916     case dqb_mode:
12917     case dqd_mode:
12918     case dqw_mode:
12919       USED_REX (REX_W);
12920       if (rex & REX_W)
12921         names = names64;
12922       else
12923         {
12924           if ((sizeflag & DFLAG)
12925               || (bytemode != v_mode
12926                   && bytemode != v_swap_mode))
12927             names = names32;
12928           else
12929             names = names16;
12930           used_prefixes |= (prefixes & PREFIX_DATA);
12931         }
12932       break;
12933     case 0:
12934       return;
12935     default:
12936       oappend (INTERNAL_DISASSEMBLER_ERROR);
12937       return;
12938     }
12939   oappend (names[reg]);
12940 }
12941
12942 static void
12943 OP_E_memory (int bytemode, int sizeflag)
12944 {
12945   bfd_vma disp = 0;
12946   int add = (rex & REX_B) ? 8 : 0;
12947   int riprel = 0;
12948
12949   USED_REX (REX_B);
12950   if (intel_syntax)
12951     intel_operand_size (bytemode, sizeflag);
12952   append_seg ();
12953
12954   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12955     {
12956       /* 32/64 bit address mode */
12957       int havedisp;
12958       int havesib;
12959       int havebase;
12960       int haveindex;
12961       int needindex;
12962       int base, rbase;
12963       int vindex = 0;
12964       int scale = 0;
12965       const char **indexes64 = names64;
12966       const char **indexes32 = names32;
12967
12968       havesib = 0;
12969       havebase = 1;
12970       haveindex = 0;
12971       base = modrm.rm;
12972
12973       if (base == 4)
12974         {
12975           havesib = 1;
12976           vindex = sib.index;
12977           USED_REX (REX_X);
12978           if (rex & REX_X)
12979             vindex += 8;
12980           switch (bytemode)
12981             {
12982             case vex_vsib_d_w_dq_mode:
12983             case vex_vsib_q_w_dq_mode:
12984               if (!need_vex)
12985                 abort ();
12986
12987               haveindex = 1;
12988               switch (vex.length)
12989                 {
12990                 case 128:
12991                   indexes64 = indexes32 = names_xmm;
12992                   break;
12993                 case 256:
12994                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
12995                     indexes64 = indexes32 = names_ymm;
12996                   else
12997                     indexes64 = indexes32 = names_xmm;
12998                   break;
12999                 default:
13000                   abort ();
13001                 }
13002               break;
13003             default:
13004               haveindex = vindex != 4;
13005               break;
13006             }
13007           scale = sib.scale;
13008           base = sib.base;
13009           codep++;
13010         }
13011       rbase = base + add;
13012
13013       switch (modrm.mod)
13014         {
13015         case 0:
13016           if (base == 5)
13017             {
13018               havebase = 0;
13019               if (address_mode == mode_64bit && !havesib)
13020                 riprel = 1;
13021               disp = get32s ();
13022             }
13023           break;
13024         case 1:
13025           FETCH_DATA (the_info, codep + 1);
13026           disp = *codep++;
13027           if ((disp & 0x80) != 0)
13028             disp -= 0x100;
13029           break;
13030         case 2:
13031           disp = get32s ();
13032           break;
13033         }
13034
13035       /* In 32bit mode, we need index register to tell [offset] from
13036          [eiz*1 + offset].  */
13037       needindex = (havesib
13038                    && !havebase
13039                    && !haveindex
13040                    && address_mode == mode_32bit);
13041       havedisp = (havebase
13042                   || needindex
13043                   || (havesib && (haveindex || scale != 0)));
13044
13045       if (!intel_syntax)
13046         if (modrm.mod != 0 || base == 5)
13047           {
13048             if (havedisp || riprel)
13049               print_displacement (scratchbuf, disp);
13050             else
13051               print_operand_value (scratchbuf, 1, disp);
13052             oappend (scratchbuf);
13053             if (riprel)
13054               {
13055                 set_op (disp, 1);
13056                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13057               }
13058           }
13059
13060       if (havebase || haveindex || riprel)
13061         used_prefixes |= PREFIX_ADDR;
13062
13063       if (havedisp || (intel_syntax && riprel))
13064         {
13065           *obufp++ = open_char;
13066           if (intel_syntax && riprel)
13067             {
13068               set_op (disp, 1);
13069               oappend (sizeflag & AFLAG ? "rip" : "eip");
13070             }
13071           *obufp = '\0';
13072           if (havebase)
13073             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13074                      ? names64[rbase] : names32[rbase]);
13075           if (havesib)
13076             {
13077               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13078                  print index to tell base + index from base.  */
13079               if (scale != 0
13080                   || needindex
13081                   || haveindex
13082                   || (havebase && base != ESP_REG_NUM))
13083                 {
13084                   if (!intel_syntax || havebase)
13085                     {
13086                       *obufp++ = separator_char;
13087                       *obufp = '\0';
13088                     }
13089                   if (haveindex)
13090                     oappend (address_mode == mode_64bit
13091                              && (sizeflag & AFLAG)
13092                              ? indexes64[vindex] : indexes32[vindex]);
13093                   else
13094                     oappend (address_mode == mode_64bit
13095                              && (sizeflag & AFLAG)
13096                              ? index64 : index32);
13097
13098                   *obufp++ = scale_char;
13099                   *obufp = '\0';
13100                   sprintf (scratchbuf, "%d", 1 << scale);
13101                   oappend (scratchbuf);
13102                 }
13103             }
13104           if (intel_syntax
13105               && (disp || modrm.mod != 0 || base == 5))
13106             {
13107               if (!havedisp || (bfd_signed_vma) disp >= 0)
13108                 {
13109                   *obufp++ = '+';
13110                   *obufp = '\0';
13111                 }
13112               else if (modrm.mod != 1 && disp != -disp)
13113                 {
13114                   *obufp++ = '-';
13115                   *obufp = '\0';
13116                   disp = - (bfd_signed_vma) disp;
13117                 }
13118
13119               if (havedisp)
13120                 print_displacement (scratchbuf, disp);
13121               else
13122                 print_operand_value (scratchbuf, 1, disp);
13123               oappend (scratchbuf);
13124             }
13125
13126           *obufp++ = close_char;
13127           *obufp = '\0';
13128         }
13129       else if (intel_syntax)
13130         {
13131           if (modrm.mod != 0 || base == 5)
13132             {
13133               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13134                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13135                 ;
13136               else
13137                 {
13138                   oappend (names_seg[ds_reg - es_reg]);
13139                   oappend (":");
13140                 }
13141               print_operand_value (scratchbuf, 1, disp);
13142               oappend (scratchbuf);
13143             }
13144         }
13145     }
13146   else
13147     {
13148       /* 16 bit address mode */
13149       used_prefixes |= prefixes & PREFIX_ADDR;
13150       switch (modrm.mod)
13151         {
13152         case 0:
13153           if (modrm.rm == 6)
13154             {
13155               disp = get16 ();
13156               if ((disp & 0x8000) != 0)
13157                 disp -= 0x10000;
13158             }
13159           break;
13160         case 1:
13161           FETCH_DATA (the_info, codep + 1);
13162           disp = *codep++;
13163           if ((disp & 0x80) != 0)
13164             disp -= 0x100;
13165           break;
13166         case 2:
13167           disp = get16 ();
13168           if ((disp & 0x8000) != 0)
13169             disp -= 0x10000;
13170           break;
13171         }
13172
13173       if (!intel_syntax)
13174         if (modrm.mod != 0 || modrm.rm == 6)
13175           {
13176             print_displacement (scratchbuf, disp);
13177             oappend (scratchbuf);
13178           }
13179
13180       if (modrm.mod != 0 || modrm.rm != 6)
13181         {
13182           *obufp++ = open_char;
13183           *obufp = '\0';
13184           oappend (index16[modrm.rm]);
13185           if (intel_syntax
13186               && (disp || modrm.mod != 0 || modrm.rm == 6))
13187             {
13188               if ((bfd_signed_vma) disp >= 0)
13189                 {
13190                   *obufp++ = '+';
13191                   *obufp = '\0';
13192                 }
13193               else if (modrm.mod != 1)
13194                 {
13195                   *obufp++ = '-';
13196                   *obufp = '\0';
13197                   disp = - (bfd_signed_vma) disp;
13198                 }
13199
13200               print_displacement (scratchbuf, disp);
13201               oappend (scratchbuf);
13202             }
13203
13204           *obufp++ = close_char;
13205           *obufp = '\0';
13206         }
13207       else if (intel_syntax)
13208         {
13209           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13210                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13211             ;
13212           else
13213             {
13214               oappend (names_seg[ds_reg - es_reg]);
13215               oappend (":");
13216             }
13217           print_operand_value (scratchbuf, 1, disp & 0xffff);
13218           oappend (scratchbuf);
13219         }
13220     }
13221 }
13222
13223 static void
13224 OP_E (int bytemode, int sizeflag)
13225 {
13226   /* Skip mod/rm byte.  */
13227   MODRM_CHECK;
13228   codep++;
13229
13230   if (modrm.mod == 3)
13231     OP_E_register (bytemode, sizeflag);
13232   else
13233     OP_E_memory (bytemode, sizeflag);
13234 }
13235
13236 static void
13237 OP_G (int bytemode, int sizeflag)
13238 {
13239   int add = 0;
13240   USED_REX (REX_R);
13241   if (rex & REX_R)
13242     add += 8;
13243   switch (bytemode)
13244     {
13245     case b_mode:
13246       USED_REX (0);
13247       if (rex)
13248         oappend (names8rex[modrm.reg + add]);
13249       else
13250         oappend (names8[modrm.reg + add]);
13251       break;
13252     case w_mode:
13253       oappend (names16[modrm.reg + add]);
13254       break;
13255     case d_mode:
13256       oappend (names32[modrm.reg + add]);
13257       break;
13258     case q_mode:
13259       oappend (names64[modrm.reg + add]);
13260       break;
13261     case v_mode:
13262     case dq_mode:
13263     case dqb_mode:
13264     case dqd_mode:
13265     case dqw_mode:
13266       USED_REX (REX_W);
13267       if (rex & REX_W)
13268         oappend (names64[modrm.reg + add]);
13269       else
13270         {
13271           if ((sizeflag & DFLAG) || bytemode != v_mode)
13272             oappend (names32[modrm.reg + add]);
13273           else
13274             oappend (names16[modrm.reg + add]);
13275           used_prefixes |= (prefixes & PREFIX_DATA);
13276         }
13277       break;
13278     case m_mode:
13279       if (address_mode == mode_64bit)
13280         oappend (names64[modrm.reg + add]);
13281       else
13282         oappend (names32[modrm.reg + add]);
13283       break;
13284     default:
13285       oappend (INTERNAL_DISASSEMBLER_ERROR);
13286       break;
13287     }
13288 }
13289
13290 static bfd_vma
13291 get64 (void)
13292 {
13293   bfd_vma x;
13294 #ifdef BFD64
13295   unsigned int a;
13296   unsigned int b;
13297
13298   FETCH_DATA (the_info, codep + 8);
13299   a = *codep++ & 0xff;
13300   a |= (*codep++ & 0xff) << 8;
13301   a |= (*codep++ & 0xff) << 16;
13302   a |= (*codep++ & 0xff) << 24;
13303   b = *codep++ & 0xff;
13304   b |= (*codep++ & 0xff) << 8;
13305   b |= (*codep++ & 0xff) << 16;
13306   b |= (*codep++ & 0xff) << 24;
13307   x = a + ((bfd_vma) b << 32);
13308 #else
13309   abort ();
13310   x = 0;
13311 #endif
13312   return x;
13313 }
13314
13315 static bfd_signed_vma
13316 get32 (void)
13317 {
13318   bfd_signed_vma x = 0;
13319
13320   FETCH_DATA (the_info, codep + 4);
13321   x = *codep++ & (bfd_signed_vma) 0xff;
13322   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13323   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13324   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13325   return x;
13326 }
13327
13328 static bfd_signed_vma
13329 get32s (void)
13330 {
13331   bfd_signed_vma x = 0;
13332
13333   FETCH_DATA (the_info, codep + 4);
13334   x = *codep++ & (bfd_signed_vma) 0xff;
13335   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13336   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13337   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13338
13339   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13340
13341   return x;
13342 }
13343
13344 static int
13345 get16 (void)
13346 {
13347   int x = 0;
13348
13349   FETCH_DATA (the_info, codep + 2);
13350   x = *codep++ & 0xff;
13351   x |= (*codep++ & 0xff) << 8;
13352   return x;
13353 }
13354
13355 static void
13356 set_op (bfd_vma op, int riprel)
13357 {
13358   op_index[op_ad] = op_ad;
13359   if (address_mode == mode_64bit)
13360     {
13361       op_address[op_ad] = op;
13362       op_riprel[op_ad] = riprel;
13363     }
13364   else
13365     {
13366       /* Mask to get a 32-bit address.  */
13367       op_address[op_ad] = op & 0xffffffff;
13368       op_riprel[op_ad] = riprel & 0xffffffff;
13369     }
13370 }
13371
13372 static void
13373 OP_REG (int code, int sizeflag)
13374 {
13375   const char *s;
13376   int add;
13377   USED_REX (REX_B);
13378   if (rex & REX_B)
13379     add = 8;
13380   else
13381     add = 0;
13382
13383   switch (code)
13384     {
13385     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13386     case sp_reg: case bp_reg: case si_reg: case di_reg:
13387       s = names16[code - ax_reg + add];
13388       break;
13389     case es_reg: case ss_reg: case cs_reg:
13390     case ds_reg: case fs_reg: case gs_reg:
13391       s = names_seg[code - es_reg + add];
13392       break;
13393     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13394     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13395       USED_REX (0);
13396       if (rex)
13397         s = names8rex[code - al_reg + add];
13398       else
13399         s = names8[code - al_reg];
13400       break;
13401     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13402     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13403       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13404         {
13405           s = names64[code - rAX_reg + add];
13406           break;
13407         }
13408       code += eAX_reg - rAX_reg;
13409       /* Fall through.  */
13410     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13411     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13412       USED_REX (REX_W);
13413       if (rex & REX_W)
13414         s = names64[code - eAX_reg + add];
13415       else
13416         {
13417           if (sizeflag & DFLAG)
13418             s = names32[code - eAX_reg + add];
13419           else
13420             s = names16[code - eAX_reg + add];
13421           used_prefixes |= (prefixes & PREFIX_DATA);
13422         }
13423       break;
13424     default:
13425       s = INTERNAL_DISASSEMBLER_ERROR;
13426       break;
13427     }
13428   oappend (s);
13429 }
13430
13431 static void
13432 OP_IMREG (int code, int sizeflag)
13433 {
13434   const char *s;
13435
13436   switch (code)
13437     {
13438     case indir_dx_reg:
13439       if (intel_syntax)
13440         s = "dx";
13441       else
13442         s = "(%dx)";
13443       break;
13444     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13445     case sp_reg: case bp_reg: case si_reg: case di_reg:
13446       s = names16[code - ax_reg];
13447       break;
13448     case es_reg: case ss_reg: case cs_reg:
13449     case ds_reg: case fs_reg: case gs_reg:
13450       s = names_seg[code - es_reg];
13451       break;
13452     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13453     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13454       USED_REX (0);
13455       if (rex)
13456         s = names8rex[code - al_reg];
13457       else
13458         s = names8[code - al_reg];
13459       break;
13460     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13461     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13462       USED_REX (REX_W);
13463       if (rex & REX_W)
13464         s = names64[code - eAX_reg];
13465       else
13466         {
13467           if (sizeflag & DFLAG)
13468             s = names32[code - eAX_reg];
13469           else
13470             s = names16[code - eAX_reg];
13471           used_prefixes |= (prefixes & PREFIX_DATA);
13472         }
13473       break;
13474     case z_mode_ax_reg:
13475       if ((rex & REX_W) || (sizeflag & DFLAG))
13476         s = *names32;
13477       else
13478         s = *names16;
13479       if (!(rex & REX_W))
13480         used_prefixes |= (prefixes & PREFIX_DATA);
13481       break;
13482     default:
13483       s = INTERNAL_DISASSEMBLER_ERROR;
13484       break;
13485     }
13486   oappend (s);
13487 }
13488
13489 static void
13490 OP_I (int bytemode, int sizeflag)
13491 {
13492   bfd_signed_vma op;
13493   bfd_signed_vma mask = -1;
13494
13495   switch (bytemode)
13496     {
13497     case b_mode:
13498       FETCH_DATA (the_info, codep + 1);
13499       op = *codep++;
13500       mask = 0xff;
13501       break;
13502     case q_mode:
13503       if (address_mode == mode_64bit)
13504         {
13505           op = get32s ();
13506           break;
13507         }
13508       /* Fall through.  */
13509     case v_mode:
13510       USED_REX (REX_W);
13511       if (rex & REX_W)
13512         op = get32s ();
13513       else
13514         {
13515           if (sizeflag & DFLAG)
13516             {
13517               op = get32 ();
13518               mask = 0xffffffff;
13519             }
13520           else
13521             {
13522               op = get16 ();
13523               mask = 0xfffff;
13524             }
13525           used_prefixes |= (prefixes & PREFIX_DATA);
13526         }
13527       break;
13528     case w_mode:
13529       mask = 0xfffff;
13530       op = get16 ();
13531       break;
13532     case const_1_mode:
13533       if (intel_syntax)
13534         oappend ("1");
13535       return;
13536     default:
13537       oappend (INTERNAL_DISASSEMBLER_ERROR);
13538       return;
13539     }
13540
13541   op &= mask;
13542   scratchbuf[0] = '$';
13543   print_operand_value (scratchbuf + 1, 1, op);
13544   oappend (scratchbuf + intel_syntax);
13545   scratchbuf[0] = '\0';
13546 }
13547
13548 static void
13549 OP_I64 (int bytemode, int sizeflag)
13550 {
13551   bfd_signed_vma op;
13552   bfd_signed_vma mask = -1;
13553
13554   if (address_mode != mode_64bit)
13555     {
13556       OP_I (bytemode, sizeflag);
13557       return;
13558     }
13559
13560   switch (bytemode)
13561     {
13562     case b_mode:
13563       FETCH_DATA (the_info, codep + 1);
13564       op = *codep++;
13565       mask = 0xff;
13566       break;
13567     case v_mode:
13568       USED_REX (REX_W);
13569       if (rex & REX_W)
13570         op = get64 ();
13571       else
13572         {
13573           if (sizeflag & DFLAG)
13574             {
13575               op = get32 ();
13576               mask = 0xffffffff;
13577             }
13578           else
13579             {
13580               op = get16 ();
13581               mask = 0xfffff;
13582             }
13583           used_prefixes |= (prefixes & PREFIX_DATA);
13584         }
13585       break;
13586     case w_mode:
13587       mask = 0xfffff;
13588       op = get16 ();
13589       break;
13590     default:
13591       oappend (INTERNAL_DISASSEMBLER_ERROR);
13592       return;
13593     }
13594
13595   op &= mask;
13596   scratchbuf[0] = '$';
13597   print_operand_value (scratchbuf + 1, 1, op);
13598   oappend (scratchbuf + intel_syntax);
13599   scratchbuf[0] = '\0';
13600 }
13601
13602 static void
13603 OP_sI (int bytemode, int sizeflag)
13604 {
13605   bfd_signed_vma op;
13606
13607   switch (bytemode)
13608     {
13609     case b_mode:
13610     case b_T_mode:
13611       FETCH_DATA (the_info, codep + 1);
13612       op = *codep++;
13613       if ((op & 0x80) != 0)
13614         op -= 0x100;
13615       if (bytemode == b_T_mode)
13616         {
13617           if (address_mode != mode_64bit
13618               || !(sizeflag & DFLAG))
13619             {
13620               if (sizeflag & DFLAG)
13621                 op &= 0xffffffff;
13622               else
13623                 op &= 0xffff;
13624           }
13625         }
13626       else
13627         {
13628           if (!(rex & REX_W))
13629             {
13630               if (sizeflag & DFLAG)
13631                 op &= 0xffffffff;
13632               else
13633                 op &= 0xffff;
13634             }
13635         }
13636       break;
13637     case v_mode:
13638       if (sizeflag & DFLAG)
13639         op = get32s ();
13640       else
13641         op = get16 ();
13642       break;
13643     default:
13644       oappend (INTERNAL_DISASSEMBLER_ERROR);
13645       return;
13646     }
13647
13648   scratchbuf[0] = '$';
13649   print_operand_value (scratchbuf + 1, 1, op);
13650   oappend (scratchbuf + intel_syntax);
13651 }
13652
13653 static void
13654 OP_J (int bytemode, int sizeflag)
13655 {
13656   bfd_vma disp;
13657   bfd_vma mask = -1;
13658   bfd_vma segment = 0;
13659
13660   switch (bytemode)
13661     {
13662     case b_mode:
13663       FETCH_DATA (the_info, codep + 1);
13664       disp = *codep++;
13665       if ((disp & 0x80) != 0)
13666         disp -= 0x100;
13667       break;
13668     case v_mode:
13669       USED_REX (REX_W);
13670       if ((sizeflag & DFLAG) || (rex & REX_W))
13671         disp = get32s ();
13672       else
13673         {
13674           disp = get16 ();
13675           if ((disp & 0x8000) != 0)
13676             disp -= 0x10000;
13677           /* In 16bit mode, address is wrapped around at 64k within
13678              the same segment.  Otherwise, a data16 prefix on a jump
13679              instruction means that the pc is masked to 16 bits after
13680              the displacement is added!  */
13681           mask = 0xffff;
13682           if ((prefixes & PREFIX_DATA) == 0)
13683             segment = ((start_pc + codep - start_codep)
13684                        & ~((bfd_vma) 0xffff));
13685         }
13686       if (!(rex & REX_W))
13687         used_prefixes |= (prefixes & PREFIX_DATA);
13688       break;
13689     default:
13690       oappend (INTERNAL_DISASSEMBLER_ERROR);
13691       return;
13692     }
13693   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
13694   set_op (disp, 0);
13695   print_operand_value (scratchbuf, 1, disp);
13696   oappend (scratchbuf);
13697 }
13698
13699 static void
13700 OP_SEG (int bytemode, int sizeflag)
13701 {
13702   if (bytemode == w_mode)
13703     oappend (names_seg[modrm.reg]);
13704   else
13705     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13706 }
13707
13708 static void
13709 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13710 {
13711   int seg, offset;
13712
13713   if (sizeflag & DFLAG)
13714     {
13715       offset = get32 ();
13716       seg = get16 ();
13717     }
13718   else
13719     {
13720       offset = get16 ();
13721       seg = get16 ();
13722     }
13723   used_prefixes |= (prefixes & PREFIX_DATA);
13724   if (intel_syntax)
13725     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13726   else
13727     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13728   oappend (scratchbuf);
13729 }
13730
13731 static void
13732 OP_OFF (int bytemode, int sizeflag)
13733 {
13734   bfd_vma off;
13735
13736   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13737     intel_operand_size (bytemode, sizeflag);
13738   append_seg ();
13739
13740   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13741     off = get32 ();
13742   else
13743     off = get16 ();
13744
13745   if (intel_syntax)
13746     {
13747       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13748                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13749         {
13750           oappend (names_seg[ds_reg - es_reg]);
13751           oappend (":");
13752         }
13753     }
13754   print_operand_value (scratchbuf, 1, off);
13755   oappend (scratchbuf);
13756 }
13757
13758 static void
13759 OP_OFF64 (int bytemode, int sizeflag)
13760 {
13761   bfd_vma off;
13762
13763   if (address_mode != mode_64bit
13764       || (prefixes & PREFIX_ADDR))
13765     {
13766       OP_OFF (bytemode, sizeflag);
13767       return;
13768     }
13769
13770   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13771     intel_operand_size (bytemode, sizeflag);
13772   append_seg ();
13773
13774   off = get64 ();
13775
13776   if (intel_syntax)
13777     {
13778       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13779                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13780         {
13781           oappend (names_seg[ds_reg - es_reg]);
13782           oappend (":");
13783         }
13784     }
13785   print_operand_value (scratchbuf, 1, off);
13786   oappend (scratchbuf);
13787 }
13788
13789 static void
13790 ptr_reg (int code, int sizeflag)
13791 {
13792   const char *s;
13793
13794   *obufp++ = open_char;
13795   used_prefixes |= (prefixes & PREFIX_ADDR);
13796   if (address_mode == mode_64bit)
13797     {
13798       if (!(sizeflag & AFLAG))
13799         s = names32[code - eAX_reg];
13800       else
13801         s = names64[code - eAX_reg];
13802     }
13803   else if (sizeflag & AFLAG)
13804     s = names32[code - eAX_reg];
13805   else
13806     s = names16[code - eAX_reg];
13807   oappend (s);
13808   *obufp++ = close_char;
13809   *obufp = 0;
13810 }
13811
13812 static void
13813 OP_ESreg (int code, int sizeflag)
13814 {
13815   if (intel_syntax)
13816     {
13817       switch (codep[-1])
13818         {
13819         case 0x6d:      /* insw/insl */
13820           intel_operand_size (z_mode, sizeflag);
13821           break;
13822         case 0xa5:      /* movsw/movsl/movsq */
13823         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13824         case 0xab:      /* stosw/stosl */
13825         case 0xaf:      /* scasw/scasl */
13826           intel_operand_size (v_mode, sizeflag);
13827           break;
13828         default:
13829           intel_operand_size (b_mode, sizeflag);
13830         }
13831     }
13832   oappend ("%es:" + intel_syntax);
13833   ptr_reg (code, sizeflag);
13834 }
13835
13836 static void
13837 OP_DSreg (int code, int sizeflag)
13838 {
13839   if (intel_syntax)
13840     {
13841       switch (codep[-1])
13842         {
13843         case 0x6f:      /* outsw/outsl */
13844           intel_operand_size (z_mode, sizeflag);
13845           break;
13846         case 0xa5:      /* movsw/movsl/movsq */
13847         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13848         case 0xad:      /* lodsw/lodsl/lodsq */
13849           intel_operand_size (v_mode, sizeflag);
13850           break;
13851         default:
13852           intel_operand_size (b_mode, sizeflag);
13853         }
13854     }
13855   if ((prefixes
13856        & (PREFIX_CS
13857           | PREFIX_DS
13858           | PREFIX_SS
13859           | PREFIX_ES
13860           | PREFIX_FS
13861           | PREFIX_GS)) == 0)
13862     prefixes |= PREFIX_DS;
13863   append_seg ();
13864   ptr_reg (code, sizeflag);
13865 }
13866
13867 static void
13868 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13869 {
13870   int add;
13871   if (rex & REX_R)
13872     {
13873       USED_REX (REX_R);
13874       add = 8;
13875     }
13876   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13877     {
13878       all_prefixes[last_lock_prefix] = 0;
13879       used_prefixes |= PREFIX_LOCK;
13880       add = 8;
13881     }
13882   else
13883     add = 0;
13884   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13885   oappend (scratchbuf + intel_syntax);
13886 }
13887
13888 static void
13889 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13890 {
13891   int add;
13892   USED_REX (REX_R);
13893   if (rex & REX_R)
13894     add = 8;
13895   else
13896     add = 0;
13897   if (intel_syntax)
13898     sprintf (scratchbuf, "db%d", modrm.reg + add);
13899   else
13900     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13901   oappend (scratchbuf);
13902 }
13903
13904 static void
13905 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13906 {
13907   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13908   oappend (scratchbuf + intel_syntax);
13909 }
13910
13911 static void
13912 OP_R (int bytemode, int sizeflag)
13913 {
13914   if (modrm.mod == 3)
13915     OP_E (bytemode, sizeflag);
13916   else
13917     BadOp ();
13918 }
13919
13920 static void
13921 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13922 {
13923   int reg = modrm.reg;
13924   const char **names;
13925
13926   used_prefixes |= (prefixes & PREFIX_DATA);
13927   if (prefixes & PREFIX_DATA)
13928     {
13929       names = names_xmm;
13930       USED_REX (REX_R);
13931       if (rex & REX_R)
13932         reg += 8;
13933     }
13934   else
13935     names = names_mm;
13936   oappend (names[reg]);
13937 }
13938
13939 static void
13940 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13941 {
13942   int reg = modrm.reg;
13943   const char **names;
13944
13945   USED_REX (REX_R);
13946   if (rex & REX_R)
13947     reg += 8;
13948   if (need_vex
13949       && bytemode != xmm_mode
13950       && bytemode != scalar_mode)
13951     {
13952       switch (vex.length)
13953         {
13954         case 128:
13955           names = names_xmm;
13956           break;
13957         case 256:
13958           if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
13959             names = names_ymm;
13960           else
13961             names = names_xmm;
13962           break;
13963         default:
13964           abort ();
13965         }
13966     }
13967   else
13968     names = names_xmm;
13969   oappend (names[reg]);
13970 }
13971
13972 static void
13973 OP_EM (int bytemode, int sizeflag)
13974 {
13975   int reg;
13976   const char **names;
13977
13978   if (modrm.mod != 3)
13979     {
13980       if (intel_syntax
13981           && (bytemode == v_mode || bytemode == v_swap_mode))
13982         {
13983           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13984           used_prefixes |= (prefixes & PREFIX_DATA);
13985         }
13986       OP_E (bytemode, sizeflag);
13987       return;
13988     }
13989
13990   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13991     swap_operand ();
13992
13993   /* Skip mod/rm byte.  */
13994   MODRM_CHECK;
13995   codep++;
13996   used_prefixes |= (prefixes & PREFIX_DATA);
13997   reg = modrm.rm;
13998   if (prefixes & PREFIX_DATA)
13999     {
14000       names = names_xmm;
14001       USED_REX (REX_B);
14002       if (rex & REX_B)
14003         reg += 8;
14004     }
14005   else
14006     names = names_mm;
14007   oappend (names[reg]);
14008 }
14009
14010 /* cvt* are the only instructions in sse2 which have
14011    both SSE and MMX operands and also have 0x66 prefix
14012    in their opcode. 0x66 was originally used to differentiate
14013    between SSE and MMX instruction(operands). So we have to handle the
14014    cvt* separately using OP_EMC and OP_MXC */
14015 static void
14016 OP_EMC (int bytemode, int sizeflag)
14017 {
14018   if (modrm.mod != 3)
14019     {
14020       if (intel_syntax && bytemode == v_mode)
14021         {
14022           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14023           used_prefixes |= (prefixes & PREFIX_DATA);
14024         }
14025       OP_E (bytemode, sizeflag);
14026       return;
14027     }
14028
14029   /* Skip mod/rm byte.  */
14030   MODRM_CHECK;
14031   codep++;
14032   used_prefixes |= (prefixes & PREFIX_DATA);
14033   oappend (names_mm[modrm.rm]);
14034 }
14035
14036 static void
14037 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14038 {
14039   used_prefixes |= (prefixes & PREFIX_DATA);
14040   oappend (names_mm[modrm.reg]);
14041 }
14042
14043 static void
14044 OP_EX (int bytemode, int sizeflag)
14045 {
14046   int reg;
14047   const char **names;
14048
14049   /* Skip mod/rm byte.  */
14050   MODRM_CHECK;
14051   codep++;
14052
14053   if (modrm.mod != 3)
14054     {
14055       OP_E_memory (bytemode, sizeflag);
14056       return;
14057     }
14058
14059   reg = modrm.rm;
14060   USED_REX (REX_B);
14061   if (rex & REX_B)
14062     reg += 8;
14063
14064   if ((sizeflag & SUFFIX_ALWAYS)
14065       && (bytemode == x_swap_mode
14066           || bytemode == d_swap_mode
14067           || bytemode == d_scalar_swap_mode
14068           || bytemode == q_swap_mode
14069           || bytemode == q_scalar_swap_mode))
14070     swap_operand ();
14071
14072   if (need_vex
14073       && bytemode != xmm_mode
14074       && bytemode != xmmdw_mode
14075       && bytemode != xmmqd_mode
14076       && bytemode != xmm_mb_mode
14077       && bytemode != xmm_mw_mode
14078       && bytemode != xmm_md_mode
14079       && bytemode != xmm_mq_mode
14080       && bytemode != xmmq_mode
14081       && bytemode != d_scalar_mode
14082       && bytemode != d_scalar_swap_mode
14083       && bytemode != q_scalar_mode
14084       && bytemode != q_scalar_swap_mode
14085       && bytemode != vex_scalar_w_dq_mode)
14086     {
14087       switch (vex.length)
14088         {
14089         case 128:
14090           names = names_xmm;
14091           break;
14092         case 256:
14093           names = names_ymm;
14094           break;
14095         default:
14096           abort ();
14097         }
14098     }
14099   else
14100     names = names_xmm;
14101   oappend (names[reg]);
14102 }
14103
14104 static void
14105 OP_MS (int bytemode, int sizeflag)
14106 {
14107   if (modrm.mod == 3)
14108     OP_EM (bytemode, sizeflag);
14109   else
14110     BadOp ();
14111 }
14112
14113 static void
14114 OP_XS (int bytemode, int sizeflag)
14115 {
14116   if (modrm.mod == 3)
14117     OP_EX (bytemode, sizeflag);
14118   else
14119     BadOp ();
14120 }
14121
14122 static void
14123 OP_M (int bytemode, int sizeflag)
14124 {
14125   if (modrm.mod == 3)
14126     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14127     BadOp ();
14128   else
14129     OP_E (bytemode, sizeflag);
14130 }
14131
14132 static void
14133 OP_0f07 (int bytemode, int sizeflag)
14134 {
14135   if (modrm.mod != 3 || modrm.rm != 0)
14136     BadOp ();
14137   else
14138     OP_E (bytemode, sizeflag);
14139 }
14140
14141 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14142    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14143
14144 static void
14145 NOP_Fixup1 (int bytemode, int sizeflag)
14146 {
14147   if ((prefixes & PREFIX_DATA) != 0
14148       || (rex != 0
14149           && rex != 0x48
14150           && address_mode == mode_64bit))
14151     OP_REG (bytemode, sizeflag);
14152   else
14153     strcpy (obuf, "nop");
14154 }
14155
14156 static void
14157 NOP_Fixup2 (int bytemode, int sizeflag)
14158 {
14159   if ((prefixes & PREFIX_DATA) != 0
14160       || (rex != 0
14161           && rex != 0x48
14162           && address_mode == mode_64bit))
14163     OP_IMREG (bytemode, sizeflag);
14164 }
14165
14166 static const char *const Suffix3DNow[] = {
14167 /* 00 */        NULL,           NULL,           NULL,           NULL,
14168 /* 04 */        NULL,           NULL,           NULL,           NULL,
14169 /* 08 */        NULL,           NULL,           NULL,           NULL,
14170 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14171 /* 10 */        NULL,           NULL,           NULL,           NULL,
14172 /* 14 */        NULL,           NULL,           NULL,           NULL,
14173 /* 18 */        NULL,           NULL,           NULL,           NULL,
14174 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14175 /* 20 */        NULL,           NULL,           NULL,           NULL,
14176 /* 24 */        NULL,           NULL,           NULL,           NULL,
14177 /* 28 */        NULL,           NULL,           NULL,           NULL,
14178 /* 2C */        NULL,           NULL,           NULL,           NULL,
14179 /* 30 */        NULL,           NULL,           NULL,           NULL,
14180 /* 34 */        NULL,           NULL,           NULL,           NULL,
14181 /* 38 */        NULL,           NULL,           NULL,           NULL,
14182 /* 3C */        NULL,           NULL,           NULL,           NULL,
14183 /* 40 */        NULL,           NULL,           NULL,           NULL,
14184 /* 44 */        NULL,           NULL,           NULL,           NULL,
14185 /* 48 */        NULL,           NULL,           NULL,           NULL,
14186 /* 4C */        NULL,           NULL,           NULL,           NULL,
14187 /* 50 */        NULL,           NULL,           NULL,           NULL,
14188 /* 54 */        NULL,           NULL,           NULL,           NULL,
14189 /* 58 */        NULL,           NULL,           NULL,           NULL,
14190 /* 5C */        NULL,           NULL,           NULL,           NULL,
14191 /* 60 */        NULL,           NULL,           NULL,           NULL,
14192 /* 64 */        NULL,           NULL,           NULL,           NULL,
14193 /* 68 */        NULL,           NULL,           NULL,           NULL,
14194 /* 6C */        NULL,           NULL,           NULL,           NULL,
14195 /* 70 */        NULL,           NULL,           NULL,           NULL,
14196 /* 74 */        NULL,           NULL,           NULL,           NULL,
14197 /* 78 */        NULL,           NULL,           NULL,           NULL,
14198 /* 7C */        NULL,           NULL,           NULL,           NULL,
14199 /* 80 */        NULL,           NULL,           NULL,           NULL,
14200 /* 84 */        NULL,           NULL,           NULL,           NULL,
14201 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14202 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14203 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14204 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14205 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14206 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14207 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14208 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14209 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14210 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14211 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14212 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14213 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14214 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14215 /* C0 */        NULL,           NULL,           NULL,           NULL,
14216 /* C4 */        NULL,           NULL,           NULL,           NULL,
14217 /* C8 */        NULL,           NULL,           NULL,           NULL,
14218 /* CC */        NULL,           NULL,           NULL,           NULL,
14219 /* D0 */        NULL,           NULL,           NULL,           NULL,
14220 /* D4 */        NULL,           NULL,           NULL,           NULL,
14221 /* D8 */        NULL,           NULL,           NULL,           NULL,
14222 /* DC */        NULL,           NULL,           NULL,           NULL,
14223 /* E0 */        NULL,           NULL,           NULL,           NULL,
14224 /* E4 */        NULL,           NULL,           NULL,           NULL,
14225 /* E8 */        NULL,           NULL,           NULL,           NULL,
14226 /* EC */        NULL,           NULL,           NULL,           NULL,
14227 /* F0 */        NULL,           NULL,           NULL,           NULL,
14228 /* F4 */        NULL,           NULL,           NULL,           NULL,
14229 /* F8 */        NULL,           NULL,           NULL,           NULL,
14230 /* FC */        NULL,           NULL,           NULL,           NULL,
14231 };
14232
14233 static void
14234 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14235 {
14236   const char *mnemonic;
14237
14238   FETCH_DATA (the_info, codep + 1);
14239   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14240      place where an 8-bit immediate would normally go.  ie. the last
14241      byte of the instruction.  */
14242   obufp = mnemonicendp;
14243   mnemonic = Suffix3DNow[*codep++ & 0xff];
14244   if (mnemonic)
14245     oappend (mnemonic);
14246   else
14247     {
14248       /* Since a variable sized modrm/sib chunk is between the start
14249          of the opcode (0x0f0f) and the opcode suffix, we need to do
14250          all the modrm processing first, and don't know until now that
14251          we have a bad opcode.  This necessitates some cleaning up.  */
14252       op_out[0][0] = '\0';
14253       op_out[1][0] = '\0';
14254       BadOp ();
14255     }
14256   mnemonicendp = obufp;
14257 }
14258
14259 static struct op simd_cmp_op[] =
14260 {
14261   { STRING_COMMA_LEN ("eq") },
14262   { STRING_COMMA_LEN ("lt") },
14263   { STRING_COMMA_LEN ("le") },
14264   { STRING_COMMA_LEN ("unord") },
14265   { STRING_COMMA_LEN ("neq") },
14266   { STRING_COMMA_LEN ("nlt") },
14267   { STRING_COMMA_LEN ("nle") },
14268   { STRING_COMMA_LEN ("ord") }
14269 };
14270
14271 static void
14272 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14273 {
14274   unsigned int cmp_type;
14275
14276   FETCH_DATA (the_info, codep + 1);
14277   cmp_type = *codep++ & 0xff;
14278   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14279     {
14280       char suffix [3];
14281       char *p = mnemonicendp - 2;
14282       suffix[0] = p[0];
14283       suffix[1] = p[1];
14284       suffix[2] = '\0';
14285       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14286       mnemonicendp += simd_cmp_op[cmp_type].len;
14287     }
14288   else
14289     {
14290       /* We have a reserved extension byte.  Output it directly.  */
14291       scratchbuf[0] = '$';
14292       print_operand_value (scratchbuf + 1, 1, cmp_type);
14293       oappend (scratchbuf + intel_syntax);
14294       scratchbuf[0] = '\0';
14295     }
14296 }
14297
14298 static void
14299 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14300           int sizeflag ATTRIBUTE_UNUSED)
14301 {
14302   /* mwait %eax,%ecx  */
14303   if (!intel_syntax)
14304     {
14305       const char **names = (address_mode == mode_64bit
14306                             ? names64 : names32);
14307       strcpy (op_out[0], names[0]);
14308       strcpy (op_out[1], names[1]);
14309       two_source_ops = 1;
14310     }
14311   /* Skip mod/rm byte.  */
14312   MODRM_CHECK;
14313   codep++;
14314 }
14315
14316 static void
14317 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14318             int sizeflag ATTRIBUTE_UNUSED)
14319 {
14320   /* monitor %eax,%ecx,%edx"  */
14321   if (!intel_syntax)
14322     {
14323       const char **op1_names;
14324       const char **names = (address_mode == mode_64bit
14325                             ? names64 : names32);
14326
14327       if (!(prefixes & PREFIX_ADDR))
14328         op1_names = (address_mode == mode_16bit
14329                      ? names16 : names);
14330       else
14331         {
14332           /* Remove "addr16/addr32".  */
14333           all_prefixes[last_addr_prefix] = 0;
14334           op1_names = (address_mode != mode_32bit
14335                        ? names32 : names16);
14336           used_prefixes |= PREFIX_ADDR;
14337         }
14338       strcpy (op_out[0], op1_names[0]);
14339       strcpy (op_out[1], names[1]);
14340       strcpy (op_out[2], names[2]);
14341       two_source_ops = 1;
14342     }
14343   /* Skip mod/rm byte.  */
14344   MODRM_CHECK;
14345   codep++;
14346 }
14347
14348 static void
14349 BadOp (void)
14350 {
14351   /* Throw away prefixes and 1st. opcode byte.  */
14352   codep = insn_codep + 1;
14353   oappend ("(bad)");
14354 }
14355
14356 static void
14357 REP_Fixup (int bytemode, int sizeflag)
14358 {
14359   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14360      lods and stos.  */
14361   if (prefixes & PREFIX_REPZ)
14362     all_prefixes[last_repz_prefix] = REP_PREFIX;
14363
14364   switch (bytemode)
14365     {
14366     case al_reg:
14367     case eAX_reg:
14368     case indir_dx_reg:
14369       OP_IMREG (bytemode, sizeflag);
14370       break;
14371     case eDI_reg:
14372       OP_ESreg (bytemode, sizeflag);
14373       break;
14374     case eSI_reg:
14375       OP_DSreg (bytemode, sizeflag);
14376       break;
14377     default:
14378       abort ();
14379       break;
14380     }
14381 }
14382
14383 static void
14384 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14385 {
14386   USED_REX (REX_W);
14387   if (rex & REX_W)
14388     {
14389       /* Change cmpxchg8b to cmpxchg16b.  */
14390       char *p = mnemonicendp - 2;
14391       mnemonicendp = stpcpy (p, "16b");
14392       bytemode = o_mode;
14393     }
14394   OP_M (bytemode, sizeflag);
14395 }
14396
14397 static void
14398 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14399 {
14400   const char **names;
14401
14402   if (need_vex)
14403     {
14404       switch (vex.length)
14405         {
14406         case 128:
14407           names = names_xmm;
14408           break;
14409         case 256:
14410           names = names_ymm;
14411           break;
14412         default:
14413           abort ();
14414         }
14415     }
14416   else
14417     names = names_xmm;
14418   oappend (names[reg]);
14419 }
14420
14421 static void
14422 CRC32_Fixup (int bytemode, int sizeflag)
14423 {
14424   /* Add proper suffix to "crc32".  */
14425   char *p = mnemonicendp;
14426
14427   switch (bytemode)
14428     {
14429     case b_mode:
14430       if (intel_syntax)
14431         goto skip;
14432
14433       *p++ = 'b';
14434       break;
14435     case v_mode:
14436       if (intel_syntax)
14437         goto skip;
14438
14439       USED_REX (REX_W);
14440       if (rex & REX_W)
14441         *p++ = 'q';
14442       else
14443         {
14444           if (sizeflag & DFLAG)
14445             *p++ = 'l';
14446           else
14447             *p++ = 'w';
14448           used_prefixes |= (prefixes & PREFIX_DATA);
14449         }
14450       break;
14451     default:
14452       oappend (INTERNAL_DISASSEMBLER_ERROR);
14453       break;
14454     }
14455   mnemonicendp = p;
14456   *p = '\0';
14457
14458 skip:
14459   if (modrm.mod == 3)
14460     {
14461       int add;
14462
14463       /* Skip mod/rm byte.  */
14464       MODRM_CHECK;
14465       codep++;
14466
14467       USED_REX (REX_B);
14468       add = (rex & REX_B) ? 8 : 0;
14469       if (bytemode == b_mode)
14470         {
14471           USED_REX (0);
14472           if (rex)
14473             oappend (names8rex[modrm.rm + add]);
14474           else
14475             oappend (names8[modrm.rm + add]);
14476         }
14477       else
14478         {
14479           USED_REX (REX_W);
14480           if (rex & REX_W)
14481             oappend (names64[modrm.rm + add]);
14482           else if ((prefixes & PREFIX_DATA))
14483             oappend (names16[modrm.rm + add]);
14484           else
14485             oappend (names32[modrm.rm + add]);
14486         }
14487     }
14488   else
14489     OP_E (bytemode, sizeflag);
14490 }
14491
14492 static void
14493 FXSAVE_Fixup (int bytemode, int sizeflag)
14494 {
14495   /* Add proper suffix to "fxsave" and "fxrstor".  */
14496   USED_REX (REX_W);
14497   if (rex & REX_W)
14498     {
14499       char *p = mnemonicendp;
14500       *p++ = '6';
14501       *p++ = '4';
14502       *p = '\0';
14503       mnemonicendp = p;
14504     }
14505   OP_M (bytemode, sizeflag);
14506 }
14507
14508 /* Display the destination register operand for instructions with
14509    VEX. */
14510
14511 static void
14512 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14513 {
14514   int reg;
14515   const char **names;
14516
14517   if (!need_vex)
14518     abort ();
14519
14520   if (!need_vex_reg)
14521     return;
14522
14523   reg = vex.register_specifier;
14524   if (bytemode == vex_scalar_mode)
14525     {
14526       oappend (names_xmm[reg]);
14527       return;
14528     }
14529
14530   switch (vex.length)
14531     {
14532     case 128:
14533       switch (bytemode)
14534         {
14535         case vex_mode:
14536         case vex128_mode:
14537         case vex_vsib_q_w_dq_mode:
14538           names = names_xmm;
14539           break;
14540         case dq_mode:
14541           if (vex.w)
14542             names = names64;
14543           else
14544             names = names32;
14545           break;
14546         default:
14547           abort ();
14548           return;
14549         }
14550       break;
14551     case 256:
14552       switch (bytemode)
14553         {
14554         case vex_mode:
14555         case vex256_mode:
14556           names = names_ymm;
14557           break;
14558         case vex_vsib_q_w_dq_mode:
14559           names = vex.w ? names_ymm : names_xmm;
14560           break;
14561         default:
14562           abort ();
14563           return;
14564         }
14565       break;
14566     default:
14567       abort ();
14568       break;
14569     }
14570   oappend (names[reg]);
14571 }
14572
14573 /* Get the VEX immediate byte without moving codep.  */
14574
14575 static unsigned char
14576 get_vex_imm8 (int sizeflag, int opnum)
14577 {
14578   int bytes_before_imm = 0;
14579
14580   if (modrm.mod != 3)
14581     {
14582       /* There are SIB/displacement bytes.  */
14583       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14584         {
14585           /* 32/64 bit address mode */
14586           int base = modrm.rm;
14587
14588           /* Check SIB byte.  */
14589           if (base == 4)
14590             {
14591               FETCH_DATA (the_info, codep + 1);
14592               base = *codep & 7;
14593               /* When decoding the third source, don't increase
14594                  bytes_before_imm as this has already been incremented
14595                  by one in OP_E_memory while decoding the second
14596                  source operand.  */
14597               if (opnum == 0)
14598                 bytes_before_imm++;
14599             }
14600
14601           /* Don't increase bytes_before_imm when decoding the third source,
14602              it has already been incremented by OP_E_memory while decoding
14603              the second source operand.  */
14604           if (opnum == 0)
14605             {
14606               switch (modrm.mod)
14607                 {
14608                   case 0:
14609                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14610                        SIB == 5, there is a 4 byte displacement.  */
14611                     if (base != 5)
14612                       /* No displacement. */
14613                       break;
14614                   case 2:
14615                     /* 4 byte displacement.  */
14616                     bytes_before_imm += 4;
14617                     break;
14618                   case 1:
14619                     /* 1 byte displacement.  */
14620                     bytes_before_imm++;
14621                     break;
14622                 }
14623             }
14624         }
14625       else
14626         {
14627           /* 16 bit address mode */
14628           /* Don't increase bytes_before_imm when decoding the third source,
14629              it has already been incremented by OP_E_memory while decoding
14630              the second source operand.  */
14631           if (opnum == 0)
14632             {
14633               switch (modrm.mod)
14634                 {
14635                 case 0:
14636                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14637                   if (modrm.rm != 6)
14638                     /* No displacement. */
14639                     break;
14640                 case 2:
14641                   /* 2 byte displacement.  */
14642                   bytes_before_imm += 2;
14643                   break;
14644                 case 1:
14645                   /* 1 byte displacement: when decoding the third source,
14646                      don't increase bytes_before_imm as this has already
14647                      been incremented by one in OP_E_memory while decoding
14648                      the second source operand.  */
14649                   if (opnum == 0)
14650                     bytes_before_imm++;
14651
14652                   break;
14653                 }
14654             }
14655         }
14656     }
14657
14658   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14659   return codep [bytes_before_imm];
14660 }
14661
14662 static void
14663 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14664 {
14665   const char **names;
14666
14667   if (reg == -1 && modrm.mod != 3)
14668     {
14669       OP_E_memory (bytemode, sizeflag);
14670       return;
14671     }
14672   else
14673     {
14674       if (reg == -1)
14675         {
14676           reg = modrm.rm;
14677           USED_REX (REX_B);
14678           if (rex & REX_B)
14679             reg += 8;
14680         }
14681       else if (reg > 7 && address_mode != mode_64bit)
14682         BadOp ();
14683     }
14684
14685   switch (vex.length)
14686     {
14687     case 128:
14688       names = names_xmm;
14689       break;
14690     case 256:
14691       names = names_ymm;
14692       break;
14693     default:
14694       abort ();
14695     }
14696   oappend (names[reg]);
14697 }
14698
14699 static void
14700 OP_EX_VexImmW (int bytemode, int sizeflag)
14701 {
14702   int reg = -1;
14703   static unsigned char vex_imm8;
14704
14705   if (vex_w_done == 0)
14706     {
14707       vex_w_done = 1;
14708
14709       /* Skip mod/rm byte.  */
14710       MODRM_CHECK;
14711       codep++;
14712
14713       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14714
14715       if (vex.w)
14716           reg = vex_imm8 >> 4;
14717
14718       OP_EX_VexReg (bytemode, sizeflag, reg);
14719     }
14720   else if (vex_w_done == 1)
14721     {
14722       vex_w_done = 2;
14723
14724       if (!vex.w)
14725           reg = vex_imm8 >> 4;
14726
14727       OP_EX_VexReg (bytemode, sizeflag, reg);
14728     }
14729   else
14730     {
14731       /* Output the imm8 directly.  */
14732       scratchbuf[0] = '$';
14733       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14734       oappend (scratchbuf + intel_syntax);
14735       scratchbuf[0] = '\0';
14736       codep++;
14737     }
14738 }
14739
14740 static void
14741 OP_Vex_2src (int bytemode, int sizeflag)
14742 {
14743   if (modrm.mod == 3)
14744     {
14745       int reg = modrm.rm;
14746       USED_REX (REX_B);
14747       if (rex & REX_B)
14748         reg += 8;
14749       oappend (names_xmm[reg]);
14750     }
14751   else
14752     {
14753       if (intel_syntax
14754           && (bytemode == v_mode || bytemode == v_swap_mode))
14755         {
14756           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14757           used_prefixes |= (prefixes & PREFIX_DATA);
14758         }
14759       OP_E (bytemode, sizeflag);
14760     }
14761 }
14762
14763 static void
14764 OP_Vex_2src_1 (int bytemode, int sizeflag)
14765 {
14766   if (modrm.mod == 3)
14767     {
14768       /* Skip mod/rm byte.   */
14769       MODRM_CHECK;
14770       codep++;
14771     }
14772
14773   if (vex.w)
14774     oappend (names_xmm[vex.register_specifier]);
14775   else
14776     OP_Vex_2src (bytemode, sizeflag);
14777 }
14778
14779 static void
14780 OP_Vex_2src_2 (int bytemode, int sizeflag)
14781 {
14782   if (vex.w)
14783     OP_Vex_2src (bytemode, sizeflag);
14784   else
14785     oappend (names_xmm[vex.register_specifier]);
14786 }
14787
14788 static void
14789 OP_EX_VexW (int bytemode, int sizeflag)
14790 {
14791   int reg = -1;
14792
14793   if (!vex_w_done)
14794     {
14795       vex_w_done = 1;
14796
14797       /* Skip mod/rm byte.  */
14798       MODRM_CHECK;
14799       codep++;
14800
14801       if (vex.w)
14802         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14803     }
14804   else
14805     {
14806       if (!vex.w)
14807         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14808     }
14809
14810   OP_EX_VexReg (bytemode, sizeflag, reg);
14811 }
14812
14813 static void
14814 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14815              int sizeflag ATTRIBUTE_UNUSED)
14816 {
14817   /* Skip the immediate byte and check for invalid bits.  */
14818   FETCH_DATA (the_info, codep + 1);
14819   if (*codep++ & 0xf)
14820     BadOp ();
14821 }
14822
14823 static void
14824 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14825 {
14826   int reg;
14827   const char **names;
14828
14829   FETCH_DATA (the_info, codep + 1);
14830   reg = *codep++;
14831
14832   if (bytemode != x_mode)
14833     abort ();
14834
14835   if (reg & 0xf)
14836       BadOp ();
14837
14838   reg >>= 4;
14839   if (reg > 7 && address_mode != mode_64bit)
14840     BadOp ();
14841
14842   switch (vex.length)
14843     {
14844     case 128:
14845       names = names_xmm;
14846       break;
14847     case 256:
14848       names = names_ymm;
14849       break;
14850     default:
14851       abort ();
14852     }
14853   oappend (names[reg]);
14854 }
14855
14856 static void
14857 OP_XMM_VexW (int bytemode, int sizeflag)
14858 {
14859   /* Turn off the REX.W bit since it is used for swapping operands
14860      now.  */
14861   rex &= ~REX_W;
14862   OP_XMM (bytemode, sizeflag);
14863 }
14864
14865 static void
14866 OP_EX_Vex (int bytemode, int sizeflag)
14867 {
14868   if (modrm.mod != 3)
14869     {
14870       if (vex.register_specifier != 0)
14871         BadOp ();
14872       need_vex_reg = 0;
14873     }
14874   OP_EX (bytemode, sizeflag);
14875 }
14876
14877 static void
14878 OP_XMM_Vex (int bytemode, int sizeflag)
14879 {
14880   if (modrm.mod != 3)
14881     {
14882       if (vex.register_specifier != 0)
14883         BadOp ();
14884       need_vex_reg = 0;
14885     }
14886   OP_XMM (bytemode, sizeflag);
14887 }
14888
14889 static void
14890 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14891 {
14892   switch (vex.length)
14893     {
14894     case 128:
14895       mnemonicendp = stpcpy (obuf, "vzeroupper");
14896       break;
14897     case 256:
14898       mnemonicendp = stpcpy (obuf, "vzeroall");
14899       break;
14900     default:
14901       abort ();
14902     }
14903 }
14904
14905 static struct op vex_cmp_op[] =
14906 {
14907   { STRING_COMMA_LEN ("eq") },
14908   { STRING_COMMA_LEN ("lt") },
14909   { STRING_COMMA_LEN ("le") },
14910   { STRING_COMMA_LEN ("unord") },
14911   { STRING_COMMA_LEN ("neq") },
14912   { STRING_COMMA_LEN ("nlt") },
14913   { STRING_COMMA_LEN ("nle") },
14914   { STRING_COMMA_LEN ("ord") },
14915   { STRING_COMMA_LEN ("eq_uq") },
14916   { STRING_COMMA_LEN ("nge") },
14917   { STRING_COMMA_LEN ("ngt") },
14918   { STRING_COMMA_LEN ("false") },
14919   { STRING_COMMA_LEN ("neq_oq") },
14920   { STRING_COMMA_LEN ("ge") },
14921   { STRING_COMMA_LEN ("gt") },
14922   { STRING_COMMA_LEN ("true") },
14923   { STRING_COMMA_LEN ("eq_os") },
14924   { STRING_COMMA_LEN ("lt_oq") },
14925   { STRING_COMMA_LEN ("le_oq") },
14926   { STRING_COMMA_LEN ("unord_s") },
14927   { STRING_COMMA_LEN ("neq_us") },
14928   { STRING_COMMA_LEN ("nlt_uq") },
14929   { STRING_COMMA_LEN ("nle_uq") },
14930   { STRING_COMMA_LEN ("ord_s") },
14931   { STRING_COMMA_LEN ("eq_us") },
14932   { STRING_COMMA_LEN ("nge_uq") },
14933   { STRING_COMMA_LEN ("ngt_uq") },
14934   { STRING_COMMA_LEN ("false_os") },
14935   { STRING_COMMA_LEN ("neq_os") },
14936   { STRING_COMMA_LEN ("ge_oq") },
14937   { STRING_COMMA_LEN ("gt_oq") },
14938   { STRING_COMMA_LEN ("true_us") },
14939 };
14940
14941 static void
14942 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14943 {
14944   unsigned int cmp_type;
14945
14946   FETCH_DATA (the_info, codep + 1);
14947   cmp_type = *codep++ & 0xff;
14948   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14949     {
14950       char suffix [3];
14951       char *p = mnemonicendp - 2;
14952       suffix[0] = p[0];
14953       suffix[1] = p[1];
14954       suffix[2] = '\0';
14955       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14956       mnemonicendp += vex_cmp_op[cmp_type].len;
14957     }
14958   else
14959     {
14960       /* We have a reserved extension byte.  Output it directly.  */
14961       scratchbuf[0] = '$';
14962       print_operand_value (scratchbuf + 1, 1, cmp_type);
14963       oappend (scratchbuf + intel_syntax);
14964       scratchbuf[0] = '\0';
14965     }
14966 }
14967
14968 static const struct op pclmul_op[] =
14969 {
14970   { STRING_COMMA_LEN ("lql") },
14971   { STRING_COMMA_LEN ("hql") },
14972   { STRING_COMMA_LEN ("lqh") },
14973   { STRING_COMMA_LEN ("hqh") }
14974 };
14975
14976 static void
14977 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14978               int sizeflag ATTRIBUTE_UNUSED)
14979 {
14980   unsigned int pclmul_type;
14981
14982   FETCH_DATA (the_info, codep + 1);
14983   pclmul_type = *codep++ & 0xff;
14984   switch (pclmul_type)
14985     {
14986     case 0x10:
14987       pclmul_type = 2;
14988       break;
14989     case 0x11:
14990       pclmul_type = 3;
14991       break;
14992     default:
14993       break;
14994     }
14995   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14996     {
14997       char suffix [4];
14998       char *p = mnemonicendp - 3;
14999       suffix[0] = p[0];
15000       suffix[1] = p[1];
15001       suffix[2] = p[2];
15002       suffix[3] = '\0';
15003       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15004       mnemonicendp += pclmul_op[pclmul_type].len;
15005     }
15006   else
15007     {
15008       /* We have a reserved extension byte.  Output it directly.  */
15009       scratchbuf[0] = '$';
15010       print_operand_value (scratchbuf + 1, 1, pclmul_type);
15011       oappend (scratchbuf + intel_syntax);
15012       scratchbuf[0] = '\0';
15013     }
15014 }
15015
15016 static void
15017 MOVBE_Fixup (int bytemode, int sizeflag)
15018 {
15019   /* Add proper suffix to "movbe".  */
15020   char *p = mnemonicendp;
15021
15022   switch (bytemode)
15023     {
15024     case v_mode:
15025       if (intel_syntax)
15026         goto skip;
15027
15028       USED_REX (REX_W);
15029       if (sizeflag & SUFFIX_ALWAYS)
15030         {
15031           if (rex & REX_W)
15032             *p++ = 'q';
15033           else
15034             {
15035               if (sizeflag & DFLAG)
15036                 *p++ = 'l';
15037               else
15038                 *p++ = 'w';
15039               used_prefixes |= (prefixes & PREFIX_DATA);
15040             }
15041         }
15042       break;
15043     default:
15044       oappend (INTERNAL_DISASSEMBLER_ERROR);
15045       break;
15046     }
15047   mnemonicendp = p;
15048   *p = '\0';
15049
15050 skip:
15051   OP_M (bytemode, sizeflag);
15052 }
15053
15054 static void
15055 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15056 {
15057   int reg;
15058   const char **names;
15059
15060   /* Skip mod/rm byte.  */
15061   MODRM_CHECK;
15062   codep++;
15063
15064   if (vex.w)
15065     names = names64;
15066   else
15067     names = names32;
15068
15069   reg = modrm.rm;
15070   USED_REX (REX_B);
15071   if (rex & REX_B)
15072     reg += 8;
15073
15074   oappend (names[reg]);
15075 }
15076
15077 static void
15078 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15079 {
15080   const char **names;
15081
15082   if (vex.w)
15083     names = names64;
15084   else
15085     names = names32;
15086
15087   oappend (names[vex.register_specifier]);
15088 }
15089