1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 modified by John Hassey (hassey@dg-rtp.dg.com)
24 x86-64 support added by Jan Hubicka (jh@suse.cz)
25 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27 /* The main tables describing the instructions is essentially a copy
28 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
29 Programmers Manual. Usually, there is a capital letter, followed
30 by a small letter. The capital letter tell the addressing mode,
31 and the small letter tells about the operand size. Refer to
32 the Intel manual for details. */
42 #ifndef UNIXWARE_COMPAT
43 /* Set non-zero for broken, compatible instructions. Set to zero for
44 non-broken opcodes. */
45 #define UNIXWARE_COMPAT 1
48 static int fetch_data (struct disassemble_info
*, bfd_byte
*);
49 static void ckprefix (void);
50 static const char *prefix_name (int, int);
51 static int print_insn (bfd_vma
, disassemble_info
*);
52 static void dofloat (int);
53 static void OP_ST (int, int);
54 static void OP_STi (int, int);
55 static int putop (const char *, int);
56 static void oappend (const char *);
57 static void append_seg (void);
58 static void OP_indirE (int, int);
59 static void print_operand_value (char *, int, bfd_vma
);
60 static void OP_E (int, int);
61 static void OP_G (int, int);
62 static bfd_vma
get64 (void);
63 static bfd_signed_vma
get32 (void);
64 static bfd_signed_vma
get32s (void);
65 static int get16 (void);
66 static void set_op (bfd_vma
, int);
67 static void OP_REG (int, int);
68 static void OP_IMREG (int, int);
69 static void OP_I (int, int);
70 static void OP_I64 (int, int);
71 static void OP_sI (int, int);
72 static void OP_J (int, int);
73 static void OP_SEG (int, int);
74 static void OP_DIR (int, int);
75 static void OP_OFF (int, int);
76 static void OP_OFF64 (int, int);
77 static void ptr_reg (int, int);
78 static void OP_ESreg (int, int);
79 static void OP_DSreg (int, int);
80 static void OP_C (int, int);
81 static void OP_D (int, int);
82 static void OP_T (int, int);
83 static void OP_Rd (int, int);
84 static void OP_MMX (int, int);
85 static void OP_XMM (int, int);
86 static void OP_EM (int, int);
87 static void OP_EX (int, int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VMX (int, int);
92 static void OP_0fae (int, int);
93 static void OP_0f07 (int, int);
94 static void NOP_Fixup1 (int, int);
95 static void NOP_Fixup2 (int, int);
96 static void OP_3DNowSuffix (int, int);
97 static void OP_SIMD_Suffix (int, int);
98 static void SIMD_Fixup (int, int);
99 static void PNI_Fixup (int, int);
100 static void SVME_Fixup (int, int);
101 static void INVLPG_Fixup (int, int);
102 static void BadOp (void);
103 static void SEG_Fixup (int, int);
104 static void VMX_Fixup (int, int);
105 static void REP_Fixup (int, int);
108 /* Points to first byte not fetched. */
109 bfd_byte
*max_fetched
;
110 bfd_byte the_buffer
[MAXLEN
];
116 /* The opcode for the fwait instruction, which we treat as a prefix
118 #define FWAIT_OPCODE (0x9b)
127 enum address_mode address_mode
;
129 /* Flags for the prefixes for the current instruction. See below. */
132 /* REX prefix the current instruction. See below. */
134 /* Bits of REX we've already used. */
140 /* Mark parts used in the REX prefix. When we are testing for
141 empty prefix (for 8bit register REX extension), just mask it
142 out. Otherwise test for REX bit is excuse for existence of REX
143 only in case value is nonzero. */
144 #define USED_REX(value) \
147 rex_used |= (rex & value) ? (value) | 0x40 : 0; \
152 /* Flags for prefixes which we somehow handled when printing the
153 current instruction. */
154 static int used_prefixes
;
156 /* Flags stored in PREFIXES. */
157 #define PREFIX_REPZ 1
158 #define PREFIX_REPNZ 2
159 #define PREFIX_LOCK 4
161 #define PREFIX_SS 0x10
162 #define PREFIX_DS 0x20
163 #define PREFIX_ES 0x40
164 #define PREFIX_FS 0x80
165 #define PREFIX_GS 0x100
166 #define PREFIX_DATA 0x200
167 #define PREFIX_ADDR 0x400
168 #define PREFIX_FWAIT 0x800
170 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
171 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
173 #define FETCH_DATA(info, addr) \
174 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
175 ? 1 : fetch_data ((info), (addr)))
178 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
181 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
182 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
184 if (addr
<= priv
->the_buffer
+ MAXLEN
)
185 status
= (*info
->read_memory_func
) (start
,
187 addr
- priv
->max_fetched
,
193 /* If we did manage to read at least one byte, then
194 print_insn_i386 will do something sensible. Otherwise, print
195 an error. We do that here because this is where we know
197 if (priv
->max_fetched
== priv
->the_buffer
)
198 (*info
->memory_error_func
) (status
, start
, info
);
199 longjmp (priv
->bailout
, 1);
202 priv
->max_fetched
= addr
;
208 #define Eb OP_E, b_mode
209 #define Ev OP_E, v_mode
210 #define Ed OP_E, d_mode
211 #define Eq OP_E, q_mode
212 #define Edq OP_E, dq_mode
213 #define Edqw OP_E, dqw_mode
214 #define indirEv OP_indirE, stack_v_mode
215 #define indirEp OP_indirE, f_mode
216 #define stackEv OP_E, stack_v_mode
217 #define Em OP_E, m_mode
218 #define Ew OP_E, w_mode
219 #define Ma OP_E, v_mode
220 #define M OP_M, 0 /* lea, lgdt, etc. */
221 #define Mp OP_M, f_mode /* 32 or 48 bit memory operand for LDS, LES etc */
222 #define Gb OP_G, b_mode
223 #define Gv OP_G, v_mode
224 #define Gd OP_G, d_mode
225 #define Gdq OP_G, dq_mode
226 #define Gm OP_G, m_mode
227 #define Gw OP_G, w_mode
228 #define Rd OP_Rd, d_mode
229 #define Rm OP_Rd, m_mode
230 #define Ib OP_I, b_mode
231 #define sIb OP_sI, b_mode /* sign extened byte */
232 #define Iv OP_I, v_mode
233 #define Iq OP_I, q_mode
234 #define Iv64 OP_I64, v_mode
235 #define Iw OP_I, w_mode
236 #define I1 OP_I, const_1_mode
237 #define Jb OP_J, b_mode
238 #define Jv OP_J, v_mode
239 #define Cm OP_C, m_mode
240 #define Dm OP_D, m_mode
241 #define Td OP_T, d_mode
242 #define Sv SEG_Fixup, v_mode
244 #define RMeAX OP_REG, eAX_reg
245 #define RMeBX OP_REG, eBX_reg
246 #define RMeCX OP_REG, eCX_reg
247 #define RMeDX OP_REG, eDX_reg
248 #define RMeSP OP_REG, eSP_reg
249 #define RMeBP OP_REG, eBP_reg
250 #define RMeSI OP_REG, eSI_reg
251 #define RMeDI OP_REG, eDI_reg
252 #define RMrAX OP_REG, rAX_reg
253 #define RMrBX OP_REG, rBX_reg
254 #define RMrCX OP_REG, rCX_reg
255 #define RMrDX OP_REG, rDX_reg
256 #define RMrSP OP_REG, rSP_reg
257 #define RMrBP OP_REG, rBP_reg
258 #define RMrSI OP_REG, rSI_reg
259 #define RMrDI OP_REG, rDI_reg
260 #define RMAL OP_REG, al_reg
261 #define RMAL OP_REG, al_reg
262 #define RMCL OP_REG, cl_reg
263 #define RMDL OP_REG, dl_reg
264 #define RMBL OP_REG, bl_reg
265 #define RMAH OP_REG, ah_reg
266 #define RMCH OP_REG, ch_reg
267 #define RMDH OP_REG, dh_reg
268 #define RMBH OP_REG, bh_reg
269 #define RMAX OP_REG, ax_reg
270 #define RMDX OP_REG, dx_reg
272 #define eAX OP_IMREG, eAX_reg
273 #define eBX OP_IMREG, eBX_reg
274 #define eCX OP_IMREG, eCX_reg
275 #define eDX OP_IMREG, eDX_reg
276 #define eSP OP_IMREG, eSP_reg
277 #define eBP OP_IMREG, eBP_reg
278 #define eSI OP_IMREG, eSI_reg
279 #define eDI OP_IMREG, eDI_reg
280 #define AL OP_IMREG, al_reg
281 #define CL OP_IMREG, cl_reg
282 #define DL OP_IMREG, dl_reg
283 #define BL OP_IMREG, bl_reg
284 #define AH OP_IMREG, ah_reg
285 #define CH OP_IMREG, ch_reg
286 #define DH OP_IMREG, dh_reg
287 #define BH OP_IMREG, bh_reg
288 #define AX OP_IMREG, ax_reg
289 #define DX OP_IMREG, dx_reg
290 #define indirDX OP_IMREG, indir_dx_reg
292 #define Sw OP_SEG, w_mode
294 #define Ob OP_OFF64, b_mode
295 #define Ov OP_OFF64, v_mode
296 #define Xb OP_DSreg, eSI_reg
297 #define Xv OP_DSreg, eSI_reg
298 #define Yb OP_ESreg, eDI_reg
299 #define Yv OP_ESreg, eDI_reg
300 #define DSBX OP_DSreg, eBX_reg
302 #define es OP_REG, es_reg
303 #define ss OP_REG, ss_reg
304 #define cs OP_REG, cs_reg
305 #define ds OP_REG, ds_reg
306 #define fs OP_REG, fs_reg
307 #define gs OP_REG, gs_reg
311 #define EM OP_EM, v_mode
312 #define EX OP_EX, v_mode
313 #define MS OP_MS, v_mode
314 #define XS OP_XS, v_mode
315 #define VM OP_VMX, q_mode
316 #define OPSUF OP_3DNowSuffix, 0
317 #define OPSIMD OP_SIMD_Suffix, 0
319 /* Used handle "rep" prefix for string instructions. */
320 #define Xbr REP_Fixup, eSI_reg
321 #define Xvr REP_Fixup, eSI_reg
322 #define Ybr REP_Fixup, eDI_reg
323 #define Yvr REP_Fixup, eDI_reg
324 #define indirDXr REP_Fixup, indir_dx_reg
325 #define ALr REP_Fixup, al_reg
326 #define eAXr REP_Fixup, eAX_reg
328 #define cond_jump_flag NULL, cond_jump_mode
329 #define loop_jcxz_flag NULL, loop_jcxz_mode
331 /* bits in sizeflag */
332 #define SUFFIX_ALWAYS 4
336 #define b_mode 1 /* byte operand */
337 #define v_mode 2 /* operand size depends on prefixes */
338 #define w_mode 3 /* word operand */
339 #define d_mode 4 /* double word operand */
340 #define q_mode 5 /* quad word operand */
341 #define t_mode 6 /* ten-byte operand */
342 #define x_mode 7 /* 16-byte XMM operand */
343 #define m_mode 8 /* d_mode in 32bit, q_mode in 64bit mode. */
344 #define cond_jump_mode 9
345 #define loop_jcxz_mode 10
346 #define dq_mode 11 /* operand size depends on REX prefixes. */
347 #define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
348 #define f_mode 13 /* 4- or 6-byte pointer operand */
349 #define const_1_mode 14
350 #define stack_v_mode 15 /* v_mode for stack-related opcodes. */
395 #define indir_dx_reg 150
399 #define USE_PREFIX_USER_TABLE 3
400 #define X86_64_SPECIAL 4
401 #define IS_3BYTE_OPCODE 5
403 #define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0, NULL, 0
405 #define GRP1b NULL, NULL, USE_GROUPS, NULL, 0, NULL, 0, NULL, 0
406 #define GRP1S NULL, NULL, USE_GROUPS, NULL, 1, NULL, 0, NULL, 0
407 #define GRP1Ss NULL, NULL, USE_GROUPS, NULL, 2, NULL, 0, NULL, 0
408 #define GRP2b NULL, NULL, USE_GROUPS, NULL, 3, NULL, 0, NULL, 0
409 #define GRP2S NULL, NULL, USE_GROUPS, NULL, 4, NULL, 0, NULL, 0
410 #define GRP2b_one NULL, NULL, USE_GROUPS, NULL, 5, NULL, 0, NULL, 0
411 #define GRP2S_one NULL, NULL, USE_GROUPS, NULL, 6, NULL, 0, NULL, 0
412 #define GRP2b_cl NULL, NULL, USE_GROUPS, NULL, 7, NULL, 0, NULL, 0
413 #define GRP2S_cl NULL, NULL, USE_GROUPS, NULL, 8, NULL, 0, NULL, 0
414 #define GRP3b NULL, NULL, USE_GROUPS, NULL, 9, NULL, 0, NULL, 0
415 #define GRP3S NULL, NULL, USE_GROUPS, NULL, 10, NULL, 0, NULL, 0
416 #define GRP4 NULL, NULL, USE_GROUPS, NULL, 11, NULL, 0, NULL, 0
417 #define GRP5 NULL, NULL, USE_GROUPS, NULL, 12, NULL, 0, NULL, 0
418 #define GRP6 NULL, NULL, USE_GROUPS, NULL, 13, NULL, 0, NULL, 0
419 #define GRP7 NULL, NULL, USE_GROUPS, NULL, 14, NULL, 0, NULL, 0
420 #define GRP8 NULL, NULL, USE_GROUPS, NULL, 15, NULL, 0, NULL, 0
421 #define GRP9 NULL, NULL, USE_GROUPS, NULL, 16, NULL, 0, NULL, 0
422 #define GRP11_C6 NULL, NULL, USE_GROUPS, NULL, 17, NULL, 0, NULL, 0
423 #define GRP11_C7 NULL, NULL, USE_GROUPS, NULL, 18, NULL, 0, NULL, 0
424 #define GRP12 NULL, NULL, USE_GROUPS, NULL, 19, NULL, 0, NULL, 0
425 #define GRP13 NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0, NULL, 0
426 #define GRP14 NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0, NULL, 0
427 #define GRP15 NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0, NULL, 0
428 #define GRP16 NULL, NULL, USE_GROUPS, NULL, 23, NULL, 0, NULL, 0
429 #define GRPAMD NULL, NULL, USE_GROUPS, NULL, 24, NULL, 0, NULL, 0
430 #define GRPPADLCK1 NULL, NULL, USE_GROUPS, NULL, 25, NULL, 0, NULL, 0
431 #define GRPPADLCK2 NULL, NULL, USE_GROUPS, NULL, 26, NULL, 0, NULL, 0
433 #define PREGRP0 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 0, NULL, 0, NULL, 0
434 #define PREGRP1 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 1, NULL, 0, NULL, 0
435 #define PREGRP2 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 2, NULL, 0, NULL, 0
436 #define PREGRP3 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 3, NULL, 0, NULL, 0
437 #define PREGRP4 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 4, NULL, 0, NULL, 0
438 #define PREGRP5 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 5, NULL, 0, NULL, 0
439 #define PREGRP6 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 6, NULL, 0, NULL, 0
440 #define PREGRP7 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 7, NULL, 0, NULL, 0
441 #define PREGRP8 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 8, NULL, 0, NULL, 0
442 #define PREGRP9 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 9, NULL, 0, NULL, 0
443 #define PREGRP10 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 10, NULL, 0, NULL, 0
444 #define PREGRP11 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 11, NULL, 0, NULL, 0
445 #define PREGRP12 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 12, NULL, 0, NULL, 0
446 #define PREGRP13 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 13, NULL, 0, NULL, 0
447 #define PREGRP14 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 14, NULL, 0, NULL, 0
448 #define PREGRP15 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 15, NULL, 0, NULL, 0
449 #define PREGRP16 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 16, NULL, 0, NULL, 0
450 #define PREGRP17 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 17, NULL, 0, NULL, 0
451 #define PREGRP18 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 18, NULL, 0, NULL, 0
452 #define PREGRP19 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 19, NULL, 0, NULL, 0
453 #define PREGRP20 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 20, NULL, 0, NULL, 0
454 #define PREGRP21 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 21, NULL, 0, NULL, 0
455 #define PREGRP22 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 22, NULL, 0, NULL, 0
456 #define PREGRP23 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 23, NULL, 0, NULL, 0
457 #define PREGRP24 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0, NULL, 0
458 #define PREGRP25 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0, NULL, 0
459 #define PREGRP26 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0, NULL, 0
460 #define PREGRP27 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 27, NULL, 0, NULL, 0
461 #define PREGRP28 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 28, NULL, 0, NULL, 0
462 #define PREGRP29 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 29, NULL, 0, NULL, 0
463 #define PREGRP30 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 30, NULL, 0, NULL, 0
464 #define PREGRP31 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 31, NULL, 0, NULL, 0
465 #define PREGRP32 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 32, NULL, 0, NULL, 0
466 #define PREGRP33 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 33, NULL, 0, NULL, 0
467 #define PREGRP34 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 34, NULL, 0, NULL, 0
468 #define PREGRP35 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 35, NULL, 0, NULL, 0
469 #define PREGRP36 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 36, NULL, 0, NULL, 0
471 #define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0, NULL, 0
473 #define THREE_BYTE_0 NULL, NULL, IS_3BYTE_OPCODE, NULL, 0, NULL, 0, NULL, 0
474 #define THREE_BYTE_1 NULL, NULL, IS_3BYTE_OPCODE, NULL, 1, NULL, 0, NULL, 0
476 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
490 /* Upper case letters in the instruction names here are macros.
491 'A' => print 'b' if no register operands or suffix_always is true
492 'B' => print 'b' if suffix_always is true
493 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
495 'E' => print 'e' if 32-bit form of jcxz
496 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
497 'H' => print ",pt" or ",pn" branch hint
498 'I' => honor following macro letter even in Intel mode (implemented only
499 . for some of the macro letters)
501 'L' => print 'l' if suffix_always is true
502 'N' => print 'n' if instruction has no wait "prefix"
503 'O' => print 'd', or 'o'
504 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
505 . or suffix_always is true. print 'q' if rex prefix is present.
506 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
508 'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode)
509 'S' => print 'w', 'l' or 'q' if suffix_always is true
510 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
511 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
512 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
513 'W' => print 'b' or 'w' ("w" or "de" in intel mode)
514 'X' => print 's', 'd' depending on data16 prefix (for XMM)
515 'Y' => 'q' if instruction has an REX 64bit overwrite prefix
516 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
518 Many of the above letters print nothing in Intel mode. See "putop"
521 Braces '{' and '}', and vertical bars '|', indicate alternative
522 mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel
523 modes. In cases where there are only two alternatives, the X86_64
524 instruction is reserved, and "(bad)" is printed.
527 static const struct dis386 dis386
[] = {
529 { "addB", Eb
, Gb
, XX
, XX
},
530 { "addS", Ev
, Gv
, XX
, XX
},
531 { "addB", Gb
, Eb
, XX
, XX
},
532 { "addS", Gv
, Ev
, XX
, XX
},
533 { "addB", AL
, Ib
, XX
, XX
},
534 { "addS", eAX
, Iv
, XX
, XX
},
535 { "push{T|}", es
, XX
, XX
, XX
},
536 { "pop{T|}", es
, XX
, XX
, XX
},
538 { "orB", Eb
, Gb
, XX
, XX
},
539 { "orS", Ev
, Gv
, XX
, XX
},
540 { "orB", Gb
, Eb
, XX
, XX
},
541 { "orS", Gv
, Ev
, XX
, XX
},
542 { "orB", AL
, Ib
, XX
, XX
},
543 { "orS", eAX
, Iv
, XX
, XX
},
544 { "push{T|}", cs
, XX
, XX
, XX
},
545 { "(bad)", XX
, XX
, XX
, XX
}, /* 0x0f extended opcode escape */
547 { "adcB", Eb
, Gb
, XX
, XX
},
548 { "adcS", Ev
, Gv
, XX
, XX
},
549 { "adcB", Gb
, Eb
, XX
, XX
},
550 { "adcS", Gv
, Ev
, XX
, XX
},
551 { "adcB", AL
, Ib
, XX
, XX
},
552 { "adcS", eAX
, Iv
, XX
, XX
},
553 { "push{T|}", ss
, XX
, XX
, XX
},
554 { "pop{T|}", ss
, XX
, XX
, XX
},
556 { "sbbB", Eb
, Gb
, XX
, XX
},
557 { "sbbS", Ev
, Gv
, XX
, XX
},
558 { "sbbB", Gb
, Eb
, XX
, XX
},
559 { "sbbS", Gv
, Ev
, XX
, XX
},
560 { "sbbB", AL
, Ib
, XX
, XX
},
561 { "sbbS", eAX
, Iv
, XX
, XX
},
562 { "push{T|}", ds
, XX
, XX
, XX
},
563 { "pop{T|}", ds
, XX
, XX
, XX
},
565 { "andB", Eb
, Gb
, XX
, XX
},
566 { "andS", Ev
, Gv
, XX
, XX
},
567 { "andB", Gb
, Eb
, XX
, XX
},
568 { "andS", Gv
, Ev
, XX
, XX
},
569 { "andB", AL
, Ib
, XX
, XX
},
570 { "andS", eAX
, Iv
, XX
, XX
},
571 { "(bad)", XX
, XX
, XX
, XX
}, /* SEG ES prefix */
572 { "daa{|}", XX
, XX
, XX
, XX
},
574 { "subB", Eb
, Gb
, XX
, XX
},
575 { "subS", Ev
, Gv
, XX
, XX
},
576 { "subB", Gb
, Eb
, XX
, XX
},
577 { "subS", Gv
, Ev
, XX
, XX
},
578 { "subB", AL
, Ib
, XX
, XX
},
579 { "subS", eAX
, Iv
, XX
, XX
},
580 { "(bad)", XX
, XX
, XX
, XX
}, /* SEG CS prefix */
581 { "das{|}", XX
, XX
, XX
, XX
},
583 { "xorB", Eb
, Gb
, XX
, XX
},
584 { "xorS", Ev
, Gv
, XX
, XX
},
585 { "xorB", Gb
, Eb
, XX
, XX
},
586 { "xorS", Gv
, Ev
, XX
, XX
},
587 { "xorB", AL
, Ib
, XX
, XX
},
588 { "xorS", eAX
, Iv
, XX
, XX
},
589 { "(bad)", XX
, XX
, XX
, XX
}, /* SEG SS prefix */
590 { "aaa{|}", XX
, XX
, XX
, XX
},
592 { "cmpB", Eb
, Gb
, XX
, XX
},
593 { "cmpS", Ev
, Gv
, XX
, XX
},
594 { "cmpB", Gb
, Eb
, XX
, XX
},
595 { "cmpS", Gv
, Ev
, XX
, XX
},
596 { "cmpB", AL
, Ib
, XX
, XX
},
597 { "cmpS", eAX
, Iv
, XX
, XX
},
598 { "(bad)", XX
, XX
, XX
, XX
}, /* SEG DS prefix */
599 { "aas{|}", XX
, XX
, XX
, XX
},
601 { "inc{S|}", RMeAX
, XX
, XX
, XX
},
602 { "inc{S|}", RMeCX
, XX
, XX
, XX
},
603 { "inc{S|}", RMeDX
, XX
, XX
, XX
},
604 { "inc{S|}", RMeBX
, XX
, XX
, XX
},
605 { "inc{S|}", RMeSP
, XX
, XX
, XX
},
606 { "inc{S|}", RMeBP
, XX
, XX
, XX
},
607 { "inc{S|}", RMeSI
, XX
, XX
, XX
},
608 { "inc{S|}", RMeDI
, XX
, XX
, XX
},
610 { "dec{S|}", RMeAX
, XX
, XX
, XX
},
611 { "dec{S|}", RMeCX
, XX
, XX
, XX
},
612 { "dec{S|}", RMeDX
, XX
, XX
, XX
},
613 { "dec{S|}", RMeBX
, XX
, XX
, XX
},
614 { "dec{S|}", RMeSP
, XX
, XX
, XX
},
615 { "dec{S|}", RMeBP
, XX
, XX
, XX
},
616 { "dec{S|}", RMeSI
, XX
, XX
, XX
},
617 { "dec{S|}", RMeDI
, XX
, XX
, XX
},
619 { "pushV", RMrAX
, XX
, XX
, XX
},
620 { "pushV", RMrCX
, XX
, XX
, XX
},
621 { "pushV", RMrDX
, XX
, XX
, XX
},
622 { "pushV", RMrBX
, XX
, XX
, XX
},
623 { "pushV", RMrSP
, XX
, XX
, XX
},
624 { "pushV", RMrBP
, XX
, XX
, XX
},
625 { "pushV", RMrSI
, XX
, XX
, XX
},
626 { "pushV", RMrDI
, XX
, XX
, XX
},
628 { "popV", RMrAX
, XX
, XX
, XX
},
629 { "popV", RMrCX
, XX
, XX
, XX
},
630 { "popV", RMrDX
, XX
, XX
, XX
},
631 { "popV", RMrBX
, XX
, XX
, XX
},
632 { "popV", RMrSP
, XX
, XX
, XX
},
633 { "popV", RMrBP
, XX
, XX
, XX
},
634 { "popV", RMrSI
, XX
, XX
, XX
},
635 { "popV", RMrDI
, XX
, XX
, XX
},
637 { "pusha{P|}", XX
, XX
, XX
, XX
},
638 { "popa{P|}", XX
, XX
, XX
, XX
},
639 { "bound{S|}", Gv
, Ma
, XX
, XX
},
641 { "(bad)", XX
, XX
, XX
, XX
}, /* seg fs */
642 { "(bad)", XX
, XX
, XX
, XX
}, /* seg gs */
643 { "(bad)", XX
, XX
, XX
, XX
}, /* op size prefix */
644 { "(bad)", XX
, XX
, XX
, XX
}, /* adr size prefix */
646 { "pushT", Iq
, XX
, XX
, XX
},
647 { "imulS", Gv
, Ev
, Iv
, XX
},
648 { "pushT", sIb
, XX
, XX
, XX
},
649 { "imulS", Gv
, Ev
, sIb
, XX
},
650 { "ins{b||b|}", Ybr
, indirDX
, XX
, XX
},
651 { "ins{R||R|}", Yvr
, indirDX
, XX
, XX
},
652 { "outs{b||b|}", indirDXr
, Xb
, XX
, XX
},
653 { "outs{R||R|}", indirDXr
, Xv
, XX
, XX
},
655 { "joH", Jb
, XX
, cond_jump_flag
, XX
},
656 { "jnoH", Jb
, XX
, cond_jump_flag
, XX
},
657 { "jbH", Jb
, XX
, cond_jump_flag
, XX
},
658 { "jaeH", Jb
, XX
, cond_jump_flag
, XX
},
659 { "jeH", Jb
, XX
, cond_jump_flag
, XX
},
660 { "jneH", Jb
, XX
, cond_jump_flag
, XX
},
661 { "jbeH", Jb
, XX
, cond_jump_flag
, XX
},
662 { "jaH", Jb
, XX
, cond_jump_flag
, XX
},
664 { "jsH", Jb
, XX
, cond_jump_flag
, XX
},
665 { "jnsH", Jb
, XX
, cond_jump_flag
, XX
},
666 { "jpH", Jb
, XX
, cond_jump_flag
, XX
},
667 { "jnpH", Jb
, XX
, cond_jump_flag
, XX
},
668 { "jlH", Jb
, XX
, cond_jump_flag
, XX
},
669 { "jgeH", Jb
, XX
, cond_jump_flag
, XX
},
670 { "jleH", Jb
, XX
, cond_jump_flag
, XX
},
671 { "jgH", Jb
, XX
, cond_jump_flag
, XX
},
675 { "(bad)", XX
, XX
, XX
, XX
},
677 { "testB", Eb
, Gb
, XX
, XX
},
678 { "testS", Ev
, Gv
, XX
, XX
},
679 { "xchgB", Eb
, Gb
, XX
, XX
},
680 { "xchgS", Ev
, Gv
, XX
, XX
},
682 { "movB", Eb
, Gb
, XX
, XX
},
683 { "movS", Ev
, Gv
, XX
, XX
},
684 { "movB", Gb
, Eb
, XX
, XX
},
685 { "movS", Gv
, Ev
, XX
, XX
},
686 { "movQ", Sv
, Sw
, XX
, XX
},
687 { "leaS", Gv
, M
, XX
, XX
},
688 { "movQ", Sw
, Sv
, XX
, XX
},
689 { "popU", stackEv
, XX
, XX
, XX
},
691 { "xchgS", NOP_Fixup1
, eAX_reg
, NOP_Fixup2
, eAX_reg
, XX
, XX
},
692 { "xchgS", RMeCX
, eAX
, XX
, XX
},
693 { "xchgS", RMeDX
, eAX
, XX
, XX
},
694 { "xchgS", RMeBX
, eAX
, XX
, XX
},
695 { "xchgS", RMeSP
, eAX
, XX
, XX
},
696 { "xchgS", RMeBP
, eAX
, XX
, XX
},
697 { "xchgS", RMeSI
, eAX
, XX
, XX
},
698 { "xchgS", RMeDI
, eAX
, XX
, XX
},
700 { "cW{tR||tR|}", XX
, XX
, XX
, XX
},
701 { "cR{tO||tO|}", XX
, XX
, XX
, XX
},
702 { "Jcall{T|}", Ap
, XX
, XX
, XX
},
703 { "(bad)", XX
, XX
, XX
, XX
}, /* fwait */
704 { "pushfT", XX
, XX
, XX
, XX
},
705 { "popfT", XX
, XX
, XX
, XX
},
706 { "sahf{|}", XX
, XX
, XX
, XX
},
707 { "lahf{|}", XX
, XX
, XX
, XX
},
709 { "movB", AL
, Ob
, XX
, XX
},
710 { "movS", eAX
, Ov
, XX
, XX
},
711 { "movB", Ob
, AL
, XX
, XX
},
712 { "movS", Ov
, eAX
, XX
, XX
},
713 { "movs{b||b|}", Ybr
, Xb
, XX
, XX
},
714 { "movs{R||R|}", Yvr
, Xv
, XX
, XX
},
715 { "cmps{b||b|}", Xb
, Yb
, XX
, XX
},
716 { "cmps{R||R|}", Xv
, Yv
, XX
, XX
},
718 { "testB", AL
, Ib
, XX
, XX
},
719 { "testS", eAX
, Iv
, XX
, XX
},
720 { "stosB", Ybr
, AL
, XX
, XX
},
721 { "stosS", Yvr
, eAX
, XX
, XX
},
722 { "lodsB", ALr
, Xb
, XX
, XX
},
723 { "lodsS", eAXr
, Xv
, XX
, XX
},
724 { "scasB", AL
, Yb
, XX
, XX
},
725 { "scasS", eAX
, Yv
, XX
, XX
},
727 { "movB", RMAL
, Ib
, XX
, XX
},
728 { "movB", RMCL
, Ib
, XX
, XX
},
729 { "movB", RMDL
, Ib
, XX
, XX
},
730 { "movB", RMBL
, Ib
, XX
, XX
},
731 { "movB", RMAH
, Ib
, XX
, XX
},
732 { "movB", RMCH
, Ib
, XX
, XX
},
733 { "movB", RMDH
, Ib
, XX
, XX
},
734 { "movB", RMBH
, Ib
, XX
, XX
},
736 { "movS", RMeAX
, Iv64
, XX
, XX
},
737 { "movS", RMeCX
, Iv64
, XX
, XX
},
738 { "movS", RMeDX
, Iv64
, XX
, XX
},
739 { "movS", RMeBX
, Iv64
, XX
, XX
},
740 { "movS", RMeSP
, Iv64
, XX
, XX
},
741 { "movS", RMeBP
, Iv64
, XX
, XX
},
742 { "movS", RMeSI
, Iv64
, XX
, XX
},
743 { "movS", RMeDI
, Iv64
, XX
, XX
},
747 { "retT", Iw
, XX
, XX
, XX
},
748 { "retT", XX
, XX
, XX
, XX
},
749 { "les{S|}", Gv
, Mp
, XX
, XX
},
750 { "ldsS", Gv
, Mp
, XX
, XX
},
754 { "enterT", Iw
, Ib
, XX
, XX
},
755 { "leaveT", XX
, XX
, XX
, XX
},
756 { "lretP", Iw
, XX
, XX
, XX
},
757 { "lretP", XX
, XX
, XX
, XX
},
758 { "int3", XX
, XX
, XX
, XX
},
759 { "int", Ib
, XX
, XX
, XX
},
760 { "into{|}", XX
, XX
, XX
, XX
},
761 { "iretP", XX
, XX
, XX
, XX
},
767 { "aam{|}", sIb
, XX
, XX
, XX
},
768 { "aad{|}", sIb
, XX
, XX
, XX
},
769 { "(bad)", XX
, XX
, XX
, XX
},
770 { "xlat", DSBX
, XX
, XX
, XX
},
781 { "loopneFH", Jb
, XX
, loop_jcxz_flag
, XX
},
782 { "loopeFH", Jb
, XX
, loop_jcxz_flag
, XX
},
783 { "loopFH", Jb
, XX
, loop_jcxz_flag
, XX
},
784 { "jEcxzH", Jb
, XX
, loop_jcxz_flag
, XX
},
785 { "inB", AL
, Ib
, XX
, XX
},
786 { "inS", eAX
, Ib
, XX
, XX
},
787 { "outB", Ib
, AL
, XX
, XX
},
788 { "outS", Ib
, eAX
, XX
, XX
},
790 { "callT", Jv
, XX
, XX
, XX
},
791 { "jmpT", Jv
, XX
, XX
, XX
},
792 { "Jjmp{T|}", Ap
, XX
, XX
, XX
},
793 { "jmp", Jb
, XX
, XX
, XX
},
794 { "inB", AL
, indirDX
, XX
, XX
},
795 { "inS", eAX
, indirDX
, XX
, XX
},
796 { "outB", indirDX
, AL
, XX
, XX
},
797 { "outS", indirDX
, eAX
, XX
, XX
},
799 { "(bad)", XX
, XX
, XX
, XX
}, /* lock prefix */
800 { "icebp", XX
, XX
, XX
, XX
},
801 { "(bad)", XX
, XX
, XX
, XX
}, /* repne */
802 { "(bad)", XX
, XX
, XX
, XX
}, /* repz */
803 { "hlt", XX
, XX
, XX
, XX
},
804 { "cmc", XX
, XX
, XX
, XX
},
808 { "clc", XX
, XX
, XX
, XX
},
809 { "stc", XX
, XX
, XX
, XX
},
810 { "cli", XX
, XX
, XX
, XX
},
811 { "sti", XX
, XX
, XX
, XX
},
812 { "cld", XX
, XX
, XX
, XX
},
813 { "std", XX
, XX
, XX
, XX
},
818 static const struct dis386 dis386_twobyte
[] = {
822 { "larS", Gv
, Ew
, XX
, XX
},
823 { "lslS", Gv
, Ew
, XX
, XX
},
824 { "(bad)", XX
, XX
, XX
, XX
},
825 { "syscall", XX
, XX
, XX
, XX
},
826 { "clts", XX
, XX
, XX
, XX
},
827 { "sysretP", XX
, XX
, XX
, XX
},
829 { "invd", XX
, XX
, XX
, XX
},
830 { "wbinvd", XX
, XX
, XX
, XX
},
831 { "(bad)", XX
, XX
, XX
, XX
},
832 { "ud2a", XX
, XX
, XX
, XX
},
833 { "(bad)", XX
, XX
, XX
, XX
},
835 { "femms", XX
, XX
, XX
, XX
},
836 { "", MX
, EM
, OPSUF
, XX
}, /* See OP_3DNowSuffix. */
841 { "movlpX", EX
, XM
, SIMD_Fixup
, 'h', XX
},
842 { "unpcklpX", XM
, EX
, XX
, XX
},
843 { "unpckhpX", XM
, EX
, XX
, XX
},
845 { "movhpX", EX
, XM
, SIMD_Fixup
, 'l', XX
},
848 { "(bad)", XX
, XX
, XX
, XX
},
849 { "(bad)", XX
, XX
, XX
, XX
},
850 { "(bad)", XX
, XX
, XX
, XX
},
851 { "(bad)", XX
, XX
, XX
, XX
},
852 { "(bad)", XX
, XX
, XX
, XX
},
853 { "(bad)", XX
, XX
, XX
, XX
},
854 { "nopQ", Ev
, XX
, XX
, XX
},
856 { "movZ", Rm
, Cm
, XX
, XX
},
857 { "movZ", Rm
, Dm
, XX
, XX
},
858 { "movZ", Cm
, Rm
, XX
, XX
},
859 { "movZ", Dm
, Rm
, XX
, XX
},
860 { "movL", Rd
, Td
, XX
, XX
},
861 { "(bad)", XX
, XX
, XX
, XX
},
862 { "movL", Td
, Rd
, XX
, XX
},
863 { "(bad)", XX
, XX
, XX
, XX
},
865 { "movapX", XM
, EX
, XX
, XX
},
866 { "movapX", EX
, XM
, XX
, XX
},
871 { "ucomisX", XM
,EX
, XX
, XX
},
872 { "comisX", XM
,EX
, XX
, XX
},
874 { "wrmsr", XX
, XX
, XX
, XX
},
875 { "rdtsc", XX
, XX
, XX
, XX
},
876 { "rdmsr", XX
, XX
, XX
, XX
},
877 { "rdpmc", XX
, XX
, XX
, XX
},
878 { "sysenter", XX
, XX
, XX
, XX
},
879 { "sysexit", XX
, XX
, XX
, XX
},
880 { "(bad)", XX
, XX
, XX
, XX
},
881 { "(bad)", XX
, XX
, XX
, XX
},
884 { "(bad)", XX
, XX
, XX
, XX
},
886 { "(bad)", XX
, XX
, XX
, XX
},
887 { "(bad)", XX
, XX
, XX
, XX
},
888 { "(bad)", XX
, XX
, XX
, XX
},
889 { "(bad)", XX
, XX
, XX
, XX
},
890 { "(bad)", XX
, XX
, XX
, XX
},
892 { "cmovo", Gv
, Ev
, XX
, XX
},
893 { "cmovno", Gv
, Ev
, XX
, XX
},
894 { "cmovb", Gv
, Ev
, XX
, XX
},
895 { "cmovae", Gv
, Ev
, XX
, XX
},
896 { "cmove", Gv
, Ev
, XX
, XX
},
897 { "cmovne", Gv
, Ev
, XX
, XX
},
898 { "cmovbe", Gv
, Ev
, XX
, XX
},
899 { "cmova", Gv
, Ev
, XX
, XX
},
901 { "cmovs", Gv
, Ev
, XX
, XX
},
902 { "cmovns", Gv
, Ev
, XX
, XX
},
903 { "cmovp", Gv
, Ev
, XX
, XX
},
904 { "cmovnp", Gv
, Ev
, XX
, XX
},
905 { "cmovl", Gv
, Ev
, XX
, XX
},
906 { "cmovge", Gv
, Ev
, XX
, XX
},
907 { "cmovle", Gv
, Ev
, XX
, XX
},
908 { "cmovg", Gv
, Ev
, XX
, XX
},
910 { "movmskpX", Gdq
, XS
, XX
, XX
},
914 { "andpX", XM
, EX
, XX
, XX
},
915 { "andnpX", XM
, EX
, XX
, XX
},
916 { "orpX", XM
, EX
, XX
, XX
},
917 { "xorpX", XM
, EX
, XX
, XX
},
928 { "punpcklbw", MX
, EM
, XX
, XX
},
929 { "punpcklwd", MX
, EM
, XX
, XX
},
930 { "punpckldq", MX
, EM
, XX
, XX
},
931 { "packsswb", MX
, EM
, XX
, XX
},
932 { "pcmpgtb", MX
, EM
, XX
, XX
},
933 { "pcmpgtw", MX
, EM
, XX
, XX
},
934 { "pcmpgtd", MX
, EM
, XX
, XX
},
935 { "packuswb", MX
, EM
, XX
, XX
},
937 { "punpckhbw", MX
, EM
, XX
, XX
},
938 { "punpckhwd", MX
, EM
, XX
, XX
},
939 { "punpckhdq", MX
, EM
, XX
, XX
},
940 { "packssdw", MX
, EM
, XX
, XX
},
943 { "movd", MX
, Edq
, XX
, XX
},
950 { "pcmpeqb", MX
, EM
, XX
, XX
},
951 { "pcmpeqw", MX
, EM
, XX
, XX
},
952 { "pcmpeqd", MX
, EM
, XX
, XX
},
953 { "emms", XX
, XX
, XX
, XX
},
957 { "(bad)", XX
, XX
, XX
, XX
},
958 { "(bad)", XX
, XX
, XX
, XX
},
964 { "joH", Jv
, XX
, cond_jump_flag
, XX
},
965 { "jnoH", Jv
, XX
, cond_jump_flag
, XX
},
966 { "jbH", Jv
, XX
, cond_jump_flag
, XX
},
967 { "jaeH", Jv
, XX
, cond_jump_flag
, XX
},
968 { "jeH", Jv
, XX
, cond_jump_flag
, XX
},
969 { "jneH", Jv
, XX
, cond_jump_flag
, XX
},
970 { "jbeH", Jv
, XX
, cond_jump_flag
, XX
},
971 { "jaH", Jv
, XX
, cond_jump_flag
, XX
},
973 { "jsH", Jv
, XX
, cond_jump_flag
, XX
},
974 { "jnsH", Jv
, XX
, cond_jump_flag
, XX
},
975 { "jpH", Jv
, XX
, cond_jump_flag
, XX
},
976 { "jnpH", Jv
, XX
, cond_jump_flag
, XX
},
977 { "jlH", Jv
, XX
, cond_jump_flag
, XX
},
978 { "jgeH", Jv
, XX
, cond_jump_flag
, XX
},
979 { "jleH", Jv
, XX
, cond_jump_flag
, XX
},
980 { "jgH", Jv
, XX
, cond_jump_flag
, XX
},
982 { "seto", Eb
, XX
, XX
, XX
},
983 { "setno", Eb
, XX
, XX
, XX
},
984 { "setb", Eb
, XX
, XX
, XX
},
985 { "setae", Eb
, XX
, XX
, XX
},
986 { "sete", Eb
, XX
, XX
, XX
},
987 { "setne", Eb
, XX
, XX
, XX
},
988 { "setbe", Eb
, XX
, XX
, XX
},
989 { "seta", Eb
, XX
, XX
, XX
},
991 { "sets", Eb
, XX
, XX
, XX
},
992 { "setns", Eb
, XX
, XX
, XX
},
993 { "setp", Eb
, XX
, XX
, XX
},
994 { "setnp", Eb
, XX
, XX
, XX
},
995 { "setl", Eb
, XX
, XX
, XX
},
996 { "setge", Eb
, XX
, XX
, XX
},
997 { "setle", Eb
, XX
, XX
, XX
},
998 { "setg", Eb
, XX
, XX
, XX
},
1000 { "pushT", fs
, XX
, XX
, XX
},
1001 { "popT", fs
, XX
, XX
, XX
},
1002 { "cpuid", XX
, XX
, XX
, XX
},
1003 { "btS", Ev
, Gv
, XX
, XX
},
1004 { "shldS", Ev
, Gv
, Ib
, XX
},
1005 { "shldS", Ev
, Gv
, CL
, XX
},
1009 { "pushT", gs
, XX
, XX
, XX
},
1010 { "popT", gs
, XX
, XX
, XX
},
1011 { "rsm", XX
, XX
, XX
, XX
},
1012 { "btsS", Ev
, Gv
, XX
, XX
},
1013 { "shrdS", Ev
, Gv
, Ib
, XX
},
1014 { "shrdS", Ev
, Gv
, CL
, XX
},
1016 { "imulS", Gv
, Ev
, XX
, XX
},
1018 { "cmpxchgB", Eb
, Gb
, XX
, XX
},
1019 { "cmpxchgS", Ev
, Gv
, XX
, XX
},
1020 { "lssS", Gv
, Mp
, XX
, XX
},
1021 { "btrS", Ev
, Gv
, XX
, XX
},
1022 { "lfsS", Gv
, Mp
, XX
, XX
},
1023 { "lgsS", Gv
, Mp
, XX
, XX
},
1024 { "movz{bR|x|bR|x}", Gv
, Eb
, XX
, XX
},
1025 { "movz{wR|x|wR|x}", Gv
, Ew
, XX
, XX
}, /* yes, there really is movzww ! */
1027 { "popcntS", Gv
, Ev
, XX
, XX
},
1028 { "ud2b", XX
, XX
, XX
, XX
},
1030 { "btcS", Ev
, Gv
, XX
, XX
},
1031 { "bsfS", Gv
, Ev
, XX
, XX
},
1033 { "movs{bR|x|bR|x}", Gv
, Eb
, XX
, XX
},
1034 { "movs{wR|x|wR|x}", Gv
, Ew
, XX
, XX
}, /* yes, there really is movsww ! */
1036 { "xaddB", Eb
, Gb
, XX
, XX
},
1037 { "xaddS", Ev
, Gv
, XX
, XX
},
1039 { "movntiS", Ev
, Gv
, XX
, XX
},
1040 { "pinsrw", MX
, Edqw
, Ib
, XX
},
1041 { "pextrw", Gdq
, MS
, Ib
, XX
},
1042 { "shufpX", XM
, EX
, Ib
, XX
},
1045 { "bswap", RMeAX
, XX
, XX
, XX
},
1046 { "bswap", RMeCX
, XX
, XX
, XX
},
1047 { "bswap", RMeDX
, XX
, XX
, XX
},
1048 { "bswap", RMeBX
, XX
, XX
, XX
},
1049 { "bswap", RMeSP
, XX
, XX
, XX
},
1050 { "bswap", RMeBP
, XX
, XX
, XX
},
1051 { "bswap", RMeSI
, XX
, XX
, XX
},
1052 { "bswap", RMeDI
, XX
, XX
, XX
},
1055 { "psrlw", MX
, EM
, XX
, XX
},
1056 { "psrld", MX
, EM
, XX
, XX
},
1057 { "psrlq", MX
, EM
, XX
, XX
},
1058 { "paddq", MX
, EM
, XX
, XX
},
1059 { "pmullw", MX
, EM
, XX
, XX
},
1061 { "pmovmskb", Gdq
, MS
, XX
, XX
},
1063 { "psubusb", MX
, EM
, XX
, XX
},
1064 { "psubusw", MX
, EM
, XX
, XX
},
1065 { "pminub", MX
, EM
, XX
, XX
},
1066 { "pand", MX
, EM
, XX
, XX
},
1067 { "paddusb", MX
, EM
, XX
, XX
},
1068 { "paddusw", MX
, EM
, XX
, XX
},
1069 { "pmaxub", MX
, EM
, XX
, XX
},
1070 { "pandn", MX
, EM
, XX
, XX
},
1072 { "pavgb", MX
, EM
, XX
, XX
},
1073 { "psraw", MX
, EM
, XX
, XX
},
1074 { "psrad", MX
, EM
, XX
, XX
},
1075 { "pavgw", MX
, EM
, XX
, XX
},
1076 { "pmulhuw", MX
, EM
, XX
, XX
},
1077 { "pmulhw", MX
, EM
, XX
, XX
},
1081 { "psubsb", MX
, EM
, XX
, XX
},
1082 { "psubsw", MX
, EM
, XX
, XX
},
1083 { "pminsw", MX
, EM
, XX
, XX
},
1084 { "por", MX
, EM
, XX
, XX
},
1085 { "paddsb", MX
, EM
, XX
, XX
},
1086 { "paddsw", MX
, EM
, XX
, XX
},
1087 { "pmaxsw", MX
, EM
, XX
, XX
},
1088 { "pxor", MX
, EM
, XX
, XX
},
1091 { "psllw", MX
, EM
, XX
, XX
},
1092 { "pslld", MX
, EM
, XX
, XX
},
1093 { "psllq", MX
, EM
, XX
, XX
},
1094 { "pmuludq", MX
, EM
, XX
, XX
},
1095 { "pmaddwd", MX
, EM
, XX
, XX
},
1096 { "psadbw", MX
, EM
, XX
, XX
},
1099 { "psubb", MX
, EM
, XX
, XX
},
1100 { "psubw", MX
, EM
, XX
, XX
},
1101 { "psubd", MX
, EM
, XX
, XX
},
1102 { "psubq", MX
, EM
, XX
, XX
},
1103 { "paddb", MX
, EM
, XX
, XX
},
1104 { "paddw", MX
, EM
, XX
, XX
},
1105 { "paddd", MX
, EM
, XX
, XX
},
1106 { "(bad)", XX
, XX
, XX
, XX
}
1109 static const unsigned char onebyte_has_modrm
[256] = {
1110 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1111 /* ------------------------------- */
1112 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1113 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1114 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1115 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1116 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1117 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1118 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1119 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1120 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1121 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1122 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1123 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1124 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1125 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1126 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1127 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1128 /* ------------------------------- */
1129 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1132 static const unsigned char twobyte_has_modrm
[256] = {
1133 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1134 /* ------------------------------- */
1135 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1136 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
1137 /* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */
1138 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1139 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1140 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1141 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1142 /* 70 */ 1,1,1,1,1,1,1,0,1,1,0,0,1,1,1,1, /* 7f */
1143 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1144 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1145 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1146 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1147 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1148 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1149 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1150 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1151 /* ------------------------------- */
1152 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1155 static const unsigned char twobyte_uses_SSE_prefix
[256] = {
1156 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1157 /* ------------------------------- */
1158 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
1159 /* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */
1160 /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0, /* 2f */
1161 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1162 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
1163 /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */
1164 /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */
1165 /* 70 */ 1,0,0,0,0,0,0,0,1,1,0,0,1,1,1,1, /* 7f */
1166 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1167 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
1168 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
1169 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
1170 /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
1171 /* d0 */ 1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */
1172 /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */
1173 /* f0 */ 1,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0 /* ff */
1174 /* ------------------------------- */
1175 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1178 static char obuf
[100];
1180 static char scratchbuf
[100];
1181 static unsigned char *start_codep
;
1182 static unsigned char *insn_codep
;
1183 static unsigned char *codep
;
1184 static disassemble_info
*the_info
;
1188 static unsigned char need_modrm
;
1190 /* If we are accessing mod/rm/reg without need_modrm set, then the
1191 values are stale. Hitting this abort likely indicates that you
1192 need to update onebyte_has_modrm or twobyte_has_modrm. */
1193 #define MODRM_CHECK if (!need_modrm) abort ()
1195 static const char **names64
;
1196 static const char **names32
;
1197 static const char **names16
;
1198 static const char **names8
;
1199 static const char **names8rex
;
1200 static const char **names_seg
;
1201 static const char **index16
;
1203 static const char *intel_names64
[] = {
1204 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1205 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1207 static const char *intel_names32
[] = {
1208 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1209 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1211 static const char *intel_names16
[] = {
1212 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1213 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1215 static const char *intel_names8
[] = {
1216 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1218 static const char *intel_names8rex
[] = {
1219 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1220 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1222 static const char *intel_names_seg
[] = {
1223 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1225 static const char *intel_index16
[] = {
1226 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1229 static const char *att_names64
[] = {
1230 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
1231 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1233 static const char *att_names32
[] = {
1234 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
1235 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
1237 static const char *att_names16
[] = {
1238 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
1239 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
1241 static const char *att_names8
[] = {
1242 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
1244 static const char *att_names8rex
[] = {
1245 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
1246 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1248 static const char *att_names_seg
[] = {
1249 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
1251 static const char *att_index16
[] = {
1252 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
1255 static const struct dis386 grps
[][8] = {
1258 { "addA", Eb
, Ib
, XX
, XX
},
1259 { "orA", Eb
, Ib
, XX
, XX
},
1260 { "adcA", Eb
, Ib
, XX
, XX
},
1261 { "sbbA", Eb
, Ib
, XX
, XX
},
1262 { "andA", Eb
, Ib
, XX
, XX
},
1263 { "subA", Eb
, Ib
, XX
, XX
},
1264 { "xorA", Eb
, Ib
, XX
, XX
},
1265 { "cmpA", Eb
, Ib
, XX
, XX
}
1269 { "addQ", Ev
, Iv
, XX
, XX
},
1270 { "orQ", Ev
, Iv
, XX
, XX
},
1271 { "adcQ", Ev
, Iv
, XX
, XX
},
1272 { "sbbQ", Ev
, Iv
, XX
, XX
},
1273 { "andQ", Ev
, Iv
, XX
, XX
},
1274 { "subQ", Ev
, Iv
, XX
, XX
},
1275 { "xorQ", Ev
, Iv
, XX
, XX
},
1276 { "cmpQ", Ev
, Iv
, XX
, XX
}
1280 { "addQ", Ev
, sIb
, XX
, XX
},
1281 { "orQ", Ev
, sIb
, XX
, XX
},
1282 { "adcQ", Ev
, sIb
, XX
, XX
},
1283 { "sbbQ", Ev
, sIb
, XX
, XX
},
1284 { "andQ", Ev
, sIb
, XX
, XX
},
1285 { "subQ", Ev
, sIb
, XX
, XX
},
1286 { "xorQ", Ev
, sIb
, XX
, XX
},
1287 { "cmpQ", Ev
, sIb
, XX
, XX
}
1291 { "rolA", Eb
, Ib
, XX
, XX
},
1292 { "rorA", Eb
, Ib
, XX
, XX
},
1293 { "rclA", Eb
, Ib
, XX
, XX
},
1294 { "rcrA", Eb
, Ib
, XX
, XX
},
1295 { "shlA", Eb
, Ib
, XX
, XX
},
1296 { "shrA", Eb
, Ib
, XX
, XX
},
1297 { "(bad)", XX
, XX
, XX
, XX
},
1298 { "sarA", Eb
, Ib
, XX
, XX
},
1302 { "rolQ", Ev
, Ib
, XX
, XX
},
1303 { "rorQ", Ev
, Ib
, XX
, XX
},
1304 { "rclQ", Ev
, Ib
, XX
, XX
},
1305 { "rcrQ", Ev
, Ib
, XX
, XX
},
1306 { "shlQ", Ev
, Ib
, XX
, XX
},
1307 { "shrQ", Ev
, Ib
, XX
, XX
},
1308 { "(bad)", XX
, XX
, XX
, XX
},
1309 { "sarQ", Ev
, Ib
, XX
, XX
},
1313 { "rolA", Eb
, I1
, XX
, XX
},
1314 { "rorA", Eb
, I1
, XX
, XX
},
1315 { "rclA", Eb
, I1
, XX
, XX
},
1316 { "rcrA", Eb
, I1
, XX
, XX
},
1317 { "shlA", Eb
, I1
, XX
, XX
},
1318 { "shrA", Eb
, I1
, XX
, XX
},
1319 { "(bad)", XX
, XX
, XX
, XX
},
1320 { "sarA", Eb
, I1
, XX
, XX
},
1324 { "rolQ", Ev
, I1
, XX
, XX
},
1325 { "rorQ", Ev
, I1
, XX
, XX
},
1326 { "rclQ", Ev
, I1
, XX
, XX
},
1327 { "rcrQ", Ev
, I1
, XX
, XX
},
1328 { "shlQ", Ev
, I1
, XX
, XX
},
1329 { "shrQ", Ev
, I1
, XX
, XX
},
1330 { "(bad)", XX
, XX
, XX
, XX
},
1331 { "sarQ", Ev
, I1
, XX
, XX
},
1335 { "rolA", Eb
, CL
, XX
, XX
},
1336 { "rorA", Eb
, CL
, XX
, XX
},
1337 { "rclA", Eb
, CL
, XX
, XX
},
1338 { "rcrA", Eb
, CL
, XX
, XX
},
1339 { "shlA", Eb
, CL
, XX
, XX
},
1340 { "shrA", Eb
, CL
, XX
, XX
},
1341 { "(bad)", XX
, XX
, XX
, XX
},
1342 { "sarA", Eb
, CL
, XX
, XX
},
1346 { "rolQ", Ev
, CL
, XX
, XX
},
1347 { "rorQ", Ev
, CL
, XX
, XX
},
1348 { "rclQ", Ev
, CL
, XX
, XX
},
1349 { "rcrQ", Ev
, CL
, XX
, XX
},
1350 { "shlQ", Ev
, CL
, XX
, XX
},
1351 { "shrQ", Ev
, CL
, XX
, XX
},
1352 { "(bad)", XX
, XX
, XX
, XX
},
1353 { "sarQ", Ev
, CL
, XX
, XX
}
1357 { "testA", Eb
, Ib
, XX
, XX
},
1358 { "(bad)", Eb
, XX
, XX
, XX
},
1359 { "notA", Eb
, XX
, XX
, XX
},
1360 { "negA", Eb
, XX
, XX
, XX
},
1361 { "mulA", Eb
, XX
, XX
, XX
}, /* Don't print the implicit %al register, */
1362 { "imulA", Eb
, XX
, XX
, XX
}, /* to distinguish these opcodes from other */
1363 { "divA", Eb
, XX
, XX
, XX
}, /* mul/imul opcodes. Do the same for div */
1364 { "idivA", Eb
, XX
, XX
, XX
} /* and idiv for consistency. */
1368 { "testQ", Ev
, Iv
, XX
, XX
},
1369 { "(bad)", XX
, XX
, XX
, XX
},
1370 { "notQ", Ev
, XX
, XX
, XX
},
1371 { "negQ", Ev
, XX
, XX
, XX
},
1372 { "mulQ", Ev
, XX
, XX
, XX
}, /* Don't print the implicit register. */
1373 { "imulQ", Ev
, XX
, XX
, XX
},
1374 { "divQ", Ev
, XX
, XX
, XX
},
1375 { "idivQ", Ev
, XX
, XX
, XX
},
1379 { "incA", Eb
, XX
, XX
, XX
},
1380 { "decA", Eb
, XX
, XX
, XX
},
1381 { "(bad)", XX
, XX
, XX
, XX
},
1382 { "(bad)", XX
, XX
, XX
, XX
},
1383 { "(bad)", XX
, XX
, XX
, XX
},
1384 { "(bad)", XX
, XX
, XX
, XX
},
1385 { "(bad)", XX
, XX
, XX
, XX
},
1386 { "(bad)", XX
, XX
, XX
, XX
},
1390 { "incQ", Ev
, XX
, XX
, XX
},
1391 { "decQ", Ev
, XX
, XX
, XX
},
1392 { "callT", indirEv
, XX
, XX
, XX
},
1393 { "JcallT", indirEp
, XX
, XX
, XX
},
1394 { "jmpT", indirEv
, XX
, XX
, XX
},
1395 { "JjmpT", indirEp
, XX
, XX
, XX
},
1396 { "pushU", stackEv
, XX
, XX
, XX
},
1397 { "(bad)", XX
, XX
, XX
, XX
},
1401 { "sldtQ", Ev
, XX
, XX
, XX
},
1402 { "strQ", Ev
, XX
, XX
, XX
},
1403 { "lldt", Ew
, XX
, XX
, XX
},
1404 { "ltr", Ew
, XX
, XX
, XX
},
1405 { "verr", Ew
, XX
, XX
, XX
},
1406 { "verw", Ew
, XX
, XX
, XX
},
1407 { "(bad)", XX
, XX
, XX
, XX
},
1408 { "(bad)", XX
, XX
, XX
, XX
}
1412 { "sgdt{Q|IQ||}", VMX_Fixup
, 0, XX
, XX
, XX
},
1413 { "sidt{Q|IQ||}", PNI_Fixup
, 0, XX
, XX
, XX
},
1414 { "lgdt{Q|Q||}", M
, XX
, XX
, XX
},
1415 { "lidt{Q|Q||}", SVME_Fixup
, 0, XX
, XX
, XX
},
1416 { "smswQ", Ev
, XX
, XX
, XX
},
1417 { "(bad)", XX
, XX
, XX
, XX
},
1418 { "lmsw", Ew
, XX
, XX
, XX
},
1419 { "invlpg", INVLPG_Fixup
, w_mode
, XX
, XX
, XX
},
1423 { "(bad)", XX
, XX
, XX
, XX
},
1424 { "(bad)", XX
, XX
, XX
, XX
},
1425 { "(bad)", XX
, XX
, XX
, XX
},
1426 { "(bad)", XX
, XX
, XX
, XX
},
1427 { "btQ", Ev
, Ib
, XX
, XX
},
1428 { "btsQ", Ev
, Ib
, XX
, XX
},
1429 { "btrQ", Ev
, Ib
, XX
, XX
},
1430 { "btcQ", Ev
, Ib
, XX
, XX
},
1434 { "(bad)", XX
, XX
, XX
, XX
},
1435 { "cmpxchg8b", Eq
, XX
, XX
, XX
},
1436 { "(bad)", XX
, XX
, XX
, XX
},
1437 { "(bad)", XX
, XX
, XX
, XX
},
1438 { "(bad)", XX
, XX
, XX
, XX
},
1439 { "(bad)", XX
, XX
, XX
, XX
},
1440 { "", VM
, XX
, XX
, XX
}, /* See OP_VMX. */
1441 { "vmptrst", Eq
, XX
, XX
, XX
},
1445 { "movA", Eb
, Ib
, XX
, XX
},
1446 { "(bad)", XX
, XX
, XX
, XX
},
1447 { "(bad)", XX
, XX
, XX
, XX
},
1448 { "(bad)", XX
, XX
, XX
, XX
},
1449 { "(bad)", XX
, XX
, XX
, XX
},
1450 { "(bad)", XX
, XX
, XX
, XX
},
1451 { "(bad)", XX
, XX
, XX
, XX
},
1452 { "(bad)", XX
, XX
, XX
, XX
},
1456 { "movQ", Ev
, Iv
, XX
, XX
},
1457 { "(bad)", XX
, XX
, XX
, XX
},
1458 { "(bad)", XX
, XX
, XX
, XX
},
1459 { "(bad)", XX
, XX
, XX
, XX
},
1460 { "(bad)", XX
, XX
, XX
, XX
},
1461 { "(bad)", XX
, XX
, XX
, XX
},
1462 { "(bad)", XX
, XX
, XX
, XX
},
1463 { "(bad)", XX
, XX
, XX
, XX
},
1467 { "(bad)", XX
, XX
, XX
, XX
},
1468 { "(bad)", XX
, XX
, XX
, XX
},
1469 { "psrlw", MS
, Ib
, XX
, XX
},
1470 { "(bad)", XX
, XX
, XX
, XX
},
1471 { "psraw", MS
, Ib
, XX
, XX
},
1472 { "(bad)", XX
, XX
, XX
, XX
},
1473 { "psllw", MS
, Ib
, XX
, XX
},
1474 { "(bad)", XX
, XX
, XX
, XX
},
1478 { "(bad)", XX
, XX
, XX
, XX
},
1479 { "(bad)", XX
, XX
, XX
, XX
},
1480 { "psrld", MS
, Ib
, XX
, XX
},
1481 { "(bad)", XX
, XX
, XX
, XX
},
1482 { "psrad", MS
, Ib
, XX
, XX
},
1483 { "(bad)", XX
, XX
, XX
, XX
},
1484 { "pslld", MS
, Ib
, XX
, XX
},
1485 { "(bad)", XX
, XX
, XX
, XX
},
1489 { "(bad)", XX
, XX
, XX
, XX
},
1490 { "(bad)", XX
, XX
, XX
, XX
},
1491 { "psrlq", MS
, Ib
, XX
, XX
},
1492 { "psrldq", MS
, Ib
, XX
, XX
},
1493 { "(bad)", XX
, XX
, XX
, XX
},
1494 { "(bad)", XX
, XX
, XX
, XX
},
1495 { "psllq", MS
, Ib
, XX
, XX
},
1496 { "pslldq", MS
, Ib
, XX
, XX
},
1500 { "fxsave", Ev
, XX
, XX
, XX
},
1501 { "fxrstor", Ev
, XX
, XX
, XX
},
1502 { "ldmxcsr", Ev
, XX
, XX
, XX
},
1503 { "stmxcsr", Ev
, XX
, XX
, XX
},
1504 { "(bad)", XX
, XX
, XX
, XX
},
1505 { "lfence", OP_0fae
, 0, XX
, XX
, XX
},
1506 { "mfence", OP_0fae
, 0, XX
, XX
, XX
},
1507 { "clflush", OP_0fae
, 0, XX
, XX
, XX
},
1511 { "prefetchnta", Ev
, XX
, XX
, XX
},
1512 { "prefetcht0", Ev
, XX
, XX
, XX
},
1513 { "prefetcht1", Ev
, XX
, XX
, XX
},
1514 { "prefetcht2", Ev
, XX
, XX
, XX
},
1515 { "(bad)", XX
, XX
, XX
, XX
},
1516 { "(bad)", XX
, XX
, XX
, XX
},
1517 { "(bad)", XX
, XX
, XX
, XX
},
1518 { "(bad)", XX
, XX
, XX
, XX
},
1522 { "prefetch", Eb
, XX
, XX
, XX
},
1523 { "prefetchw", Eb
, XX
, XX
, XX
},
1524 { "(bad)", XX
, XX
, XX
, XX
},
1525 { "(bad)", XX
, XX
, XX
, XX
},
1526 { "(bad)", XX
, XX
, XX
, XX
},
1527 { "(bad)", XX
, XX
, XX
, XX
},
1528 { "(bad)", XX
, XX
, XX
, XX
},
1529 { "(bad)", XX
, XX
, XX
, XX
},
1533 { "xstore-rng", OP_0f07
, 0, XX
, XX
, XX
},
1534 { "xcrypt-ecb", OP_0f07
, 0, XX
, XX
, XX
},
1535 { "xcrypt-cbc", OP_0f07
, 0, XX
, XX
, XX
},
1536 { "xcrypt-ctr", OP_0f07
, 0, XX
, XX
, XX
},
1537 { "xcrypt-cfb", OP_0f07
, 0, XX
, XX
, XX
},
1538 { "xcrypt-ofb", OP_0f07
, 0, XX
, XX
, XX
},
1539 { "(bad)", OP_0f07
, 0, XX
, XX
, XX
},
1540 { "(bad)", OP_0f07
, 0, XX
, XX
, XX
},
1544 { "montmul", OP_0f07
, 0, XX
, XX
, XX
},
1545 { "xsha1", OP_0f07
, 0, XX
, XX
, XX
},
1546 { "xsha256", OP_0f07
, 0, XX
, XX
, XX
},
1547 { "(bad)", OP_0f07
, 0, XX
, XX
, XX
},
1548 { "(bad)", OP_0f07
, 0, XX
, XX
, XX
},
1549 { "(bad)", OP_0f07
, 0, XX
, XX
, XX
},
1550 { "(bad)", OP_0f07
, 0, XX
, XX
, XX
},
1551 { "(bad)", OP_0f07
, 0, XX
, XX
, XX
},
1555 static const struct dis386 prefix_user_table
[][4] = {
1558 { "addps", XM
, EX
, XX
, XX
},
1559 { "addss", XM
, EX
, XX
, XX
},
1560 { "addpd", XM
, EX
, XX
, XX
},
1561 { "addsd", XM
, EX
, XX
, XX
},
1565 { "", XM
, EX
, OPSIMD
, XX
}, /* See OP_SIMD_SUFFIX. */
1566 { "", XM
, EX
, OPSIMD
, XX
},
1567 { "", XM
, EX
, OPSIMD
, XX
},
1568 { "", XM
, EX
, OPSIMD
, XX
},
1572 { "cvtpi2ps", XM
, EM
, XX
, XX
},
1573 { "cvtsi2ssY", XM
, Ev
, XX
, XX
},
1574 { "cvtpi2pd", XM
, EM
, XX
, XX
},
1575 { "cvtsi2sdY", XM
, Ev
, XX
, XX
},
1579 { "cvtps2pi", MX
, EX
, XX
, XX
},
1580 { "cvtss2siY", Gv
, EX
, XX
, XX
},
1581 { "cvtpd2pi", MX
, EX
, XX
, XX
},
1582 { "cvtsd2siY", Gv
, EX
, XX
, XX
},
1586 { "cvttps2pi", MX
, EX
, XX
, XX
},
1587 { "cvttss2siY", Gv
, EX
, XX
, XX
},
1588 { "cvttpd2pi", MX
, EX
, XX
, XX
},
1589 { "cvttsd2siY", Gv
, EX
, XX
, XX
},
1593 { "divps", XM
, EX
, XX
, XX
},
1594 { "divss", XM
, EX
, XX
, XX
},
1595 { "divpd", XM
, EX
, XX
, XX
},
1596 { "divsd", XM
, EX
, XX
, XX
},
1600 { "maxps", XM
, EX
, XX
, XX
},
1601 { "maxss", XM
, EX
, XX
, XX
},
1602 { "maxpd", XM
, EX
, XX
, XX
},
1603 { "maxsd", XM
, EX
, XX
, XX
},
1607 { "minps", XM
, EX
, XX
, XX
},
1608 { "minss", XM
, EX
, XX
, XX
},
1609 { "minpd", XM
, EX
, XX
, XX
},
1610 { "minsd", XM
, EX
, XX
, XX
},
1614 { "movups", XM
, EX
, XX
, XX
},
1615 { "movss", XM
, EX
, XX
, XX
},
1616 { "movupd", XM
, EX
, XX
, XX
},
1617 { "movsd", XM
, EX
, XX
, XX
},
1621 { "movups", EX
, XM
, XX
, XX
},
1622 { "movss", EX
, XM
, XX
, XX
},
1623 { "movupd", EX
, XM
, XX
, XX
},
1624 { "movsd", EX
, XM
, XX
, XX
},
1628 { "mulps", XM
, EX
, XX
, XX
},
1629 { "mulss", XM
, EX
, XX
, XX
},
1630 { "mulpd", XM
, EX
, XX
, XX
},
1631 { "mulsd", XM
, EX
, XX
, XX
},
1635 { "rcpps", XM
, EX
, XX
, XX
},
1636 { "rcpss", XM
, EX
, XX
, XX
},
1637 { "(bad)", XM
, EX
, XX
, XX
},
1638 { "(bad)", XM
, EX
, XX
, XX
},
1642 { "rsqrtps", XM
, EX
, XX
, XX
},
1643 { "rsqrtss", XM
, EX
, XX
, XX
},
1644 { "(bad)", XM
, EX
, XX
, XX
},
1645 { "(bad)", XM
, EX
, XX
, XX
},
1649 { "sqrtps", XM
, EX
, XX
, XX
},
1650 { "sqrtss", XM
, EX
, XX
, XX
},
1651 { "sqrtpd", XM
, EX
, XX
, XX
},
1652 { "sqrtsd", XM
, EX
, XX
, XX
},
1656 { "subps", XM
, EX
, XX
, XX
},
1657 { "subss", XM
, EX
, XX
, XX
},
1658 { "subpd", XM
, EX
, XX
, XX
},
1659 { "subsd", XM
, EX
, XX
, XX
},
1663 { "(bad)", XM
, EX
, XX
, XX
},
1664 { "cvtdq2pd", XM
, EX
, XX
, XX
},
1665 { "cvttpd2dq", XM
, EX
, XX
, XX
},
1666 { "cvtpd2dq", XM
, EX
, XX
, XX
},
1670 { "cvtdq2ps", XM
, EX
, XX
, XX
},
1671 { "cvttps2dq",XM
, EX
, XX
, XX
},
1672 { "cvtps2dq",XM
, EX
, XX
, XX
},
1673 { "(bad)", XM
, EX
, XX
, XX
},
1677 { "cvtps2pd", XM
, EX
, XX
, XX
},
1678 { "cvtss2sd", XM
, EX
, XX
, XX
},
1679 { "cvtpd2ps", XM
, EX
, XX
, XX
},
1680 { "cvtsd2ss", XM
, EX
, XX
, XX
},
1684 { "maskmovq", MX
, MS
, XX
, XX
},
1685 { "(bad)", XM
, EX
, XX
, XX
},
1686 { "maskmovdqu", XM
, EX
, XX
, XX
},
1687 { "(bad)", XM
, EX
, XX
, XX
},
1691 { "movq", MX
, EM
, XX
, XX
},
1692 { "movdqu", XM
, EX
, XX
, XX
},
1693 { "movdqa", XM
, EX
, XX
, XX
},
1694 { "(bad)", XM
, EX
, XX
, XX
},
1698 { "movq", EM
, MX
, XX
, XX
},
1699 { "movdqu", EX
, XM
, XX
, XX
},
1700 { "movdqa", EX
, XM
, XX
, XX
},
1701 { "(bad)", EX
, XM
, XX
, XX
},
1705 { "(bad)", EX
, XM
, XX
, XX
},
1706 { "movq2dq", XM
, MS
, XX
, XX
},
1707 { "movq", EX
, XM
, XX
, XX
},
1708 { "movdq2q", MX
, XS
, XX
, XX
},
1712 { "pshufw", MX
, EM
, Ib
, XX
},
1713 { "pshufhw", XM
, EX
, Ib
, XX
},
1714 { "pshufd", XM
, EX
, Ib
, XX
},
1715 { "pshuflw", XM
, EX
, Ib
, XX
},
1719 { "movd", Edq
, MX
, XX
, XX
},
1720 { "movq", XM
, EX
, XX
, XX
},
1721 { "movd", Edq
, XM
, XX
, XX
},
1722 { "(bad)", Ed
, XM
, XX
, XX
},
1726 { "(bad)", MX
, EX
, XX
, XX
},
1727 { "(bad)", XM
, EX
, XX
, XX
},
1728 { "punpckhqdq", XM
, EX
, XX
, XX
},
1729 { "(bad)", XM
, EX
, XX
, XX
},
1733 { "movntq", EM
, MX
, XX
, XX
},
1734 { "(bad)", EM
, XM
, XX
, XX
},
1735 { "movntdq", EM
, XM
, XX
, XX
},
1736 { "(bad)", EM
, XM
, XX
, XX
},
1740 { "(bad)", MX
, EX
, XX
, XX
},
1741 { "(bad)", XM
, EX
, XX
, XX
},
1742 { "punpcklqdq", XM
, EX
, XX
, XX
},
1743 { "(bad)", XM
, EX
, XX
, XX
},
1747 { "(bad)", MX
, EX
, XX
, XX
},
1748 { "(bad)", XM
, EX
, XX
, XX
},
1749 { "addsubpd", XM
, EX
, XX
, XX
},
1750 { "addsubps", XM
, EX
, XX
, XX
},
1754 { "(bad)", MX
, EX
, XX
, XX
},
1755 { "(bad)", XM
, EX
, XX
, XX
},
1756 { "haddpd", XM
, EX
, XX
, XX
},
1757 { "haddps", XM
, EX
, XX
, XX
},
1761 { "(bad)", MX
, EX
, XX
, XX
},
1762 { "(bad)", XM
, EX
, XX
, XX
},
1763 { "hsubpd", XM
, EX
, XX
, XX
},
1764 { "hsubps", XM
, EX
, XX
, XX
},
1768 { "movlpX", XM
, EX
, SIMD_Fixup
, 'h', XX
}, /* really only 2 operands */
1769 { "movsldup", XM
, EX
, XX
, XX
},
1770 { "movlpd", XM
, EX
, XX
, XX
},
1771 { "movddup", XM
, EX
, XX
, XX
},
1775 { "movhpX", XM
, EX
, SIMD_Fixup
, 'l', XX
},
1776 { "movshdup", XM
, EX
, XX
, XX
},
1777 { "movhpd", XM
, EX
, XX
, XX
},
1778 { "(bad)", XM
, EX
, XX
, XX
},
1782 { "(bad)", XM
, EX
, XX
, XX
},
1783 { "(bad)", XM
, EX
, XX
, XX
},
1784 { "(bad)", XM
, EX
, XX
, XX
},
1785 { "lddqu", XM
, M
, XX
, XX
},
1789 {"movntps",Ev
, XM
, XX
, XX
},
1790 {"movntss",Ev
, XM
, XX
, XX
},
1791 {"movntpd",Ev
, XM
, XX
, XX
},
1792 {"movntsd",Ev
, XM
, XX
, XX
},
1797 {"vmread", Em
, Gm
, XX
, XX
},
1798 {"(bad)", XX
, XX
, XX
, XX
},
1799 {"extrq", XS
, Ib
, Ib
, XX
},
1800 {"insertq",XM
, XS
, Ib
, Ib
},
1805 {"vmwrite", Gm
, Em
, XX
, XX
},
1806 {"(bad)", XX
, XX
, XX
, XX
},
1807 {"extrq", XM
, XS
, XX
, XX
},
1808 {"insertq", XM
, XS
, XX
, XX
},
1813 { "bsrS", Gv
, Ev
, XX
, XX
},
1814 { "lzcntS", Gv
, Ev
, XX
, XX
},
1815 { "bsrS", Gv
, Ev
, XX
, XX
},
1816 { "(bad)", XX
, XX
, XX
, XX
},
1821 static const struct dis386 x86_64_table
[][2] = {
1823 { "arpl", Ew
, Gw
, XX
, XX
},
1824 { "movs{||lq|xd}", Gv
, Ed
, XX
, XX
},
1828 static const struct dis386 three_byte_table
[][32] = {
1831 { "pshufb", MX
, EM
, XX
, XX
},
1832 { "phaddw", MX
, EM
, XX
, XX
},
1833 { "phaddd", MX
, EM
, XX
, XX
},
1834 { "phaddsw", MX
, EM
, XX
, XX
},
1835 { "pmaddubsw", MX
, EM
, XX
, XX
},
1836 { "phsubw", MX
, EM
, XX
, XX
},
1837 { "phsubd", MX
, EM
, XX
, XX
},
1838 { "phsubsw", MX
, EM
, XX
, XX
},
1839 { "psignb", MX
, EM
, XX
, XX
},
1840 { "psignw", MX
, EM
, XX
, XX
},
1841 { "psignd", MX
, EM
, XX
, XX
},
1842 { "pmulhrsw", MX
, EM
, XX
, XX
},
1843 { "(bad)", XX
, XX
, XX
, XX
},
1844 { "(bad)", XX
, XX
, XX
, XX
},
1845 { "(bad)", XX
, XX
, XX
, XX
},
1846 { "(bad)", XX
, XX
, XX
, XX
},
1847 { "(bad)", XX
, XX
, XX
, XX
},
1848 { "(bad)", XX
, XX
, XX
, XX
},
1849 { "(bad)", XX
, XX
, XX
, XX
},
1850 { "(bad)", XX
, XX
, XX
, XX
},
1851 { "(bad)", XX
, XX
, XX
, XX
},
1852 { "(bad)", XX
, XX
, XX
, XX
},
1853 { "(bad)", XX
, XX
, XX
, XX
},
1854 { "(bad)", XX
, XX
, XX
, XX
},
1855 { "(bad)", XX
, XX
, XX
, XX
},
1856 { "(bad)", XX
, XX
, XX
, XX
},
1857 { "(bad)", XX
, XX
, XX
, XX
},
1858 { "(bad)", XX
, XX
, XX
, XX
},
1859 { "pabsb", MX
, EM
, XX
, XX
},
1860 { "pabsw", MX
, EM
, XX
, XX
},
1861 { "pabsd", MX
, EM
, XX
, XX
},
1862 { "(bad)", XX
, XX
, XX
, XX
}
1866 { "(bad)", XX
, XX
, XX
, XX
},
1867 { "(bad)", XX
, XX
, XX
, XX
},
1868 { "(bad)", XX
, XX
, XX
, XX
},
1869 { "(bad)", XX
, XX
, XX
, XX
},
1870 { "(bad)", XX
, XX
, XX
, XX
},
1871 { "(bad)", XX
, XX
, XX
, XX
},
1872 { "(bad)", XX
, XX
, XX
, XX
},
1873 { "(bad)", XX
, XX
, XX
, XX
},
1874 { "(bad)", XX
, XX
, XX
, XX
},
1875 { "(bad)", XX
, XX
, XX
, XX
},
1876 { "(bad)", XX
, XX
, XX
, XX
},
1877 { "(bad)", XX
, XX
, XX
, XX
},
1878 { "(bad)", XX
, XX
, XX
, XX
},
1879 { "(bad)", XX
, XX
, XX
, XX
},
1880 { "(bad)", XX
, XX
, XX
, XX
},
1881 { "palignr", MX
, EM
, Ib
, XX
},
1882 { "(bad)", XX
, XX
, XX
, XX
},
1883 { "(bad)", XX
, XX
, XX
, XX
},
1884 { "(bad)", XX
, XX
, XX
, XX
},
1885 { "(bad)", XX
, XX
, XX
, XX
},
1886 { "(bad)", XX
, XX
, XX
, XX
},
1887 { "(bad)", XX
, XX
, XX
, XX
},
1888 { "(bad)", XX
, XX
, XX
, XX
},
1889 { "(bad)", XX
, XX
, XX
, XX
},
1890 { "(bad)", XX
, XX
, XX
, XX
},
1891 { "(bad)", XX
, XX
, XX
, XX
},
1892 { "(bad)", XX
, XX
, XX
, XX
},
1893 { "(bad)", XX
, XX
, XX
, XX
},
1894 { "(bad)", XX
, XX
, XX
, XX
},
1895 { "(bad)", XX
, XX
, XX
, XX
},
1896 { "(bad)", XX
, XX
, XX
, XX
},
1897 { "(bad)", XX
, XX
, XX
, XX
}
1901 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
1913 FETCH_DATA (the_info
, codep
+ 1);
1917 /* REX prefixes family. */
1934 if (address_mode
== mode_64bit
)
1940 prefixes
|= PREFIX_REPZ
;
1943 prefixes
|= PREFIX_REPNZ
;
1946 prefixes
|= PREFIX_LOCK
;
1949 prefixes
|= PREFIX_CS
;
1952 prefixes
|= PREFIX_SS
;
1955 prefixes
|= PREFIX_DS
;
1958 prefixes
|= PREFIX_ES
;
1961 prefixes
|= PREFIX_FS
;
1964 prefixes
|= PREFIX_GS
;
1967 prefixes
|= PREFIX_DATA
;
1970 prefixes
|= PREFIX_ADDR
;
1973 /* fwait is really an instruction. If there are prefixes
1974 before the fwait, they belong to the fwait, *not* to the
1975 following instruction. */
1976 if (prefixes
|| rex
)
1978 prefixes
|= PREFIX_FWAIT
;
1982 prefixes
= PREFIX_FWAIT
;
1987 /* Rex is ignored when followed by another prefix. */
1998 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
2002 prefix_name (int pref
, int sizeflag
)
2006 /* REX prefixes family. */
2058 return (sizeflag
& DFLAG
) ? "data16" : "data32";
2060 if (address_mode
== mode_64bit
)
2061 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
2063 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
2071 static char op1out
[100], op2out
[100], op3out
[100], op4out
[100];
2072 static int op_ad
, op_index
[4];
2073 static int two_source_ops
;
2074 static bfd_vma op_address
[4];
2075 static bfd_vma op_riprel
[4];
2076 static bfd_vma start_pc
;
2079 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
2080 * (see topic "Redundant prefixes" in the "Differences from 8086"
2081 * section of the "Virtual 8086 Mode" chapter.)
2082 * 'pc' should be the address of this instruction, it will
2083 * be used to print the target address if this is a relative jump or call
2084 * The function returns the length of this instruction in bytes.
2087 static char intel_syntax
;
2088 static char open_char
;
2089 static char close_char
;
2090 static char separator_char
;
2091 static char scale_char
;
2093 /* Here for backwards compatibility. When gdb stops using
2094 print_insn_i386_att and print_insn_i386_intel these functions can
2095 disappear, and print_insn_i386 be merged into print_insn. */
2097 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
2101 return print_insn (pc
, info
);
2105 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
2109 return print_insn (pc
, info
);
2113 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
2117 return print_insn (pc
, info
);
2121 print_insn (bfd_vma pc
, disassemble_info
*info
)
2123 const struct dis386
*dp
;
2125 char *first
, *second
, *third
, *fourth
;
2127 unsigned char uses_SSE_prefix
, uses_LOCK_prefix
;
2130 struct dis_private priv
;
2132 if (info
->mach
== bfd_mach_x86_64_intel_syntax
2133 || info
->mach
== bfd_mach_x86_64
)
2134 address_mode
= mode_64bit
;
2136 address_mode
= mode_32bit
;
2138 if (intel_syntax
== (char) -1)
2139 intel_syntax
= (info
->mach
== bfd_mach_i386_i386_intel_syntax
2140 || info
->mach
== bfd_mach_x86_64_intel_syntax
);
2142 if (info
->mach
== bfd_mach_i386_i386
2143 || info
->mach
== bfd_mach_x86_64
2144 || info
->mach
== bfd_mach_i386_i386_intel_syntax
2145 || info
->mach
== bfd_mach_x86_64_intel_syntax
)
2146 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
2147 else if (info
->mach
== bfd_mach_i386_i8086
)
2148 priv
.orig_sizeflag
= 0;
2152 for (p
= info
->disassembler_options
; p
!= NULL
; )
2154 if (strncmp (p
, "x86-64", 6) == 0)
2156 address_mode
= mode_64bit
;
2157 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
2159 else if (strncmp (p
, "i386", 4) == 0)
2161 address_mode
= mode_32bit
;
2162 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
2164 else if (strncmp (p
, "i8086", 5) == 0)
2166 address_mode
= mode_16bit
;
2167 priv
.orig_sizeflag
= 0;
2169 else if (strncmp (p
, "intel", 5) == 0)
2173 else if (strncmp (p
, "att", 3) == 0)
2177 else if (strncmp (p
, "addr", 4) == 0)
2179 if (p
[4] == '1' && p
[5] == '6')
2180 priv
.orig_sizeflag
&= ~AFLAG
;
2181 else if (p
[4] == '3' && p
[5] == '2')
2182 priv
.orig_sizeflag
|= AFLAG
;
2184 else if (strncmp (p
, "data", 4) == 0)
2186 if (p
[4] == '1' && p
[5] == '6')
2187 priv
.orig_sizeflag
&= ~DFLAG
;
2188 else if (p
[4] == '3' && p
[5] == '2')
2189 priv
.orig_sizeflag
|= DFLAG
;
2191 else if (strncmp (p
, "suffix", 6) == 0)
2192 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
2194 p
= strchr (p
, ',');
2201 names64
= intel_names64
;
2202 names32
= intel_names32
;
2203 names16
= intel_names16
;
2204 names8
= intel_names8
;
2205 names8rex
= intel_names8rex
;
2206 names_seg
= intel_names_seg
;
2207 index16
= intel_index16
;
2210 separator_char
= '+';
2215 names64
= att_names64
;
2216 names32
= att_names32
;
2217 names16
= att_names16
;
2218 names8
= att_names8
;
2219 names8rex
= att_names8rex
;
2220 names_seg
= att_names_seg
;
2221 index16
= att_index16
;
2224 separator_char
= ',';
2228 /* The output looks better if we put 7 bytes on a line, since that
2229 puts most long word instructions on a single line. */
2230 info
->bytes_per_line
= 7;
2232 info
->private_data
= &priv
;
2233 priv
.max_fetched
= priv
.the_buffer
;
2234 priv
.insn_start
= pc
;
2242 op_index
[0] = op_index
[1] = op_index
[2] = op_index
[3] = -1;
2246 start_codep
= priv
.the_buffer
;
2247 codep
= priv
.the_buffer
;
2249 if (setjmp (priv
.bailout
) != 0)
2253 /* Getting here means we tried for data but didn't get it. That
2254 means we have an incomplete instruction of some sort. Just
2255 print the first byte as a prefix or a .byte pseudo-op. */
2256 if (codep
> priv
.the_buffer
)
2258 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
2260 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
2263 /* Just print the first byte as a .byte instruction. */
2264 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
2265 (unsigned int) priv
.the_buffer
[0]);
2278 sizeflag
= priv
.orig_sizeflag
;
2280 FETCH_DATA (info
, codep
+ 1);
2281 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
2283 if (((prefixes
& PREFIX_FWAIT
)
2284 && ((*codep
< 0xd8) || (*codep
> 0xdf)))
2285 || (rex
&& rex_used
))
2289 /* fwait not followed by floating point instruction, or rex followed
2290 by other prefixes. Print the first prefix. */
2291 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
2293 name
= INTERNAL_DISASSEMBLER_ERROR
;
2294 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
2300 FETCH_DATA (info
, codep
+ 2);
2301 dp
= &dis386_twobyte
[*++codep
];
2302 need_modrm
= twobyte_has_modrm
[*codep
];
2303 uses_SSE_prefix
= twobyte_uses_SSE_prefix
[*codep
];
2304 uses_LOCK_prefix
= (*codep
& ~0x02) == 0x20;
2308 dp
= &dis386
[*codep
];
2309 need_modrm
= onebyte_has_modrm
[*codep
];
2310 uses_SSE_prefix
= 0;
2311 uses_LOCK_prefix
= 0;
2314 /*"lzcnt"=0xBD is the only non-sse instruction which uses F3 in the opcode without any "rep(z|nz)"*/
2315 if (!uses_SSE_prefix
&& (prefixes
& PREFIX_REPZ
) && *codep
!=0xBD)
2318 used_prefixes
|= PREFIX_REPZ
;
2320 if (!uses_SSE_prefix
&& (prefixes
& PREFIX_REPNZ
) && *codep
!=0xBD)
2323 used_prefixes
|= PREFIX_REPNZ
;
2328 if (!uses_LOCK_prefix
&& (prefixes
& PREFIX_LOCK
))
2331 used_prefixes
|= PREFIX_LOCK
;
2334 if (prefixes
& PREFIX_ADDR
)
2337 if (dp
->bytemode3
!= loop_jcxz_mode
|| intel_syntax
)
2339 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
2340 oappend ("addr32 ");
2342 oappend ("addr16 ");
2343 used_prefixes
|= PREFIX_ADDR
;
2347 if (!uses_SSE_prefix
&& (prefixes
& PREFIX_DATA
))
2350 if (dp
->bytemode3
== cond_jump_mode
2351 && dp
->bytemode1
== v_mode
2354 if (sizeflag
& DFLAG
)
2355 oappend ("data32 ");
2357 oappend ("data16 ");
2358 used_prefixes
|= PREFIX_DATA
;
2362 if (dp
->name
== NULL
&& dp
->bytemode1
== IS_3BYTE_OPCODE
)
2364 FETCH_DATA (info
, codep
+ 2);
2365 dp
= &three_byte_table
[dp
->bytemode2
][*codep
++];
2366 mod
= (*codep
>> 6) & 3;
2367 reg
= (*codep
>> 3) & 7;
2370 else if (need_modrm
)
2372 FETCH_DATA (info
, codep
+ 1);
2373 mod
= (*codep
>> 6) & 3;
2374 reg
= (*codep
>> 3) & 7;
2378 if (dp
->name
== NULL
&& dp
->bytemode1
== FLOATCODE
)
2385 if (dp
->name
== NULL
)
2387 switch (dp
->bytemode1
)
2390 dp
= &grps
[dp
->bytemode2
][reg
];
2393 case USE_PREFIX_USER_TABLE
:
2395 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
2396 if (prefixes
& PREFIX_REPZ
)
2400 used_prefixes
|= (prefixes
& PREFIX_DATA
);
2401 if (prefixes
& PREFIX_DATA
)
2405 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
2406 if (prefixes
& PREFIX_REPNZ
)
2410 dp
= &prefix_user_table
[dp
->bytemode2
][index
];
2413 case X86_64_SPECIAL
:
2414 index
= address_mode
== mode_64bit
? 1 : 0;
2415 dp
= &x86_64_table
[dp
->bytemode2
][index
];
2419 oappend (INTERNAL_DISASSEMBLER_ERROR
);
2424 if (putop (dp
->name
, sizeflag
) == 0)
2429 (*dp
->op1
) (dp
->bytemode1
, sizeflag
);
2434 (*dp
->op2
) (dp
->bytemode2
, sizeflag
);
2439 (*dp
->op3
) (dp
->bytemode3
, sizeflag
);
2444 (*dp
->op4
) (dp
->bytemode4
, sizeflag
);
2448 /* See if any prefixes were not used. If so, print the first one
2449 separately. If we don't do this, we'll wind up printing an
2450 instruction stream which does not precisely correspond to the
2451 bytes we are disassembling. */
2452 if ((prefixes
& ~used_prefixes
) != 0)
2456 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
2458 name
= INTERNAL_DISASSEMBLER_ERROR
;
2459 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
2462 if (rex
& ~rex_used
)
2465 name
= prefix_name (rex
| 0x40, priv
.orig_sizeflag
);
2467 name
= INTERNAL_DISASSEMBLER_ERROR
;
2468 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
2471 obufp
= obuf
+ strlen (obuf
);
2472 for (i
= strlen (obuf
); i
< 6; i
++)
2475 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
2477 /* The enter and bound instructions are printed with operands in the same
2478 order as the intel book; everything else is printed in reverse order. */
2479 if (intel_syntax
|| two_source_ops
)
2485 op_ad
= op_index
[0];
2486 op_index
[0] = op_index
[3];
2487 op_index
[3] = op_ad
;
2488 op_ad
= op_index
[1];
2489 op_index
[1] = op_index
[2];
2490 op_index
[2] = op_ad
;
2503 if (op_index
[0] != -1 && !op_riprel
[0])
2504 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[0]], info
);
2506 (*info
->fprintf_func
) (info
->stream
, "%s", first
);
2513 (*info
->fprintf_func
) (info
->stream
, ",");
2514 if (op_index
[1] != -1 && !op_riprel
[1])
2515 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[1]], info
);
2517 (*info
->fprintf_func
) (info
->stream
, "%s", second
);
2524 (*info
->fprintf_func
) (info
->stream
, ",");
2525 if (op_index
[2] != -1 && !op_riprel
[2])
2526 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[2]], info
);
2528 (*info
->fprintf_func
) (info
->stream
, "%s", third
);
2535 (*info
->fprintf_func
) (info
->stream
, ",");
2536 if (op_index
[3] != -1 && !op_riprel
[3])
2537 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[3]], info
);
2539 (*info
->fprintf_func
) (info
->stream
, "%s", fourth
);
2542 for (i
= 0; i
< 4; i
++)
2543 if (op_index
[i
] != -1 && op_riprel
[i
])
2545 (*info
->fprintf_func
) (info
->stream
, " # ");
2546 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
2547 + op_address
[op_index
[i
]]), info
);
2549 return codep
- priv
.the_buffer
;
2552 static const char *float_mem
[] = {
2627 static const unsigned char float_mem_mode
[] = {
2703 #define STi OP_STi, 0
2705 #define FGRPd9_2 NULL, NULL, 0, NULL, 0, NULL, 0, NULL, 0
2706 #define FGRPd9_4 NULL, NULL, 1, NULL, 0, NULL, 0, NULL, 0
2707 #define FGRPd9_5 NULL, NULL, 2, NULL, 0, NULL, 0, NULL, 0
2708 #define FGRPd9_6 NULL, NULL, 3, NULL, 0, NULL, 0, NULL, 0
2709 #define FGRPd9_7 NULL, NULL, 4, NULL, 0, NULL, 0, NULL, 0
2710 #define FGRPda_5 NULL, NULL, 5, NULL, 0, NULL, 0, NULL, 0
2711 #define FGRPdb_4 NULL, NULL, 6, NULL, 0, NULL, 0, NULL, 0
2712 #define FGRPde_3 NULL, NULL, 7, NULL, 0, NULL, 0, NULL, 0
2713 #define FGRPdf_4 NULL, NULL, 8, NULL, 0, NULL, 0, NULL, 0
2715 static const struct dis386 float_reg
[][8] = {
2718 { "fadd", ST
, STi
, XX
, XX
},
2719 { "fmul", ST
, STi
, XX
, XX
},
2720 { "fcom", STi
, XX
, XX
, XX
},
2721 { "fcomp", STi
, XX
, XX
, XX
},
2722 { "fsub", ST
, STi
, XX
, XX
},
2723 { "fsubr", ST
, STi
, XX
, XX
},
2724 { "fdiv", ST
, STi
, XX
, XX
},
2725 { "fdivr", ST
, STi
, XX
, XX
},
2729 { "fld", STi
, XX
, XX
, XX
},
2730 { "fxch", STi
, XX
, XX
, XX
},
2732 { "(bad)", XX
, XX
, XX
, XX
},
2740 { "fcmovb", ST
, STi
, XX
, XX
},
2741 { "fcmove", ST
, STi
, XX
, XX
},
2742 { "fcmovbe",ST
, STi
, XX
, XX
},
2743 { "fcmovu", ST
, STi
, XX
, XX
},
2744 { "(bad)", XX
, XX
, XX
, XX
},
2746 { "(bad)", XX
, XX
, XX
, XX
},
2747 { "(bad)", XX
, XX
, XX
, XX
},
2751 { "fcmovnb",ST
, STi
, XX
, XX
},
2752 { "fcmovne",ST
, STi
, XX
, XX
},
2753 { "fcmovnbe",ST
, STi
, XX
, XX
},
2754 { "fcmovnu",ST
, STi
, XX
, XX
},
2756 { "fucomi", ST
, STi
, XX
, XX
},
2757 { "fcomi", ST
, STi
, XX
, XX
},
2758 { "(bad)", XX
, XX
, XX
, XX
},
2762 { "fadd", STi
, ST
, XX
, XX
},
2763 { "fmul", STi
, ST
, XX
, XX
},
2764 { "(bad)", XX
, XX
, XX
, XX
},
2765 { "(bad)", XX
, XX
, XX
, XX
},
2767 { "fsub", STi
, ST
, XX
, XX
},
2768 { "fsubr", STi
, ST
, XX
, XX
},
2769 { "fdiv", STi
, ST
, XX
, XX
},
2770 { "fdivr", STi
, ST
, XX
, XX
},
2772 { "fsubr", STi
, ST
, XX
, XX
},
2773 { "fsub", STi
, ST
, XX
, XX
},
2774 { "fdivr", STi
, ST
, XX
, XX
},
2775 { "fdiv", STi
, ST
, XX
, XX
},
2780 { "ffree", STi
, XX
, XX
, XX
},
2781 { "(bad)", XX
, XX
, XX
, XX
},
2782 { "fst", STi
, XX
, XX
, XX
},
2783 { "fstp", STi
, XX
, XX
, XX
},
2784 { "fucom", STi
, XX
, XX
, XX
},
2785 { "fucomp", STi
, XX
, XX
, XX
},
2786 { "(bad)", XX
, XX
, XX
, XX
},
2787 { "(bad)", XX
, XX
, XX
, XX
},
2791 { "faddp", STi
, ST
, XX
, XX
},
2792 { "fmulp", STi
, ST
, XX
, XX
},
2793 { "(bad)", XX
, XX
, XX
, XX
},
2796 { "fsubp", STi
, ST
, XX
, XX
},
2797 { "fsubrp", STi
, ST
, XX
, XX
},
2798 { "fdivp", STi
, ST
, XX
, XX
},
2799 { "fdivrp", STi
, ST
, XX
, XX
},
2801 { "fsubrp", STi
, ST
, XX
, XX
},
2802 { "fsubp", STi
, ST
, XX
, XX
},
2803 { "fdivrp", STi
, ST
, XX
, XX
},
2804 { "fdivp", STi
, ST
, XX
, XX
},
2809 { "ffreep", STi
, XX
, XX
, XX
},
2810 { "(bad)", XX
, XX
, XX
, XX
},
2811 { "(bad)", XX
, XX
, XX
, XX
},
2812 { "(bad)", XX
, XX
, XX
, XX
},
2814 { "fucomip",ST
, STi
, XX
, XX
},
2815 { "fcomip", ST
, STi
, XX
, XX
},
2816 { "(bad)", XX
, XX
, XX
, XX
},
2820 static char *fgrps
[][8] = {
2823 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2828 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
2833 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
2838 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
2843 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
2848 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2853 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
2854 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
2859 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2864 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2869 dofloat (int sizeflag
)
2871 const struct dis386
*dp
;
2872 unsigned char floatop
;
2874 floatop
= codep
[-1];
2878 int fp_indx
= (floatop
- 0xd8) * 8 + reg
;
2880 putop (float_mem
[fp_indx
], sizeflag
);
2883 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
2886 /* Skip mod/rm byte. */
2890 dp
= &float_reg
[floatop
- 0xd8][reg
];
2891 if (dp
->name
== NULL
)
2893 putop (fgrps
[dp
->bytemode1
][rm
], sizeflag
);
2895 /* Instruction fnstsw is only one with strange arg. */
2896 if (floatop
== 0xdf && codep
[-1] == 0xe0)
2897 strcpy (op1out
, names16
[0]);
2901 putop (dp
->name
, sizeflag
);
2906 (*dp
->op1
) (dp
->bytemode1
, sizeflag
);
2911 (*dp
->op2
) (dp
->bytemode2
, sizeflag
);
2916 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
2918 oappend ("%st" + intel_syntax
);
2922 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
2924 sprintf (scratchbuf
, "%%st(%d)", rm
);
2925 oappend (scratchbuf
+ intel_syntax
);
2928 /* Capital letters in template are macros. */
2930 putop (const char *template, int sizeflag
)
2935 for (p
= template; *p
; p
++)
2946 if (address_mode
== mode_64bit
)
2954 /* Alternative not valid. */
2955 strcpy (obuf
, "(bad)");
2959 else if (*p
== '\0')
2980 if (mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
2986 if (sizeflag
& SUFFIX_ALWAYS
)
2990 if (intel_syntax
&& !alt
)
2992 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
2994 if (sizeflag
& DFLAG
)
2995 *obufp
++ = intel_syntax
? 'd' : 'l';
2997 *obufp
++ = intel_syntax
? 'w' : 's';
2998 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3001 case 'E': /* For jcxz/jecxz */
3002 if (address_mode
== mode_64bit
)
3004 if (sizeflag
& AFLAG
)
3010 if (sizeflag
& AFLAG
)
3012 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
3017 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
3019 if (sizeflag
& AFLAG
)
3020 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
3022 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
3023 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
3029 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
3030 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
3032 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
3035 if (prefixes
& PREFIX_DS
)
3049 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
3058 if (sizeflag
& SUFFIX_ALWAYS
)
3062 if ((prefixes
& PREFIX_FWAIT
) == 0)
3065 used_prefixes
|= PREFIX_FWAIT
;
3068 USED_REX (REX_MODE64
);
3069 if (rex
& REX_MODE64
)
3077 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
3086 if ((prefixes
& PREFIX_DATA
)
3087 || (rex
& REX_MODE64
)
3088 || (sizeflag
& SUFFIX_ALWAYS
))
3090 USED_REX (REX_MODE64
);
3091 if (rex
& REX_MODE64
)
3095 if (sizeflag
& DFLAG
)
3100 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3106 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
3108 if (mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
3114 if (intel_syntax
&& !alt
)
3116 USED_REX (REX_MODE64
);
3117 if (mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
3119 if (rex
& REX_MODE64
)
3123 if (sizeflag
& DFLAG
)
3124 *obufp
++ = intel_syntax
? 'd' : 'l';
3128 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3132 USED_REX (REX_MODE64
);
3135 if (rex
& REX_MODE64
)
3140 else if (sizeflag
& DFLAG
)
3153 if (rex
& REX_MODE64
)
3155 else if (sizeflag
& DFLAG
)
3160 if (!(rex
& REX_MODE64
))
3161 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3166 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
3168 if (sizeflag
& SUFFIX_ALWAYS
)
3176 if (sizeflag
& SUFFIX_ALWAYS
)
3178 if (rex
& REX_MODE64
)
3182 if (sizeflag
& DFLAG
)
3186 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3191 if (prefixes
& PREFIX_DATA
)
3195 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3200 if (rex
& REX_MODE64
)
3202 USED_REX (REX_MODE64
);
3206 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
3208 /* operand size flag for cwtl, cbtw */
3212 else if (sizeflag
& DFLAG
)
3223 if (sizeflag
& DFLAG
)
3234 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3244 oappend (const char *s
)
3247 obufp
+= strlen (s
);
3253 if (prefixes
& PREFIX_CS
)
3255 used_prefixes
|= PREFIX_CS
;
3256 oappend ("%cs:" + intel_syntax
);
3258 if (prefixes
& PREFIX_DS
)
3260 used_prefixes
|= PREFIX_DS
;
3261 oappend ("%ds:" + intel_syntax
);
3263 if (prefixes
& PREFIX_SS
)
3265 used_prefixes
|= PREFIX_SS
;
3266 oappend ("%ss:" + intel_syntax
);
3268 if (prefixes
& PREFIX_ES
)
3270 used_prefixes
|= PREFIX_ES
;
3271 oappend ("%es:" + intel_syntax
);
3273 if (prefixes
& PREFIX_FS
)
3275 used_prefixes
|= PREFIX_FS
;
3276 oappend ("%fs:" + intel_syntax
);
3278 if (prefixes
& PREFIX_GS
)
3280 used_prefixes
|= PREFIX_GS
;
3281 oappend ("%gs:" + intel_syntax
);
3286 OP_indirE (int bytemode
, int sizeflag
)
3290 OP_E (bytemode
, sizeflag
);
3294 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
3296 if (address_mode
== mode_64bit
)
3304 sprintf_vma (tmp
, disp
);
3305 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
3306 strcpy (buf
+ 2, tmp
+ i
);
3310 bfd_signed_vma v
= disp
;
3317 /* Check for possible overflow on 0x8000000000000000. */
3320 strcpy (buf
, "9223372036854775808");
3334 tmp
[28 - i
] = (v
% 10) + '0';
3338 strcpy (buf
, tmp
+ 29 - i
);
3344 sprintf (buf
, "0x%x", (unsigned int) disp
);
3346 sprintf (buf
, "%d", (int) disp
);
3351 intel_operand_size (int bytemode
, int sizeflag
)
3356 oappend ("BYTE PTR ");
3360 oappend ("WORD PTR ");
3363 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
3365 oappend ("QWORD PTR ");
3366 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3372 USED_REX (REX_MODE64
);
3373 if (rex
& REX_MODE64
)
3374 oappend ("QWORD PTR ");
3375 else if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
3376 oappend ("DWORD PTR ");
3378 oappend ("WORD PTR ");
3379 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3382 oappend ("DWORD PTR ");
3385 oappend ("QWORD PTR ");
3388 if (address_mode
== mode_64bit
)
3389 oappend ("QWORD PTR ");
3391 oappend ("DWORD PTR ");
3394 if (sizeflag
& DFLAG
)
3395 oappend ("FWORD PTR ");
3397 oappend ("DWORD PTR ");
3398 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3401 oappend ("TBYTE PTR ");
3404 oappend ("XMMWORD PTR ");
3412 OP_E (int bytemode
, int sizeflag
)
3417 USED_REX (REX_EXTZ
);
3421 /* Skip mod/rm byte. */
3432 oappend (names8rex
[rm
+ add
]);
3434 oappend (names8
[rm
+ add
]);
3437 oappend (names16
[rm
+ add
]);
3440 oappend (names32
[rm
+ add
]);
3443 oappend (names64
[rm
+ add
]);
3446 if (address_mode
== mode_64bit
)
3447 oappend (names64
[rm
+ add
]);
3449 oappend (names32
[rm
+ add
]);
3452 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
3454 oappend (names64
[rm
+ add
]);
3455 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3463 USED_REX (REX_MODE64
);
3464 if (rex
& REX_MODE64
)
3465 oappend (names64
[rm
+ add
]);
3466 else if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
3467 oappend (names32
[rm
+ add
]);
3469 oappend (names16
[rm
+ add
]);
3470 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3475 oappend (INTERNAL_DISASSEMBLER_ERROR
);
3483 intel_operand_size (bytemode
, sizeflag
);
3486 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
) /* 32 bit address mode */
3501 FETCH_DATA (the_info
, codep
+ 1);
3502 index
= (*codep
>> 3) & 7;
3503 if (address_mode
== mode_64bit
|| index
!= 0x4)
3504 /* When INDEX == 0x4 in 32 bit mode, SCALE is ignored. */
3505 scale
= (*codep
>> 6) & 3;
3507 USED_REX (REX_EXTY
);
3517 if ((base
& 7) == 5)
3520 if (address_mode
== mode_64bit
&& !havesib
)
3526 FETCH_DATA (the_info
, codep
+ 1);
3528 if ((disp
& 0x80) != 0)
3537 if (mod
!= 0 || (base
& 7) == 5)
3539 print_operand_value (scratchbuf
, !riprel
, disp
);
3540 oappend (scratchbuf
);
3548 if (havebase
|| (havesib
&& (index
!= 4 || scale
!= 0)))
3550 *obufp
++ = open_char
;
3551 if (intel_syntax
&& riprel
)
3555 oappend (address_mode
== mode_64bit
&& (sizeflag
& AFLAG
)
3556 ? names64
[base
] : names32
[base
]);
3561 if (!intel_syntax
|| havebase
)
3563 *obufp
++ = separator_char
;
3566 oappend (address_mode
== mode_64bit
&& (sizeflag
& AFLAG
)
3567 ? names64
[index
] : names32
[index
]);
3569 if (scale
!= 0 || (!intel_syntax
&& index
!= 4))
3571 *obufp
++ = scale_char
;
3573 sprintf (scratchbuf
, "%d", 1 << scale
);
3574 oappend (scratchbuf
);
3577 if (intel_syntax
&& disp
)
3579 if ((bfd_signed_vma
) disp
> 0)
3588 disp
= - (bfd_signed_vma
) disp
;
3591 print_operand_value (scratchbuf
, mod
!= 1, disp
);
3592 oappend (scratchbuf
);
3595 *obufp
++ = close_char
;
3598 else if (intel_syntax
)
3600 if (mod
!= 0 || (base
& 7) == 5)
3602 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
3603 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
3607 oappend (names_seg
[ds_reg
- es_reg
]);
3610 print_operand_value (scratchbuf
, 1, disp
);
3611 oappend (scratchbuf
);
3616 { /* 16 bit address mode */
3623 if ((disp
& 0x8000) != 0)
3628 FETCH_DATA (the_info
, codep
+ 1);
3630 if ((disp
& 0x80) != 0)
3635 if ((disp
& 0x8000) != 0)
3641 if (mod
!= 0 || rm
== 6)
3643 print_operand_value (scratchbuf
, 0, disp
);
3644 oappend (scratchbuf
);
3647 if (mod
!= 0 || rm
!= 6)
3649 *obufp
++ = open_char
;
3651 oappend (index16
[rm
]);
3652 if (intel_syntax
&& disp
)
3654 if ((bfd_signed_vma
) disp
> 0)
3663 disp
= - (bfd_signed_vma
) disp
;
3666 print_operand_value (scratchbuf
, mod
!= 1, disp
);
3667 oappend (scratchbuf
);
3670 *obufp
++ = close_char
;
3673 else if (intel_syntax
)
3675 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
3676 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
3680 oappend (names_seg
[ds_reg
- es_reg
]);
3683 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
3684 oappend (scratchbuf
);
3690 OP_G (int bytemode
, int sizeflag
)
3693 USED_REX (REX_EXTX
);
3701 oappend (names8rex
[reg
+ add
]);
3703 oappend (names8
[reg
+ add
]);
3706 oappend (names16
[reg
+ add
]);
3709 oappend (names32
[reg
+ add
]);
3712 oappend (names64
[reg
+ add
]);
3717 USED_REX (REX_MODE64
);
3718 if (rex
& REX_MODE64
)
3719 oappend (names64
[reg
+ add
]);
3720 else if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
3721 oappend (names32
[reg
+ add
]);
3723 oappend (names16
[reg
+ add
]);
3724 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3727 if (address_mode
== mode_64bit
)
3728 oappend (names64
[reg
+ add
]);
3730 oappend (names32
[reg
+ add
]);
3733 oappend (INTERNAL_DISASSEMBLER_ERROR
);
3746 FETCH_DATA (the_info
, codep
+ 8);
3747 a
= *codep
++ & 0xff;
3748 a
|= (*codep
++ & 0xff) << 8;
3749 a
|= (*codep
++ & 0xff) << 16;
3750 a
|= (*codep
++ & 0xff) << 24;
3751 b
= *codep
++ & 0xff;
3752 b
|= (*codep
++ & 0xff) << 8;
3753 b
|= (*codep
++ & 0xff) << 16;
3754 b
|= (*codep
++ & 0xff) << 24;
3755 x
= a
+ ((bfd_vma
) b
<< 32);
3763 static bfd_signed_vma
3766 bfd_signed_vma x
= 0;
3768 FETCH_DATA (the_info
, codep
+ 4);
3769 x
= *codep
++ & (bfd_signed_vma
) 0xff;
3770 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
3771 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
3772 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
3776 static bfd_signed_vma
3779 bfd_signed_vma x
= 0;
3781 FETCH_DATA (the_info
, codep
+ 4);
3782 x
= *codep
++ & (bfd_signed_vma
) 0xff;
3783 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
3784 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
3785 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
3787 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
3797 FETCH_DATA (the_info
, codep
+ 2);
3798 x
= *codep
++ & 0xff;
3799 x
|= (*codep
++ & 0xff) << 8;
3804 set_op (bfd_vma op
, int riprel
)
3806 op_index
[op_ad
] = op_ad
;
3807 if (address_mode
== mode_64bit
)
3809 op_address
[op_ad
] = op
;
3810 op_riprel
[op_ad
] = riprel
;
3814 /* Mask to get a 32-bit address. */
3815 op_address
[op_ad
] = op
& 0xffffffff;
3816 op_riprel
[op_ad
] = riprel
& 0xffffffff;
3821 OP_REG (int code
, int sizeflag
)
3825 USED_REX (REX_EXTZ
);
3837 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
3838 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
3839 s
= names16
[code
- ax_reg
+ add
];
3841 case es_reg
: case ss_reg
: case cs_reg
:
3842 case ds_reg
: case fs_reg
: case gs_reg
:
3843 s
= names_seg
[code
- es_reg
+ add
];
3845 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
3846 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
3849 s
= names8rex
[code
- al_reg
+ add
];
3851 s
= names8
[code
- al_reg
];
3853 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
3854 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
3855 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
3857 s
= names64
[code
- rAX_reg
+ add
];
3860 code
+= eAX_reg
- rAX_reg
;
3862 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
3863 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
3864 USED_REX (REX_MODE64
);
3865 if (rex
& REX_MODE64
)
3866 s
= names64
[code
- eAX_reg
+ add
];
3867 else if (sizeflag
& DFLAG
)
3868 s
= names32
[code
- eAX_reg
+ add
];
3870 s
= names16
[code
- eAX_reg
+ add
];
3871 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3874 s
= INTERNAL_DISASSEMBLER_ERROR
;
3881 OP_IMREG (int code
, int sizeflag
)
3893 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
3894 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
3895 s
= names16
[code
- ax_reg
];
3897 case es_reg
: case ss_reg
: case cs_reg
:
3898 case ds_reg
: case fs_reg
: case gs_reg
:
3899 s
= names_seg
[code
- es_reg
];
3901 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
3902 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
3905 s
= names8rex
[code
- al_reg
];
3907 s
= names8
[code
- al_reg
];
3909 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
3910 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
3911 USED_REX (REX_MODE64
);
3912 if (rex
& REX_MODE64
)
3913 s
= names64
[code
- eAX_reg
];
3914 else if (sizeflag
& DFLAG
)
3915 s
= names32
[code
- eAX_reg
];
3917 s
= names16
[code
- eAX_reg
];
3918 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3921 s
= INTERNAL_DISASSEMBLER_ERROR
;
3928 OP_I (int bytemode
, int sizeflag
)
3931 bfd_signed_vma mask
= -1;
3936 FETCH_DATA (the_info
, codep
+ 1);
3941 if (address_mode
== mode_64bit
)
3948 USED_REX (REX_MODE64
);
3949 if (rex
& REX_MODE64
)
3951 else if (sizeflag
& DFLAG
)
3961 used_prefixes
|= (prefixes
& PREFIX_DATA
);
3972 oappend (INTERNAL_DISASSEMBLER_ERROR
);
3977 scratchbuf
[0] = '$';
3978 print_operand_value (scratchbuf
+ 1, 1, op
);
3979 oappend (scratchbuf
+ intel_syntax
);
3980 scratchbuf
[0] = '\0';
3984 OP_I64 (int bytemode
, int sizeflag
)
3987 bfd_signed_vma mask
= -1;
3989 if (address_mode
!= mode_64bit
)
3991 OP_I (bytemode
, sizeflag
);
3998 FETCH_DATA (the_info
, codep
+ 1);
4003 USED_REX (REX_MODE64
);
4004 if (rex
& REX_MODE64
)
4006 else if (sizeflag
& DFLAG
)
4016 used_prefixes
|= (prefixes
& PREFIX_DATA
);
4023 oappend (INTERNAL_DISASSEMBLER_ERROR
);
4028 scratchbuf
[0] = '$';
4029 print_operand_value (scratchbuf
+ 1, 1, op
);
4030 oappend (scratchbuf
+ intel_syntax
);
4031 scratchbuf
[0] = '\0';
4035 OP_sI (int bytemode
, int sizeflag
)
4038 bfd_signed_vma mask
= -1;
4043 FETCH_DATA (the_info
, codep
+ 1);
4045 if ((op
& 0x80) != 0)
4050 USED_REX (REX_MODE64
);
4051 if (rex
& REX_MODE64
)
4053 else if (sizeflag
& DFLAG
)
4062 if ((op
& 0x8000) != 0)
4065 used_prefixes
|= (prefixes
& PREFIX_DATA
);
4070 if ((op
& 0x8000) != 0)
4074 oappend (INTERNAL_DISASSEMBLER_ERROR
);
4078 scratchbuf
[0] = '$';
4079 print_operand_value (scratchbuf
+ 1, 1, op
);
4080 oappend (scratchbuf
+ intel_syntax
);
4084 OP_J (int bytemode
, int sizeflag
)
4092 FETCH_DATA (the_info
, codep
+ 1);
4094 if ((disp
& 0x80) != 0)
4098 if ((sizeflag
& DFLAG
) || (rex
& REX_MODE64
))
4103 /* For some reason, a data16 prefix on a jump instruction
4104 means that the pc is masked to 16 bits after the
4105 displacement is added! */
4110 oappend (INTERNAL_DISASSEMBLER_ERROR
);
4113 disp
= (start_pc
+ codep
- start_codep
+ disp
) & mask
;
4115 print_operand_value (scratchbuf
, 1, disp
);
4116 oappend (scratchbuf
);
4120 OP_SEG (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
4122 oappend (names_seg
[reg
]);
4126 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
4130 if (sizeflag
& DFLAG
)
4140 used_prefixes
|= (prefixes
& PREFIX_DATA
);
4142 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
4144 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
4145 oappend (scratchbuf
);
4149 OP_OFF (int bytemode
, int sizeflag
)
4153 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
4154 intel_operand_size (bytemode
, sizeflag
);
4157 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
4164 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
4165 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
4167 oappend (names_seg
[ds_reg
- es_reg
]);
4171 print_operand_value (scratchbuf
, 1, off
);
4172 oappend (scratchbuf
);
4176 OP_OFF64 (int bytemode
, int sizeflag
)
4180 if (address_mode
!= mode_64bit
)
4182 OP_OFF (bytemode
, sizeflag
);
4186 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
4187 intel_operand_size (bytemode
, sizeflag
);
4194 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
4195 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
4197 oappend (names_seg
[ds_reg
- es_reg
]);
4201 print_operand_value (scratchbuf
, 1, off
);
4202 oappend (scratchbuf
);
4206 ptr_reg (int code
, int sizeflag
)
4210 *obufp
++ = open_char
;
4211 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
4212 if (address_mode
== mode_64bit
)
4214 if (!(sizeflag
& AFLAG
))
4215 s
= names32
[code
- eAX_reg
];
4217 s
= names64
[code
- eAX_reg
];
4219 else if (sizeflag
& AFLAG
)
4220 s
= names32
[code
- eAX_reg
];
4222 s
= names16
[code
- eAX_reg
];
4224 *obufp
++ = close_char
;
4229 OP_ESreg (int code
, int sizeflag
)
4232 intel_operand_size (codep
[-1] & 1 ? v_mode
: b_mode
, sizeflag
);
4233 oappend ("%es:" + intel_syntax
);
4234 ptr_reg (code
, sizeflag
);
4238 OP_DSreg (int code
, int sizeflag
)
4241 intel_operand_size (codep
[-1] != 0xd7 && (codep
[-1] & 1)
4252 prefixes
|= PREFIX_DS
;
4254 ptr_reg (code
, sizeflag
);
4258 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
4263 USED_REX (REX_EXTX
);
4266 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
4268 used_prefixes
|= PREFIX_LOCK
;
4271 sprintf (scratchbuf
, "%%cr%d", reg
+ add
);
4272 oappend (scratchbuf
+ intel_syntax
);
4276 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
4279 USED_REX (REX_EXTX
);
4283 sprintf (scratchbuf
, "db%d", reg
+ add
);
4285 sprintf (scratchbuf
, "%%db%d", reg
+ add
);
4286 oappend (scratchbuf
);
4290 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
4292 sprintf (scratchbuf
, "%%tr%d", reg
);
4293 oappend (scratchbuf
+ intel_syntax
);
4297 OP_Rd (int bytemode
, int sizeflag
)
4300 OP_E (bytemode
, sizeflag
);
4306 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
4308 used_prefixes
|= (prefixes
& PREFIX_DATA
);
4309 if (prefixes
& PREFIX_DATA
)
4312 USED_REX (REX_EXTX
);
4315 sprintf (scratchbuf
, "%%xmm%d", reg
+ add
);
4318 sprintf (scratchbuf
, "%%mm%d", reg
);
4319 oappend (scratchbuf
+ intel_syntax
);
4323 OP_XMM (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
4326 USED_REX (REX_EXTX
);
4329 sprintf (scratchbuf
, "%%xmm%d", reg
+ add
);
4330 oappend (scratchbuf
+ intel_syntax
);
4334 OP_EM (int bytemode
, int sizeflag
)
4338 if (intel_syntax
&& bytemode
== v_mode
)
4340 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
4341 used_prefixes
|= (prefixes
& PREFIX_DATA
);
4343 OP_E (bytemode
, sizeflag
);
4347 /* Skip mod/rm byte. */
4350 used_prefixes
|= (prefixes
& PREFIX_DATA
);
4351 if (prefixes
& PREFIX_DATA
)
4355 USED_REX (REX_EXTZ
);
4358 sprintf (scratchbuf
, "%%xmm%d", rm
+ add
);
4361 sprintf (scratchbuf
, "%%mm%d", rm
);
4362 oappend (scratchbuf
+ intel_syntax
);
4366 OP_EX (int bytemode
, int sizeflag
)
4371 if (intel_syntax
&& bytemode
== v_mode
)
4373 switch (prefixes
& (PREFIX_DATA
|PREFIX_REPZ
|PREFIX_REPNZ
))
4375 case 0: bytemode
= x_mode
; break;
4376 case PREFIX_REPZ
: bytemode
= d_mode
; used_prefixes
|= PREFIX_REPZ
; break;
4377 case PREFIX_DATA
: bytemode
= x_mode
; used_prefixes
|= PREFIX_DATA
; break;
4378 case PREFIX_REPNZ
: bytemode
= q_mode
; used_prefixes
|= PREFIX_REPNZ
; break;
4379 default: bytemode
= 0; break;
4382 OP_E (bytemode
, sizeflag
);
4385 USED_REX (REX_EXTZ
);
4389 /* Skip mod/rm byte. */
4392 sprintf (scratchbuf
, "%%xmm%d", rm
+ add
);
4393 oappend (scratchbuf
+ intel_syntax
);
4397 OP_MS (int bytemode
, int sizeflag
)
4400 OP_EM (bytemode
, sizeflag
);
4406 OP_XS (int bytemode
, int sizeflag
)
4409 OP_EX (bytemode
, sizeflag
);
4415 OP_M (int bytemode
, int sizeflag
)
4418 BadOp (); /* bad lea,lds,les,lfs,lgs,lss modrm */
4420 OP_E (bytemode
, sizeflag
);
4424 OP_0f07 (int bytemode
, int sizeflag
)
4426 if (mod
!= 3 || rm
!= 0)
4429 OP_E (bytemode
, sizeflag
);
4433 OP_0fae (int bytemode
, int sizeflag
)
4438 strcpy (obuf
+ strlen (obuf
) - sizeof ("clflush") + 1, "sfence");
4440 if (reg
< 5 || rm
!= 0)
4442 BadOp (); /* bad sfence, mfence, or lfence */
4448 BadOp (); /* bad clflush */
4452 OP_E (bytemode
, sizeflag
);
4455 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
4456 32bit mode and "xchg %rax,%rax" in 64bit mode. NOP with REPZ prefix
4457 is called PAUSE. We display "xchg %ax,%ax" instead of "data16 nop".
4461 NOP_Fixup1 (int bytemode
, int sizeflag
)
4463 if (prefixes
== PREFIX_REPZ
)
4464 strcpy (obuf
, "pause");
4465 else if (prefixes
== PREFIX_DATA
4466 || ((rex
& REX_MODE64
) && rex
!= 0x48))
4467 OP_REG (bytemode
, sizeflag
);
4469 strcpy (obuf
, "nop");
4473 NOP_Fixup2 (int bytemode
, int sizeflag
)
4475 if (prefixes
== PREFIX_DATA
4476 || ((rex
& REX_MODE64
) && rex
!= 0x48))
4477 OP_IMREG (bytemode
, sizeflag
);
4480 static const char *const Suffix3DNow
[] = {
4481 /* 00 */ NULL
, NULL
, NULL
, NULL
,
4482 /* 04 */ NULL
, NULL
, NULL
, NULL
,
4483 /* 08 */ NULL
, NULL
, NULL
, NULL
,
4484 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
4485 /* 10 */ NULL
, NULL
, NULL
, NULL
,
4486 /* 14 */ NULL
, NULL
, NULL
, NULL
,
4487 /* 18 */ NULL
, NULL
, NULL
, NULL
,
4488 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
4489 /* 20 */ NULL
, NULL
, NULL
, NULL
,
4490 /* 24 */ NULL
, NULL
, NULL
, NULL
,
4491 /* 28 */ NULL
, NULL
, NULL
, NULL
,
4492 /* 2C */ NULL
, NULL
, NULL
, NULL
,
4493 /* 30 */ NULL
, NULL
, NULL
, NULL
,
4494 /* 34 */ NULL
, NULL
, NULL
, NULL
,
4495 /* 38 */ NULL
, NULL
, NULL
, NULL
,
4496 /* 3C */ NULL
, NULL
, NULL
, NULL
,
4497 /* 40 */ NULL
, NULL
, NULL
, NULL
,
4498 /* 44 */ NULL
, NULL
, NULL
, NULL
,
4499 /* 48 */ NULL
, NULL
, NULL
, NULL
,
4500 /* 4C */ NULL
, NULL
, NULL
, NULL
,
4501 /* 50 */ NULL
, NULL
, NULL
, NULL
,
4502 /* 54 */ NULL
, NULL
, NULL
, NULL
,
4503 /* 58 */ NULL
, NULL
, NULL
, NULL
,
4504 /* 5C */ NULL
, NULL
, NULL
, NULL
,
4505 /* 60 */ NULL
, NULL
, NULL
, NULL
,
4506 /* 64 */ NULL
, NULL
, NULL
, NULL
,
4507 /* 68 */ NULL
, NULL
, NULL
, NULL
,
4508 /* 6C */ NULL
, NULL
, NULL
, NULL
,
4509 /* 70 */ NULL
, NULL
, NULL
, NULL
,
4510 /* 74 */ NULL
, NULL
, NULL
, NULL
,
4511 /* 78 */ NULL
, NULL
, NULL
, NULL
,
4512 /* 7C */ NULL
, NULL
, NULL
, NULL
,
4513 /* 80 */ NULL
, NULL
, NULL
, NULL
,
4514 /* 84 */ NULL
, NULL
, NULL
, NULL
,
4515 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
4516 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
4517 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
4518 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
4519 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
4520 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
4521 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
4522 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
4523 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
4524 /* AC */ NULL
, NULL
, "pfacc", NULL
,
4525 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
4526 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pfmulhrw",
4527 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
4528 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
4529 /* C0 */ NULL
, NULL
, NULL
, NULL
,
4530 /* C4 */ NULL
, NULL
, NULL
, NULL
,
4531 /* C8 */ NULL
, NULL
, NULL
, NULL
,
4532 /* CC */ NULL
, NULL
, NULL
, NULL
,
4533 /* D0 */ NULL
, NULL
, NULL
, NULL
,
4534 /* D4 */ NULL
, NULL
, NULL
, NULL
,
4535 /* D8 */ NULL
, NULL
, NULL
, NULL
,
4536 /* DC */ NULL
, NULL
, NULL
, NULL
,
4537 /* E0 */ NULL
, NULL
, NULL
, NULL
,
4538 /* E4 */ NULL
, NULL
, NULL
, NULL
,
4539 /* E8 */ NULL
, NULL
, NULL
, NULL
,
4540 /* EC */ NULL
, NULL
, NULL
, NULL
,
4541 /* F0 */ NULL
, NULL
, NULL
, NULL
,
4542 /* F4 */ NULL
, NULL
, NULL
, NULL
,
4543 /* F8 */ NULL
, NULL
, NULL
, NULL
,
4544 /* FC */ NULL
, NULL
, NULL
, NULL
,
4548 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
4550 const char *mnemonic
;
4552 FETCH_DATA (the_info
, codep
+ 1);
4553 /* AMD 3DNow! instructions are specified by an opcode suffix in the
4554 place where an 8-bit immediate would normally go. ie. the last
4555 byte of the instruction. */
4556 obufp
= obuf
+ strlen (obuf
);
4557 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
4562 /* Since a variable sized modrm/sib chunk is between the start
4563 of the opcode (0x0f0f) and the opcode suffix, we need to do
4564 all the modrm processing first, and don't know until now that
4565 we have a bad opcode. This necessitates some cleaning up. */
4572 static const char *simd_cmp_op
[] = {
4584 OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
4586 unsigned int cmp_type
;
4588 FETCH_DATA (the_info
, codep
+ 1);
4589 obufp
= obuf
+ strlen (obuf
);
4590 cmp_type
= *codep
++ & 0xff;
4593 char suffix1
= 'p', suffix2
= 's';
4594 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
4595 if (prefixes
& PREFIX_REPZ
)
4599 used_prefixes
|= (prefixes
& PREFIX_DATA
);
4600 if (prefixes
& PREFIX_DATA
)
4604 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
4605 if (prefixes
& PREFIX_REPNZ
)
4606 suffix1
= 's', suffix2
= 'd';
4609 sprintf (scratchbuf
, "cmp%s%c%c",
4610 simd_cmp_op
[cmp_type
], suffix1
, suffix2
);
4611 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
4612 oappend (scratchbuf
);
4616 /* We have a bad extension byte. Clean up. */
4624 SIMD_Fixup (int extrachar
, int sizeflag ATTRIBUTE_UNUSED
)
4626 /* Change movlps/movhps to movhlps/movlhps for 2 register operand
4627 forms of these instructions. */
4630 char *p
= obuf
+ strlen (obuf
);
4633 *(p
- 1) = *(p
- 2);
4634 *(p
- 2) = *(p
- 3);
4635 *(p
- 3) = extrachar
;
4640 PNI_Fixup (int extrachar ATTRIBUTE_UNUSED
, int sizeflag
)
4642 if (mod
== 3 && reg
== 1 && rm
<= 1)
4644 /* Override "sidt". */
4645 size_t olen
= strlen (obuf
);
4646 char *p
= obuf
+ olen
- 4;
4647 const char **names
= (address_mode
== mode_64bit
4648 ? names64
: names32
);
4650 /* We might have a suffix when disassembling with -Msuffix. */
4654 /* Remove "addr16/addr32" if we aren't in Intel mode. */
4656 && (prefixes
& PREFIX_ADDR
)
4659 && strncmp (p
- 7, "addr", 4) == 0
4660 && (strncmp (p
- 3, "16", 2) == 0
4661 || strncmp (p
- 3, "32", 2) == 0))
4666 /* mwait %eax,%ecx */
4667 strcpy (p
, "mwait");
4669 strcpy (op1out
, names
[0]);
4673 /* monitor %eax,%ecx,%edx" */
4674 strcpy (p
, "monitor");
4677 const char **op1_names
;
4678 if (!(prefixes
& PREFIX_ADDR
))
4679 op1_names
= (address_mode
== mode_16bit
4683 op1_names
= (address_mode
!= mode_32bit
4684 ? names32
: names16
);
4685 used_prefixes
|= PREFIX_ADDR
;
4687 strcpy (op1out
, op1_names
[0]);
4688 strcpy (op3out
, names
[2]);
4693 strcpy (op2out
, names
[1]);
4704 SVME_Fixup (int bytemode
, int sizeflag
)
4736 OP_M (bytemode
, sizeflag
);
4739 /* Override "lidt". */
4740 p
= obuf
+ strlen (obuf
) - 4;
4741 /* We might have a suffix. */
4745 if (!(prefixes
& PREFIX_ADDR
))
4750 used_prefixes
|= PREFIX_ADDR
;
4754 strcpy (op2out
, names32
[1]);
4760 *obufp
++ = open_char
;
4761 if (address_mode
== mode_64bit
|| (sizeflag
& AFLAG
))
4765 strcpy (obufp
, alt
);
4766 obufp
+= strlen (alt
);
4767 *obufp
++ = close_char
;
4774 INVLPG_Fixup (int bytemode
, int sizeflag
)
4787 OP_M (bytemode
, sizeflag
);
4790 /* Override "invlpg". */
4791 strcpy (obuf
+ strlen (obuf
) - 6, alt
);
4798 /* Throw away prefixes and 1st. opcode byte. */
4799 codep
= insn_codep
+ 1;
4804 SEG_Fixup (int extrachar
, int sizeflag
)
4808 /* We need to add a proper suffix with
4819 if (prefixes
& PREFIX_DATA
)
4823 USED_REX (REX_MODE64
);
4824 if (rex
& REX_MODE64
)
4829 strcat (obuf
, suffix
);
4833 /* We need to fix the suffix for
4840 Override "mov[l|q]". */
4841 char *p
= obuf
+ strlen (obuf
) - 1;
4843 /* We might not have a suffix. */
4849 OP_E (extrachar
, sizeflag
);
4853 VMX_Fixup (int extrachar ATTRIBUTE_UNUSED
, int sizeflag
)
4855 if (mod
== 3 && reg
== 0 && rm
>=1 && rm
<= 4)
4857 /* Override "sgdt". */
4858 char *p
= obuf
+ strlen (obuf
) - 4;
4860 /* We might have a suffix when disassembling with -Msuffix. */
4867 strcpy (p
, "vmcall");
4870 strcpy (p
, "vmlaunch");
4873 strcpy (p
, "vmresume");
4876 strcpy (p
, "vmxoff");
4887 OP_VMX (int bytemode
, int sizeflag
)
4889 used_prefixes
|= (prefixes
& (PREFIX_DATA
| PREFIX_REPZ
));
4890 if (prefixes
& PREFIX_DATA
)
4891 strcpy (obuf
, "vmclear");
4892 else if (prefixes
& PREFIX_REPZ
)
4893 strcpy (obuf
, "vmxon");
4895 strcpy (obuf
, "vmptrld");
4896 OP_E (bytemode
, sizeflag
);
4900 REP_Fixup (int bytemode
, int sizeflag
)
4902 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
4906 if (prefixes
& PREFIX_REPZ
)
4907 switch (*insn_codep
)
4909 case 0x6e: /* outsb */
4910 case 0x6f: /* outsw/outsl */
4911 case 0xa4: /* movsb */
4912 case 0xa5: /* movsw/movsl/movsq */
4918 case 0xaa: /* stosb */
4919 case 0xab: /* stosw/stosl/stosq */
4920 case 0xac: /* lodsb */
4921 case 0xad: /* lodsw/lodsl/lodsq */
4922 if (!intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
4927 case 0x6c: /* insb */
4928 case 0x6d: /* insl/insw */
4944 olen
= strlen (obuf
);
4945 p
= obuf
+ olen
- ilen
- 1 - 4;
4946 /* Handle "repz [addr16|addr32]". */
4947 if ((prefixes
& PREFIX_ADDR
))
4950 memmove (p
+ 3, p
+ 4, olen
- (p
+ 3 - obuf
));
4958 OP_IMREG (bytemode
, sizeflag
);
4961 OP_ESreg (bytemode
, sizeflag
);
4964 OP_DSreg (bytemode
, sizeflag
);