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x86/Intel: debug registers are named DRn
[binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43
44 static int print_insn (bfd_vma, disassemble_info *);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma get64 (void);
59 static bfd_signed_vma get32 (void);
60 static bfd_signed_vma get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
116
117 static void MOVSXD_Fixup (int, int);
118
119 static void OP_Mask (int, int);
120
121 struct dis_private {
122 /* Points to first byte not fetched. */
123 bfd_byte *max_fetched;
124 bfd_byte the_buffer[MAX_MNEM_SIZE];
125 bfd_vma insn_start;
126 int orig_sizeflag;
127 OPCODES_SIGJMP_BUF bailout;
128 };
129
130 enum address_mode
131 {
132 mode_16bit,
133 mode_32bit,
134 mode_64bit
135 };
136
137 enum address_mode address_mode;
138
139 /* Flags for the prefixes for the current instruction. See below. */
140 static int prefixes;
141
142 /* REX prefix the current instruction. See below. */
143 static int rex;
144 /* Bits of REX we've already used. */
145 static int rex_used;
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
151 { \
152 if (value) \
153 { \
154 if ((rex & value)) \
155 rex_used |= (value) | REX_OPCODE; \
156 } \
157 else \
158 rex_used |= REX_OPCODE; \
159 }
160
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes;
164
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
169 #define PREFIX_CS 8
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
178
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
181 on error. */
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
185
186 static int
187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
188 {
189 int status;
190 struct dis_private *priv = (struct dis_private *) info->private_data;
191 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
192
193 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
194 status = (*info->read_memory_func) (start,
195 priv->max_fetched,
196 addr - priv->max_fetched,
197 info);
198 else
199 status = -1;
200 if (status != 0)
201 {
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
205 STATUS. */
206 if (priv->max_fetched == priv->the_buffer)
207 (*info->memory_error_func) (status, start, info);
208 OPCODES_SIGLONGJMP (priv->bailout, 1);
209 }
210 else
211 priv->max_fetched = addr;
212 return 1;
213 }
214
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
222
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
225 | PREFIX_REPNZ \
226 | PREFIX_DATA)
227
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
232
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
235
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
292
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
319
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
325
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
337
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
344
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
388
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
402
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
406
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
412
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
417
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
419
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
429
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
437
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
440
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
443
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
446 #define AFLAG 2
447 #define DFLAG 1
448
449 enum
450 {
451 /* byte operand */
452 b_mode = 1,
453 /* byte operand with operand swapped */
454 b_swap_mode,
455 /* byte operand, sign extend like 'T' suffix */
456 b_T_mode,
457 /* operand size depends on prefixes */
458 v_mode,
459 /* operand size depends on prefixes with operand swapped */
460 v_swap_mode,
461 /* operand size depends on address prefix */
462 va_mode,
463 /* word operand */
464 w_mode,
465 /* double word operand */
466 d_mode,
467 /* double word operand with operand swapped */
468 d_swap_mode,
469 /* quad word operand */
470 q_mode,
471 /* quad word operand with operand swapped */
472 q_swap_mode,
473 /* ten-byte operand */
474 t_mode,
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
477 x_mode,
478 /* Similar to x_mode, but with different EVEX mem shifts. */
479 evex_x_gscat_mode,
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
481 bw_unit_mode,
482 /* Similar to x_mode, but with disabled broadcast. */
483 evex_x_nobcst_mode,
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
485 in EVEX. */
486 x_swap_mode,
487 /* 16-byte XMM operand */
488 xmm_mode,
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
491 allowed. */
492 xmmq_mode,
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode,
495 /* XMM register or byte memory operand */
496 xmm_mb_mode,
497 /* XMM register or word memory operand */
498 xmm_mw_mode,
499 /* XMM register or double word memory operand */
500 xmm_md_mode,
501 /* XMM register or quad word memory operand */
502 xmm_mq_mode,
503 /* 16-byte XMM, word, double word or quad word operand. */
504 xmmdw_mode,
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
506 xmmqd_mode,
507 /* 32-byte YMM operand */
508 ymm_mode,
509 /* quad word, ymmword or zmmword memory operand. */
510 ymmq_mode,
511 /* 32-byte YMM or 16-byte word operand */
512 ymmxmm_mode,
513 /* TMM operand */
514 tmm_mode,
515 /* d_mode in 32bit, q_mode in 64bit mode. */
516 m_mode,
517 /* pair of v_mode operands */
518 a_mode,
519 cond_jump_mode,
520 loop_jcxz_mode,
521 movsxd_mode,
522 v_bnd_mode,
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
524 v_bndmk_mode,
525 /* operand size depends on REX prefixes. */
526 dq_mode,
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
529 dqw_mode,
530 /* bounds operand */
531 bnd_mode,
532 /* bounds operand with operand swapped */
533 bnd_swap_mode,
534 /* 4- or 6-byte pointer operand */
535 f_mode,
536 const_1_mode,
537 /* v_mode for indirect branch opcodes. */
538 indir_v_mode,
539 /* v_mode for stack-related opcodes. */
540 stack_v_mode,
541 /* non-quad operand size depends on prefixes */
542 z_mode,
543 /* 16-byte operand */
544 o_mode,
545 /* registers like dq_mode, memory like b_mode. */
546 dqb_mode,
547 /* registers like d_mode, memory like b_mode. */
548 db_mode,
549 /* registers like d_mode, memory like w_mode. */
550 dw_mode,
551 /* registers like dq_mode, memory like d_mode. */
552 dqd_mode,
553 /* normal vex mode */
554 vex_mode,
555
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode,
558 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
559 vex_vsib_d_w_d_mode,
560 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
561 vex_vsib_q_w_dq_mode,
562 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
563 vex_vsib_q_w_d_mode,
564 /* mandatory non-vector SIB. */
565 vex_sibmem_mode,
566
567 /* scalar, ignore vector length. */
568 scalar_mode,
569 /* like vex_mode, ignore vector length. */
570 vex_scalar_mode,
571 /* Operand size depends on the VEX.W bit, ignore vector length. */
572 vex_scalar_w_dq_mode,
573
574 /* Static rounding. */
575 evex_rounding_mode,
576 /* Static rounding, 64-bit mode only. */
577 evex_rounding_64_mode,
578 /* Supress all exceptions. */
579 evex_sae_mode,
580
581 /* Mask register operand. */
582 mask_mode,
583 /* Mask register operand. */
584 mask_bd_mode,
585
586 es_reg,
587 cs_reg,
588 ss_reg,
589 ds_reg,
590 fs_reg,
591 gs_reg,
592
593 eAX_reg,
594 eCX_reg,
595 eDX_reg,
596 eBX_reg,
597 eSP_reg,
598 eBP_reg,
599 eSI_reg,
600 eDI_reg,
601
602 al_reg,
603 cl_reg,
604 dl_reg,
605 bl_reg,
606 ah_reg,
607 ch_reg,
608 dh_reg,
609 bh_reg,
610
611 ax_reg,
612 cx_reg,
613 dx_reg,
614 bx_reg,
615 sp_reg,
616 bp_reg,
617 si_reg,
618 di_reg,
619
620 rAX_reg,
621 rCX_reg,
622 rDX_reg,
623 rBX_reg,
624 rSP_reg,
625 rBP_reg,
626 rSI_reg,
627 rDI_reg,
628
629 z_mode_ax_reg,
630 indir_dx_reg
631 };
632
633 enum
634 {
635 FLOATCODE = 1,
636 USE_REG_TABLE,
637 USE_MOD_TABLE,
638 USE_RM_TABLE,
639 USE_PREFIX_TABLE,
640 USE_X86_64_TABLE,
641 USE_3BYTE_TABLE,
642 USE_XOP_8F_TABLE,
643 USE_VEX_C4_TABLE,
644 USE_VEX_C5_TABLE,
645 USE_VEX_LEN_TABLE,
646 USE_VEX_W_TABLE,
647 USE_EVEX_TABLE,
648 USE_EVEX_LEN_TABLE
649 };
650
651 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
652
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
654 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
655 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
656 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
657 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
658 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
659 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
660 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
661 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
662 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
663 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
664 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
665 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
666 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
667 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
668 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
669
670 enum
671 {
672 REG_80 = 0,
673 REG_81,
674 REG_83,
675 REG_8F,
676 REG_C0,
677 REG_C1,
678 REG_C6,
679 REG_C7,
680 REG_D0,
681 REG_D1,
682 REG_D2,
683 REG_D3,
684 REG_F6,
685 REG_F7,
686 REG_FE,
687 REG_FF,
688 REG_0F00,
689 REG_0F01,
690 REG_0F0D,
691 REG_0F18,
692 REG_0F1C_P_0_MOD_0,
693 REG_0F1E_P_1_MOD_3,
694 REG_0F71,
695 REG_0F72,
696 REG_0F73,
697 REG_0FA6,
698 REG_0FA7,
699 REG_0FAE,
700 REG_0FBA,
701 REG_0FC7,
702 REG_VEX_0F71,
703 REG_VEX_0F72,
704 REG_VEX_0F73,
705 REG_VEX_0FAE,
706 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
707 REG_VEX_0F38F3,
708
709 REG_0FXOP_09_01_L_0,
710 REG_0FXOP_09_02_L_0,
711 REG_0FXOP_09_12_M_1_L_0,
712 REG_0FXOP_0A_12_L_0,
713
714 REG_EVEX_0F71,
715 REG_EVEX_0F72,
716 REG_EVEX_0F73,
717 REG_EVEX_0F38C6,
718 REG_EVEX_0F38C7
719 };
720
721 enum
722 {
723 MOD_8D = 0,
724 MOD_C6_REG_7,
725 MOD_C7_REG_7,
726 MOD_FF_REG_3,
727 MOD_FF_REG_5,
728 MOD_0F01_REG_0,
729 MOD_0F01_REG_1,
730 MOD_0F01_REG_2,
731 MOD_0F01_REG_3,
732 MOD_0F01_REG_5,
733 MOD_0F01_REG_7,
734 MOD_0F12_PREFIX_0,
735 MOD_0F12_PREFIX_2,
736 MOD_0F13,
737 MOD_0F16_PREFIX_0,
738 MOD_0F16_PREFIX_2,
739 MOD_0F17,
740 MOD_0F18_REG_0,
741 MOD_0F18_REG_1,
742 MOD_0F18_REG_2,
743 MOD_0F18_REG_3,
744 MOD_0F18_REG_4,
745 MOD_0F18_REG_5,
746 MOD_0F18_REG_6,
747 MOD_0F18_REG_7,
748 MOD_0F1A_PREFIX_0,
749 MOD_0F1B_PREFIX_0,
750 MOD_0F1B_PREFIX_1,
751 MOD_0F1C_PREFIX_0,
752 MOD_0F1E_PREFIX_1,
753 MOD_0F2B_PREFIX_0,
754 MOD_0F2B_PREFIX_1,
755 MOD_0F2B_PREFIX_2,
756 MOD_0F2B_PREFIX_3,
757 MOD_0F50,
758 MOD_0F71_REG_2,
759 MOD_0F71_REG_4,
760 MOD_0F71_REG_6,
761 MOD_0F72_REG_2,
762 MOD_0F72_REG_4,
763 MOD_0F72_REG_6,
764 MOD_0F73_REG_2,
765 MOD_0F73_REG_3,
766 MOD_0F73_REG_6,
767 MOD_0F73_REG_7,
768 MOD_0FAE_REG_0,
769 MOD_0FAE_REG_1,
770 MOD_0FAE_REG_2,
771 MOD_0FAE_REG_3,
772 MOD_0FAE_REG_4,
773 MOD_0FAE_REG_5,
774 MOD_0FAE_REG_6,
775 MOD_0FAE_REG_7,
776 MOD_0FB2,
777 MOD_0FB4,
778 MOD_0FB5,
779 MOD_0FC3,
780 MOD_0FC7_REG_3,
781 MOD_0FC7_REG_4,
782 MOD_0FC7_REG_5,
783 MOD_0FC7_REG_6,
784 MOD_0FC7_REG_7,
785 MOD_0FD7,
786 MOD_0FE7_PREFIX_2,
787 MOD_0FF0_PREFIX_3,
788 MOD_0F382A,
789 MOD_VEX_0F3849_X86_64_P_0_W_0,
790 MOD_VEX_0F3849_X86_64_P_2_W_0,
791 MOD_VEX_0F3849_X86_64_P_3_W_0,
792 MOD_VEX_0F384B_X86_64_P_1_W_0,
793 MOD_VEX_0F384B_X86_64_P_2_W_0,
794 MOD_VEX_0F384B_X86_64_P_3_W_0,
795 MOD_VEX_0F385C_X86_64_P_1_W_0,
796 MOD_VEX_0F385E_X86_64_P_0_W_0,
797 MOD_VEX_0F385E_X86_64_P_1_W_0,
798 MOD_VEX_0F385E_X86_64_P_2_W_0,
799 MOD_VEX_0F385E_X86_64_P_3_W_0,
800 MOD_0F38F5,
801 MOD_0F38F6_PREFIX_0,
802 MOD_0F38F8_PREFIX_1,
803 MOD_0F38F8_PREFIX_2,
804 MOD_0F38F8_PREFIX_3,
805 MOD_0F38F9,
806 MOD_62_32BIT,
807 MOD_C4_32BIT,
808 MOD_C5_32BIT,
809 MOD_VEX_0F12_PREFIX_0,
810 MOD_VEX_0F12_PREFIX_2,
811 MOD_VEX_0F13,
812 MOD_VEX_0F16_PREFIX_0,
813 MOD_VEX_0F16_PREFIX_2,
814 MOD_VEX_0F17,
815 MOD_VEX_0F2B,
816 MOD_VEX_W_0_0F41_P_0_LEN_1,
817 MOD_VEX_W_1_0F41_P_0_LEN_1,
818 MOD_VEX_W_0_0F41_P_2_LEN_1,
819 MOD_VEX_W_1_0F41_P_2_LEN_1,
820 MOD_VEX_W_0_0F42_P_0_LEN_1,
821 MOD_VEX_W_1_0F42_P_0_LEN_1,
822 MOD_VEX_W_0_0F42_P_2_LEN_1,
823 MOD_VEX_W_1_0F42_P_2_LEN_1,
824 MOD_VEX_W_0_0F44_P_0_LEN_1,
825 MOD_VEX_W_1_0F44_P_0_LEN_1,
826 MOD_VEX_W_0_0F44_P_2_LEN_1,
827 MOD_VEX_W_1_0F44_P_2_LEN_1,
828 MOD_VEX_W_0_0F45_P_0_LEN_1,
829 MOD_VEX_W_1_0F45_P_0_LEN_1,
830 MOD_VEX_W_0_0F45_P_2_LEN_1,
831 MOD_VEX_W_1_0F45_P_2_LEN_1,
832 MOD_VEX_W_0_0F46_P_0_LEN_1,
833 MOD_VEX_W_1_0F46_P_0_LEN_1,
834 MOD_VEX_W_0_0F46_P_2_LEN_1,
835 MOD_VEX_W_1_0F46_P_2_LEN_1,
836 MOD_VEX_W_0_0F47_P_0_LEN_1,
837 MOD_VEX_W_1_0F47_P_0_LEN_1,
838 MOD_VEX_W_0_0F47_P_2_LEN_1,
839 MOD_VEX_W_1_0F47_P_2_LEN_1,
840 MOD_VEX_W_0_0F4A_P_0_LEN_1,
841 MOD_VEX_W_1_0F4A_P_0_LEN_1,
842 MOD_VEX_W_0_0F4A_P_2_LEN_1,
843 MOD_VEX_W_1_0F4A_P_2_LEN_1,
844 MOD_VEX_W_0_0F4B_P_0_LEN_1,
845 MOD_VEX_W_1_0F4B_P_0_LEN_1,
846 MOD_VEX_W_0_0F4B_P_2_LEN_1,
847 MOD_VEX_0F50,
848 MOD_VEX_0F71_REG_2,
849 MOD_VEX_0F71_REG_4,
850 MOD_VEX_0F71_REG_6,
851 MOD_VEX_0F72_REG_2,
852 MOD_VEX_0F72_REG_4,
853 MOD_VEX_0F72_REG_6,
854 MOD_VEX_0F73_REG_2,
855 MOD_VEX_0F73_REG_3,
856 MOD_VEX_0F73_REG_6,
857 MOD_VEX_0F73_REG_7,
858 MOD_VEX_W_0_0F91_P_0_LEN_0,
859 MOD_VEX_W_1_0F91_P_0_LEN_0,
860 MOD_VEX_W_0_0F91_P_2_LEN_0,
861 MOD_VEX_W_1_0F91_P_2_LEN_0,
862 MOD_VEX_W_0_0F92_P_0_LEN_0,
863 MOD_VEX_W_0_0F92_P_2_LEN_0,
864 MOD_VEX_0F92_P_3_LEN_0,
865 MOD_VEX_W_0_0F93_P_0_LEN_0,
866 MOD_VEX_W_0_0F93_P_2_LEN_0,
867 MOD_VEX_0F93_P_3_LEN_0,
868 MOD_VEX_W_0_0F98_P_0_LEN_0,
869 MOD_VEX_W_1_0F98_P_0_LEN_0,
870 MOD_VEX_W_0_0F98_P_2_LEN_0,
871 MOD_VEX_W_1_0F98_P_2_LEN_0,
872 MOD_VEX_W_0_0F99_P_0_LEN_0,
873 MOD_VEX_W_1_0F99_P_0_LEN_0,
874 MOD_VEX_W_0_0F99_P_2_LEN_0,
875 MOD_VEX_W_1_0F99_P_2_LEN_0,
876 MOD_VEX_0FAE_REG_2,
877 MOD_VEX_0FAE_REG_3,
878 MOD_VEX_0FD7,
879 MOD_VEX_0FE7,
880 MOD_VEX_0FF0_PREFIX_3,
881 MOD_VEX_0F381A,
882 MOD_VEX_0F382A,
883 MOD_VEX_0F382C,
884 MOD_VEX_0F382D,
885 MOD_VEX_0F382E,
886 MOD_VEX_0F382F,
887 MOD_VEX_0F385A,
888 MOD_VEX_0F388C,
889 MOD_VEX_0F388E,
890 MOD_VEX_0F3A30_L_0,
891 MOD_VEX_0F3A31_L_0,
892 MOD_VEX_0F3A32_L_0,
893 MOD_VEX_0F3A33_L_0,
894
895 MOD_VEX_0FXOP_09_12,
896
897 MOD_EVEX_0F12_PREFIX_0,
898 MOD_EVEX_0F12_PREFIX_2,
899 MOD_EVEX_0F13,
900 MOD_EVEX_0F16_PREFIX_0,
901 MOD_EVEX_0F16_PREFIX_2,
902 MOD_EVEX_0F17,
903 MOD_EVEX_0F2B,
904 MOD_EVEX_0F381A_W_0,
905 MOD_EVEX_0F381A_W_1,
906 MOD_EVEX_0F381B_W_0,
907 MOD_EVEX_0F381B_W_1,
908 MOD_EVEX_0F3828_P_1,
909 MOD_EVEX_0F382A_P_1_W_1,
910 MOD_EVEX_0F3838_P_1,
911 MOD_EVEX_0F383A_P_1_W_0,
912 MOD_EVEX_0F385A_W_0,
913 MOD_EVEX_0F385A_W_1,
914 MOD_EVEX_0F385B_W_0,
915 MOD_EVEX_0F385B_W_1,
916 MOD_EVEX_0F387A_W_0,
917 MOD_EVEX_0F387B_W_0,
918 MOD_EVEX_0F387C,
919 MOD_EVEX_0F38C6_REG_1,
920 MOD_EVEX_0F38C6_REG_2,
921 MOD_EVEX_0F38C6_REG_5,
922 MOD_EVEX_0F38C6_REG_6,
923 MOD_EVEX_0F38C7_REG_1,
924 MOD_EVEX_0F38C7_REG_2,
925 MOD_EVEX_0F38C7_REG_5,
926 MOD_EVEX_0F38C7_REG_6
927 };
928
929 enum
930 {
931 RM_C6_REG_7 = 0,
932 RM_C7_REG_7,
933 RM_0F01_REG_0,
934 RM_0F01_REG_1,
935 RM_0F01_REG_2,
936 RM_0F01_REG_3,
937 RM_0F01_REG_5_MOD_3,
938 RM_0F01_REG_7_MOD_3,
939 RM_0F1E_P_1_MOD_3_REG_7,
940 RM_0FAE_REG_6_MOD_3_P_0,
941 RM_0FAE_REG_7_MOD_3,
942 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
943 };
944
945 enum
946 {
947 PREFIX_90 = 0,
948 PREFIX_0F01_REG_3_RM_1,
949 PREFIX_0F01_REG_5_MOD_0,
950 PREFIX_0F01_REG_5_MOD_3_RM_0,
951 PREFIX_0F01_REG_5_MOD_3_RM_1,
952 PREFIX_0F01_REG_5_MOD_3_RM_2,
953 PREFIX_0F01_REG_7_MOD_3_RM_2,
954 PREFIX_0F09,
955 PREFIX_0F10,
956 PREFIX_0F11,
957 PREFIX_0F12,
958 PREFIX_0F16,
959 PREFIX_0F1A,
960 PREFIX_0F1B,
961 PREFIX_0F1C,
962 PREFIX_0F1E,
963 PREFIX_0F2A,
964 PREFIX_0F2B,
965 PREFIX_0F2C,
966 PREFIX_0F2D,
967 PREFIX_0F2E,
968 PREFIX_0F2F,
969 PREFIX_0F51,
970 PREFIX_0F52,
971 PREFIX_0F53,
972 PREFIX_0F58,
973 PREFIX_0F59,
974 PREFIX_0F5A,
975 PREFIX_0F5B,
976 PREFIX_0F5C,
977 PREFIX_0F5D,
978 PREFIX_0F5E,
979 PREFIX_0F5F,
980 PREFIX_0F60,
981 PREFIX_0F61,
982 PREFIX_0F62,
983 PREFIX_0F6F,
984 PREFIX_0F70,
985 PREFIX_0F78,
986 PREFIX_0F79,
987 PREFIX_0F7C,
988 PREFIX_0F7D,
989 PREFIX_0F7E,
990 PREFIX_0F7F,
991 PREFIX_0FAE_REG_0_MOD_3,
992 PREFIX_0FAE_REG_1_MOD_3,
993 PREFIX_0FAE_REG_2_MOD_3,
994 PREFIX_0FAE_REG_3_MOD_3,
995 PREFIX_0FAE_REG_4_MOD_0,
996 PREFIX_0FAE_REG_4_MOD_3,
997 PREFIX_0FAE_REG_5_MOD_3,
998 PREFIX_0FAE_REG_6_MOD_0,
999 PREFIX_0FAE_REG_6_MOD_3,
1000 PREFIX_0FAE_REG_7_MOD_0,
1001 PREFIX_0FB8,
1002 PREFIX_0FBC,
1003 PREFIX_0FBD,
1004 PREFIX_0FC2,
1005 PREFIX_0FC7_REG_6_MOD_0,
1006 PREFIX_0FC7_REG_6_MOD_3,
1007 PREFIX_0FC7_REG_7_MOD_3,
1008 PREFIX_0FD0,
1009 PREFIX_0FD6,
1010 PREFIX_0FE6,
1011 PREFIX_0FE7,
1012 PREFIX_0FF0,
1013 PREFIX_0FF7,
1014 PREFIX_0F38F0,
1015 PREFIX_0F38F1,
1016 PREFIX_0F38F6,
1017 PREFIX_0F38F8,
1018 PREFIX_VEX_0F10,
1019 PREFIX_VEX_0F11,
1020 PREFIX_VEX_0F12,
1021 PREFIX_VEX_0F16,
1022 PREFIX_VEX_0F2A,
1023 PREFIX_VEX_0F2C,
1024 PREFIX_VEX_0F2D,
1025 PREFIX_VEX_0F2E,
1026 PREFIX_VEX_0F2F,
1027 PREFIX_VEX_0F41,
1028 PREFIX_VEX_0F42,
1029 PREFIX_VEX_0F44,
1030 PREFIX_VEX_0F45,
1031 PREFIX_VEX_0F46,
1032 PREFIX_VEX_0F47,
1033 PREFIX_VEX_0F4A,
1034 PREFIX_VEX_0F4B,
1035 PREFIX_VEX_0F51,
1036 PREFIX_VEX_0F52,
1037 PREFIX_VEX_0F53,
1038 PREFIX_VEX_0F58,
1039 PREFIX_VEX_0F59,
1040 PREFIX_VEX_0F5A,
1041 PREFIX_VEX_0F5B,
1042 PREFIX_VEX_0F5C,
1043 PREFIX_VEX_0F5D,
1044 PREFIX_VEX_0F5E,
1045 PREFIX_VEX_0F5F,
1046 PREFIX_VEX_0F6F,
1047 PREFIX_VEX_0F70,
1048 PREFIX_VEX_0F7C,
1049 PREFIX_VEX_0F7D,
1050 PREFIX_VEX_0F7E,
1051 PREFIX_VEX_0F7F,
1052 PREFIX_VEX_0F90,
1053 PREFIX_VEX_0F91,
1054 PREFIX_VEX_0F92,
1055 PREFIX_VEX_0F93,
1056 PREFIX_VEX_0F98,
1057 PREFIX_VEX_0F99,
1058 PREFIX_VEX_0FC2,
1059 PREFIX_VEX_0FD0,
1060 PREFIX_VEX_0FE6,
1061 PREFIX_VEX_0FF0,
1062 PREFIX_VEX_0F3849_X86_64,
1063 PREFIX_VEX_0F384B_X86_64,
1064 PREFIX_VEX_0F385C_X86_64,
1065 PREFIX_VEX_0F385E_X86_64,
1066 PREFIX_VEX_0F38F5,
1067 PREFIX_VEX_0F38F6,
1068 PREFIX_VEX_0F38F7,
1069 PREFIX_VEX_0F3AF0,
1070
1071 PREFIX_EVEX_0F10,
1072 PREFIX_EVEX_0F11,
1073 PREFIX_EVEX_0F12,
1074 PREFIX_EVEX_0F16,
1075 PREFIX_EVEX_0F2A,
1076 PREFIX_EVEX_0F51,
1077 PREFIX_EVEX_0F58,
1078 PREFIX_EVEX_0F59,
1079 PREFIX_EVEX_0F5A,
1080 PREFIX_EVEX_0F5B,
1081 PREFIX_EVEX_0F5C,
1082 PREFIX_EVEX_0F5D,
1083 PREFIX_EVEX_0F5E,
1084 PREFIX_EVEX_0F5F,
1085 PREFIX_EVEX_0F6F,
1086 PREFIX_EVEX_0F70,
1087 PREFIX_EVEX_0F78,
1088 PREFIX_EVEX_0F79,
1089 PREFIX_EVEX_0F7A,
1090 PREFIX_EVEX_0F7B,
1091 PREFIX_EVEX_0F7E,
1092 PREFIX_EVEX_0F7F,
1093 PREFIX_EVEX_0FC2,
1094 PREFIX_EVEX_0FE6,
1095 PREFIX_EVEX_0F3810,
1096 PREFIX_EVEX_0F3811,
1097 PREFIX_EVEX_0F3812,
1098 PREFIX_EVEX_0F3813,
1099 PREFIX_EVEX_0F3814,
1100 PREFIX_EVEX_0F3815,
1101 PREFIX_EVEX_0F3820,
1102 PREFIX_EVEX_0F3821,
1103 PREFIX_EVEX_0F3822,
1104 PREFIX_EVEX_0F3823,
1105 PREFIX_EVEX_0F3824,
1106 PREFIX_EVEX_0F3825,
1107 PREFIX_EVEX_0F3826,
1108 PREFIX_EVEX_0F3827,
1109 PREFIX_EVEX_0F3828,
1110 PREFIX_EVEX_0F3829,
1111 PREFIX_EVEX_0F382A,
1112 PREFIX_EVEX_0F3830,
1113 PREFIX_EVEX_0F3831,
1114 PREFIX_EVEX_0F3832,
1115 PREFIX_EVEX_0F3833,
1116 PREFIX_EVEX_0F3834,
1117 PREFIX_EVEX_0F3835,
1118 PREFIX_EVEX_0F3838,
1119 PREFIX_EVEX_0F3839,
1120 PREFIX_EVEX_0F383A,
1121 PREFIX_EVEX_0F3852,
1122 PREFIX_EVEX_0F3853,
1123 PREFIX_EVEX_0F3868,
1124 PREFIX_EVEX_0F3872,
1125 PREFIX_EVEX_0F389A,
1126 PREFIX_EVEX_0F389B,
1127 PREFIX_EVEX_0F38AA,
1128 PREFIX_EVEX_0F38AB,
1129 };
1130
1131 enum
1132 {
1133 X86_64_06 = 0,
1134 X86_64_07,
1135 X86_64_0E,
1136 X86_64_16,
1137 X86_64_17,
1138 X86_64_1E,
1139 X86_64_1F,
1140 X86_64_27,
1141 X86_64_2F,
1142 X86_64_37,
1143 X86_64_3F,
1144 X86_64_60,
1145 X86_64_61,
1146 X86_64_62,
1147 X86_64_63,
1148 X86_64_6D,
1149 X86_64_6F,
1150 X86_64_82,
1151 X86_64_9A,
1152 X86_64_C2,
1153 X86_64_C3,
1154 X86_64_C4,
1155 X86_64_C5,
1156 X86_64_CE,
1157 X86_64_D4,
1158 X86_64_D5,
1159 X86_64_E8,
1160 X86_64_E9,
1161 X86_64_EA,
1162 X86_64_0F01_REG_0,
1163 X86_64_0F01_REG_1,
1164 X86_64_0F01_REG_2,
1165 X86_64_0F01_REG_3,
1166 X86_64_0F24,
1167 X86_64_0F26,
1168 X86_64_VEX_0F3849,
1169 X86_64_VEX_0F384B,
1170 X86_64_VEX_0F385C,
1171 X86_64_VEX_0F385E
1172 };
1173
1174 enum
1175 {
1176 THREE_BYTE_0F38 = 0,
1177 THREE_BYTE_0F3A
1178 };
1179
1180 enum
1181 {
1182 XOP_08 = 0,
1183 XOP_09,
1184 XOP_0A
1185 };
1186
1187 enum
1188 {
1189 VEX_0F = 0,
1190 VEX_0F38,
1191 VEX_0F3A
1192 };
1193
1194 enum
1195 {
1196 EVEX_0F = 0,
1197 EVEX_0F38,
1198 EVEX_0F3A
1199 };
1200
1201 enum
1202 {
1203 VEX_LEN_0F12_P_0_M_0 = 0,
1204 VEX_LEN_0F12_P_0_M_1,
1205 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1206 VEX_LEN_0F13_M_0,
1207 VEX_LEN_0F16_P_0_M_0,
1208 VEX_LEN_0F16_P_0_M_1,
1209 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1210 VEX_LEN_0F17_M_0,
1211 VEX_LEN_0F41_P_0,
1212 VEX_LEN_0F41_P_2,
1213 VEX_LEN_0F42_P_0,
1214 VEX_LEN_0F42_P_2,
1215 VEX_LEN_0F44_P_0,
1216 VEX_LEN_0F44_P_2,
1217 VEX_LEN_0F45_P_0,
1218 VEX_LEN_0F45_P_2,
1219 VEX_LEN_0F46_P_0,
1220 VEX_LEN_0F46_P_2,
1221 VEX_LEN_0F47_P_0,
1222 VEX_LEN_0F47_P_2,
1223 VEX_LEN_0F4A_P_0,
1224 VEX_LEN_0F4A_P_2,
1225 VEX_LEN_0F4B_P_0,
1226 VEX_LEN_0F4B_P_2,
1227 VEX_LEN_0F6E,
1228 VEX_LEN_0F77,
1229 VEX_LEN_0F7E_P_1,
1230 VEX_LEN_0F7E_P_2,
1231 VEX_LEN_0F90_P_0,
1232 VEX_LEN_0F90_P_2,
1233 VEX_LEN_0F91_P_0,
1234 VEX_LEN_0F91_P_2,
1235 VEX_LEN_0F92_P_0,
1236 VEX_LEN_0F92_P_2,
1237 VEX_LEN_0F92_P_3,
1238 VEX_LEN_0F93_P_0,
1239 VEX_LEN_0F93_P_2,
1240 VEX_LEN_0F93_P_3,
1241 VEX_LEN_0F98_P_0,
1242 VEX_LEN_0F98_P_2,
1243 VEX_LEN_0F99_P_0,
1244 VEX_LEN_0F99_P_2,
1245 VEX_LEN_0FAE_R_2_M_0,
1246 VEX_LEN_0FAE_R_3_M_0,
1247 VEX_LEN_0FC4,
1248 VEX_LEN_0FC5,
1249 VEX_LEN_0FD6,
1250 VEX_LEN_0FF7,
1251 VEX_LEN_0F3816,
1252 VEX_LEN_0F3819,
1253 VEX_LEN_0F381A_M_0,
1254 VEX_LEN_0F3836,
1255 VEX_LEN_0F3841,
1256 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1257 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1258 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1259 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1260 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1261 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1262 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1263 VEX_LEN_0F385A_M_0,
1264 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1265 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1266 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1267 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1268 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1269 VEX_LEN_0F38DB,
1270 VEX_LEN_0F38F2,
1271 VEX_LEN_0F38F3_R_1,
1272 VEX_LEN_0F38F3_R_2,
1273 VEX_LEN_0F38F3_R_3,
1274 VEX_LEN_0F38F5_P_0,
1275 VEX_LEN_0F38F5_P_1,
1276 VEX_LEN_0F38F5_P_3,
1277 VEX_LEN_0F38F6_P_3,
1278 VEX_LEN_0F38F7_P_0,
1279 VEX_LEN_0F38F7_P_1,
1280 VEX_LEN_0F38F7_P_2,
1281 VEX_LEN_0F38F7_P_3,
1282 VEX_LEN_0F3A00,
1283 VEX_LEN_0F3A01,
1284 VEX_LEN_0F3A06,
1285 VEX_LEN_0F3A14,
1286 VEX_LEN_0F3A15,
1287 VEX_LEN_0F3A16,
1288 VEX_LEN_0F3A17,
1289 VEX_LEN_0F3A18,
1290 VEX_LEN_0F3A19,
1291 VEX_LEN_0F3A20,
1292 VEX_LEN_0F3A21,
1293 VEX_LEN_0F3A22,
1294 VEX_LEN_0F3A30,
1295 VEX_LEN_0F3A31,
1296 VEX_LEN_0F3A32,
1297 VEX_LEN_0F3A33,
1298 VEX_LEN_0F3A38,
1299 VEX_LEN_0F3A39,
1300 VEX_LEN_0F3A41,
1301 VEX_LEN_0F3A46,
1302 VEX_LEN_0F3A60,
1303 VEX_LEN_0F3A61,
1304 VEX_LEN_0F3A62,
1305 VEX_LEN_0F3A63,
1306 VEX_LEN_0F3ADF,
1307 VEX_LEN_0F3AF0_P_3,
1308 VEX_LEN_0FXOP_08_85,
1309 VEX_LEN_0FXOP_08_86,
1310 VEX_LEN_0FXOP_08_87,
1311 VEX_LEN_0FXOP_08_8E,
1312 VEX_LEN_0FXOP_08_8F,
1313 VEX_LEN_0FXOP_08_95,
1314 VEX_LEN_0FXOP_08_96,
1315 VEX_LEN_0FXOP_08_97,
1316 VEX_LEN_0FXOP_08_9E,
1317 VEX_LEN_0FXOP_08_9F,
1318 VEX_LEN_0FXOP_08_A3,
1319 VEX_LEN_0FXOP_08_A6,
1320 VEX_LEN_0FXOP_08_B6,
1321 VEX_LEN_0FXOP_08_C0,
1322 VEX_LEN_0FXOP_08_C1,
1323 VEX_LEN_0FXOP_08_C2,
1324 VEX_LEN_0FXOP_08_C3,
1325 VEX_LEN_0FXOP_08_CC,
1326 VEX_LEN_0FXOP_08_CD,
1327 VEX_LEN_0FXOP_08_CE,
1328 VEX_LEN_0FXOP_08_CF,
1329 VEX_LEN_0FXOP_08_EC,
1330 VEX_LEN_0FXOP_08_ED,
1331 VEX_LEN_0FXOP_08_EE,
1332 VEX_LEN_0FXOP_08_EF,
1333 VEX_LEN_0FXOP_09_01,
1334 VEX_LEN_0FXOP_09_02,
1335 VEX_LEN_0FXOP_09_12_M_1,
1336 VEX_LEN_0FXOP_09_82_W_0,
1337 VEX_LEN_0FXOP_09_83_W_0,
1338 VEX_LEN_0FXOP_09_90,
1339 VEX_LEN_0FXOP_09_91,
1340 VEX_LEN_0FXOP_09_92,
1341 VEX_LEN_0FXOP_09_93,
1342 VEX_LEN_0FXOP_09_94,
1343 VEX_LEN_0FXOP_09_95,
1344 VEX_LEN_0FXOP_09_96,
1345 VEX_LEN_0FXOP_09_97,
1346 VEX_LEN_0FXOP_09_98,
1347 VEX_LEN_0FXOP_09_99,
1348 VEX_LEN_0FXOP_09_9A,
1349 VEX_LEN_0FXOP_09_9B,
1350 VEX_LEN_0FXOP_09_C1,
1351 VEX_LEN_0FXOP_09_C2,
1352 VEX_LEN_0FXOP_09_C3,
1353 VEX_LEN_0FXOP_09_C6,
1354 VEX_LEN_0FXOP_09_C7,
1355 VEX_LEN_0FXOP_09_CB,
1356 VEX_LEN_0FXOP_09_D1,
1357 VEX_LEN_0FXOP_09_D2,
1358 VEX_LEN_0FXOP_09_D3,
1359 VEX_LEN_0FXOP_09_D6,
1360 VEX_LEN_0FXOP_09_D7,
1361 VEX_LEN_0FXOP_09_DB,
1362 VEX_LEN_0FXOP_09_E1,
1363 VEX_LEN_0FXOP_09_E2,
1364 VEX_LEN_0FXOP_09_E3,
1365 VEX_LEN_0FXOP_0A_12,
1366 };
1367
1368 enum
1369 {
1370 EVEX_LEN_0F6E = 0,
1371 EVEX_LEN_0F7E_P_1,
1372 EVEX_LEN_0F7E_P_2,
1373 EVEX_LEN_0FC4,
1374 EVEX_LEN_0FC5,
1375 EVEX_LEN_0FD6,
1376 EVEX_LEN_0F3816,
1377 EVEX_LEN_0F3819_W_0,
1378 EVEX_LEN_0F3819_W_1,
1379 EVEX_LEN_0F381A_W_0_M_0,
1380 EVEX_LEN_0F381A_W_1_M_0,
1381 EVEX_LEN_0F381B_W_0_M_0,
1382 EVEX_LEN_0F381B_W_1_M_0,
1383 EVEX_LEN_0F3836,
1384 EVEX_LEN_0F385A_W_0_M_0,
1385 EVEX_LEN_0F385A_W_1_M_0,
1386 EVEX_LEN_0F385B_W_0_M_0,
1387 EVEX_LEN_0F385B_W_1_M_0,
1388 EVEX_LEN_0F38C6_R_1_M_0,
1389 EVEX_LEN_0F38C6_R_2_M_0,
1390 EVEX_LEN_0F38C6_R_5_M_0,
1391 EVEX_LEN_0F38C6_R_6_M_0,
1392 EVEX_LEN_0F38C7_R_1_M_0_W_0,
1393 EVEX_LEN_0F38C7_R_1_M_0_W_1,
1394 EVEX_LEN_0F38C7_R_2_M_0_W_0,
1395 EVEX_LEN_0F38C7_R_2_M_0_W_1,
1396 EVEX_LEN_0F38C7_R_5_M_0_W_0,
1397 EVEX_LEN_0F38C7_R_5_M_0_W_1,
1398 EVEX_LEN_0F38C7_R_6_M_0_W_0,
1399 EVEX_LEN_0F38C7_R_6_M_0_W_1,
1400 EVEX_LEN_0F3A00_W_1,
1401 EVEX_LEN_0F3A01_W_1,
1402 EVEX_LEN_0F3A14,
1403 EVEX_LEN_0F3A15,
1404 EVEX_LEN_0F3A16,
1405 EVEX_LEN_0F3A17,
1406 EVEX_LEN_0F3A18_W_0,
1407 EVEX_LEN_0F3A18_W_1,
1408 EVEX_LEN_0F3A19_W_0,
1409 EVEX_LEN_0F3A19_W_1,
1410 EVEX_LEN_0F3A1A_W_0,
1411 EVEX_LEN_0F3A1A_W_1,
1412 EVEX_LEN_0F3A1B_W_0,
1413 EVEX_LEN_0F3A1B_W_1,
1414 EVEX_LEN_0F3A20,
1415 EVEX_LEN_0F3A21_W_0,
1416 EVEX_LEN_0F3A22,
1417 EVEX_LEN_0F3A23_W_0,
1418 EVEX_LEN_0F3A23_W_1,
1419 EVEX_LEN_0F3A38_W_0,
1420 EVEX_LEN_0F3A38_W_1,
1421 EVEX_LEN_0F3A39_W_0,
1422 EVEX_LEN_0F3A39_W_1,
1423 EVEX_LEN_0F3A3A_W_0,
1424 EVEX_LEN_0F3A3A_W_1,
1425 EVEX_LEN_0F3A3B_W_0,
1426 EVEX_LEN_0F3A3B_W_1,
1427 EVEX_LEN_0F3A43_W_0,
1428 EVEX_LEN_0F3A43_W_1
1429 };
1430
1431 enum
1432 {
1433 VEX_W_0F41_P_0_LEN_1 = 0,
1434 VEX_W_0F41_P_2_LEN_1,
1435 VEX_W_0F42_P_0_LEN_1,
1436 VEX_W_0F42_P_2_LEN_1,
1437 VEX_W_0F44_P_0_LEN_0,
1438 VEX_W_0F44_P_2_LEN_0,
1439 VEX_W_0F45_P_0_LEN_1,
1440 VEX_W_0F45_P_2_LEN_1,
1441 VEX_W_0F46_P_0_LEN_1,
1442 VEX_W_0F46_P_2_LEN_1,
1443 VEX_W_0F47_P_0_LEN_1,
1444 VEX_W_0F47_P_2_LEN_1,
1445 VEX_W_0F4A_P_0_LEN_1,
1446 VEX_W_0F4A_P_2_LEN_1,
1447 VEX_W_0F4B_P_0_LEN_1,
1448 VEX_W_0F4B_P_2_LEN_1,
1449 VEX_W_0F90_P_0_LEN_0,
1450 VEX_W_0F90_P_2_LEN_0,
1451 VEX_W_0F91_P_0_LEN_0,
1452 VEX_W_0F91_P_2_LEN_0,
1453 VEX_W_0F92_P_0_LEN_0,
1454 VEX_W_0F92_P_2_LEN_0,
1455 VEX_W_0F93_P_0_LEN_0,
1456 VEX_W_0F93_P_2_LEN_0,
1457 VEX_W_0F98_P_0_LEN_0,
1458 VEX_W_0F98_P_2_LEN_0,
1459 VEX_W_0F99_P_0_LEN_0,
1460 VEX_W_0F99_P_2_LEN_0,
1461 VEX_W_0F380C,
1462 VEX_W_0F380D,
1463 VEX_W_0F380E,
1464 VEX_W_0F380F,
1465 VEX_W_0F3813,
1466 VEX_W_0F3816_L_1,
1467 VEX_W_0F3818,
1468 VEX_W_0F3819_L_1,
1469 VEX_W_0F381A_M_0_L_1,
1470 VEX_W_0F382C_M_0,
1471 VEX_W_0F382D_M_0,
1472 VEX_W_0F382E_M_0,
1473 VEX_W_0F382F_M_0,
1474 VEX_W_0F3836,
1475 VEX_W_0F3846,
1476 VEX_W_0F3849_X86_64_P_0,
1477 VEX_W_0F3849_X86_64_P_2,
1478 VEX_W_0F3849_X86_64_P_3,
1479 VEX_W_0F384B_X86_64_P_1,
1480 VEX_W_0F384B_X86_64_P_2,
1481 VEX_W_0F384B_X86_64_P_3,
1482 VEX_W_0F3858,
1483 VEX_W_0F3859,
1484 VEX_W_0F385A_M_0_L_0,
1485 VEX_W_0F385C_X86_64_P_1,
1486 VEX_W_0F385E_X86_64_P_0,
1487 VEX_W_0F385E_X86_64_P_1,
1488 VEX_W_0F385E_X86_64_P_2,
1489 VEX_W_0F385E_X86_64_P_3,
1490 VEX_W_0F3878,
1491 VEX_W_0F3879,
1492 VEX_W_0F38CF,
1493 VEX_W_0F3A00_L_1,
1494 VEX_W_0F3A01_L_1,
1495 VEX_W_0F3A02,
1496 VEX_W_0F3A04,
1497 VEX_W_0F3A05,
1498 VEX_W_0F3A06_L_1,
1499 VEX_W_0F3A18_L_1,
1500 VEX_W_0F3A19_L_1,
1501 VEX_W_0F3A1D,
1502 VEX_W_0F3A38_L_1,
1503 VEX_W_0F3A39_L_1,
1504 VEX_W_0F3A46_L_1,
1505 VEX_W_0F3A4A,
1506 VEX_W_0F3A4B,
1507 VEX_W_0F3A4C,
1508 VEX_W_0F3ACE,
1509 VEX_W_0F3ACF,
1510
1511 VEX_W_0FXOP_08_85_L_0,
1512 VEX_W_0FXOP_08_86_L_0,
1513 VEX_W_0FXOP_08_87_L_0,
1514 VEX_W_0FXOP_08_8E_L_0,
1515 VEX_W_0FXOP_08_8F_L_0,
1516 VEX_W_0FXOP_08_95_L_0,
1517 VEX_W_0FXOP_08_96_L_0,
1518 VEX_W_0FXOP_08_97_L_0,
1519 VEX_W_0FXOP_08_9E_L_0,
1520 VEX_W_0FXOP_08_9F_L_0,
1521 VEX_W_0FXOP_08_A6_L_0,
1522 VEX_W_0FXOP_08_B6_L_0,
1523 VEX_W_0FXOP_08_C0_L_0,
1524 VEX_W_0FXOP_08_C1_L_0,
1525 VEX_W_0FXOP_08_C2_L_0,
1526 VEX_W_0FXOP_08_C3_L_0,
1527 VEX_W_0FXOP_08_CC_L_0,
1528 VEX_W_0FXOP_08_CD_L_0,
1529 VEX_W_0FXOP_08_CE_L_0,
1530 VEX_W_0FXOP_08_CF_L_0,
1531 VEX_W_0FXOP_08_EC_L_0,
1532 VEX_W_0FXOP_08_ED_L_0,
1533 VEX_W_0FXOP_08_EE_L_0,
1534 VEX_W_0FXOP_08_EF_L_0,
1535
1536 VEX_W_0FXOP_09_80,
1537 VEX_W_0FXOP_09_81,
1538 VEX_W_0FXOP_09_82,
1539 VEX_W_0FXOP_09_83,
1540 VEX_W_0FXOP_09_C1_L_0,
1541 VEX_W_0FXOP_09_C2_L_0,
1542 VEX_W_0FXOP_09_C3_L_0,
1543 VEX_W_0FXOP_09_C6_L_0,
1544 VEX_W_0FXOP_09_C7_L_0,
1545 VEX_W_0FXOP_09_CB_L_0,
1546 VEX_W_0FXOP_09_D1_L_0,
1547 VEX_W_0FXOP_09_D2_L_0,
1548 VEX_W_0FXOP_09_D3_L_0,
1549 VEX_W_0FXOP_09_D6_L_0,
1550 VEX_W_0FXOP_09_D7_L_0,
1551 VEX_W_0FXOP_09_DB_L_0,
1552 VEX_W_0FXOP_09_E1_L_0,
1553 VEX_W_0FXOP_09_E2_L_0,
1554 VEX_W_0FXOP_09_E3_L_0,
1555
1556 EVEX_W_0F10_P_1,
1557 EVEX_W_0F10_P_3,
1558 EVEX_W_0F11_P_1,
1559 EVEX_W_0F11_P_3,
1560 EVEX_W_0F12_P_0_M_1,
1561 EVEX_W_0F12_P_1,
1562 EVEX_W_0F12_P_3,
1563 EVEX_W_0F16_P_0_M_1,
1564 EVEX_W_0F16_P_1,
1565 EVEX_W_0F2A_P_3,
1566 EVEX_W_0F51_P_1,
1567 EVEX_W_0F51_P_3,
1568 EVEX_W_0F58_P_1,
1569 EVEX_W_0F58_P_3,
1570 EVEX_W_0F59_P_1,
1571 EVEX_W_0F59_P_3,
1572 EVEX_W_0F5A_P_0,
1573 EVEX_W_0F5A_P_1,
1574 EVEX_W_0F5A_P_2,
1575 EVEX_W_0F5A_P_3,
1576 EVEX_W_0F5B_P_0,
1577 EVEX_W_0F5B_P_1,
1578 EVEX_W_0F5B_P_2,
1579 EVEX_W_0F5C_P_1,
1580 EVEX_W_0F5C_P_3,
1581 EVEX_W_0F5D_P_1,
1582 EVEX_W_0F5D_P_3,
1583 EVEX_W_0F5E_P_1,
1584 EVEX_W_0F5E_P_3,
1585 EVEX_W_0F5F_P_1,
1586 EVEX_W_0F5F_P_3,
1587 EVEX_W_0F62,
1588 EVEX_W_0F66,
1589 EVEX_W_0F6A,
1590 EVEX_W_0F6B,
1591 EVEX_W_0F6C,
1592 EVEX_W_0F6D,
1593 EVEX_W_0F6F_P_1,
1594 EVEX_W_0F6F_P_2,
1595 EVEX_W_0F6F_P_3,
1596 EVEX_W_0F70_P_2,
1597 EVEX_W_0F72_R_2,
1598 EVEX_W_0F72_R_6,
1599 EVEX_W_0F73_R_2,
1600 EVEX_W_0F73_R_6,
1601 EVEX_W_0F76,
1602 EVEX_W_0F78_P_0,
1603 EVEX_W_0F78_P_2,
1604 EVEX_W_0F79_P_0,
1605 EVEX_W_0F79_P_2,
1606 EVEX_W_0F7A_P_1,
1607 EVEX_W_0F7A_P_2,
1608 EVEX_W_0F7A_P_3,
1609 EVEX_W_0F7B_P_2,
1610 EVEX_W_0F7B_P_3,
1611 EVEX_W_0F7E_P_1,
1612 EVEX_W_0F7F_P_1,
1613 EVEX_W_0F7F_P_2,
1614 EVEX_W_0F7F_P_3,
1615 EVEX_W_0FC2_P_1,
1616 EVEX_W_0FC2_P_3,
1617 EVEX_W_0FD2,
1618 EVEX_W_0FD3,
1619 EVEX_W_0FD4,
1620 EVEX_W_0FD6_L_0,
1621 EVEX_W_0FE6_P_1,
1622 EVEX_W_0FE6_P_2,
1623 EVEX_W_0FE6_P_3,
1624 EVEX_W_0FE7,
1625 EVEX_W_0FF2,
1626 EVEX_W_0FF3,
1627 EVEX_W_0FF4,
1628 EVEX_W_0FFA,
1629 EVEX_W_0FFB,
1630 EVEX_W_0FFE,
1631 EVEX_W_0F380D,
1632 EVEX_W_0F3810_P_1,
1633 EVEX_W_0F3810_P_2,
1634 EVEX_W_0F3811_P_1,
1635 EVEX_W_0F3811_P_2,
1636 EVEX_W_0F3812_P_1,
1637 EVEX_W_0F3812_P_2,
1638 EVEX_W_0F3813_P_1,
1639 EVEX_W_0F3813_P_2,
1640 EVEX_W_0F3814_P_1,
1641 EVEX_W_0F3815_P_1,
1642 EVEX_W_0F3819,
1643 EVEX_W_0F381A,
1644 EVEX_W_0F381B,
1645 EVEX_W_0F381E,
1646 EVEX_W_0F381F,
1647 EVEX_W_0F3820_P_1,
1648 EVEX_W_0F3821_P_1,
1649 EVEX_W_0F3822_P_1,
1650 EVEX_W_0F3823_P_1,
1651 EVEX_W_0F3824_P_1,
1652 EVEX_W_0F3825_P_1,
1653 EVEX_W_0F3825_P_2,
1654 EVEX_W_0F3828_P_2,
1655 EVEX_W_0F3829_P_2,
1656 EVEX_W_0F382A_P_1,
1657 EVEX_W_0F382A_P_2,
1658 EVEX_W_0F382B,
1659 EVEX_W_0F3830_P_1,
1660 EVEX_W_0F3831_P_1,
1661 EVEX_W_0F3832_P_1,
1662 EVEX_W_0F3833_P_1,
1663 EVEX_W_0F3834_P_1,
1664 EVEX_W_0F3835_P_1,
1665 EVEX_W_0F3835_P_2,
1666 EVEX_W_0F3837,
1667 EVEX_W_0F383A_P_1,
1668 EVEX_W_0F3852_P_1,
1669 EVEX_W_0F3859,
1670 EVEX_W_0F385A,
1671 EVEX_W_0F385B,
1672 EVEX_W_0F3870,
1673 EVEX_W_0F3872_P_1,
1674 EVEX_W_0F3872_P_2,
1675 EVEX_W_0F3872_P_3,
1676 EVEX_W_0F387A,
1677 EVEX_W_0F387B,
1678 EVEX_W_0F3883,
1679 EVEX_W_0F3891,
1680 EVEX_W_0F3893,
1681 EVEX_W_0F38A1,
1682 EVEX_W_0F38A3,
1683 EVEX_W_0F38C7_R_1_M_0,
1684 EVEX_W_0F38C7_R_2_M_0,
1685 EVEX_W_0F38C7_R_5_M_0,
1686 EVEX_W_0F38C7_R_6_M_0,
1687
1688 EVEX_W_0F3A00,
1689 EVEX_W_0F3A01,
1690 EVEX_W_0F3A05,
1691 EVEX_W_0F3A08,
1692 EVEX_W_0F3A09,
1693 EVEX_W_0F3A0A,
1694 EVEX_W_0F3A0B,
1695 EVEX_W_0F3A18,
1696 EVEX_W_0F3A19,
1697 EVEX_W_0F3A1A,
1698 EVEX_W_0F3A1B,
1699 EVEX_W_0F3A21,
1700 EVEX_W_0F3A23,
1701 EVEX_W_0F3A38,
1702 EVEX_W_0F3A39,
1703 EVEX_W_0F3A3A,
1704 EVEX_W_0F3A3B,
1705 EVEX_W_0F3A42,
1706 EVEX_W_0F3A43,
1707 EVEX_W_0F3A70,
1708 EVEX_W_0F3A72,
1709 };
1710
1711 typedef void (*op_rtn) (int bytemode, int sizeflag);
1712
1713 struct dis386 {
1714 const char *name;
1715 struct
1716 {
1717 op_rtn rtn;
1718 int bytemode;
1719 } op[MAX_OPERANDS];
1720 unsigned int prefix_requirement;
1721 };
1722
1723 /* Upper case letters in the instruction names here are macros.
1724 'A' => print 'b' if no register operands or suffix_always is true
1725 'B' => print 'b' if suffix_always is true
1726 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1727 size prefix
1728 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1729 suffix_always is true
1730 'E' => print 'e' if 32-bit form of jcxz
1731 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1732 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1733 'H' => print ",pt" or ",pn" branch hint
1734 'I' unused.
1735 'J' unused.
1736 'K' => print 'd' or 'q' if rex prefix is present.
1737 'L' unused.
1738 'M' => print 'r' if intel_mnemonic is false.
1739 'N' => print 'n' if instruction has no wait "prefix"
1740 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1741 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1742 or suffix_always is true. print 'q' if rex prefix is present.
1743 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1744 is true
1745 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1746 'S' => print 'w', 'l' or 'q' if suffix_always is true
1747 'T' => print 'q' in 64bit mode if instruction has no operand size
1748 prefix and behave as 'P' otherwise
1749 'U' => print 'q' in 64bit mode if instruction has no operand size
1750 prefix and behave as 'Q' otherwise
1751 'V' => print 'q' in 64bit mode if instruction has no operand size
1752 prefix and behave as 'S' otherwise
1753 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1754 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1755 'Y' unused.
1756 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1757 '!' => change condition from true to false or from false to true.
1758 '%' => add 1 upper case letter to the macro.
1759 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1760 prefix or suffix_always is true (lcall/ljmp).
1761 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
1762 on operand size prefix.
1763 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
1764 has no operand size prefix for AMD64 ISA, behave as 'P'
1765 otherwise
1766
1767 2 upper case letter macros:
1768 "XY" => print 'x' or 'y' if suffix_always is true or no register
1769 operands and no broadcast.
1770 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1771 register operands and no broadcast.
1772 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1773 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1774 being false, or no operand at all in 64bit mode, or if suffix_always
1775 is true.
1776 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1777 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1778 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1779 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1780 "BW" => print 'b' or 'w' depending on the VEX.W bit
1781 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1782 an operand size prefix, or suffix_always is true. print
1783 'q' if rex prefix is present.
1784
1785 Many of the above letters print nothing in Intel mode. See "putop"
1786 for the details.
1787
1788 Braces '{' and '}', and vertical bars '|', indicate alternative
1789 mnemonic strings for AT&T and Intel. */
1790
1791 static const struct dis386 dis386[] = {
1792 /* 00 */
1793 { "addB", { Ebh1, Gb }, 0 },
1794 { "addS", { Evh1, Gv }, 0 },
1795 { "addB", { Gb, EbS }, 0 },
1796 { "addS", { Gv, EvS }, 0 },
1797 { "addB", { AL, Ib }, 0 },
1798 { "addS", { eAX, Iv }, 0 },
1799 { X86_64_TABLE (X86_64_06) },
1800 { X86_64_TABLE (X86_64_07) },
1801 /* 08 */
1802 { "orB", { Ebh1, Gb }, 0 },
1803 { "orS", { Evh1, Gv }, 0 },
1804 { "orB", { Gb, EbS }, 0 },
1805 { "orS", { Gv, EvS }, 0 },
1806 { "orB", { AL, Ib }, 0 },
1807 { "orS", { eAX, Iv }, 0 },
1808 { X86_64_TABLE (X86_64_0E) },
1809 { Bad_Opcode }, /* 0x0f extended opcode escape */
1810 /* 10 */
1811 { "adcB", { Ebh1, Gb }, 0 },
1812 { "adcS", { Evh1, Gv }, 0 },
1813 { "adcB", { Gb, EbS }, 0 },
1814 { "adcS", { Gv, EvS }, 0 },
1815 { "adcB", { AL, Ib }, 0 },
1816 { "adcS", { eAX, Iv }, 0 },
1817 { X86_64_TABLE (X86_64_16) },
1818 { X86_64_TABLE (X86_64_17) },
1819 /* 18 */
1820 { "sbbB", { Ebh1, Gb }, 0 },
1821 { "sbbS", { Evh1, Gv }, 0 },
1822 { "sbbB", { Gb, EbS }, 0 },
1823 { "sbbS", { Gv, EvS }, 0 },
1824 { "sbbB", { AL, Ib }, 0 },
1825 { "sbbS", { eAX, Iv }, 0 },
1826 { X86_64_TABLE (X86_64_1E) },
1827 { X86_64_TABLE (X86_64_1F) },
1828 /* 20 */
1829 { "andB", { Ebh1, Gb }, 0 },
1830 { "andS", { Evh1, Gv }, 0 },
1831 { "andB", { Gb, EbS }, 0 },
1832 { "andS", { Gv, EvS }, 0 },
1833 { "andB", { AL, Ib }, 0 },
1834 { "andS", { eAX, Iv }, 0 },
1835 { Bad_Opcode }, /* SEG ES prefix */
1836 { X86_64_TABLE (X86_64_27) },
1837 /* 28 */
1838 { "subB", { Ebh1, Gb }, 0 },
1839 { "subS", { Evh1, Gv }, 0 },
1840 { "subB", { Gb, EbS }, 0 },
1841 { "subS", { Gv, EvS }, 0 },
1842 { "subB", { AL, Ib }, 0 },
1843 { "subS", { eAX, Iv }, 0 },
1844 { Bad_Opcode }, /* SEG CS prefix */
1845 { X86_64_TABLE (X86_64_2F) },
1846 /* 30 */
1847 { "xorB", { Ebh1, Gb }, 0 },
1848 { "xorS", { Evh1, Gv }, 0 },
1849 { "xorB", { Gb, EbS }, 0 },
1850 { "xorS", { Gv, EvS }, 0 },
1851 { "xorB", { AL, Ib }, 0 },
1852 { "xorS", { eAX, Iv }, 0 },
1853 { Bad_Opcode }, /* SEG SS prefix */
1854 { X86_64_TABLE (X86_64_37) },
1855 /* 38 */
1856 { "cmpB", { Eb, Gb }, 0 },
1857 { "cmpS", { Ev, Gv }, 0 },
1858 { "cmpB", { Gb, EbS }, 0 },
1859 { "cmpS", { Gv, EvS }, 0 },
1860 { "cmpB", { AL, Ib }, 0 },
1861 { "cmpS", { eAX, Iv }, 0 },
1862 { Bad_Opcode }, /* SEG DS prefix */
1863 { X86_64_TABLE (X86_64_3F) },
1864 /* 40 */
1865 { "inc{S|}", { RMeAX }, 0 },
1866 { "inc{S|}", { RMeCX }, 0 },
1867 { "inc{S|}", { RMeDX }, 0 },
1868 { "inc{S|}", { RMeBX }, 0 },
1869 { "inc{S|}", { RMeSP }, 0 },
1870 { "inc{S|}", { RMeBP }, 0 },
1871 { "inc{S|}", { RMeSI }, 0 },
1872 { "inc{S|}", { RMeDI }, 0 },
1873 /* 48 */
1874 { "dec{S|}", { RMeAX }, 0 },
1875 { "dec{S|}", { RMeCX }, 0 },
1876 { "dec{S|}", { RMeDX }, 0 },
1877 { "dec{S|}", { RMeBX }, 0 },
1878 { "dec{S|}", { RMeSP }, 0 },
1879 { "dec{S|}", { RMeBP }, 0 },
1880 { "dec{S|}", { RMeSI }, 0 },
1881 { "dec{S|}", { RMeDI }, 0 },
1882 /* 50 */
1883 { "pushV", { RMrAX }, 0 },
1884 { "pushV", { RMrCX }, 0 },
1885 { "pushV", { RMrDX }, 0 },
1886 { "pushV", { RMrBX }, 0 },
1887 { "pushV", { RMrSP }, 0 },
1888 { "pushV", { RMrBP }, 0 },
1889 { "pushV", { RMrSI }, 0 },
1890 { "pushV", { RMrDI }, 0 },
1891 /* 58 */
1892 { "popV", { RMrAX }, 0 },
1893 { "popV", { RMrCX }, 0 },
1894 { "popV", { RMrDX }, 0 },
1895 { "popV", { RMrBX }, 0 },
1896 { "popV", { RMrSP }, 0 },
1897 { "popV", { RMrBP }, 0 },
1898 { "popV", { RMrSI }, 0 },
1899 { "popV", { RMrDI }, 0 },
1900 /* 60 */
1901 { X86_64_TABLE (X86_64_60) },
1902 { X86_64_TABLE (X86_64_61) },
1903 { X86_64_TABLE (X86_64_62) },
1904 { X86_64_TABLE (X86_64_63) },
1905 { Bad_Opcode }, /* seg fs */
1906 { Bad_Opcode }, /* seg gs */
1907 { Bad_Opcode }, /* op size prefix */
1908 { Bad_Opcode }, /* adr size prefix */
1909 /* 68 */
1910 { "pushT", { sIv }, 0 },
1911 { "imulS", { Gv, Ev, Iv }, 0 },
1912 { "pushT", { sIbT }, 0 },
1913 { "imulS", { Gv, Ev, sIb }, 0 },
1914 { "ins{b|}", { Ybr, indirDX }, 0 },
1915 { X86_64_TABLE (X86_64_6D) },
1916 { "outs{b|}", { indirDXr, Xb }, 0 },
1917 { X86_64_TABLE (X86_64_6F) },
1918 /* 70 */
1919 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1920 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1921 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1922 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1923 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1924 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1925 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1926 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1927 /* 78 */
1928 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1929 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1930 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1931 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1932 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1933 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1934 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1935 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1936 /* 80 */
1937 { REG_TABLE (REG_80) },
1938 { REG_TABLE (REG_81) },
1939 { X86_64_TABLE (X86_64_82) },
1940 { REG_TABLE (REG_83) },
1941 { "testB", { Eb, Gb }, 0 },
1942 { "testS", { Ev, Gv }, 0 },
1943 { "xchgB", { Ebh2, Gb }, 0 },
1944 { "xchgS", { Evh2, Gv }, 0 },
1945 /* 88 */
1946 { "movB", { Ebh3, Gb }, 0 },
1947 { "movS", { Evh3, Gv }, 0 },
1948 { "movB", { Gb, EbS }, 0 },
1949 { "movS", { Gv, EvS }, 0 },
1950 { "movD", { Sv, Sw }, 0 },
1951 { MOD_TABLE (MOD_8D) },
1952 { "movD", { Sw, Sv }, 0 },
1953 { REG_TABLE (REG_8F) },
1954 /* 90 */
1955 { PREFIX_TABLE (PREFIX_90) },
1956 { "xchgS", { RMeCX, eAX }, 0 },
1957 { "xchgS", { RMeDX, eAX }, 0 },
1958 { "xchgS", { RMeBX, eAX }, 0 },
1959 { "xchgS", { RMeSP, eAX }, 0 },
1960 { "xchgS", { RMeBP, eAX }, 0 },
1961 { "xchgS", { RMeSI, eAX }, 0 },
1962 { "xchgS", { RMeDI, eAX }, 0 },
1963 /* 98 */
1964 { "cW{t|}R", { XX }, 0 },
1965 { "cR{t|}O", { XX }, 0 },
1966 { X86_64_TABLE (X86_64_9A) },
1967 { Bad_Opcode }, /* fwait */
1968 { "pushfT", { XX }, 0 },
1969 { "popfT", { XX }, 0 },
1970 { "sahf", { XX }, 0 },
1971 { "lahf", { XX }, 0 },
1972 /* a0 */
1973 { "mov%LB", { AL, Ob }, 0 },
1974 { "mov%LS", { eAX, Ov }, 0 },
1975 { "mov%LB", { Ob, AL }, 0 },
1976 { "mov%LS", { Ov, eAX }, 0 },
1977 { "movs{b|}", { Ybr, Xb }, 0 },
1978 { "movs{R|}", { Yvr, Xv }, 0 },
1979 { "cmps{b|}", { Xb, Yb }, 0 },
1980 { "cmps{R|}", { Xv, Yv }, 0 },
1981 /* a8 */
1982 { "testB", { AL, Ib }, 0 },
1983 { "testS", { eAX, Iv }, 0 },
1984 { "stosB", { Ybr, AL }, 0 },
1985 { "stosS", { Yvr, eAX }, 0 },
1986 { "lodsB", { ALr, Xb }, 0 },
1987 { "lodsS", { eAXr, Xv }, 0 },
1988 { "scasB", { AL, Yb }, 0 },
1989 { "scasS", { eAX, Yv }, 0 },
1990 /* b0 */
1991 { "movB", { RMAL, Ib }, 0 },
1992 { "movB", { RMCL, Ib }, 0 },
1993 { "movB", { RMDL, Ib }, 0 },
1994 { "movB", { RMBL, Ib }, 0 },
1995 { "movB", { RMAH, Ib }, 0 },
1996 { "movB", { RMCH, Ib }, 0 },
1997 { "movB", { RMDH, Ib }, 0 },
1998 { "movB", { RMBH, Ib }, 0 },
1999 /* b8 */
2000 { "mov%LV", { RMeAX, Iv64 }, 0 },
2001 { "mov%LV", { RMeCX, Iv64 }, 0 },
2002 { "mov%LV", { RMeDX, Iv64 }, 0 },
2003 { "mov%LV", { RMeBX, Iv64 }, 0 },
2004 { "mov%LV", { RMeSP, Iv64 }, 0 },
2005 { "mov%LV", { RMeBP, Iv64 }, 0 },
2006 { "mov%LV", { RMeSI, Iv64 }, 0 },
2007 { "mov%LV", { RMeDI, Iv64 }, 0 },
2008 /* c0 */
2009 { REG_TABLE (REG_C0) },
2010 { REG_TABLE (REG_C1) },
2011 { X86_64_TABLE (X86_64_C2) },
2012 { X86_64_TABLE (X86_64_C3) },
2013 { X86_64_TABLE (X86_64_C4) },
2014 { X86_64_TABLE (X86_64_C5) },
2015 { REG_TABLE (REG_C6) },
2016 { REG_TABLE (REG_C7) },
2017 /* c8 */
2018 { "enterT", { Iw, Ib }, 0 },
2019 { "leaveT", { XX }, 0 },
2020 { "{l|}ret{|f}P", { Iw }, 0 },
2021 { "{l|}ret{|f}P", { XX }, 0 },
2022 { "int3", { XX }, 0 },
2023 { "int", { Ib }, 0 },
2024 { X86_64_TABLE (X86_64_CE) },
2025 { "iret%LP", { XX }, 0 },
2026 /* d0 */
2027 { REG_TABLE (REG_D0) },
2028 { REG_TABLE (REG_D1) },
2029 { REG_TABLE (REG_D2) },
2030 { REG_TABLE (REG_D3) },
2031 { X86_64_TABLE (X86_64_D4) },
2032 { X86_64_TABLE (X86_64_D5) },
2033 { Bad_Opcode },
2034 { "xlat", { DSBX }, 0 },
2035 /* d8 */
2036 { FLOAT },
2037 { FLOAT },
2038 { FLOAT },
2039 { FLOAT },
2040 { FLOAT },
2041 { FLOAT },
2042 { FLOAT },
2043 { FLOAT },
2044 /* e0 */
2045 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2046 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2047 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2048 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2049 { "inB", { AL, Ib }, 0 },
2050 { "inG", { zAX, Ib }, 0 },
2051 { "outB", { Ib, AL }, 0 },
2052 { "outG", { Ib, zAX }, 0 },
2053 /* e8 */
2054 { X86_64_TABLE (X86_64_E8) },
2055 { X86_64_TABLE (X86_64_E9) },
2056 { X86_64_TABLE (X86_64_EA) },
2057 { "jmp", { Jb, BND }, 0 },
2058 { "inB", { AL, indirDX }, 0 },
2059 { "inG", { zAX, indirDX }, 0 },
2060 { "outB", { indirDX, AL }, 0 },
2061 { "outG", { indirDX, zAX }, 0 },
2062 /* f0 */
2063 { Bad_Opcode }, /* lock prefix */
2064 { "icebp", { XX }, 0 },
2065 { Bad_Opcode }, /* repne */
2066 { Bad_Opcode }, /* repz */
2067 { "hlt", { XX }, 0 },
2068 { "cmc", { XX }, 0 },
2069 { REG_TABLE (REG_F6) },
2070 { REG_TABLE (REG_F7) },
2071 /* f8 */
2072 { "clc", { XX }, 0 },
2073 { "stc", { XX }, 0 },
2074 { "cli", { XX }, 0 },
2075 { "sti", { XX }, 0 },
2076 { "cld", { XX }, 0 },
2077 { "std", { XX }, 0 },
2078 { REG_TABLE (REG_FE) },
2079 { REG_TABLE (REG_FF) },
2080 };
2081
2082 static const struct dis386 dis386_twobyte[] = {
2083 /* 00 */
2084 { REG_TABLE (REG_0F00 ) },
2085 { REG_TABLE (REG_0F01 ) },
2086 { "larS", { Gv, Ew }, 0 },
2087 { "lslS", { Gv, Ew }, 0 },
2088 { Bad_Opcode },
2089 { "syscall", { XX }, 0 },
2090 { "clts", { XX }, 0 },
2091 { "sysret%LQ", { XX }, 0 },
2092 /* 08 */
2093 { "invd", { XX }, 0 },
2094 { PREFIX_TABLE (PREFIX_0F09) },
2095 { Bad_Opcode },
2096 { "ud2", { XX }, 0 },
2097 { Bad_Opcode },
2098 { REG_TABLE (REG_0F0D) },
2099 { "femms", { XX }, 0 },
2100 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2101 /* 10 */
2102 { PREFIX_TABLE (PREFIX_0F10) },
2103 { PREFIX_TABLE (PREFIX_0F11) },
2104 { PREFIX_TABLE (PREFIX_0F12) },
2105 { MOD_TABLE (MOD_0F13) },
2106 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2107 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2108 { PREFIX_TABLE (PREFIX_0F16) },
2109 { MOD_TABLE (MOD_0F17) },
2110 /* 18 */
2111 { REG_TABLE (REG_0F18) },
2112 { "nopQ", { Ev }, 0 },
2113 { PREFIX_TABLE (PREFIX_0F1A) },
2114 { PREFIX_TABLE (PREFIX_0F1B) },
2115 { PREFIX_TABLE (PREFIX_0F1C) },
2116 { "nopQ", { Ev }, 0 },
2117 { PREFIX_TABLE (PREFIX_0F1E) },
2118 { "nopQ", { Ev }, 0 },
2119 /* 20 */
2120 { "movZ", { Em, Cm }, 0 },
2121 { "movZ", { Em, Dm }, 0 },
2122 { "movZ", { Cm, Em }, 0 },
2123 { "movZ", { Dm, Em }, 0 },
2124 { X86_64_TABLE (X86_64_0F24) },
2125 { Bad_Opcode },
2126 { X86_64_TABLE (X86_64_0F26) },
2127 { Bad_Opcode },
2128 /* 28 */
2129 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2130 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2131 { PREFIX_TABLE (PREFIX_0F2A) },
2132 { PREFIX_TABLE (PREFIX_0F2B) },
2133 { PREFIX_TABLE (PREFIX_0F2C) },
2134 { PREFIX_TABLE (PREFIX_0F2D) },
2135 { PREFIX_TABLE (PREFIX_0F2E) },
2136 { PREFIX_TABLE (PREFIX_0F2F) },
2137 /* 30 */
2138 { "wrmsr", { XX }, 0 },
2139 { "rdtsc", { XX }, 0 },
2140 { "rdmsr", { XX }, 0 },
2141 { "rdpmc", { XX }, 0 },
2142 { "sysenter", { SEP }, 0 },
2143 { "sysexit", { SEP }, 0 },
2144 { Bad_Opcode },
2145 { "getsec", { XX }, 0 },
2146 /* 38 */
2147 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2148 { Bad_Opcode },
2149 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2150 { Bad_Opcode },
2151 { Bad_Opcode },
2152 { Bad_Opcode },
2153 { Bad_Opcode },
2154 { Bad_Opcode },
2155 /* 40 */
2156 { "cmovoS", { Gv, Ev }, 0 },
2157 { "cmovnoS", { Gv, Ev }, 0 },
2158 { "cmovbS", { Gv, Ev }, 0 },
2159 { "cmovaeS", { Gv, Ev }, 0 },
2160 { "cmoveS", { Gv, Ev }, 0 },
2161 { "cmovneS", { Gv, Ev }, 0 },
2162 { "cmovbeS", { Gv, Ev }, 0 },
2163 { "cmovaS", { Gv, Ev }, 0 },
2164 /* 48 */
2165 { "cmovsS", { Gv, Ev }, 0 },
2166 { "cmovnsS", { Gv, Ev }, 0 },
2167 { "cmovpS", { Gv, Ev }, 0 },
2168 { "cmovnpS", { Gv, Ev }, 0 },
2169 { "cmovlS", { Gv, Ev }, 0 },
2170 { "cmovgeS", { Gv, Ev }, 0 },
2171 { "cmovleS", { Gv, Ev }, 0 },
2172 { "cmovgS", { Gv, Ev }, 0 },
2173 /* 50 */
2174 { MOD_TABLE (MOD_0F50) },
2175 { PREFIX_TABLE (PREFIX_0F51) },
2176 { PREFIX_TABLE (PREFIX_0F52) },
2177 { PREFIX_TABLE (PREFIX_0F53) },
2178 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2179 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2180 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2181 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2182 /* 58 */
2183 { PREFIX_TABLE (PREFIX_0F58) },
2184 { PREFIX_TABLE (PREFIX_0F59) },
2185 { PREFIX_TABLE (PREFIX_0F5A) },
2186 { PREFIX_TABLE (PREFIX_0F5B) },
2187 { PREFIX_TABLE (PREFIX_0F5C) },
2188 { PREFIX_TABLE (PREFIX_0F5D) },
2189 { PREFIX_TABLE (PREFIX_0F5E) },
2190 { PREFIX_TABLE (PREFIX_0F5F) },
2191 /* 60 */
2192 { PREFIX_TABLE (PREFIX_0F60) },
2193 { PREFIX_TABLE (PREFIX_0F61) },
2194 { PREFIX_TABLE (PREFIX_0F62) },
2195 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2196 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2197 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2198 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2199 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2200 /* 68 */
2201 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2202 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2203 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2204 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2205 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2206 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2207 { "movK", { MX, Edq }, PREFIX_OPCODE },
2208 { PREFIX_TABLE (PREFIX_0F6F) },
2209 /* 70 */
2210 { PREFIX_TABLE (PREFIX_0F70) },
2211 { REG_TABLE (REG_0F71) },
2212 { REG_TABLE (REG_0F72) },
2213 { REG_TABLE (REG_0F73) },
2214 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2215 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2216 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2217 { "emms", { XX }, PREFIX_OPCODE },
2218 /* 78 */
2219 { PREFIX_TABLE (PREFIX_0F78) },
2220 { PREFIX_TABLE (PREFIX_0F79) },
2221 { Bad_Opcode },
2222 { Bad_Opcode },
2223 { PREFIX_TABLE (PREFIX_0F7C) },
2224 { PREFIX_TABLE (PREFIX_0F7D) },
2225 { PREFIX_TABLE (PREFIX_0F7E) },
2226 { PREFIX_TABLE (PREFIX_0F7F) },
2227 /* 80 */
2228 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2229 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2230 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2231 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2232 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2233 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2234 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2235 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2236 /* 88 */
2237 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2238 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2239 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2240 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2241 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2242 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2243 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2244 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2245 /* 90 */
2246 { "seto", { Eb }, 0 },
2247 { "setno", { Eb }, 0 },
2248 { "setb", { Eb }, 0 },
2249 { "setae", { Eb }, 0 },
2250 { "sete", { Eb }, 0 },
2251 { "setne", { Eb }, 0 },
2252 { "setbe", { Eb }, 0 },
2253 { "seta", { Eb }, 0 },
2254 /* 98 */
2255 { "sets", { Eb }, 0 },
2256 { "setns", { Eb }, 0 },
2257 { "setp", { Eb }, 0 },
2258 { "setnp", { Eb }, 0 },
2259 { "setl", { Eb }, 0 },
2260 { "setge", { Eb }, 0 },
2261 { "setle", { Eb }, 0 },
2262 { "setg", { Eb }, 0 },
2263 /* a0 */
2264 { "pushT", { fs }, 0 },
2265 { "popT", { fs }, 0 },
2266 { "cpuid", { XX }, 0 },
2267 { "btS", { Ev, Gv }, 0 },
2268 { "shldS", { Ev, Gv, Ib }, 0 },
2269 { "shldS", { Ev, Gv, CL }, 0 },
2270 { REG_TABLE (REG_0FA6) },
2271 { REG_TABLE (REG_0FA7) },
2272 /* a8 */
2273 { "pushT", { gs }, 0 },
2274 { "popT", { gs }, 0 },
2275 { "rsm", { XX }, 0 },
2276 { "btsS", { Evh1, Gv }, 0 },
2277 { "shrdS", { Ev, Gv, Ib }, 0 },
2278 { "shrdS", { Ev, Gv, CL }, 0 },
2279 { REG_TABLE (REG_0FAE) },
2280 { "imulS", { Gv, Ev }, 0 },
2281 /* b0 */
2282 { "cmpxchgB", { Ebh1, Gb }, 0 },
2283 { "cmpxchgS", { Evh1, Gv }, 0 },
2284 { MOD_TABLE (MOD_0FB2) },
2285 { "btrS", { Evh1, Gv }, 0 },
2286 { MOD_TABLE (MOD_0FB4) },
2287 { MOD_TABLE (MOD_0FB5) },
2288 { "movz{bR|x}", { Gv, Eb }, 0 },
2289 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2290 /* b8 */
2291 { PREFIX_TABLE (PREFIX_0FB8) },
2292 { "ud1S", { Gv, Ev }, 0 },
2293 { REG_TABLE (REG_0FBA) },
2294 { "btcS", { Evh1, Gv }, 0 },
2295 { PREFIX_TABLE (PREFIX_0FBC) },
2296 { PREFIX_TABLE (PREFIX_0FBD) },
2297 { "movs{bR|x}", { Gv, Eb }, 0 },
2298 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2299 /* c0 */
2300 { "xaddB", { Ebh1, Gb }, 0 },
2301 { "xaddS", { Evh1, Gv }, 0 },
2302 { PREFIX_TABLE (PREFIX_0FC2) },
2303 { MOD_TABLE (MOD_0FC3) },
2304 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2305 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2306 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2307 { REG_TABLE (REG_0FC7) },
2308 /* c8 */
2309 { "bswap", { RMeAX }, 0 },
2310 { "bswap", { RMeCX }, 0 },
2311 { "bswap", { RMeDX }, 0 },
2312 { "bswap", { RMeBX }, 0 },
2313 { "bswap", { RMeSP }, 0 },
2314 { "bswap", { RMeBP }, 0 },
2315 { "bswap", { RMeSI }, 0 },
2316 { "bswap", { RMeDI }, 0 },
2317 /* d0 */
2318 { PREFIX_TABLE (PREFIX_0FD0) },
2319 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2320 { "psrld", { MX, EM }, PREFIX_OPCODE },
2321 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2322 { "paddq", { MX, EM }, PREFIX_OPCODE },
2323 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2324 { PREFIX_TABLE (PREFIX_0FD6) },
2325 { MOD_TABLE (MOD_0FD7) },
2326 /* d8 */
2327 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2328 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2329 { "pminub", { MX, EM }, PREFIX_OPCODE },
2330 { "pand", { MX, EM }, PREFIX_OPCODE },
2331 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2332 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2333 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2334 { "pandn", { MX, EM }, PREFIX_OPCODE },
2335 /* e0 */
2336 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2337 { "psraw", { MX, EM }, PREFIX_OPCODE },
2338 { "psrad", { MX, EM }, PREFIX_OPCODE },
2339 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2340 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2341 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2342 { PREFIX_TABLE (PREFIX_0FE6) },
2343 { PREFIX_TABLE (PREFIX_0FE7) },
2344 /* e8 */
2345 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2346 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2347 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2348 { "por", { MX, EM }, PREFIX_OPCODE },
2349 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2350 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2351 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2352 { "pxor", { MX, EM }, PREFIX_OPCODE },
2353 /* f0 */
2354 { PREFIX_TABLE (PREFIX_0FF0) },
2355 { "psllw", { MX, EM }, PREFIX_OPCODE },
2356 { "pslld", { MX, EM }, PREFIX_OPCODE },
2357 { "psllq", { MX, EM }, PREFIX_OPCODE },
2358 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2359 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2360 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2361 { PREFIX_TABLE (PREFIX_0FF7) },
2362 /* f8 */
2363 { "psubb", { MX, EM }, PREFIX_OPCODE },
2364 { "psubw", { MX, EM }, PREFIX_OPCODE },
2365 { "psubd", { MX, EM }, PREFIX_OPCODE },
2366 { "psubq", { MX, EM }, PREFIX_OPCODE },
2367 { "paddb", { MX, EM }, PREFIX_OPCODE },
2368 { "paddw", { MX, EM }, PREFIX_OPCODE },
2369 { "paddd", { MX, EM }, PREFIX_OPCODE },
2370 { "ud0S", { Gv, Ev }, 0 },
2371 };
2372
2373 static const unsigned char onebyte_has_modrm[256] = {
2374 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2375 /* ------------------------------- */
2376 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2377 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2378 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2379 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2380 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2381 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2382 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2383 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2384 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2385 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2386 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2387 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2388 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2389 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2390 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2391 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2392 /* ------------------------------- */
2393 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2394 };
2395
2396 static const unsigned char twobyte_has_modrm[256] = {
2397 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2398 /* ------------------------------- */
2399 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2400 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2401 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2402 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2403 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2404 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2405 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2406 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2407 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2408 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2409 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2410 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2411 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2412 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2413 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2414 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2415 /* ------------------------------- */
2416 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2417 };
2418
2419 static char obuf[100];
2420 static char *obufp;
2421 static char *mnemonicendp;
2422 static char scratchbuf[100];
2423 static unsigned char *start_codep;
2424 static unsigned char *insn_codep;
2425 static unsigned char *codep;
2426 static unsigned char *end_codep;
2427 static int last_lock_prefix;
2428 static int last_repz_prefix;
2429 static int last_repnz_prefix;
2430 static int last_data_prefix;
2431 static int last_addr_prefix;
2432 static int last_rex_prefix;
2433 static int last_seg_prefix;
2434 static int fwait_prefix;
2435 /* The active segment register prefix. */
2436 static int active_seg_prefix;
2437 #define MAX_CODE_LENGTH 15
2438 /* We can up to 14 prefixes since the maximum instruction length is
2439 15bytes. */
2440 static int all_prefixes[MAX_CODE_LENGTH - 1];
2441 static disassemble_info *the_info;
2442 static struct
2443 {
2444 int mod;
2445 int reg;
2446 int rm;
2447 }
2448 modrm;
2449 static unsigned char need_modrm;
2450 static struct
2451 {
2452 int scale;
2453 int index;
2454 int base;
2455 }
2456 sib;
2457 static struct
2458 {
2459 int register_specifier;
2460 int length;
2461 int prefix;
2462 int w;
2463 int evex;
2464 int r;
2465 int v;
2466 int mask_register_specifier;
2467 int zeroing;
2468 int ll;
2469 int b;
2470 }
2471 vex;
2472 static unsigned char need_vex;
2473
2474 struct op
2475 {
2476 const char *name;
2477 unsigned int len;
2478 };
2479
2480 /* If we are accessing mod/rm/reg without need_modrm set, then the
2481 values are stale. Hitting this abort likely indicates that you
2482 need to update onebyte_has_modrm or twobyte_has_modrm. */
2483 #define MODRM_CHECK if (!need_modrm) abort ()
2484
2485 static const char **names64;
2486 static const char **names32;
2487 static const char **names16;
2488 static const char **names8;
2489 static const char **names8rex;
2490 static const char **names_seg;
2491 static const char *index64;
2492 static const char *index32;
2493 static const char **index16;
2494 static const char **names_bnd;
2495
2496 static const char *intel_names64[] = {
2497 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2498 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2499 };
2500 static const char *intel_names32[] = {
2501 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2502 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2503 };
2504 static const char *intel_names16[] = {
2505 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2506 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2507 };
2508 static const char *intel_names8[] = {
2509 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2510 };
2511 static const char *intel_names8rex[] = {
2512 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2513 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2514 };
2515 static const char *intel_names_seg[] = {
2516 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2517 };
2518 static const char *intel_index64 = "riz";
2519 static const char *intel_index32 = "eiz";
2520 static const char *intel_index16[] = {
2521 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2522 };
2523
2524 static const char *att_names64[] = {
2525 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2526 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2527 };
2528 static const char *att_names32[] = {
2529 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2530 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2531 };
2532 static const char *att_names16[] = {
2533 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2534 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2535 };
2536 static const char *att_names8[] = {
2537 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2538 };
2539 static const char *att_names8rex[] = {
2540 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2541 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2542 };
2543 static const char *att_names_seg[] = {
2544 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2545 };
2546 static const char *att_index64 = "%riz";
2547 static const char *att_index32 = "%eiz";
2548 static const char *att_index16[] = {
2549 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2550 };
2551
2552 static const char **names_mm;
2553 static const char *intel_names_mm[] = {
2554 "mm0", "mm1", "mm2", "mm3",
2555 "mm4", "mm5", "mm6", "mm7"
2556 };
2557 static const char *att_names_mm[] = {
2558 "%mm0", "%mm1", "%mm2", "%mm3",
2559 "%mm4", "%mm5", "%mm6", "%mm7"
2560 };
2561
2562 static const char *intel_names_bnd[] = {
2563 "bnd0", "bnd1", "bnd2", "bnd3"
2564 };
2565
2566 static const char *att_names_bnd[] = {
2567 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2568 };
2569
2570 static const char **names_xmm;
2571 static const char *intel_names_xmm[] = {
2572 "xmm0", "xmm1", "xmm2", "xmm3",
2573 "xmm4", "xmm5", "xmm6", "xmm7",
2574 "xmm8", "xmm9", "xmm10", "xmm11",
2575 "xmm12", "xmm13", "xmm14", "xmm15",
2576 "xmm16", "xmm17", "xmm18", "xmm19",
2577 "xmm20", "xmm21", "xmm22", "xmm23",
2578 "xmm24", "xmm25", "xmm26", "xmm27",
2579 "xmm28", "xmm29", "xmm30", "xmm31"
2580 };
2581 static const char *att_names_xmm[] = {
2582 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2583 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2584 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2585 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2586 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2587 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2588 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2589 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2590 };
2591
2592 static const char **names_ymm;
2593 static const char *intel_names_ymm[] = {
2594 "ymm0", "ymm1", "ymm2", "ymm3",
2595 "ymm4", "ymm5", "ymm6", "ymm7",
2596 "ymm8", "ymm9", "ymm10", "ymm11",
2597 "ymm12", "ymm13", "ymm14", "ymm15",
2598 "ymm16", "ymm17", "ymm18", "ymm19",
2599 "ymm20", "ymm21", "ymm22", "ymm23",
2600 "ymm24", "ymm25", "ymm26", "ymm27",
2601 "ymm28", "ymm29", "ymm30", "ymm31"
2602 };
2603 static const char *att_names_ymm[] = {
2604 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2605 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2606 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2607 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2608 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2609 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2610 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2611 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2612 };
2613
2614 static const char **names_zmm;
2615 static const char *intel_names_zmm[] = {
2616 "zmm0", "zmm1", "zmm2", "zmm3",
2617 "zmm4", "zmm5", "zmm6", "zmm7",
2618 "zmm8", "zmm9", "zmm10", "zmm11",
2619 "zmm12", "zmm13", "zmm14", "zmm15",
2620 "zmm16", "zmm17", "zmm18", "zmm19",
2621 "zmm20", "zmm21", "zmm22", "zmm23",
2622 "zmm24", "zmm25", "zmm26", "zmm27",
2623 "zmm28", "zmm29", "zmm30", "zmm31"
2624 };
2625 static const char *att_names_zmm[] = {
2626 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2627 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2628 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2629 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2630 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2631 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2632 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2633 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2634 };
2635
2636 static const char **names_tmm;
2637 static const char *intel_names_tmm[] = {
2638 "tmm0", "tmm1", "tmm2", "tmm3",
2639 "tmm4", "tmm5", "tmm6", "tmm7"
2640 };
2641 static const char *att_names_tmm[] = {
2642 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2643 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2644 };
2645
2646 static const char **names_mask;
2647 static const char *intel_names_mask[] = {
2648 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2649 };
2650 static const char *att_names_mask[] = {
2651 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2652 };
2653
2654 static const char *names_rounding[] =
2655 {
2656 "{rn-sae}",
2657 "{rd-sae}",
2658 "{ru-sae}",
2659 "{rz-sae}"
2660 };
2661
2662 static const struct dis386 reg_table[][8] = {
2663 /* REG_80 */
2664 {
2665 { "addA", { Ebh1, Ib }, 0 },
2666 { "orA", { Ebh1, Ib }, 0 },
2667 { "adcA", { Ebh1, Ib }, 0 },
2668 { "sbbA", { Ebh1, Ib }, 0 },
2669 { "andA", { Ebh1, Ib }, 0 },
2670 { "subA", { Ebh1, Ib }, 0 },
2671 { "xorA", { Ebh1, Ib }, 0 },
2672 { "cmpA", { Eb, Ib }, 0 },
2673 },
2674 /* REG_81 */
2675 {
2676 { "addQ", { Evh1, Iv }, 0 },
2677 { "orQ", { Evh1, Iv }, 0 },
2678 { "adcQ", { Evh1, Iv }, 0 },
2679 { "sbbQ", { Evh1, Iv }, 0 },
2680 { "andQ", { Evh1, Iv }, 0 },
2681 { "subQ", { Evh1, Iv }, 0 },
2682 { "xorQ", { Evh1, Iv }, 0 },
2683 { "cmpQ", { Ev, Iv }, 0 },
2684 },
2685 /* REG_83 */
2686 {
2687 { "addQ", { Evh1, sIb }, 0 },
2688 { "orQ", { Evh1, sIb }, 0 },
2689 { "adcQ", { Evh1, sIb }, 0 },
2690 { "sbbQ", { Evh1, sIb }, 0 },
2691 { "andQ", { Evh1, sIb }, 0 },
2692 { "subQ", { Evh1, sIb }, 0 },
2693 { "xorQ", { Evh1, sIb }, 0 },
2694 { "cmpQ", { Ev, sIb }, 0 },
2695 },
2696 /* REG_8F */
2697 {
2698 { "popU", { stackEv }, 0 },
2699 { XOP_8F_TABLE (XOP_09) },
2700 { Bad_Opcode },
2701 { Bad_Opcode },
2702 { Bad_Opcode },
2703 { XOP_8F_TABLE (XOP_09) },
2704 },
2705 /* REG_C0 */
2706 {
2707 { "rolA", { Eb, Ib }, 0 },
2708 { "rorA", { Eb, Ib }, 0 },
2709 { "rclA", { Eb, Ib }, 0 },
2710 { "rcrA", { Eb, Ib }, 0 },
2711 { "shlA", { Eb, Ib }, 0 },
2712 { "shrA", { Eb, Ib }, 0 },
2713 { "shlA", { Eb, Ib }, 0 },
2714 { "sarA", { Eb, Ib }, 0 },
2715 },
2716 /* REG_C1 */
2717 {
2718 { "rolQ", { Ev, Ib }, 0 },
2719 { "rorQ", { Ev, Ib }, 0 },
2720 { "rclQ", { Ev, Ib }, 0 },
2721 { "rcrQ", { Ev, Ib }, 0 },
2722 { "shlQ", { Ev, Ib }, 0 },
2723 { "shrQ", { Ev, Ib }, 0 },
2724 { "shlQ", { Ev, Ib }, 0 },
2725 { "sarQ", { Ev, Ib }, 0 },
2726 },
2727 /* REG_C6 */
2728 {
2729 { "movA", { Ebh3, Ib }, 0 },
2730 { Bad_Opcode },
2731 { Bad_Opcode },
2732 { Bad_Opcode },
2733 { Bad_Opcode },
2734 { Bad_Opcode },
2735 { Bad_Opcode },
2736 { MOD_TABLE (MOD_C6_REG_7) },
2737 },
2738 /* REG_C7 */
2739 {
2740 { "movQ", { Evh3, Iv }, 0 },
2741 { Bad_Opcode },
2742 { Bad_Opcode },
2743 { Bad_Opcode },
2744 { Bad_Opcode },
2745 { Bad_Opcode },
2746 { Bad_Opcode },
2747 { MOD_TABLE (MOD_C7_REG_7) },
2748 },
2749 /* REG_D0 */
2750 {
2751 { "rolA", { Eb, I1 }, 0 },
2752 { "rorA", { Eb, I1 }, 0 },
2753 { "rclA", { Eb, I1 }, 0 },
2754 { "rcrA", { Eb, I1 }, 0 },
2755 { "shlA", { Eb, I1 }, 0 },
2756 { "shrA", { Eb, I1 }, 0 },
2757 { "shlA", { Eb, I1 }, 0 },
2758 { "sarA", { Eb, I1 }, 0 },
2759 },
2760 /* REG_D1 */
2761 {
2762 { "rolQ", { Ev, I1 }, 0 },
2763 { "rorQ", { Ev, I1 }, 0 },
2764 { "rclQ", { Ev, I1 }, 0 },
2765 { "rcrQ", { Ev, I1 }, 0 },
2766 { "shlQ", { Ev, I1 }, 0 },
2767 { "shrQ", { Ev, I1 }, 0 },
2768 { "shlQ", { Ev, I1 }, 0 },
2769 { "sarQ", { Ev, I1 }, 0 },
2770 },
2771 /* REG_D2 */
2772 {
2773 { "rolA", { Eb, CL }, 0 },
2774 { "rorA", { Eb, CL }, 0 },
2775 { "rclA", { Eb, CL }, 0 },
2776 { "rcrA", { Eb, CL }, 0 },
2777 { "shlA", { Eb, CL }, 0 },
2778 { "shrA", { Eb, CL }, 0 },
2779 { "shlA", { Eb, CL }, 0 },
2780 { "sarA", { Eb, CL }, 0 },
2781 },
2782 /* REG_D3 */
2783 {
2784 { "rolQ", { Ev, CL }, 0 },
2785 { "rorQ", { Ev, CL }, 0 },
2786 { "rclQ", { Ev, CL }, 0 },
2787 { "rcrQ", { Ev, CL }, 0 },
2788 { "shlQ", { Ev, CL }, 0 },
2789 { "shrQ", { Ev, CL }, 0 },
2790 { "shlQ", { Ev, CL }, 0 },
2791 { "sarQ", { Ev, CL }, 0 },
2792 },
2793 /* REG_F6 */
2794 {
2795 { "testA", { Eb, Ib }, 0 },
2796 { "testA", { Eb, Ib }, 0 },
2797 { "notA", { Ebh1 }, 0 },
2798 { "negA", { Ebh1 }, 0 },
2799 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2800 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2801 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2802 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2803 },
2804 /* REG_F7 */
2805 {
2806 { "testQ", { Ev, Iv }, 0 },
2807 { "testQ", { Ev, Iv }, 0 },
2808 { "notQ", { Evh1 }, 0 },
2809 { "negQ", { Evh1 }, 0 },
2810 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2811 { "imulQ", { Ev }, 0 },
2812 { "divQ", { Ev }, 0 },
2813 { "idivQ", { Ev }, 0 },
2814 },
2815 /* REG_FE */
2816 {
2817 { "incA", { Ebh1 }, 0 },
2818 { "decA", { Ebh1 }, 0 },
2819 },
2820 /* REG_FF */
2821 {
2822 { "incQ", { Evh1 }, 0 },
2823 { "decQ", { Evh1 }, 0 },
2824 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
2825 { MOD_TABLE (MOD_FF_REG_3) },
2826 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
2827 { MOD_TABLE (MOD_FF_REG_5) },
2828 { "pushU", { stackEv }, 0 },
2829 { Bad_Opcode },
2830 },
2831 /* REG_0F00 */
2832 {
2833 { "sldtD", { Sv }, 0 },
2834 { "strD", { Sv }, 0 },
2835 { "lldt", { Ew }, 0 },
2836 { "ltr", { Ew }, 0 },
2837 { "verr", { Ew }, 0 },
2838 { "verw", { Ew }, 0 },
2839 { Bad_Opcode },
2840 { Bad_Opcode },
2841 },
2842 /* REG_0F01 */
2843 {
2844 { MOD_TABLE (MOD_0F01_REG_0) },
2845 { MOD_TABLE (MOD_0F01_REG_1) },
2846 { MOD_TABLE (MOD_0F01_REG_2) },
2847 { MOD_TABLE (MOD_0F01_REG_3) },
2848 { "smswD", { Sv }, 0 },
2849 { MOD_TABLE (MOD_0F01_REG_5) },
2850 { "lmsw", { Ew }, 0 },
2851 { MOD_TABLE (MOD_0F01_REG_7) },
2852 },
2853 /* REG_0F0D */
2854 {
2855 { "prefetch", { Mb }, 0 },
2856 { "prefetchw", { Mb }, 0 },
2857 { "prefetchwt1", { Mb }, 0 },
2858 { "prefetch", { Mb }, 0 },
2859 { "prefetch", { Mb }, 0 },
2860 { "prefetch", { Mb }, 0 },
2861 { "prefetch", { Mb }, 0 },
2862 { "prefetch", { Mb }, 0 },
2863 },
2864 /* REG_0F18 */
2865 {
2866 { MOD_TABLE (MOD_0F18_REG_0) },
2867 { MOD_TABLE (MOD_0F18_REG_1) },
2868 { MOD_TABLE (MOD_0F18_REG_2) },
2869 { MOD_TABLE (MOD_0F18_REG_3) },
2870 { MOD_TABLE (MOD_0F18_REG_4) },
2871 { MOD_TABLE (MOD_0F18_REG_5) },
2872 { MOD_TABLE (MOD_0F18_REG_6) },
2873 { MOD_TABLE (MOD_0F18_REG_7) },
2874 },
2875 /* REG_0F1C_P_0_MOD_0 */
2876 {
2877 { "cldemote", { Mb }, 0 },
2878 { "nopQ", { Ev }, 0 },
2879 { "nopQ", { Ev }, 0 },
2880 { "nopQ", { Ev }, 0 },
2881 { "nopQ", { Ev }, 0 },
2882 { "nopQ", { Ev }, 0 },
2883 { "nopQ", { Ev }, 0 },
2884 { "nopQ", { Ev }, 0 },
2885 },
2886 /* REG_0F1E_P_1_MOD_3 */
2887 {
2888 { "nopQ", { Ev }, 0 },
2889 { "rdsspK", { Edq }, PREFIX_OPCODE },
2890 { "nopQ", { Ev }, 0 },
2891 { "nopQ", { Ev }, 0 },
2892 { "nopQ", { Ev }, 0 },
2893 { "nopQ", { Ev }, 0 },
2894 { "nopQ", { Ev }, 0 },
2895 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2896 },
2897 /* REG_0F71 */
2898 {
2899 { Bad_Opcode },
2900 { Bad_Opcode },
2901 { MOD_TABLE (MOD_0F71_REG_2) },
2902 { Bad_Opcode },
2903 { MOD_TABLE (MOD_0F71_REG_4) },
2904 { Bad_Opcode },
2905 { MOD_TABLE (MOD_0F71_REG_6) },
2906 },
2907 /* REG_0F72 */
2908 {
2909 { Bad_Opcode },
2910 { Bad_Opcode },
2911 { MOD_TABLE (MOD_0F72_REG_2) },
2912 { Bad_Opcode },
2913 { MOD_TABLE (MOD_0F72_REG_4) },
2914 { Bad_Opcode },
2915 { MOD_TABLE (MOD_0F72_REG_6) },
2916 },
2917 /* REG_0F73 */
2918 {
2919 { Bad_Opcode },
2920 { Bad_Opcode },
2921 { MOD_TABLE (MOD_0F73_REG_2) },
2922 { MOD_TABLE (MOD_0F73_REG_3) },
2923 { Bad_Opcode },
2924 { Bad_Opcode },
2925 { MOD_TABLE (MOD_0F73_REG_6) },
2926 { MOD_TABLE (MOD_0F73_REG_7) },
2927 },
2928 /* REG_0FA6 */
2929 {
2930 { "montmul", { { OP_0f07, 0 } }, 0 },
2931 { "xsha1", { { OP_0f07, 0 } }, 0 },
2932 { "xsha256", { { OP_0f07, 0 } }, 0 },
2933 },
2934 /* REG_0FA7 */
2935 {
2936 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2937 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2938 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2939 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2940 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2941 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2942 },
2943 /* REG_0FAE */
2944 {
2945 { MOD_TABLE (MOD_0FAE_REG_0) },
2946 { MOD_TABLE (MOD_0FAE_REG_1) },
2947 { MOD_TABLE (MOD_0FAE_REG_2) },
2948 { MOD_TABLE (MOD_0FAE_REG_3) },
2949 { MOD_TABLE (MOD_0FAE_REG_4) },
2950 { MOD_TABLE (MOD_0FAE_REG_5) },
2951 { MOD_TABLE (MOD_0FAE_REG_6) },
2952 { MOD_TABLE (MOD_0FAE_REG_7) },
2953 },
2954 /* REG_0FBA */
2955 {
2956 { Bad_Opcode },
2957 { Bad_Opcode },
2958 { Bad_Opcode },
2959 { Bad_Opcode },
2960 { "btQ", { Ev, Ib }, 0 },
2961 { "btsQ", { Evh1, Ib }, 0 },
2962 { "btrQ", { Evh1, Ib }, 0 },
2963 { "btcQ", { Evh1, Ib }, 0 },
2964 },
2965 /* REG_0FC7 */
2966 {
2967 { Bad_Opcode },
2968 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2969 { Bad_Opcode },
2970 { MOD_TABLE (MOD_0FC7_REG_3) },
2971 { MOD_TABLE (MOD_0FC7_REG_4) },
2972 { MOD_TABLE (MOD_0FC7_REG_5) },
2973 { MOD_TABLE (MOD_0FC7_REG_6) },
2974 { MOD_TABLE (MOD_0FC7_REG_7) },
2975 },
2976 /* REG_VEX_0F71 */
2977 {
2978 { Bad_Opcode },
2979 { Bad_Opcode },
2980 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2981 { Bad_Opcode },
2982 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2983 { Bad_Opcode },
2984 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2985 },
2986 /* REG_VEX_0F72 */
2987 {
2988 { Bad_Opcode },
2989 { Bad_Opcode },
2990 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2991 { Bad_Opcode },
2992 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2993 { Bad_Opcode },
2994 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2995 },
2996 /* REG_VEX_0F73 */
2997 {
2998 { Bad_Opcode },
2999 { Bad_Opcode },
3000 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3001 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3002 { Bad_Opcode },
3003 { Bad_Opcode },
3004 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3005 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3006 },
3007 /* REG_VEX_0FAE */
3008 {
3009 { Bad_Opcode },
3010 { Bad_Opcode },
3011 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3012 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3013 },
3014 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3015 {
3016 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3017 },
3018 /* REG_VEX_0F38F3 */
3019 {
3020 { Bad_Opcode },
3021 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
3022 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
3023 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
3024 },
3025 /* REG_0FXOP_09_01_L_0 */
3026 {
3027 { Bad_Opcode },
3028 { "blcfill", { VexGdq, Edq }, 0 },
3029 { "blsfill", { VexGdq, Edq }, 0 },
3030 { "blcs", { VexGdq, Edq }, 0 },
3031 { "tzmsk", { VexGdq, Edq }, 0 },
3032 { "blcic", { VexGdq, Edq }, 0 },
3033 { "blsic", { VexGdq, Edq }, 0 },
3034 { "t1mskc", { VexGdq, Edq }, 0 },
3035 },
3036 /* REG_0FXOP_09_02_L_0 */
3037 {
3038 { Bad_Opcode },
3039 { "blcmsk", { VexGdq, Edq }, 0 },
3040 { Bad_Opcode },
3041 { Bad_Opcode },
3042 { Bad_Opcode },
3043 { Bad_Opcode },
3044 { "blci", { VexGdq, Edq }, 0 },
3045 },
3046 /* REG_0FXOP_09_12_M_1_L_0 */
3047 {
3048 { "llwpcb", { Edq }, 0 },
3049 { "slwpcb", { Edq }, 0 },
3050 },
3051 /* REG_0FXOP_0A_12_L_0 */
3052 {
3053 { "lwpins", { VexGdq, Ed, Id }, 0 },
3054 { "lwpval", { VexGdq, Ed, Id }, 0 },
3055 },
3056
3057 #include "i386-dis-evex-reg.h"
3058 };
3059
3060 static const struct dis386 prefix_table[][4] = {
3061 /* PREFIX_90 */
3062 {
3063 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3064 { "pause", { XX }, 0 },
3065 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3066 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3067 },
3068
3069 /* PREFIX_0F01_REG_3_RM_1 */
3070 {
3071 { "vmmcall", { Skip_MODRM }, 0 },
3072 { "vmgexit", { Skip_MODRM }, 0 },
3073 { Bad_Opcode },
3074 { "vmgexit", { Skip_MODRM }, 0 },
3075 },
3076
3077 /* PREFIX_0F01_REG_5_MOD_0 */
3078 {
3079 { Bad_Opcode },
3080 { "rstorssp", { Mq }, PREFIX_OPCODE },
3081 },
3082
3083 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3084 {
3085 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3086 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3087 { Bad_Opcode },
3088 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3089 },
3090
3091 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3092 {
3093 { Bad_Opcode },
3094 { Bad_Opcode },
3095 { Bad_Opcode },
3096 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3097 },
3098
3099 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3100 {
3101 { Bad_Opcode },
3102 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3103 },
3104
3105 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3106 {
3107 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3108 { "mcommit", { Skip_MODRM }, 0 },
3109 },
3110
3111 /* PREFIX_0F09 */
3112 {
3113 { "wbinvd", { XX }, 0 },
3114 { "wbnoinvd", { XX }, 0 },
3115 },
3116
3117 /* PREFIX_0F10 */
3118 {
3119 { "movups", { XM, EXx }, PREFIX_OPCODE },
3120 { "movss", { XM, EXd }, PREFIX_OPCODE },
3121 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3122 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3123 },
3124
3125 /* PREFIX_0F11 */
3126 {
3127 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3128 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3129 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3130 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3131 },
3132
3133 /* PREFIX_0F12 */
3134 {
3135 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3136 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3137 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3138 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3139 },
3140
3141 /* PREFIX_0F16 */
3142 {
3143 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3144 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3145 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3146 },
3147
3148 /* PREFIX_0F1A */
3149 {
3150 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3151 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3152 { "bndmov", { Gbnd, Ebnd }, 0 },
3153 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3154 },
3155
3156 /* PREFIX_0F1B */
3157 {
3158 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3159 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3160 { "bndmov", { EbndS, Gbnd }, 0 },
3161 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3162 },
3163
3164 /* PREFIX_0F1C */
3165 {
3166 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3167 { "nopQ", { Ev }, PREFIX_OPCODE },
3168 { "nopQ", { Ev }, PREFIX_OPCODE },
3169 { "nopQ", { Ev }, PREFIX_OPCODE },
3170 },
3171
3172 /* PREFIX_0F1E */
3173 {
3174 { "nopQ", { Ev }, PREFIX_OPCODE },
3175 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3176 { "nopQ", { Ev }, PREFIX_OPCODE },
3177 { "nopQ", { Ev }, PREFIX_OPCODE },
3178 },
3179
3180 /* PREFIX_0F2A */
3181 {
3182 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3183 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3184 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3185 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3186 },
3187
3188 /* PREFIX_0F2B */
3189 {
3190 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3191 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3192 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3193 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3194 },
3195
3196 /* PREFIX_0F2C */
3197 {
3198 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3199 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3200 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3201 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3202 },
3203
3204 /* PREFIX_0F2D */
3205 {
3206 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3207 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3208 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3209 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3210 },
3211
3212 /* PREFIX_0F2E */
3213 {
3214 { "ucomiss",{ XM, EXd }, 0 },
3215 { Bad_Opcode },
3216 { "ucomisd",{ XM, EXq }, 0 },
3217 },
3218
3219 /* PREFIX_0F2F */
3220 {
3221 { "comiss", { XM, EXd }, 0 },
3222 { Bad_Opcode },
3223 { "comisd", { XM, EXq }, 0 },
3224 },
3225
3226 /* PREFIX_0F51 */
3227 {
3228 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3229 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3230 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3231 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3232 },
3233
3234 /* PREFIX_0F52 */
3235 {
3236 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3237 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3238 },
3239
3240 /* PREFIX_0F53 */
3241 {
3242 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3243 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3244 },
3245
3246 /* PREFIX_0F58 */
3247 {
3248 { "addps", { XM, EXx }, PREFIX_OPCODE },
3249 { "addss", { XM, EXd }, PREFIX_OPCODE },
3250 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3251 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3252 },
3253
3254 /* PREFIX_0F59 */
3255 {
3256 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3257 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3258 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3259 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3260 },
3261
3262 /* PREFIX_0F5A */
3263 {
3264 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3265 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3266 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3267 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3268 },
3269
3270 /* PREFIX_0F5B */
3271 {
3272 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3273 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3274 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3275 },
3276
3277 /* PREFIX_0F5C */
3278 {
3279 { "subps", { XM, EXx }, PREFIX_OPCODE },
3280 { "subss", { XM, EXd }, PREFIX_OPCODE },
3281 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3282 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3283 },
3284
3285 /* PREFIX_0F5D */
3286 {
3287 { "minps", { XM, EXx }, PREFIX_OPCODE },
3288 { "minss", { XM, EXd }, PREFIX_OPCODE },
3289 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3290 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3291 },
3292
3293 /* PREFIX_0F5E */
3294 {
3295 { "divps", { XM, EXx }, PREFIX_OPCODE },
3296 { "divss", { XM, EXd }, PREFIX_OPCODE },
3297 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3298 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3299 },
3300
3301 /* PREFIX_0F5F */
3302 {
3303 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3304 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3305 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3306 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3307 },
3308
3309 /* PREFIX_0F60 */
3310 {
3311 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3312 { Bad_Opcode },
3313 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3314 },
3315
3316 /* PREFIX_0F61 */
3317 {
3318 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3319 { Bad_Opcode },
3320 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3321 },
3322
3323 /* PREFIX_0F62 */
3324 {
3325 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3326 { Bad_Opcode },
3327 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3328 },
3329
3330 /* PREFIX_0F6F */
3331 {
3332 { "movq", { MX, EM }, PREFIX_OPCODE },
3333 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3334 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3335 },
3336
3337 /* PREFIX_0F70 */
3338 {
3339 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3340 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3341 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3342 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3343 },
3344
3345 /* PREFIX_0F78 */
3346 {
3347 {"vmread", { Em, Gm }, 0 },
3348 { Bad_Opcode },
3349 {"extrq", { XS, Ib, Ib }, 0 },
3350 {"insertq", { XM, XS, Ib, Ib }, 0 },
3351 },
3352
3353 /* PREFIX_0F79 */
3354 {
3355 {"vmwrite", { Gm, Em }, 0 },
3356 { Bad_Opcode },
3357 {"extrq", { XM, XS }, 0 },
3358 {"insertq", { XM, XS }, 0 },
3359 },
3360
3361 /* PREFIX_0F7C */
3362 {
3363 { Bad_Opcode },
3364 { Bad_Opcode },
3365 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3366 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3367 },
3368
3369 /* PREFIX_0F7D */
3370 {
3371 { Bad_Opcode },
3372 { Bad_Opcode },
3373 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3374 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3375 },
3376
3377 /* PREFIX_0F7E */
3378 {
3379 { "movK", { Edq, MX }, PREFIX_OPCODE },
3380 { "movq", { XM, EXq }, PREFIX_OPCODE },
3381 { "movK", { Edq, XM }, PREFIX_OPCODE },
3382 },
3383
3384 /* PREFIX_0F7F */
3385 {
3386 { "movq", { EMS, MX }, PREFIX_OPCODE },
3387 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3388 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3389 },
3390
3391 /* PREFIX_0FAE_REG_0_MOD_3 */
3392 {
3393 { Bad_Opcode },
3394 { "rdfsbase", { Ev }, 0 },
3395 },
3396
3397 /* PREFIX_0FAE_REG_1_MOD_3 */
3398 {
3399 { Bad_Opcode },
3400 { "rdgsbase", { Ev }, 0 },
3401 },
3402
3403 /* PREFIX_0FAE_REG_2_MOD_3 */
3404 {
3405 { Bad_Opcode },
3406 { "wrfsbase", { Ev }, 0 },
3407 },
3408
3409 /* PREFIX_0FAE_REG_3_MOD_3 */
3410 {
3411 { Bad_Opcode },
3412 { "wrgsbase", { Ev }, 0 },
3413 },
3414
3415 /* PREFIX_0FAE_REG_4_MOD_0 */
3416 {
3417 { "xsave", { FXSAVE }, 0 },
3418 { "ptwrite{%LQ|}", { Edq }, 0 },
3419 },
3420
3421 /* PREFIX_0FAE_REG_4_MOD_3 */
3422 {
3423 { Bad_Opcode },
3424 { "ptwrite{%LQ|}", { Edq }, 0 },
3425 },
3426
3427 /* PREFIX_0FAE_REG_5_MOD_3 */
3428 {
3429 { "lfence", { Skip_MODRM }, 0 },
3430 { "incsspK", { Edq }, PREFIX_OPCODE },
3431 },
3432
3433 /* PREFIX_0FAE_REG_6_MOD_0 */
3434 {
3435 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3436 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3437 { "clwb", { Mb }, PREFIX_OPCODE },
3438 },
3439
3440 /* PREFIX_0FAE_REG_6_MOD_3 */
3441 {
3442 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3443 { "umonitor", { Eva }, PREFIX_OPCODE },
3444 { "tpause", { Edq }, PREFIX_OPCODE },
3445 { "umwait", { Edq }, PREFIX_OPCODE },
3446 },
3447
3448 /* PREFIX_0FAE_REG_7_MOD_0 */
3449 {
3450 { "clflush", { Mb }, 0 },
3451 { Bad_Opcode },
3452 { "clflushopt", { Mb }, 0 },
3453 },
3454
3455 /* PREFIX_0FB8 */
3456 {
3457 { Bad_Opcode },
3458 { "popcntS", { Gv, Ev }, 0 },
3459 },
3460
3461 /* PREFIX_0FBC */
3462 {
3463 { "bsfS", { Gv, Ev }, 0 },
3464 { "tzcntS", { Gv, Ev }, 0 },
3465 { "bsfS", { Gv, Ev }, 0 },
3466 },
3467
3468 /* PREFIX_0FBD */
3469 {
3470 { "bsrS", { Gv, Ev }, 0 },
3471 { "lzcntS", { Gv, Ev }, 0 },
3472 { "bsrS", { Gv, Ev }, 0 },
3473 },
3474
3475 /* PREFIX_0FC2 */
3476 {
3477 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3478 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3479 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3480 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3481 },
3482
3483 /* PREFIX_0FC7_REG_6_MOD_0 */
3484 {
3485 { "vmptrld",{ Mq }, 0 },
3486 { "vmxon", { Mq }, 0 },
3487 { "vmclear",{ Mq }, 0 },
3488 },
3489
3490 /* PREFIX_0FC7_REG_6_MOD_3 */
3491 {
3492 { "rdrand", { Ev }, 0 },
3493 { Bad_Opcode },
3494 { "rdrand", { Ev }, 0 }
3495 },
3496
3497 /* PREFIX_0FC7_REG_7_MOD_3 */
3498 {
3499 { "rdseed", { Ev }, 0 },
3500 { "rdpid", { Em }, 0 },
3501 { "rdseed", { Ev }, 0 },
3502 },
3503
3504 /* PREFIX_0FD0 */
3505 {
3506 { Bad_Opcode },
3507 { Bad_Opcode },
3508 { "addsubpd", { XM, EXx }, 0 },
3509 { "addsubps", { XM, EXx }, 0 },
3510 },
3511
3512 /* PREFIX_0FD6 */
3513 {
3514 { Bad_Opcode },
3515 { "movq2dq",{ XM, MS }, 0 },
3516 { "movq", { EXqS, XM }, 0 },
3517 { "movdq2q",{ MX, XS }, 0 },
3518 },
3519
3520 /* PREFIX_0FE6 */
3521 {
3522 { Bad_Opcode },
3523 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3524 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3525 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3526 },
3527
3528 /* PREFIX_0FE7 */
3529 {
3530 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3531 { Bad_Opcode },
3532 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3533 },
3534
3535 /* PREFIX_0FF0 */
3536 {
3537 { Bad_Opcode },
3538 { Bad_Opcode },
3539 { Bad_Opcode },
3540 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3541 },
3542
3543 /* PREFIX_0FF7 */
3544 {
3545 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3546 { Bad_Opcode },
3547 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3548 },
3549
3550 /* PREFIX_0F38F0 */
3551 {
3552 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3553 { Bad_Opcode },
3554 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3555 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3556 },
3557
3558 /* PREFIX_0F38F1 */
3559 {
3560 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3561 { Bad_Opcode },
3562 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3563 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3564 },
3565
3566 /* PREFIX_0F38F6 */
3567 {
3568 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3569 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3570 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3571 { Bad_Opcode },
3572 },
3573
3574 /* PREFIX_0F38F8 */
3575 {
3576 { Bad_Opcode },
3577 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3578 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3579 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3580 },
3581
3582 /* PREFIX_VEX_0F10 */
3583 {
3584 { "vmovups", { XM, EXx }, 0 },
3585 { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
3586 { "vmovupd", { XM, EXx }, 0 },
3587 { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3588 },
3589
3590 /* PREFIX_VEX_0F11 */
3591 {
3592 { "vmovups", { EXxS, XM }, 0 },
3593 { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
3594 { "vmovupd", { EXxS, XM }, 0 },
3595 { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
3596 },
3597
3598 /* PREFIX_VEX_0F12 */
3599 {
3600 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3601 { "vmovsldup", { XM, EXx }, 0 },
3602 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3603 { "vmovddup", { XM, EXymmq }, 0 },
3604 },
3605
3606 /* PREFIX_VEX_0F16 */
3607 {
3608 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3609 { "vmovshdup", { XM, EXx }, 0 },
3610 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3611 },
3612
3613 /* PREFIX_VEX_0F2A */
3614 {
3615 { Bad_Opcode },
3616 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3617 { Bad_Opcode },
3618 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3619 },
3620
3621 /* PREFIX_VEX_0F2C */
3622 {
3623 { Bad_Opcode },
3624 { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
3625 { Bad_Opcode },
3626 { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3627 },
3628
3629 /* PREFIX_VEX_0F2D */
3630 {
3631 { Bad_Opcode },
3632 { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
3633 { Bad_Opcode },
3634 { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3635 },
3636
3637 /* PREFIX_VEX_0F2E */
3638 {
3639 { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3640 { Bad_Opcode },
3641 { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3642 },
3643
3644 /* PREFIX_VEX_0F2F */
3645 {
3646 { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3647 { Bad_Opcode },
3648 { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3649 },
3650
3651 /* PREFIX_VEX_0F41 */
3652 {
3653 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3654 { Bad_Opcode },
3655 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3656 },
3657
3658 /* PREFIX_VEX_0F42 */
3659 {
3660 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3661 { Bad_Opcode },
3662 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3663 },
3664
3665 /* PREFIX_VEX_0F44 */
3666 {
3667 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3668 { Bad_Opcode },
3669 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3670 },
3671
3672 /* PREFIX_VEX_0F45 */
3673 {
3674 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3675 { Bad_Opcode },
3676 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3677 },
3678
3679 /* PREFIX_VEX_0F46 */
3680 {
3681 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3682 { Bad_Opcode },
3683 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3684 },
3685
3686 /* PREFIX_VEX_0F47 */
3687 {
3688 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3689 { Bad_Opcode },
3690 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3691 },
3692
3693 /* PREFIX_VEX_0F4A */
3694 {
3695 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3696 { Bad_Opcode },
3697 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3698 },
3699
3700 /* PREFIX_VEX_0F4B */
3701 {
3702 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3703 { Bad_Opcode },
3704 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3705 },
3706
3707 /* PREFIX_VEX_0F51 */
3708 {
3709 { "vsqrtps", { XM, EXx }, 0 },
3710 { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3711 { "vsqrtpd", { XM, EXx }, 0 },
3712 { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3713 },
3714
3715 /* PREFIX_VEX_0F52 */
3716 {
3717 { "vrsqrtps", { XM, EXx }, 0 },
3718 { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3719 },
3720
3721 /* PREFIX_VEX_0F53 */
3722 {
3723 { "vrcpps", { XM, EXx }, 0 },
3724 { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3725 },
3726
3727 /* PREFIX_VEX_0F58 */
3728 {
3729 { "vaddps", { XM, Vex, EXx }, 0 },
3730 { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3731 { "vaddpd", { XM, Vex, EXx }, 0 },
3732 { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3733 },
3734
3735 /* PREFIX_VEX_0F59 */
3736 {
3737 { "vmulps", { XM, Vex, EXx }, 0 },
3738 { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3739 { "vmulpd", { XM, Vex, EXx }, 0 },
3740 { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3741 },
3742
3743 /* PREFIX_VEX_0F5A */
3744 {
3745 { "vcvtps2pd", { XM, EXxmmq }, 0 },
3746 { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
3747 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3748 { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3749 },
3750
3751 /* PREFIX_VEX_0F5B */
3752 {
3753 { "vcvtdq2ps", { XM, EXx }, 0 },
3754 { "vcvttps2dq", { XM, EXx }, 0 },
3755 { "vcvtps2dq", { XM, EXx }, 0 },
3756 },
3757
3758 /* PREFIX_VEX_0F5C */
3759 {
3760 { "vsubps", { XM, Vex, EXx }, 0 },
3761 { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3762 { "vsubpd", { XM, Vex, EXx }, 0 },
3763 { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3764 },
3765
3766 /* PREFIX_VEX_0F5D */
3767 {
3768 { "vminps", { XM, Vex, EXx }, 0 },
3769 { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3770 { "vminpd", { XM, Vex, EXx }, 0 },
3771 { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3772 },
3773
3774 /* PREFIX_VEX_0F5E */
3775 {
3776 { "vdivps", { XM, Vex, EXx }, 0 },
3777 { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3778 { "vdivpd", { XM, Vex, EXx }, 0 },
3779 { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3780 },
3781
3782 /* PREFIX_VEX_0F5F */
3783 {
3784 { "vmaxps", { XM, Vex, EXx }, 0 },
3785 { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3786 { "vmaxpd", { XM, Vex, EXx }, 0 },
3787 { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3788 },
3789
3790 /* PREFIX_VEX_0F6F */
3791 {
3792 { Bad_Opcode },
3793 { "vmovdqu", { XM, EXx }, 0 },
3794 { "vmovdqa", { XM, EXx }, 0 },
3795 },
3796
3797 /* PREFIX_VEX_0F70 */
3798 {
3799 { Bad_Opcode },
3800 { "vpshufhw", { XM, EXx, Ib }, 0 },
3801 { "vpshufd", { XM, EXx, Ib }, 0 },
3802 { "vpshuflw", { XM, EXx, Ib }, 0 },
3803 },
3804
3805 /* PREFIX_VEX_0F7C */
3806 {
3807 { Bad_Opcode },
3808 { Bad_Opcode },
3809 { "vhaddpd", { XM, Vex, EXx }, 0 },
3810 { "vhaddps", { XM, Vex, EXx }, 0 },
3811 },
3812
3813 /* PREFIX_VEX_0F7D */
3814 {
3815 { Bad_Opcode },
3816 { Bad_Opcode },
3817 { "vhsubpd", { XM, Vex, EXx }, 0 },
3818 { "vhsubps", { XM, Vex, EXx }, 0 },
3819 },
3820
3821 /* PREFIX_VEX_0F7E */
3822 {
3823 { Bad_Opcode },
3824 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3825 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3826 },
3827
3828 /* PREFIX_VEX_0F7F */
3829 {
3830 { Bad_Opcode },
3831 { "vmovdqu", { EXxS, XM }, 0 },
3832 { "vmovdqa", { EXxS, XM }, 0 },
3833 },
3834
3835 /* PREFIX_VEX_0F90 */
3836 {
3837 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
3838 { Bad_Opcode },
3839 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
3840 },
3841
3842 /* PREFIX_VEX_0F91 */
3843 {
3844 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
3845 { Bad_Opcode },
3846 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
3847 },
3848
3849 /* PREFIX_VEX_0F92 */
3850 {
3851 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
3852 { Bad_Opcode },
3853 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
3854 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
3855 },
3856
3857 /* PREFIX_VEX_0F93 */
3858 {
3859 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
3860 { Bad_Opcode },
3861 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
3862 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
3863 },
3864
3865 /* PREFIX_VEX_0F98 */
3866 {
3867 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
3868 { Bad_Opcode },
3869 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
3870 },
3871
3872 /* PREFIX_VEX_0F99 */
3873 {
3874 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
3875 { Bad_Opcode },
3876 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
3877 },
3878
3879 /* PREFIX_VEX_0FC2 */
3880 {
3881 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
3882 { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
3883 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
3884 { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
3885 },
3886
3887 /* PREFIX_VEX_0FD0 */
3888 {
3889 { Bad_Opcode },
3890 { Bad_Opcode },
3891 { "vaddsubpd", { XM, Vex, EXx }, 0 },
3892 { "vaddsubps", { XM, Vex, EXx }, 0 },
3893 },
3894
3895 /* PREFIX_VEX_0FE6 */
3896 {
3897 { Bad_Opcode },
3898 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
3899 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
3900 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
3901 },
3902
3903 /* PREFIX_VEX_0FF0 */
3904 {
3905 { Bad_Opcode },
3906 { Bad_Opcode },
3907 { Bad_Opcode },
3908 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3909 },
3910
3911 /* PREFIX_VEX_0F3849_X86_64 */
3912 {
3913 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3914 { Bad_Opcode },
3915 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3916 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
3917 },
3918
3919 /* PREFIX_VEX_0F384B_X86_64 */
3920 {
3921 { Bad_Opcode },
3922 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
3923 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
3924 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
3925 },
3926
3927 /* PREFIX_VEX_0F385C_X86_64 */
3928 {
3929 { Bad_Opcode },
3930 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
3931 { Bad_Opcode },
3932 },
3933
3934 /* PREFIX_VEX_0F385E_X86_64 */
3935 {
3936 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
3937 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
3938 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
3939 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
3940 },
3941
3942 /* PREFIX_VEX_0F38F5 */
3943 {
3944 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
3945 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
3946 { Bad_Opcode },
3947 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
3948 },
3949
3950 /* PREFIX_VEX_0F38F6 */
3951 {
3952 { Bad_Opcode },
3953 { Bad_Opcode },
3954 { Bad_Opcode },
3955 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
3956 },
3957
3958 /* PREFIX_VEX_0F38F7 */
3959 {
3960 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
3961 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
3962 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
3963 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
3964 },
3965
3966 /* PREFIX_VEX_0F3AF0 */
3967 {
3968 { Bad_Opcode },
3969 { Bad_Opcode },
3970 { Bad_Opcode },
3971 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
3972 },
3973
3974 #include "i386-dis-evex-prefix.h"
3975 };
3976
3977 static const struct dis386 x86_64_table[][2] = {
3978 /* X86_64_06 */
3979 {
3980 { "pushP", { es }, 0 },
3981 },
3982
3983 /* X86_64_07 */
3984 {
3985 { "popP", { es }, 0 },
3986 },
3987
3988 /* X86_64_0E */
3989 {
3990 { "pushP", { cs }, 0 },
3991 },
3992
3993 /* X86_64_16 */
3994 {
3995 { "pushP", { ss }, 0 },
3996 },
3997
3998 /* X86_64_17 */
3999 {
4000 { "popP", { ss }, 0 },
4001 },
4002
4003 /* X86_64_1E */
4004 {
4005 { "pushP", { ds }, 0 },
4006 },
4007
4008 /* X86_64_1F */
4009 {
4010 { "popP", { ds }, 0 },
4011 },
4012
4013 /* X86_64_27 */
4014 {
4015 { "daa", { XX }, 0 },
4016 },
4017
4018 /* X86_64_2F */
4019 {
4020 { "das", { XX }, 0 },
4021 },
4022
4023 /* X86_64_37 */
4024 {
4025 { "aaa", { XX }, 0 },
4026 },
4027
4028 /* X86_64_3F */
4029 {
4030 { "aas", { XX }, 0 },
4031 },
4032
4033 /* X86_64_60 */
4034 {
4035 { "pushaP", { XX }, 0 },
4036 },
4037
4038 /* X86_64_61 */
4039 {
4040 { "popaP", { XX }, 0 },
4041 },
4042
4043 /* X86_64_62 */
4044 {
4045 { MOD_TABLE (MOD_62_32BIT) },
4046 { EVEX_TABLE (EVEX_0F) },
4047 },
4048
4049 /* X86_64_63 */
4050 {
4051 { "arpl", { Ew, Gw }, 0 },
4052 { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4053 },
4054
4055 /* X86_64_6D */
4056 {
4057 { "ins{R|}", { Yzr, indirDX }, 0 },
4058 { "ins{G|}", { Yzr, indirDX }, 0 },
4059 },
4060
4061 /* X86_64_6F */
4062 {
4063 { "outs{R|}", { indirDXr, Xz }, 0 },
4064 { "outs{G|}", { indirDXr, Xz }, 0 },
4065 },
4066
4067 /* X86_64_82 */
4068 {
4069 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4070 { REG_TABLE (REG_80) },
4071 },
4072
4073 /* X86_64_9A */
4074 {
4075 { "{l|}call{T|}", { Ap }, 0 },
4076 },
4077
4078 /* X86_64_C2 */
4079 {
4080 { "retP", { Iw, BND }, 0 },
4081 { "ret@", { Iw, BND }, 0 },
4082 },
4083
4084 /* X86_64_C3 */
4085 {
4086 { "retP", { BND }, 0 },
4087 { "ret@", { BND }, 0 },
4088 },
4089
4090 /* X86_64_C4 */
4091 {
4092 { MOD_TABLE (MOD_C4_32BIT) },
4093 { VEX_C4_TABLE (VEX_0F) },
4094 },
4095
4096 /* X86_64_C5 */
4097 {
4098 { MOD_TABLE (MOD_C5_32BIT) },
4099 { VEX_C5_TABLE (VEX_0F) },
4100 },
4101
4102 /* X86_64_CE */
4103 {
4104 { "into", { XX }, 0 },
4105 },
4106
4107 /* X86_64_D4 */
4108 {
4109 { "aam", { Ib }, 0 },
4110 },
4111
4112 /* X86_64_D5 */
4113 {
4114 { "aad", { Ib }, 0 },
4115 },
4116
4117 /* X86_64_E8 */
4118 {
4119 { "callP", { Jv, BND }, 0 },
4120 { "call@", { Jv, BND }, 0 }
4121 },
4122
4123 /* X86_64_E9 */
4124 {
4125 { "jmpP", { Jv, BND }, 0 },
4126 { "jmp@", { Jv, BND }, 0 }
4127 },
4128
4129 /* X86_64_EA */
4130 {
4131 { "{l|}jmp{T|}", { Ap }, 0 },
4132 },
4133
4134 /* X86_64_0F01_REG_0 */
4135 {
4136 { "sgdt{Q|Q}", { M }, 0 },
4137 { "sgdt", { M }, 0 },
4138 },
4139
4140 /* X86_64_0F01_REG_1 */
4141 {
4142 { "sidt{Q|Q}", { M }, 0 },
4143 { "sidt", { M }, 0 },
4144 },
4145
4146 /* X86_64_0F01_REG_2 */
4147 {
4148 { "lgdt{Q|Q}", { M }, 0 },
4149 { "lgdt", { M }, 0 },
4150 },
4151
4152 /* X86_64_0F01_REG_3 */
4153 {
4154 { "lidt{Q|Q}", { M }, 0 },
4155 { "lidt", { M }, 0 },
4156 },
4157
4158 {
4159 /* X86_64_0F24 */
4160 { "movZ", { Em, Td }, 0 },
4161 },
4162
4163 {
4164 /* X86_64_0F26 */
4165 { "movZ", { Td, Em }, 0 },
4166 },
4167
4168 /* X86_64_VEX_0F3849 */
4169 {
4170 { Bad_Opcode },
4171 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4172 },
4173
4174 /* X86_64_VEX_0F384B */
4175 {
4176 { Bad_Opcode },
4177 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4178 },
4179
4180 /* X86_64_VEX_0F385C */
4181 {
4182 { Bad_Opcode },
4183 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4184 },
4185
4186 /* X86_64_VEX_0F385E */
4187 {
4188 { Bad_Opcode },
4189 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4190 },
4191 };
4192
4193 static const struct dis386 three_byte_table[][256] = {
4194
4195 /* THREE_BYTE_0F38 */
4196 {
4197 /* 00 */
4198 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4199 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4200 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4201 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4202 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4203 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4204 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4205 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4206 /* 08 */
4207 { "psignb", { MX, EM }, PREFIX_OPCODE },
4208 { "psignw", { MX, EM }, PREFIX_OPCODE },
4209 { "psignd", { MX, EM }, PREFIX_OPCODE },
4210 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4211 { Bad_Opcode },
4212 { Bad_Opcode },
4213 { Bad_Opcode },
4214 { Bad_Opcode },
4215 /* 10 */
4216 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4217 { Bad_Opcode },
4218 { Bad_Opcode },
4219 { Bad_Opcode },
4220 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4221 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4222 { Bad_Opcode },
4223 { "ptest", { XM, EXx }, PREFIX_DATA },
4224 /* 18 */
4225 { Bad_Opcode },
4226 { Bad_Opcode },
4227 { Bad_Opcode },
4228 { Bad_Opcode },
4229 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4230 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4231 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4232 { Bad_Opcode },
4233 /* 20 */
4234 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4235 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4236 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4237 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4238 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4239 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4240 { Bad_Opcode },
4241 { Bad_Opcode },
4242 /* 28 */
4243 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4244 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4245 { MOD_TABLE (MOD_0F382A) },
4246 { "packusdw", { XM, EXx }, PREFIX_DATA },
4247 { Bad_Opcode },
4248 { Bad_Opcode },
4249 { Bad_Opcode },
4250 { Bad_Opcode },
4251 /* 30 */
4252 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4253 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4254 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4255 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4256 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4257 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4258 { Bad_Opcode },
4259 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4260 /* 38 */
4261 { "pminsb", { XM, EXx }, PREFIX_DATA },
4262 { "pminsd", { XM, EXx }, PREFIX_DATA },
4263 { "pminuw", { XM, EXx }, PREFIX_DATA },
4264 { "pminud", { XM, EXx }, PREFIX_DATA },
4265 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4266 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4267 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4268 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4269 /* 40 */
4270 { "pmulld", { XM, EXx }, PREFIX_DATA },
4271 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4272 { Bad_Opcode },
4273 { Bad_Opcode },
4274 { Bad_Opcode },
4275 { Bad_Opcode },
4276 { Bad_Opcode },
4277 { Bad_Opcode },
4278 /* 48 */
4279 { Bad_Opcode },
4280 { Bad_Opcode },
4281 { Bad_Opcode },
4282 { Bad_Opcode },
4283 { Bad_Opcode },
4284 { Bad_Opcode },
4285 { Bad_Opcode },
4286 { Bad_Opcode },
4287 /* 50 */
4288 { Bad_Opcode },
4289 { Bad_Opcode },
4290 { Bad_Opcode },
4291 { Bad_Opcode },
4292 { Bad_Opcode },
4293 { Bad_Opcode },
4294 { Bad_Opcode },
4295 { Bad_Opcode },
4296 /* 58 */
4297 { Bad_Opcode },
4298 { Bad_Opcode },
4299 { Bad_Opcode },
4300 { Bad_Opcode },
4301 { Bad_Opcode },
4302 { Bad_Opcode },
4303 { Bad_Opcode },
4304 { Bad_Opcode },
4305 /* 60 */
4306 { Bad_Opcode },
4307 { Bad_Opcode },
4308 { Bad_Opcode },
4309 { Bad_Opcode },
4310 { Bad_Opcode },
4311 { Bad_Opcode },
4312 { Bad_Opcode },
4313 { Bad_Opcode },
4314 /* 68 */
4315 { Bad_Opcode },
4316 { Bad_Opcode },
4317 { Bad_Opcode },
4318 { Bad_Opcode },
4319 { Bad_Opcode },
4320 { Bad_Opcode },
4321 { Bad_Opcode },
4322 { Bad_Opcode },
4323 /* 70 */
4324 { Bad_Opcode },
4325 { Bad_Opcode },
4326 { Bad_Opcode },
4327 { Bad_Opcode },
4328 { Bad_Opcode },
4329 { Bad_Opcode },
4330 { Bad_Opcode },
4331 { Bad_Opcode },
4332 /* 78 */
4333 { Bad_Opcode },
4334 { Bad_Opcode },
4335 { Bad_Opcode },
4336 { Bad_Opcode },
4337 { Bad_Opcode },
4338 { Bad_Opcode },
4339 { Bad_Opcode },
4340 { Bad_Opcode },
4341 /* 80 */
4342 { "invept", { Gm, Mo }, PREFIX_DATA },
4343 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4344 { "invpcid", { Gm, M }, PREFIX_DATA },
4345 { Bad_Opcode },
4346 { Bad_Opcode },
4347 { Bad_Opcode },
4348 { Bad_Opcode },
4349 { Bad_Opcode },
4350 /* 88 */
4351 { Bad_Opcode },
4352 { Bad_Opcode },
4353 { Bad_Opcode },
4354 { Bad_Opcode },
4355 { Bad_Opcode },
4356 { Bad_Opcode },
4357 { Bad_Opcode },
4358 { Bad_Opcode },
4359 /* 90 */
4360 { Bad_Opcode },
4361 { Bad_Opcode },
4362 { Bad_Opcode },
4363 { Bad_Opcode },
4364 { Bad_Opcode },
4365 { Bad_Opcode },
4366 { Bad_Opcode },
4367 { Bad_Opcode },
4368 /* 98 */
4369 { Bad_Opcode },
4370 { Bad_Opcode },
4371 { Bad_Opcode },
4372 { Bad_Opcode },
4373 { Bad_Opcode },
4374 { Bad_Opcode },
4375 { Bad_Opcode },
4376 { Bad_Opcode },
4377 /* a0 */
4378 { Bad_Opcode },
4379 { Bad_Opcode },
4380 { Bad_Opcode },
4381 { Bad_Opcode },
4382 { Bad_Opcode },
4383 { Bad_Opcode },
4384 { Bad_Opcode },
4385 { Bad_Opcode },
4386 /* a8 */
4387 { Bad_Opcode },
4388 { Bad_Opcode },
4389 { Bad_Opcode },
4390 { Bad_Opcode },
4391 { Bad_Opcode },
4392 { Bad_Opcode },
4393 { Bad_Opcode },
4394 { Bad_Opcode },
4395 /* b0 */
4396 { Bad_Opcode },
4397 { Bad_Opcode },
4398 { Bad_Opcode },
4399 { Bad_Opcode },
4400 { Bad_Opcode },
4401 { Bad_Opcode },
4402 { Bad_Opcode },
4403 { Bad_Opcode },
4404 /* b8 */
4405 { Bad_Opcode },
4406 { Bad_Opcode },
4407 { Bad_Opcode },
4408 { Bad_Opcode },
4409 { Bad_Opcode },
4410 { Bad_Opcode },
4411 { Bad_Opcode },
4412 { Bad_Opcode },
4413 /* c0 */
4414 { Bad_Opcode },
4415 { Bad_Opcode },
4416 { Bad_Opcode },
4417 { Bad_Opcode },
4418 { Bad_Opcode },
4419 { Bad_Opcode },
4420 { Bad_Opcode },
4421 { Bad_Opcode },
4422 /* c8 */
4423 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4424 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4425 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4426 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4427 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4428 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4429 { Bad_Opcode },
4430 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4431 /* d0 */
4432 { Bad_Opcode },
4433 { Bad_Opcode },
4434 { Bad_Opcode },
4435 { Bad_Opcode },
4436 { Bad_Opcode },
4437 { Bad_Opcode },
4438 { Bad_Opcode },
4439 { Bad_Opcode },
4440 /* d8 */
4441 { Bad_Opcode },
4442 { Bad_Opcode },
4443 { Bad_Opcode },
4444 { "aesimc", { XM, EXx }, PREFIX_DATA },
4445 { "aesenc", { XM, EXx }, PREFIX_DATA },
4446 { "aesenclast", { XM, EXx }, PREFIX_DATA },
4447 { "aesdec", { XM, EXx }, PREFIX_DATA },
4448 { "aesdeclast", { XM, EXx }, PREFIX_DATA },
4449 /* e0 */
4450 { Bad_Opcode },
4451 { Bad_Opcode },
4452 { Bad_Opcode },
4453 { Bad_Opcode },
4454 { Bad_Opcode },
4455 { Bad_Opcode },
4456 { Bad_Opcode },
4457 { Bad_Opcode },
4458 /* e8 */
4459 { Bad_Opcode },
4460 { Bad_Opcode },
4461 { Bad_Opcode },
4462 { Bad_Opcode },
4463 { Bad_Opcode },
4464 { Bad_Opcode },
4465 { Bad_Opcode },
4466 { Bad_Opcode },
4467 /* f0 */
4468 { PREFIX_TABLE (PREFIX_0F38F0) },
4469 { PREFIX_TABLE (PREFIX_0F38F1) },
4470 { Bad_Opcode },
4471 { Bad_Opcode },
4472 { Bad_Opcode },
4473 { MOD_TABLE (MOD_0F38F5) },
4474 { PREFIX_TABLE (PREFIX_0F38F6) },
4475 { Bad_Opcode },
4476 /* f8 */
4477 { PREFIX_TABLE (PREFIX_0F38F8) },
4478 { MOD_TABLE (MOD_0F38F9) },
4479 { Bad_Opcode },
4480 { Bad_Opcode },
4481 { Bad_Opcode },
4482 { Bad_Opcode },
4483 { Bad_Opcode },
4484 { Bad_Opcode },
4485 },
4486 /* THREE_BYTE_0F3A */
4487 {
4488 /* 00 */
4489 { Bad_Opcode },
4490 { Bad_Opcode },
4491 { Bad_Opcode },
4492 { Bad_Opcode },
4493 { Bad_Opcode },
4494 { Bad_Opcode },
4495 { Bad_Opcode },
4496 { Bad_Opcode },
4497 /* 08 */
4498 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4499 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4500 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4501 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4502 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4503 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4504 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4505 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4506 /* 10 */
4507 { Bad_Opcode },
4508 { Bad_Opcode },
4509 { Bad_Opcode },
4510 { Bad_Opcode },
4511 { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4512 { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4513 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4514 { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4515 /* 18 */
4516 { Bad_Opcode },
4517 { Bad_Opcode },
4518 { Bad_Opcode },
4519 { Bad_Opcode },
4520 { Bad_Opcode },
4521 { Bad_Opcode },
4522 { Bad_Opcode },
4523 { Bad_Opcode },
4524 /* 20 */
4525 { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4526 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4527 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4528 { Bad_Opcode },
4529 { Bad_Opcode },
4530 { Bad_Opcode },
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 /* 28 */
4534 { Bad_Opcode },
4535 { Bad_Opcode },
4536 { Bad_Opcode },
4537 { Bad_Opcode },
4538 { Bad_Opcode },
4539 { Bad_Opcode },
4540 { Bad_Opcode },
4541 { Bad_Opcode },
4542 /* 30 */
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 { Bad_Opcode },
4546 { Bad_Opcode },
4547 { Bad_Opcode },
4548 { Bad_Opcode },
4549 { Bad_Opcode },
4550 { Bad_Opcode },
4551 /* 38 */
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 { Bad_Opcode },
4555 { Bad_Opcode },
4556 { Bad_Opcode },
4557 { Bad_Opcode },
4558 { Bad_Opcode },
4559 { Bad_Opcode },
4560 /* 40 */
4561 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4562 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4563 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4564 { Bad_Opcode },
4565 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4566 { Bad_Opcode },
4567 { Bad_Opcode },
4568 { Bad_Opcode },
4569 /* 48 */
4570 { Bad_Opcode },
4571 { Bad_Opcode },
4572 { Bad_Opcode },
4573 { Bad_Opcode },
4574 { Bad_Opcode },
4575 { Bad_Opcode },
4576 { Bad_Opcode },
4577 { Bad_Opcode },
4578 /* 50 */
4579 { Bad_Opcode },
4580 { Bad_Opcode },
4581 { Bad_Opcode },
4582 { Bad_Opcode },
4583 { Bad_Opcode },
4584 { Bad_Opcode },
4585 { Bad_Opcode },
4586 { Bad_Opcode },
4587 /* 58 */
4588 { Bad_Opcode },
4589 { Bad_Opcode },
4590 { Bad_Opcode },
4591 { Bad_Opcode },
4592 { Bad_Opcode },
4593 { Bad_Opcode },
4594 { Bad_Opcode },
4595 { Bad_Opcode },
4596 /* 60 */
4597 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4598 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4599 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4600 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4601 { Bad_Opcode },
4602 { Bad_Opcode },
4603 { Bad_Opcode },
4604 { Bad_Opcode },
4605 /* 68 */
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 { Bad_Opcode },
4609 { Bad_Opcode },
4610 { Bad_Opcode },
4611 { Bad_Opcode },
4612 { Bad_Opcode },
4613 { Bad_Opcode },
4614 /* 70 */
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 { Bad_Opcode },
4618 { Bad_Opcode },
4619 { Bad_Opcode },
4620 { Bad_Opcode },
4621 { Bad_Opcode },
4622 { Bad_Opcode },
4623 /* 78 */
4624 { Bad_Opcode },
4625 { Bad_Opcode },
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 { Bad_Opcode },
4629 { Bad_Opcode },
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 /* 80 */
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 { Bad_Opcode },
4638 { Bad_Opcode },
4639 { Bad_Opcode },
4640 { Bad_Opcode },
4641 /* 88 */
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { Bad_Opcode },
4646 { Bad_Opcode },
4647 { Bad_Opcode },
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 /* 90 */
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 { Bad_Opcode },
4654 { Bad_Opcode },
4655 { Bad_Opcode },
4656 { Bad_Opcode },
4657 { Bad_Opcode },
4658 { Bad_Opcode },
4659 /* 98 */
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { Bad_Opcode },
4665 { Bad_Opcode },
4666 { Bad_Opcode },
4667 { Bad_Opcode },
4668 /* a0 */
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 { Bad_Opcode },
4674 { Bad_Opcode },
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 /* a8 */
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 { Bad_Opcode },
4683 { Bad_Opcode },
4684 { Bad_Opcode },
4685 { Bad_Opcode },
4686 /* b0 */
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 { Bad_Opcode },
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 /* b8 */
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 { Bad_Opcode },
4702 { Bad_Opcode },
4703 { Bad_Opcode },
4704 /* c0 */
4705 { Bad_Opcode },
4706 { Bad_Opcode },
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 { Bad_Opcode },
4710 { Bad_Opcode },
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 /* c8 */
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4719 { Bad_Opcode },
4720 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4721 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4722 /* d0 */
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { Bad_Opcode },
4728 { Bad_Opcode },
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 /* d8 */
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 { Bad_Opcode },
4738 { Bad_Opcode },
4739 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4740 /* e0 */
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 { Bad_Opcode },
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 /* e8 */
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 { Bad_Opcode },
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 /* f0 */
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 { Bad_Opcode },
4765 { Bad_Opcode },
4766 { Bad_Opcode },
4767 /* f8 */
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 { Bad_Opcode },
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 },
4777 };
4778
4779 static const struct dis386 xop_table[][256] = {
4780 /* XOP_08 */
4781 {
4782 /* 00 */
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 /* 08 */
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 /* 10 */
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 /* 18 */
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 /* 20 */
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 /* 28 */
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 /* 30 */
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 /* 38 */
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 /* 40 */
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 /* 48 */
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 /* 50 */
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 /* 58 */
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 /* 60 */
4891 { Bad_Opcode },
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 /* 68 */
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 /* 70 */
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 { Bad_Opcode },
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 /* 78 */
4918 { Bad_Opcode },
4919 { Bad_Opcode },
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 /* 80 */
4927 { Bad_Opcode },
4928 { Bad_Opcode },
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 { Bad_Opcode },
4932 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
4933 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
4934 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
4935 /* 88 */
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 { Bad_Opcode },
4941 { Bad_Opcode },
4942 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
4943 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
4944 /* 90 */
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 { Bad_Opcode },
4948 { Bad_Opcode },
4949 { Bad_Opcode },
4950 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
4951 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
4952 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
4953 /* 98 */
4954 { Bad_Opcode },
4955 { Bad_Opcode },
4956 { Bad_Opcode },
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
4961 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
4962 /* a0 */
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
4966 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
4967 { Bad_Opcode },
4968 { Bad_Opcode },
4969 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
4970 { Bad_Opcode },
4971 /* a8 */
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 { Bad_Opcode },
4976 { Bad_Opcode },
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 /* b0 */
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { Bad_Opcode },
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
4988 { Bad_Opcode },
4989 /* b8 */
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 /* c0 */
4999 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5000 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5001 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5002 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 /* c8 */
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5013 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5014 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5015 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5016 /* d0 */
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 /* d8 */
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 /* e0 */
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 /* e8 */
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5049 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5050 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5051 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5052 /* f0 */
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 /* f8 */
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 },
5071 /* XOP_09 */
5072 {
5073 /* 00 */
5074 { Bad_Opcode },
5075 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5076 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 /* 08 */
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 /* 10 */
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 /* 18 */
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 /* 20 */
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 /* 28 */
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 /* 30 */
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 /* 38 */
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 /* 40 */
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 /* 48 */
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 /* 50 */
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 /* 58 */
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 /* 60 */
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { Bad_Opcode },
5190 /* 68 */
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 /* 70 */
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 /* 78 */
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 { Bad_Opcode },
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 /* 80 */
5218 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5219 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5220 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5221 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5222 { Bad_Opcode },
5223 { Bad_Opcode },
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 /* 88 */
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 { Bad_Opcode },
5232 { Bad_Opcode },
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 /* 90 */
5236 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5237 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5238 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5239 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5240 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5241 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5242 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5243 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5244 /* 98 */
5245 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5246 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5247 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5248 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5249 { Bad_Opcode },
5250 { Bad_Opcode },
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 /* a0 */
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 /* a8 */
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 { Bad_Opcode },
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 /* b0 */
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 { Bad_Opcode },
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 /* b8 */
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 { Bad_Opcode },
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 /* c0 */
5290 { Bad_Opcode },
5291 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5292 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5293 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5294 { Bad_Opcode },
5295 { Bad_Opcode },
5296 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5297 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5298 /* c8 */
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5303 { Bad_Opcode },
5304 { Bad_Opcode },
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 /* d0 */
5308 { Bad_Opcode },
5309 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5310 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5311 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5312 { Bad_Opcode },
5313 { Bad_Opcode },
5314 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5315 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5316 /* d8 */
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5321 { Bad_Opcode },
5322 { Bad_Opcode },
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 /* e0 */
5326 { Bad_Opcode },
5327 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5328 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5329 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5330 { Bad_Opcode },
5331 { Bad_Opcode },
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 /* e8 */
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 { Bad_Opcode },
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 /* f0 */
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 { Bad_Opcode },
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 /* f8 */
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 { Bad_Opcode },
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 },
5362 /* XOP_0A */
5363 {
5364 /* 00 */
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { Bad_Opcode },
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 /* 08 */
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 { Bad_Opcode },
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 /* 10 */
5383 { "bextrS", { Gdq, Edq, Id }, 0 },
5384 { Bad_Opcode },
5385 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5386 { Bad_Opcode },
5387 { Bad_Opcode },
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 /* 18 */
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { Bad_Opcode },
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 /* 20 */
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 /* 28 */
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { Bad_Opcode },
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 /* 30 */
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { Bad_Opcode },
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 /* 38 */
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 { Bad_Opcode },
5432 { Bad_Opcode },
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 /* 40 */
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 { Bad_Opcode },
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { Bad_Opcode },
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 /* 48 */
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 { Bad_Opcode },
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 /* 50 */
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 { Bad_Opcode },
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 /* 58 */
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 { Bad_Opcode },
5467 { Bad_Opcode },
5468 { Bad_Opcode },
5469 { Bad_Opcode },
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 /* 60 */
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 { Bad_Opcode },
5476 { Bad_Opcode },
5477 { Bad_Opcode },
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 /* 68 */
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 /* 70 */
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 /* 78 */
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 /* 80 */
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 /* 88 */
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 { Bad_Opcode },
5524 { Bad_Opcode },
5525 { Bad_Opcode },
5526 /* 90 */
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 { Bad_Opcode },
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 /* 98 */
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 { Bad_Opcode },
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 /* a0 */
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 { Bad_Opcode },
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 /* a8 */
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 { Bad_Opcode },
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 /* b0 */
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 { Bad_Opcode },
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 /* b8 */
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 { Bad_Opcode },
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 /* c0 */
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 { Bad_Opcode },
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 /* c8 */
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 { Bad_Opcode },
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 /* d0 */
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 { Bad_Opcode },
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 /* d8 */
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 { Bad_Opcode },
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 /* e0 */
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 { Bad_Opcode },
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 /* e8 */
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 /* f0 */
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { Bad_Opcode },
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 /* f8 */
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 },
5653 };
5654
5655 static const struct dis386 vex_table[][256] = {
5656 /* VEX_0F */
5657 {
5658 /* 00 */
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 /* 08 */
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 /* 10 */
5677 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5678 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5679 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5680 { MOD_TABLE (MOD_VEX_0F13) },
5681 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5682 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5683 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5684 { MOD_TABLE (MOD_VEX_0F17) },
5685 /* 18 */
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 /* 20 */
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 /* 28 */
5704 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5705 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5706 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5707 { MOD_TABLE (MOD_VEX_0F2B) },
5708 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5709 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5710 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5711 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5712 /* 30 */
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 /* 38 */
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 /* 40 */
5731 { Bad_Opcode },
5732 { PREFIX_TABLE (PREFIX_VEX_0F41) },
5733 { PREFIX_TABLE (PREFIX_VEX_0F42) },
5734 { Bad_Opcode },
5735 { PREFIX_TABLE (PREFIX_VEX_0F44) },
5736 { PREFIX_TABLE (PREFIX_VEX_0F45) },
5737 { PREFIX_TABLE (PREFIX_VEX_0F46) },
5738 { PREFIX_TABLE (PREFIX_VEX_0F47) },
5739 /* 48 */
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5743 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 /* 50 */
5749 { MOD_TABLE (MOD_VEX_0F50) },
5750 { PREFIX_TABLE (PREFIX_VEX_0F51) },
5751 { PREFIX_TABLE (PREFIX_VEX_0F52) },
5752 { PREFIX_TABLE (PREFIX_VEX_0F53) },
5753 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5754 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5755 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5756 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5757 /* 58 */
5758 { PREFIX_TABLE (PREFIX_VEX_0F58) },
5759 { PREFIX_TABLE (PREFIX_VEX_0F59) },
5760 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5761 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5762 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5763 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5764 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5765 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5766 /* 60 */
5767 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
5768 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
5769 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
5770 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
5771 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
5772 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
5773 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
5774 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
5775 /* 68 */
5776 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
5777 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
5778 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
5779 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
5780 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
5781 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
5782 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5783 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5784 /* 70 */
5785 { PREFIX_TABLE (PREFIX_VEX_0F70) },
5786 { REG_TABLE (REG_VEX_0F71) },
5787 { REG_TABLE (REG_VEX_0F72) },
5788 { REG_TABLE (REG_VEX_0F73) },
5789 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
5790 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
5791 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
5792 { VEX_LEN_TABLE (VEX_LEN_0F77) },
5793 /* 78 */
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5799 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5800 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5801 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5802 /* 80 */
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 /* 88 */
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 /* 90 */
5821 { PREFIX_TABLE (PREFIX_VEX_0F90) },
5822 { PREFIX_TABLE (PREFIX_VEX_0F91) },
5823 { PREFIX_TABLE (PREFIX_VEX_0F92) },
5824 { PREFIX_TABLE (PREFIX_VEX_0F93) },
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 /* 98 */
5830 { PREFIX_TABLE (PREFIX_VEX_0F98) },
5831 { PREFIX_TABLE (PREFIX_VEX_0F99) },
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 /* a0 */
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 /* a8 */
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 { Bad_Opcode },
5851 { Bad_Opcode },
5852 { Bad_Opcode },
5853 { Bad_Opcode },
5854 { REG_TABLE (REG_VEX_0FAE) },
5855 { Bad_Opcode },
5856 /* b0 */
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 /* b8 */
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 /* c0 */
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
5878 { Bad_Opcode },
5879 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
5880 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
5881 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
5882 { Bad_Opcode },
5883 /* c8 */
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 /* d0 */
5893 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
5894 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
5895 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
5896 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
5897 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
5898 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
5899 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
5900 { MOD_TABLE (MOD_VEX_0FD7) },
5901 /* d8 */
5902 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
5903 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
5904 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
5905 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
5906 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
5907 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
5908 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
5909 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
5910 /* e0 */
5911 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
5912 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
5913 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
5914 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
5915 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
5916 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
5917 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
5918 { MOD_TABLE (MOD_VEX_0FE7) },
5919 /* e8 */
5920 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
5921 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
5922 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
5923 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
5924 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
5925 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
5926 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
5927 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
5928 /* f0 */
5929 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
5930 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
5931 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
5932 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
5933 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
5934 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
5935 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
5936 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
5937 /* f8 */
5938 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
5939 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
5940 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
5941 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
5942 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
5943 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
5944 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
5945 { Bad_Opcode },
5946 },
5947 /* VEX_0F38 */
5948 {
5949 /* 00 */
5950 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
5951 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
5952 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
5953 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
5954 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
5955 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
5956 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
5957 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
5958 /* 08 */
5959 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
5960 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
5961 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
5962 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
5963 { VEX_W_TABLE (VEX_W_0F380C) },
5964 { VEX_W_TABLE (VEX_W_0F380D) },
5965 { VEX_W_TABLE (VEX_W_0F380E) },
5966 { VEX_W_TABLE (VEX_W_0F380F) },
5967 /* 10 */
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 { Bad_Opcode },
5971 { VEX_W_TABLE (VEX_W_0F3813) },
5972 { Bad_Opcode },
5973 { Bad_Opcode },
5974 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
5975 { "vptest", { XM, EXx }, PREFIX_DATA },
5976 /* 18 */
5977 { VEX_W_TABLE (VEX_W_0F3818) },
5978 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
5979 { MOD_TABLE (MOD_VEX_0F381A) },
5980 { Bad_Opcode },
5981 { "vpabsb", { XM, EXx }, PREFIX_DATA },
5982 { "vpabsw", { XM, EXx }, PREFIX_DATA },
5983 { "vpabsd", { XM, EXx }, PREFIX_DATA },
5984 { Bad_Opcode },
5985 /* 20 */
5986 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
5987 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
5988 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
5989 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
5990 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
5991 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 /* 28 */
5995 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
5996 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
5997 { MOD_TABLE (MOD_VEX_0F382A) },
5998 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
5999 { MOD_TABLE (MOD_VEX_0F382C) },
6000 { MOD_TABLE (MOD_VEX_0F382D) },
6001 { MOD_TABLE (MOD_VEX_0F382E) },
6002 { MOD_TABLE (MOD_VEX_0F382F) },
6003 /* 30 */
6004 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6005 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6006 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6007 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6008 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6009 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6010 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6011 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6012 /* 38 */
6013 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6014 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6015 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6016 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6017 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6018 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6019 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6020 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6021 /* 40 */
6022 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6023 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6024 { Bad_Opcode },
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6028 { VEX_W_TABLE (VEX_W_0F3846) },
6029 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6030 /* 48 */
6031 { Bad_Opcode },
6032 { X86_64_TABLE (X86_64_VEX_0F3849) },
6033 { Bad_Opcode },
6034 { X86_64_TABLE (X86_64_VEX_0F384B) },
6035 { Bad_Opcode },
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 /* 50 */
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 { Bad_Opcode },
6047 { Bad_Opcode },
6048 /* 58 */
6049 { VEX_W_TABLE (VEX_W_0F3858) },
6050 { VEX_W_TABLE (VEX_W_0F3859) },
6051 { MOD_TABLE (MOD_VEX_0F385A) },
6052 { Bad_Opcode },
6053 { X86_64_TABLE (X86_64_VEX_0F385C) },
6054 { Bad_Opcode },
6055 { X86_64_TABLE (X86_64_VEX_0F385E) },
6056 { Bad_Opcode },
6057 /* 60 */
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 { Bad_Opcode },
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 /* 68 */
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 { Bad_Opcode },
6072 { Bad_Opcode },
6073 { Bad_Opcode },
6074 { Bad_Opcode },
6075 /* 70 */
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { Bad_Opcode },
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 { Bad_Opcode },
6082 { Bad_Opcode },
6083 { Bad_Opcode },
6084 /* 78 */
6085 { VEX_W_TABLE (VEX_W_0F3878) },
6086 { VEX_W_TABLE (VEX_W_0F3879) },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 { Bad_Opcode },
6091 { Bad_Opcode },
6092 { Bad_Opcode },
6093 /* 80 */
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 { Bad_Opcode },
6099 { Bad_Opcode },
6100 { Bad_Opcode },
6101 { Bad_Opcode },
6102 /* 88 */
6103 { Bad_Opcode },
6104 { Bad_Opcode },
6105 { Bad_Opcode },
6106 { Bad_Opcode },
6107 { MOD_TABLE (MOD_VEX_0F388C) },
6108 { Bad_Opcode },
6109 { MOD_TABLE (MOD_VEX_0F388E) },
6110 { Bad_Opcode },
6111 /* 90 */
6112 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6113 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6114 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6115 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6116 { Bad_Opcode },
6117 { Bad_Opcode },
6118 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6119 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6120 /* 98 */
6121 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6122 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6123 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6124 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6125 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6126 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6127 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6128 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6129 /* a0 */
6130 { Bad_Opcode },
6131 { Bad_Opcode },
6132 { Bad_Opcode },
6133 { Bad_Opcode },
6134 { Bad_Opcode },
6135 { Bad_Opcode },
6136 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6137 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6138 /* a8 */
6139 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6140 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6141 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6142 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6143 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6144 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6145 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6146 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6147 /* b0 */
6148 { Bad_Opcode },
6149 { Bad_Opcode },
6150 { Bad_Opcode },
6151 { Bad_Opcode },
6152 { Bad_Opcode },
6153 { Bad_Opcode },
6154 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6155 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6156 /* b8 */
6157 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6158 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6159 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6160 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6161 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6162 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6163 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6164 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6165 /* c0 */
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { Bad_Opcode },
6169 { Bad_Opcode },
6170 { Bad_Opcode },
6171 { Bad_Opcode },
6172 { Bad_Opcode },
6173 { Bad_Opcode },
6174 /* c8 */
6175 { Bad_Opcode },
6176 { Bad_Opcode },
6177 { Bad_Opcode },
6178 { Bad_Opcode },
6179 { Bad_Opcode },
6180 { Bad_Opcode },
6181 { Bad_Opcode },
6182 { VEX_W_TABLE (VEX_W_0F38CF) },
6183 /* d0 */
6184 { Bad_Opcode },
6185 { Bad_Opcode },
6186 { Bad_Opcode },
6187 { Bad_Opcode },
6188 { Bad_Opcode },
6189 { Bad_Opcode },
6190 { Bad_Opcode },
6191 { Bad_Opcode },
6192 /* d8 */
6193 { Bad_Opcode },
6194 { Bad_Opcode },
6195 { Bad_Opcode },
6196 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6197 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6198 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6199 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6200 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6201 /* e0 */
6202 { Bad_Opcode },
6203 { Bad_Opcode },
6204 { Bad_Opcode },
6205 { Bad_Opcode },
6206 { Bad_Opcode },
6207 { Bad_Opcode },
6208 { Bad_Opcode },
6209 { Bad_Opcode },
6210 /* e8 */
6211 { Bad_Opcode },
6212 { Bad_Opcode },
6213 { Bad_Opcode },
6214 { Bad_Opcode },
6215 { Bad_Opcode },
6216 { Bad_Opcode },
6217 { Bad_Opcode },
6218 { Bad_Opcode },
6219 /* f0 */
6220 { Bad_Opcode },
6221 { Bad_Opcode },
6222 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6223 { REG_TABLE (REG_VEX_0F38F3) },
6224 { Bad_Opcode },
6225 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6226 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6227 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6228 /* f8 */
6229 { Bad_Opcode },
6230 { Bad_Opcode },
6231 { Bad_Opcode },
6232 { Bad_Opcode },
6233 { Bad_Opcode },
6234 { Bad_Opcode },
6235 { Bad_Opcode },
6236 { Bad_Opcode },
6237 },
6238 /* VEX_0F3A */
6239 {
6240 /* 00 */
6241 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6242 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6243 { VEX_W_TABLE (VEX_W_0F3A02) },
6244 { Bad_Opcode },
6245 { VEX_W_TABLE (VEX_W_0F3A04) },
6246 { VEX_W_TABLE (VEX_W_0F3A05) },
6247 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6248 { Bad_Opcode },
6249 /* 08 */
6250 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6251 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6252 { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6253 { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6254 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6255 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6256 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6257 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6258 /* 10 */
6259 { Bad_Opcode },
6260 { Bad_Opcode },
6261 { Bad_Opcode },
6262 { Bad_Opcode },
6263 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6264 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6265 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6266 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6267 /* 18 */
6268 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6269 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6270 { Bad_Opcode },
6271 { Bad_Opcode },
6272 { Bad_Opcode },
6273 { VEX_W_TABLE (VEX_W_0F3A1D) },
6274 { Bad_Opcode },
6275 { Bad_Opcode },
6276 /* 20 */
6277 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6278 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6279 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6280 { Bad_Opcode },
6281 { Bad_Opcode },
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 /* 28 */
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 { Bad_Opcode },
6289 { Bad_Opcode },
6290 { Bad_Opcode },
6291 { Bad_Opcode },
6292 { Bad_Opcode },
6293 { Bad_Opcode },
6294 /* 30 */
6295 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6296 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6297 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6298 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6299 { Bad_Opcode },
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 { Bad_Opcode },
6303 /* 38 */
6304 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6305 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6306 { Bad_Opcode },
6307 { Bad_Opcode },
6308 { Bad_Opcode },
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 { Bad_Opcode },
6312 /* 40 */
6313 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6314 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6315 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6316 { Bad_Opcode },
6317 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6318 { Bad_Opcode },
6319 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6320 { Bad_Opcode },
6321 /* 48 */
6322 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6323 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6324 { VEX_W_TABLE (VEX_W_0F3A4A) },
6325 { VEX_W_TABLE (VEX_W_0F3A4B) },
6326 { VEX_W_TABLE (VEX_W_0F3A4C) },
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 /* 50 */
6331 { Bad_Opcode },
6332 { Bad_Opcode },
6333 { Bad_Opcode },
6334 { Bad_Opcode },
6335 { Bad_Opcode },
6336 { Bad_Opcode },
6337 { Bad_Opcode },
6338 { Bad_Opcode },
6339 /* 58 */
6340 { Bad_Opcode },
6341 { Bad_Opcode },
6342 { Bad_Opcode },
6343 { Bad_Opcode },
6344 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6345 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6346 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6347 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6348 /* 60 */
6349 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6350 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6351 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6352 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6353 { Bad_Opcode },
6354 { Bad_Opcode },
6355 { Bad_Opcode },
6356 { Bad_Opcode },
6357 /* 68 */
6358 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6359 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6360 { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6361 { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6362 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6363 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6364 { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6365 { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6366 /* 70 */
6367 { Bad_Opcode },
6368 { Bad_Opcode },
6369 { Bad_Opcode },
6370 { Bad_Opcode },
6371 { Bad_Opcode },
6372 { Bad_Opcode },
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 /* 78 */
6376 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6377 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6378 { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6379 { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6380 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6381 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6382 { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6383 { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6384 /* 80 */
6385 { Bad_Opcode },
6386 { Bad_Opcode },
6387 { Bad_Opcode },
6388 { Bad_Opcode },
6389 { Bad_Opcode },
6390 { Bad_Opcode },
6391 { Bad_Opcode },
6392 { Bad_Opcode },
6393 /* 88 */
6394 { Bad_Opcode },
6395 { Bad_Opcode },
6396 { Bad_Opcode },
6397 { Bad_Opcode },
6398 { Bad_Opcode },
6399 { Bad_Opcode },
6400 { Bad_Opcode },
6401 { Bad_Opcode },
6402 /* 90 */
6403 { Bad_Opcode },
6404 { Bad_Opcode },
6405 { Bad_Opcode },
6406 { Bad_Opcode },
6407 { Bad_Opcode },
6408 { Bad_Opcode },
6409 { Bad_Opcode },
6410 { Bad_Opcode },
6411 /* 98 */
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 { Bad_Opcode },
6417 { Bad_Opcode },
6418 { Bad_Opcode },
6419 { Bad_Opcode },
6420 /* a0 */
6421 { Bad_Opcode },
6422 { Bad_Opcode },
6423 { Bad_Opcode },
6424 { Bad_Opcode },
6425 { Bad_Opcode },
6426 { Bad_Opcode },
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 /* a8 */
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 { Bad_Opcode },
6435 { Bad_Opcode },
6436 { Bad_Opcode },
6437 { Bad_Opcode },
6438 /* b0 */
6439 { Bad_Opcode },
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { Bad_Opcode },
6443 { Bad_Opcode },
6444 { Bad_Opcode },
6445 { Bad_Opcode },
6446 { Bad_Opcode },
6447 /* b8 */
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 { Bad_Opcode },
6454 { Bad_Opcode },
6455 { Bad_Opcode },
6456 /* c0 */
6457 { Bad_Opcode },
6458 { Bad_Opcode },
6459 { Bad_Opcode },
6460 { Bad_Opcode },
6461 { Bad_Opcode },
6462 { Bad_Opcode },
6463 { Bad_Opcode },
6464 { Bad_Opcode },
6465 /* c8 */
6466 { Bad_Opcode },
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 { Bad_Opcode },
6472 { VEX_W_TABLE (VEX_W_0F3ACE) },
6473 { VEX_W_TABLE (VEX_W_0F3ACF) },
6474 /* d0 */
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 { Bad_Opcode },
6480 { Bad_Opcode },
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 /* d8 */
6484 { Bad_Opcode },
6485 { Bad_Opcode },
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 { Bad_Opcode },
6489 { Bad_Opcode },
6490 { Bad_Opcode },
6491 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6492 /* e0 */
6493 { Bad_Opcode },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 { Bad_Opcode },
6499 { Bad_Opcode },
6500 { Bad_Opcode },
6501 /* e8 */
6502 { Bad_Opcode },
6503 { Bad_Opcode },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { Bad_Opcode },
6507 { Bad_Opcode },
6508 { Bad_Opcode },
6509 { Bad_Opcode },
6510 /* f0 */
6511 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 { Bad_Opcode },
6517 { Bad_Opcode },
6518 { Bad_Opcode },
6519 /* f8 */
6520 { Bad_Opcode },
6521 { Bad_Opcode },
6522 { Bad_Opcode },
6523 { Bad_Opcode },
6524 { Bad_Opcode },
6525 { Bad_Opcode },
6526 { Bad_Opcode },
6527 { Bad_Opcode },
6528 },
6529 };
6530
6531 #include "i386-dis-evex.h"
6532
6533 static const struct dis386 vex_len_table[][2] = {
6534 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6535 {
6536 { "vmovlpX", { XM, Vex, EXq }, 0 },
6537 },
6538
6539 /* VEX_LEN_0F12_P_0_M_1 */
6540 {
6541 { "vmovhlps", { XM, Vex, EXq }, 0 },
6542 },
6543
6544 /* VEX_LEN_0F13_M_0 */
6545 {
6546 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6547 },
6548
6549 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6550 {
6551 { "vmovhpX", { XM, Vex, EXq }, 0 },
6552 },
6553
6554 /* VEX_LEN_0F16_P_0_M_1 */
6555 {
6556 { "vmovlhps", { XM, Vex, EXq }, 0 },
6557 },
6558
6559 /* VEX_LEN_0F17_M_0 */
6560 {
6561 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6562 },
6563
6564 /* VEX_LEN_0F41_P_0 */
6565 {
6566 { Bad_Opcode },
6567 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6568 },
6569 /* VEX_LEN_0F41_P_2 */
6570 {
6571 { Bad_Opcode },
6572 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6573 },
6574 /* VEX_LEN_0F42_P_0 */
6575 {
6576 { Bad_Opcode },
6577 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6578 },
6579 /* VEX_LEN_0F42_P_2 */
6580 {
6581 { Bad_Opcode },
6582 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6583 },
6584 /* VEX_LEN_0F44_P_0 */
6585 {
6586 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6587 },
6588 /* VEX_LEN_0F44_P_2 */
6589 {
6590 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6591 },
6592 /* VEX_LEN_0F45_P_0 */
6593 {
6594 { Bad_Opcode },
6595 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6596 },
6597 /* VEX_LEN_0F45_P_2 */
6598 {
6599 { Bad_Opcode },
6600 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6601 },
6602 /* VEX_LEN_0F46_P_0 */
6603 {
6604 { Bad_Opcode },
6605 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6606 },
6607 /* VEX_LEN_0F46_P_2 */
6608 {
6609 { Bad_Opcode },
6610 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6611 },
6612 /* VEX_LEN_0F47_P_0 */
6613 {
6614 { Bad_Opcode },
6615 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6616 },
6617 /* VEX_LEN_0F47_P_2 */
6618 {
6619 { Bad_Opcode },
6620 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6621 },
6622 /* VEX_LEN_0F4A_P_0 */
6623 {
6624 { Bad_Opcode },
6625 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6626 },
6627 /* VEX_LEN_0F4A_P_2 */
6628 {
6629 { Bad_Opcode },
6630 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6631 },
6632 /* VEX_LEN_0F4B_P_0 */
6633 {
6634 { Bad_Opcode },
6635 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6636 },
6637 /* VEX_LEN_0F4B_P_2 */
6638 {
6639 { Bad_Opcode },
6640 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6641 },
6642
6643 /* VEX_LEN_0F6E */
6644 {
6645 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6646 },
6647
6648 /* VEX_LEN_0F77 */
6649 {
6650 { "vzeroupper", { XX }, 0 },
6651 { "vzeroall", { XX }, 0 },
6652 },
6653
6654 /* VEX_LEN_0F7E_P_1 */
6655 {
6656 { "vmovq", { XMScalar, EXxmm_mq }, 0 },
6657 },
6658
6659 /* VEX_LEN_0F7E_P_2 */
6660 {
6661 { "vmovK", { Edq, XMScalar }, 0 },
6662 },
6663
6664 /* VEX_LEN_0F90_P_0 */
6665 {
6666 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6667 },
6668
6669 /* VEX_LEN_0F90_P_2 */
6670 {
6671 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6672 },
6673
6674 /* VEX_LEN_0F91_P_0 */
6675 {
6676 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6677 },
6678
6679 /* VEX_LEN_0F91_P_2 */
6680 {
6681 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6682 },
6683
6684 /* VEX_LEN_0F92_P_0 */
6685 {
6686 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6687 },
6688
6689 /* VEX_LEN_0F92_P_2 */
6690 {
6691 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6692 },
6693
6694 /* VEX_LEN_0F92_P_3 */
6695 {
6696 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6697 },
6698
6699 /* VEX_LEN_0F93_P_0 */
6700 {
6701 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6702 },
6703
6704 /* VEX_LEN_0F93_P_2 */
6705 {
6706 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6707 },
6708
6709 /* VEX_LEN_0F93_P_3 */
6710 {
6711 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6712 },
6713
6714 /* VEX_LEN_0F98_P_0 */
6715 {
6716 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6717 },
6718
6719 /* VEX_LEN_0F98_P_2 */
6720 {
6721 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6722 },
6723
6724 /* VEX_LEN_0F99_P_0 */
6725 {
6726 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6727 },
6728
6729 /* VEX_LEN_0F99_P_2 */
6730 {
6731 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6732 },
6733
6734 /* VEX_LEN_0FAE_R_2_M_0 */
6735 {
6736 { "vldmxcsr", { Md }, 0 },
6737 },
6738
6739 /* VEX_LEN_0FAE_R_3_M_0 */
6740 {
6741 { "vstmxcsr", { Md }, 0 },
6742 },
6743
6744 /* VEX_LEN_0FC4 */
6745 {
6746 { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6747 },
6748
6749 /* VEX_LEN_0FC5 */
6750 {
6751 { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
6752 },
6753
6754 /* VEX_LEN_0FD6 */
6755 {
6756 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6757 },
6758
6759 /* VEX_LEN_0FF7 */
6760 {
6761 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6762 },
6763
6764 /* VEX_LEN_0F3816 */
6765 {
6766 { Bad_Opcode },
6767 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6768 },
6769
6770 /* VEX_LEN_0F3819 */
6771 {
6772 { Bad_Opcode },
6773 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6774 },
6775
6776 /* VEX_LEN_0F381A_M_0 */
6777 {
6778 { Bad_Opcode },
6779 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6780 },
6781
6782 /* VEX_LEN_0F3836 */
6783 {
6784 { Bad_Opcode },
6785 { VEX_W_TABLE (VEX_W_0F3836) },
6786 },
6787
6788 /* VEX_LEN_0F3841 */
6789 {
6790 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
6791 },
6792
6793 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6794 {
6795 { "ldtilecfg", { M }, 0 },
6796 },
6797
6798 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6799 {
6800 { "tilerelease", { Skip_MODRM }, 0 },
6801 },
6802
6803 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6804 {
6805 { "sttilecfg", { M }, 0 },
6806 },
6807
6808 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6809 {
6810 { "tilezero", { TMM, Skip_MODRM }, 0 },
6811 },
6812
6813 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6814 {
6815 { "tilestored", { MVexSIBMEM, TMM }, 0 },
6816 },
6817 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6818 {
6819 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6820 },
6821
6822 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6823 {
6824 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6825 },
6826
6827 /* VEX_LEN_0F385A_M_0 */
6828 {
6829 { Bad_Opcode },
6830 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6831 },
6832
6833 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6834 {
6835 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6836 },
6837
6838 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6839 {
6840 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6841 },
6842
6843 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6844 {
6845 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6846 },
6847
6848 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6849 {
6850 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6851 },
6852
6853 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6854 {
6855 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6856 },
6857
6858 /* VEX_LEN_0F38DB */
6859 {
6860 { "vaesimc", { XM, EXx }, PREFIX_DATA },
6861 },
6862
6863 /* VEX_LEN_0F38F2 */
6864 {
6865 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6866 },
6867
6868 /* VEX_LEN_0F38F3_R_1 */
6869 {
6870 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
6871 },
6872
6873 /* VEX_LEN_0F38F3_R_2 */
6874 {
6875 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
6876 },
6877
6878 /* VEX_LEN_0F38F3_R_3 */
6879 {
6880 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
6881 },
6882
6883 /* VEX_LEN_0F38F5_P_0 */
6884 {
6885 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
6886 },
6887
6888 /* VEX_LEN_0F38F5_P_1 */
6889 {
6890 { "pextS", { Gdq, VexGdq, Edq }, 0 },
6891 },
6892
6893 /* VEX_LEN_0F38F5_P_3 */
6894 {
6895 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
6896 },
6897
6898 /* VEX_LEN_0F38F6_P_3 */
6899 {
6900 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
6901 },
6902
6903 /* VEX_LEN_0F38F7_P_0 */
6904 {
6905 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
6906 },
6907
6908 /* VEX_LEN_0F38F7_P_1 */
6909 {
6910 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
6911 },
6912
6913 /* VEX_LEN_0F38F7_P_2 */
6914 {
6915 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
6916 },
6917
6918 /* VEX_LEN_0F38F7_P_3 */
6919 {
6920 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
6921 },
6922
6923 /* VEX_LEN_0F3A00 */
6924 {
6925 { Bad_Opcode },
6926 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
6927 },
6928
6929 /* VEX_LEN_0F3A01 */
6930 {
6931 { Bad_Opcode },
6932 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
6933 },
6934
6935 /* VEX_LEN_0F3A06 */
6936 {
6937 { Bad_Opcode },
6938 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
6939 },
6940
6941 /* VEX_LEN_0F3A14 */
6942 {
6943 { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
6944 },
6945
6946 /* VEX_LEN_0F3A15 */
6947 {
6948 { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
6949 },
6950
6951 /* VEX_LEN_0F3A16 */
6952 {
6953 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
6954 },
6955
6956 /* VEX_LEN_0F3A17 */
6957 {
6958 { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
6959 },
6960
6961 /* VEX_LEN_0F3A18 */
6962 {
6963 { Bad_Opcode },
6964 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
6965 },
6966
6967 /* VEX_LEN_0F3A19 */
6968 {
6969 { Bad_Opcode },
6970 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
6971 },
6972
6973 /* VEX_LEN_0F3A20 */
6974 {
6975 { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
6976 },
6977
6978 /* VEX_LEN_0F3A21 */
6979 {
6980 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
6981 },
6982
6983 /* VEX_LEN_0F3A22 */
6984 {
6985 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
6986 },
6987
6988 /* VEX_LEN_0F3A30 */
6989 {
6990 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
6991 },
6992
6993 /* VEX_LEN_0F3A31 */
6994 {
6995 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
6996 },
6997
6998 /* VEX_LEN_0F3A32 */
6999 {
7000 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7001 },
7002
7003 /* VEX_LEN_0F3A33 */
7004 {
7005 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7006 },
7007
7008 /* VEX_LEN_0F3A38 */
7009 {
7010 { Bad_Opcode },
7011 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7012 },
7013
7014 /* VEX_LEN_0F3A39 */
7015 {
7016 { Bad_Opcode },
7017 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7018 },
7019
7020 /* VEX_LEN_0F3A41 */
7021 {
7022 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7023 },
7024
7025 /* VEX_LEN_0F3A46 */
7026 {
7027 { Bad_Opcode },
7028 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7029 },
7030
7031 /* VEX_LEN_0F3A60 */
7032 {
7033 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7034 },
7035
7036 /* VEX_LEN_0F3A61 */
7037 {
7038 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7039 },
7040
7041 /* VEX_LEN_0F3A62 */
7042 {
7043 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7044 },
7045
7046 /* VEX_LEN_0F3A63 */
7047 {
7048 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7049 },
7050
7051 /* VEX_LEN_0F3ADF */
7052 {
7053 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7054 },
7055
7056 /* VEX_LEN_0F3AF0_P_3 */
7057 {
7058 { "rorxS", { Gdq, Edq, Ib }, 0 },
7059 },
7060
7061 /* VEX_LEN_0FXOP_08_85 */
7062 {
7063 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7064 },
7065
7066 /* VEX_LEN_0FXOP_08_86 */
7067 {
7068 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7069 },
7070
7071 /* VEX_LEN_0FXOP_08_87 */
7072 {
7073 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7074 },
7075
7076 /* VEX_LEN_0FXOP_08_8E */
7077 {
7078 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7079 },
7080
7081 /* VEX_LEN_0FXOP_08_8F */
7082 {
7083 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7084 },
7085
7086 /* VEX_LEN_0FXOP_08_95 */
7087 {
7088 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7089 },
7090
7091 /* VEX_LEN_0FXOP_08_96 */
7092 {
7093 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7094 },
7095
7096 /* VEX_LEN_0FXOP_08_97 */
7097 {
7098 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7099 },
7100
7101 /* VEX_LEN_0FXOP_08_9E */
7102 {
7103 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7104 },
7105
7106 /* VEX_LEN_0FXOP_08_9F */
7107 {
7108 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7109 },
7110
7111 /* VEX_LEN_0FXOP_08_A3 */
7112 {
7113 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7114 },
7115
7116 /* VEX_LEN_0FXOP_08_A6 */
7117 {
7118 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7119 },
7120
7121 /* VEX_LEN_0FXOP_08_B6 */
7122 {
7123 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7124 },
7125
7126 /* VEX_LEN_0FXOP_08_C0 */
7127 {
7128 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7129 },
7130
7131 /* VEX_LEN_0FXOP_08_C1 */
7132 {
7133 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7134 },
7135
7136 /* VEX_LEN_0FXOP_08_C2 */
7137 {
7138 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7139 },
7140
7141 /* VEX_LEN_0FXOP_08_C3 */
7142 {
7143 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7144 },
7145
7146 /* VEX_LEN_0FXOP_08_CC */
7147 {
7148 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7149 },
7150
7151 /* VEX_LEN_0FXOP_08_CD */
7152 {
7153 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7154 },
7155
7156 /* VEX_LEN_0FXOP_08_CE */
7157 {
7158 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7159 },
7160
7161 /* VEX_LEN_0FXOP_08_CF */
7162 {
7163 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7164 },
7165
7166 /* VEX_LEN_0FXOP_08_EC */
7167 {
7168 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7169 },
7170
7171 /* VEX_LEN_0FXOP_08_ED */
7172 {
7173 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7174 },
7175
7176 /* VEX_LEN_0FXOP_08_EE */
7177 {
7178 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7179 },
7180
7181 /* VEX_LEN_0FXOP_08_EF */
7182 {
7183 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7184 },
7185
7186 /* VEX_LEN_0FXOP_09_01 */
7187 {
7188 { REG_TABLE (REG_0FXOP_09_01_L_0) },
7189 },
7190
7191 /* VEX_LEN_0FXOP_09_02 */
7192 {
7193 { REG_TABLE (REG_0FXOP_09_02_L_0) },
7194 },
7195
7196 /* VEX_LEN_0FXOP_09_12_M_1 */
7197 {
7198 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7199 },
7200
7201 /* VEX_LEN_0FXOP_09_82_W_0 */
7202 {
7203 { "vfrczss", { XM, EXd }, 0 },
7204 },
7205
7206 /* VEX_LEN_0FXOP_09_83_W_0 */
7207 {
7208 { "vfrczsd", { XM, EXq }, 0 },
7209 },
7210
7211 /* VEX_LEN_0FXOP_09_90 */
7212 {
7213 { "vprotb", { XM, EXx, VexW }, 0 },
7214 },
7215
7216 /* VEX_LEN_0FXOP_09_91 */
7217 {
7218 { "vprotw", { XM, EXx, VexW }, 0 },
7219 },
7220
7221 /* VEX_LEN_0FXOP_09_92 */
7222 {
7223 { "vprotd", { XM, EXx, VexW }, 0 },
7224 },
7225
7226 /* VEX_LEN_0FXOP_09_93 */
7227 {
7228 { "vprotq", { XM, EXx, VexW }, 0 },
7229 },
7230
7231 /* VEX_LEN_0FXOP_09_94 */
7232 {
7233 { "vpshlb", { XM, EXx, VexW }, 0 },
7234 },
7235
7236 /* VEX_LEN_0FXOP_09_95 */
7237 {
7238 { "vpshlw", { XM, EXx, VexW }, 0 },
7239 },
7240
7241 /* VEX_LEN_0FXOP_09_96 */
7242 {
7243 { "vpshld", { XM, EXx, VexW }, 0 },
7244 },
7245
7246 /* VEX_LEN_0FXOP_09_97 */
7247 {
7248 { "vpshlq", { XM, EXx, VexW }, 0 },
7249 },
7250
7251 /* VEX_LEN_0FXOP_09_98 */
7252 {
7253 { "vpshab", { XM, EXx, VexW }, 0 },
7254 },
7255
7256 /* VEX_LEN_0FXOP_09_99 */
7257 {
7258 { "vpshaw", { XM, EXx, VexW }, 0 },
7259 },
7260
7261 /* VEX_LEN_0FXOP_09_9A */
7262 {
7263 { "vpshad", { XM, EXx, VexW }, 0 },
7264 },
7265
7266 /* VEX_LEN_0FXOP_09_9B */
7267 {
7268 { "vpshaq", { XM, EXx, VexW }, 0 },
7269 },
7270
7271 /* VEX_LEN_0FXOP_09_C1 */
7272 {
7273 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7274 },
7275
7276 /* VEX_LEN_0FXOP_09_C2 */
7277 {
7278 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7279 },
7280
7281 /* VEX_LEN_0FXOP_09_C3 */
7282 {
7283 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7284 },
7285
7286 /* VEX_LEN_0FXOP_09_C6 */
7287 {
7288 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7289 },
7290
7291 /* VEX_LEN_0FXOP_09_C7 */
7292 {
7293 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7294 },
7295
7296 /* VEX_LEN_0FXOP_09_CB */
7297 {
7298 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7299 },
7300
7301 /* VEX_LEN_0FXOP_09_D1 */
7302 {
7303 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7304 },
7305
7306 /* VEX_LEN_0FXOP_09_D2 */
7307 {
7308 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7309 },
7310
7311 /* VEX_LEN_0FXOP_09_D3 */
7312 {
7313 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7314 },
7315
7316 /* VEX_LEN_0FXOP_09_D6 */
7317 {
7318 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7319 },
7320
7321 /* VEX_LEN_0FXOP_09_D7 */
7322 {
7323 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7324 },
7325
7326 /* VEX_LEN_0FXOP_09_DB */
7327 {
7328 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7329 },
7330
7331 /* VEX_LEN_0FXOP_09_E1 */
7332 {
7333 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7334 },
7335
7336 /* VEX_LEN_0FXOP_09_E2 */
7337 {
7338 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7339 },
7340
7341 /* VEX_LEN_0FXOP_09_E3 */
7342 {
7343 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7344 },
7345
7346 /* VEX_LEN_0FXOP_0A_12 */
7347 {
7348 { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7349 },
7350 };
7351
7352 #include "i386-dis-evex-len.h"
7353
7354 static const struct dis386 vex_w_table[][2] = {
7355 {
7356 /* VEX_W_0F41_P_0_LEN_1 */
7357 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7358 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7359 },
7360 {
7361 /* VEX_W_0F41_P_2_LEN_1 */
7362 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7363 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7364 },
7365 {
7366 /* VEX_W_0F42_P_0_LEN_1 */
7367 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7368 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7369 },
7370 {
7371 /* VEX_W_0F42_P_2_LEN_1 */
7372 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7373 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7374 },
7375 {
7376 /* VEX_W_0F44_P_0_LEN_0 */
7377 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7378 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7379 },
7380 {
7381 /* VEX_W_0F44_P_2_LEN_0 */
7382 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7383 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7384 },
7385 {
7386 /* VEX_W_0F45_P_0_LEN_1 */
7387 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7388 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7389 },
7390 {
7391 /* VEX_W_0F45_P_2_LEN_1 */
7392 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7393 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7394 },
7395 {
7396 /* VEX_W_0F46_P_0_LEN_1 */
7397 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7398 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7399 },
7400 {
7401 /* VEX_W_0F46_P_2_LEN_1 */
7402 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7403 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7404 },
7405 {
7406 /* VEX_W_0F47_P_0_LEN_1 */
7407 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7408 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7409 },
7410 {
7411 /* VEX_W_0F47_P_2_LEN_1 */
7412 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7413 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7414 },
7415 {
7416 /* VEX_W_0F4A_P_0_LEN_1 */
7417 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7418 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7419 },
7420 {
7421 /* VEX_W_0F4A_P_2_LEN_1 */
7422 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7423 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7424 },
7425 {
7426 /* VEX_W_0F4B_P_0_LEN_1 */
7427 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7428 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7429 },
7430 {
7431 /* VEX_W_0F4B_P_2_LEN_1 */
7432 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7433 },
7434 {
7435 /* VEX_W_0F90_P_0_LEN_0 */
7436 { "kmovw", { MaskG, MaskE }, 0 },
7437 { "kmovq", { MaskG, MaskE }, 0 },
7438 },
7439 {
7440 /* VEX_W_0F90_P_2_LEN_0 */
7441 { "kmovb", { MaskG, MaskBDE }, 0 },
7442 { "kmovd", { MaskG, MaskBDE }, 0 },
7443 },
7444 {
7445 /* VEX_W_0F91_P_0_LEN_0 */
7446 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7447 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7448 },
7449 {
7450 /* VEX_W_0F91_P_2_LEN_0 */
7451 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7452 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7453 },
7454 {
7455 /* VEX_W_0F92_P_0_LEN_0 */
7456 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7457 },
7458 {
7459 /* VEX_W_0F92_P_2_LEN_0 */
7460 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7461 },
7462 {
7463 /* VEX_W_0F93_P_0_LEN_0 */
7464 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7465 },
7466 {
7467 /* VEX_W_0F93_P_2_LEN_0 */
7468 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7469 },
7470 {
7471 /* VEX_W_0F98_P_0_LEN_0 */
7472 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7473 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7474 },
7475 {
7476 /* VEX_W_0F98_P_2_LEN_0 */
7477 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7478 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7479 },
7480 {
7481 /* VEX_W_0F99_P_0_LEN_0 */
7482 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7483 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7484 },
7485 {
7486 /* VEX_W_0F99_P_2_LEN_0 */
7487 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7488 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7489 },
7490 {
7491 /* VEX_W_0F380C */
7492 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7493 },
7494 {
7495 /* VEX_W_0F380D */
7496 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7497 },
7498 {
7499 /* VEX_W_0F380E */
7500 { "vtestps", { XM, EXx }, PREFIX_DATA },
7501 },
7502 {
7503 /* VEX_W_0F380F */
7504 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7505 },
7506 {
7507 /* VEX_W_0F3813 */
7508 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7509 },
7510 {
7511 /* VEX_W_0F3816_L_1 */
7512 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7513 },
7514 {
7515 /* VEX_W_0F3818 */
7516 { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
7517 },
7518 {
7519 /* VEX_W_0F3819_L_1 */
7520 { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
7521 },
7522 {
7523 /* VEX_W_0F381A_M_0_L_1 */
7524 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7525 },
7526 {
7527 /* VEX_W_0F382C_M_0 */
7528 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7529 },
7530 {
7531 /* VEX_W_0F382D_M_0 */
7532 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7533 },
7534 {
7535 /* VEX_W_0F382E_M_0 */
7536 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7537 },
7538 {
7539 /* VEX_W_0F382F_M_0 */
7540 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7541 },
7542 {
7543 /* VEX_W_0F3836 */
7544 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7545 },
7546 {
7547 /* VEX_W_0F3846 */
7548 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7549 },
7550 {
7551 /* VEX_W_0F3849_X86_64_P_0 */
7552 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7553 },
7554 {
7555 /* VEX_W_0F3849_X86_64_P_2 */
7556 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7557 },
7558 {
7559 /* VEX_W_0F3849_X86_64_P_3 */
7560 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7561 },
7562 {
7563 /* VEX_W_0F384B_X86_64_P_1 */
7564 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7565 },
7566 {
7567 /* VEX_W_0F384B_X86_64_P_2 */
7568 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7569 },
7570 {
7571 /* VEX_W_0F384B_X86_64_P_3 */
7572 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7573 },
7574 {
7575 /* VEX_W_0F3858 */
7576 { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7577 },
7578 {
7579 /* VEX_W_0F3859 */
7580 { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
7581 },
7582 {
7583 /* VEX_W_0F385A_M_0_L_0 */
7584 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7585 },
7586 {
7587 /* VEX_W_0F385C_X86_64_P_1 */
7588 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7589 },
7590 {
7591 /* VEX_W_0F385E_X86_64_P_0 */
7592 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7593 },
7594 {
7595 /* VEX_W_0F385E_X86_64_P_1 */
7596 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7597 },
7598 {
7599 /* VEX_W_0F385E_X86_64_P_2 */
7600 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7601 },
7602 {
7603 /* VEX_W_0F385E_X86_64_P_3 */
7604 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7605 },
7606 {
7607 /* VEX_W_0F3878 */
7608 { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
7609 },
7610 {
7611 /* VEX_W_0F3879 */
7612 { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
7613 },
7614 {
7615 /* VEX_W_0F38CF */
7616 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7617 },
7618 {
7619 /* VEX_W_0F3A00_L_1 */
7620 { Bad_Opcode },
7621 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7622 },
7623 {
7624 /* VEX_W_0F3A01_L_1 */
7625 { Bad_Opcode },
7626 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7627 },
7628 {
7629 /* VEX_W_0F3A02 */
7630 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7631 },
7632 {
7633 /* VEX_W_0F3A04 */
7634 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7635 },
7636 {
7637 /* VEX_W_0F3A05 */
7638 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7639 },
7640 {
7641 /* VEX_W_0F3A06_L_1 */
7642 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7643 },
7644 {
7645 /* VEX_W_0F3A18_L_1 */
7646 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7647 },
7648 {
7649 /* VEX_W_0F3A19_L_1 */
7650 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7651 },
7652 {
7653 /* VEX_W_0F3A1D */
7654 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7655 },
7656 {
7657 /* VEX_W_0F3A38_L_1 */
7658 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7659 },
7660 {
7661 /* VEX_W_0F3A39_L_1 */
7662 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7663 },
7664 {
7665 /* VEX_W_0F3A46_L_1 */
7666 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7667 },
7668 {
7669 /* VEX_W_0F3A4A */
7670 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7671 },
7672 {
7673 /* VEX_W_0F3A4B */
7674 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7675 },
7676 {
7677 /* VEX_W_0F3A4C */
7678 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7679 },
7680 {
7681 /* VEX_W_0F3ACE */
7682 { Bad_Opcode },
7683 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7684 },
7685 {
7686 /* VEX_W_0F3ACF */
7687 { Bad_Opcode },
7688 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7689 },
7690 /* VEX_W_0FXOP_08_85_L_0 */
7691 {
7692 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7693 },
7694 /* VEX_W_0FXOP_08_86_L_0 */
7695 {
7696 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7697 },
7698 /* VEX_W_0FXOP_08_87_L_0 */
7699 {
7700 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7701 },
7702 /* VEX_W_0FXOP_08_8E_L_0 */
7703 {
7704 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7705 },
7706 /* VEX_W_0FXOP_08_8F_L_0 */
7707 {
7708 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7709 },
7710 /* VEX_W_0FXOP_08_95_L_0 */
7711 {
7712 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7713 },
7714 /* VEX_W_0FXOP_08_96_L_0 */
7715 {
7716 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7717 },
7718 /* VEX_W_0FXOP_08_97_L_0 */
7719 {
7720 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7721 },
7722 /* VEX_W_0FXOP_08_9E_L_0 */
7723 {
7724 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7725 },
7726 /* VEX_W_0FXOP_08_9F_L_0 */
7727 {
7728 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7729 },
7730 /* VEX_W_0FXOP_08_A6_L_0 */
7731 {
7732 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7733 },
7734 /* VEX_W_0FXOP_08_B6_L_0 */
7735 {
7736 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7737 },
7738 /* VEX_W_0FXOP_08_C0_L_0 */
7739 {
7740 { "vprotb", { XM, EXx, Ib }, 0 },
7741 },
7742 /* VEX_W_0FXOP_08_C1_L_0 */
7743 {
7744 { "vprotw", { XM, EXx, Ib }, 0 },
7745 },
7746 /* VEX_W_0FXOP_08_C2_L_0 */
7747 {
7748 { "vprotd", { XM, EXx, Ib }, 0 },
7749 },
7750 /* VEX_W_0FXOP_08_C3_L_0 */
7751 {
7752 { "vprotq", { XM, EXx, Ib }, 0 },
7753 },
7754 /* VEX_W_0FXOP_08_CC_L_0 */
7755 {
7756 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7757 },
7758 /* VEX_W_0FXOP_08_CD_L_0 */
7759 {
7760 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7761 },
7762 /* VEX_W_0FXOP_08_CE_L_0 */
7763 {
7764 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7765 },
7766 /* VEX_W_0FXOP_08_CF_L_0 */
7767 {
7768 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7769 },
7770 /* VEX_W_0FXOP_08_EC_L_0 */
7771 {
7772 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7773 },
7774 /* VEX_W_0FXOP_08_ED_L_0 */
7775 {
7776 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7777 },
7778 /* VEX_W_0FXOP_08_EE_L_0 */
7779 {
7780 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7781 },
7782 /* VEX_W_0FXOP_08_EF_L_0 */
7783 {
7784 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7785 },
7786 /* VEX_W_0FXOP_09_80 */
7787 {
7788 { "vfrczps", { XM, EXx }, 0 },
7789 },
7790 /* VEX_W_0FXOP_09_81 */
7791 {
7792 { "vfrczpd", { XM, EXx }, 0 },
7793 },
7794 /* VEX_W_0FXOP_09_82 */
7795 {
7796 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7797 },
7798 /* VEX_W_0FXOP_09_83 */
7799 {
7800 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7801 },
7802 /* VEX_W_0FXOP_09_C1_L_0 */
7803 {
7804 { "vphaddbw", { XM, EXxmm }, 0 },
7805 },
7806 /* VEX_W_0FXOP_09_C2_L_0 */
7807 {
7808 { "vphaddbd", { XM, EXxmm }, 0 },
7809 },
7810 /* VEX_W_0FXOP_09_C3_L_0 */
7811 {
7812 { "vphaddbq", { XM, EXxmm }, 0 },
7813 },
7814 /* VEX_W_0FXOP_09_C6_L_0 */
7815 {
7816 { "vphaddwd", { XM, EXxmm }, 0 },
7817 },
7818 /* VEX_W_0FXOP_09_C7_L_0 */
7819 {
7820 { "vphaddwq", { XM, EXxmm }, 0 },
7821 },
7822 /* VEX_W_0FXOP_09_CB_L_0 */
7823 {
7824 { "vphadddq", { XM, EXxmm }, 0 },
7825 },
7826 /* VEX_W_0FXOP_09_D1_L_0 */
7827 {
7828 { "vphaddubw", { XM, EXxmm }, 0 },
7829 },
7830 /* VEX_W_0FXOP_09_D2_L_0 */
7831 {
7832 { "vphaddubd", { XM, EXxmm }, 0 },
7833 },
7834 /* VEX_W_0FXOP_09_D3_L_0 */
7835 {
7836 { "vphaddubq", { XM, EXxmm }, 0 },
7837 },
7838 /* VEX_W_0FXOP_09_D6_L_0 */
7839 {
7840 { "vphadduwd", { XM, EXxmm }, 0 },
7841 },
7842 /* VEX_W_0FXOP_09_D7_L_0 */
7843 {
7844 { "vphadduwq", { XM, EXxmm }, 0 },
7845 },
7846 /* VEX_W_0FXOP_09_DB_L_0 */
7847 {
7848 { "vphaddudq", { XM, EXxmm }, 0 },
7849 },
7850 /* VEX_W_0FXOP_09_E1_L_0 */
7851 {
7852 { "vphsubbw", { XM, EXxmm }, 0 },
7853 },
7854 /* VEX_W_0FXOP_09_E2_L_0 */
7855 {
7856 { "vphsubwd", { XM, EXxmm }, 0 },
7857 },
7858 /* VEX_W_0FXOP_09_E3_L_0 */
7859 {
7860 { "vphsubdq", { XM, EXxmm }, 0 },
7861 },
7862
7863 #include "i386-dis-evex-w.h"
7864 };
7865
7866 static const struct dis386 mod_table[][2] = {
7867 {
7868 /* MOD_8D */
7869 { "leaS", { Gv, M }, 0 },
7870 },
7871 {
7872 /* MOD_C6_REG_7 */
7873 { Bad_Opcode },
7874 { RM_TABLE (RM_C6_REG_7) },
7875 },
7876 {
7877 /* MOD_C7_REG_7 */
7878 { Bad_Opcode },
7879 { RM_TABLE (RM_C7_REG_7) },
7880 },
7881 {
7882 /* MOD_FF_REG_3 */
7883 { "{l|}call^", { indirEp }, 0 },
7884 },
7885 {
7886 /* MOD_FF_REG_5 */
7887 { "{l|}jmp^", { indirEp }, 0 },
7888 },
7889 {
7890 /* MOD_0F01_REG_0 */
7891 { X86_64_TABLE (X86_64_0F01_REG_0) },
7892 { RM_TABLE (RM_0F01_REG_0) },
7893 },
7894 {
7895 /* MOD_0F01_REG_1 */
7896 { X86_64_TABLE (X86_64_0F01_REG_1) },
7897 { RM_TABLE (RM_0F01_REG_1) },
7898 },
7899 {
7900 /* MOD_0F01_REG_2 */
7901 { X86_64_TABLE (X86_64_0F01_REG_2) },
7902 { RM_TABLE (RM_0F01_REG_2) },
7903 },
7904 {
7905 /* MOD_0F01_REG_3 */
7906 { X86_64_TABLE (X86_64_0F01_REG_3) },
7907 { RM_TABLE (RM_0F01_REG_3) },
7908 },
7909 {
7910 /* MOD_0F01_REG_5 */
7911 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7912 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7913 },
7914 {
7915 /* MOD_0F01_REG_7 */
7916 { "invlpg", { Mb }, 0 },
7917 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7918 },
7919 {
7920 /* MOD_0F12_PREFIX_0 */
7921 { "movlpX", { XM, EXq }, 0 },
7922 { "movhlps", { XM, EXq }, 0 },
7923 },
7924 {
7925 /* MOD_0F12_PREFIX_2 */
7926 { "movlpX", { XM, EXq }, 0 },
7927 },
7928 {
7929 /* MOD_0F13 */
7930 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
7931 },
7932 {
7933 /* MOD_0F16_PREFIX_0 */
7934 { "movhpX", { XM, EXq }, 0 },
7935 { "movlhps", { XM, EXq }, 0 },
7936 },
7937 {
7938 /* MOD_0F16_PREFIX_2 */
7939 { "movhpX", { XM, EXq }, 0 },
7940 },
7941 {
7942 /* MOD_0F17 */
7943 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
7944 },
7945 {
7946 /* MOD_0F18_REG_0 */
7947 { "prefetchnta", { Mb }, 0 },
7948 },
7949 {
7950 /* MOD_0F18_REG_1 */
7951 { "prefetcht0", { Mb }, 0 },
7952 },
7953 {
7954 /* MOD_0F18_REG_2 */
7955 { "prefetcht1", { Mb }, 0 },
7956 },
7957 {
7958 /* MOD_0F18_REG_3 */
7959 { "prefetcht2", { Mb }, 0 },
7960 },
7961 {
7962 /* MOD_0F18_REG_4 */
7963 { "nop/reserved", { Mb }, 0 },
7964 },
7965 {
7966 /* MOD_0F18_REG_5 */
7967 { "nop/reserved", { Mb }, 0 },
7968 },
7969 {
7970 /* MOD_0F18_REG_6 */
7971 { "nop/reserved", { Mb }, 0 },
7972 },
7973 {
7974 /* MOD_0F18_REG_7 */
7975 { "nop/reserved", { Mb }, 0 },
7976 },
7977 {
7978 /* MOD_0F1A_PREFIX_0 */
7979 { "bndldx", { Gbnd, Mv_bnd }, 0 },
7980 { "nopQ", { Ev }, 0 },
7981 },
7982 {
7983 /* MOD_0F1B_PREFIX_0 */
7984 { "bndstx", { Mv_bnd, Gbnd }, 0 },
7985 { "nopQ", { Ev }, 0 },
7986 },
7987 {
7988 /* MOD_0F1B_PREFIX_1 */
7989 { "bndmk", { Gbnd, Mv_bnd }, 0 },
7990 { "nopQ", { Ev }, 0 },
7991 },
7992 {
7993 /* MOD_0F1C_PREFIX_0 */
7994 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
7995 { "nopQ", { Ev }, 0 },
7996 },
7997 {
7998 /* MOD_0F1E_PREFIX_1 */
7999 { "nopQ", { Ev }, 0 },
8000 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8001 },
8002 {
8003 /* MOD_0F2B_PREFIX_0 */
8004 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8005 },
8006 {
8007 /* MOD_0F2B_PREFIX_1 */
8008 {"movntss", { Md, XM }, PREFIX_OPCODE },
8009 },
8010 {
8011 /* MOD_0F2B_PREFIX_2 */
8012 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8013 },
8014 {
8015 /* MOD_0F2B_PREFIX_3 */
8016 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8017 },
8018 {
8019 /* MOD_0F50 */
8020 { Bad_Opcode },
8021 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8022 },
8023 {
8024 /* MOD_0F71_REG_2 */
8025 { Bad_Opcode },
8026 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
8027 },
8028 {
8029 /* MOD_0F71_REG_4 */
8030 { Bad_Opcode },
8031 { "psraw", { MS, Ib }, PREFIX_OPCODE },
8032 },
8033 {
8034 /* MOD_0F71_REG_6 */
8035 { Bad_Opcode },
8036 { "psllw", { MS, Ib }, PREFIX_OPCODE },
8037 },
8038 {
8039 /* MOD_0F72_REG_2 */
8040 { Bad_Opcode },
8041 { "psrld", { MS, Ib }, PREFIX_OPCODE },
8042 },
8043 {
8044 /* MOD_0F72_REG_4 */
8045 { Bad_Opcode },
8046 { "psrad", { MS, Ib }, PREFIX_OPCODE },
8047 },
8048 {
8049 /* MOD_0F72_REG_6 */
8050 { Bad_Opcode },
8051 { "pslld", { MS, Ib }, PREFIX_OPCODE },
8052 },
8053 {
8054 /* MOD_0F73_REG_2 */
8055 { Bad_Opcode },
8056 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
8057 },
8058 {
8059 /* MOD_0F73_REG_3 */
8060 { Bad_Opcode },
8061 { "psrldq", { XS, Ib }, PREFIX_DATA },
8062 },
8063 {
8064 /* MOD_0F73_REG_6 */
8065 { Bad_Opcode },
8066 { "psllq", { MS, Ib }, PREFIX_OPCODE },
8067 },
8068 {
8069 /* MOD_0F73_REG_7 */
8070 { Bad_Opcode },
8071 { "pslldq", { XS, Ib }, PREFIX_DATA },
8072 },
8073 {
8074 /* MOD_0FAE_REG_0 */
8075 { "fxsave", { FXSAVE }, 0 },
8076 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8077 },
8078 {
8079 /* MOD_0FAE_REG_1 */
8080 { "fxrstor", { FXSAVE }, 0 },
8081 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8082 },
8083 {
8084 /* MOD_0FAE_REG_2 */
8085 { "ldmxcsr", { Md }, 0 },
8086 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8087 },
8088 {
8089 /* MOD_0FAE_REG_3 */
8090 { "stmxcsr", { Md }, 0 },
8091 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8092 },
8093 {
8094 /* MOD_0FAE_REG_4 */
8095 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8096 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8097 },
8098 {
8099 /* MOD_0FAE_REG_5 */
8100 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8101 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8102 },
8103 {
8104 /* MOD_0FAE_REG_6 */
8105 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8106 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8107 },
8108 {
8109 /* MOD_0FAE_REG_7 */
8110 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8111 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8112 },
8113 {
8114 /* MOD_0FB2 */
8115 { "lssS", { Gv, Mp }, 0 },
8116 },
8117 {
8118 /* MOD_0FB4 */
8119 { "lfsS", { Gv, Mp }, 0 },
8120 },
8121 {
8122 /* MOD_0FB5 */
8123 { "lgsS", { Gv, Mp }, 0 },
8124 },
8125 {
8126 /* MOD_0FC3 */
8127 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8128 },
8129 {
8130 /* MOD_0FC7_REG_3 */
8131 { "xrstors", { FXSAVE }, 0 },
8132 },
8133 {
8134 /* MOD_0FC7_REG_4 */
8135 { "xsavec", { FXSAVE }, 0 },
8136 },
8137 {
8138 /* MOD_0FC7_REG_5 */
8139 { "xsaves", { FXSAVE }, 0 },
8140 },
8141 {
8142 /* MOD_0FC7_REG_6 */
8143 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8144 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8145 },
8146 {
8147 /* MOD_0FC7_REG_7 */
8148 { "vmptrst", { Mq }, 0 },
8149 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8150 },
8151 {
8152 /* MOD_0FD7 */
8153 { Bad_Opcode },
8154 { "pmovmskb", { Gdq, MS }, 0 },
8155 },
8156 {
8157 /* MOD_0FE7_PREFIX_2 */
8158 { "movntdq", { Mx, XM }, 0 },
8159 },
8160 {
8161 /* MOD_0FF0_PREFIX_3 */
8162 { "lddqu", { XM, M }, 0 },
8163 },
8164 {
8165 /* MOD_0F382A */
8166 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8167 },
8168 {
8169 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8170 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8171 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8172 },
8173 {
8174 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8175 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8176 },
8177 {
8178 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8179 { Bad_Opcode },
8180 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8181 },
8182 {
8183 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8184 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8185 },
8186 {
8187 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8188 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8189 },
8190 {
8191 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8192 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8193 },
8194 {
8195 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8196 { Bad_Opcode },
8197 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8198 },
8199 {
8200 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8201 { Bad_Opcode },
8202 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8203 },
8204 {
8205 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8206 { Bad_Opcode },
8207 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8208 },
8209 {
8210 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8211 { Bad_Opcode },
8212 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8213 },
8214 {
8215 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8216 { Bad_Opcode },
8217 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8218 },
8219 {
8220 /* MOD_0F38F5 */
8221 { "wrussK", { M, Gdq }, PREFIX_DATA },
8222 },
8223 {
8224 /* MOD_0F38F6_PREFIX_0 */
8225 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8226 },
8227 {
8228 /* MOD_0F38F8_PREFIX_1 */
8229 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8230 },
8231 {
8232 /* MOD_0F38F8_PREFIX_2 */
8233 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8234 },
8235 {
8236 /* MOD_0F38F8_PREFIX_3 */
8237 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8238 },
8239 {
8240 /* MOD_0F38F9 */
8241 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8242 },
8243 {
8244 /* MOD_62_32BIT */
8245 { "bound{S|}", { Gv, Ma }, 0 },
8246 { EVEX_TABLE (EVEX_0F) },
8247 },
8248 {
8249 /* MOD_C4_32BIT */
8250 { "lesS", { Gv, Mp }, 0 },
8251 { VEX_C4_TABLE (VEX_0F) },
8252 },
8253 {
8254 /* MOD_C5_32BIT */
8255 { "ldsS", { Gv, Mp }, 0 },
8256 { VEX_C5_TABLE (VEX_0F) },
8257 },
8258 {
8259 /* MOD_VEX_0F12_PREFIX_0 */
8260 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8261 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8262 },
8263 {
8264 /* MOD_VEX_0F12_PREFIX_2 */
8265 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8266 },
8267 {
8268 /* MOD_VEX_0F13 */
8269 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8270 },
8271 {
8272 /* MOD_VEX_0F16_PREFIX_0 */
8273 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8274 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8275 },
8276 {
8277 /* MOD_VEX_0F16_PREFIX_2 */
8278 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8279 },
8280 {
8281 /* MOD_VEX_0F17 */
8282 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8283 },
8284 {
8285 /* MOD_VEX_0F2B */
8286 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8287 },
8288 {
8289 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8290 { Bad_Opcode },
8291 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
8292 },
8293 {
8294 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8295 { Bad_Opcode },
8296 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
8297 },
8298 {
8299 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8300 { Bad_Opcode },
8301 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
8302 },
8303 {
8304 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8305 { Bad_Opcode },
8306 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
8307 },
8308 {
8309 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8310 { Bad_Opcode },
8311 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
8312 },
8313 {
8314 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8315 { Bad_Opcode },
8316 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
8317 },
8318 {
8319 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8320 { Bad_Opcode },
8321 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
8322 },
8323 {
8324 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8325 { Bad_Opcode },
8326 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
8327 },
8328 {
8329 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8330 { Bad_Opcode },
8331 { "knotw", { MaskG, MaskE }, 0 },
8332 },
8333 {
8334 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8335 { Bad_Opcode },
8336 { "knotq", { MaskG, MaskE }, 0 },
8337 },
8338 {
8339 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8340 { Bad_Opcode },
8341 { "knotb", { MaskG, MaskE }, 0 },
8342 },
8343 {
8344 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8345 { Bad_Opcode },
8346 { "knotd", { MaskG, MaskE }, 0 },
8347 },
8348 {
8349 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8350 { Bad_Opcode },
8351 { "korw", { MaskG, MaskVex, MaskE }, 0 },
8352 },
8353 {
8354 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8355 { Bad_Opcode },
8356 { "korq", { MaskG, MaskVex, MaskE }, 0 },
8357 },
8358 {
8359 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8360 { Bad_Opcode },
8361 { "korb", { MaskG, MaskVex, MaskE }, 0 },
8362 },
8363 {
8364 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8365 { Bad_Opcode },
8366 { "kord", { MaskG, MaskVex, MaskE }, 0 },
8367 },
8368 {
8369 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8370 { Bad_Opcode },
8371 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
8372 },
8373 {
8374 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8375 { Bad_Opcode },
8376 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
8377 },
8378 {
8379 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8380 { Bad_Opcode },
8381 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
8382 },
8383 {
8384 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8385 { Bad_Opcode },
8386 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
8387 },
8388 {
8389 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8390 { Bad_Opcode },
8391 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
8392 },
8393 {
8394 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8395 { Bad_Opcode },
8396 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
8397 },
8398 {
8399 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8400 { Bad_Opcode },
8401 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
8402 },
8403 {
8404 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8405 { Bad_Opcode },
8406 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
8407 },
8408 {
8409 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8410 { Bad_Opcode },
8411 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
8412 },
8413 {
8414 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8415 { Bad_Opcode },
8416 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
8417 },
8418 {
8419 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8420 { Bad_Opcode },
8421 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
8422 },
8423 {
8424 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8425 { Bad_Opcode },
8426 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
8427 },
8428 {
8429 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8430 { Bad_Opcode },
8431 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
8432 },
8433 {
8434 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8435 { Bad_Opcode },
8436 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
8437 },
8438 {
8439 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8440 { Bad_Opcode },
8441 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
8442 },
8443 {
8444 /* MOD_VEX_0F50 */
8445 { Bad_Opcode },
8446 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8447 },
8448 {
8449 /* MOD_VEX_0F71_REG_2 */
8450 { Bad_Opcode },
8451 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
8452 },
8453 {
8454 /* MOD_VEX_0F71_REG_4 */
8455 { Bad_Opcode },
8456 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
8457 },
8458 {
8459 /* MOD_VEX_0F71_REG_6 */
8460 { Bad_Opcode },
8461 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
8462 },
8463 {
8464 /* MOD_VEX_0F72_REG_2 */
8465 { Bad_Opcode },
8466 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
8467 },
8468 {
8469 /* MOD_VEX_0F72_REG_4 */
8470 { Bad_Opcode },
8471 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
8472 },
8473 {
8474 /* MOD_VEX_0F72_REG_6 */
8475 { Bad_Opcode },
8476 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
8477 },
8478 {
8479 /* MOD_VEX_0F73_REG_2 */
8480 { Bad_Opcode },
8481 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
8482 },
8483 {
8484 /* MOD_VEX_0F73_REG_3 */
8485 { Bad_Opcode },
8486 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
8487 },
8488 {
8489 /* MOD_VEX_0F73_REG_6 */
8490 { Bad_Opcode },
8491 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
8492 },
8493 {
8494 /* MOD_VEX_0F73_REG_7 */
8495 { Bad_Opcode },
8496 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
8497 },
8498 {
8499 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8500 { "kmovw", { Ew, MaskG }, 0 },
8501 { Bad_Opcode },
8502 },
8503 {
8504 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8505 { "kmovq", { Eq, MaskG }, 0 },
8506 { Bad_Opcode },
8507 },
8508 {
8509 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8510 { "kmovb", { Eb, MaskG }, 0 },
8511 { Bad_Opcode },
8512 },
8513 {
8514 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8515 { "kmovd", { Ed, MaskG }, 0 },
8516 { Bad_Opcode },
8517 },
8518 {
8519 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8520 { Bad_Opcode },
8521 { "kmovw", { MaskG, Edq }, 0 },
8522 },
8523 {
8524 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8525 { Bad_Opcode },
8526 { "kmovb", { MaskG, Edq }, 0 },
8527 },
8528 {
8529 /* MOD_VEX_0F92_P_3_LEN_0 */
8530 { Bad_Opcode },
8531 { "kmovK", { MaskG, Edq }, 0 },
8532 },
8533 {
8534 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8535 { Bad_Opcode },
8536 { "kmovw", { Gdq, MaskE }, 0 },
8537 },
8538 {
8539 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8540 { Bad_Opcode },
8541 { "kmovb", { Gdq, MaskE }, 0 },
8542 },
8543 {
8544 /* MOD_VEX_0F93_P_3_LEN_0 */
8545 { Bad_Opcode },
8546 { "kmovK", { Gdq, MaskE }, 0 },
8547 },
8548 {
8549 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8550 { Bad_Opcode },
8551 { "kortestw", { MaskG, MaskE }, 0 },
8552 },
8553 {
8554 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8555 { Bad_Opcode },
8556 { "kortestq", { MaskG, MaskE }, 0 },
8557 },
8558 {
8559 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8560 { Bad_Opcode },
8561 { "kortestb", { MaskG, MaskE }, 0 },
8562 },
8563 {
8564 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8565 { Bad_Opcode },
8566 { "kortestd", { MaskG, MaskE }, 0 },
8567 },
8568 {
8569 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8570 { Bad_Opcode },
8571 { "ktestw", { MaskG, MaskE }, 0 },
8572 },
8573 {
8574 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8575 { Bad_Opcode },
8576 { "ktestq", { MaskG, MaskE }, 0 },
8577 },
8578 {
8579 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8580 { Bad_Opcode },
8581 { "ktestb", { MaskG, MaskE }, 0 },
8582 },
8583 {
8584 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8585 { Bad_Opcode },
8586 { "ktestd", { MaskG, MaskE }, 0 },
8587 },
8588 {
8589 /* MOD_VEX_0FAE_REG_2 */
8590 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8591 },
8592 {
8593 /* MOD_VEX_0FAE_REG_3 */
8594 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8595 },
8596 {
8597 /* MOD_VEX_0FD7 */
8598 { Bad_Opcode },
8599 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8600 },
8601 {
8602 /* MOD_VEX_0FE7 */
8603 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8604 },
8605 {
8606 /* MOD_VEX_0FF0_PREFIX_3 */
8607 { "vlddqu", { XM, M }, 0 },
8608 },
8609 {
8610 /* MOD_VEX_0F381A */
8611 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8612 },
8613 {
8614 /* MOD_VEX_0F382A */
8615 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8616 },
8617 {
8618 /* MOD_VEX_0F382C */
8619 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8620 },
8621 {
8622 /* MOD_VEX_0F382D */
8623 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8624 },
8625 {
8626 /* MOD_VEX_0F382E */
8627 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8628 },
8629 {
8630 /* MOD_VEX_0F382F */
8631 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8632 },
8633 {
8634 /* MOD_VEX_0F385A */
8635 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8636 },
8637 {
8638 /* MOD_VEX_0F388C */
8639 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8640 },
8641 {
8642 /* MOD_VEX_0F388E */
8643 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8644 },
8645 {
8646 /* MOD_VEX_0F3A30_L_0 */
8647 { Bad_Opcode },
8648 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8649 },
8650 {
8651 /* MOD_VEX_0F3A31_L_0 */
8652 { Bad_Opcode },
8653 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8654 },
8655 {
8656 /* MOD_VEX_0F3A32_L_0 */
8657 { Bad_Opcode },
8658 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8659 },
8660 {
8661 /* MOD_VEX_0F3A33_L_0 */
8662 { Bad_Opcode },
8663 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8664 },
8665 {
8666 /* MOD_VEX_0FXOP_09_12 */
8667 { Bad_Opcode },
8668 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8669 },
8670
8671 #include "i386-dis-evex-mod.h"
8672 };
8673
8674 static const struct dis386 rm_table[][8] = {
8675 {
8676 /* RM_C6_REG_7 */
8677 { "xabort", { Skip_MODRM, Ib }, 0 },
8678 },
8679 {
8680 /* RM_C7_REG_7 */
8681 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8682 },
8683 {
8684 /* RM_0F01_REG_0 */
8685 { "enclv", { Skip_MODRM }, 0 },
8686 { "vmcall", { Skip_MODRM }, 0 },
8687 { "vmlaunch", { Skip_MODRM }, 0 },
8688 { "vmresume", { Skip_MODRM }, 0 },
8689 { "vmxoff", { Skip_MODRM }, 0 },
8690 { "pconfig", { Skip_MODRM }, 0 },
8691 },
8692 {
8693 /* RM_0F01_REG_1 */
8694 { "monitor", { { OP_Monitor, 0 } }, 0 },
8695 { "mwait", { { OP_Mwait, 0 } }, 0 },
8696 { "clac", { Skip_MODRM }, 0 },
8697 { "stac", { Skip_MODRM }, 0 },
8698 { Bad_Opcode },
8699 { Bad_Opcode },
8700 { Bad_Opcode },
8701 { "encls", { Skip_MODRM }, 0 },
8702 },
8703 {
8704 /* RM_0F01_REG_2 */
8705 { "xgetbv", { Skip_MODRM }, 0 },
8706 { "xsetbv", { Skip_MODRM }, 0 },
8707 { Bad_Opcode },
8708 { Bad_Opcode },
8709 { "vmfunc", { Skip_MODRM }, 0 },
8710 { "xend", { Skip_MODRM }, 0 },
8711 { "xtest", { Skip_MODRM }, 0 },
8712 { "enclu", { Skip_MODRM }, 0 },
8713 },
8714 {
8715 /* RM_0F01_REG_3 */
8716 { "vmrun", { Skip_MODRM }, 0 },
8717 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8718 { "vmload", { Skip_MODRM }, 0 },
8719 { "vmsave", { Skip_MODRM }, 0 },
8720 { "stgi", { Skip_MODRM }, 0 },
8721 { "clgi", { Skip_MODRM }, 0 },
8722 { "skinit", { Skip_MODRM }, 0 },
8723 { "invlpga", { Skip_MODRM }, 0 },
8724 },
8725 {
8726 /* RM_0F01_REG_5_MOD_3 */
8727 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8728 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8729 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8730 { Bad_Opcode },
8731 { Bad_Opcode },
8732 { Bad_Opcode },
8733 { "rdpkru", { Skip_MODRM }, 0 },
8734 { "wrpkru", { Skip_MODRM }, 0 },
8735 },
8736 {
8737 /* RM_0F01_REG_7_MOD_3 */
8738 { "swapgs", { Skip_MODRM }, 0 },
8739 { "rdtscp", { Skip_MODRM }, 0 },
8740 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8741 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8742 { "clzero", { Skip_MODRM }, 0 },
8743 { "rdpru", { Skip_MODRM }, 0 },
8744 },
8745 {
8746 /* RM_0F1E_P_1_MOD_3_REG_7 */
8747 { "nopQ", { Ev }, 0 },
8748 { "nopQ", { Ev }, 0 },
8749 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
8750 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
8751 { "nopQ", { Ev }, 0 },
8752 { "nopQ", { Ev }, 0 },
8753 { "nopQ", { Ev }, 0 },
8754 { "nopQ", { Ev }, 0 },
8755 },
8756 {
8757 /* RM_0FAE_REG_6_MOD_3 */
8758 { "mfence", { Skip_MODRM }, 0 },
8759 },
8760 {
8761 /* RM_0FAE_REG_7_MOD_3 */
8762 { "sfence", { Skip_MODRM }, 0 },
8763
8764 },
8765 {
8766 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8767 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8768 },
8769 };
8770
8771 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8772
8773 /* We use the high bit to indicate different name for the same
8774 prefix. */
8775 #define REP_PREFIX (0xf3 | 0x100)
8776 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8777 #define XRELEASE_PREFIX (0xf3 | 0x400)
8778 #define BND_PREFIX (0xf2 | 0x400)
8779 #define NOTRACK_PREFIX (0x3e | 0x100)
8780
8781 /* Remember if the current op is a jump instruction. */
8782 static bfd_boolean op_is_jump = FALSE;
8783
8784 static int
8785 ckprefix (void)
8786 {
8787 int newrex, i, length;
8788 rex = 0;
8789 prefixes = 0;
8790 used_prefixes = 0;
8791 rex_used = 0;
8792 last_lock_prefix = -1;
8793 last_repz_prefix = -1;
8794 last_repnz_prefix = -1;
8795 last_data_prefix = -1;
8796 last_addr_prefix = -1;
8797 last_rex_prefix = -1;
8798 last_seg_prefix = -1;
8799 fwait_prefix = -1;
8800 active_seg_prefix = 0;
8801 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8802 all_prefixes[i] = 0;
8803 i = 0;
8804 length = 0;
8805 /* The maximum instruction length is 15bytes. */
8806 while (length < MAX_CODE_LENGTH - 1)
8807 {
8808 FETCH_DATA (the_info, codep + 1);
8809 newrex = 0;
8810 switch (*codep)
8811 {
8812 /* REX prefixes family. */
8813 case 0x40:
8814 case 0x41:
8815 case 0x42:
8816 case 0x43:
8817 case 0x44:
8818 case 0x45:
8819 case 0x46:
8820 case 0x47:
8821 case 0x48:
8822 case 0x49:
8823 case 0x4a:
8824 case 0x4b:
8825 case 0x4c:
8826 case 0x4d:
8827 case 0x4e:
8828 case 0x4f:
8829 if (address_mode == mode_64bit)
8830 newrex = *codep;
8831 else
8832 return 1;
8833 last_rex_prefix = i;
8834 break;
8835 case 0xf3:
8836 prefixes |= PREFIX_REPZ;
8837 last_repz_prefix = i;
8838 break;
8839 case 0xf2:
8840 prefixes |= PREFIX_REPNZ;
8841 last_repnz_prefix = i;
8842 break;
8843 case 0xf0:
8844 prefixes |= PREFIX_LOCK;
8845 last_lock_prefix = i;
8846 break;
8847 case 0x2e:
8848 prefixes |= PREFIX_CS;
8849 last_seg_prefix = i;
8850 active_seg_prefix = PREFIX_CS;
8851 break;
8852 case 0x36:
8853 prefixes |= PREFIX_SS;
8854 last_seg_prefix = i;
8855 active_seg_prefix = PREFIX_SS;
8856 break;
8857 case 0x3e:
8858 prefixes |= PREFIX_DS;
8859 last_seg_prefix = i;
8860 active_seg_prefix = PREFIX_DS;
8861 break;
8862 case 0x26:
8863 prefixes |= PREFIX_ES;
8864 last_seg_prefix = i;
8865 active_seg_prefix = PREFIX_ES;
8866 break;
8867 case 0x64:
8868 prefixes |= PREFIX_FS;
8869 last_seg_prefix = i;
8870 active_seg_prefix = PREFIX_FS;
8871 break;
8872 case 0x65:
8873 prefixes |= PREFIX_GS;
8874 last_seg_prefix = i;
8875 active_seg_prefix = PREFIX_GS;
8876 break;
8877 case 0x66:
8878 prefixes |= PREFIX_DATA;
8879 last_data_prefix = i;
8880 break;
8881 case 0x67:
8882 prefixes |= PREFIX_ADDR;
8883 last_addr_prefix = i;
8884 break;
8885 case FWAIT_OPCODE:
8886 /* fwait is really an instruction. If there are prefixes
8887 before the fwait, they belong to the fwait, *not* to the
8888 following instruction. */
8889 fwait_prefix = i;
8890 if (prefixes || rex)
8891 {
8892 prefixes |= PREFIX_FWAIT;
8893 codep++;
8894 /* This ensures that the previous REX prefixes are noticed
8895 as unused prefixes, as in the return case below. */
8896 rex_used = rex;
8897 return 1;
8898 }
8899 prefixes = PREFIX_FWAIT;
8900 break;
8901 default:
8902 return 1;
8903 }
8904 /* Rex is ignored when followed by another prefix. */
8905 if (rex)
8906 {
8907 rex_used = rex;
8908 return 1;
8909 }
8910 if (*codep != FWAIT_OPCODE)
8911 all_prefixes[i++] = *codep;
8912 rex = newrex;
8913 codep++;
8914 length++;
8915 }
8916 return 0;
8917 }
8918
8919 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8920 prefix byte. */
8921
8922 static const char *
8923 prefix_name (int pref, int sizeflag)
8924 {
8925 static const char *rexes [16] =
8926 {
8927 "rex", /* 0x40 */
8928 "rex.B", /* 0x41 */
8929 "rex.X", /* 0x42 */
8930 "rex.XB", /* 0x43 */
8931 "rex.R", /* 0x44 */
8932 "rex.RB", /* 0x45 */
8933 "rex.RX", /* 0x46 */
8934 "rex.RXB", /* 0x47 */
8935 "rex.W", /* 0x48 */
8936 "rex.WB", /* 0x49 */
8937 "rex.WX", /* 0x4a */
8938 "rex.WXB", /* 0x4b */
8939 "rex.WR", /* 0x4c */
8940 "rex.WRB", /* 0x4d */
8941 "rex.WRX", /* 0x4e */
8942 "rex.WRXB", /* 0x4f */
8943 };
8944
8945 switch (pref)
8946 {
8947 /* REX prefixes family. */
8948 case 0x40:
8949 case 0x41:
8950 case 0x42:
8951 case 0x43:
8952 case 0x44:
8953 case 0x45:
8954 case 0x46:
8955 case 0x47:
8956 case 0x48:
8957 case 0x49:
8958 case 0x4a:
8959 case 0x4b:
8960 case 0x4c:
8961 case 0x4d:
8962 case 0x4e:
8963 case 0x4f:
8964 return rexes [pref - 0x40];
8965 case 0xf3:
8966 return "repz";
8967 case 0xf2:
8968 return "repnz";
8969 case 0xf0:
8970 return "lock";
8971 case 0x2e:
8972 return "cs";
8973 case 0x36:
8974 return "ss";
8975 case 0x3e:
8976 return "ds";
8977 case 0x26:
8978 return "es";
8979 case 0x64:
8980 return "fs";
8981 case 0x65:
8982 return "gs";
8983 case 0x66:
8984 return (sizeflag & DFLAG) ? "data16" : "data32";
8985 case 0x67:
8986 if (address_mode == mode_64bit)
8987 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8988 else
8989 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8990 case FWAIT_OPCODE:
8991 return "fwait";
8992 case REP_PREFIX:
8993 return "rep";
8994 case XACQUIRE_PREFIX:
8995 return "xacquire";
8996 case XRELEASE_PREFIX:
8997 return "xrelease";
8998 case BND_PREFIX:
8999 return "bnd";
9000 case NOTRACK_PREFIX:
9001 return "notrack";
9002 default:
9003 return NULL;
9004 }
9005 }
9006
9007 static char op_out[MAX_OPERANDS][100];
9008 static int op_ad, op_index[MAX_OPERANDS];
9009 static int two_source_ops;
9010 static bfd_vma op_address[MAX_OPERANDS];
9011 static bfd_vma op_riprel[MAX_OPERANDS];
9012 static bfd_vma start_pc;
9013
9014 /*
9015 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9016 * (see topic "Redundant prefixes" in the "Differences from 8086"
9017 * section of the "Virtual 8086 Mode" chapter.)
9018 * 'pc' should be the address of this instruction, it will
9019 * be used to print the target address if this is a relative jump or call
9020 * The function returns the length of this instruction in bytes.
9021 */
9022
9023 static char intel_syntax;
9024 static char intel_mnemonic = !SYSV386_COMPAT;
9025 static char open_char;
9026 static char close_char;
9027 static char separator_char;
9028 static char scale_char;
9029
9030 enum x86_64_isa
9031 {
9032 amd64 = 1,
9033 intel64
9034 };
9035
9036 static enum x86_64_isa isa64;
9037
9038 /* Here for backwards compatibility. When gdb stops using
9039 print_insn_i386_att and print_insn_i386_intel these functions can
9040 disappear, and print_insn_i386 be merged into print_insn. */
9041 int
9042 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9043 {
9044 intel_syntax = 0;
9045
9046 return print_insn (pc, info);
9047 }
9048
9049 int
9050 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9051 {
9052 intel_syntax = 1;
9053
9054 return print_insn (pc, info);
9055 }
9056
9057 int
9058 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9059 {
9060 intel_syntax = -1;
9061
9062 return print_insn (pc, info);
9063 }
9064
9065 void
9066 print_i386_disassembler_options (FILE *stream)
9067 {
9068 fprintf (stream, _("\n\
9069 The following i386/x86-64 specific disassembler options are supported for use\n\
9070 with the -M switch (multiple options should be separated by commas):\n"));
9071
9072 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9073 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9074 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9075 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9076 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9077 fprintf (stream, _(" att-mnemonic\n"
9078 " Display instruction in AT&T mnemonic\n"));
9079 fprintf (stream, _(" intel-mnemonic\n"
9080 " Display instruction in Intel mnemonic\n"));
9081 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9082 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9083 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9084 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9085 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9086 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9087 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
9088 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
9089 }
9090
9091 /* Bad opcode. */
9092 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9093
9094 /* Get a pointer to struct dis386 with a valid name. */
9095
9096 static const struct dis386 *
9097 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9098 {
9099 int vindex, vex_table_index;
9100
9101 if (dp->name != NULL)
9102 return dp;
9103
9104 switch (dp->op[0].bytemode)
9105 {
9106 case USE_REG_TABLE:
9107 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9108 break;
9109
9110 case USE_MOD_TABLE:
9111 vindex = modrm.mod == 0x3 ? 1 : 0;
9112 dp = &mod_table[dp->op[1].bytemode][vindex];
9113 break;
9114
9115 case USE_RM_TABLE:
9116 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9117 break;
9118
9119 case USE_PREFIX_TABLE:
9120 if (need_vex)
9121 {
9122 /* The prefix in VEX is implicit. */
9123 switch (vex.prefix)
9124 {
9125 case 0:
9126 vindex = 0;
9127 break;
9128 case REPE_PREFIX_OPCODE:
9129 vindex = 1;
9130 break;
9131 case DATA_PREFIX_OPCODE:
9132 vindex = 2;
9133 break;
9134 case REPNE_PREFIX_OPCODE:
9135 vindex = 3;
9136 break;
9137 default:
9138 abort ();
9139 break;
9140 }
9141 }
9142 else
9143 {
9144 int last_prefix = -1;
9145 int prefix = 0;
9146 vindex = 0;
9147 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9148 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9149 last one wins. */
9150 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9151 {
9152 if (last_repz_prefix > last_repnz_prefix)
9153 {
9154 vindex = 1;
9155 prefix = PREFIX_REPZ;
9156 last_prefix = last_repz_prefix;
9157 }
9158 else
9159 {
9160 vindex = 3;
9161 prefix = PREFIX_REPNZ;
9162 last_prefix = last_repnz_prefix;
9163 }
9164
9165 /* Check if prefix should be ignored. */
9166 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9167 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9168 & prefix) != 0)
9169 vindex = 0;
9170 }
9171
9172 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9173 {
9174 vindex = 2;
9175 prefix = PREFIX_DATA;
9176 last_prefix = last_data_prefix;
9177 }
9178
9179 if (vindex != 0)
9180 {
9181 used_prefixes |= prefix;
9182 all_prefixes[last_prefix] = 0;
9183 }
9184 }
9185 dp = &prefix_table[dp->op[1].bytemode][vindex];
9186 break;
9187
9188 case USE_X86_64_TABLE:
9189 vindex = address_mode == mode_64bit ? 1 : 0;
9190 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9191 break;
9192
9193 case USE_3BYTE_TABLE:
9194 FETCH_DATA (info, codep + 2);
9195 vindex = *codep++;
9196 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9197 end_codep = codep;
9198 modrm.mod = (*codep >> 6) & 3;
9199 modrm.reg = (*codep >> 3) & 7;
9200 modrm.rm = *codep & 7;
9201 break;
9202
9203 case USE_VEX_LEN_TABLE:
9204 if (!need_vex)
9205 abort ();
9206
9207 switch (vex.length)
9208 {
9209 case 128:
9210 vindex = 0;
9211 break;
9212 case 256:
9213 vindex = 1;
9214 break;
9215 default:
9216 abort ();
9217 break;
9218 }
9219
9220 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9221 break;
9222
9223 case USE_EVEX_LEN_TABLE:
9224 if (!vex.evex)
9225 abort ();
9226
9227 switch (vex.length)
9228 {
9229 case 128:
9230 vindex = 0;
9231 break;
9232 case 256:
9233 vindex = 1;
9234 break;
9235 case 512:
9236 vindex = 2;
9237 break;
9238 default:
9239 abort ();
9240 break;
9241 }
9242
9243 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9244 break;
9245
9246 case USE_XOP_8F_TABLE:
9247 FETCH_DATA (info, codep + 3);
9248 rex = ~(*codep >> 5) & 0x7;
9249
9250 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9251 switch ((*codep & 0x1f))
9252 {
9253 default:
9254 dp = &bad_opcode;
9255 return dp;
9256 case 0x8:
9257 vex_table_index = XOP_08;
9258 break;
9259 case 0x9:
9260 vex_table_index = XOP_09;
9261 break;
9262 case 0xa:
9263 vex_table_index = XOP_0A;
9264 break;
9265 }
9266 codep++;
9267 vex.w = *codep & 0x80;
9268 if (vex.w && address_mode == mode_64bit)
9269 rex |= REX_W;
9270
9271 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9272 if (address_mode != mode_64bit)
9273 {
9274 /* In 16/32-bit mode REX_B is silently ignored. */
9275 rex &= ~REX_B;
9276 }
9277
9278 vex.length = (*codep & 0x4) ? 256 : 128;
9279 switch ((*codep & 0x3))
9280 {
9281 case 0:
9282 break;
9283 case 1:
9284 vex.prefix = DATA_PREFIX_OPCODE;
9285 break;
9286 case 2:
9287 vex.prefix = REPE_PREFIX_OPCODE;
9288 break;
9289 case 3:
9290 vex.prefix = REPNE_PREFIX_OPCODE;
9291 break;
9292 }
9293 need_vex = 1;
9294 codep++;
9295 vindex = *codep++;
9296 dp = &xop_table[vex_table_index][vindex];
9297
9298 end_codep = codep;
9299 FETCH_DATA (info, codep + 1);
9300 modrm.mod = (*codep >> 6) & 3;
9301 modrm.reg = (*codep >> 3) & 7;
9302 modrm.rm = *codep & 7;
9303
9304 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9305 having to decode the bits for every otherwise valid encoding. */
9306 if (vex.prefix)
9307 return &bad_opcode;
9308 break;
9309
9310 case USE_VEX_C4_TABLE:
9311 /* VEX prefix. */
9312 FETCH_DATA (info, codep + 3);
9313 rex = ~(*codep >> 5) & 0x7;
9314 switch ((*codep & 0x1f))
9315 {
9316 default:
9317 dp = &bad_opcode;
9318 return dp;
9319 case 0x1:
9320 vex_table_index = VEX_0F;
9321 break;
9322 case 0x2:
9323 vex_table_index = VEX_0F38;
9324 break;
9325 case 0x3:
9326 vex_table_index = VEX_0F3A;
9327 break;
9328 }
9329 codep++;
9330 vex.w = *codep & 0x80;
9331 if (address_mode == mode_64bit)
9332 {
9333 if (vex.w)
9334 rex |= REX_W;
9335 }
9336 else
9337 {
9338 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9339 is ignored, other REX bits are 0 and the highest bit in
9340 VEX.vvvv is also ignored (but we mustn't clear it here). */
9341 rex = 0;
9342 }
9343 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9344 vex.length = (*codep & 0x4) ? 256 : 128;
9345 switch ((*codep & 0x3))
9346 {
9347 case 0:
9348 break;
9349 case 1:
9350 vex.prefix = DATA_PREFIX_OPCODE;
9351 break;
9352 case 2:
9353 vex.prefix = REPE_PREFIX_OPCODE;
9354 break;
9355 case 3:
9356 vex.prefix = REPNE_PREFIX_OPCODE;
9357 break;
9358 }
9359 need_vex = 1;
9360 codep++;
9361 vindex = *codep++;
9362 dp = &vex_table[vex_table_index][vindex];
9363 end_codep = codep;
9364 /* There is no MODRM byte for VEX0F 77. */
9365 if (vex_table_index != VEX_0F || vindex != 0x77)
9366 {
9367 FETCH_DATA (info, codep + 1);
9368 modrm.mod = (*codep >> 6) & 3;
9369 modrm.reg = (*codep >> 3) & 7;
9370 modrm.rm = *codep & 7;
9371 }
9372 break;
9373
9374 case USE_VEX_C5_TABLE:
9375 /* VEX prefix. */
9376 FETCH_DATA (info, codep + 2);
9377 rex = (*codep & 0x80) ? 0 : REX_R;
9378
9379 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9380 VEX.vvvv is 1. */
9381 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9382 vex.length = (*codep & 0x4) ? 256 : 128;
9383 switch ((*codep & 0x3))
9384 {
9385 case 0:
9386 break;
9387 case 1:
9388 vex.prefix = DATA_PREFIX_OPCODE;
9389 break;
9390 case 2:
9391 vex.prefix = REPE_PREFIX_OPCODE;
9392 break;
9393 case 3:
9394 vex.prefix = REPNE_PREFIX_OPCODE;
9395 break;
9396 }
9397 need_vex = 1;
9398 codep++;
9399 vindex = *codep++;
9400 dp = &vex_table[dp->op[1].bytemode][vindex];
9401 end_codep = codep;
9402 /* There is no MODRM byte for VEX 77. */
9403 if (vindex != 0x77)
9404 {
9405 FETCH_DATA (info, codep + 1);
9406 modrm.mod = (*codep >> 6) & 3;
9407 modrm.reg = (*codep >> 3) & 7;
9408 modrm.rm = *codep & 7;
9409 }
9410 break;
9411
9412 case USE_VEX_W_TABLE:
9413 if (!need_vex)
9414 abort ();
9415
9416 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9417 break;
9418
9419 case USE_EVEX_TABLE:
9420 two_source_ops = 0;
9421 /* EVEX prefix. */
9422 vex.evex = 1;
9423 FETCH_DATA (info, codep + 4);
9424 /* The first byte after 0x62. */
9425 rex = ~(*codep >> 5) & 0x7;
9426 vex.r = *codep & 0x10;
9427 switch ((*codep & 0xf))
9428 {
9429 default:
9430 return &bad_opcode;
9431 case 0x1:
9432 vex_table_index = EVEX_0F;
9433 break;
9434 case 0x2:
9435 vex_table_index = EVEX_0F38;
9436 break;
9437 case 0x3:
9438 vex_table_index = EVEX_0F3A;
9439 break;
9440 }
9441
9442 /* The second byte after 0x62. */
9443 codep++;
9444 vex.w = *codep & 0x80;
9445 if (vex.w && address_mode == mode_64bit)
9446 rex |= REX_W;
9447
9448 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9449
9450 /* The U bit. */
9451 if (!(*codep & 0x4))
9452 return &bad_opcode;
9453
9454 switch ((*codep & 0x3))
9455 {
9456 case 0:
9457 break;
9458 case 1:
9459 vex.prefix = DATA_PREFIX_OPCODE;
9460 break;
9461 case 2:
9462 vex.prefix = REPE_PREFIX_OPCODE;
9463 break;
9464 case 3:
9465 vex.prefix = REPNE_PREFIX_OPCODE;
9466 break;
9467 }
9468
9469 /* The third byte after 0x62. */
9470 codep++;
9471
9472 /* Remember the static rounding bits. */
9473 vex.ll = (*codep >> 5) & 3;
9474 vex.b = (*codep & 0x10) != 0;
9475
9476 vex.v = *codep & 0x8;
9477 vex.mask_register_specifier = *codep & 0x7;
9478 vex.zeroing = *codep & 0x80;
9479
9480 if (address_mode != mode_64bit)
9481 {
9482 /* In 16/32-bit mode silently ignore following bits. */
9483 rex &= ~REX_B;
9484 vex.r = 1;
9485 vex.v = 1;
9486 }
9487
9488 need_vex = 1;
9489 codep++;
9490 vindex = *codep++;
9491 dp = &evex_table[vex_table_index][vindex];
9492 end_codep = codep;
9493 FETCH_DATA (info, codep + 1);
9494 modrm.mod = (*codep >> 6) & 3;
9495 modrm.reg = (*codep >> 3) & 7;
9496 modrm.rm = *codep & 7;
9497
9498 /* Set vector length. */
9499 if (modrm.mod == 3 && vex.b)
9500 vex.length = 512;
9501 else
9502 {
9503 switch (vex.ll)
9504 {
9505 case 0x0:
9506 vex.length = 128;
9507 break;
9508 case 0x1:
9509 vex.length = 256;
9510 break;
9511 case 0x2:
9512 vex.length = 512;
9513 break;
9514 default:
9515 return &bad_opcode;
9516 }
9517 }
9518 break;
9519
9520 case 0:
9521 dp = &bad_opcode;
9522 break;
9523
9524 default:
9525 abort ();
9526 }
9527
9528 if (dp->name != NULL)
9529 return dp;
9530 else
9531 return get_valid_dis386 (dp, info);
9532 }
9533
9534 static void
9535 get_sib (disassemble_info *info, int sizeflag)
9536 {
9537 /* If modrm.mod == 3, operand must be register. */
9538 if (need_modrm
9539 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9540 && modrm.mod != 3
9541 && modrm.rm == 4)
9542 {
9543 FETCH_DATA (info, codep + 2);
9544 sib.index = (codep [1] >> 3) & 7;
9545 sib.scale = (codep [1] >> 6) & 3;
9546 sib.base = codep [1] & 7;
9547 }
9548 }
9549
9550 static int
9551 print_insn (bfd_vma pc, disassemble_info *info)
9552 {
9553 const struct dis386 *dp;
9554 int i;
9555 char *op_txt[MAX_OPERANDS];
9556 int needcomma;
9557 int sizeflag, orig_sizeflag;
9558 const char *p;
9559 struct dis_private priv;
9560 int prefix_length;
9561
9562 priv.orig_sizeflag = AFLAG | DFLAG;
9563 if ((info->mach & bfd_mach_i386_i386) != 0)
9564 address_mode = mode_32bit;
9565 else if (info->mach == bfd_mach_i386_i8086)
9566 {
9567 address_mode = mode_16bit;
9568 priv.orig_sizeflag = 0;
9569 }
9570 else
9571 address_mode = mode_64bit;
9572
9573 if (intel_syntax == (char) -1)
9574 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9575
9576 for (p = info->disassembler_options; p != NULL; )
9577 {
9578 if (CONST_STRNEQ (p, "amd64"))
9579 isa64 = amd64;
9580 else if (CONST_STRNEQ (p, "intel64"))
9581 isa64 = intel64;
9582 else if (CONST_STRNEQ (p, "x86-64"))
9583 {
9584 address_mode = mode_64bit;
9585 priv.orig_sizeflag |= AFLAG | DFLAG;
9586 }
9587 else if (CONST_STRNEQ (p, "i386"))
9588 {
9589 address_mode = mode_32bit;
9590 priv.orig_sizeflag |= AFLAG | DFLAG;
9591 }
9592 else if (CONST_STRNEQ (p, "i8086"))
9593 {
9594 address_mode = mode_16bit;
9595 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9596 }
9597 else if (CONST_STRNEQ (p, "intel"))
9598 {
9599 intel_syntax = 1;
9600 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9601 intel_mnemonic = 1;
9602 }
9603 else if (CONST_STRNEQ (p, "att"))
9604 {
9605 intel_syntax = 0;
9606 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9607 intel_mnemonic = 0;
9608 }
9609 else if (CONST_STRNEQ (p, "addr"))
9610 {
9611 if (address_mode == mode_64bit)
9612 {
9613 if (p[4] == '3' && p[5] == '2')
9614 priv.orig_sizeflag &= ~AFLAG;
9615 else if (p[4] == '6' && p[5] == '4')
9616 priv.orig_sizeflag |= AFLAG;
9617 }
9618 else
9619 {
9620 if (p[4] == '1' && p[5] == '6')
9621 priv.orig_sizeflag &= ~AFLAG;
9622 else if (p[4] == '3' && p[5] == '2')
9623 priv.orig_sizeflag |= AFLAG;
9624 }
9625 }
9626 else if (CONST_STRNEQ (p, "data"))
9627 {
9628 if (p[4] == '1' && p[5] == '6')
9629 priv.orig_sizeflag &= ~DFLAG;
9630 else if (p[4] == '3' && p[5] == '2')
9631 priv.orig_sizeflag |= DFLAG;
9632 }
9633 else if (CONST_STRNEQ (p, "suffix"))
9634 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9635
9636 p = strchr (p, ',');
9637 if (p != NULL)
9638 p++;
9639 }
9640
9641 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9642 {
9643 (*info->fprintf_func) (info->stream,
9644 _("64-bit address is disabled"));
9645 return -1;
9646 }
9647
9648 if (intel_syntax)
9649 {
9650 names64 = intel_names64;
9651 names32 = intel_names32;
9652 names16 = intel_names16;
9653 names8 = intel_names8;
9654 names8rex = intel_names8rex;
9655 names_seg = intel_names_seg;
9656 names_mm = intel_names_mm;
9657 names_bnd = intel_names_bnd;
9658 names_xmm = intel_names_xmm;
9659 names_ymm = intel_names_ymm;
9660 names_zmm = intel_names_zmm;
9661 names_tmm = intel_names_tmm;
9662 index64 = intel_index64;
9663 index32 = intel_index32;
9664 names_mask = intel_names_mask;
9665 index16 = intel_index16;
9666 open_char = '[';
9667 close_char = ']';
9668 separator_char = '+';
9669 scale_char = '*';
9670 }
9671 else
9672 {
9673 names64 = att_names64;
9674 names32 = att_names32;
9675 names16 = att_names16;
9676 names8 = att_names8;
9677 names8rex = att_names8rex;
9678 names_seg = att_names_seg;
9679 names_mm = att_names_mm;
9680 names_bnd = att_names_bnd;
9681 names_xmm = att_names_xmm;
9682 names_ymm = att_names_ymm;
9683 names_zmm = att_names_zmm;
9684 names_tmm = att_names_tmm;
9685 index64 = att_index64;
9686 index32 = att_index32;
9687 names_mask = att_names_mask;
9688 index16 = att_index16;
9689 open_char = '(';
9690 close_char = ')';
9691 separator_char = ',';
9692 scale_char = ',';
9693 }
9694
9695 /* The output looks better if we put 7 bytes on a line, since that
9696 puts most long word instructions on a single line. Use 8 bytes
9697 for Intel L1OM. */
9698 if ((info->mach & bfd_mach_l1om) != 0)
9699 info->bytes_per_line = 8;
9700 else
9701 info->bytes_per_line = 7;
9702
9703 info->private_data = &priv;
9704 priv.max_fetched = priv.the_buffer;
9705 priv.insn_start = pc;
9706
9707 obuf[0] = 0;
9708 for (i = 0; i < MAX_OPERANDS; ++i)
9709 {
9710 op_out[i][0] = 0;
9711 op_index[i] = -1;
9712 }
9713
9714 the_info = info;
9715 start_pc = pc;
9716 start_codep = priv.the_buffer;
9717 codep = priv.the_buffer;
9718
9719 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9720 {
9721 const char *name;
9722
9723 /* Getting here means we tried for data but didn't get it. That
9724 means we have an incomplete instruction of some sort. Just
9725 print the first byte as a prefix or a .byte pseudo-op. */
9726 if (codep > priv.the_buffer)
9727 {
9728 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9729 if (name != NULL)
9730 (*info->fprintf_func) (info->stream, "%s", name);
9731 else
9732 {
9733 /* Just print the first byte as a .byte instruction. */
9734 (*info->fprintf_func) (info->stream, ".byte 0x%x",
9735 (unsigned int) priv.the_buffer[0]);
9736 }
9737
9738 return 1;
9739 }
9740
9741 return -1;
9742 }
9743
9744 obufp = obuf;
9745 sizeflag = priv.orig_sizeflag;
9746
9747 if (!ckprefix () || rex_used)
9748 {
9749 /* Too many prefixes or unused REX prefixes. */
9750 for (i = 0;
9751 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9752 i++)
9753 (*info->fprintf_func) (info->stream, "%s%s",
9754 i == 0 ? "" : " ",
9755 prefix_name (all_prefixes[i], sizeflag));
9756 return i;
9757 }
9758
9759 insn_codep = codep;
9760
9761 FETCH_DATA (info, codep + 1);
9762 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9763
9764 if (((prefixes & PREFIX_FWAIT)
9765 && ((*codep < 0xd8) || (*codep > 0xdf))))
9766 {
9767 /* Handle prefixes before fwait. */
9768 for (i = 0; i < fwait_prefix && all_prefixes[i];
9769 i++)
9770 (*info->fprintf_func) (info->stream, "%s ",
9771 prefix_name (all_prefixes[i], sizeflag));
9772 (*info->fprintf_func) (info->stream, "fwait");
9773 return i + 1;
9774 }
9775
9776 if (*codep == 0x0f)
9777 {
9778 unsigned char threebyte;
9779
9780 codep++;
9781 FETCH_DATA (info, codep + 1);
9782 threebyte = *codep;
9783 dp = &dis386_twobyte[threebyte];
9784 need_modrm = twobyte_has_modrm[*codep];
9785 codep++;
9786 }
9787 else
9788 {
9789 dp = &dis386[*codep];
9790 need_modrm = onebyte_has_modrm[*codep];
9791 codep++;
9792 }
9793
9794 /* Save sizeflag for printing the extra prefixes later before updating
9795 it for mnemonic and operand processing. The prefix names depend
9796 only on the address mode. */
9797 orig_sizeflag = sizeflag;
9798 if (prefixes & PREFIX_ADDR)
9799 sizeflag ^= AFLAG;
9800 if ((prefixes & PREFIX_DATA))
9801 sizeflag ^= DFLAG;
9802
9803 end_codep = codep;
9804 if (need_modrm)
9805 {
9806 FETCH_DATA (info, codep + 1);
9807 modrm.mod = (*codep >> 6) & 3;
9808 modrm.reg = (*codep >> 3) & 7;
9809 modrm.rm = *codep & 7;
9810 }
9811
9812 need_vex = 0;
9813 memset (&vex, 0, sizeof (vex));
9814
9815 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9816 {
9817 get_sib (info, sizeflag);
9818 dofloat (sizeflag);
9819 }
9820 else
9821 {
9822 dp = get_valid_dis386 (dp, info);
9823 if (dp != NULL && putop (dp->name, sizeflag) == 0)
9824 {
9825 get_sib (info, sizeflag);
9826 for (i = 0; i < MAX_OPERANDS; ++i)
9827 {
9828 obufp = op_out[i];
9829 op_ad = MAX_OPERANDS - 1 - i;
9830 if (dp->op[i].rtn)
9831 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9832 /* For EVEX instruction after the last operand masking
9833 should be printed. */
9834 if (i == 0 && vex.evex)
9835 {
9836 /* Don't print {%k0}. */
9837 if (vex.mask_register_specifier)
9838 {
9839 oappend ("{");
9840 oappend (names_mask[vex.mask_register_specifier]);
9841 oappend ("}");
9842 }
9843 if (vex.zeroing)
9844 oappend ("{z}");
9845 }
9846 }
9847 }
9848 }
9849
9850 /* Clear instruction information. */
9851 if (the_info)
9852 {
9853 the_info->insn_info_valid = 0;
9854 the_info->branch_delay_insns = 0;
9855 the_info->data_size = 0;
9856 the_info->insn_type = dis_noninsn;
9857 the_info->target = 0;
9858 the_info->target2 = 0;
9859 }
9860
9861 /* Reset jump operation indicator. */
9862 op_is_jump = FALSE;
9863
9864 {
9865 int jump_detection = 0;
9866
9867 /* Extract flags. */
9868 for (i = 0; i < MAX_OPERANDS; ++i)
9869 {
9870 if ((dp->op[i].rtn == OP_J)
9871 || (dp->op[i].rtn == OP_indirE))
9872 jump_detection |= 1;
9873 else if ((dp->op[i].rtn == BND_Fixup)
9874 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9875 jump_detection |= 2;
9876 else if ((dp->op[i].bytemode == cond_jump_mode)
9877 || (dp->op[i].bytemode == loop_jcxz_mode))
9878 jump_detection |= 4;
9879 }
9880
9881 /* Determine if this is a jump or branch. */
9882 if ((jump_detection & 0x3) == 0x3)
9883 {
9884 op_is_jump = TRUE;
9885 if (jump_detection & 0x4)
9886 the_info->insn_type = dis_condbranch;
9887 else
9888 the_info->insn_type =
9889 (dp->name && !strncmp(dp->name, "call", 4))
9890 ? dis_jsr : dis_branch;
9891 }
9892 }
9893
9894 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9895 are all 0s in inverted form. */
9896 if (need_vex && vex.register_specifier != 0)
9897 {
9898 (*info->fprintf_func) (info->stream, "(bad)");
9899 return end_codep - priv.the_buffer;
9900 }
9901
9902 switch (dp->prefix_requirement)
9903 {
9904 case PREFIX_DATA:
9905 /* If only the data prefix is marked as mandatory, its absence renders
9906 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9907 if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9908 {
9909 (*info->fprintf_func) (info->stream, "(bad)");
9910 return end_codep - priv.the_buffer;
9911 }
9912 used_prefixes |= PREFIX_DATA;
9913 /* Fall through. */
9914 case PREFIX_OPCODE:
9915 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9916 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9917 used by putop and MMX/SSE operand and may be overridden by the
9918 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9919 separately. */
9920 if (((need_vex
9921 ? vex.prefix == REPE_PREFIX_OPCODE
9922 || vex.prefix == REPNE_PREFIX_OPCODE
9923 : (prefixes
9924 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9925 && (used_prefixes
9926 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9927 || (((need_vex
9928 ? vex.prefix == DATA_PREFIX_OPCODE
9929 : ((prefixes
9930 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9931 == PREFIX_DATA))
9932 && (used_prefixes & PREFIX_DATA) == 0))
9933 || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9934 && !vex.w != !(used_prefixes & PREFIX_DATA)))
9935 {
9936 (*info->fprintf_func) (info->stream, "(bad)");
9937 return end_codep - priv.the_buffer;
9938 }
9939 break;
9940 }
9941
9942 /* Check if the REX prefix is used. */
9943 if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9944 all_prefixes[last_rex_prefix] = 0;
9945
9946 /* Check if the SEG prefix is used. */
9947 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9948 | PREFIX_FS | PREFIX_GS)) != 0
9949 && (used_prefixes & active_seg_prefix) != 0)
9950 all_prefixes[last_seg_prefix] = 0;
9951
9952 /* Check if the ADDR prefix is used. */
9953 if ((prefixes & PREFIX_ADDR) != 0
9954 && (used_prefixes & PREFIX_ADDR) != 0)
9955 all_prefixes[last_addr_prefix] = 0;
9956
9957 /* Check if the DATA prefix is used. */
9958 if ((prefixes & PREFIX_DATA) != 0
9959 && (used_prefixes & PREFIX_DATA) != 0
9960 && !need_vex)
9961 all_prefixes[last_data_prefix] = 0;
9962
9963 /* Print the extra prefixes. */
9964 prefix_length = 0;
9965 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9966 if (all_prefixes[i])
9967 {
9968 const char *name;
9969 name = prefix_name (all_prefixes[i], orig_sizeflag);
9970 if (name == NULL)
9971 abort ();
9972 prefix_length += strlen (name) + 1;
9973 (*info->fprintf_func) (info->stream, "%s ", name);
9974 }
9975
9976 /* Check maximum code length. */
9977 if ((codep - start_codep) > MAX_CODE_LENGTH)
9978 {
9979 (*info->fprintf_func) (info->stream, "(bad)");
9980 return MAX_CODE_LENGTH;
9981 }
9982
9983 obufp = mnemonicendp;
9984 for (i = strlen (obuf) + prefix_length; i < 6; i++)
9985 oappend (" ");
9986 oappend (" ");
9987 (*info->fprintf_func) (info->stream, "%s", obuf);
9988
9989 /* The enter and bound instructions are printed with operands in the same
9990 order as the intel book; everything else is printed in reverse order. */
9991 if (intel_syntax || two_source_ops)
9992 {
9993 bfd_vma riprel;
9994
9995 for (i = 0; i < MAX_OPERANDS; ++i)
9996 op_txt[i] = op_out[i];
9997
9998 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9999 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10000 {
10001 op_txt[2] = op_out[3];
10002 op_txt[3] = op_out[2];
10003 }
10004
10005 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10006 {
10007 op_ad = op_index[i];
10008 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10009 op_index[MAX_OPERANDS - 1 - i] = op_ad;
10010 riprel = op_riprel[i];
10011 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10012 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10013 }
10014 }
10015 else
10016 {
10017 for (i = 0; i < MAX_OPERANDS; ++i)
10018 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10019 }
10020
10021 needcomma = 0;
10022 for (i = 0; i < MAX_OPERANDS; ++i)
10023 if (*op_txt[i])
10024 {
10025 if (needcomma)
10026 (*info->fprintf_func) (info->stream, ",");
10027 if (op_index[i] != -1 && !op_riprel[i])
10028 {
10029 bfd_vma target = (bfd_vma) op_address[op_index[i]];
10030
10031 if (the_info && op_is_jump)
10032 {
10033 the_info->insn_info_valid = 1;
10034 the_info->branch_delay_insns = 0;
10035 the_info->data_size = 0;
10036 the_info->target = target;
10037 the_info->target2 = 0;
10038 }
10039 (*info->print_address_func) (target, info);
10040 }
10041 else
10042 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10043 needcomma = 1;
10044 }
10045
10046 for (i = 0; i < MAX_OPERANDS; i++)
10047 if (op_index[i] != -1 && op_riprel[i])
10048 {
10049 (*info->fprintf_func) (info->stream, " # ");
10050 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10051 + op_address[op_index[i]]), info);
10052 break;
10053 }
10054 return codep - priv.the_buffer;
10055 }
10056
10057 static const char *float_mem[] = {
10058 /* d8 */
10059 "fadd{s|}",
10060 "fmul{s|}",
10061 "fcom{s|}",
10062 "fcomp{s|}",
10063 "fsub{s|}",
10064 "fsubr{s|}",
10065 "fdiv{s|}",
10066 "fdivr{s|}",
10067 /* d9 */
10068 "fld{s|}",
10069 "(bad)",
10070 "fst{s|}",
10071 "fstp{s|}",
10072 "fldenv{C|C}",
10073 "fldcw",
10074 "fNstenv{C|C}",
10075 "fNstcw",
10076 /* da */
10077 "fiadd{l|}",
10078 "fimul{l|}",
10079 "ficom{l|}",
10080 "ficomp{l|}",
10081 "fisub{l|}",
10082 "fisubr{l|}",
10083 "fidiv{l|}",
10084 "fidivr{l|}",
10085 /* db */
10086 "fild{l|}",
10087 "fisttp{l|}",
10088 "fist{l|}",
10089 "fistp{l|}",
10090 "(bad)",
10091 "fld{t|}",
10092 "(bad)",
10093 "fstp{t|}",
10094 /* dc */
10095 "fadd{l|}",
10096 "fmul{l|}",
10097 "fcom{l|}",
10098 "fcomp{l|}",
10099 "fsub{l|}",
10100 "fsubr{l|}",
10101 "fdiv{l|}",
10102 "fdivr{l|}",
10103 /* dd */
10104 "fld{l|}",
10105 "fisttp{ll|}",
10106 "fst{l||}",
10107 "fstp{l|}",
10108 "frstor{C|C}",
10109 "(bad)",
10110 "fNsave{C|C}",
10111 "fNstsw",
10112 /* de */
10113 "fiadd{s|}",
10114 "fimul{s|}",
10115 "ficom{s|}",
10116 "ficomp{s|}",
10117 "fisub{s|}",
10118 "fisubr{s|}",
10119 "fidiv{s|}",
10120 "fidivr{s|}",
10121 /* df */
10122 "fild{s|}",
10123 "fisttp{s|}",
10124 "fist{s|}",
10125 "fistp{s|}",
10126 "fbld",
10127 "fild{ll|}",
10128 "fbstp",
10129 "fistp{ll|}",
10130 };
10131
10132 static const unsigned char float_mem_mode[] = {
10133 /* d8 */
10134 d_mode,
10135 d_mode,
10136 d_mode,
10137 d_mode,
10138 d_mode,
10139 d_mode,
10140 d_mode,
10141 d_mode,
10142 /* d9 */
10143 d_mode,
10144 0,
10145 d_mode,
10146 d_mode,
10147 0,
10148 w_mode,
10149 0,
10150 w_mode,
10151 /* da */
10152 d_mode,
10153 d_mode,
10154 d_mode,
10155 d_mode,
10156 d_mode,
10157 d_mode,
10158 d_mode,
10159 d_mode,
10160 /* db */
10161 d_mode,
10162 d_mode,
10163 d_mode,
10164 d_mode,
10165 0,
10166 t_mode,
10167 0,
10168 t_mode,
10169 /* dc */
10170 q_mode,
10171 q_mode,
10172 q_mode,
10173 q_mode,
10174 q_mode,
10175 q_mode,
10176 q_mode,
10177 q_mode,
10178 /* dd */
10179 q_mode,
10180 q_mode,
10181 q_mode,
10182 q_mode,
10183 0,
10184 0,
10185 0,
10186 w_mode,
10187 /* de */
10188 w_mode,
10189 w_mode,
10190 w_mode,
10191 w_mode,
10192 w_mode,
10193 w_mode,
10194 w_mode,
10195 w_mode,
10196 /* df */
10197 w_mode,
10198 w_mode,
10199 w_mode,
10200 w_mode,
10201 t_mode,
10202 q_mode,
10203 t_mode,
10204 q_mode
10205 };
10206
10207 #define ST { OP_ST, 0 }
10208 #define STi { OP_STi, 0 }
10209
10210 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10211 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10212 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10213 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10214 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10215 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10216 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10217 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10218 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10219
10220 static const struct dis386 float_reg[][8] = {
10221 /* d8 */
10222 {
10223 { "fadd", { ST, STi }, 0 },
10224 { "fmul", { ST, STi }, 0 },
10225 { "fcom", { STi }, 0 },
10226 { "fcomp", { STi }, 0 },
10227 { "fsub", { ST, STi }, 0 },
10228 { "fsubr", { ST, STi }, 0 },
10229 { "fdiv", { ST, STi }, 0 },
10230 { "fdivr", { ST, STi }, 0 },
10231 },
10232 /* d9 */
10233 {
10234 { "fld", { STi }, 0 },
10235 { "fxch", { STi }, 0 },
10236 { FGRPd9_2 },
10237 { Bad_Opcode },
10238 { FGRPd9_4 },
10239 { FGRPd9_5 },
10240 { FGRPd9_6 },
10241 { FGRPd9_7 },
10242 },
10243 /* da */
10244 {
10245 { "fcmovb", { ST, STi }, 0 },
10246 { "fcmove", { ST, STi }, 0 },
10247 { "fcmovbe",{ ST, STi }, 0 },
10248 { "fcmovu", { ST, STi }, 0 },
10249 { Bad_Opcode },
10250 { FGRPda_5 },
10251 { Bad_Opcode },
10252 { Bad_Opcode },
10253 },
10254 /* db */
10255 {
10256 { "fcmovnb",{ ST, STi }, 0 },
10257 { "fcmovne",{ ST, STi }, 0 },
10258 { "fcmovnbe",{ ST, STi }, 0 },
10259 { "fcmovnu",{ ST, STi }, 0 },
10260 { FGRPdb_4 },
10261 { "fucomi", { ST, STi }, 0 },
10262 { "fcomi", { ST, STi }, 0 },
10263 { Bad_Opcode },
10264 },
10265 /* dc */
10266 {
10267 { "fadd", { STi, ST }, 0 },
10268 { "fmul", { STi, ST }, 0 },
10269 { Bad_Opcode },
10270 { Bad_Opcode },
10271 { "fsub{!M|r}", { STi, ST }, 0 },
10272 { "fsub{M|}", { STi, ST }, 0 },
10273 { "fdiv{!M|r}", { STi, ST }, 0 },
10274 { "fdiv{M|}", { STi, ST }, 0 },
10275 },
10276 /* dd */
10277 {
10278 { "ffree", { STi }, 0 },
10279 { Bad_Opcode },
10280 { "fst", { STi }, 0 },
10281 { "fstp", { STi }, 0 },
10282 { "fucom", { STi }, 0 },
10283 { "fucomp", { STi }, 0 },
10284 { Bad_Opcode },
10285 { Bad_Opcode },
10286 },
10287 /* de */
10288 {
10289 { "faddp", { STi, ST }, 0 },
10290 { "fmulp", { STi, ST }, 0 },
10291 { Bad_Opcode },
10292 { FGRPde_3 },
10293 { "fsub{!M|r}p", { STi, ST }, 0 },
10294 { "fsub{M|}p", { STi, ST }, 0 },
10295 { "fdiv{!M|r}p", { STi, ST }, 0 },
10296 { "fdiv{M|}p", { STi, ST }, 0 },
10297 },
10298 /* df */
10299 {
10300 { "ffreep", { STi }, 0 },
10301 { Bad_Opcode },
10302 { Bad_Opcode },
10303 { Bad_Opcode },
10304 { FGRPdf_4 },
10305 { "fucomip", { ST, STi }, 0 },
10306 { "fcomip", { ST, STi }, 0 },
10307 { Bad_Opcode },
10308 },
10309 };
10310
10311 static char *fgrps[][8] = {
10312 /* Bad opcode 0 */
10313 {
10314 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10315 },
10316
10317 /* d9_2 1 */
10318 {
10319 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10320 },
10321
10322 /* d9_4 2 */
10323 {
10324 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10325 },
10326
10327 /* d9_5 3 */
10328 {
10329 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10330 },
10331
10332 /* d9_6 4 */
10333 {
10334 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10335 },
10336
10337 /* d9_7 5 */
10338 {
10339 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10340 },
10341
10342 /* da_5 6 */
10343 {
10344 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10345 },
10346
10347 /* db_4 7 */
10348 {
10349 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10350 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10351 },
10352
10353 /* de_3 8 */
10354 {
10355 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10356 },
10357
10358 /* df_4 9 */
10359 {
10360 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10361 },
10362 };
10363
10364 static void
10365 swap_operand (void)
10366 {
10367 mnemonicendp[0] = '.';
10368 mnemonicendp[1] = 's';
10369 mnemonicendp += 2;
10370 }
10371
10372 static void
10373 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10374 int sizeflag ATTRIBUTE_UNUSED)
10375 {
10376 /* Skip mod/rm byte. */
10377 MODRM_CHECK;
10378 codep++;
10379 }
10380
10381 static void
10382 dofloat (int sizeflag)
10383 {
10384 const struct dis386 *dp;
10385 unsigned char floatop;
10386
10387 floatop = codep[-1];
10388
10389 if (modrm.mod != 3)
10390 {
10391 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10392
10393 putop (float_mem[fp_indx], sizeflag);
10394 obufp = op_out[0];
10395 op_ad = 2;
10396 OP_E (float_mem_mode[fp_indx], sizeflag);
10397 return;
10398 }
10399 /* Skip mod/rm byte. */
10400 MODRM_CHECK;
10401 codep++;
10402
10403 dp = &float_reg[floatop - 0xd8][modrm.reg];
10404 if (dp->name == NULL)
10405 {
10406 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10407
10408 /* Instruction fnstsw is only one with strange arg. */
10409 if (floatop == 0xdf && codep[-1] == 0xe0)
10410 strcpy (op_out[0], names16[0]);
10411 }
10412 else
10413 {
10414 putop (dp->name, sizeflag);
10415
10416 obufp = op_out[0];
10417 op_ad = 2;
10418 if (dp->op[0].rtn)
10419 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10420
10421 obufp = op_out[1];
10422 op_ad = 1;
10423 if (dp->op[1].rtn)
10424 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10425 }
10426 }
10427
10428 /* Like oappend (below), but S is a string starting with '%'.
10429 In Intel syntax, the '%' is elided. */
10430 static void
10431 oappend_maybe_intel (const char *s)
10432 {
10433 oappend (s + intel_syntax);
10434 }
10435
10436 static void
10437 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10438 {
10439 oappend_maybe_intel ("%st");
10440 }
10441
10442 static void
10443 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10444 {
10445 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10446 oappend_maybe_intel (scratchbuf);
10447 }
10448
10449 /* Capital letters in template are macros. */
10450 static int
10451 putop (const char *in_template, int sizeflag)
10452 {
10453 const char *p;
10454 int alt = 0;
10455 int cond = 1;
10456 unsigned int l = 0, len = 0;
10457 char last[4];
10458
10459 for (p = in_template; *p; p++)
10460 {
10461 if (len > l)
10462 {
10463 if (l >= sizeof (last) || !ISUPPER (*p))
10464 abort ();
10465 last[l++] = *p;
10466 continue;
10467 }
10468 switch (*p)
10469 {
10470 default:
10471 *obufp++ = *p;
10472 break;
10473 case '%':
10474 len++;
10475 break;
10476 case '!':
10477 cond = 0;
10478 break;
10479 case '{':
10480 if (intel_syntax)
10481 {
10482 while (*++p != '|')
10483 if (*p == '}' || *p == '\0')
10484 abort ();
10485 alt = 1;
10486 }
10487 break;
10488 case '|':
10489 while (*++p != '}')
10490 {
10491 if (*p == '\0')
10492 abort ();
10493 }
10494 break;
10495 case '}':
10496 alt = 0;
10497 break;
10498 case 'A':
10499 if (intel_syntax)
10500 break;
10501 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10502 *obufp++ = 'b';
10503 break;
10504 case 'B':
10505 if (l == 0)
10506 {
10507 case_B:
10508 if (intel_syntax)
10509 break;
10510 if (sizeflag & SUFFIX_ALWAYS)
10511 *obufp++ = 'b';
10512 }
10513 else if (l == 1 && last[0] == 'L')
10514 {
10515 if (address_mode == mode_64bit
10516 && !(prefixes & PREFIX_ADDR))
10517 {
10518 *obufp++ = 'a';
10519 *obufp++ = 'b';
10520 *obufp++ = 's';
10521 }
10522
10523 goto case_B;
10524 }
10525 else
10526 abort ();
10527 break;
10528 case 'C':
10529 if (intel_syntax && !alt)
10530 break;
10531 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10532 {
10533 if (sizeflag & DFLAG)
10534 *obufp++ = intel_syntax ? 'd' : 'l';
10535 else
10536 *obufp++ = intel_syntax ? 'w' : 's';
10537 used_prefixes |= (prefixes & PREFIX_DATA);
10538 }
10539 break;
10540 case 'D':
10541 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10542 break;
10543 USED_REX (REX_W);
10544 if (modrm.mod == 3)
10545 {
10546 if (rex & REX_W)
10547 *obufp++ = 'q';
10548 else
10549 {
10550 if (sizeflag & DFLAG)
10551 *obufp++ = intel_syntax ? 'd' : 'l';
10552 else
10553 *obufp++ = 'w';
10554 used_prefixes |= (prefixes & PREFIX_DATA);
10555 }
10556 }
10557 else
10558 *obufp++ = 'w';
10559 break;
10560 case 'E': /* For jcxz/jecxz */
10561 if (address_mode == mode_64bit)
10562 {
10563 if (sizeflag & AFLAG)
10564 *obufp++ = 'r';
10565 else
10566 *obufp++ = 'e';
10567 }
10568 else
10569 if (sizeflag & AFLAG)
10570 *obufp++ = 'e';
10571 used_prefixes |= (prefixes & PREFIX_ADDR);
10572 break;
10573 case 'F':
10574 if (intel_syntax)
10575 break;
10576 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10577 {
10578 if (sizeflag & AFLAG)
10579 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10580 else
10581 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10582 used_prefixes |= (prefixes & PREFIX_ADDR);
10583 }
10584 break;
10585 case 'G':
10586 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10587 break;
10588 if ((rex & REX_W) || (sizeflag & DFLAG))
10589 *obufp++ = 'l';
10590 else
10591 *obufp++ = 'w';
10592 if (!(rex & REX_W))
10593 used_prefixes |= (prefixes & PREFIX_DATA);
10594 break;
10595 case 'H':
10596 if (intel_syntax)
10597 break;
10598 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10599 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10600 {
10601 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10602 *obufp++ = ',';
10603 *obufp++ = 'p';
10604 if (prefixes & PREFIX_DS)
10605 *obufp++ = 't';
10606 else
10607 *obufp++ = 'n';
10608 }
10609 break;
10610 case 'K':
10611 USED_REX (REX_W);
10612 if (rex & REX_W)
10613 *obufp++ = 'q';
10614 else
10615 *obufp++ = 'd';
10616 break;
10617 case 'L':
10618 abort ();
10619 case 'M':
10620 if (intel_mnemonic != cond)
10621 *obufp++ = 'r';
10622 break;
10623 case 'N':
10624 if ((prefixes & PREFIX_FWAIT) == 0)
10625 *obufp++ = 'n';
10626 else
10627 used_prefixes |= PREFIX_FWAIT;
10628 break;
10629 case 'O':
10630 USED_REX (REX_W);
10631 if (rex & REX_W)
10632 *obufp++ = 'o';
10633 else if (intel_syntax && (sizeflag & DFLAG))
10634 *obufp++ = 'q';
10635 else
10636 *obufp++ = 'd';
10637 if (!(rex & REX_W))
10638 used_prefixes |= (prefixes & PREFIX_DATA);
10639 break;
10640 case '&':
10641 if (!intel_syntax
10642 && address_mode == mode_64bit
10643 && isa64 == intel64)
10644 {
10645 *obufp++ = 'q';
10646 break;
10647 }
10648 /* Fall through. */
10649 case 'T':
10650 if (!intel_syntax
10651 && address_mode == mode_64bit
10652 && ((sizeflag & DFLAG) || (rex & REX_W)))
10653 {
10654 *obufp++ = 'q';
10655 break;
10656 }
10657 /* Fall through. */
10658 goto case_P;
10659 case 'P':
10660 if (l == 0)
10661 {
10662 case_P:
10663 if (intel_syntax)
10664 {
10665 if ((rex & REX_W) == 0
10666 && (prefixes & PREFIX_DATA))
10667 {
10668 if ((sizeflag & DFLAG) == 0)
10669 *obufp++ = 'w';
10670 used_prefixes |= (prefixes & PREFIX_DATA);
10671 }
10672 break;
10673 }
10674 if ((prefixes & PREFIX_DATA)
10675 || (rex & REX_W)
10676 || (sizeflag & SUFFIX_ALWAYS))
10677 {
10678 USED_REX (REX_W);
10679 if (rex & REX_W)
10680 *obufp++ = 'q';
10681 else
10682 {
10683 if (sizeflag & DFLAG)
10684 *obufp++ = 'l';
10685 else
10686 *obufp++ = 'w';
10687 used_prefixes |= (prefixes & PREFIX_DATA);
10688 }
10689 }
10690 }
10691 else if (l == 1 && last[0] == 'L')
10692 {
10693 if ((prefixes & PREFIX_DATA)
10694 || (rex & REX_W)
10695 || (sizeflag & SUFFIX_ALWAYS))
10696 {
10697 USED_REX (REX_W);
10698 if (rex & REX_W)
10699 *obufp++ = 'q';
10700 else
10701 {
10702 if (sizeflag & DFLAG)
10703 *obufp++ = intel_syntax ? 'd' : 'l';
10704 else
10705 *obufp++ = 'w';
10706 used_prefixes |= (prefixes & PREFIX_DATA);
10707 }
10708 }
10709 }
10710 else
10711 abort ();
10712 break;
10713 case 'U':
10714 if (intel_syntax)
10715 break;
10716 if (address_mode == mode_64bit
10717 && ((sizeflag & DFLAG) || (rex & REX_W)))
10718 {
10719 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10720 *obufp++ = 'q';
10721 break;
10722 }
10723 /* Fall through. */
10724 goto case_Q;
10725 case 'Q':
10726 if (l == 0)
10727 {
10728 case_Q:
10729 if (intel_syntax && !alt)
10730 break;
10731 USED_REX (REX_W);
10732 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10733 {
10734 if (rex & REX_W)
10735 *obufp++ = 'q';
10736 else
10737 {
10738 if (sizeflag & DFLAG)
10739 *obufp++ = intel_syntax ? 'd' : 'l';
10740 else
10741 *obufp++ = 'w';
10742 used_prefixes |= (prefixes & PREFIX_DATA);
10743 }
10744 }
10745 }
10746 else if (l == 1 && last[0] == 'D')
10747 *obufp++ = vex.w ? 'q' : 'd';
10748 else if (l == 1 && last[0] == 'L')
10749 {
10750 if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10751 : address_mode != mode_64bit)
10752 break;
10753 if ((rex & REX_W))
10754 {
10755 USED_REX (REX_W);
10756 *obufp++ = 'q';
10757 }
10758 else if((address_mode == mode_64bit && need_modrm && cond)
10759 || (sizeflag & SUFFIX_ALWAYS))
10760 *obufp++ = intel_syntax? 'd' : 'l';
10761 }
10762 else
10763 abort ();
10764 break;
10765 case 'R':
10766 USED_REX (REX_W);
10767 if (rex & REX_W)
10768 *obufp++ = 'q';
10769 else if (sizeflag & DFLAG)
10770 {
10771 if (intel_syntax)
10772 *obufp++ = 'd';
10773 else
10774 *obufp++ = 'l';
10775 }
10776 else
10777 *obufp++ = 'w';
10778 if (intel_syntax && !p[1]
10779 && ((rex & REX_W) || (sizeflag & DFLAG)))
10780 *obufp++ = 'e';
10781 if (!(rex & REX_W))
10782 used_prefixes |= (prefixes & PREFIX_DATA);
10783 break;
10784 case 'V':
10785 if (l == 0)
10786 {
10787 if (intel_syntax)
10788 break;
10789 if (address_mode == mode_64bit
10790 && ((sizeflag & DFLAG) || (rex & REX_W)))
10791 {
10792 if (sizeflag & SUFFIX_ALWAYS)
10793 *obufp++ = 'q';
10794 break;
10795 }
10796 }
10797 else if (l == 1 && last[0] == 'L')
10798 {
10799 if (rex & REX_W)
10800 {
10801 *obufp++ = 'a';
10802 *obufp++ = 'b';
10803 *obufp++ = 's';
10804 }
10805 }
10806 else
10807 abort ();
10808 /* Fall through. */
10809 goto case_S;
10810 case 'S':
10811 if (l == 0)
10812 {
10813 case_S:
10814 if (intel_syntax)
10815 break;
10816 if (sizeflag & SUFFIX_ALWAYS)
10817 {
10818 if (rex & REX_W)
10819 *obufp++ = 'q';
10820 else
10821 {
10822 if (sizeflag & DFLAG)
10823 *obufp++ = 'l';
10824 else
10825 *obufp++ = 'w';
10826 used_prefixes |= (prefixes & PREFIX_DATA);
10827 }
10828 }
10829 }
10830 else if (l == 1 && last[0] == 'L')
10831 {
10832 if (address_mode == mode_64bit
10833 && !(prefixes & PREFIX_ADDR))
10834 {
10835 *obufp++ = 'a';
10836 *obufp++ = 'b';
10837 *obufp++ = 's';
10838 }
10839
10840 goto case_S;
10841 }
10842 else
10843 abort ();
10844 break;
10845 case 'X':
10846 if (l != 0)
10847 abort ();
10848 if (need_vex
10849 ? vex.prefix == DATA_PREFIX_OPCODE
10850 : prefixes & PREFIX_DATA)
10851 {
10852 *obufp++ = 'd';
10853 used_prefixes |= PREFIX_DATA;
10854 }
10855 else
10856 *obufp++ = 's';
10857 break;
10858 case 'Y':
10859 if (l == 1 && last[0] == 'X')
10860 {
10861 if (!need_vex)
10862 abort ();
10863 if (intel_syntax
10864 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10865 break;
10866 switch (vex.length)
10867 {
10868 case 128:
10869 *obufp++ = 'x';
10870 break;
10871 case 256:
10872 *obufp++ = 'y';
10873 break;
10874 case 512:
10875 if (!vex.evex)
10876 default:
10877 abort ();
10878 }
10879 }
10880 else
10881 abort ();
10882 break;
10883 case 'Z':
10884 if (l == 0)
10885 {
10886 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10887 modrm.mod = 3;
10888 if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10889 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10890 }
10891 else if (l == 1 && last[0] == 'X')
10892 {
10893 if (!need_vex || !vex.evex)
10894 abort ();
10895 if (intel_syntax
10896 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10897 break;
10898 switch (vex.length)
10899 {
10900 case 128:
10901 *obufp++ = 'x';
10902 break;
10903 case 256:
10904 *obufp++ = 'y';
10905 break;
10906 case 512:
10907 *obufp++ = 'z';
10908 break;
10909 default:
10910 abort ();
10911 }
10912 }
10913 else
10914 abort ();
10915 break;
10916 case 'W':
10917 if (l == 0)
10918 {
10919 /* operand size flag for cwtl, cbtw */
10920 USED_REX (REX_W);
10921 if (rex & REX_W)
10922 {
10923 if (intel_syntax)
10924 *obufp++ = 'd';
10925 else
10926 *obufp++ = 'l';
10927 }
10928 else if (sizeflag & DFLAG)
10929 *obufp++ = 'w';
10930 else
10931 *obufp++ = 'b';
10932 if (!(rex & REX_W))
10933 used_prefixes |= (prefixes & PREFIX_DATA);
10934 }
10935 else if (l == 1)
10936 {
10937 if (!need_vex)
10938 abort ();
10939 if (last[0] == 'X')
10940 *obufp++ = vex.w ? 'd': 's';
10941 else if (last[0] == 'B')
10942 *obufp++ = vex.w ? 'w': 'b';
10943 else
10944 abort ();
10945 }
10946 else
10947 abort ();
10948 break;
10949 case '^':
10950 if (intel_syntax)
10951 break;
10952 if (isa64 == intel64 && (rex & REX_W))
10953 {
10954 USED_REX (REX_W);
10955 *obufp++ = 'q';
10956 break;
10957 }
10958 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10959 {
10960 if (sizeflag & DFLAG)
10961 *obufp++ = 'l';
10962 else
10963 *obufp++ = 'w';
10964 used_prefixes |= (prefixes & PREFIX_DATA);
10965 }
10966 break;
10967 case '@':
10968 if (intel_syntax)
10969 break;
10970 if (address_mode == mode_64bit
10971 && (isa64 == intel64
10972 || ((sizeflag & DFLAG) || (rex & REX_W))))
10973 *obufp++ = 'q';
10974 else if ((prefixes & PREFIX_DATA))
10975 {
10976 if (!(sizeflag & DFLAG))
10977 *obufp++ = 'w';
10978 used_prefixes |= (prefixes & PREFIX_DATA);
10979 }
10980 break;
10981 }
10982
10983 if (len == l)
10984 len = l = 0;
10985 }
10986 *obufp = 0;
10987 mnemonicendp = obufp;
10988 return 0;
10989 }
10990
10991 static void
10992 oappend (const char *s)
10993 {
10994 obufp = stpcpy (obufp, s);
10995 }
10996
10997 static void
10998 append_seg (void)
10999 {
11000 /* Only print the active segment register. */
11001 if (!active_seg_prefix)
11002 return;
11003
11004 used_prefixes |= active_seg_prefix;
11005 switch (active_seg_prefix)
11006 {
11007 case PREFIX_CS:
11008 oappend_maybe_intel ("%cs:");
11009 break;
11010 case PREFIX_DS:
11011 oappend_maybe_intel ("%ds:");
11012 break;
11013 case PREFIX_SS:
11014 oappend_maybe_intel ("%ss:");
11015 break;
11016 case PREFIX_ES:
11017 oappend_maybe_intel ("%es:");
11018 break;
11019 case PREFIX_FS:
11020 oappend_maybe_intel ("%fs:");
11021 break;
11022 case PREFIX_GS:
11023 oappend_maybe_intel ("%gs:");
11024 break;
11025 default:
11026 break;
11027 }
11028 }
11029
11030 static void
11031 OP_indirE (int bytemode, int sizeflag)
11032 {
11033 if (!intel_syntax)
11034 oappend ("*");
11035 OP_E (bytemode, sizeflag);
11036 }
11037
11038 static void
11039 print_operand_value (char *buf, int hex, bfd_vma disp)
11040 {
11041 if (address_mode == mode_64bit)
11042 {
11043 if (hex)
11044 {
11045 char tmp[30];
11046 int i;
11047 buf[0] = '0';
11048 buf[1] = 'x';
11049 sprintf_vma (tmp, disp);
11050 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11051 strcpy (buf + 2, tmp + i);
11052 }
11053 else
11054 {
11055 bfd_signed_vma v = disp;
11056 char tmp[30];
11057 int i;
11058 if (v < 0)
11059 {
11060 *(buf++) = '-';
11061 v = -disp;
11062 /* Check for possible overflow on 0x8000000000000000. */
11063 if (v < 0)
11064 {
11065 strcpy (buf, "9223372036854775808");
11066 return;
11067 }
11068 }
11069 if (!v)
11070 {
11071 strcpy (buf, "0");
11072 return;
11073 }
11074
11075 i = 0;
11076 tmp[29] = 0;
11077 while (v)
11078 {
11079 tmp[28 - i] = (v % 10) + '0';
11080 v /= 10;
11081 i++;
11082 }
11083 strcpy (buf, tmp + 29 - i);
11084 }
11085 }
11086 else
11087 {
11088 if (hex)
11089 sprintf (buf, "0x%x", (unsigned int) disp);
11090 else
11091 sprintf (buf, "%d", (int) disp);
11092 }
11093 }
11094
11095 /* Put DISP in BUF as signed hex number. */
11096
11097 static void
11098 print_displacement (char *buf, bfd_vma disp)
11099 {
11100 bfd_signed_vma val = disp;
11101 char tmp[30];
11102 int i, j = 0;
11103
11104 if (val < 0)
11105 {
11106 buf[j++] = '-';
11107 val = -disp;
11108
11109 /* Check for possible overflow. */
11110 if (val < 0)
11111 {
11112 switch (address_mode)
11113 {
11114 case mode_64bit:
11115 strcpy (buf + j, "0x8000000000000000");
11116 break;
11117 case mode_32bit:
11118 strcpy (buf + j, "0x80000000");
11119 break;
11120 case mode_16bit:
11121 strcpy (buf + j, "0x8000");
11122 break;
11123 }
11124 return;
11125 }
11126 }
11127
11128 buf[j++] = '0';
11129 buf[j++] = 'x';
11130
11131 sprintf_vma (tmp, (bfd_vma) val);
11132 for (i = 0; tmp[i] == '0'; i++)
11133 continue;
11134 if (tmp[i] == '\0')
11135 i--;
11136 strcpy (buf + j, tmp + i);
11137 }
11138
11139 static void
11140 intel_operand_size (int bytemode, int sizeflag)
11141 {
11142 if (vex.evex
11143 && vex.b
11144 && (bytemode == x_mode
11145 || bytemode == evex_half_bcst_xmmq_mode))
11146 {
11147 if (vex.w)
11148 oappend ("QWORD PTR ");
11149 else
11150 oappend ("DWORD PTR ");
11151 return;
11152 }
11153 switch (bytemode)
11154 {
11155 case b_mode:
11156 case b_swap_mode:
11157 case dqb_mode:
11158 case db_mode:
11159 oappend ("BYTE PTR ");
11160 break;
11161 case w_mode:
11162 case dw_mode:
11163 case dqw_mode:
11164 oappend ("WORD PTR ");
11165 break;
11166 case indir_v_mode:
11167 if (address_mode == mode_64bit && isa64 == intel64)
11168 {
11169 oappend ("QWORD PTR ");
11170 break;
11171 }
11172 /* Fall through. */
11173 case stack_v_mode:
11174 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11175 {
11176 oappend ("QWORD PTR ");
11177 break;
11178 }
11179 /* Fall through. */
11180 case v_mode:
11181 case v_swap_mode:
11182 case dq_mode:
11183 USED_REX (REX_W);
11184 if (rex & REX_W)
11185 oappend ("QWORD PTR ");
11186 else if (bytemode == dq_mode)
11187 oappend ("DWORD PTR ");
11188 else
11189 {
11190 if (sizeflag & DFLAG)
11191 oappend ("DWORD PTR ");
11192 else
11193 oappend ("WORD PTR ");
11194 used_prefixes |= (prefixes & PREFIX_DATA);
11195 }
11196 break;
11197 case z_mode:
11198 if ((rex & REX_W) || (sizeflag & DFLAG))
11199 *obufp++ = 'D';
11200 oappend ("WORD PTR ");
11201 if (!(rex & REX_W))
11202 used_prefixes |= (prefixes & PREFIX_DATA);
11203 break;
11204 case a_mode:
11205 if (sizeflag & DFLAG)
11206 oappend ("QWORD PTR ");
11207 else
11208 oappend ("DWORD PTR ");
11209 used_prefixes |= (prefixes & PREFIX_DATA);
11210 break;
11211 case movsxd_mode:
11212 if (!(sizeflag & DFLAG) && isa64 == intel64)
11213 oappend ("WORD PTR ");
11214 else
11215 oappend ("DWORD PTR ");
11216 used_prefixes |= (prefixes & PREFIX_DATA);
11217 break;
11218 case d_mode:
11219 case d_swap_mode:
11220 case dqd_mode:
11221 oappend ("DWORD PTR ");
11222 break;
11223 case q_mode:
11224 case q_swap_mode:
11225 oappend ("QWORD PTR ");
11226 break;
11227 case m_mode:
11228 if (address_mode == mode_64bit)
11229 oappend ("QWORD PTR ");
11230 else
11231 oappend ("DWORD PTR ");
11232 break;
11233 case f_mode:
11234 if (sizeflag & DFLAG)
11235 oappend ("FWORD PTR ");
11236 else
11237 oappend ("DWORD PTR ");
11238 used_prefixes |= (prefixes & PREFIX_DATA);
11239 break;
11240 case t_mode:
11241 oappend ("TBYTE PTR ");
11242 break;
11243 case x_mode:
11244 case x_swap_mode:
11245 case evex_x_gscat_mode:
11246 case evex_x_nobcst_mode:
11247 case bw_unit_mode:
11248 if (need_vex)
11249 {
11250 switch (vex.length)
11251 {
11252 case 128:
11253 oappend ("XMMWORD PTR ");
11254 break;
11255 case 256:
11256 oappend ("YMMWORD PTR ");
11257 break;
11258 case 512:
11259 oappend ("ZMMWORD PTR ");
11260 break;
11261 default:
11262 abort ();
11263 }
11264 }
11265 else
11266 oappend ("XMMWORD PTR ");
11267 break;
11268 case xmm_mode:
11269 oappend ("XMMWORD PTR ");
11270 break;
11271 case ymm_mode:
11272 oappend ("YMMWORD PTR ");
11273 break;
11274 case xmmq_mode:
11275 case evex_half_bcst_xmmq_mode:
11276 if (!need_vex)
11277 abort ();
11278
11279 switch (vex.length)
11280 {
11281 case 128:
11282 oappend ("QWORD PTR ");
11283 break;
11284 case 256:
11285 oappend ("XMMWORD PTR ");
11286 break;
11287 case 512:
11288 oappend ("YMMWORD PTR ");
11289 break;
11290 default:
11291 abort ();
11292 }
11293 break;
11294 case xmm_mb_mode:
11295 if (!need_vex)
11296 abort ();
11297
11298 switch (vex.length)
11299 {
11300 case 128:
11301 case 256:
11302 case 512:
11303 oappend ("BYTE PTR ");
11304 break;
11305 default:
11306 abort ();
11307 }
11308 break;
11309 case xmm_mw_mode:
11310 if (!need_vex)
11311 abort ();
11312
11313 switch (vex.length)
11314 {
11315 case 128:
11316 case 256:
11317 case 512:
11318 oappend ("WORD PTR ");
11319 break;
11320 default:
11321 abort ();
11322 }
11323 break;
11324 case xmm_md_mode:
11325 if (!need_vex)
11326 abort ();
11327
11328 switch (vex.length)
11329 {
11330 case 128:
11331 case 256:
11332 case 512:
11333 oappend ("DWORD PTR ");
11334 break;
11335 default:
11336 abort ();
11337 }
11338 break;
11339 case xmm_mq_mode:
11340 if (!need_vex)
11341 abort ();
11342
11343 switch (vex.length)
11344 {
11345 case 128:
11346 case 256:
11347 case 512:
11348 oappend ("QWORD PTR ");
11349 break;
11350 default:
11351 abort ();
11352 }
11353 break;
11354 case xmmdw_mode:
11355 if (!need_vex)
11356 abort ();
11357
11358 switch (vex.length)
11359 {
11360 case 128:
11361 oappend ("WORD PTR ");
11362 break;
11363 case 256:
11364 oappend ("DWORD PTR ");
11365 break;
11366 case 512:
11367 oappend ("QWORD PTR ");
11368 break;
11369 default:
11370 abort ();
11371 }
11372 break;
11373 case xmmqd_mode:
11374 if (!need_vex)
11375 abort ();
11376
11377 switch (vex.length)
11378 {
11379 case 128:
11380 oappend ("DWORD PTR ");
11381 break;
11382 case 256:
11383 oappend ("QWORD PTR ");
11384 break;
11385 case 512:
11386 oappend ("XMMWORD PTR ");
11387 break;
11388 default:
11389 abort ();
11390 }
11391 break;
11392 case ymmq_mode:
11393 if (!need_vex)
11394 abort ();
11395
11396 switch (vex.length)
11397 {
11398 case 128:
11399 oappend ("QWORD PTR ");
11400 break;
11401 case 256:
11402 oappend ("YMMWORD PTR ");
11403 break;
11404 case 512:
11405 oappend ("ZMMWORD PTR ");
11406 break;
11407 default:
11408 abort ();
11409 }
11410 break;
11411 case ymmxmm_mode:
11412 if (!need_vex)
11413 abort ();
11414
11415 switch (vex.length)
11416 {
11417 case 128:
11418 case 256:
11419 oappend ("XMMWORD PTR ");
11420 break;
11421 default:
11422 abort ();
11423 }
11424 break;
11425 case o_mode:
11426 oappend ("OWORD PTR ");
11427 break;
11428 case vex_scalar_w_dq_mode:
11429 if (!need_vex)
11430 abort ();
11431
11432 if (vex.w)
11433 oappend ("QWORD PTR ");
11434 else
11435 oappend ("DWORD PTR ");
11436 break;
11437 case vex_vsib_d_w_dq_mode:
11438 case vex_vsib_q_w_dq_mode:
11439 if (!need_vex)
11440 abort ();
11441
11442 if (!vex.evex)
11443 {
11444 if (vex.w)
11445 oappend ("QWORD PTR ");
11446 else
11447 oappend ("DWORD PTR ");
11448 }
11449 else
11450 {
11451 switch (vex.length)
11452 {
11453 case 128:
11454 oappend ("XMMWORD PTR ");
11455 break;
11456 case 256:
11457 oappend ("YMMWORD PTR ");
11458 break;
11459 case 512:
11460 oappend ("ZMMWORD PTR ");
11461 break;
11462 default:
11463 abort ();
11464 }
11465 }
11466 break;
11467 case vex_vsib_q_w_d_mode:
11468 case vex_vsib_d_w_d_mode:
11469 if (!need_vex || !vex.evex)
11470 abort ();
11471
11472 switch (vex.length)
11473 {
11474 case 128:
11475 oappend ("QWORD PTR ");
11476 break;
11477 case 256:
11478 oappend ("XMMWORD PTR ");
11479 break;
11480 case 512:
11481 oappend ("YMMWORD PTR ");
11482 break;
11483 default:
11484 abort ();
11485 }
11486
11487 break;
11488 case mask_bd_mode:
11489 if (!need_vex || vex.length != 128)
11490 abort ();
11491 if (vex.w)
11492 oappend ("DWORD PTR ");
11493 else
11494 oappend ("BYTE PTR ");
11495 break;
11496 case mask_mode:
11497 if (!need_vex)
11498 abort ();
11499 if (vex.w)
11500 oappend ("QWORD PTR ");
11501 else
11502 oappend ("WORD PTR ");
11503 break;
11504 case v_bnd_mode:
11505 case v_bndmk_mode:
11506 default:
11507 break;
11508 }
11509 }
11510
11511 static void
11512 OP_E_register (int bytemode, int sizeflag)
11513 {
11514 int reg = modrm.rm;
11515 const char **names;
11516
11517 USED_REX (REX_B);
11518 if ((rex & REX_B))
11519 reg += 8;
11520
11521 if ((sizeflag & SUFFIX_ALWAYS)
11522 && (bytemode == b_swap_mode
11523 || bytemode == bnd_swap_mode
11524 || bytemode == v_swap_mode))
11525 swap_operand ();
11526
11527 switch (bytemode)
11528 {
11529 case b_mode:
11530 case b_swap_mode:
11531 if (reg & 4)
11532 USED_REX (0);
11533 if (rex)
11534 names = names8rex;
11535 else
11536 names = names8;
11537 break;
11538 case w_mode:
11539 names = names16;
11540 break;
11541 case d_mode:
11542 case dw_mode:
11543 case db_mode:
11544 names = names32;
11545 break;
11546 case q_mode:
11547 names = names64;
11548 break;
11549 case m_mode:
11550 case v_bnd_mode:
11551 names = address_mode == mode_64bit ? names64 : names32;
11552 break;
11553 case bnd_mode:
11554 case bnd_swap_mode:
11555 if (reg > 0x3)
11556 {
11557 oappend ("(bad)");
11558 return;
11559 }
11560 names = names_bnd;
11561 break;
11562 case indir_v_mode:
11563 if (address_mode == mode_64bit && isa64 == intel64)
11564 {
11565 names = names64;
11566 break;
11567 }
11568 /* Fall through. */
11569 case stack_v_mode:
11570 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11571 {
11572 names = names64;
11573 break;
11574 }
11575 bytemode = v_mode;
11576 /* Fall through. */
11577 case v_mode:
11578 case v_swap_mode:
11579 case dq_mode:
11580 case dqb_mode:
11581 case dqd_mode:
11582 case dqw_mode:
11583 USED_REX (REX_W);
11584 if (rex & REX_W)
11585 names = names64;
11586 else if (bytemode != v_mode && bytemode != v_swap_mode)
11587 names = names32;
11588 else
11589 {
11590 if (sizeflag & DFLAG)
11591 names = names32;
11592 else
11593 names = names16;
11594 used_prefixes |= (prefixes & PREFIX_DATA);
11595 }
11596 break;
11597 case movsxd_mode:
11598 if (!(sizeflag & DFLAG) && isa64 == intel64)
11599 names = names16;
11600 else
11601 names = names32;
11602 used_prefixes |= (prefixes & PREFIX_DATA);
11603 break;
11604 case va_mode:
11605 names = (address_mode == mode_64bit
11606 ? names64 : names32);
11607 if (!(prefixes & PREFIX_ADDR))
11608 names = (address_mode == mode_16bit
11609 ? names16 : names);
11610 else
11611 {
11612 /* Remove "addr16/addr32". */
11613 all_prefixes[last_addr_prefix] = 0;
11614 names = (address_mode != mode_32bit
11615 ? names32 : names16);
11616 used_prefixes |= PREFIX_ADDR;
11617 }
11618 break;
11619 case mask_bd_mode:
11620 case mask_mode:
11621 if (reg > 0x7)
11622 {
11623 oappend ("(bad)");
11624 return;
11625 }
11626 names = names_mask;
11627 break;
11628 case 0:
11629 return;
11630 default:
11631 oappend (INTERNAL_DISASSEMBLER_ERROR);
11632 return;
11633 }
11634 oappend (names[reg]);
11635 }
11636
11637 static void
11638 OP_E_memory (int bytemode, int sizeflag)
11639 {
11640 bfd_vma disp = 0;
11641 int add = (rex & REX_B) ? 8 : 0;
11642 int riprel = 0;
11643 int shift;
11644
11645 if (vex.evex)
11646 {
11647 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11648 if (vex.b
11649 && bytemode != x_mode
11650 && bytemode != xmmq_mode
11651 && bytemode != evex_half_bcst_xmmq_mode)
11652 {
11653 BadOp ();
11654 return;
11655 }
11656 switch (bytemode)
11657 {
11658 case dqw_mode:
11659 case dw_mode:
11660 case xmm_mw_mode:
11661 shift = 1;
11662 break;
11663 case dqb_mode:
11664 case db_mode:
11665 case xmm_mb_mode:
11666 shift = 0;
11667 break;
11668 case dq_mode:
11669 if (address_mode != mode_64bit)
11670 {
11671 case dqd_mode:
11672 case xmm_md_mode:
11673 case d_mode:
11674 case d_swap_mode:
11675 shift = 2;
11676 break;
11677 }
11678 /* fall through */
11679 case vex_scalar_w_dq_mode:
11680 case vex_vsib_d_w_dq_mode:
11681 case vex_vsib_d_w_d_mode:
11682 case vex_vsib_q_w_dq_mode:
11683 case vex_vsib_q_w_d_mode:
11684 case evex_x_gscat_mode:
11685 shift = vex.w ? 3 : 2;
11686 break;
11687 case x_mode:
11688 case evex_half_bcst_xmmq_mode:
11689 case xmmq_mode:
11690 if (vex.b)
11691 {
11692 shift = vex.w ? 3 : 2;
11693 break;
11694 }
11695 /* Fall through. */
11696 case xmmqd_mode:
11697 case xmmdw_mode:
11698 case ymmq_mode:
11699 case evex_x_nobcst_mode:
11700 case x_swap_mode:
11701 switch (vex.length)
11702 {
11703 case 128:
11704 shift = 4;
11705 break;
11706 case 256:
11707 shift = 5;
11708 break;
11709 case 512:
11710 shift = 6;
11711 break;
11712 default:
11713 abort ();
11714 }
11715 /* Make necessary corrections to shift for modes that need it. */
11716 if (bytemode == xmmq_mode
11717 || bytemode == evex_half_bcst_xmmq_mode
11718 || (bytemode == ymmq_mode && vex.length == 128))
11719 shift -= 1;
11720 else if (bytemode == xmmqd_mode)
11721 shift -= 2;
11722 else if (bytemode == xmmdw_mode)
11723 shift -= 3;
11724 break;
11725 case ymm_mode:
11726 shift = 5;
11727 break;
11728 case xmm_mode:
11729 shift = 4;
11730 break;
11731 case xmm_mq_mode:
11732 case q_mode:
11733 case q_swap_mode:
11734 shift = 3;
11735 break;
11736 case bw_unit_mode:
11737 shift = vex.w ? 1 : 0;
11738 break;
11739 default:
11740 abort ();
11741 }
11742 }
11743 else
11744 shift = 0;
11745
11746 USED_REX (REX_B);
11747 if (intel_syntax)
11748 intel_operand_size (bytemode, sizeflag);
11749 append_seg ();
11750
11751 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11752 {
11753 /* 32/64 bit address mode */
11754 int havedisp;
11755 int havesib;
11756 int havebase;
11757 int haveindex;
11758 int needindex;
11759 int needaddr32;
11760 int base, rbase;
11761 int vindex = 0;
11762 int scale = 0;
11763 int addr32flag = !((sizeflag & AFLAG)
11764 || bytemode == v_bnd_mode
11765 || bytemode == v_bndmk_mode
11766 || bytemode == bnd_mode
11767 || bytemode == bnd_swap_mode);
11768 const char **indexes64 = names64;
11769 const char **indexes32 = names32;
11770
11771 havesib = 0;
11772 havebase = 1;
11773 haveindex = 0;
11774 base = modrm.rm;
11775
11776 if (base == 4)
11777 {
11778 havesib = 1;
11779 vindex = sib.index;
11780 USED_REX (REX_X);
11781 if (rex & REX_X)
11782 vindex += 8;
11783 switch (bytemode)
11784 {
11785 case vex_vsib_d_w_dq_mode:
11786 case vex_vsib_d_w_d_mode:
11787 case vex_vsib_q_w_dq_mode:
11788 case vex_vsib_q_w_d_mode:
11789 if (!need_vex)
11790 abort ();
11791 if (vex.evex)
11792 {
11793 if (!vex.v)
11794 vindex += 16;
11795 }
11796
11797 haveindex = 1;
11798 switch (vex.length)
11799 {
11800 case 128:
11801 indexes64 = indexes32 = names_xmm;
11802 break;
11803 case 256:
11804 if (!vex.w
11805 || bytemode == vex_vsib_q_w_dq_mode
11806 || bytemode == vex_vsib_q_w_d_mode)
11807 indexes64 = indexes32 = names_ymm;
11808 else
11809 indexes64 = indexes32 = names_xmm;
11810 break;
11811 case 512:
11812 if (!vex.w
11813 || bytemode == vex_vsib_q_w_dq_mode
11814 || bytemode == vex_vsib_q_w_d_mode)
11815 indexes64 = indexes32 = names_zmm;
11816 else
11817 indexes64 = indexes32 = names_ymm;
11818 break;
11819 default:
11820 abort ();
11821 }
11822 break;
11823 default:
11824 haveindex = vindex != 4;
11825 break;
11826 }
11827 scale = sib.scale;
11828 base = sib.base;
11829 codep++;
11830 }
11831 else
11832 {
11833 /* mandatory non-vector SIB must have sib */
11834 if (bytemode == vex_sibmem_mode)
11835 {
11836 oappend ("(bad)");
11837 return;
11838 }
11839 }
11840 rbase = base + add;
11841
11842 switch (modrm.mod)
11843 {
11844 case 0:
11845 if (base == 5)
11846 {
11847 havebase = 0;
11848 if (address_mode == mode_64bit && !havesib)
11849 riprel = 1;
11850 disp = get32s ();
11851 if (riprel && bytemode == v_bndmk_mode)
11852 {
11853 oappend ("(bad)");
11854 return;
11855 }
11856 }
11857 break;
11858 case 1:
11859 FETCH_DATA (the_info, codep + 1);
11860 disp = *codep++;
11861 if ((disp & 0x80) != 0)
11862 disp -= 0x100;
11863 if (vex.evex && shift > 0)
11864 disp <<= shift;
11865 break;
11866 case 2:
11867 disp = get32s ();
11868 break;
11869 }
11870
11871 needindex = 0;
11872 needaddr32 = 0;
11873 if (havesib
11874 && !havebase
11875 && !haveindex
11876 && address_mode != mode_16bit)
11877 {
11878 if (address_mode == mode_64bit)
11879 {
11880 /* Display eiz instead of addr32. */
11881 needindex = addr32flag;
11882 needaddr32 = 1;
11883 }
11884 else
11885 {
11886 /* In 32-bit mode, we need index register to tell [offset]
11887 from [eiz*1 + offset]. */
11888 needindex = 1;
11889 }
11890 }
11891
11892 havedisp = (havebase
11893 || needindex
11894 || (havesib && (haveindex || scale != 0)));
11895
11896 if (!intel_syntax)
11897 if (modrm.mod != 0 || base == 5)
11898 {
11899 if (havedisp || riprel)
11900 print_displacement (scratchbuf, disp);
11901 else
11902 print_operand_value (scratchbuf, 1, disp);
11903 oappend (scratchbuf);
11904 if (riprel)
11905 {
11906 set_op (disp, 1);
11907 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11908 }
11909 }
11910
11911 if ((havebase || haveindex || needindex || needaddr32 || riprel)
11912 && (address_mode != mode_64bit
11913 || ((bytemode != v_bnd_mode)
11914 && (bytemode != v_bndmk_mode)
11915 && (bytemode != bnd_mode)
11916 && (bytemode != bnd_swap_mode))))
11917 used_prefixes |= PREFIX_ADDR;
11918
11919 if (havedisp || (intel_syntax && riprel))
11920 {
11921 *obufp++ = open_char;
11922 if (intel_syntax && riprel)
11923 {
11924 set_op (disp, 1);
11925 oappend (!addr32flag ? "rip" : "eip");
11926 }
11927 *obufp = '\0';
11928 if (havebase)
11929 oappend (address_mode == mode_64bit && !addr32flag
11930 ? names64[rbase] : names32[rbase]);
11931 if (havesib)
11932 {
11933 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11934 print index to tell base + index from base. */
11935 if (scale != 0
11936 || needindex
11937 || haveindex
11938 || (havebase && base != ESP_REG_NUM))
11939 {
11940 if (!intel_syntax || havebase)
11941 {
11942 *obufp++ = separator_char;
11943 *obufp = '\0';
11944 }
11945 if (haveindex)
11946 oappend (address_mode == mode_64bit && !addr32flag
11947 ? indexes64[vindex] : indexes32[vindex]);
11948 else
11949 oappend (address_mode == mode_64bit && !addr32flag
11950 ? index64 : index32);
11951
11952 *obufp++ = scale_char;
11953 *obufp = '\0';
11954 sprintf (scratchbuf, "%d", 1 << scale);
11955 oappend (scratchbuf);
11956 }
11957 }
11958 if (intel_syntax
11959 && (disp || modrm.mod != 0 || base == 5))
11960 {
11961 if (!havedisp || (bfd_signed_vma) disp >= 0)
11962 {
11963 *obufp++ = '+';
11964 *obufp = '\0';
11965 }
11966 else if (modrm.mod != 1 && disp != -disp)
11967 {
11968 *obufp++ = '-';
11969 *obufp = '\0';
11970 disp = - (bfd_signed_vma) disp;
11971 }
11972
11973 if (havedisp)
11974 print_displacement (scratchbuf, disp);
11975 else
11976 print_operand_value (scratchbuf, 1, disp);
11977 oappend (scratchbuf);
11978 }
11979
11980 *obufp++ = close_char;
11981 *obufp = '\0';
11982 }
11983 else if (intel_syntax)
11984 {
11985 if (modrm.mod != 0 || base == 5)
11986 {
11987 if (!active_seg_prefix)
11988 {
11989 oappend (names_seg[ds_reg - es_reg]);
11990 oappend (":");
11991 }
11992 print_operand_value (scratchbuf, 1, disp);
11993 oappend (scratchbuf);
11994 }
11995 }
11996 }
11997 else if (bytemode == v_bnd_mode
11998 || bytemode == v_bndmk_mode
11999 || bytemode == bnd_mode
12000 || bytemode == bnd_swap_mode)
12001 {
12002 oappend ("(bad)");
12003 return;
12004 }
12005 else
12006 {
12007 /* 16 bit address mode */
12008 used_prefixes |= prefixes & PREFIX_ADDR;
12009 switch (modrm.mod)
12010 {
12011 case 0:
12012 if (modrm.rm == 6)
12013 {
12014 disp = get16 ();
12015 if ((disp & 0x8000) != 0)
12016 disp -= 0x10000;
12017 }
12018 break;
12019 case 1:
12020 FETCH_DATA (the_info, codep + 1);
12021 disp = *codep++;
12022 if ((disp & 0x80) != 0)
12023 disp -= 0x100;
12024 if (vex.evex && shift > 0)
12025 disp <<= shift;
12026 break;
12027 case 2:
12028 disp = get16 ();
12029 if ((disp & 0x8000) != 0)
12030 disp -= 0x10000;
12031 break;
12032 }
12033
12034 if (!intel_syntax)
12035 if (modrm.mod != 0 || modrm.rm == 6)
12036 {
12037 print_displacement (scratchbuf, disp);
12038 oappend (scratchbuf);
12039 }
12040
12041 if (modrm.mod != 0 || modrm.rm != 6)
12042 {
12043 *obufp++ = open_char;
12044 *obufp = '\0';
12045 oappend (index16[modrm.rm]);
12046 if (intel_syntax
12047 && (disp || modrm.mod != 0 || modrm.rm == 6))
12048 {
12049 if ((bfd_signed_vma) disp >= 0)
12050 {
12051 *obufp++ = '+';
12052 *obufp = '\0';
12053 }
12054 else if (modrm.mod != 1)
12055 {
12056 *obufp++ = '-';
12057 *obufp = '\0';
12058 disp = - (bfd_signed_vma) disp;
12059 }
12060
12061 print_displacement (scratchbuf, disp);
12062 oappend (scratchbuf);
12063 }
12064
12065 *obufp++ = close_char;
12066 *obufp = '\0';
12067 }
12068 else if (intel_syntax)
12069 {
12070 if (!active_seg_prefix)
12071 {
12072 oappend (names_seg[ds_reg - es_reg]);
12073 oappend (":");
12074 }
12075 print_operand_value (scratchbuf, 1, disp & 0xffff);
12076 oappend (scratchbuf);
12077 }
12078 }
12079 if (vex.evex && vex.b
12080 && (bytemode == x_mode
12081 || bytemode == xmmq_mode
12082 || bytemode == evex_half_bcst_xmmq_mode))
12083 {
12084 if (vex.w
12085 || bytemode == xmmq_mode
12086 || bytemode == evex_half_bcst_xmmq_mode)
12087 {
12088 switch (vex.length)
12089 {
12090 case 128:
12091 oappend ("{1to2}");
12092 break;
12093 case 256:
12094 oappend ("{1to4}");
12095 break;
12096 case 512:
12097 oappend ("{1to8}");
12098 break;
12099 default:
12100 abort ();
12101 }
12102 }
12103 else
12104 {
12105 switch (vex.length)
12106 {
12107 case 128:
12108 oappend ("{1to4}");
12109 break;
12110 case 256:
12111 oappend ("{1to8}");
12112 break;
12113 case 512:
12114 oappend ("{1to16}");
12115 break;
12116 default:
12117 abort ();
12118 }
12119 }
12120 }
12121 }
12122
12123 static void
12124 OP_E (int bytemode, int sizeflag)
12125 {
12126 /* Skip mod/rm byte. */
12127 MODRM_CHECK;
12128 codep++;
12129
12130 if (modrm.mod == 3)
12131 OP_E_register (bytemode, sizeflag);
12132 else
12133 OP_E_memory (bytemode, sizeflag);
12134 }
12135
12136 static void
12137 OP_G (int bytemode, int sizeflag)
12138 {
12139 int add = 0;
12140 const char **names;
12141 USED_REX (REX_R);
12142 if (rex & REX_R)
12143 add += 8;
12144 switch (bytemode)
12145 {
12146 case b_mode:
12147 if (modrm.reg & 4)
12148 USED_REX (0);
12149 if (rex)
12150 oappend (names8rex[modrm.reg + add]);
12151 else
12152 oappend (names8[modrm.reg + add]);
12153 break;
12154 case w_mode:
12155 oappend (names16[modrm.reg + add]);
12156 break;
12157 case d_mode:
12158 case db_mode:
12159 case dw_mode:
12160 oappend (names32[modrm.reg + add]);
12161 break;
12162 case q_mode:
12163 oappend (names64[modrm.reg + add]);
12164 break;
12165 case bnd_mode:
12166 if (modrm.reg > 0x3)
12167 {
12168 oappend ("(bad)");
12169 return;
12170 }
12171 oappend (names_bnd[modrm.reg]);
12172 break;
12173 case v_mode:
12174 case dq_mode:
12175 case dqb_mode:
12176 case dqd_mode:
12177 case dqw_mode:
12178 case movsxd_mode:
12179 USED_REX (REX_W);
12180 if (rex & REX_W)
12181 oappend (names64[modrm.reg + add]);
12182 else if (bytemode != v_mode && bytemode != movsxd_mode)
12183 oappend (names32[modrm.reg + add]);
12184 else
12185 {
12186 if (sizeflag & DFLAG)
12187 oappend (names32[modrm.reg + add]);
12188 else
12189 oappend (names16[modrm.reg + add]);
12190 used_prefixes |= (prefixes & PREFIX_DATA);
12191 }
12192 break;
12193 case va_mode:
12194 names = (address_mode == mode_64bit
12195 ? names64 : names32);
12196 if (!(prefixes & PREFIX_ADDR))
12197 {
12198 if (address_mode == mode_16bit)
12199 names = names16;
12200 }
12201 else
12202 {
12203 /* Remove "addr16/addr32". */
12204 all_prefixes[last_addr_prefix] = 0;
12205 names = (address_mode != mode_32bit
12206 ? names32 : names16);
12207 used_prefixes |= PREFIX_ADDR;
12208 }
12209 oappend (names[modrm.reg + add]);
12210 break;
12211 case m_mode:
12212 if (address_mode == mode_64bit)
12213 oappend (names64[modrm.reg + add]);
12214 else
12215 oappend (names32[modrm.reg + add]);
12216 break;
12217 case mask_bd_mode:
12218 case mask_mode:
12219 if ((modrm.reg + add) > 0x7)
12220 {
12221 oappend ("(bad)");
12222 return;
12223 }
12224 oappend (names_mask[modrm.reg + add]);
12225 break;
12226 default:
12227 oappend (INTERNAL_DISASSEMBLER_ERROR);
12228 break;
12229 }
12230 }
12231
12232 static bfd_vma
12233 get64 (void)
12234 {
12235 bfd_vma x;
12236 #ifdef BFD64
12237 unsigned int a;
12238 unsigned int b;
12239
12240 FETCH_DATA (the_info, codep + 8);
12241 a = *codep++ & 0xff;
12242 a |= (*codep++ & 0xff) << 8;
12243 a |= (*codep++ & 0xff) << 16;
12244 a |= (*codep++ & 0xffu) << 24;
12245 b = *codep++ & 0xff;
12246 b |= (*codep++ & 0xff) << 8;
12247 b |= (*codep++ & 0xff) << 16;
12248 b |= (*codep++ & 0xffu) << 24;
12249 x = a + ((bfd_vma) b << 32);
12250 #else
12251 abort ();
12252 x = 0;
12253 #endif
12254 return x;
12255 }
12256
12257 static bfd_signed_vma
12258 get32 (void)
12259 {
12260 bfd_signed_vma x = 0;
12261
12262 FETCH_DATA (the_info, codep + 4);
12263 x = *codep++ & (bfd_signed_vma) 0xff;
12264 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12265 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12266 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12267 return x;
12268 }
12269
12270 static bfd_signed_vma
12271 get32s (void)
12272 {
12273 bfd_signed_vma x = 0;
12274
12275 FETCH_DATA (the_info, codep + 4);
12276 x = *codep++ & (bfd_signed_vma) 0xff;
12277 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12278 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12279 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12280
12281 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12282
12283 return x;
12284 }
12285
12286 static int
12287 get16 (void)
12288 {
12289 int x = 0;
12290
12291 FETCH_DATA (the_info, codep + 2);
12292 x = *codep++ & 0xff;
12293 x |= (*codep++ & 0xff) << 8;
12294 return x;
12295 }
12296
12297 static void
12298 set_op (bfd_vma op, int riprel)
12299 {
12300 op_index[op_ad] = op_ad;
12301 if (address_mode == mode_64bit)
12302 {
12303 op_address[op_ad] = op;
12304 op_riprel[op_ad] = riprel;
12305 }
12306 else
12307 {
12308 /* Mask to get a 32-bit address. */
12309 op_address[op_ad] = op & 0xffffffff;
12310 op_riprel[op_ad] = riprel & 0xffffffff;
12311 }
12312 }
12313
12314 static void
12315 OP_REG (int code, int sizeflag)
12316 {
12317 const char *s;
12318 int add;
12319
12320 switch (code)
12321 {
12322 case es_reg: case ss_reg: case cs_reg:
12323 case ds_reg: case fs_reg: case gs_reg:
12324 oappend (names_seg[code - es_reg]);
12325 return;
12326 }
12327
12328 USED_REX (REX_B);
12329 if (rex & REX_B)
12330 add = 8;
12331 else
12332 add = 0;
12333
12334 switch (code)
12335 {
12336 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12337 case sp_reg: case bp_reg: case si_reg: case di_reg:
12338 s = names16[code - ax_reg + add];
12339 break;
12340 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12341 USED_REX (0);
12342 /* Fall through. */
12343 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12344 if (rex)
12345 s = names8rex[code - al_reg + add];
12346 else
12347 s = names8[code - al_reg];
12348 break;
12349 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12350 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12351 if (address_mode == mode_64bit
12352 && ((sizeflag & DFLAG) || (rex & REX_W)))
12353 {
12354 s = names64[code - rAX_reg + add];
12355 break;
12356 }
12357 code += eAX_reg - rAX_reg;
12358 /* Fall through. */
12359 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12360 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12361 USED_REX (REX_W);
12362 if (rex & REX_W)
12363 s = names64[code - eAX_reg + add];
12364 else
12365 {
12366 if (sizeflag & DFLAG)
12367 s = names32[code - eAX_reg + add];
12368 else
12369 s = names16[code - eAX_reg + add];
12370 used_prefixes |= (prefixes & PREFIX_DATA);
12371 }
12372 break;
12373 default:
12374 s = INTERNAL_DISASSEMBLER_ERROR;
12375 break;
12376 }
12377 oappend (s);
12378 }
12379
12380 static void
12381 OP_IMREG (int code, int sizeflag)
12382 {
12383 const char *s;
12384
12385 switch (code)
12386 {
12387 case indir_dx_reg:
12388 if (intel_syntax)
12389 s = "dx";
12390 else
12391 s = "(%dx)";
12392 break;
12393 case al_reg: case cl_reg:
12394 s = names8[code - al_reg];
12395 break;
12396 case eAX_reg:
12397 USED_REX (REX_W);
12398 if (rex & REX_W)
12399 {
12400 s = *names64;
12401 break;
12402 }
12403 /* Fall through. */
12404 case z_mode_ax_reg:
12405 if ((rex & REX_W) || (sizeflag & DFLAG))
12406 s = *names32;
12407 else
12408 s = *names16;
12409 if (!(rex & REX_W))
12410 used_prefixes |= (prefixes & PREFIX_DATA);
12411 break;
12412 default:
12413 s = INTERNAL_DISASSEMBLER_ERROR;
12414 break;
12415 }
12416 oappend (s);
12417 }
12418
12419 static void
12420 OP_I (int bytemode, int sizeflag)
12421 {
12422 bfd_signed_vma op;
12423 bfd_signed_vma mask = -1;
12424
12425 switch (bytemode)
12426 {
12427 case b_mode:
12428 FETCH_DATA (the_info, codep + 1);
12429 op = *codep++;
12430 mask = 0xff;
12431 break;
12432 case v_mode:
12433 USED_REX (REX_W);
12434 if (rex & REX_W)
12435 op = get32s ();
12436 else
12437 {
12438 if (sizeflag & DFLAG)
12439 {
12440 op = get32 ();
12441 mask = 0xffffffff;
12442 }
12443 else
12444 {
12445 op = get16 ();
12446 mask = 0xfffff;
12447 }
12448 used_prefixes |= (prefixes & PREFIX_DATA);
12449 }
12450 break;
12451 case d_mode:
12452 mask = 0xffffffff;
12453 op = get32 ();
12454 break;
12455 case w_mode:
12456 mask = 0xfffff;
12457 op = get16 ();
12458 break;
12459 case const_1_mode:
12460 if (intel_syntax)
12461 oappend ("1");
12462 return;
12463 default:
12464 oappend (INTERNAL_DISASSEMBLER_ERROR);
12465 return;
12466 }
12467
12468 op &= mask;
12469 scratchbuf[0] = '$';
12470 print_operand_value (scratchbuf + 1, 1, op);
12471 oappend_maybe_intel (scratchbuf);
12472 scratchbuf[0] = '\0';
12473 }
12474
12475 static void
12476 OP_I64 (int bytemode, int sizeflag)
12477 {
12478 if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12479 {
12480 OP_I (bytemode, sizeflag);
12481 return;
12482 }
12483
12484 USED_REX (REX_W);
12485
12486 scratchbuf[0] = '$';
12487 print_operand_value (scratchbuf + 1, 1, get64 ());
12488 oappend_maybe_intel (scratchbuf);
12489 scratchbuf[0] = '\0';
12490 }
12491
12492 static void
12493 OP_sI (int bytemode, int sizeflag)
12494 {
12495 bfd_signed_vma op;
12496
12497 switch (bytemode)
12498 {
12499 case b_mode:
12500 case b_T_mode:
12501 FETCH_DATA (the_info, codep + 1);
12502 op = *codep++;
12503 if ((op & 0x80) != 0)
12504 op -= 0x100;
12505 if (bytemode == b_T_mode)
12506 {
12507 if (address_mode != mode_64bit
12508 || !((sizeflag & DFLAG) || (rex & REX_W)))
12509 {
12510 /* The operand-size prefix is overridden by a REX prefix. */
12511 if ((sizeflag & DFLAG) || (rex & REX_W))
12512 op &= 0xffffffff;
12513 else
12514 op &= 0xffff;
12515 }
12516 }
12517 else
12518 {
12519 if (!(rex & REX_W))
12520 {
12521 if (sizeflag & DFLAG)
12522 op &= 0xffffffff;
12523 else
12524 op &= 0xffff;
12525 }
12526 }
12527 break;
12528 case v_mode:
12529 /* The operand-size prefix is overridden by a REX prefix. */
12530 if ((sizeflag & DFLAG) || (rex & REX_W))
12531 op = get32s ();
12532 else
12533 op = get16 ();
12534 break;
12535 default:
12536 oappend (INTERNAL_DISASSEMBLER_ERROR);
12537 return;
12538 }
12539
12540 scratchbuf[0] = '$';
12541 print_operand_value (scratchbuf + 1, 1, op);
12542 oappend_maybe_intel (scratchbuf);
12543 }
12544
12545 static void
12546 OP_J (int bytemode, int sizeflag)
12547 {
12548 bfd_vma disp;
12549 bfd_vma mask = -1;
12550 bfd_vma segment = 0;
12551
12552 switch (bytemode)
12553 {
12554 case b_mode:
12555 FETCH_DATA (the_info, codep + 1);
12556 disp = *codep++;
12557 if ((disp & 0x80) != 0)
12558 disp -= 0x100;
12559 break;
12560 case v_mode:
12561 if (isa64 != intel64)
12562 case dqw_mode:
12563 USED_REX (REX_W);
12564 if ((sizeflag & DFLAG)
12565 || (address_mode == mode_64bit
12566 && ((isa64 == intel64 && bytemode != dqw_mode)
12567 || (rex & REX_W))))
12568 disp = get32s ();
12569 else
12570 {
12571 disp = get16 ();
12572 if ((disp & 0x8000) != 0)
12573 disp -= 0x10000;
12574 /* In 16bit mode, address is wrapped around at 64k within
12575 the same segment. Otherwise, a data16 prefix on a jump
12576 instruction means that the pc is masked to 16 bits after
12577 the displacement is added! */
12578 mask = 0xffff;
12579 if ((prefixes & PREFIX_DATA) == 0)
12580 segment = ((start_pc + (codep - start_codep))
12581 & ~((bfd_vma) 0xffff));
12582 }
12583 if (address_mode != mode_64bit
12584 || (isa64 != intel64 && !(rex & REX_W)))
12585 used_prefixes |= (prefixes & PREFIX_DATA);
12586 break;
12587 default:
12588 oappend (INTERNAL_DISASSEMBLER_ERROR);
12589 return;
12590 }
12591 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12592 set_op (disp, 0);
12593 print_operand_value (scratchbuf, 1, disp);
12594 oappend (scratchbuf);
12595 }
12596
12597 static void
12598 OP_SEG (int bytemode, int sizeflag)
12599 {
12600 if (bytemode == w_mode)
12601 oappend (names_seg[modrm.reg]);
12602 else
12603 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12604 }
12605
12606 static void
12607 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12608 {
12609 int seg, offset;
12610
12611 if (sizeflag & DFLAG)
12612 {
12613 offset = get32 ();
12614 seg = get16 ();
12615 }
12616 else
12617 {
12618 offset = get16 ();
12619 seg = get16 ();
12620 }
12621 used_prefixes |= (prefixes & PREFIX_DATA);
12622 if (intel_syntax)
12623 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12624 else
12625 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12626 oappend (scratchbuf);
12627 }
12628
12629 static void
12630 OP_OFF (int bytemode, int sizeflag)
12631 {
12632 bfd_vma off;
12633
12634 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12635 intel_operand_size (bytemode, sizeflag);
12636 append_seg ();
12637
12638 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12639 off = get32 ();
12640 else
12641 off = get16 ();
12642
12643 if (intel_syntax)
12644 {
12645 if (!active_seg_prefix)
12646 {
12647 oappend (names_seg[ds_reg - es_reg]);
12648 oappend (":");
12649 }
12650 }
12651 print_operand_value (scratchbuf, 1, off);
12652 oappend (scratchbuf);
12653 }
12654
12655 static void
12656 OP_OFF64 (int bytemode, int sizeflag)
12657 {
12658 bfd_vma off;
12659
12660 if (address_mode != mode_64bit
12661 || (prefixes & PREFIX_ADDR))
12662 {
12663 OP_OFF (bytemode, sizeflag);
12664 return;
12665 }
12666
12667 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12668 intel_operand_size (bytemode, sizeflag);
12669 append_seg ();
12670
12671 off = get64 ();
12672
12673 if (intel_syntax)
12674 {
12675 if (!active_seg_prefix)
12676 {
12677 oappend (names_seg[ds_reg - es_reg]);
12678 oappend (":");
12679 }
12680 }
12681 print_operand_value (scratchbuf, 1, off);
12682 oappend (scratchbuf);
12683 }
12684
12685 static void
12686 ptr_reg (int code, int sizeflag)
12687 {
12688 const char *s;
12689
12690 *obufp++ = open_char;
12691 used_prefixes |= (prefixes & PREFIX_ADDR);
12692 if (address_mode == mode_64bit)
12693 {
12694 if (!(sizeflag & AFLAG))
12695 s = names32[code - eAX_reg];
12696 else
12697 s = names64[code - eAX_reg];
12698 }
12699 else if (sizeflag & AFLAG)
12700 s = names32[code - eAX_reg];
12701 else
12702 s = names16[code - eAX_reg];
12703 oappend (s);
12704 *obufp++ = close_char;
12705 *obufp = 0;
12706 }
12707
12708 static void
12709 OP_ESreg (int code, int sizeflag)
12710 {
12711 if (intel_syntax)
12712 {
12713 switch (codep[-1])
12714 {
12715 case 0x6d: /* insw/insl */
12716 intel_operand_size (z_mode, sizeflag);
12717 break;
12718 case 0xa5: /* movsw/movsl/movsq */
12719 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12720 case 0xab: /* stosw/stosl */
12721 case 0xaf: /* scasw/scasl */
12722 intel_operand_size (v_mode, sizeflag);
12723 break;
12724 default:
12725 intel_operand_size (b_mode, sizeflag);
12726 }
12727 }
12728 oappend_maybe_intel ("%es:");
12729 ptr_reg (code, sizeflag);
12730 }
12731
12732 static void
12733 OP_DSreg (int code, int sizeflag)
12734 {
12735 if (intel_syntax)
12736 {
12737 switch (codep[-1])
12738 {
12739 case 0x6f: /* outsw/outsl */
12740 intel_operand_size (z_mode, sizeflag);
12741 break;
12742 case 0xa5: /* movsw/movsl/movsq */
12743 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12744 case 0xad: /* lodsw/lodsl/lodsq */
12745 intel_operand_size (v_mode, sizeflag);
12746 break;
12747 default:
12748 intel_operand_size (b_mode, sizeflag);
12749 }
12750 }
12751 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12752 default segment register DS is printed. */
12753 if (!active_seg_prefix)
12754 active_seg_prefix = PREFIX_DS;
12755 append_seg ();
12756 ptr_reg (code, sizeflag);
12757 }
12758
12759 static void
12760 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12761 {
12762 int add;
12763 if (rex & REX_R)
12764 {
12765 USED_REX (REX_R);
12766 add = 8;
12767 }
12768 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12769 {
12770 all_prefixes[last_lock_prefix] = 0;
12771 used_prefixes |= PREFIX_LOCK;
12772 add = 8;
12773 }
12774 else
12775 add = 0;
12776 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12777 oappend_maybe_intel (scratchbuf);
12778 }
12779
12780 static void
12781 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12782 {
12783 int add;
12784 USED_REX (REX_R);
12785 if (rex & REX_R)
12786 add = 8;
12787 else
12788 add = 0;
12789 if (intel_syntax)
12790 sprintf (scratchbuf, "dr%d", modrm.reg + add);
12791 else
12792 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12793 oappend (scratchbuf);
12794 }
12795
12796 static void
12797 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12798 {
12799 sprintf (scratchbuf, "%%tr%d", modrm.reg);
12800 oappend_maybe_intel (scratchbuf);
12801 }
12802
12803 static void
12804 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12805 {
12806 int reg = modrm.reg;
12807 const char **names;
12808
12809 used_prefixes |= (prefixes & PREFIX_DATA);
12810 if (prefixes & PREFIX_DATA)
12811 {
12812 names = names_xmm;
12813 USED_REX (REX_R);
12814 if (rex & REX_R)
12815 reg += 8;
12816 }
12817 else
12818 names = names_mm;
12819 oappend (names[reg]);
12820 }
12821
12822 static void
12823 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12824 {
12825 int reg = modrm.reg;
12826 const char **names;
12827
12828 USED_REX (REX_R);
12829 if (rex & REX_R)
12830 reg += 8;
12831 if (vex.evex)
12832 {
12833 if (!vex.r)
12834 reg += 16;
12835 }
12836
12837 if (need_vex
12838 && bytemode != xmm_mode
12839 && bytemode != xmmq_mode
12840 && bytemode != evex_half_bcst_xmmq_mode
12841 && bytemode != ymm_mode
12842 && bytemode != tmm_mode
12843 && bytemode != scalar_mode)
12844 {
12845 switch (vex.length)
12846 {
12847 case 128:
12848 names = names_xmm;
12849 break;
12850 case 256:
12851 if (vex.w
12852 || (bytemode != vex_vsib_q_w_dq_mode
12853 && bytemode != vex_vsib_q_w_d_mode))
12854 names = names_ymm;
12855 else
12856 names = names_xmm;
12857 break;
12858 case 512:
12859 names = names_zmm;
12860 break;
12861 default:
12862 abort ();
12863 }
12864 }
12865 else if (bytemode == xmmq_mode
12866 || bytemode == evex_half_bcst_xmmq_mode)
12867 {
12868 switch (vex.length)
12869 {
12870 case 128:
12871 case 256:
12872 names = names_xmm;
12873 break;
12874 case 512:
12875 names = names_ymm;
12876 break;
12877 default:
12878 abort ();
12879 }
12880 }
12881 else if (bytemode == tmm_mode)
12882 {
12883 modrm.reg = reg;
12884 if (reg >= 8)
12885 {
12886 oappend ("(bad)");
12887 return;
12888 }
12889 names = names_tmm;
12890 }
12891 else if (bytemode == ymm_mode)
12892 names = names_ymm;
12893 else
12894 names = names_xmm;
12895 oappend (names[reg]);
12896 }
12897
12898 static void
12899 OP_EM (int bytemode, int sizeflag)
12900 {
12901 int reg;
12902 const char **names;
12903
12904 if (modrm.mod != 3)
12905 {
12906 if (intel_syntax
12907 && (bytemode == v_mode || bytemode == v_swap_mode))
12908 {
12909 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12910 used_prefixes |= (prefixes & PREFIX_DATA);
12911 }
12912 OP_E (bytemode, sizeflag);
12913 return;
12914 }
12915
12916 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12917 swap_operand ();
12918
12919 /* Skip mod/rm byte. */
12920 MODRM_CHECK;
12921 codep++;
12922 used_prefixes |= (prefixes & PREFIX_DATA);
12923 reg = modrm.rm;
12924 if (prefixes & PREFIX_DATA)
12925 {
12926 names = names_xmm;
12927 USED_REX (REX_B);
12928 if (rex & REX_B)
12929 reg += 8;
12930 }
12931 else
12932 names = names_mm;
12933 oappend (names[reg]);
12934 }
12935
12936 /* cvt* are the only instructions in sse2 which have
12937 both SSE and MMX operands and also have 0x66 prefix
12938 in their opcode. 0x66 was originally used to differentiate
12939 between SSE and MMX instruction(operands). So we have to handle the
12940 cvt* separately using OP_EMC and OP_MXC */
12941 static void
12942 OP_EMC (int bytemode, int sizeflag)
12943 {
12944 if (modrm.mod != 3)
12945 {
12946 if (intel_syntax && bytemode == v_mode)
12947 {
12948 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12949 used_prefixes |= (prefixes & PREFIX_DATA);
12950 }
12951 OP_E (bytemode, sizeflag);
12952 return;
12953 }
12954
12955 /* Skip mod/rm byte. */
12956 MODRM_CHECK;
12957 codep++;
12958 used_prefixes |= (prefixes & PREFIX_DATA);
12959 oappend (names_mm[modrm.rm]);
12960 }
12961
12962 static void
12963 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12964 {
12965 used_prefixes |= (prefixes & PREFIX_DATA);
12966 oappend (names_mm[modrm.reg]);
12967 }
12968
12969 static void
12970 OP_EX (int bytemode, int sizeflag)
12971 {
12972 int reg;
12973 const char **names;
12974
12975 /* Skip mod/rm byte. */
12976 MODRM_CHECK;
12977 codep++;
12978
12979 if (modrm.mod != 3)
12980 {
12981 OP_E_memory (bytemode, sizeflag);
12982 return;
12983 }
12984
12985 reg = modrm.rm;
12986 USED_REX (REX_B);
12987 if (rex & REX_B)
12988 reg += 8;
12989 if (vex.evex)
12990 {
12991 USED_REX (REX_X);
12992 if ((rex & REX_X))
12993 reg += 16;
12994 }
12995
12996 if ((sizeflag & SUFFIX_ALWAYS)
12997 && (bytemode == x_swap_mode
12998 || bytemode == d_swap_mode
12999 || bytemode == q_swap_mode))
13000 swap_operand ();
13001
13002 if (need_vex
13003 && bytemode != xmm_mode
13004 && bytemode != xmmdw_mode
13005 && bytemode != xmmqd_mode
13006 && bytemode != xmm_mb_mode
13007 && bytemode != xmm_mw_mode
13008 && bytemode != xmm_md_mode
13009 && bytemode != xmm_mq_mode
13010 && bytemode != xmmq_mode
13011 && bytemode != evex_half_bcst_xmmq_mode
13012 && bytemode != ymm_mode
13013 && bytemode != tmm_mode
13014 && bytemode != vex_scalar_w_dq_mode)
13015 {
13016 switch (vex.length)
13017 {
13018 case 128:
13019 names = names_xmm;
13020 break;
13021 case 256:
13022 names = names_ymm;
13023 break;
13024 case 512:
13025 names = names_zmm;
13026 break;
13027 default:
13028 abort ();
13029 }
13030 }
13031 else if (bytemode == xmmq_mode
13032 || bytemode == evex_half_bcst_xmmq_mode)
13033 {
13034 switch (vex.length)
13035 {
13036 case 128:
13037 case 256:
13038 names = names_xmm;
13039 break;
13040 case 512:
13041 names = names_ymm;
13042 break;
13043 default:
13044 abort ();
13045 }
13046 }
13047 else if (bytemode == tmm_mode)
13048 {
13049 modrm.rm = reg;
13050 if (reg >= 8)
13051 {
13052 oappend ("(bad)");
13053 return;
13054 }
13055 names = names_tmm;
13056 }
13057 else if (bytemode == ymm_mode)
13058 names = names_ymm;
13059 else
13060 names = names_xmm;
13061 oappend (names[reg]);
13062 }
13063
13064 static void
13065 OP_MS (int bytemode, int sizeflag)
13066 {
13067 if (modrm.mod == 3)
13068 OP_EM (bytemode, sizeflag);
13069 else
13070 BadOp ();
13071 }
13072
13073 static void
13074 OP_XS (int bytemode, int sizeflag)
13075 {
13076 if (modrm.mod == 3)
13077 OP_EX (bytemode, sizeflag);
13078 else
13079 BadOp ();
13080 }
13081
13082 static void
13083 OP_M (int bytemode, int sizeflag)
13084 {
13085 if (modrm.mod == 3)
13086 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13087 BadOp ();
13088 else
13089 OP_E (bytemode, sizeflag);
13090 }
13091
13092 static void
13093 OP_0f07 (int bytemode, int sizeflag)
13094 {
13095 if (modrm.mod != 3 || modrm.rm != 0)
13096 BadOp ();
13097 else
13098 OP_E (bytemode, sizeflag);
13099 }
13100
13101 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13102 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13103
13104 static void
13105 NOP_Fixup1 (int bytemode, int sizeflag)
13106 {
13107 if ((prefixes & PREFIX_DATA) != 0
13108 || (rex != 0
13109 && rex != 0x48
13110 && address_mode == mode_64bit))
13111 OP_REG (bytemode, sizeflag);
13112 else
13113 strcpy (obuf, "nop");
13114 }
13115
13116 static void
13117 NOP_Fixup2 (int bytemode, int sizeflag)
13118 {
13119 if ((prefixes & PREFIX_DATA) != 0
13120 || (rex != 0
13121 && rex != 0x48
13122 && address_mode == mode_64bit))
13123 OP_IMREG (bytemode, sizeflag);
13124 }
13125
13126 static const char *const Suffix3DNow[] = {
13127 /* 00 */ NULL, NULL, NULL, NULL,
13128 /* 04 */ NULL, NULL, NULL, NULL,
13129 /* 08 */ NULL, NULL, NULL, NULL,
13130 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13131 /* 10 */ NULL, NULL, NULL, NULL,
13132 /* 14 */ NULL, NULL, NULL, NULL,
13133 /* 18 */ NULL, NULL, NULL, NULL,
13134 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13135 /* 20 */ NULL, NULL, NULL, NULL,
13136 /* 24 */ NULL, NULL, NULL, NULL,
13137 /* 28 */ NULL, NULL, NULL, NULL,
13138 /* 2C */ NULL, NULL, NULL, NULL,
13139 /* 30 */ NULL, NULL, NULL, NULL,
13140 /* 34 */ NULL, NULL, NULL, NULL,
13141 /* 38 */ NULL, NULL, NULL, NULL,
13142 /* 3C */ NULL, NULL, NULL, NULL,
13143 /* 40 */ NULL, NULL, NULL, NULL,
13144 /* 44 */ NULL, NULL, NULL, NULL,
13145 /* 48 */ NULL, NULL, NULL, NULL,
13146 /* 4C */ NULL, NULL, NULL, NULL,
13147 /* 50 */ NULL, NULL, NULL, NULL,
13148 /* 54 */ NULL, NULL, NULL, NULL,
13149 /* 58 */ NULL, NULL, NULL, NULL,
13150 /* 5C */ NULL, NULL, NULL, NULL,
13151 /* 60 */ NULL, NULL, NULL, NULL,
13152 /* 64 */ NULL, NULL, NULL, NULL,
13153 /* 68 */ NULL, NULL, NULL, NULL,
13154 /* 6C */ NULL, NULL, NULL, NULL,
13155 /* 70 */ NULL, NULL, NULL, NULL,
13156 /* 74 */ NULL, NULL, NULL, NULL,
13157 /* 78 */ NULL, NULL, NULL, NULL,
13158 /* 7C */ NULL, NULL, NULL, NULL,
13159 /* 80 */ NULL, NULL, NULL, NULL,
13160 /* 84 */ NULL, NULL, NULL, NULL,
13161 /* 88 */ NULL, NULL, "pfnacc", NULL,
13162 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13163 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13164 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13165 /* 98 */ NULL, NULL, "pfsub", NULL,
13166 /* 9C */ NULL, NULL, "pfadd", NULL,
13167 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13168 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13169 /* A8 */ NULL, NULL, "pfsubr", NULL,
13170 /* AC */ NULL, NULL, "pfacc", NULL,
13171 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13172 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13173 /* B8 */ NULL, NULL, NULL, "pswapd",
13174 /* BC */ NULL, NULL, NULL, "pavgusb",
13175 /* C0 */ NULL, NULL, NULL, NULL,
13176 /* C4 */ NULL, NULL, NULL, NULL,
13177 /* C8 */ NULL, NULL, NULL, NULL,
13178 /* CC */ NULL, NULL, NULL, NULL,
13179 /* D0 */ NULL, NULL, NULL, NULL,
13180 /* D4 */ NULL, NULL, NULL, NULL,
13181 /* D8 */ NULL, NULL, NULL, NULL,
13182 /* DC */ NULL, NULL, NULL, NULL,
13183 /* E0 */ NULL, NULL, NULL, NULL,
13184 /* E4 */ NULL, NULL, NULL, NULL,
13185 /* E8 */ NULL, NULL, NULL, NULL,
13186 /* EC */ NULL, NULL, NULL, NULL,
13187 /* F0 */ NULL, NULL, NULL, NULL,
13188 /* F4 */ NULL, NULL, NULL, NULL,
13189 /* F8 */ NULL, NULL, NULL, NULL,
13190 /* FC */ NULL, NULL, NULL, NULL,
13191 };
13192
13193 static void
13194 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13195 {
13196 const char *mnemonic;
13197
13198 FETCH_DATA (the_info, codep + 1);
13199 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13200 place where an 8-bit immediate would normally go. ie. the last
13201 byte of the instruction. */
13202 obufp = mnemonicendp;
13203 mnemonic = Suffix3DNow[*codep++ & 0xff];
13204 if (mnemonic)
13205 oappend (mnemonic);
13206 else
13207 {
13208 /* Since a variable sized modrm/sib chunk is between the start
13209 of the opcode (0x0f0f) and the opcode suffix, we need to do
13210 all the modrm processing first, and don't know until now that
13211 we have a bad opcode. This necessitates some cleaning up. */
13212 op_out[0][0] = '\0';
13213 op_out[1][0] = '\0';
13214 BadOp ();
13215 }
13216 mnemonicendp = obufp;
13217 }
13218
13219 static const struct op simd_cmp_op[] =
13220 {
13221 { STRING_COMMA_LEN ("eq") },
13222 { STRING_COMMA_LEN ("lt") },
13223 { STRING_COMMA_LEN ("le") },
13224 { STRING_COMMA_LEN ("unord") },
13225 { STRING_COMMA_LEN ("neq") },
13226 { STRING_COMMA_LEN ("nlt") },
13227 { STRING_COMMA_LEN ("nle") },
13228 { STRING_COMMA_LEN ("ord") }
13229 };
13230
13231 static const struct op vex_cmp_op[] =
13232 {
13233 { STRING_COMMA_LEN ("eq_uq") },
13234 { STRING_COMMA_LEN ("nge") },
13235 { STRING_COMMA_LEN ("ngt") },
13236 { STRING_COMMA_LEN ("false") },
13237 { STRING_COMMA_LEN ("neq_oq") },
13238 { STRING_COMMA_LEN ("ge") },
13239 { STRING_COMMA_LEN ("gt") },
13240 { STRING_COMMA_LEN ("true") },
13241 { STRING_COMMA_LEN ("eq_os") },
13242 { STRING_COMMA_LEN ("lt_oq") },
13243 { STRING_COMMA_LEN ("le_oq") },
13244 { STRING_COMMA_LEN ("unord_s") },
13245 { STRING_COMMA_LEN ("neq_us") },
13246 { STRING_COMMA_LEN ("nlt_uq") },
13247 { STRING_COMMA_LEN ("nle_uq") },
13248 { STRING_COMMA_LEN ("ord_s") },
13249 { STRING_COMMA_LEN ("eq_us") },
13250 { STRING_COMMA_LEN ("nge_uq") },
13251 { STRING_COMMA_LEN ("ngt_uq") },
13252 { STRING_COMMA_LEN ("false_os") },
13253 { STRING_COMMA_LEN ("neq_os") },
13254 { STRING_COMMA_LEN ("ge_oq") },
13255 { STRING_COMMA_LEN ("gt_oq") },
13256 { STRING_COMMA_LEN ("true_us") },
13257 };
13258
13259 static void
13260 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13261 {
13262 unsigned int cmp_type;
13263
13264 FETCH_DATA (the_info, codep + 1);
13265 cmp_type = *codep++ & 0xff;
13266 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13267 {
13268 char suffix [3];
13269 char *p = mnemonicendp - 2;
13270 suffix[0] = p[0];
13271 suffix[1] = p[1];
13272 suffix[2] = '\0';
13273 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13274 mnemonicendp += simd_cmp_op[cmp_type].len;
13275 }
13276 else if (need_vex
13277 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13278 {
13279 char suffix [3];
13280 char *p = mnemonicendp - 2;
13281 suffix[0] = p[0];
13282 suffix[1] = p[1];
13283 suffix[2] = '\0';
13284 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13285 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13286 mnemonicendp += vex_cmp_op[cmp_type].len;
13287 }
13288 else
13289 {
13290 /* We have a reserved extension byte. Output it directly. */
13291 scratchbuf[0] = '$';
13292 print_operand_value (scratchbuf + 1, 1, cmp_type);
13293 oappend_maybe_intel (scratchbuf);
13294 scratchbuf[0] = '\0';
13295 }
13296 }
13297
13298 static void
13299 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13300 {
13301 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13302 if (!intel_syntax)
13303 {
13304 strcpy (op_out[0], names32[0]);
13305 strcpy (op_out[1], names32[1]);
13306 if (bytemode == eBX_reg)
13307 strcpy (op_out[2], names32[3]);
13308 two_source_ops = 1;
13309 }
13310 /* Skip mod/rm byte. */
13311 MODRM_CHECK;
13312 codep++;
13313 }
13314
13315 static void
13316 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13317 int sizeflag ATTRIBUTE_UNUSED)
13318 {
13319 /* monitor %{e,r,}ax,%ecx,%edx" */
13320 if (!intel_syntax)
13321 {
13322 const char **names = (address_mode == mode_64bit
13323 ? names64 : names32);
13324
13325 if (prefixes & PREFIX_ADDR)
13326 {
13327 /* Remove "addr16/addr32". */
13328 all_prefixes[last_addr_prefix] = 0;
13329 names = (address_mode != mode_32bit
13330 ? names32 : names16);
13331 used_prefixes |= PREFIX_ADDR;
13332 }
13333 else if (address_mode == mode_16bit)
13334 names = names16;
13335 strcpy (op_out[0], names[0]);
13336 strcpy (op_out[1], names32[1]);
13337 strcpy (op_out[2], names32[2]);
13338 two_source_ops = 1;
13339 }
13340 /* Skip mod/rm byte. */
13341 MODRM_CHECK;
13342 codep++;
13343 }
13344
13345 static void
13346 BadOp (void)
13347 {
13348 /* Throw away prefixes and 1st. opcode byte. */
13349 codep = insn_codep + 1;
13350 oappend ("(bad)");
13351 }
13352
13353 static void
13354 REP_Fixup (int bytemode, int sizeflag)
13355 {
13356 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13357 lods and stos. */
13358 if (prefixes & PREFIX_REPZ)
13359 all_prefixes[last_repz_prefix] = REP_PREFIX;
13360
13361 switch (bytemode)
13362 {
13363 case al_reg:
13364 case eAX_reg:
13365 case indir_dx_reg:
13366 OP_IMREG (bytemode, sizeflag);
13367 break;
13368 case eDI_reg:
13369 OP_ESreg (bytemode, sizeflag);
13370 break;
13371 case eSI_reg:
13372 OP_DSreg (bytemode, sizeflag);
13373 break;
13374 default:
13375 abort ();
13376 break;
13377 }
13378 }
13379
13380 static void
13381 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13382 {
13383 if ( isa64 != amd64 )
13384 return;
13385
13386 obufp = obuf;
13387 BadOp ();
13388 mnemonicendp = obufp;
13389 ++codep;
13390 }
13391
13392 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13393 "bnd". */
13394
13395 static void
13396 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13397 {
13398 if (prefixes & PREFIX_REPNZ)
13399 all_prefixes[last_repnz_prefix] = BND_PREFIX;
13400 }
13401
13402 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13403 "notrack". */
13404
13405 static void
13406 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13407 int sizeflag ATTRIBUTE_UNUSED)
13408 {
13409 if (active_seg_prefix == PREFIX_DS
13410 && (address_mode != mode_64bit || last_data_prefix < 0))
13411 {
13412 /* NOTRACK prefix is only valid on indirect branch instructions.
13413 NB: DATA prefix is unsupported for Intel64. */
13414 active_seg_prefix = 0;
13415 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13416 }
13417 }
13418
13419 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13420 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13421 */
13422
13423 static void
13424 HLE_Fixup1 (int bytemode, int sizeflag)
13425 {
13426 if (modrm.mod != 3
13427 && (prefixes & PREFIX_LOCK) != 0)
13428 {
13429 if (prefixes & PREFIX_REPZ)
13430 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13431 if (prefixes & PREFIX_REPNZ)
13432 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13433 }
13434
13435 OP_E (bytemode, sizeflag);
13436 }
13437
13438 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13439 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13440 */
13441
13442 static void
13443 HLE_Fixup2 (int bytemode, int sizeflag)
13444 {
13445 if (modrm.mod != 3)
13446 {
13447 if (prefixes & PREFIX_REPZ)
13448 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13449 if (prefixes & PREFIX_REPNZ)
13450 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13451 }
13452
13453 OP_E (bytemode, sizeflag);
13454 }
13455
13456 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13457 "xrelease" for memory operand. No check for LOCK prefix. */
13458
13459 static void
13460 HLE_Fixup3 (int bytemode, int sizeflag)
13461 {
13462 if (modrm.mod != 3
13463 && last_repz_prefix > last_repnz_prefix
13464 && (prefixes & PREFIX_REPZ) != 0)
13465 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13466
13467 OP_E (bytemode, sizeflag);
13468 }
13469
13470 static void
13471 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13472 {
13473 USED_REX (REX_W);
13474 if (rex & REX_W)
13475 {
13476 /* Change cmpxchg8b to cmpxchg16b. */
13477 char *p = mnemonicendp - 2;
13478 mnemonicendp = stpcpy (p, "16b");
13479 bytemode = o_mode;
13480 }
13481 else if ((prefixes & PREFIX_LOCK) != 0)
13482 {
13483 if (prefixes & PREFIX_REPZ)
13484 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13485 if (prefixes & PREFIX_REPNZ)
13486 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13487 }
13488
13489 OP_M (bytemode, sizeflag);
13490 }
13491
13492 static void
13493 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13494 {
13495 const char **names;
13496
13497 if (need_vex)
13498 {
13499 switch (vex.length)
13500 {
13501 case 128:
13502 names = names_xmm;
13503 break;
13504 case 256:
13505 names = names_ymm;
13506 break;
13507 default:
13508 abort ();
13509 }
13510 }
13511 else
13512 names = names_xmm;
13513 oappend (names[reg]);
13514 }
13515
13516 static void
13517 FXSAVE_Fixup (int bytemode, int sizeflag)
13518 {
13519 /* Add proper suffix to "fxsave" and "fxrstor". */
13520 USED_REX (REX_W);
13521 if (rex & REX_W)
13522 {
13523 char *p = mnemonicendp;
13524 *p++ = '6';
13525 *p++ = '4';
13526 *p = '\0';
13527 mnemonicendp = p;
13528 }
13529 OP_M (bytemode, sizeflag);
13530 }
13531
13532 /* Display the destination register operand for instructions with
13533 VEX. */
13534
13535 static void
13536 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13537 {
13538 int reg;
13539 const char **names;
13540
13541 if (!need_vex)
13542 abort ();
13543
13544 reg = vex.register_specifier;
13545 vex.register_specifier = 0;
13546 if (address_mode != mode_64bit)
13547 reg &= 7;
13548 else if (vex.evex && !vex.v)
13549 reg += 16;
13550
13551 if (bytemode == vex_scalar_mode)
13552 {
13553 oappend (names_xmm[reg]);
13554 return;
13555 }
13556
13557 if (bytemode == tmm_mode)
13558 {
13559 /* All 3 TMM registers must be distinct. */
13560 if (reg >= 8)
13561 oappend ("(bad)");
13562 else
13563 {
13564 /* This must be the 3rd operand. */
13565 if (obufp != op_out[2])
13566 abort ();
13567 oappend (names_tmm[reg]);
13568 if (reg == modrm.reg || reg == modrm.rm)
13569 strcpy (obufp, "/(bad)");
13570 }
13571
13572 if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13573 {
13574 if (modrm.reg <= 8
13575 && (modrm.reg == modrm.rm || modrm.reg == reg))
13576 strcat (op_out[0], "/(bad)");
13577 if (modrm.rm <= 8
13578 && (modrm.rm == modrm.reg || modrm.rm == reg))
13579 strcat (op_out[1], "/(bad)");
13580 }
13581
13582 return;
13583 }
13584
13585 switch (vex.length)
13586 {
13587 case 128:
13588 switch (bytemode)
13589 {
13590 case vex_mode:
13591 case vex_vsib_q_w_dq_mode:
13592 case vex_vsib_q_w_d_mode:
13593 names = names_xmm;
13594 break;
13595 case dq_mode:
13596 if (rex & REX_W)
13597 names = names64;
13598 else
13599 names = names32;
13600 break;
13601 case mask_bd_mode:
13602 case mask_mode:
13603 if (reg > 0x7)
13604 {
13605 oappend ("(bad)");
13606 return;
13607 }
13608 names = names_mask;
13609 break;
13610 default:
13611 abort ();
13612 return;
13613 }
13614 break;
13615 case 256:
13616 switch (bytemode)
13617 {
13618 case vex_mode:
13619 names = names_ymm;
13620 break;
13621 case vex_vsib_q_w_dq_mode:
13622 case vex_vsib_q_w_d_mode:
13623 names = vex.w ? names_ymm : names_xmm;
13624 break;
13625 case mask_bd_mode:
13626 case mask_mode:
13627 if (reg > 0x7)
13628 {
13629 oappend ("(bad)");
13630 return;
13631 }
13632 names = names_mask;
13633 break;
13634 default:
13635 /* See PR binutils/20893 for a reproducer. */
13636 oappend ("(bad)");
13637 return;
13638 }
13639 break;
13640 case 512:
13641 names = names_zmm;
13642 break;
13643 default:
13644 abort ();
13645 break;
13646 }
13647 oappend (names[reg]);
13648 }
13649
13650 static void
13651 OP_VexR (int bytemode, int sizeflag)
13652 {
13653 if (modrm.mod == 3)
13654 OP_VEX (bytemode, sizeflag);
13655 }
13656
13657 static void
13658 OP_VexW (int bytemode, int sizeflag)
13659 {
13660 OP_VEX (bytemode, sizeflag);
13661
13662 if (vex.w)
13663 {
13664 /* Swap 2nd and 3rd operands. */
13665 strcpy (scratchbuf, op_out[2]);
13666 strcpy (op_out[2], op_out[1]);
13667 strcpy (op_out[1], scratchbuf);
13668 }
13669 }
13670
13671 static void
13672 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13673 {
13674 int reg;
13675 const char **names = names_xmm;
13676
13677 FETCH_DATA (the_info, codep + 1);
13678 reg = *codep++;
13679
13680 if (bytemode != x_mode && bytemode != scalar_mode)
13681 abort ();
13682
13683 reg >>= 4;
13684 if (address_mode != mode_64bit)
13685 reg &= 7;
13686
13687 if (bytemode == x_mode && vex.length == 256)
13688 names = names_ymm;
13689
13690 oappend (names[reg]);
13691
13692 if (vex.w)
13693 {
13694 /* Swap 3rd and 4th operands. */
13695 strcpy (scratchbuf, op_out[3]);
13696 strcpy (op_out[3], op_out[2]);
13697 strcpy (op_out[2], scratchbuf);
13698 }
13699 }
13700
13701 static void
13702 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13703 int sizeflag ATTRIBUTE_UNUSED)
13704 {
13705 scratchbuf[0] = '$';
13706 print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13707 oappend_maybe_intel (scratchbuf);
13708 }
13709
13710 static void
13711 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13712 int sizeflag ATTRIBUTE_UNUSED)
13713 {
13714 unsigned int cmp_type;
13715
13716 if (!vex.evex)
13717 abort ();
13718
13719 FETCH_DATA (the_info, codep + 1);
13720 cmp_type = *codep++ & 0xff;
13721 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13722 If it's the case, print suffix, otherwise - print the immediate. */
13723 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13724 && cmp_type != 3
13725 && cmp_type != 7)
13726 {
13727 char suffix [3];
13728 char *p = mnemonicendp - 2;
13729
13730 /* vpcmp* can have both one- and two-lettered suffix. */
13731 if (p[0] == 'p')
13732 {
13733 p++;
13734 suffix[0] = p[0];
13735 suffix[1] = '\0';
13736 }
13737 else
13738 {
13739 suffix[0] = p[0];
13740 suffix[1] = p[1];
13741 suffix[2] = '\0';
13742 }
13743
13744 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13745 mnemonicendp += simd_cmp_op[cmp_type].len;
13746 }
13747 else
13748 {
13749 /* We have a reserved extension byte. Output it directly. */
13750 scratchbuf[0] = '$';
13751 print_operand_value (scratchbuf + 1, 1, cmp_type);
13752 oappend_maybe_intel (scratchbuf);
13753 scratchbuf[0] = '\0';
13754 }
13755 }
13756
13757 static const struct op xop_cmp_op[] =
13758 {
13759 { STRING_COMMA_LEN ("lt") },
13760 { STRING_COMMA_LEN ("le") },
13761 { STRING_COMMA_LEN ("gt") },
13762 { STRING_COMMA_LEN ("ge") },
13763 { STRING_COMMA_LEN ("eq") },
13764 { STRING_COMMA_LEN ("neq") },
13765 { STRING_COMMA_LEN ("false") },
13766 { STRING_COMMA_LEN ("true") }
13767 };
13768
13769 static void
13770 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13771 int sizeflag ATTRIBUTE_UNUSED)
13772 {
13773 unsigned int cmp_type;
13774
13775 FETCH_DATA (the_info, codep + 1);
13776 cmp_type = *codep++ & 0xff;
13777 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13778 {
13779 char suffix[3];
13780 char *p = mnemonicendp - 2;
13781
13782 /* vpcom* can have both one- and two-lettered suffix. */
13783 if (p[0] == 'm')
13784 {
13785 p++;
13786 suffix[0] = p[0];
13787 suffix[1] = '\0';
13788 }
13789 else
13790 {
13791 suffix[0] = p[0];
13792 suffix[1] = p[1];
13793 suffix[2] = '\0';
13794 }
13795
13796 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13797 mnemonicendp += xop_cmp_op[cmp_type].len;
13798 }
13799 else
13800 {
13801 /* We have a reserved extension byte. Output it directly. */
13802 scratchbuf[0] = '$';
13803 print_operand_value (scratchbuf + 1, 1, cmp_type);
13804 oappend_maybe_intel (scratchbuf);
13805 scratchbuf[0] = '\0';
13806 }
13807 }
13808
13809 static const struct op pclmul_op[] =
13810 {
13811 { STRING_COMMA_LEN ("lql") },
13812 { STRING_COMMA_LEN ("hql") },
13813 { STRING_COMMA_LEN ("lqh") },
13814 { STRING_COMMA_LEN ("hqh") }
13815 };
13816
13817 static void
13818 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13819 int sizeflag ATTRIBUTE_UNUSED)
13820 {
13821 unsigned int pclmul_type;
13822
13823 FETCH_DATA (the_info, codep + 1);
13824 pclmul_type = *codep++ & 0xff;
13825 switch (pclmul_type)
13826 {
13827 case 0x10:
13828 pclmul_type = 2;
13829 break;
13830 case 0x11:
13831 pclmul_type = 3;
13832 break;
13833 default:
13834 break;
13835 }
13836 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13837 {
13838 char suffix [4];
13839 char *p = mnemonicendp - 3;
13840 suffix[0] = p[0];
13841 suffix[1] = p[1];
13842 suffix[2] = p[2];
13843 suffix[3] = '\0';
13844 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13845 mnemonicendp += pclmul_op[pclmul_type].len;
13846 }
13847 else
13848 {
13849 /* We have a reserved extension byte. Output it directly. */
13850 scratchbuf[0] = '$';
13851 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13852 oappend_maybe_intel (scratchbuf);
13853 scratchbuf[0] = '\0';
13854 }
13855 }
13856
13857 static void
13858 MOVSXD_Fixup (int bytemode, int sizeflag)
13859 {
13860 /* Add proper suffix to "movsxd". */
13861 char *p = mnemonicendp;
13862
13863 switch (bytemode)
13864 {
13865 case movsxd_mode:
13866 if (intel_syntax)
13867 {
13868 *p++ = 'x';
13869 *p++ = 'd';
13870 goto skip;
13871 }
13872
13873 USED_REX (REX_W);
13874 if (rex & REX_W)
13875 {
13876 *p++ = 'l';
13877 *p++ = 'q';
13878 }
13879 else
13880 {
13881 *p++ = 'x';
13882 *p++ = 'd';
13883 }
13884 break;
13885 default:
13886 oappend (INTERNAL_DISASSEMBLER_ERROR);
13887 break;
13888 }
13889
13890 skip:
13891 mnemonicendp = p;
13892 *p = '\0';
13893 OP_E (bytemode, sizeflag);
13894 }
13895
13896 static void
13897 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13898 {
13899 if (!vex.evex
13900 || (bytemode != mask_mode && bytemode != mask_bd_mode))
13901 abort ();
13902
13903 USED_REX (REX_R);
13904 if ((rex & REX_R) != 0 || !vex.r)
13905 {
13906 BadOp ();
13907 return;
13908 }
13909
13910 oappend (names_mask [modrm.reg]);
13911 }
13912
13913 static void
13914 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13915 {
13916 if (modrm.mod == 3 && vex.b)
13917 switch (bytemode)
13918 {
13919 case evex_rounding_64_mode:
13920 if (address_mode != mode_64bit)
13921 {
13922 oappend ("(bad)");
13923 break;
13924 }
13925 /* Fall through. */
13926 case evex_rounding_mode:
13927 oappend (names_rounding[vex.ll]);
13928 break;
13929 case evex_sae_mode:
13930 oappend ("{sae}");
13931 break;
13932 default:
13933 abort ();
13934 break;
13935 }
13936 }