opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2023 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43 typedef struct instr_info instr_info;
  44
  45 static void dofloat (instr_info *, int);
  46 static void OP_ST (instr_info *, int, int);
  47 static void OP_STi (instr_info *, int, int);
  48 static int putop (instr_info *, const char *, int);
  49 static void oappend_with_style (instr_info *, const char *,
  50                                 enum disassembler_style);
  51 static void oappend (instr_info *, const char *);
  52 static void append_seg (instr_info *);
  53 static void OP_indirE (instr_info *, int, int);
  54 static void OP_E_memory (instr_info *, int, int);
  55 static void OP_E (instr_info *, int, int);
  56 static void OP_G (instr_info *, int, int);
  57 static bfd_vma get64 (instr_info *);
  58 static bfd_signed_vma get32 (instr_info *);
  59 static bfd_signed_vma get32s (instr_info *);
  60 static int get16 (instr_info *);
  61 static void set_op (instr_info *, bfd_vma, bool);
  62 static void OP_Skip_MODRM (instr_info *, int, int);
  63 static void OP_REG (instr_info *, int, int);
  64 static void OP_IMREG (instr_info *, int, int);
  65 static void OP_I (instr_info *, int, int);
  66 static void OP_I64 (instr_info *, int, int);
  67 static void OP_sI (instr_info *, int, int);
  68 static void OP_J (instr_info *, int, int);
  69 static void OP_SEG (instr_info *, int, int);
  70 static void OP_DIR (instr_info *, int, int);
  71 static void OP_OFF (instr_info *, int, int);
  72 static void OP_OFF64 (instr_info *, int, int);
  73 static void ptr_reg (instr_info *, int, int);
  74 static void OP_ESreg (instr_info *, int, int);
  75 static void OP_DSreg (instr_info *, int, int);
  76 static void OP_C (instr_info *, int, int);
  77 static void OP_D (instr_info *, int, int);
  78 static void OP_T (instr_info *, int, int);
  79 static void OP_MMX (instr_info *, int, int);
  80 static void OP_XMM (instr_info *, int, int);
  81 static void OP_EM (instr_info *, int, int);
  82 static void OP_EX (instr_info *, int, int);
  83 static void OP_EMC (instr_info *, int,int);
  84 static void OP_MXC (instr_info *, int,int);
  85 static void OP_MS (instr_info *, int, int);
  86 static void OP_XS (instr_info *, int, int);
  87 static void OP_M (instr_info *, int, int);
  88 static void OP_VEX (instr_info *, int, int);
  89 static void OP_VexR (instr_info *, int, int);
  90 static void OP_VexW (instr_info *, int, int);
  91 static void OP_Rounding (instr_info *, int, int);
  92 static void OP_REG_VexI4 (instr_info *, int, int);
  93 static void OP_VexI4 (instr_info *, int, int);
  94 static void PCLMUL_Fixup (instr_info *, int, int);
  95 static void VPCMP_Fixup (instr_info *, int, int);
  96 static void VPCOM_Fixup (instr_info *, int, int);
  97 static void OP_0f07 (instr_info *, int, int);
  98 static void OP_Monitor (instr_info *, int, int);
  99 static void OP_Mwait (instr_info *, int, int);
 100 static void NOP_Fixup (instr_info *, int, int);
 101 static void OP_3DNowSuffix (instr_info *, int, int);
 102 static void CMP_Fixup (instr_info *, int, int);
 103 static void BadOp (instr_info *);
 104 static void REP_Fixup (instr_info *, int, int);
 105 static void SEP_Fixup (instr_info *, int, int);
 106 static void BND_Fixup (instr_info *, int, int);
 107 static void NOTRACK_Fixup (instr_info *, int, int);
 108 static void HLE_Fixup1 (instr_info *, int, int);
 109 static void HLE_Fixup2 (instr_info *, int, int);
 110 static void HLE_Fixup3 (instr_info *, int, int);
 111 static void CMPXCHG8B_Fixup (instr_info *, int, int);
 112 static void XMM_Fixup (instr_info *, int, int);
 113 static void FXSAVE_Fixup (instr_info *, int, int);
 114
 115 static void MOVSXD_Fixup (instr_info *, int, int);
 116 static void DistinctDest_Fixup (instr_info *, int, int);
 117 static void PREFETCHI_Fixup (instr_info *, int, int);
 118
 119 /* This character is used to encode style information within the output
 120    buffers.  See oappend_insert_style for more details.  */
 121 #define STYLE_MARKER_CHAR '\002'
 122
 123 /* The maximum operand buffer size.  */
 124 #define MAX_OPERAND_BUFFER_SIZE 128
 125
 126 struct dis_private {
 127   /* Points to first byte not fetched.  */
 128   bfd_byte *max_fetched;
 129   bfd_byte the_buffer[MAX_MNEM_SIZE];
 130   bfd_vma insn_start;
 131   int orig_sizeflag;
 132   OPCODES_SIGJMP_BUF bailout;
 133 };
 134
 135 enum address_mode
 136 {
 137   mode_16bit,
 138   mode_32bit,
 139   mode_64bit
 140 };
 141
 142 enum x86_64_isa
 143 {
 144   amd64 = 1,
 145   intel64
 146 };
 147
 148 struct instr_info
 149 {
 150   enum address_mode address_mode;
 151
 152   /* Flags for the prefixes for the current instruction.  See below.  */
 153   int prefixes;
 154
 155   /* REX prefix the current instruction.  See below.  */
 156   unsigned char rex;
 157   /* Bits of REX we've already used.  */
 158   unsigned char rex_used;
 159
 160   bool need_modrm;
 161   bool need_vex;
 162   bool has_sib;
 163
 164   /* Flags for ins->prefixes which we somehow handled when printing the
 165      current instruction.  */
 166   int used_prefixes;
 167
 168   /* Flags for EVEX bits which we somehow handled when printing the
 169      current instruction.  */
 170   int evex_used;
 171
 172   char obuf[MAX_OPERAND_BUFFER_SIZE];
 173   char *obufp;
 174   char *mnemonicendp;
 175   unsigned char *start_codep;
 176   unsigned char *insn_codep;
 177   unsigned char *codep;
 178   unsigned char *end_codep;
 179   signed char last_lock_prefix;
 180   signed char last_repz_prefix;
 181   signed char last_repnz_prefix;
 182   signed char last_data_prefix;
 183   signed char last_addr_prefix;
 184   signed char last_rex_prefix;
 185   signed char last_seg_prefix;
 186   signed char fwait_prefix;
 187   /* The active segment register prefix.  */
 188   unsigned char active_seg_prefix;
 189
 190 #define MAX_CODE_LENGTH 15
 191   /* We can up to 14 ins->prefixes since the maximum instruction length is
 192      15bytes.  */
 193   unsigned char all_prefixes[MAX_CODE_LENGTH - 1];
 194   disassemble_info *info;
 195
 196   struct
 197   {
 198     int mod;
 199     int reg;
 200     int rm;
 201   }
 202   modrm;
 203
 204   struct
 205   {
 206     int scale;
 207     int index;
 208     int base;
 209   }
 210   sib;
 211
 212   struct
 213   {
 214     int register_specifier;
 215     int length;
 216     int prefix;
 217     int mask_register_specifier;
 218     int ll;
 219     bool w;
 220     bool evex;
 221     bool r;
 222     bool v;
 223     bool zeroing;
 224     bool b;
 225     bool no_broadcast;
 226   }
 227   vex;
 228
 229   /* Remember if the current op is a jump instruction.  */
 230   bool op_is_jump;
 231
 232   bool two_source_ops;
 233
 234   unsigned char op_ad;
 235   signed char op_index[MAX_OPERANDS];
 236   bool op_riprel[MAX_OPERANDS];
 237   char *op_out[MAX_OPERANDS];
 238   bfd_vma op_address[MAX_OPERANDS];
 239   bfd_vma start_pc;
 240
 241   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 242    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 243    *   section of the "Virtual 8086 Mode" chapter.)
 244    * 'pc' should be the address of this instruction, it will
 245    *   be used to print the target address if this is a relative jump or call
 246    * The function returns the length of this instruction in bytes.
 247    */
 248   char intel_syntax;
 249   bool intel_mnemonic;
 250   char open_char;
 251   char close_char;
 252   char separator_char;
 253   char scale_char;
 254
 255   enum x86_64_isa isa64;
 256 };
 257
 258 /* Mark parts used in the REX prefix.  When we are testing for
 259    empty prefix (for 8bit register REX extension), just mask it
 260    out.  Otherwise test for REX bit is excuse for existence of REX
 261    only in case value is nonzero.  */
 262 #define USED_REX(value)                                 \
 263   {                                                     \
 264     if (value)                                          \
 265       {                                                 \
 266         if ((ins->rex & value))                         \
 267           ins->rex_used |= (value) | REX_OPCODE;        \
 268       }                                                 \
 269     else                                                \
 270       ins->rex_used |= REX_OPCODE;                      \
 271   }
 272
 273
 274 #define EVEX_b_used 1
 275 #define EVEX_len_used 2
 276
 277 /* Flags stored in PREFIXES.  */
 278 #define PREFIX_REPZ 1
 279 #define PREFIX_REPNZ 2
 280 #define PREFIX_CS 4
 281 #define PREFIX_SS 8
 282 #define PREFIX_DS 0x10
 283 #define PREFIX_ES 0x20
 284 #define PREFIX_FS 0x40
 285 #define PREFIX_GS 0x80
 286 #define PREFIX_LOCK 0x100
 287 #define PREFIX_DATA 0x200
 288 #define PREFIX_ADDR 0x400
 289 #define PREFIX_FWAIT 0x800
 290
 291 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 292    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 293    on error.  */
 294 #define FETCH_DATA(info, addr) \
 295   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 296    ? 1 : fetch_data ((info), (addr)))
 297
 298 static int
 299 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 300 {
 301   int status;
 302   struct dis_private *priv = (struct dis_private *) info->private_data;
 303   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 304
 305   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 306     status = (*info->read_memory_func) (start,
 307                                         priv->max_fetched,
 308                                         addr - priv->max_fetched,
 309                                         info);
 310   else
 311     status = -1;
 312   if (status != 0)
 313     {
 314       /* If we did manage to read at least one byte, then
 315          print_insn_i386 will do something sensible.  Otherwise, print
 316          an error.  We do that here because this is where we know
 317          STATUS.  */
 318       if (priv->max_fetched == priv->the_buffer)
 319         (*info->memory_error_func) (status, start, info);
 320       OPCODES_SIGLONGJMP (priv->bailout, 1);
 321     }
 322   else
 323     priv->max_fetched = addr;
 324   return 1;
 325 }
 326
 327 /* Possible values for prefix requirement.  */
 328 #define PREFIX_IGNORED_SHIFT    16
 329 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 330 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 331 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 332 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 333 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 334
 335 /* Opcode prefixes.  */
 336 #define PREFIX_OPCODE           (PREFIX_REPZ \
 337                                  | PREFIX_REPNZ \
 338                                  | PREFIX_DATA)
 339
 340 /* Prefixes ignored.  */
 341 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 342                                  | PREFIX_IGNORED_REPNZ \
 343                                  | PREFIX_IGNORED_DATA)
 344
 345 #define XX { NULL, 0 }
 346 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 347
 348 #define Eb { OP_E, b_mode }
 349 #define Ebnd { OP_E, bnd_mode }
 350 #define EbS { OP_E, b_swap_mode }
 351 #define EbndS { OP_E, bnd_swap_mode }
 352 #define Ev { OP_E, v_mode }
 353 #define Eva { OP_E, va_mode }
 354 #define Ev_bnd { OP_E, v_bnd_mode }
 355 #define EvS { OP_E, v_swap_mode }
 356 #define Ed { OP_E, d_mode }
 357 #define Edq { OP_E, dq_mode }
 358 #define Edb { OP_E, db_mode }
 359 #define Edw { OP_E, dw_mode }
 360 #define Eq { OP_E, q_mode }
 361 #define indirEv { OP_indirE, indir_v_mode }
 362 #define indirEp { OP_indirE, f_mode }
 363 #define stackEv { OP_E, stack_v_mode }
 364 #define Em { OP_E, m_mode }
 365 #define Ew { OP_E, w_mode }
 366 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 367 #define Ma { OP_M, a_mode }
 368 #define Mb { OP_M, b_mode }
 369 #define Md { OP_M, d_mode }
 370 #define Mdq { OP_M, dq_mode }
 371 #define Mo { OP_M, o_mode }
 372 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 373 #define Mq { OP_M, q_mode }
 374 #define Mv { OP_M, v_mode }
 375 #define Mv_bnd { OP_M, v_bndmk_mode }
 376 #define Mw { OP_M, w_mode }
 377 #define Mx { OP_M, x_mode }
 378 #define Mxmm { OP_M, xmm_mode }
 379 #define Gb { OP_G, b_mode }
 380 #define Gbnd { OP_G, bnd_mode }
 381 #define Gv { OP_G, v_mode }
 382 #define Gd { OP_G, d_mode }
 383 #define Gdq { OP_G, dq_mode }
 384 #define Gm { OP_G, m_mode }
 385 #define Gva { OP_G, va_mode }
 386 #define Gw { OP_G, w_mode }
 387 #define Ib { OP_I, b_mode }
 388 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 389 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 390 #define Iv { OP_I, v_mode }
 391 #define sIv { OP_sI, v_mode }
 392 #define Iv64 { OP_I64, v_mode }
 393 #define Id { OP_I, d_mode }
 394 #define Iw { OP_I, w_mode }
 395 #define I1 { OP_I, const_1_mode }
 396 #define Jb { OP_J, b_mode }
 397 #define Jv { OP_J, v_mode }
 398 #define Jdqw { OP_J, dqw_mode }
 399 #define Cm { OP_C, m_mode }
 400 #define Dm { OP_D, m_mode }
 401 #define Td { OP_T, d_mode }
 402 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 403
 404 #define RMeAX { OP_REG, eAX_reg }
 405 #define RMeBX { OP_REG, eBX_reg }
 406 #define RMeCX { OP_REG, eCX_reg }
 407 #define RMeDX { OP_REG, eDX_reg }
 408 #define RMeSP { OP_REG, eSP_reg }
 409 #define RMeBP { OP_REG, eBP_reg }
 410 #define RMeSI { OP_REG, eSI_reg }
 411 #define RMeDI { OP_REG, eDI_reg }
 412 #define RMrAX { OP_REG, rAX_reg }
 413 #define RMrBX { OP_REG, rBX_reg }
 414 #define RMrCX { OP_REG, rCX_reg }
 415 #define RMrDX { OP_REG, rDX_reg }
 416 #define RMrSP { OP_REG, rSP_reg }
 417 #define RMrBP { OP_REG, rBP_reg }
 418 #define RMrSI { OP_REG, rSI_reg }
 419 #define RMrDI { OP_REG, rDI_reg }
 420 #define RMAL { OP_REG, al_reg }
 421 #define RMCL { OP_REG, cl_reg }
 422 #define RMDL { OP_REG, dl_reg }
 423 #define RMBL { OP_REG, bl_reg }
 424 #define RMAH { OP_REG, ah_reg }
 425 #define RMCH { OP_REG, ch_reg }
 426 #define RMDH { OP_REG, dh_reg }
 427 #define RMBH { OP_REG, bh_reg }
 428 #define RMAX { OP_REG, ax_reg }
 429 #define RMDX { OP_REG, dx_reg }
 430
 431 #define eAX { OP_IMREG, eAX_reg }
 432 #define AL { OP_IMREG, al_reg }
 433 #define CL { OP_IMREG, cl_reg }
 434 #define zAX { OP_IMREG, z_mode_ax_reg }
 435 #define indirDX { OP_IMREG, indir_dx_reg }
 436
 437 #define Sw { OP_SEG, w_mode }
 438 #define Sv { OP_SEG, v_mode }
 439 #define Ap { OP_DIR, 0 }
 440 #define Ob { OP_OFF64, b_mode }
 441 #define Ov { OP_OFF64, v_mode }
 442 #define Xb { OP_DSreg, eSI_reg }
 443 #define Xv { OP_DSreg, eSI_reg }
 444 #define Xz { OP_DSreg, eSI_reg }
 445 #define Yb { OP_ESreg, eDI_reg }
 446 #define Yv { OP_ESreg, eDI_reg }
 447 #define DSBX { OP_DSreg, eBX_reg }
 448
 449 #define es { OP_REG, es_reg }
 450 #define ss { OP_REG, ss_reg }
 451 #define cs { OP_REG, cs_reg }
 452 #define ds { OP_REG, ds_reg }
 453 #define fs { OP_REG, fs_reg }
 454 #define gs { OP_REG, gs_reg }
 455
 456 #define MX { OP_MMX, 0 }
 457 #define XM { OP_XMM, 0 }
 458 #define XMScalar { OP_XMM, scalar_mode }
 459 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 460 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 461 #define XMM { OP_XMM, xmm_mode }
 462 #define TMM { OP_XMM, tmm_mode }
 463 #define XMxmmq { OP_XMM, xmmq_mode }
 464 #define EM { OP_EM, v_mode }
 465 #define EMS { OP_EM, v_swap_mode }
 466 #define EMd { OP_EM, d_mode }
 467 #define EMx { OP_EM, x_mode }
 468 #define EXbwUnit { OP_EX, bw_unit_mode }
 469 #define EXb { OP_EX, b_mode }
 470 #define EXw { OP_EX, w_mode }
 471 #define EXd { OP_EX, d_mode }
 472 #define EXdS { OP_EX, d_swap_mode }
 473 #define EXwS { OP_EX, w_swap_mode }
 474 #define EXq { OP_EX, q_mode }
 475 #define EXqS { OP_EX, q_swap_mode }
 476 #define EXdq { OP_EX, dq_mode }
 477 #define EXx { OP_EX, x_mode }
 478 #define EXxh { OP_EX, xh_mode }
 479 #define EXxS { OP_EX, x_swap_mode }
 480 #define EXxmm { OP_EX, xmm_mode }
 481 #define EXymm { OP_EX, ymm_mode }
 482 #define EXtmm { OP_EX, tmm_mode }
 483 #define EXxmmq { OP_EX, xmmq_mode }
 484 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 485 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 486 #define EXxmmdw { OP_EX, xmmdw_mode }
 487 #define EXxmmqd { OP_EX, xmmqd_mode }
 488 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 489 #define EXymmq { OP_EX, ymmq_mode }
 490 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 491 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 492 #define MS { OP_MS, v_mode }
 493 #define XS { OP_XS, v_mode }
 494 #define EMCq { OP_EMC, q_mode }
 495 #define MXC { OP_MXC, 0 }
 496 #define OPSUF { OP_3DNowSuffix, 0 }
 497 #define SEP { SEP_Fixup, 0 }
 498 #define CMP { CMP_Fixup, 0 }
 499 #define XMM0 { XMM_Fixup, 0 }
 500 #define FXSAVE { FXSAVE_Fixup, 0 }
 501
 502 #define Vex { OP_VEX, x_mode }
 503 #define VexW { OP_VexW, x_mode }
 504 #define VexScalar { OP_VEX, scalar_mode }
 505 #define VexScalarR { OP_VexR, scalar_mode }
 506 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 507 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 508 #define VexGdq { OP_VEX, dq_mode }
 509 #define VexTmm { OP_VEX, tmm_mode }
 510 #define XMVexI4 { OP_REG_VexI4, x_mode }
 511 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 512 #define VexI4 { OP_VexI4, 0 }
 513 #define PCLMUL { PCLMUL_Fixup, 0 }
 514 #define VPCMP { VPCMP_Fixup, 0 }
 515 #define VPCOM { VPCOM_Fixup, 0 }
 516
 517 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 518 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 519 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 520
 521 #define MaskG { OP_G, mask_mode }
 522 #define MaskE { OP_E, mask_mode }
 523 #define MaskBDE { OP_E, mask_bd_mode }
 524 #define MaskVex { OP_VEX, mask_mode }
 525
 526 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 527 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 528
 529 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 530
 531 /* Used handle "rep" prefix for string instructions.  */
 532 #define Xbr { REP_Fixup, eSI_reg }
 533 #define Xvr { REP_Fixup, eSI_reg }
 534 #define Ybr { REP_Fixup, eDI_reg }
 535 #define Yvr { REP_Fixup, eDI_reg }
 536 #define Yzr { REP_Fixup, eDI_reg }
 537 #define indirDXr { REP_Fixup, indir_dx_reg }
 538 #define ALr { REP_Fixup, al_reg }
 539 #define eAXr { REP_Fixup, eAX_reg }
 540
 541 /* Used handle HLE prefix for lockable instructions.  */
 542 #define Ebh1 { HLE_Fixup1, b_mode }
 543 #define Evh1 { HLE_Fixup1, v_mode }
 544 #define Ebh2 { HLE_Fixup2, b_mode }
 545 #define Evh2 { HLE_Fixup2, v_mode }
 546 #define Ebh3 { HLE_Fixup3, b_mode }
 547 #define Evh3 { HLE_Fixup3, v_mode }
 548
 549 #define BND { BND_Fixup, 0 }
 550 #define NOTRACK { NOTRACK_Fixup, 0 }
 551
 552 #define cond_jump_flag { NULL, cond_jump_mode }
 553 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 554
 555 /* bits in sizeflag */
 556 #define SUFFIX_ALWAYS 4
 557 #define AFLAG 2
 558 #define DFLAG 1
 559
 560 enum
 561 {
 562   /* byte operand */
 563   b_mode = 1,
 564   /* byte operand with operand swapped */
 565   b_swap_mode,
 566   /* byte operand, sign extend like 'T' suffix */
 567   b_T_mode,
 568   /* operand size depends on prefixes */
 569   v_mode,
 570   /* operand size depends on prefixes with operand swapped */
 571   v_swap_mode,
 572   /* operand size depends on address prefix */
 573   va_mode,
 574   /* word operand */
 575   w_mode,
 576   /* double word operand  */
 577   d_mode,
 578   /* word operand with operand swapped  */
 579   w_swap_mode,
 580   /* double word operand with operand swapped */
 581   d_swap_mode,
 582   /* quad word operand */
 583   q_mode,
 584   /* quad word operand with operand swapped */
 585   q_swap_mode,
 586   /* ten-byte operand */
 587   t_mode,
 588   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 589      broadcast enabled.  */
 590   x_mode,
 591   /* Similar to x_mode, but with different EVEX mem shifts.  */
 592   evex_x_gscat_mode,
 593   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 594   bw_unit_mode,
 595   /* Similar to x_mode, but with disabled broadcast.  */
 596   evex_x_nobcst_mode,
 597   /* Similar to x_mode, but with operands swapped and disabled broadcast
 598      in EVEX.  */
 599   x_swap_mode,
 600   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 601      broadcast of 16bit enabled.  */
 602   xh_mode,
 603   /* 16-byte XMM operand */
 604   xmm_mode,
 605   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 606      memory operand (depending on vector length).  Broadcast isn't
 607      allowed.  */
 608   xmmq_mode,
 609   /* Same as xmmq_mode, but broadcast is allowed.  */
 610   evex_half_bcst_xmmq_mode,
 611   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 612      memory operand (depending on vector length).  16bit broadcast.  */
 613   evex_half_bcst_xmmqh_mode,
 614   /* 16-byte XMM, word, double word or quad word operand.  */
 615   xmmdw_mode,
 616   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 617   xmmqd_mode,
 618   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 619      16bit broadcast.  */
 620   evex_half_bcst_xmmqdh_mode,
 621   /* 32-byte YMM operand */
 622   ymm_mode,
 623   /* quad word, ymmword or zmmword memory operand.  */
 624   ymmq_mode,
 625   /* TMM operand */
 626   tmm_mode,
 627   /* d_mode in 32bit, q_mode in 64bit mode.  */
 628   m_mode,
 629   /* pair of v_mode operands */
 630   a_mode,
 631   cond_jump_mode,
 632   loop_jcxz_mode,
 633   movsxd_mode,
 634   v_bnd_mode,
 635   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 636   v_bndmk_mode,
 637   /* operand size depends on REX.W / VEX.W.  */
 638   dq_mode,
 639   /* Displacements like v_mode without considering Intel64 ISA.  */
 640   dqw_mode,
 641   /* bounds operand */
 642   bnd_mode,
 643   /* bounds operand with operand swapped */
 644   bnd_swap_mode,
 645   /* 4- or 6-byte pointer operand */
 646   f_mode,
 647   const_1_mode,
 648   /* v_mode for indirect branch opcodes.  */
 649   indir_v_mode,
 650   /* v_mode for stack-related opcodes.  */
 651   stack_v_mode,
 652   /* non-quad operand size depends on prefixes */
 653   z_mode,
 654   /* 16-byte operand */
 655   o_mode,
 656   /* registers like d_mode, memory like b_mode.  */
 657   db_mode,
 658   /* registers like d_mode, memory like w_mode.  */
 659   dw_mode,
 660
 661   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 662   vex_vsib_d_w_dq_mode,
 663   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 664   vex_vsib_q_w_dq_mode,
 665   /* mandatory non-vector SIB.  */
 666   vex_sibmem_mode,
 667
 668   /* scalar, ignore vector length.  */
 669   scalar_mode,
 670
 671   /* Static rounding.  */
 672   evex_rounding_mode,
 673   /* Static rounding, 64-bit mode only.  */
 674   evex_rounding_64_mode,
 675   /* Supress all exceptions.  */
 676   evex_sae_mode,
 677
 678   /* Mask register operand.  */
 679   mask_mode,
 680   /* Mask register operand.  */
 681   mask_bd_mode,
 682
 683   es_reg,
 684   cs_reg,
 685   ss_reg,
 686   ds_reg,
 687   fs_reg,
 688   gs_reg,
 689
 690   eAX_reg,
 691   eCX_reg,
 692   eDX_reg,
 693   eBX_reg,
 694   eSP_reg,
 695   eBP_reg,
 696   eSI_reg,
 697   eDI_reg,
 698
 699   al_reg,
 700   cl_reg,
 701   dl_reg,
 702   bl_reg,
 703   ah_reg,
 704   ch_reg,
 705   dh_reg,
 706   bh_reg,
 707
 708   ax_reg,
 709   cx_reg,
 710   dx_reg,
 711   bx_reg,
 712   sp_reg,
 713   bp_reg,
 714   si_reg,
 715   di_reg,
 716
 717   rAX_reg,
 718   rCX_reg,
 719   rDX_reg,
 720   rBX_reg,
 721   rSP_reg,
 722   rBP_reg,
 723   rSI_reg,
 724   rDI_reg,
 725
 726   z_mode_ax_reg,
 727   indir_dx_reg
 728 };
 729
 730 enum
 731 {
 732   FLOATCODE = 1,
 733   USE_REG_TABLE,
 734   USE_MOD_TABLE,
 735   USE_RM_TABLE,
 736   USE_PREFIX_TABLE,
 737   USE_X86_64_TABLE,
 738   USE_3BYTE_TABLE,
 739   USE_XOP_8F_TABLE,
 740   USE_VEX_C4_TABLE,
 741   USE_VEX_C5_TABLE,
 742   USE_VEX_LEN_TABLE,
 743   USE_VEX_W_TABLE,
 744   USE_EVEX_TABLE,
 745   USE_EVEX_LEN_TABLE
 746 };
 747
 748 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 749
 750 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 751 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 752 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 753 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 754 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 755 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 756 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 757 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 758 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 759 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 760 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 761 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 762 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 763 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 764 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 765 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 766
 767 enum
 768 {
 769   REG_80 = 0,
 770   REG_81,
 771   REG_83,
 772   REG_8F,
 773   REG_C0,
 774   REG_C1,
 775   REG_C6,
 776   REG_C7,
 777   REG_D0,
 778   REG_D1,
 779   REG_D2,
 780   REG_D3,
 781   REG_F6,
 782   REG_F7,
 783   REG_FE,
 784   REG_FF,
 785   REG_0F00,
 786   REG_0F01,
 787   REG_0F0D,
 788   REG_0F18,
 789   REG_0F1C_P_0_MOD_0,
 790   REG_0F1E_P_1_MOD_3,
 791   REG_0F38D8_PREFIX_1,
 792   REG_0F3A0F_PREFIX_1_MOD_3,
 793   REG_0F71_MOD_0,
 794   REG_0F72_MOD_0,
 795   REG_0F73_MOD_0,
 796   REG_0FA6,
 797   REG_0FA7,
 798   REG_0FAE,
 799   REG_0FBA,
 800   REG_0FC7,
 801   REG_VEX_0F71_M_0,
 802   REG_VEX_0F72_M_0,
 803   REG_VEX_0F73_M_0,
 804   REG_VEX_0FAE,
 805   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 806   REG_VEX_0F38F3_L_0,
 807
 808   REG_XOP_09_01_L_0,
 809   REG_XOP_09_02_L_0,
 810   REG_XOP_09_12_M_1_L_0,
 811   REG_XOP_0A_12_L_0,
 812
 813   REG_EVEX_0F71,
 814   REG_EVEX_0F72,
 815   REG_EVEX_0F73,
 816   REG_EVEX_0F38C6_M_0_L_2,
 817   REG_EVEX_0F38C7_M_0_L_2
 818 };
 819
 820 enum
 821 {
 822   MOD_62_32BIT = 0,
 823   MOD_8D,
 824   MOD_C4_32BIT,
 825   MOD_C5_32BIT,
 826   MOD_C6_REG_7,
 827   MOD_C7_REG_7,
 828   MOD_FF_REG_3,
 829   MOD_FF_REG_5,
 830   MOD_0F01_REG_0,
 831   MOD_0F01_REG_1,
 832   MOD_0F01_REG_2,
 833   MOD_0F01_REG_3,
 834   MOD_0F01_REG_5,
 835   MOD_0F01_REG_7,
 836   MOD_0F02,
 837   MOD_0F03,
 838   MOD_0F12_PREFIX_0,
 839   MOD_0F12_PREFIX_2,
 840   MOD_0F13,
 841   MOD_0F16_PREFIX_0,
 842   MOD_0F16_PREFIX_2,
 843   MOD_0F17,
 844   MOD_0F18_REG_0,
 845   MOD_0F18_REG_1,
 846   MOD_0F18_REG_2,
 847   MOD_0F18_REG_3,
 848   MOD_0F18_REG_6,
 849   MOD_0F18_REG_7,
 850   MOD_0F1A_PREFIX_0,
 851   MOD_0F1B_PREFIX_0,
 852   MOD_0F1B_PREFIX_1,
 853   MOD_0F1C_PREFIX_0,
 854   MOD_0F1E_PREFIX_1,
 855   MOD_0F2B_PREFIX_0,
 856   MOD_0F2B_PREFIX_1,
 857   MOD_0F2B_PREFIX_2,
 858   MOD_0F2B_PREFIX_3,
 859   MOD_0F50,
 860   MOD_0F71,
 861   MOD_0F72,
 862   MOD_0F73,
 863   MOD_0FAE_REG_0,
 864   MOD_0FAE_REG_1,
 865   MOD_0FAE_REG_2,
 866   MOD_0FAE_REG_3,
 867   MOD_0FAE_REG_4,
 868   MOD_0FAE_REG_5,
 869   MOD_0FAE_REG_6,
 870   MOD_0FAE_REG_7,
 871   MOD_0FB2,
 872   MOD_0FB4,
 873   MOD_0FB5,
 874   MOD_0FC3,
 875   MOD_0FC7_REG_3,
 876   MOD_0FC7_REG_4,
 877   MOD_0FC7_REG_5,
 878   MOD_0FC7_REG_6,
 879   MOD_0FC7_REG_7,
 880   MOD_0FD7,
 881   MOD_0FE7_PREFIX_2,
 882   MOD_0FF0_PREFIX_3,
 883   MOD_0F382A,
 884   MOD_0F38DC_PREFIX_1,
 885   MOD_0F38DD_PREFIX_1,
 886   MOD_0F38DE_PREFIX_1,
 887   MOD_0F38DF_PREFIX_1,
 888   MOD_0F38F5,
 889   MOD_0F38F6_PREFIX_0,
 890   MOD_0F38F8_PREFIX_1,
 891   MOD_0F38F8_PREFIX_2,
 892   MOD_0F38F8_PREFIX_3,
 893   MOD_0F38F9,
 894   MOD_0F38FA_PREFIX_1,
 895   MOD_0F38FB_PREFIX_1,
 896   MOD_0F3A0F_PREFIX_1,
 897
 898   MOD_VEX_0F12_PREFIX_0,
 899   MOD_VEX_0F12_PREFIX_2,
 900   MOD_VEX_0F13,
 901   MOD_VEX_0F16_PREFIX_0,
 902   MOD_VEX_0F16_PREFIX_2,
 903   MOD_VEX_0F17,
 904   MOD_VEX_0F2B,
 905   MOD_VEX_0F41_L_1,
 906   MOD_VEX_0F42_L_1,
 907   MOD_VEX_0F44_L_0,
 908   MOD_VEX_0F45_L_1,
 909   MOD_VEX_0F46_L_1,
 910   MOD_VEX_0F47_L_1,
 911   MOD_VEX_0F4A_L_1,
 912   MOD_VEX_0F4B_L_1,
 913   MOD_VEX_0F50,
 914   MOD_VEX_0F71,
 915   MOD_VEX_0F72,
 916   MOD_VEX_0F73,
 917   MOD_VEX_0F91_L_0,
 918   MOD_VEX_0F92_L_0,
 919   MOD_VEX_0F93_L_0,
 920   MOD_VEX_0F98_L_0,
 921   MOD_VEX_0F99_L_0,
 922   MOD_VEX_0FAE_REG_2,
 923   MOD_VEX_0FAE_REG_3,
 924   MOD_VEX_0FD7,
 925   MOD_VEX_0FE7,
 926   MOD_VEX_0FF0_PREFIX_3,
 927   MOD_VEX_0F381A,
 928   MOD_VEX_0F382A,
 929   MOD_VEX_0F382C,
 930   MOD_VEX_0F382D,
 931   MOD_VEX_0F382E,
 932   MOD_VEX_0F382F,
 933   MOD_VEX_0F3849_X86_64_P_0_W_0,
 934   MOD_VEX_0F3849_X86_64_P_2_W_0,
 935   MOD_VEX_0F3849_X86_64_P_3_W_0,
 936   MOD_VEX_0F384B_X86_64_P_1_W_0,
 937   MOD_VEX_0F384B_X86_64_P_2_W_0,
 938   MOD_VEX_0F384B_X86_64_P_3_W_0,
 939   MOD_VEX_0F385A,
 940   MOD_VEX_0F385C_X86_64_P_1_W_0,
 941   MOD_VEX_0F385C_X86_64_P_3_W_0,
 942   MOD_VEX_0F385E_X86_64_P_0_W_0,
 943   MOD_VEX_0F385E_X86_64_P_1_W_0,
 944   MOD_VEX_0F385E_X86_64_P_2_W_0,
 945   MOD_VEX_0F385E_X86_64_P_3_W_0,
 946   MOD_VEX_0F388C,
 947   MOD_VEX_0F388E,
 948   MOD_VEX_0F3A30_L_0,
 949   MOD_VEX_0F3A31_L_0,
 950   MOD_VEX_0F3A32_L_0,
 951   MOD_VEX_0F3A33_L_0,
 952
 953   MOD_XOP_09_12,
 954
 955   MOD_EVEX_0F381A,
 956   MOD_EVEX_0F381B,
 957   MOD_EVEX_0F3828_P_1,
 958   MOD_EVEX_0F382A_P_1_W_1,
 959   MOD_EVEX_0F3838_P_1,
 960   MOD_EVEX_0F383A_P_1_W_0,
 961   MOD_EVEX_0F385A,
 962   MOD_EVEX_0F385B,
 963   MOD_EVEX_0F387A_W_0,
 964   MOD_EVEX_0F387B_W_0,
 965   MOD_EVEX_0F387C,
 966   MOD_EVEX_0F38C6,
 967   MOD_EVEX_0F38C7,
 968 };
 969
 970 enum
 971 {
 972   RM_C6_REG_7 = 0,
 973   RM_C7_REG_7,
 974   RM_0F01_REG_0,
 975   RM_0F01_REG_1,
 976   RM_0F01_REG_2,
 977   RM_0F01_REG_3,
 978   RM_0F01_REG_5_MOD_3,
 979   RM_0F01_REG_7_MOD_3,
 980   RM_0F1E_P_1_MOD_3_REG_7,
 981   RM_0FAE_REG_6_MOD_3_P_0,
 982   RM_0FAE_REG_7_MOD_3,
 983   RM_0F3A0F_P_1_MOD_3_REG_0,
 984
 985   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 986 };
 987
 988 enum
 989 {
 990   PREFIX_90 = 0,
 991   PREFIX_0F01_REG_0_MOD_3_RM_6,
 992   PREFIX_0F01_REG_1_RM_4,
 993   PREFIX_0F01_REG_1_RM_5,
 994   PREFIX_0F01_REG_1_RM_6,
 995   PREFIX_0F01_REG_1_RM_7,
 996   PREFIX_0F01_REG_3_RM_1,
 997   PREFIX_0F01_REG_5_MOD_0,
 998   PREFIX_0F01_REG_5_MOD_3_RM_0,
 999   PREFIX_0F01_REG_5_MOD_3_RM_1,
1000   PREFIX_0F01_REG_5_MOD_3_RM_2,
1001   PREFIX_0F01_REG_5_MOD_3_RM_4,
1002   PREFIX_0F01_REG_5_MOD_3_RM_5,
1003   PREFIX_0F01_REG_5_MOD_3_RM_6,
1004   PREFIX_0F01_REG_5_MOD_3_RM_7,
1005   PREFIX_0F01_REG_7_MOD_3_RM_2,
1006   PREFIX_0F01_REG_7_MOD_3_RM_5,
1007   PREFIX_0F01_REG_7_MOD_3_RM_6,
1008   PREFIX_0F01_REG_7_MOD_3_RM_7,
1009   PREFIX_0F09,
1010   PREFIX_0F10,
1011   PREFIX_0F11,
1012   PREFIX_0F12,
1013   PREFIX_0F16,
1014   PREFIX_0F18_REG_6_MOD_0_X86_64,
1015   PREFIX_0F18_REG_7_MOD_0_X86_64,
1016   PREFIX_0F1A,
1017   PREFIX_0F1B,
1018   PREFIX_0F1C,
1019   PREFIX_0F1E,
1020   PREFIX_0F2A,
1021   PREFIX_0F2B,
1022   PREFIX_0F2C,
1023   PREFIX_0F2D,
1024   PREFIX_0F2E,
1025   PREFIX_0F2F,
1026   PREFIX_0F51,
1027   PREFIX_0F52,
1028   PREFIX_0F53,
1029   PREFIX_0F58,
1030   PREFIX_0F59,
1031   PREFIX_0F5A,
1032   PREFIX_0F5B,
1033   PREFIX_0F5C,
1034   PREFIX_0F5D,
1035   PREFIX_0F5E,
1036   PREFIX_0F5F,
1037   PREFIX_0F60,
1038   PREFIX_0F61,
1039   PREFIX_0F62,
1040   PREFIX_0F6F,
1041   PREFIX_0F70,
1042   PREFIX_0F78,
1043   PREFIX_0F79,
1044   PREFIX_0F7C,
1045   PREFIX_0F7D,
1046   PREFIX_0F7E,
1047   PREFIX_0F7F,
1048   PREFIX_0FAE_REG_0_MOD_3,
1049   PREFIX_0FAE_REG_1_MOD_3,
1050   PREFIX_0FAE_REG_2_MOD_3,
1051   PREFIX_0FAE_REG_3_MOD_3,
1052   PREFIX_0FAE_REG_4_MOD_0,
1053   PREFIX_0FAE_REG_4_MOD_3,
1054   PREFIX_0FAE_REG_5_MOD_3,
1055   PREFIX_0FAE_REG_6_MOD_0,
1056   PREFIX_0FAE_REG_6_MOD_3,
1057   PREFIX_0FAE_REG_7_MOD_0,
1058   PREFIX_0FB8,
1059   PREFIX_0FBC,
1060   PREFIX_0FBD,
1061   PREFIX_0FC2,
1062   PREFIX_0FC7_REG_6_MOD_0,
1063   PREFIX_0FC7_REG_6_MOD_3,
1064   PREFIX_0FC7_REG_7_MOD_3,
1065   PREFIX_0FD0,
1066   PREFIX_0FD6,
1067   PREFIX_0FE6,
1068   PREFIX_0FE7,
1069   PREFIX_0FF0,
1070   PREFIX_0FF7,
1071   PREFIX_0F38D8,
1072   PREFIX_0F38DC,
1073   PREFIX_0F38DD,
1074   PREFIX_0F38DE,
1075   PREFIX_0F38DF,
1076   PREFIX_0F38F0,
1077   PREFIX_0F38F1,
1078   PREFIX_0F38F6,
1079   PREFIX_0F38F8,
1080   PREFIX_0F38FA,
1081   PREFIX_0F38FB,
1082   PREFIX_0F38FC,
1083   PREFIX_0F3A0F,
1084   PREFIX_VEX_0F10,
1085   PREFIX_VEX_0F11,
1086   PREFIX_VEX_0F12,
1087   PREFIX_VEX_0F16,
1088   PREFIX_VEX_0F2A,
1089   PREFIX_VEX_0F2C,
1090   PREFIX_VEX_0F2D,
1091   PREFIX_VEX_0F2E,
1092   PREFIX_VEX_0F2F,
1093   PREFIX_VEX_0F41_L_1_M_1_W_0,
1094   PREFIX_VEX_0F41_L_1_M_1_W_1,
1095   PREFIX_VEX_0F42_L_1_M_1_W_0,
1096   PREFIX_VEX_0F42_L_1_M_1_W_1,
1097   PREFIX_VEX_0F44_L_0_M_1_W_0,
1098   PREFIX_VEX_0F44_L_0_M_1_W_1,
1099   PREFIX_VEX_0F45_L_1_M_1_W_0,
1100   PREFIX_VEX_0F45_L_1_M_1_W_1,
1101   PREFIX_VEX_0F46_L_1_M_1_W_0,
1102   PREFIX_VEX_0F46_L_1_M_1_W_1,
1103   PREFIX_VEX_0F47_L_1_M_1_W_0,
1104   PREFIX_VEX_0F47_L_1_M_1_W_1,
1105   PREFIX_VEX_0F4A_L_1_M_1_W_0,
1106   PREFIX_VEX_0F4A_L_1_M_1_W_1,
1107   PREFIX_VEX_0F4B_L_1_M_1_W_0,
1108   PREFIX_VEX_0F4B_L_1_M_1_W_1,
1109   PREFIX_VEX_0F51,
1110   PREFIX_VEX_0F52,
1111   PREFIX_VEX_0F53,
1112   PREFIX_VEX_0F58,
1113   PREFIX_VEX_0F59,
1114   PREFIX_VEX_0F5A,
1115   PREFIX_VEX_0F5B,
1116   PREFIX_VEX_0F5C,
1117   PREFIX_VEX_0F5D,
1118   PREFIX_VEX_0F5E,
1119   PREFIX_VEX_0F5F,
1120   PREFIX_VEX_0F6F,
1121   PREFIX_VEX_0F70,
1122   PREFIX_VEX_0F7C,
1123   PREFIX_VEX_0F7D,
1124   PREFIX_VEX_0F7E,
1125   PREFIX_VEX_0F7F,
1126   PREFIX_VEX_0F90_L_0_W_0,
1127   PREFIX_VEX_0F90_L_0_W_1,
1128   PREFIX_VEX_0F91_L_0_M_0_W_0,
1129   PREFIX_VEX_0F91_L_0_M_0_W_1,
1130   PREFIX_VEX_0F92_L_0_M_1_W_0,
1131   PREFIX_VEX_0F92_L_0_M_1_W_1,
1132   PREFIX_VEX_0F93_L_0_M_1_W_0,
1133   PREFIX_VEX_0F93_L_0_M_1_W_1,
1134   PREFIX_VEX_0F98_L_0_M_1_W_0,
1135   PREFIX_VEX_0F98_L_0_M_1_W_1,
1136   PREFIX_VEX_0F99_L_0_M_1_W_0,
1137   PREFIX_VEX_0F99_L_0_M_1_W_1,
1138   PREFIX_VEX_0FC2,
1139   PREFIX_VEX_0FD0,
1140   PREFIX_VEX_0FE6,
1141   PREFIX_VEX_0FF0,
1142   PREFIX_VEX_0F3849_X86_64,
1143   PREFIX_VEX_0F384B_X86_64,
1144   PREFIX_VEX_0F3850_W_0,
1145   PREFIX_VEX_0F3851_W_0,
1146   PREFIX_VEX_0F385C_X86_64,
1147   PREFIX_VEX_0F385E_X86_64,
1148   PREFIX_VEX_0F3872,
1149   PREFIX_VEX_0F38B0_W_0,
1150   PREFIX_VEX_0F38B1_W_0,
1151   PREFIX_VEX_0F38F5_L_0,
1152   PREFIX_VEX_0F38F6_L_0,
1153   PREFIX_VEX_0F38F7_L_0,
1154   PREFIX_VEX_0F3AF0_L_0,
1155
1156   PREFIX_EVEX_0F5B,
1157   PREFIX_EVEX_0F6F,
1158   PREFIX_EVEX_0F70,
1159   PREFIX_EVEX_0F78,
1160   PREFIX_EVEX_0F79,
1161   PREFIX_EVEX_0F7A,
1162   PREFIX_EVEX_0F7B,
1163   PREFIX_EVEX_0F7E,
1164   PREFIX_EVEX_0F7F,
1165   PREFIX_EVEX_0FC2,
1166   PREFIX_EVEX_0FE6,
1167   PREFIX_EVEX_0F3810,
1168   PREFIX_EVEX_0F3811,
1169   PREFIX_EVEX_0F3812,
1170   PREFIX_EVEX_0F3813,
1171   PREFIX_EVEX_0F3814,
1172   PREFIX_EVEX_0F3815,
1173   PREFIX_EVEX_0F3820,
1174   PREFIX_EVEX_0F3821,
1175   PREFIX_EVEX_0F3822,
1176   PREFIX_EVEX_0F3823,
1177   PREFIX_EVEX_0F3824,
1178   PREFIX_EVEX_0F3825,
1179   PREFIX_EVEX_0F3826,
1180   PREFIX_EVEX_0F3827,
1181   PREFIX_EVEX_0F3828,
1182   PREFIX_EVEX_0F3829,
1183   PREFIX_EVEX_0F382A,
1184   PREFIX_EVEX_0F3830,
1185   PREFIX_EVEX_0F3831,
1186   PREFIX_EVEX_0F3832,
1187   PREFIX_EVEX_0F3833,
1188   PREFIX_EVEX_0F3834,
1189   PREFIX_EVEX_0F3835,
1190   PREFIX_EVEX_0F3838,
1191   PREFIX_EVEX_0F3839,
1192   PREFIX_EVEX_0F383A,
1193   PREFIX_EVEX_0F3852,
1194   PREFIX_EVEX_0F3853,
1195   PREFIX_EVEX_0F3868,
1196   PREFIX_EVEX_0F3872,
1197   PREFIX_EVEX_0F389A,
1198   PREFIX_EVEX_0F389B,
1199   PREFIX_EVEX_0F38AA,
1200   PREFIX_EVEX_0F38AB,
1201
1202   PREFIX_EVEX_0F3A08,
1203   PREFIX_EVEX_0F3A0A,
1204   PREFIX_EVEX_0F3A26,
1205   PREFIX_EVEX_0F3A27,
1206   PREFIX_EVEX_0F3A56,
1207   PREFIX_EVEX_0F3A57,
1208   PREFIX_EVEX_0F3A66,
1209   PREFIX_EVEX_0F3A67,
1210   PREFIX_EVEX_0F3AC2,
1211
1212   PREFIX_EVEX_MAP5_10,
1213   PREFIX_EVEX_MAP5_11,
1214   PREFIX_EVEX_MAP5_1D,
1215   PREFIX_EVEX_MAP5_2A,
1216   PREFIX_EVEX_MAP5_2C,
1217   PREFIX_EVEX_MAP5_2D,
1218   PREFIX_EVEX_MAP5_2E,
1219   PREFIX_EVEX_MAP5_2F,
1220   PREFIX_EVEX_MAP5_51,
1221   PREFIX_EVEX_MAP5_58,
1222   PREFIX_EVEX_MAP5_59,
1223   PREFIX_EVEX_MAP5_5A,
1224   PREFIX_EVEX_MAP5_5B,
1225   PREFIX_EVEX_MAP5_5C,
1226   PREFIX_EVEX_MAP5_5D,
1227   PREFIX_EVEX_MAP5_5E,
1228   PREFIX_EVEX_MAP5_5F,
1229   PREFIX_EVEX_MAP5_78,
1230   PREFIX_EVEX_MAP5_79,
1231   PREFIX_EVEX_MAP5_7A,
1232   PREFIX_EVEX_MAP5_7B,
1233   PREFIX_EVEX_MAP5_7C,
1234   PREFIX_EVEX_MAP5_7D,
1235
1236   PREFIX_EVEX_MAP6_13,
1237   PREFIX_EVEX_MAP6_56,
1238   PREFIX_EVEX_MAP6_57,
1239   PREFIX_EVEX_MAP6_D6,
1240   PREFIX_EVEX_MAP6_D7,
1241 };
1242
1243 enum
1244 {
1245   X86_64_06 = 0,
1246   X86_64_07,
1247   X86_64_0E,
1248   X86_64_16,
1249   X86_64_17,
1250   X86_64_1E,
1251   X86_64_1F,
1252   X86_64_27,
1253   X86_64_2F,
1254   X86_64_37,
1255   X86_64_3F,
1256   X86_64_60,
1257   X86_64_61,
1258   X86_64_62,
1259   X86_64_63,
1260   X86_64_6D,
1261   X86_64_6F,
1262   X86_64_82,
1263   X86_64_9A,
1264   X86_64_C2,
1265   X86_64_C3,
1266   X86_64_C4,
1267   X86_64_C5,
1268   X86_64_CE,
1269   X86_64_D4,
1270   X86_64_D5,
1271   X86_64_E8,
1272   X86_64_E9,
1273   X86_64_EA,
1274   X86_64_0F01_REG_0,
1275   X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1276   X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1277   X86_64_0F01_REG_1,
1278   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1279   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1280   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1281   X86_64_0F01_REG_2,
1282   X86_64_0F01_REG_3,
1283   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1284   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1285   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1286   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1287   X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1288   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1289   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1290   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1291   X86_64_0F18_REG_6_MOD_0,
1292   X86_64_0F18_REG_7_MOD_0,
1293   X86_64_0F24,
1294   X86_64_0F26,
1295   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1296
1297   X86_64_VEX_0F3849,
1298   X86_64_VEX_0F384B,
1299   X86_64_VEX_0F385C,
1300   X86_64_VEX_0F385E,
1301   X86_64_VEX_0F38E0,
1302   X86_64_VEX_0F38E1,
1303   X86_64_VEX_0F38E2,
1304   X86_64_VEX_0F38E3,
1305   X86_64_VEX_0F38E4,
1306   X86_64_VEX_0F38E5,
1307   X86_64_VEX_0F38E6,
1308   X86_64_VEX_0F38E7,
1309   X86_64_VEX_0F38E8,
1310   X86_64_VEX_0F38E9,
1311   X86_64_VEX_0F38EA,
1312   X86_64_VEX_0F38EB,
1313   X86_64_VEX_0F38EC,
1314   X86_64_VEX_0F38ED,
1315   X86_64_VEX_0F38EE,
1316   X86_64_VEX_0F38EF,
1317 };
1318
1319 enum
1320 {
1321   THREE_BYTE_0F38 = 0,
1322   THREE_BYTE_0F3A
1323 };
1324
1325 enum
1326 {
1327   XOP_08 = 0,
1328   XOP_09,
1329   XOP_0A
1330 };
1331
1332 enum
1333 {
1334   VEX_0F = 0,
1335   VEX_0F38,
1336   VEX_0F3A
1337 };
1338
1339 enum
1340 {
1341   EVEX_0F = 0,
1342   EVEX_0F38,
1343   EVEX_0F3A,
1344   EVEX_MAP5,
1345   EVEX_MAP6,
1346 };
1347
1348 enum
1349 {
1350   VEX_LEN_0F12_P_0_M_0 = 0,
1351   VEX_LEN_0F12_P_0_M_1,
1352 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1353   VEX_LEN_0F13_M_0,
1354   VEX_LEN_0F16_P_0_M_0,
1355   VEX_LEN_0F16_P_0_M_1,
1356 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1357   VEX_LEN_0F17_M_0,
1358   VEX_LEN_0F41,
1359   VEX_LEN_0F42,
1360   VEX_LEN_0F44,
1361   VEX_LEN_0F45,
1362   VEX_LEN_0F46,
1363   VEX_LEN_0F47,
1364   VEX_LEN_0F4A,
1365   VEX_LEN_0F4B,
1366   VEX_LEN_0F6E,
1367   VEX_LEN_0F77,
1368   VEX_LEN_0F7E_P_1,
1369   VEX_LEN_0F7E_P_2,
1370   VEX_LEN_0F90,
1371   VEX_LEN_0F91,
1372   VEX_LEN_0F92,
1373   VEX_LEN_0F93,
1374   VEX_LEN_0F98,
1375   VEX_LEN_0F99,
1376   VEX_LEN_0FAE_R_2_M_0,
1377   VEX_LEN_0FAE_R_3_M_0,
1378   VEX_LEN_0FC4,
1379   VEX_LEN_0FC5,
1380   VEX_LEN_0FD6,
1381   VEX_LEN_0FF7,
1382   VEX_LEN_0F3816,
1383   VEX_LEN_0F3819,
1384   VEX_LEN_0F381A_M_0,
1385   VEX_LEN_0F3836,
1386   VEX_LEN_0F3841,
1387   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1388   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1389   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1390   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1391   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1392   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1393   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1394   VEX_LEN_0F385A_M_0,
1395   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1396   VEX_LEN_0F385C_X86_64_P_3_W_0_M_0,
1397   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1398   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1399   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1400   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1401   VEX_LEN_0F38DB,
1402   VEX_LEN_0F38F2,
1403   VEX_LEN_0F38F3,
1404   VEX_LEN_0F38F5,
1405   VEX_LEN_0F38F6,
1406   VEX_LEN_0F38F7,
1407   VEX_LEN_0F3A00,
1408   VEX_LEN_0F3A01,
1409   VEX_LEN_0F3A06,
1410   VEX_LEN_0F3A14,
1411   VEX_LEN_0F3A15,
1412   VEX_LEN_0F3A16,
1413   VEX_LEN_0F3A17,
1414   VEX_LEN_0F3A18,
1415   VEX_LEN_0F3A19,
1416   VEX_LEN_0F3A20,
1417   VEX_LEN_0F3A21,
1418   VEX_LEN_0F3A22,
1419   VEX_LEN_0F3A30,
1420   VEX_LEN_0F3A31,
1421   VEX_LEN_0F3A32,
1422   VEX_LEN_0F3A33,
1423   VEX_LEN_0F3A38,
1424   VEX_LEN_0F3A39,
1425   VEX_LEN_0F3A41,
1426   VEX_LEN_0F3A46,
1427   VEX_LEN_0F3A60,
1428   VEX_LEN_0F3A61,
1429   VEX_LEN_0F3A62,
1430   VEX_LEN_0F3A63,
1431   VEX_LEN_0F3ADF,
1432   VEX_LEN_0F3AF0,
1433   VEX_LEN_0FXOP_08_85,
1434   VEX_LEN_0FXOP_08_86,
1435   VEX_LEN_0FXOP_08_87,
1436   VEX_LEN_0FXOP_08_8E,
1437   VEX_LEN_0FXOP_08_8F,
1438   VEX_LEN_0FXOP_08_95,
1439   VEX_LEN_0FXOP_08_96,
1440   VEX_LEN_0FXOP_08_97,
1441   VEX_LEN_0FXOP_08_9E,
1442   VEX_LEN_0FXOP_08_9F,
1443   VEX_LEN_0FXOP_08_A3,
1444   VEX_LEN_0FXOP_08_A6,
1445   VEX_LEN_0FXOP_08_B6,
1446   VEX_LEN_0FXOP_08_C0,
1447   VEX_LEN_0FXOP_08_C1,
1448   VEX_LEN_0FXOP_08_C2,
1449   VEX_LEN_0FXOP_08_C3,
1450   VEX_LEN_0FXOP_08_CC,
1451   VEX_LEN_0FXOP_08_CD,
1452   VEX_LEN_0FXOP_08_CE,
1453   VEX_LEN_0FXOP_08_CF,
1454   VEX_LEN_0FXOP_08_EC,
1455   VEX_LEN_0FXOP_08_ED,
1456   VEX_LEN_0FXOP_08_EE,
1457   VEX_LEN_0FXOP_08_EF,
1458   VEX_LEN_0FXOP_09_01,
1459   VEX_LEN_0FXOP_09_02,
1460   VEX_LEN_0FXOP_09_12_M_1,
1461   VEX_LEN_0FXOP_09_82_W_0,
1462   VEX_LEN_0FXOP_09_83_W_0,
1463   VEX_LEN_0FXOP_09_90,
1464   VEX_LEN_0FXOP_09_91,
1465   VEX_LEN_0FXOP_09_92,
1466   VEX_LEN_0FXOP_09_93,
1467   VEX_LEN_0FXOP_09_94,
1468   VEX_LEN_0FXOP_09_95,
1469   VEX_LEN_0FXOP_09_96,
1470   VEX_LEN_0FXOP_09_97,
1471   VEX_LEN_0FXOP_09_98,
1472   VEX_LEN_0FXOP_09_99,
1473   VEX_LEN_0FXOP_09_9A,
1474   VEX_LEN_0FXOP_09_9B,
1475   VEX_LEN_0FXOP_09_C1,
1476   VEX_LEN_0FXOP_09_C2,
1477   VEX_LEN_0FXOP_09_C3,
1478   VEX_LEN_0FXOP_09_C6,
1479   VEX_LEN_0FXOP_09_C7,
1480   VEX_LEN_0FXOP_09_CB,
1481   VEX_LEN_0FXOP_09_D1,
1482   VEX_LEN_0FXOP_09_D2,
1483   VEX_LEN_0FXOP_09_D3,
1484   VEX_LEN_0FXOP_09_D6,
1485   VEX_LEN_0FXOP_09_D7,
1486   VEX_LEN_0FXOP_09_DB,
1487   VEX_LEN_0FXOP_09_E1,
1488   VEX_LEN_0FXOP_09_E2,
1489   VEX_LEN_0FXOP_09_E3,
1490   VEX_LEN_0FXOP_0A_12,
1491 };
1492
1493 enum
1494 {
1495   EVEX_LEN_0F3816 = 0,
1496   EVEX_LEN_0F3819,
1497   EVEX_LEN_0F381A_M_0,
1498   EVEX_LEN_0F381B_M_0,
1499   EVEX_LEN_0F3836,
1500   EVEX_LEN_0F385A_M_0,
1501   EVEX_LEN_0F385B_M_0,
1502   EVEX_LEN_0F38C6_M_0,
1503   EVEX_LEN_0F38C7_M_0,
1504   EVEX_LEN_0F3A00,
1505   EVEX_LEN_0F3A01,
1506   EVEX_LEN_0F3A18,
1507   EVEX_LEN_0F3A19,
1508   EVEX_LEN_0F3A1A,
1509   EVEX_LEN_0F3A1B,
1510   EVEX_LEN_0F3A23,
1511   EVEX_LEN_0F3A38,
1512   EVEX_LEN_0F3A39,
1513   EVEX_LEN_0F3A3A,
1514   EVEX_LEN_0F3A3B,
1515   EVEX_LEN_0F3A43
1516 };
1517
1518 enum
1519 {
1520   VEX_W_0F41_L_1_M_1 = 0,
1521   VEX_W_0F42_L_1_M_1,
1522   VEX_W_0F44_L_0_M_1,
1523   VEX_W_0F45_L_1_M_1,
1524   VEX_W_0F46_L_1_M_1,
1525   VEX_W_0F47_L_1_M_1,
1526   VEX_W_0F4A_L_1_M_1,
1527   VEX_W_0F4B_L_1_M_1,
1528   VEX_W_0F90_L_0,
1529   VEX_W_0F91_L_0_M_0,
1530   VEX_W_0F92_L_0_M_1,
1531   VEX_W_0F93_L_0_M_1,
1532   VEX_W_0F98_L_0_M_1,
1533   VEX_W_0F99_L_0_M_1,
1534   VEX_W_0F380C,
1535   VEX_W_0F380D,
1536   VEX_W_0F380E,
1537   VEX_W_0F380F,
1538   VEX_W_0F3813,
1539   VEX_W_0F3816_L_1,
1540   VEX_W_0F3818,
1541   VEX_W_0F3819_L_1,
1542   VEX_W_0F381A_M_0_L_1,
1543   VEX_W_0F382C_M_0,
1544   VEX_W_0F382D_M_0,
1545   VEX_W_0F382E_M_0,
1546   VEX_W_0F382F_M_0,
1547   VEX_W_0F3836,
1548   VEX_W_0F3846,
1549   VEX_W_0F3849_X86_64_P_0,
1550   VEX_W_0F3849_X86_64_P_2,
1551   VEX_W_0F3849_X86_64_P_3,
1552   VEX_W_0F384B_X86_64_P_1,
1553   VEX_W_0F384B_X86_64_P_2,
1554   VEX_W_0F384B_X86_64_P_3,
1555   VEX_W_0F3850,
1556   VEX_W_0F3851,
1557   VEX_W_0F3852,
1558   VEX_W_0F3853,
1559   VEX_W_0F3858,
1560   VEX_W_0F3859,
1561   VEX_W_0F385A_M_0_L_0,
1562   VEX_W_0F385C_X86_64_P_1,
1563   VEX_W_0F385C_X86_64_P_3,
1564   VEX_W_0F385E_X86_64_P_0,
1565   VEX_W_0F385E_X86_64_P_1,
1566   VEX_W_0F385E_X86_64_P_2,
1567   VEX_W_0F385E_X86_64_P_3,
1568   VEX_W_0F3872_P_1,
1569   VEX_W_0F3878,
1570   VEX_W_0F3879,
1571   VEX_W_0F38B0,
1572   VEX_W_0F38B1,
1573   VEX_W_0F38B4,
1574   VEX_W_0F38B5,
1575   VEX_W_0F38CF,
1576   VEX_W_0F3A00_L_1,
1577   VEX_W_0F3A01_L_1,
1578   VEX_W_0F3A02,
1579   VEX_W_0F3A04,
1580   VEX_W_0F3A05,
1581   VEX_W_0F3A06_L_1,
1582   VEX_W_0F3A18_L_1,
1583   VEX_W_0F3A19_L_1,
1584   VEX_W_0F3A1D,
1585   VEX_W_0F3A38_L_1,
1586   VEX_W_0F3A39_L_1,
1587   VEX_W_0F3A46_L_1,
1588   VEX_W_0F3A4A,
1589   VEX_W_0F3A4B,
1590   VEX_W_0F3A4C,
1591   VEX_W_0F3ACE,
1592   VEX_W_0F3ACF,
1593
1594   VEX_W_0FXOP_08_85_L_0,
1595   VEX_W_0FXOP_08_86_L_0,
1596   VEX_W_0FXOP_08_87_L_0,
1597   VEX_W_0FXOP_08_8E_L_0,
1598   VEX_W_0FXOP_08_8F_L_0,
1599   VEX_W_0FXOP_08_95_L_0,
1600   VEX_W_0FXOP_08_96_L_0,
1601   VEX_W_0FXOP_08_97_L_0,
1602   VEX_W_0FXOP_08_9E_L_0,
1603   VEX_W_0FXOP_08_9F_L_0,
1604   VEX_W_0FXOP_08_A6_L_0,
1605   VEX_W_0FXOP_08_B6_L_0,
1606   VEX_W_0FXOP_08_C0_L_0,
1607   VEX_W_0FXOP_08_C1_L_0,
1608   VEX_W_0FXOP_08_C2_L_0,
1609   VEX_W_0FXOP_08_C3_L_0,
1610   VEX_W_0FXOP_08_CC_L_0,
1611   VEX_W_0FXOP_08_CD_L_0,
1612   VEX_W_0FXOP_08_CE_L_0,
1613   VEX_W_0FXOP_08_CF_L_0,
1614   VEX_W_0FXOP_08_EC_L_0,
1615   VEX_W_0FXOP_08_ED_L_0,
1616   VEX_W_0FXOP_08_EE_L_0,
1617   VEX_W_0FXOP_08_EF_L_0,
1618
1619   VEX_W_0FXOP_09_80,
1620   VEX_W_0FXOP_09_81,
1621   VEX_W_0FXOP_09_82,
1622   VEX_W_0FXOP_09_83,
1623   VEX_W_0FXOP_09_C1_L_0,
1624   VEX_W_0FXOP_09_C2_L_0,
1625   VEX_W_0FXOP_09_C3_L_0,
1626   VEX_W_0FXOP_09_C6_L_0,
1627   VEX_W_0FXOP_09_C7_L_0,
1628   VEX_W_0FXOP_09_CB_L_0,
1629   VEX_W_0FXOP_09_D1_L_0,
1630   VEX_W_0FXOP_09_D2_L_0,
1631   VEX_W_0FXOP_09_D3_L_0,
1632   VEX_W_0FXOP_09_D6_L_0,
1633   VEX_W_0FXOP_09_D7_L_0,
1634   VEX_W_0FXOP_09_DB_L_0,
1635   VEX_W_0FXOP_09_E1_L_0,
1636   VEX_W_0FXOP_09_E2_L_0,
1637   VEX_W_0FXOP_09_E3_L_0,
1638
1639   EVEX_W_0F5B_P_0,
1640   EVEX_W_0F62,
1641   EVEX_W_0F66,
1642   EVEX_W_0F6A,
1643   EVEX_W_0F6B,
1644   EVEX_W_0F6C,
1645   EVEX_W_0F6D,
1646   EVEX_W_0F6F_P_1,
1647   EVEX_W_0F6F_P_2,
1648   EVEX_W_0F6F_P_3,
1649   EVEX_W_0F70_P_2,
1650   EVEX_W_0F72_R_2,
1651   EVEX_W_0F72_R_6,
1652   EVEX_W_0F73_R_2,
1653   EVEX_W_0F73_R_6,
1654   EVEX_W_0F76,
1655   EVEX_W_0F78_P_0,
1656   EVEX_W_0F78_P_2,
1657   EVEX_W_0F79_P_0,
1658   EVEX_W_0F79_P_2,
1659   EVEX_W_0F7A_P_1,
1660   EVEX_W_0F7A_P_2,
1661   EVEX_W_0F7A_P_3,
1662   EVEX_W_0F7B_P_2,
1663   EVEX_W_0F7E_P_1,
1664   EVEX_W_0F7F_P_1,
1665   EVEX_W_0F7F_P_2,
1666   EVEX_W_0F7F_P_3,
1667   EVEX_W_0FD2,
1668   EVEX_W_0FD3,
1669   EVEX_W_0FD4,
1670   EVEX_W_0FD6,
1671   EVEX_W_0FE6_P_1,
1672   EVEX_W_0FE7,
1673   EVEX_W_0FF2,
1674   EVEX_W_0FF3,
1675   EVEX_W_0FF4,
1676   EVEX_W_0FFA,
1677   EVEX_W_0FFB,
1678   EVEX_W_0FFE,
1679
1680   EVEX_W_0F3810_P_1,
1681   EVEX_W_0F3810_P_2,
1682   EVEX_W_0F3811_P_1,
1683   EVEX_W_0F3811_P_2,
1684   EVEX_W_0F3812_P_1,
1685   EVEX_W_0F3812_P_2,
1686   EVEX_W_0F3813_P_1,
1687   EVEX_W_0F3814_P_1,
1688   EVEX_W_0F3815_P_1,
1689   EVEX_W_0F3819_L_n,
1690   EVEX_W_0F381A_M_0_L_n,
1691   EVEX_W_0F381B_M_0_L_2,
1692   EVEX_W_0F381E,
1693   EVEX_W_0F381F,
1694   EVEX_W_0F3820_P_1,
1695   EVEX_W_0F3821_P_1,
1696   EVEX_W_0F3822_P_1,
1697   EVEX_W_0F3823_P_1,
1698   EVEX_W_0F3824_P_1,
1699   EVEX_W_0F3825_P_1,
1700   EVEX_W_0F3825_P_2,
1701   EVEX_W_0F3828_P_2,
1702   EVEX_W_0F3829_P_2,
1703   EVEX_W_0F382A_P_1,
1704   EVEX_W_0F382A_P_2,
1705   EVEX_W_0F382B,
1706   EVEX_W_0F3830_P_1,
1707   EVEX_W_0F3831_P_1,
1708   EVEX_W_0F3832_P_1,
1709   EVEX_W_0F3833_P_1,
1710   EVEX_W_0F3834_P_1,
1711   EVEX_W_0F3835_P_1,
1712   EVEX_W_0F3835_P_2,
1713   EVEX_W_0F3837,
1714   EVEX_W_0F383A_P_1,
1715   EVEX_W_0F3859,
1716   EVEX_W_0F385A_M_0_L_n,
1717   EVEX_W_0F385B_M_0_L_2,
1718   EVEX_W_0F3870,
1719   EVEX_W_0F3872_P_2,
1720   EVEX_W_0F387A,
1721   EVEX_W_0F387B,
1722   EVEX_W_0F3883,
1723
1724   EVEX_W_0F3A18_L_n,
1725   EVEX_W_0F3A19_L_n,
1726   EVEX_W_0F3A1A_L_2,
1727   EVEX_W_0F3A1B_L_2,
1728   EVEX_W_0F3A21,
1729   EVEX_W_0F3A23_L_n,
1730   EVEX_W_0F3A38_L_n,
1731   EVEX_W_0F3A39_L_n,
1732   EVEX_W_0F3A3A_L_2,
1733   EVEX_W_0F3A3B_L_2,
1734   EVEX_W_0F3A42,
1735   EVEX_W_0F3A43_L_n,
1736   EVEX_W_0F3A70,
1737   EVEX_W_0F3A72,
1738
1739   EVEX_W_MAP5_5B_P_0,
1740   EVEX_W_MAP5_7A_P_3,
1741 };
1742
1743 typedef void (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1744
1745 struct dis386 {
1746   const char *name;
1747   struct
1748     {
1749       op_rtn rtn;
1750       int bytemode;
1751     } op[MAX_OPERANDS];
1752   unsigned int prefix_requirement;
1753 };
1754
1755 /* Upper case letters in the instruction names here are macros.
1756    'A' => print 'b' if no register operands or suffix_always is true
1757    'B' => print 'b' if suffix_always is true
1758    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1759           size prefix
1760    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1761           suffix_always is true
1762    'E' => print 'e' if 32-bit form of jcxz
1763    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1764    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1765    'H' => print ",pt" or ",pn" branch hint
1766    'I' unused.
1767    'J' unused.
1768    'K' => print 'd' or 'q' if rex prefix is present.
1769    'L' unused.
1770    'M' => print 'r' if intel_mnemonic is false.
1771    'N' => print 'n' if instruction has no wait "prefix"
1772    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1773    'P' => behave as 'T' except with register operand outside of suffix_always
1774           mode
1775    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1776           is true
1777    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1778    'S' => print 'w', 'l' or 'q' if suffix_always is true
1779    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1780           prefix or if suffix_always is true.
1781    'U' unused.
1782    'V' unused.
1783    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1784    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1785    'Y' unused.
1786    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1787    '!' => change condition from true to false or from false to true.
1788    '%' => add 1 upper case letter to the macro.
1789    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1790           prefix or suffix_always is true (lcall/ljmp).
1791    '@' => in 64bit mode for Intel64 ISA or if instruction
1792           has no operand sizing prefix, print 'q' if suffix_always is true or
1793           nothing otherwise; behave as 'P' in all other cases
1794
1795    2 upper case letter macros:
1796    "XY" => print 'x' or 'y' if suffix_always is true or no register
1797            operands and no broadcast.
1798    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1799            register operands and no broadcast.
1800    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1801    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1802    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1803    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1804    "XV" => print "{vex} " pseudo prefix
1805    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1806            is used by an EVEX-encoded (AVX512VL) instruction.
1807    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1808            being false, or no operand at all in 64bit mode, or if suffix_always
1809            is true.
1810    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1811    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1812    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1813    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1814    "BW" => print 'b' or 'w' depending on the VEX.W bit
1815    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1816            an operand size prefix, or suffix_always is true.  print
1817            'q' if rex prefix is present.
1818
1819    Many of the above letters print nothing in Intel mode.  See "putop"
1820    for the details.
1821
1822    Braces '{' and '}', and vertical bars '|', indicate alternative
1823    mnemonic strings for AT&T and Intel.  */
1824
1825 static const struct dis386 dis386[] = {
1826   /* 00 */
1827   { "addB",             { Ebh1, Gb }, 0 },
1828   { "addS",             { Evh1, Gv }, 0 },
1829   { "addB",             { Gb, EbS }, 0 },
1830   { "addS",             { Gv, EvS }, 0 },
1831   { "addB",             { AL, Ib }, 0 },
1832   { "addS",             { eAX, Iv }, 0 },
1833   { X86_64_TABLE (X86_64_06) },
1834   { X86_64_TABLE (X86_64_07) },
1835   /* 08 */
1836   { "orB",              { Ebh1, Gb }, 0 },
1837   { "orS",              { Evh1, Gv }, 0 },
1838   { "orB",              { Gb, EbS }, 0 },
1839   { "orS",              { Gv, EvS }, 0 },
1840   { "orB",              { AL, Ib }, 0 },
1841   { "orS",              { eAX, Iv }, 0 },
1842   { X86_64_TABLE (X86_64_0E) },
1843   { Bad_Opcode },       /* 0x0f extended opcode escape */
1844   /* 10 */
1845   { "adcB",             { Ebh1, Gb }, 0 },
1846   { "adcS",             { Evh1, Gv }, 0 },
1847   { "adcB",             { Gb, EbS }, 0 },
1848   { "adcS",             { Gv, EvS }, 0 },
1849   { "adcB",             { AL, Ib }, 0 },
1850   { "adcS",             { eAX, Iv }, 0 },
1851   { X86_64_TABLE (X86_64_16) },
1852   { X86_64_TABLE (X86_64_17) },
1853   /* 18 */
1854   { "sbbB",             { Ebh1, Gb }, 0 },
1855   { "sbbS",             { Evh1, Gv }, 0 },
1856   { "sbbB",             { Gb, EbS }, 0 },
1857   { "sbbS",             { Gv, EvS }, 0 },
1858   { "sbbB",             { AL, Ib }, 0 },
1859   { "sbbS",             { eAX, Iv }, 0 },
1860   { X86_64_TABLE (X86_64_1E) },
1861   { X86_64_TABLE (X86_64_1F) },
1862   /* 20 */
1863   { "andB",             { Ebh1, Gb }, 0 },
1864   { "andS",             { Evh1, Gv }, 0 },
1865   { "andB",             { Gb, EbS }, 0 },
1866   { "andS",             { Gv, EvS }, 0 },
1867   { "andB",             { AL, Ib }, 0 },
1868   { "andS",             { eAX, Iv }, 0 },
1869   { Bad_Opcode },       /* SEG ES prefix */
1870   { X86_64_TABLE (X86_64_27) },
1871   /* 28 */
1872   { "subB",             { Ebh1, Gb }, 0 },
1873   { "subS",             { Evh1, Gv }, 0 },
1874   { "subB",             { Gb, EbS }, 0 },
1875   { "subS",             { Gv, EvS }, 0 },
1876   { "subB",             { AL, Ib }, 0 },
1877   { "subS",             { eAX, Iv }, 0 },
1878   { Bad_Opcode },       /* SEG CS prefix */
1879   { X86_64_TABLE (X86_64_2F) },
1880   /* 30 */
1881   { "xorB",             { Ebh1, Gb }, 0 },
1882   { "xorS",             { Evh1, Gv }, 0 },
1883   { "xorB",             { Gb, EbS }, 0 },
1884   { "xorS",             { Gv, EvS }, 0 },
1885   { "xorB",             { AL, Ib }, 0 },
1886   { "xorS",             { eAX, Iv }, 0 },
1887   { Bad_Opcode },       /* SEG SS prefix */
1888   { X86_64_TABLE (X86_64_37) },
1889   /* 38 */
1890   { "cmpB",             { Eb, Gb }, 0 },
1891   { "cmpS",             { Ev, Gv }, 0 },
1892   { "cmpB",             { Gb, EbS }, 0 },
1893   { "cmpS",             { Gv, EvS }, 0 },
1894   { "cmpB",             { AL, Ib }, 0 },
1895   { "cmpS",             { eAX, Iv }, 0 },
1896   { Bad_Opcode },       /* SEG DS prefix */
1897   { X86_64_TABLE (X86_64_3F) },
1898   /* 40 */
1899   { "inc{S|}",          { RMeAX }, 0 },
1900   { "inc{S|}",          { RMeCX }, 0 },
1901   { "inc{S|}",          { RMeDX }, 0 },
1902   { "inc{S|}",          { RMeBX }, 0 },
1903   { "inc{S|}",          { RMeSP }, 0 },
1904   { "inc{S|}",          { RMeBP }, 0 },
1905   { "inc{S|}",          { RMeSI }, 0 },
1906   { "inc{S|}",          { RMeDI }, 0 },
1907   /* 48 */
1908   { "dec{S|}",          { RMeAX }, 0 },
1909   { "dec{S|}",          { RMeCX }, 0 },
1910   { "dec{S|}",          { RMeDX }, 0 },
1911   { "dec{S|}",          { RMeBX }, 0 },
1912   { "dec{S|}",          { RMeSP }, 0 },
1913   { "dec{S|}",          { RMeBP }, 0 },
1914   { "dec{S|}",          { RMeSI }, 0 },
1915   { "dec{S|}",          { RMeDI }, 0 },
1916   /* 50 */
1917   { "push{!P|}",                { RMrAX }, 0 },
1918   { "push{!P|}",                { RMrCX }, 0 },
1919   { "push{!P|}",                { RMrDX }, 0 },
1920   { "push{!P|}",                { RMrBX }, 0 },
1921   { "push{!P|}",                { RMrSP }, 0 },
1922   { "push{!P|}",                { RMrBP }, 0 },
1923   { "push{!P|}",                { RMrSI }, 0 },
1924   { "push{!P|}",                { RMrDI }, 0 },
1925   /* 58 */
1926   { "pop{!P|}",         { RMrAX }, 0 },
1927   { "pop{!P|}",         { RMrCX }, 0 },
1928   { "pop{!P|}",         { RMrDX }, 0 },
1929   { "pop{!P|}",         { RMrBX }, 0 },
1930   { "pop{!P|}",         { RMrSP }, 0 },
1931   { "pop{!P|}",         { RMrBP }, 0 },
1932   { "pop{!P|}",         { RMrSI }, 0 },
1933   { "pop{!P|}",         { RMrDI }, 0 },
1934   /* 60 */
1935   { X86_64_TABLE (X86_64_60) },
1936   { X86_64_TABLE (X86_64_61) },
1937   { X86_64_TABLE (X86_64_62) },
1938   { X86_64_TABLE (X86_64_63) },
1939   { Bad_Opcode },       /* seg fs */
1940   { Bad_Opcode },       /* seg gs */
1941   { Bad_Opcode },       /* op size prefix */
1942   { Bad_Opcode },       /* adr size prefix */
1943   /* 68 */
1944   { "pushP",            { sIv }, 0 },
1945   { "imulS",            { Gv, Ev, Iv }, 0 },
1946   { "pushP",            { sIbT }, 0 },
1947   { "imulS",            { Gv, Ev, sIb }, 0 },
1948   { "ins{b|}",          { Ybr, indirDX }, 0 },
1949   { X86_64_TABLE (X86_64_6D) },
1950   { "outs{b|}",         { indirDXr, Xb }, 0 },
1951   { X86_64_TABLE (X86_64_6F) },
1952   /* 70 */
1953   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1954   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1955   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1956   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1957   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1958   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1959   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1960   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1961   /* 78 */
1962   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1963   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1964   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1965   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1966   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1967   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1968   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1969   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1970   /* 80 */
1971   { REG_TABLE (REG_80) },
1972   { REG_TABLE (REG_81) },
1973   { X86_64_TABLE (X86_64_82) },
1974   { REG_TABLE (REG_83) },
1975   { "testB",            { Eb, Gb }, 0 },
1976   { "testS",            { Ev, Gv }, 0 },
1977   { "xchgB",            { Ebh2, Gb }, 0 },
1978   { "xchgS",            { Evh2, Gv }, 0 },
1979   /* 88 */
1980   { "movB",             { Ebh3, Gb }, 0 },
1981   { "movS",             { Evh3, Gv }, 0 },
1982   { "movB",             { Gb, EbS }, 0 },
1983   { "movS",             { Gv, EvS }, 0 },
1984   { "movD",             { Sv, Sw }, 0 },
1985   { MOD_TABLE (MOD_8D) },
1986   { "movD",             { Sw, Sv }, 0 },
1987   { REG_TABLE (REG_8F) },
1988   /* 90 */
1989   { PREFIX_TABLE (PREFIX_90) },
1990   { "xchgS",            { RMeCX, eAX }, 0 },
1991   { "xchgS",            { RMeDX, eAX }, 0 },
1992   { "xchgS",            { RMeBX, eAX }, 0 },
1993   { "xchgS",            { RMeSP, eAX }, 0 },
1994   { "xchgS",            { RMeBP, eAX }, 0 },
1995   { "xchgS",            { RMeSI, eAX }, 0 },
1996   { "xchgS",            { RMeDI, eAX }, 0 },
1997   /* 98 */
1998   { "cW{t|}R",          { XX }, 0 },
1999   { "cR{t|}O",          { XX }, 0 },
2000   { X86_64_TABLE (X86_64_9A) },
2001   { Bad_Opcode },       /* fwait */
2002   { "pushfP",           { XX }, 0 },
2003   { "popfP",            { XX }, 0 },
2004   { "sahf",             { XX }, 0 },
2005   { "lahf",             { XX }, 0 },
2006   /* a0 */
2007   { "mov%LB",           { AL, Ob }, 0 },
2008   { "mov%LS",           { eAX, Ov }, 0 },
2009   { "mov%LB",           { Ob, AL }, 0 },
2010   { "mov%LS",           { Ov, eAX }, 0 },
2011   { "movs{b|}",         { Ybr, Xb }, 0 },
2012   { "movs{R|}",         { Yvr, Xv }, 0 },
2013   { "cmps{b|}",         { Xb, Yb }, 0 },
2014   { "cmps{R|}",         { Xv, Yv }, 0 },
2015   /* a8 */
2016   { "testB",            { AL, Ib }, 0 },
2017   { "testS",            { eAX, Iv }, 0 },
2018   { "stosB",            { Ybr, AL }, 0 },
2019   { "stosS",            { Yvr, eAX }, 0 },
2020   { "lodsB",            { ALr, Xb }, 0 },
2021   { "lodsS",            { eAXr, Xv }, 0 },
2022   { "scasB",            { AL, Yb }, 0 },
2023   { "scasS",            { eAX, Yv }, 0 },
2024   /* b0 */
2025   { "movB",             { RMAL, Ib }, 0 },
2026   { "movB",             { RMCL, Ib }, 0 },
2027   { "movB",             { RMDL, Ib }, 0 },
2028   { "movB",             { RMBL, Ib }, 0 },
2029   { "movB",             { RMAH, Ib }, 0 },
2030   { "movB",             { RMCH, Ib }, 0 },
2031   { "movB",             { RMDH, Ib }, 0 },
2032   { "movB",             { RMBH, Ib }, 0 },
2033   /* b8 */
2034   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2035   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2036   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2037   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2038   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2039   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2040   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2041   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2042   /* c0 */
2043   { REG_TABLE (REG_C0) },
2044   { REG_TABLE (REG_C1) },
2045   { X86_64_TABLE (X86_64_C2) },
2046   { X86_64_TABLE (X86_64_C3) },
2047   { X86_64_TABLE (X86_64_C4) },
2048   { X86_64_TABLE (X86_64_C5) },
2049   { REG_TABLE (REG_C6) },
2050   { REG_TABLE (REG_C7) },
2051   /* c8 */
2052   { "enterP",           { Iw, Ib }, 0 },
2053   { "leaveP",           { XX }, 0 },
2054   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2055   { "{l|}ret{|f}%LP",   { XX }, 0 },
2056   { "int3",             { XX }, 0 },
2057   { "int",              { Ib }, 0 },
2058   { X86_64_TABLE (X86_64_CE) },
2059   { "iret%LP",          { XX }, 0 },
2060   /* d0 */
2061   { REG_TABLE (REG_D0) },
2062   { REG_TABLE (REG_D1) },
2063   { REG_TABLE (REG_D2) },
2064   { REG_TABLE (REG_D3) },
2065   { X86_64_TABLE (X86_64_D4) },
2066   { X86_64_TABLE (X86_64_D5) },
2067   { Bad_Opcode },
2068   { "xlat",             { DSBX }, 0 },
2069   /* d8 */
2070   { FLOAT },
2071   { FLOAT },
2072   { FLOAT },
2073   { FLOAT },
2074   { FLOAT },
2075   { FLOAT },
2076   { FLOAT },
2077   { FLOAT },
2078   /* e0 */
2079   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2080   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2081   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2082   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2083   { "inB",              { AL, Ib }, 0 },
2084   { "inG",              { zAX, Ib }, 0 },
2085   { "outB",             { Ib, AL }, 0 },
2086   { "outG",             { Ib, zAX }, 0 },
2087   /* e8 */
2088   { X86_64_TABLE (X86_64_E8) },
2089   { X86_64_TABLE (X86_64_E9) },
2090   { X86_64_TABLE (X86_64_EA) },
2091   { "jmp",              { Jb, BND }, 0 },
2092   { "inB",              { AL, indirDX }, 0 },
2093   { "inG",              { zAX, indirDX }, 0 },
2094   { "outB",             { indirDX, AL }, 0 },
2095   { "outG",             { indirDX, zAX }, 0 },
2096   /* f0 */
2097   { Bad_Opcode },       /* lock prefix */
2098   { "int1",             { XX }, 0 },
2099   { Bad_Opcode },       /* repne */
2100   { Bad_Opcode },       /* repz */
2101   { "hlt",              { XX }, 0 },
2102   { "cmc",              { XX }, 0 },
2103   { REG_TABLE (REG_F6) },
2104   { REG_TABLE (REG_F7) },
2105   /* f8 */
2106   { "clc",              { XX }, 0 },
2107   { "stc",              { XX }, 0 },
2108   { "cli",              { XX }, 0 },
2109   { "sti",              { XX }, 0 },
2110   { "cld",              { XX }, 0 },
2111   { "std",              { XX }, 0 },
2112   { REG_TABLE (REG_FE) },
2113   { REG_TABLE (REG_FF) },
2114 };
2115
2116 static const struct dis386 dis386_twobyte[] = {
2117   /* 00 */
2118   { REG_TABLE (REG_0F00 ) },
2119   { REG_TABLE (REG_0F01 ) },
2120   { MOD_TABLE (MOD_0F02) },
2121   { MOD_TABLE (MOD_0F03) },
2122   { Bad_Opcode },
2123   { "syscall",          { XX }, 0 },
2124   { "clts",             { XX }, 0 },
2125   { "sysret%LQ",                { XX }, 0 },
2126   /* 08 */
2127   { "invd",             { XX }, 0 },
2128   { PREFIX_TABLE (PREFIX_0F09) },
2129   { Bad_Opcode },
2130   { "ud2",              { XX }, 0 },
2131   { Bad_Opcode },
2132   { REG_TABLE (REG_0F0D) },
2133   { "femms",            { XX }, 0 },
2134   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2135   /* 10 */
2136   { PREFIX_TABLE (PREFIX_0F10) },
2137   { PREFIX_TABLE (PREFIX_0F11) },
2138   { PREFIX_TABLE (PREFIX_0F12) },
2139   { MOD_TABLE (MOD_0F13) },
2140   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2141   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2142   { PREFIX_TABLE (PREFIX_0F16) },
2143   { MOD_TABLE (MOD_0F17) },
2144   /* 18 */
2145   { REG_TABLE (REG_0F18) },
2146   { "nopQ",             { Ev }, 0 },
2147   { PREFIX_TABLE (PREFIX_0F1A) },
2148   { PREFIX_TABLE (PREFIX_0F1B) },
2149   { PREFIX_TABLE (PREFIX_0F1C) },
2150   { "nopQ",             { Ev }, 0 },
2151   { PREFIX_TABLE (PREFIX_0F1E) },
2152   { "nopQ",             { Ev }, 0 },
2153   /* 20 */
2154   { "movZ",             { Em, Cm }, 0 },
2155   { "movZ",             { Em, Dm }, 0 },
2156   { "movZ",             { Cm, Em }, 0 },
2157   { "movZ",             { Dm, Em }, 0 },
2158   { X86_64_TABLE (X86_64_0F24) },
2159   { Bad_Opcode },
2160   { X86_64_TABLE (X86_64_0F26) },
2161   { Bad_Opcode },
2162   /* 28 */
2163   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2164   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2165   { PREFIX_TABLE (PREFIX_0F2A) },
2166   { PREFIX_TABLE (PREFIX_0F2B) },
2167   { PREFIX_TABLE (PREFIX_0F2C) },
2168   { PREFIX_TABLE (PREFIX_0F2D) },
2169   { PREFIX_TABLE (PREFIX_0F2E) },
2170   { PREFIX_TABLE (PREFIX_0F2F) },
2171   /* 30 */
2172   { "wrmsr",            { XX }, 0 },
2173   { "rdtsc",            { XX }, 0 },
2174   { "rdmsr",            { XX }, 0 },
2175   { "rdpmc",            { XX }, 0 },
2176   { "sysenter",         { SEP }, 0 },
2177   { "sysexit%LQ",       { SEP }, 0 },
2178   { Bad_Opcode },
2179   { "getsec",           { XX }, 0 },
2180   /* 38 */
2181   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2182   { Bad_Opcode },
2183   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2184   { Bad_Opcode },
2185   { Bad_Opcode },
2186   { Bad_Opcode },
2187   { Bad_Opcode },
2188   { Bad_Opcode },
2189   /* 40 */
2190   { "cmovoS",           { Gv, Ev }, 0 },
2191   { "cmovnoS",          { Gv, Ev }, 0 },
2192   { "cmovbS",           { Gv, Ev }, 0 },
2193   { "cmovaeS",          { Gv, Ev }, 0 },
2194   { "cmoveS",           { Gv, Ev }, 0 },
2195   { "cmovneS",          { Gv, Ev }, 0 },
2196   { "cmovbeS",          { Gv, Ev }, 0 },
2197   { "cmovaS",           { Gv, Ev }, 0 },
2198   /* 48 */
2199   { "cmovsS",           { Gv, Ev }, 0 },
2200   { "cmovnsS",          { Gv, Ev }, 0 },
2201   { "cmovpS",           { Gv, Ev }, 0 },
2202   { "cmovnpS",          { Gv, Ev }, 0 },
2203   { "cmovlS",           { Gv, Ev }, 0 },
2204   { "cmovgeS",          { Gv, Ev }, 0 },
2205   { "cmovleS",          { Gv, Ev }, 0 },
2206   { "cmovgS",           { Gv, Ev }, 0 },
2207   /* 50 */
2208   { MOD_TABLE (MOD_0F50) },
2209   { PREFIX_TABLE (PREFIX_0F51) },
2210   { PREFIX_TABLE (PREFIX_0F52) },
2211   { PREFIX_TABLE (PREFIX_0F53) },
2212   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2213   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2214   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2215   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2216   /* 58 */
2217   { PREFIX_TABLE (PREFIX_0F58) },
2218   { PREFIX_TABLE (PREFIX_0F59) },
2219   { PREFIX_TABLE (PREFIX_0F5A) },
2220   { PREFIX_TABLE (PREFIX_0F5B) },
2221   { PREFIX_TABLE (PREFIX_0F5C) },
2222   { PREFIX_TABLE (PREFIX_0F5D) },
2223   { PREFIX_TABLE (PREFIX_0F5E) },
2224   { PREFIX_TABLE (PREFIX_0F5F) },
2225   /* 60 */
2226   { PREFIX_TABLE (PREFIX_0F60) },
2227   { PREFIX_TABLE (PREFIX_0F61) },
2228   { PREFIX_TABLE (PREFIX_0F62) },
2229   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2230   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2231   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2232   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2233   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2234   /* 68 */
2235   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2236   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2237   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2238   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2239   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2240   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2241   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2242   { PREFIX_TABLE (PREFIX_0F6F) },
2243   /* 70 */
2244   { PREFIX_TABLE (PREFIX_0F70) },
2245   { MOD_TABLE (MOD_0F71) },
2246   { MOD_TABLE (MOD_0F72) },
2247   { MOD_TABLE (MOD_0F73) },
2248   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2249   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2250   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2251   { "emms",             { XX }, PREFIX_OPCODE },
2252   /* 78 */
2253   { PREFIX_TABLE (PREFIX_0F78) },
2254   { PREFIX_TABLE (PREFIX_0F79) },
2255   { Bad_Opcode },
2256   { Bad_Opcode },
2257   { PREFIX_TABLE (PREFIX_0F7C) },
2258   { PREFIX_TABLE (PREFIX_0F7D) },
2259   { PREFIX_TABLE (PREFIX_0F7E) },
2260   { PREFIX_TABLE (PREFIX_0F7F) },
2261   /* 80 */
2262   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2263   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2264   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2265   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2266   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2267   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2268   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2269   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2270   /* 88 */
2271   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2272   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2273   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2274   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2275   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2276   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2277   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2278   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2279   /* 90 */
2280   { "seto",             { Eb }, 0 },
2281   { "setno",            { Eb }, 0 },
2282   { "setb",             { Eb }, 0 },
2283   { "setae",            { Eb }, 0 },
2284   { "sete",             { Eb }, 0 },
2285   { "setne",            { Eb }, 0 },
2286   { "setbe",            { Eb }, 0 },
2287   { "seta",             { Eb }, 0 },
2288   /* 98 */
2289   { "sets",             { Eb }, 0 },
2290   { "setns",            { Eb }, 0 },
2291   { "setp",             { Eb }, 0 },
2292   { "setnp",            { Eb }, 0 },
2293   { "setl",             { Eb }, 0 },
2294   { "setge",            { Eb }, 0 },
2295   { "setle",            { Eb }, 0 },
2296   { "setg",             { Eb }, 0 },
2297   /* a0 */
2298   { "pushP",            { fs }, 0 },
2299   { "popP",             { fs }, 0 },
2300   { "cpuid",            { XX }, 0 },
2301   { "btS",              { Ev, Gv }, 0 },
2302   { "shldS",            { Ev, Gv, Ib }, 0 },
2303   { "shldS",            { Ev, Gv, CL }, 0 },
2304   { REG_TABLE (REG_0FA6) },
2305   { REG_TABLE (REG_0FA7) },
2306   /* a8 */
2307   { "pushP",            { gs }, 0 },
2308   { "popP",             { gs }, 0 },
2309   { "rsm",              { XX }, 0 },
2310   { "btsS",             { Evh1, Gv }, 0 },
2311   { "shrdS",            { Ev, Gv, Ib }, 0 },
2312   { "shrdS",            { Ev, Gv, CL }, 0 },
2313   { REG_TABLE (REG_0FAE) },
2314   { "imulS",            { Gv, Ev }, 0 },
2315   /* b0 */
2316   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2317   { "cmpxchgS",         { Evh1, Gv }, 0 },
2318   { MOD_TABLE (MOD_0FB2) },
2319   { "btrS",             { Evh1, Gv }, 0 },
2320   { MOD_TABLE (MOD_0FB4) },
2321   { MOD_TABLE (MOD_0FB5) },
2322   { "movz{bR|x}",       { Gv, Eb }, 0 },
2323   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2324   /* b8 */
2325   { PREFIX_TABLE (PREFIX_0FB8) },
2326   { "ud1S",             { Gv, Ev }, 0 },
2327   { REG_TABLE (REG_0FBA) },
2328   { "btcS",             { Evh1, Gv }, 0 },
2329   { PREFIX_TABLE (PREFIX_0FBC) },
2330   { PREFIX_TABLE (PREFIX_0FBD) },
2331   { "movs{bR|x}",       { Gv, Eb }, 0 },
2332   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2333   /* c0 */
2334   { "xaddB",            { Ebh1, Gb }, 0 },
2335   { "xaddS",            { Evh1, Gv }, 0 },
2336   { PREFIX_TABLE (PREFIX_0FC2) },
2337   { MOD_TABLE (MOD_0FC3) },
2338   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2339   { "pextrw",           { Gd, MS, Ib }, PREFIX_OPCODE },
2340   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2341   { REG_TABLE (REG_0FC7) },
2342   /* c8 */
2343   { "bswap",            { RMeAX }, 0 },
2344   { "bswap",            { RMeCX }, 0 },
2345   { "bswap",            { RMeDX }, 0 },
2346   { "bswap",            { RMeBX }, 0 },
2347   { "bswap",            { RMeSP }, 0 },
2348   { "bswap",            { RMeBP }, 0 },
2349   { "bswap",            { RMeSI }, 0 },
2350   { "bswap",            { RMeDI }, 0 },
2351   /* d0 */
2352   { PREFIX_TABLE (PREFIX_0FD0) },
2353   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2354   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2355   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2356   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2357   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2358   { PREFIX_TABLE (PREFIX_0FD6) },
2359   { MOD_TABLE (MOD_0FD7) },
2360   /* d8 */
2361   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2362   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2363   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2364   { "pand",             { MX, EM }, PREFIX_OPCODE },
2365   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2366   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2367   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2368   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2369   /* e0 */
2370   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2371   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2372   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2373   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2374   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2375   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2376   { PREFIX_TABLE (PREFIX_0FE6) },
2377   { PREFIX_TABLE (PREFIX_0FE7) },
2378   /* e8 */
2379   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2380   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2381   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2382   { "por",              { MX, EM }, PREFIX_OPCODE },
2383   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2384   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2385   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2386   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2387   /* f0 */
2388   { PREFIX_TABLE (PREFIX_0FF0) },
2389   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2390   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2391   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2392   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2393   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2394   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2395   { PREFIX_TABLE (PREFIX_0FF7) },
2396   /* f8 */
2397   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2398   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2399   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2400   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2401   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2402   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2403   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2404   { "ud0S",             { Gv, Ev }, 0 },
2405 };
2406
2407 static const bool onebyte_has_modrm[256] = {
2408   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2409   /*       -------------------------------        */
2410   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2411   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2412   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2413   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2414   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2415   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2416   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2417   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2418   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2419   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2420   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2421   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2422   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2423   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2424   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2425   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2426   /*       -------------------------------        */
2427   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2428 };
2429
2430 static const bool twobyte_has_modrm[256] = {
2431   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2432   /*       -------------------------------        */
2433   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2434   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2435   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2436   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2437   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2438   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2439   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2440   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2441   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2442   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2443   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2444   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2445   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2446   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2447   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2448   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2449   /*       -------------------------------        */
2450   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2451 };
2452
2453
2454 struct op
2455   {
2456     const char *name;
2457     unsigned int len;
2458   };
2459
2460 /* If we are accessing mod/rm/reg without need_modrm set, then the
2461    values are stale.  Hitting this abort likely indicates that you
2462    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2463 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2464
2465 static const char *const intel_index16[] = {
2466   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2467 };
2468
2469 static const char *const att_names64[] = {
2470   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2471   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2472 };
2473 static const char *const att_names32[] = {
2474   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2475   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2476 };
2477 static const char *const att_names16[] = {
2478   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2479   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2480 };
2481 static const char *const att_names8[] = {
2482   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2483 };
2484 static const char *const att_names8rex[] = {
2485   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2486   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2487 };
2488 static const char *const att_names_seg[] = {
2489   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2490 };
2491 static const char att_index64[] = "%riz";
2492 static const char att_index32[] = "%eiz";
2493 static const char *const att_index16[] = {
2494   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2495 };
2496
2497 static const char *const att_names_mm[] = {
2498   "%mm0", "%mm1", "%mm2", "%mm3",
2499   "%mm4", "%mm5", "%mm6", "%mm7"
2500 };
2501
2502 static const char *const att_names_bnd[] = {
2503   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2504 };
2505
2506 static const char *const att_names_xmm[] = {
2507   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2508   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2509   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2510   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2511   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2512   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2513   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2514   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2515 };
2516
2517 static const char *const att_names_ymm[] = {
2518   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2519   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2520   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2521   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2522   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2523   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2524   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2525   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2526 };
2527
2528 static const char *const att_names_zmm[] = {
2529   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2530   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2531   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2532   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2533   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2534   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2535   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2536   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2537 };
2538
2539 static const char *const att_names_tmm[] = {
2540   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2541   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2542 };
2543
2544 static const char *const att_names_mask[] = {
2545   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2546 };
2547
2548 static const char *const names_rounding[] =
2549 {
2550   "{rn-",
2551   "{rd-",
2552   "{ru-",
2553   "{rz-"
2554 };
2555
2556 static const struct dis386 reg_table[][8] = {
2557   /* REG_80 */
2558   {
2559     { "addA",   { Ebh1, Ib }, 0 },
2560     { "orA",    { Ebh1, Ib }, 0 },
2561     { "adcA",   { Ebh1, Ib }, 0 },
2562     { "sbbA",   { Ebh1, Ib }, 0 },
2563     { "andA",   { Ebh1, Ib }, 0 },
2564     { "subA",   { Ebh1, Ib }, 0 },
2565     { "xorA",   { Ebh1, Ib }, 0 },
2566     { "cmpA",   { Eb, Ib }, 0 },
2567   },
2568   /* REG_81 */
2569   {
2570     { "addQ",   { Evh1, Iv }, 0 },
2571     { "orQ",    { Evh1, Iv }, 0 },
2572     { "adcQ",   { Evh1, Iv }, 0 },
2573     { "sbbQ",   { Evh1, Iv }, 0 },
2574     { "andQ",   { Evh1, Iv }, 0 },
2575     { "subQ",   { Evh1, Iv }, 0 },
2576     { "xorQ",   { Evh1, Iv }, 0 },
2577     { "cmpQ",   { Ev, Iv }, 0 },
2578   },
2579   /* REG_83 */
2580   {
2581     { "addQ",   { Evh1, sIb }, 0 },
2582     { "orQ",    { Evh1, sIb }, 0 },
2583     { "adcQ",   { Evh1, sIb }, 0 },
2584     { "sbbQ",   { Evh1, sIb }, 0 },
2585     { "andQ",   { Evh1, sIb }, 0 },
2586     { "subQ",   { Evh1, sIb }, 0 },
2587     { "xorQ",   { Evh1, sIb }, 0 },
2588     { "cmpQ",   { Ev, sIb }, 0 },
2589   },
2590   /* REG_8F */
2591   {
2592     { "pop{P|}", { stackEv }, 0 },
2593     { XOP_8F_TABLE (XOP_09) },
2594     { Bad_Opcode },
2595     { Bad_Opcode },
2596     { Bad_Opcode },
2597     { XOP_8F_TABLE (XOP_09) },
2598   },
2599   /* REG_C0 */
2600   {
2601     { "rolA",   { Eb, Ib }, 0 },
2602     { "rorA",   { Eb, Ib }, 0 },
2603     { "rclA",   { Eb, Ib }, 0 },
2604     { "rcrA",   { Eb, Ib }, 0 },
2605     { "shlA",   { Eb, Ib }, 0 },
2606     { "shrA",   { Eb, Ib }, 0 },
2607     { "shlA",   { Eb, Ib }, 0 },
2608     { "sarA",   { Eb, Ib }, 0 },
2609   },
2610   /* REG_C1 */
2611   {
2612     { "rolQ",   { Ev, Ib }, 0 },
2613     { "rorQ",   { Ev, Ib }, 0 },
2614     { "rclQ",   { Ev, Ib }, 0 },
2615     { "rcrQ",   { Ev, Ib }, 0 },
2616     { "shlQ",   { Ev, Ib }, 0 },
2617     { "shrQ",   { Ev, Ib }, 0 },
2618     { "shlQ",   { Ev, Ib }, 0 },
2619     { "sarQ",   { Ev, Ib }, 0 },
2620   },
2621   /* REG_C6 */
2622   {
2623     { "movA",   { Ebh3, Ib }, 0 },
2624     { Bad_Opcode },
2625     { Bad_Opcode },
2626     { Bad_Opcode },
2627     { Bad_Opcode },
2628     { Bad_Opcode },
2629     { Bad_Opcode },
2630     { MOD_TABLE (MOD_C6_REG_7) },
2631   },
2632   /* REG_C7 */
2633   {
2634     { "movQ",   { Evh3, Iv }, 0 },
2635     { Bad_Opcode },
2636     { Bad_Opcode },
2637     { Bad_Opcode },
2638     { Bad_Opcode },
2639     { Bad_Opcode },
2640     { Bad_Opcode },
2641     { MOD_TABLE (MOD_C7_REG_7) },
2642   },
2643   /* REG_D0 */
2644   {
2645     { "rolA",   { Eb, I1 }, 0 },
2646     { "rorA",   { Eb, I1 }, 0 },
2647     { "rclA",   { Eb, I1 }, 0 },
2648     { "rcrA",   { Eb, I1 }, 0 },
2649     { "shlA",   { Eb, I1 }, 0 },
2650     { "shrA",   { Eb, I1 }, 0 },
2651     { "shlA",   { Eb, I1 }, 0 },
2652     { "sarA",   { Eb, I1 }, 0 },
2653   },
2654   /* REG_D1 */
2655   {
2656     { "rolQ",   { Ev, I1 }, 0 },
2657     { "rorQ",   { Ev, I1 }, 0 },
2658     { "rclQ",   { Ev, I1 }, 0 },
2659     { "rcrQ",   { Ev, I1 }, 0 },
2660     { "shlQ",   { Ev, I1 }, 0 },
2661     { "shrQ",   { Ev, I1 }, 0 },
2662     { "shlQ",   { Ev, I1 }, 0 },
2663     { "sarQ",   { Ev, I1 }, 0 },
2664   },
2665   /* REG_D2 */
2666   {
2667     { "rolA",   { Eb, CL }, 0 },
2668     { "rorA",   { Eb, CL }, 0 },
2669     { "rclA",   { Eb, CL }, 0 },
2670     { "rcrA",   { Eb, CL }, 0 },
2671     { "shlA",   { Eb, CL }, 0 },
2672     { "shrA",   { Eb, CL }, 0 },
2673     { "shlA",   { Eb, CL }, 0 },
2674     { "sarA",   { Eb, CL }, 0 },
2675   },
2676   /* REG_D3 */
2677   {
2678     { "rolQ",   { Ev, CL }, 0 },
2679     { "rorQ",   { Ev, CL }, 0 },
2680     { "rclQ",   { Ev, CL }, 0 },
2681     { "rcrQ",   { Ev, CL }, 0 },
2682     { "shlQ",   { Ev, CL }, 0 },
2683     { "shrQ",   { Ev, CL }, 0 },
2684     { "shlQ",   { Ev, CL }, 0 },
2685     { "sarQ",   { Ev, CL }, 0 },
2686   },
2687   /* REG_F6 */
2688   {
2689     { "testA",  { Eb, Ib }, 0 },
2690     { "testA",  { Eb, Ib }, 0 },
2691     { "notA",   { Ebh1 }, 0 },
2692     { "negA",   { Ebh1 }, 0 },
2693     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2694     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2695     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2696     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2697   },
2698   /* REG_F7 */
2699   {
2700     { "testQ",  { Ev, Iv }, 0 },
2701     { "testQ",  { Ev, Iv }, 0 },
2702     { "notQ",   { Evh1 }, 0 },
2703     { "negQ",   { Evh1 }, 0 },
2704     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2705     { "imulQ",  { Ev }, 0 },
2706     { "divQ",   { Ev }, 0 },
2707     { "idivQ",  { Ev }, 0 },
2708   },
2709   /* REG_FE */
2710   {
2711     { "incA",   { Ebh1 }, 0 },
2712     { "decA",   { Ebh1 }, 0 },
2713   },
2714   /* REG_FF */
2715   {
2716     { "incQ",   { Evh1 }, 0 },
2717     { "decQ",   { Evh1 }, 0 },
2718     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2719     { MOD_TABLE (MOD_FF_REG_3) },
2720     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2721     { MOD_TABLE (MOD_FF_REG_5) },
2722     { "push{P|}", { stackEv }, 0 },
2723     { Bad_Opcode },
2724   },
2725   /* REG_0F00 */
2726   {
2727     { "sldtD",  { Sv }, 0 },
2728     { "strD",   { Sv }, 0 },
2729     { "lldt",   { Ew }, 0 },
2730     { "ltr",    { Ew }, 0 },
2731     { "verr",   { Ew }, 0 },
2732     { "verw",   { Ew }, 0 },
2733     { Bad_Opcode },
2734     { Bad_Opcode },
2735   },
2736   /* REG_0F01 */
2737   {
2738     { MOD_TABLE (MOD_0F01_REG_0) },
2739     { MOD_TABLE (MOD_0F01_REG_1) },
2740     { MOD_TABLE (MOD_0F01_REG_2) },
2741     { MOD_TABLE (MOD_0F01_REG_3) },
2742     { "smswD",  { Sv }, 0 },
2743     { MOD_TABLE (MOD_0F01_REG_5) },
2744     { "lmsw",   { Ew }, 0 },
2745     { MOD_TABLE (MOD_0F01_REG_7) },
2746   },
2747   /* REG_0F0D */
2748   {
2749     { "prefetch",       { Mb }, 0 },
2750     { "prefetchw",      { Mb }, 0 },
2751     { "prefetchwt1",    { Mb }, 0 },
2752     { "prefetch",       { Mb }, 0 },
2753     { "prefetch",       { Mb }, 0 },
2754     { "prefetch",       { Mb }, 0 },
2755     { "prefetch",       { Mb }, 0 },
2756     { "prefetch",       { Mb }, 0 },
2757   },
2758   /* REG_0F18 */
2759   {
2760     { MOD_TABLE (MOD_0F18_REG_0) },
2761     { MOD_TABLE (MOD_0F18_REG_1) },
2762     { MOD_TABLE (MOD_0F18_REG_2) },
2763     { MOD_TABLE (MOD_0F18_REG_3) },
2764     { "nopQ",           { Ev }, 0 },
2765     { "nopQ",           { Ev }, 0 },
2766     { MOD_TABLE (MOD_0F18_REG_6) },
2767     { MOD_TABLE (MOD_0F18_REG_7) },
2768   },
2769   /* REG_0F1C_P_0_MOD_0 */
2770   {
2771     { "cldemote",       { Mb }, 0 },
2772     { "nopQ",           { Ev }, 0 },
2773     { "nopQ",           { Ev }, 0 },
2774     { "nopQ",           { Ev }, 0 },
2775     { "nopQ",           { Ev }, 0 },
2776     { "nopQ",           { Ev }, 0 },
2777     { "nopQ",           { Ev }, 0 },
2778     { "nopQ",           { Ev }, 0 },
2779   },
2780   /* REG_0F1E_P_1_MOD_3 */
2781   {
2782     { "nopQ",           { Ev }, PREFIX_IGNORED },
2783     { "rdsspK",         { Edq }, 0 },
2784     { "nopQ",           { Ev }, PREFIX_IGNORED },
2785     { "nopQ",           { Ev }, PREFIX_IGNORED },
2786     { "nopQ",           { Ev }, PREFIX_IGNORED },
2787     { "nopQ",           { Ev }, PREFIX_IGNORED },
2788     { "nopQ",           { Ev }, PREFIX_IGNORED },
2789     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2790   },
2791   /* REG_0F38D8_PREFIX_1 */
2792   {
2793     { "aesencwide128kl",        { M }, 0 },
2794     { "aesdecwide128kl",        { M }, 0 },
2795     { "aesencwide256kl",        { M }, 0 },
2796     { "aesdecwide256kl",        { M }, 0 },
2797   },
2798   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2799   {
2800     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2801   },
2802   /* REG_0F71_MOD_0 */
2803   {
2804     { Bad_Opcode },
2805     { Bad_Opcode },
2806     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
2807     { Bad_Opcode },
2808     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
2809     { Bad_Opcode },
2810     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
2811   },
2812   /* REG_0F72_MOD_0 */
2813   {
2814     { Bad_Opcode },
2815     { Bad_Opcode },
2816     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
2817     { Bad_Opcode },
2818     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
2819     { Bad_Opcode },
2820     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
2821   },
2822   /* REG_0F73_MOD_0 */
2823   {
2824     { Bad_Opcode },
2825     { Bad_Opcode },
2826     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
2827     { "psrldq",         { XS, Ib }, PREFIX_DATA },
2828     { Bad_Opcode },
2829     { Bad_Opcode },
2830     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
2831     { "pslldq",         { XS, Ib }, PREFIX_DATA },
2832   },
2833   /* REG_0FA6 */
2834   {
2835     { "montmul",        { { OP_0f07, 0 } }, 0 },
2836     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2837     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2838   },
2839   /* REG_0FA7 */
2840   {
2841     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2842     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2843     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2844     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2845     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2846     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2847   },
2848   /* REG_0FAE */
2849   {
2850     { MOD_TABLE (MOD_0FAE_REG_0) },
2851     { MOD_TABLE (MOD_0FAE_REG_1) },
2852     { MOD_TABLE (MOD_0FAE_REG_2) },
2853     { MOD_TABLE (MOD_0FAE_REG_3) },
2854     { MOD_TABLE (MOD_0FAE_REG_4) },
2855     { MOD_TABLE (MOD_0FAE_REG_5) },
2856     { MOD_TABLE (MOD_0FAE_REG_6) },
2857     { MOD_TABLE (MOD_0FAE_REG_7) },
2858   },
2859   /* REG_0FBA */
2860   {
2861     { Bad_Opcode },
2862     { Bad_Opcode },
2863     { Bad_Opcode },
2864     { Bad_Opcode },
2865     { "btQ",    { Ev, Ib }, 0 },
2866     { "btsQ",   { Evh1, Ib }, 0 },
2867     { "btrQ",   { Evh1, Ib }, 0 },
2868     { "btcQ",   { Evh1, Ib }, 0 },
2869   },
2870   /* REG_0FC7 */
2871   {
2872     { Bad_Opcode },
2873     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2874     { Bad_Opcode },
2875     { MOD_TABLE (MOD_0FC7_REG_3) },
2876     { MOD_TABLE (MOD_0FC7_REG_4) },
2877     { MOD_TABLE (MOD_0FC7_REG_5) },
2878     { MOD_TABLE (MOD_0FC7_REG_6) },
2879     { MOD_TABLE (MOD_0FC7_REG_7) },
2880   },
2881   /* REG_VEX_0F71_M_0 */
2882   {
2883     { Bad_Opcode },
2884     { Bad_Opcode },
2885     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
2886     { Bad_Opcode },
2887     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
2888     { Bad_Opcode },
2889     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
2890   },
2891   /* REG_VEX_0F72_M_0 */
2892   {
2893     { Bad_Opcode },
2894     { Bad_Opcode },
2895     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
2896     { Bad_Opcode },
2897     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
2898     { Bad_Opcode },
2899     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
2900   },
2901   /* REG_VEX_0F73_M_0 */
2902   {
2903     { Bad_Opcode },
2904     { Bad_Opcode },
2905     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
2906     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
2907     { Bad_Opcode },
2908     { Bad_Opcode },
2909     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
2910     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
2911   },
2912   /* REG_VEX_0FAE */
2913   {
2914     { Bad_Opcode },
2915     { Bad_Opcode },
2916     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2917     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2918   },
2919   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2920   {
2921     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2922   },
2923   /* REG_VEX_0F38F3_L_0 */
2924   {
2925     { Bad_Opcode },
2926     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
2927     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
2928     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
2929   },
2930   /* REG_XOP_09_01_L_0 */
2931   {
2932     { Bad_Opcode },
2933     { "blcfill",        { VexGdq, Edq }, 0 },
2934     { "blsfill",        { VexGdq, Edq }, 0 },
2935     { "blcs",   { VexGdq, Edq }, 0 },
2936     { "tzmsk",  { VexGdq, Edq }, 0 },
2937     { "blcic",  { VexGdq, Edq }, 0 },
2938     { "blsic",  { VexGdq, Edq }, 0 },
2939     { "t1mskc", { VexGdq, Edq }, 0 },
2940   },
2941   /* REG_XOP_09_02_L_0 */
2942   {
2943     { Bad_Opcode },
2944     { "blcmsk", { VexGdq, Edq }, 0 },
2945     { Bad_Opcode },
2946     { Bad_Opcode },
2947     { Bad_Opcode },
2948     { Bad_Opcode },
2949     { "blci",   { VexGdq, Edq }, 0 },
2950   },
2951   /* REG_XOP_09_12_M_1_L_0 */
2952   {
2953     { "llwpcb", { Edq }, 0 },
2954     { "slwpcb", { Edq }, 0 },
2955   },
2956   /* REG_XOP_0A_12_L_0 */
2957   {
2958     { "lwpins", { VexGdq, Ed, Id }, 0 },
2959     { "lwpval", { VexGdq, Ed, Id }, 0 },
2960   },
2961
2962 #include "i386-dis-evex-reg.h"
2963 };
2964
2965 static const struct dis386 prefix_table[][4] = {
2966   /* PREFIX_90 */
2967   {
2968     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2969     { "pause", { XX }, 0 },
2970     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2971     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2972   },
2973
2974   /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
2975   {
2976     { "wrmsrns",        { Skip_MODRM }, 0 },
2977     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
2978     { Bad_Opcode },
2979     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
2980   },
2981
2982   /* PREFIX_0F01_REG_1_RM_4 */
2983   {
2984     { Bad_Opcode },
2985     { Bad_Opcode },
2986     { "tdcall",         { Skip_MODRM }, 0 },
2987     { Bad_Opcode },
2988   },
2989
2990   /* PREFIX_0F01_REG_1_RM_5 */
2991   {
2992     { Bad_Opcode },
2993     { Bad_Opcode },
2994     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2995     { Bad_Opcode },
2996   },
2997
2998   /* PREFIX_0F01_REG_1_RM_6 */
2999   {
3000     { Bad_Opcode },
3001     { Bad_Opcode },
3002     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3003     { Bad_Opcode },
3004   },
3005
3006   /* PREFIX_0F01_REG_1_RM_7 */
3007   {
3008     { "encls",          { Skip_MODRM }, 0 },
3009     { Bad_Opcode },
3010     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3011     { Bad_Opcode },
3012   },
3013
3014   /* PREFIX_0F01_REG_3_RM_1 */
3015   {
3016     { "vmmcall",        { Skip_MODRM }, 0 },
3017     { "vmgexit",        { Skip_MODRM }, 0 },
3018     { Bad_Opcode },
3019     { "vmgexit",        { Skip_MODRM }, 0 },
3020   },
3021
3022   /* PREFIX_0F01_REG_5_MOD_0 */
3023   {
3024     { Bad_Opcode },
3025     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3026   },
3027
3028   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3029   {
3030     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3031     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3032     { Bad_Opcode },
3033     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3034   },
3035
3036   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3037   {
3038     { Bad_Opcode },
3039     { Bad_Opcode },
3040     { Bad_Opcode },
3041     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3042   },
3043
3044   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3045   {
3046     { Bad_Opcode },
3047     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3048   },
3049
3050   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3051   {
3052     { Bad_Opcode },
3053     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3054   },
3055
3056   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3057   {
3058     { Bad_Opcode },
3059     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3060   },
3061
3062   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3063   {
3064     { "rdpkru", { Skip_MODRM }, 0 },
3065     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3066   },
3067
3068   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3069   {
3070     { "wrpkru", { Skip_MODRM }, 0 },
3071     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3072   },
3073
3074   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3075   {
3076     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3077     { "mcommit",        { Skip_MODRM }, 0 },
3078   },
3079
3080   /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3081   {
3082     { "rdpru", { Skip_MODRM }, 0 },
3083     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3084   },
3085
3086   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3087   {
3088     { "invlpgb",        { Skip_MODRM }, 0 },
3089     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3090     { Bad_Opcode },
3091     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3092   },
3093
3094   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3095   {
3096     { "tlbsync",        { Skip_MODRM }, 0 },
3097     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3098     { Bad_Opcode },
3099     { "pvalidate",      { Skip_MODRM }, 0 },
3100   },
3101
3102   /* PREFIX_0F09 */
3103   {
3104     { "wbinvd",   { XX }, 0 },
3105     { "wbnoinvd", { XX }, 0 },
3106   },
3107
3108   /* PREFIX_0F10 */
3109   {
3110     { "movups", { XM, EXx }, PREFIX_OPCODE },
3111     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3112     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3113     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3114   },
3115
3116   /* PREFIX_0F11 */
3117   {
3118     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3119     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3120     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3121     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3122   },
3123
3124   /* PREFIX_0F12 */
3125   {
3126     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3127     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3128     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3129     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3130   },
3131
3132   /* PREFIX_0F16 */
3133   {
3134     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3135     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3136     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3137   },
3138
3139   /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3140   {
3141     { "prefetchit1",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3142     { "nopQ",           { Ev }, 0 },
3143     { "nopQ",           { Ev }, 0 },
3144     { "nopQ",           { Ev }, 0 },
3145   },
3146
3147   /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3148   {
3149     { "prefetchit0",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3150     { "nopQ",           { Ev }, 0 },
3151     { "nopQ",           { Ev }, 0 },
3152     { "nopQ",           { Ev }, 0 },
3153   },
3154
3155   /* PREFIX_0F1A */
3156   {
3157     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3158     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3159     { "bndmov", { Gbnd, Ebnd }, 0 },
3160     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3161   },
3162
3163   /* PREFIX_0F1B */
3164   {
3165     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3166     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3167     { "bndmov", { EbndS, Gbnd }, 0 },
3168     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3169   },
3170
3171   /* PREFIX_0F1C */
3172   {
3173     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3174     { "nopQ",   { Ev }, PREFIX_IGNORED },
3175     { "nopQ",   { Ev }, 0 },
3176     { "nopQ",   { Ev }, PREFIX_IGNORED },
3177   },
3178
3179   /* PREFIX_0F1E */
3180   {
3181     { "nopQ",   { Ev }, 0 },
3182     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3183     { "nopQ",   { Ev }, 0 },
3184     { NULL,     { XX }, PREFIX_IGNORED },
3185   },
3186
3187   /* PREFIX_0F2A */
3188   {
3189     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3190     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3191     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3192     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3193   },
3194
3195   /* PREFIX_0F2B */
3196   {
3197     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3198     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3199     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3200     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3201   },
3202
3203   /* PREFIX_0F2C */
3204   {
3205     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3206     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3207     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3208     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3209   },
3210
3211   /* PREFIX_0F2D */
3212   {
3213     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3214     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3215     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3216     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3217   },
3218
3219   /* PREFIX_0F2E */
3220   {
3221     { "ucomiss",{ XM, EXd }, 0 },
3222     { Bad_Opcode },
3223     { "ucomisd",{ XM, EXq }, 0 },
3224   },
3225
3226   /* PREFIX_0F2F */
3227   {
3228     { "comiss", { XM, EXd }, 0 },
3229     { Bad_Opcode },
3230     { "comisd", { XM, EXq }, 0 },
3231   },
3232
3233   /* PREFIX_0F51 */
3234   {
3235     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3236     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3237     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3238     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3239   },
3240
3241   /* PREFIX_0F52 */
3242   {
3243     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3244     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3245   },
3246
3247   /* PREFIX_0F53 */
3248   {
3249     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3250     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3251   },
3252
3253   /* PREFIX_0F58 */
3254   {
3255     { "addps", { XM, EXx }, PREFIX_OPCODE },
3256     { "addss", { XM, EXd }, PREFIX_OPCODE },
3257     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3258     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3259   },
3260
3261   /* PREFIX_0F59 */
3262   {
3263     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3264     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3265     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3266     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3267   },
3268
3269   /* PREFIX_0F5A */
3270   {
3271     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3272     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3273     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3274     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3275   },
3276
3277   /* PREFIX_0F5B */
3278   {
3279     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3280     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3281     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3282   },
3283
3284   /* PREFIX_0F5C */
3285   {
3286     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3287     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3288     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3289     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3290   },
3291
3292   /* PREFIX_0F5D */
3293   {
3294     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3295     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3296     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3297     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3298   },
3299
3300   /* PREFIX_0F5E */
3301   {
3302     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3303     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3304     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3305     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3306   },
3307
3308   /* PREFIX_0F5F */
3309   {
3310     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3311     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3312     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3313     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3314   },
3315
3316   /* PREFIX_0F60 */
3317   {
3318     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3319     { Bad_Opcode },
3320     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3321   },
3322
3323   /* PREFIX_0F61 */
3324   {
3325     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3326     { Bad_Opcode },
3327     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3328   },
3329
3330   /* PREFIX_0F62 */
3331   {
3332     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3333     { Bad_Opcode },
3334     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3335   },
3336
3337   /* PREFIX_0F6F */
3338   {
3339     { "movq",   { MX, EM }, PREFIX_OPCODE },
3340     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3341     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3342   },
3343
3344   /* PREFIX_0F70 */
3345   {
3346     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3347     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3348     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3349     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3350   },
3351
3352   /* PREFIX_0F78 */
3353   {
3354     {"vmread",  { Em, Gm }, 0 },
3355     { Bad_Opcode },
3356     {"extrq",   { XS, Ib, Ib }, 0 },
3357     {"insertq", { XM, XS, Ib, Ib }, 0 },
3358   },
3359
3360   /* PREFIX_0F79 */
3361   {
3362     {"vmwrite", { Gm, Em }, 0 },
3363     { Bad_Opcode },
3364     {"extrq",   { XM, XS }, 0 },
3365     {"insertq", { XM, XS }, 0 },
3366   },
3367
3368   /* PREFIX_0F7C */
3369   {
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3373     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3374   },
3375
3376   /* PREFIX_0F7D */
3377   {
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3381     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3382   },
3383
3384   /* PREFIX_0F7E */
3385   {
3386     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3387     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3388     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3389   },
3390
3391   /* PREFIX_0F7F */
3392   {
3393     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3394     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3395     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3396   },
3397
3398   /* PREFIX_0FAE_REG_0_MOD_3 */
3399   {
3400     { Bad_Opcode },
3401     { "rdfsbase", { Ev }, 0 },
3402   },
3403
3404   /* PREFIX_0FAE_REG_1_MOD_3 */
3405   {
3406     { Bad_Opcode },
3407     { "rdgsbase", { Ev }, 0 },
3408   },
3409
3410   /* PREFIX_0FAE_REG_2_MOD_3 */
3411   {
3412     { Bad_Opcode },
3413     { "wrfsbase", { Ev }, 0 },
3414   },
3415
3416   /* PREFIX_0FAE_REG_3_MOD_3 */
3417   {
3418     { Bad_Opcode },
3419     { "wrgsbase", { Ev }, 0 },
3420   },
3421
3422   /* PREFIX_0FAE_REG_4_MOD_0 */
3423   {
3424     { "xsave",  { FXSAVE }, 0 },
3425     { "ptwrite{%LQ|}", { Edq }, 0 },
3426   },
3427
3428   /* PREFIX_0FAE_REG_4_MOD_3 */
3429   {
3430     { Bad_Opcode },
3431     { "ptwrite{%LQ|}", { Edq }, 0 },
3432   },
3433
3434   /* PREFIX_0FAE_REG_5_MOD_3 */
3435   {
3436     { "lfence",         { Skip_MODRM }, 0 },
3437     { "incsspK",        { Edq }, PREFIX_OPCODE },
3438   },
3439
3440   /* PREFIX_0FAE_REG_6_MOD_0 */
3441   {
3442     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3443     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3444     { "clwb",   { Mb }, PREFIX_OPCODE },
3445   },
3446
3447   /* PREFIX_0FAE_REG_6_MOD_3 */
3448   {
3449     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3450     { "umonitor",       { Eva }, PREFIX_OPCODE },
3451     { "tpause", { Edq }, PREFIX_OPCODE },
3452     { "umwait", { Edq }, PREFIX_OPCODE },
3453   },
3454
3455   /* PREFIX_0FAE_REG_7_MOD_0 */
3456   {
3457     { "clflush",        { Mb }, 0 },
3458     { Bad_Opcode },
3459     { "clflushopt",     { Mb }, 0 },
3460   },
3461
3462   /* PREFIX_0FB8 */
3463   {
3464     { Bad_Opcode },
3465     { "popcntS", { Gv, Ev }, 0 },
3466   },
3467
3468   /* PREFIX_0FBC */
3469   {
3470     { "bsfS",   { Gv, Ev }, 0 },
3471     { "tzcntS", { Gv, Ev }, 0 },
3472     { "bsfS",   { Gv, Ev }, 0 },
3473   },
3474
3475   /* PREFIX_0FBD */
3476   {
3477     { "bsrS",   { Gv, Ev }, 0 },
3478     { "lzcntS", { Gv, Ev }, 0 },
3479     { "bsrS",   { Gv, Ev }, 0 },
3480   },
3481
3482   /* PREFIX_0FC2 */
3483   {
3484     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3485     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3486     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3487     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3488   },
3489
3490   /* PREFIX_0FC7_REG_6_MOD_0 */
3491   {
3492     { "vmptrld",{ Mq }, 0 },
3493     { "vmxon",  { Mq }, 0 },
3494     { "vmclear",{ Mq }, 0 },
3495   },
3496
3497   /* PREFIX_0FC7_REG_6_MOD_3 */
3498   {
3499     { "rdrand", { Ev }, 0 },
3500     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3501     { "rdrand", { Ev }, 0 }
3502   },
3503
3504   /* PREFIX_0FC7_REG_7_MOD_3 */
3505   {
3506     { "rdseed", { Ev }, 0 },
3507     { "rdpid",  { Em }, 0 },
3508     { "rdseed", { Ev }, 0 },
3509   },
3510
3511   /* PREFIX_0FD0 */
3512   {
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { "addsubpd", { XM, EXx }, 0 },
3516     { "addsubps", { XM, EXx }, 0 },
3517   },
3518
3519   /* PREFIX_0FD6 */
3520   {
3521     { Bad_Opcode },
3522     { "movq2dq",{ XM, MS }, 0 },
3523     { "movq",   { EXqS, XM }, 0 },
3524     { "movdq2q",{ MX, XS }, 0 },
3525   },
3526
3527   /* PREFIX_0FE6 */
3528   {
3529     { Bad_Opcode },
3530     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3531     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3532     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3533   },
3534
3535   /* PREFIX_0FE7 */
3536   {
3537     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3538     { Bad_Opcode },
3539     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3540   },
3541
3542   /* PREFIX_0FF0 */
3543   {
3544     { Bad_Opcode },
3545     { Bad_Opcode },
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3548   },
3549
3550   /* PREFIX_0FF7 */
3551   {
3552     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3553     { Bad_Opcode },
3554     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3555   },
3556
3557   /* PREFIX_0F38D8 */
3558   {
3559     { Bad_Opcode },
3560     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3561   },
3562
3563   /* PREFIX_0F38DC */
3564   {
3565     { Bad_Opcode },
3566     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3567     { "aesenc", { XM, EXx }, 0 },
3568   },
3569
3570   /* PREFIX_0F38DD */
3571   {
3572     { Bad_Opcode },
3573     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3574     { "aesenclast", { XM, EXx }, 0 },
3575   },
3576
3577   /* PREFIX_0F38DE */
3578   {
3579     { Bad_Opcode },
3580     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3581     { "aesdec", { XM, EXx }, 0 },
3582   },
3583
3584   /* PREFIX_0F38DF */
3585   {
3586     { Bad_Opcode },
3587     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3588     { "aesdeclast", { XM, EXx }, 0 },
3589   },
3590
3591   /* PREFIX_0F38F0 */
3592   {
3593     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3594     { Bad_Opcode },
3595     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3596     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3597   },
3598
3599   /* PREFIX_0F38F1 */
3600   {
3601     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3602     { Bad_Opcode },
3603     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3604     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3605   },
3606
3607   /* PREFIX_0F38F6 */
3608   {
3609     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3610     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3611     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3612     { Bad_Opcode },
3613   },
3614
3615   /* PREFIX_0F38F8 */
3616   {
3617     { Bad_Opcode },
3618     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3619     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3620     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3621   },
3622   /* PREFIX_0F38FA */
3623   {
3624     { Bad_Opcode },
3625     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3626   },
3627
3628   /* PREFIX_0F38FB */
3629   {
3630     { Bad_Opcode },
3631     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3632   },
3633
3634   /* PREFIX_0F38FC */
3635   {
3636     { "aadd",   { Mdq, Gdq }, 0 },
3637     { "axor",   { Mdq, Gdq }, 0 },
3638     { "aand",   { Mdq, Gdq }, 0 },
3639     { "aor",    { Mdq, Gdq }, 0 },
3640   },
3641
3642   /* PREFIX_0F3A0F */
3643   {
3644     { Bad_Opcode },
3645     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3646   },
3647
3648   /* PREFIX_VEX_0F10 */
3649   {
3650     { "%XEvmovupX",     { XM, EXEvexXNoBcst }, 0 },
3651     { "%XEvmovs%XS",    { XMScalar, VexScalarR, EXd }, 0 },
3652     { "%XEvmovupX",     { XM, EXEvexXNoBcst }, 0 },
3653     { "%XEvmovs%XD",    { XMScalar, VexScalarR, EXq }, 0 },
3654   },
3655
3656   /* PREFIX_VEX_0F11 */
3657   {
3658     { "%XEvmovupX",     { EXxS, XM }, 0 },
3659     { "%XEvmovs%XS",    { EXdS, VexScalarR, XMScalar }, 0 },
3660     { "%XEvmovupX",     { EXxS, XM }, 0 },
3661     { "%XEvmovs%XD",    { EXqS, VexScalarR, XMScalar }, 0 },
3662   },
3663
3664   /* PREFIX_VEX_0F12 */
3665   {
3666     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3667     { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3668     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3669     { "%XEvmov%XDdup",  { XM, EXymmq }, 0 },
3670   },
3671
3672   /* PREFIX_VEX_0F16 */
3673   {
3674     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3675     { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3676     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3677   },
3678
3679   /* PREFIX_VEX_0F2A */
3680   {
3681     { Bad_Opcode },
3682     { "%XEvcvtsi2ss{%LQ|}",     { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3683     { Bad_Opcode },
3684     { "%XEvcvtsi2sd{%LQ|}",     { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3685   },
3686
3687   /* PREFIX_VEX_0F2C */
3688   {
3689     { Bad_Opcode },
3690     { "%XEvcvttss2si",  { Gdq, EXd, EXxEVexS }, 0 },
3691     { Bad_Opcode },
3692     { "%XEvcvttsd2si",  { Gdq, EXq, EXxEVexS }, 0 },
3693   },
3694
3695   /* PREFIX_VEX_0F2D */
3696   {
3697     { Bad_Opcode },
3698     { "%XEvcvtss2si",   { Gdq, EXd, EXxEVexR }, 0 },
3699     { Bad_Opcode },
3700     { "%XEvcvtsd2si",   { Gdq, EXq, EXxEVexR }, 0 },
3701   },
3702
3703   /* PREFIX_VEX_0F2E */
3704   {
3705     { "%XEvucomisX",    { XMScalar, EXd, EXxEVexS }, 0 },
3706     { Bad_Opcode },
3707     { "%XEvucomisX",    { XMScalar, EXq, EXxEVexS }, 0 },
3708   },
3709
3710   /* PREFIX_VEX_0F2F */
3711   {
3712     { "%XEvcomisX",     { XMScalar, EXd, EXxEVexS }, 0 },
3713     { Bad_Opcode },
3714     { "%XEvcomisX",     { XMScalar, EXq, EXxEVexS }, 0 },
3715   },
3716
3717   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3718   {
3719     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3720     { Bad_Opcode },
3721     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3722   },
3723
3724   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3725   {
3726     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3727     { Bad_Opcode },
3728     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3729   },
3730
3731   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3732   {
3733     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3734     { Bad_Opcode },
3735     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3736   },
3737
3738   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3739   {
3740     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3741     { Bad_Opcode },
3742     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3743   },
3744
3745   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3746   {
3747     { "knotw",          { MaskG, MaskE }, 0 },
3748     { Bad_Opcode },
3749     { "knotb",          { MaskG, MaskE }, 0 },
3750   },
3751
3752   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3753   {
3754     { "knotq",          { MaskG, MaskE }, 0 },
3755     { Bad_Opcode },
3756     { "knotd",          { MaskG, MaskE }, 0 },
3757   },
3758
3759   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3760   {
3761     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3762     { Bad_Opcode },
3763     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3764   },
3765
3766   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3767   {
3768     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3769     { Bad_Opcode },
3770     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3771   },
3772
3773   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3774   {
3775     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3776     { Bad_Opcode },
3777     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3778   },
3779
3780   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3781   {
3782     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3783     { Bad_Opcode },
3784     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3785   },
3786
3787   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3788   {
3789     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3790     { Bad_Opcode },
3791     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3792   },
3793
3794   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3795   {
3796     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3797     { Bad_Opcode },
3798     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3799   },
3800
3801   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3802   {
3803     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3804     { Bad_Opcode },
3805     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3806   },
3807
3808   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3809   {
3810     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3811     { Bad_Opcode },
3812     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3813   },
3814
3815   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3816   {
3817     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3818     { Bad_Opcode },
3819     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3820   },
3821
3822   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3823   {
3824     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3825   },
3826
3827   /* PREFIX_VEX_0F51 */
3828   {
3829     { "%XEvsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3830     { "%XEvsqrts%XS",   { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3831     { "%XEvsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3832     { "%XEvsqrts%XD",   { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3833   },
3834
3835   /* PREFIX_VEX_0F52 */
3836   {
3837     { "vrsqrtps",       { XM, EXx }, 0 },
3838     { "vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3839   },
3840
3841   /* PREFIX_VEX_0F53 */
3842   {
3843     { "vrcpps",         { XM, EXx }, 0 },
3844     { "vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3845   },
3846
3847   /* PREFIX_VEX_0F58 */
3848   {
3849     { "%XEvaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3850     { "%XEvadds%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3851     { "%XEvaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3852     { "%XEvadds%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3853   },
3854
3855   /* PREFIX_VEX_0F59 */
3856   {
3857     { "%XEvmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3858     { "%XEvmuls%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3859     { "%XEvmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3860     { "%XEvmuls%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3861   },
3862
3863   /* PREFIX_VEX_0F5A */
3864   {
3865     { "%XEvcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3866     { "%XEvcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3867     { "%XEvcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3868     { "%XEvcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3869   },
3870
3871   /* PREFIX_VEX_0F5B */
3872   {
3873     { "vcvtdq2ps",      { XM, EXx }, 0 },
3874     { "vcvttps2dq",     { XM, EXx }, 0 },
3875     { "vcvtps2dq",      { XM, EXx }, 0 },
3876   },
3877
3878   /* PREFIX_VEX_0F5C */
3879   {
3880     { "%XEvsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3881     { "%XEvsubs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3882     { "%XEvsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3883     { "%XEvsubs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3884   },
3885
3886   /* PREFIX_VEX_0F5D */
3887   {
3888     { "%XEvminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3889     { "%XEvmins%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3890     { "%XEvminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3891     { "%XEvmins%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3892   },
3893
3894   /* PREFIX_VEX_0F5E */
3895   {
3896     { "%XEvdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3897     { "%XEvdivs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3898     { "%XEvdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3899     { "%XEvdivs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3900   },
3901
3902   /* PREFIX_VEX_0F5F */
3903   {
3904     { "%XEvmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3905     { "%XEvmaxs%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3906     { "%XEvmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3907     { "%XEvmaxs%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3908   },
3909
3910   /* PREFIX_VEX_0F6F */
3911   {
3912     { Bad_Opcode },
3913     { "vmovdqu",        { XM, EXx }, 0 },
3914     { "vmovdqa",        { XM, EXx }, 0 },
3915   },
3916
3917   /* PREFIX_VEX_0F70 */
3918   {
3919     { Bad_Opcode },
3920     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3921     { "vpshufd",        { XM, EXx, Ib }, 0 },
3922     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3923   },
3924
3925   /* PREFIX_VEX_0F7C */
3926   {
3927     { Bad_Opcode },
3928     { Bad_Opcode },
3929     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3930     { "vhaddps",        { XM, Vex, EXx }, 0 },
3931   },
3932
3933   /* PREFIX_VEX_0F7D */
3934   {
3935     { Bad_Opcode },
3936     { Bad_Opcode },
3937     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3938     { "vhsubps",        { XM, Vex, EXx }, 0 },
3939   },
3940
3941   /* PREFIX_VEX_0F7E */
3942   {
3943     { Bad_Opcode },
3944     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3945     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3946   },
3947
3948   /* PREFIX_VEX_0F7F */
3949   {
3950     { Bad_Opcode },
3951     { "vmovdqu",        { EXxS, XM }, 0 },
3952     { "vmovdqa",        { EXxS, XM }, 0 },
3953   },
3954
3955   /* PREFIX_VEX_0F90_L_0_W_0 */
3956   {
3957     { "kmovw",          { MaskG, MaskE }, 0 },
3958     { Bad_Opcode },
3959     { "kmovb",          { MaskG, MaskBDE }, 0 },
3960   },
3961
3962   /* PREFIX_VEX_0F90_L_0_W_1 */
3963   {
3964     { "kmovq",          { MaskG, MaskE }, 0 },
3965     { Bad_Opcode },
3966     { "kmovd",          { MaskG, MaskBDE }, 0 },
3967   },
3968
3969   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3970   {
3971     { "kmovw",          { Ew, MaskG }, 0 },
3972     { Bad_Opcode },
3973     { "kmovb",          { Eb, MaskG }, 0 },
3974   },
3975
3976   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3977   {
3978     { "kmovq",          { Eq, MaskG }, 0 },
3979     { Bad_Opcode },
3980     { "kmovd",          { Ed, MaskG }, 0 },
3981   },
3982
3983   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3984   {
3985     { "kmovw",          { MaskG, Edq }, 0 },
3986     { Bad_Opcode },
3987     { "kmovb",          { MaskG, Edq }, 0 },
3988     { "kmovd",          { MaskG, Edq }, 0 },
3989   },
3990
3991   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3992   {
3993     { Bad_Opcode },
3994     { Bad_Opcode },
3995     { Bad_Opcode },
3996     { "kmovK",          { MaskG, Edq }, 0 },
3997   },
3998
3999   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
4000   {
4001     { "kmovw",          { Gdq, MaskE }, 0 },
4002     { Bad_Opcode },
4003     { "kmovb",          { Gdq, MaskE }, 0 },
4004     { "kmovd",          { Gdq, MaskE }, 0 },
4005   },
4006
4007   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
4008   {
4009     { Bad_Opcode },
4010     { Bad_Opcode },
4011     { Bad_Opcode },
4012     { "kmovK",          { Gdq, MaskE }, 0 },
4013   },
4014
4015   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
4016   {
4017     { "kortestw", { MaskG, MaskE }, 0 },
4018     { Bad_Opcode },
4019     { "kortestb", { MaskG, MaskE }, 0 },
4020   },
4021
4022   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4023   {
4024     { "kortestq", { MaskG, MaskE }, 0 },
4025     { Bad_Opcode },
4026     { "kortestd", { MaskG, MaskE }, 0 },
4027   },
4028
4029   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4030   {
4031     { "ktestw", { MaskG, MaskE }, 0 },
4032     { Bad_Opcode },
4033     { "ktestb", { MaskG, MaskE }, 0 },
4034   },
4035
4036   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4037   {
4038     { "ktestq", { MaskG, MaskE }, 0 },
4039     { Bad_Opcode },
4040     { "ktestd", { MaskG, MaskE }, 0 },
4041   },
4042
4043   /* PREFIX_VEX_0FC2 */
4044   {
4045     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
4046     { "vcmpss",         { XMScalar, VexScalar, EXd, CMP }, 0 },
4047     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
4048     { "vcmpsd",         { XMScalar, VexScalar, EXq, CMP }, 0 },
4049   },
4050
4051   /* PREFIX_VEX_0FD0 */
4052   {
4053     { Bad_Opcode },
4054     { Bad_Opcode },
4055     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
4056     { "vaddsubps",      { XM, Vex, EXx }, 0 },
4057   },
4058
4059   /* PREFIX_VEX_0FE6 */
4060   {
4061     { Bad_Opcode },
4062     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
4063     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
4064     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
4065   },
4066
4067   /* PREFIX_VEX_0FF0 */
4068   {
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { Bad_Opcode },
4072     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4073   },
4074
4075   /* PREFIX_VEX_0F3849_X86_64 */
4076   {
4077     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4078     { Bad_Opcode },
4079     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4080     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4081   },
4082
4083   /* PREFIX_VEX_0F384B_X86_64 */
4084   {
4085     { Bad_Opcode },
4086     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4087     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4088     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4089   },
4090
4091   /* PREFIX_VEX_0F3850_W_0 */
4092   {
4093     { "vpdpbuud",       { XM, Vex, EXx }, 0 },
4094     { "vpdpbsud",       { XM, Vex, EXx }, 0 },
4095     { "%XVvpdpbusd",    { XM, Vex, EXx }, 0 },
4096     { "vpdpbssd",       { XM, Vex, EXx }, 0 },
4097   },
4098
4099   /* PREFIX_VEX_0F3851_W_0 */
4100   {
4101     { "vpdpbuuds",      { XM, Vex, EXx }, 0 },
4102     { "vpdpbsuds",      { XM, Vex, EXx }, 0 },
4103     { "%XVvpdpbusds",   { XM, Vex, EXx }, 0 },
4104     { "vpdpbssds",      { XM, Vex, EXx }, 0 },
4105   },
4106   /* PREFIX_VEX_0F385C_X86_64 */
4107   {
4108     { Bad_Opcode },
4109     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4110     { Bad_Opcode },
4111     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_3) },
4112   },
4113
4114   /* PREFIX_VEX_0F385E_X86_64 */
4115   {
4116     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4117     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4118     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4119     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4120   },
4121
4122   /* PREFIX_VEX_0F3872 */
4123   {
4124     { Bad_Opcode },
4125     { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4126   },
4127
4128   /* PREFIX_VEX_0F38B0_W_0 */
4129   {
4130     { "vcvtneoph2ps", { XM, Mx }, 0 },
4131     { "vcvtneebf162ps", { XM, Mx }, 0 },
4132     { "vcvtneeph2ps", { XM, Mx }, 0 },
4133     { "vcvtneobf162ps", { XM, Mx }, 0 },
4134   },
4135
4136   /* PREFIX_VEX_0F38B1_W_0 */
4137   {
4138     { Bad_Opcode },
4139     { "vbcstnebf162ps", { XM, Mw }, 0 },
4140     { "vbcstnesh2ps", { XM, Mw }, 0 },
4141   },
4142
4143   /* PREFIX_VEX_0F38F5_L_0 */
4144   {
4145     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4146     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4147     { Bad_Opcode },
4148     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4149   },
4150
4151   /* PREFIX_VEX_0F38F6_L_0 */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4157   },
4158
4159   /* PREFIX_VEX_0F38F7_L_0 */
4160   {
4161     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4162     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4163     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4164     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4165   },
4166
4167   /* PREFIX_VEX_0F3AF0_L_0 */
4168   {
4169     { Bad_Opcode },
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4173   },
4174
4175 #include "i386-dis-evex-prefix.h"
4176 };
4177
4178 static const struct dis386 x86_64_table[][2] = {
4179   /* X86_64_06 */
4180   {
4181     { "pushP", { es }, 0 },
4182   },
4183
4184   /* X86_64_07 */
4185   {
4186     { "popP", { es }, 0 },
4187   },
4188
4189   /* X86_64_0E */
4190   {
4191     { "pushP", { cs }, 0 },
4192   },
4193
4194   /* X86_64_16 */
4195   {
4196     { "pushP", { ss }, 0 },
4197   },
4198
4199   /* X86_64_17 */
4200   {
4201     { "popP", { ss }, 0 },
4202   },
4203
4204   /* X86_64_1E */
4205   {
4206     { "pushP", { ds }, 0 },
4207   },
4208
4209   /* X86_64_1F */
4210   {
4211     { "popP", { ds }, 0 },
4212   },
4213
4214   /* X86_64_27 */
4215   {
4216     { "daa", { XX }, 0 },
4217   },
4218
4219   /* X86_64_2F */
4220   {
4221     { "das", { XX }, 0 },
4222   },
4223
4224   /* X86_64_37 */
4225   {
4226     { "aaa", { XX }, 0 },
4227   },
4228
4229   /* X86_64_3F */
4230   {
4231     { "aas", { XX }, 0 },
4232   },
4233
4234   /* X86_64_60 */
4235   {
4236     { "pushaP", { XX }, 0 },
4237   },
4238
4239   /* X86_64_61 */
4240   {
4241     { "popaP", { XX }, 0 },
4242   },
4243
4244   /* X86_64_62 */
4245   {
4246     { MOD_TABLE (MOD_62_32BIT) },
4247     { EVEX_TABLE (EVEX_0F) },
4248   },
4249
4250   /* X86_64_63 */
4251   {
4252     { "arpl", { Ew, Gw }, 0 },
4253     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4254   },
4255
4256   /* X86_64_6D */
4257   {
4258     { "ins{R|}", { Yzr, indirDX }, 0 },
4259     { "ins{G|}", { Yzr, indirDX }, 0 },
4260   },
4261
4262   /* X86_64_6F */
4263   {
4264     { "outs{R|}", { indirDXr, Xz }, 0 },
4265     { "outs{G|}", { indirDXr, Xz }, 0 },
4266   },
4267
4268   /* X86_64_82 */
4269   {
4270     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4271     { REG_TABLE (REG_80) },
4272   },
4273
4274   /* X86_64_9A */
4275   {
4276     { "{l|}call{P|}", { Ap }, 0 },
4277   },
4278
4279   /* X86_64_C2 */
4280   {
4281     { "retP",           { Iw, BND }, 0 },
4282     { "ret@",           { Iw, BND }, 0 },
4283   },
4284
4285   /* X86_64_C3 */
4286   {
4287     { "retP",           { BND }, 0 },
4288     { "ret@",           { BND }, 0 },
4289   },
4290
4291   /* X86_64_C4 */
4292   {
4293     { MOD_TABLE (MOD_C4_32BIT) },
4294     { VEX_C4_TABLE (VEX_0F) },
4295   },
4296
4297   /* X86_64_C5 */
4298   {
4299     { MOD_TABLE (MOD_C5_32BIT) },
4300     { VEX_C5_TABLE (VEX_0F) },
4301   },
4302
4303   /* X86_64_CE */
4304   {
4305     { "into", { XX }, 0 },
4306   },
4307
4308   /* X86_64_D4 */
4309   {
4310     { "aam", { Ib }, 0 },
4311   },
4312
4313   /* X86_64_D5 */
4314   {
4315     { "aad", { Ib }, 0 },
4316   },
4317
4318   /* X86_64_E8 */
4319   {
4320     { "callP",          { Jv, BND }, 0 },
4321     { "call@",          { Jv, BND }, 0 }
4322   },
4323
4324   /* X86_64_E9 */
4325   {
4326     { "jmpP",           { Jv, BND }, 0 },
4327     { "jmp@",           { Jv, BND }, 0 }
4328   },
4329
4330   /* X86_64_EA */
4331   {
4332     { "{l|}jmp{P|}", { Ap }, 0 },
4333   },
4334
4335   /* X86_64_0F01_REG_0 */
4336   {
4337     { "sgdt{Q|Q}", { M }, 0 },
4338     { "sgdt", { M }, 0 },
4339   },
4340
4341   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4342   {
4343     { Bad_Opcode },
4344     { "wrmsrlist",      { Skip_MODRM }, 0 },
4345   },
4346
4347   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4348   {
4349     { Bad_Opcode },
4350     { "rdmsrlist",      { Skip_MODRM }, 0 },
4351   },
4352
4353   /* X86_64_0F01_REG_1 */
4354   {
4355     { "sidt{Q|Q}", { M }, 0 },
4356     { "sidt", { M }, 0 },
4357   },
4358
4359   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4360   {
4361     { Bad_Opcode },
4362     { "seamret",        { Skip_MODRM }, 0 },
4363   },
4364
4365   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4366   {
4367     { Bad_Opcode },
4368     { "seamops",        { Skip_MODRM }, 0 },
4369   },
4370
4371   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4372   {
4373     { Bad_Opcode },
4374     { "seamcall",       { Skip_MODRM }, 0 },
4375   },
4376
4377   /* X86_64_0F01_REG_2 */
4378   {
4379     { "lgdt{Q|Q}", { M }, 0 },
4380     { "lgdt", { M }, 0 },
4381   },
4382
4383   /* X86_64_0F01_REG_3 */
4384   {
4385     { "lidt{Q|Q}", { M }, 0 },
4386     { "lidt", { M }, 0 },
4387   },
4388
4389   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4390   {
4391     { Bad_Opcode },
4392     { "uiret",  { Skip_MODRM }, 0 },
4393   },
4394
4395   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4396   {
4397     { Bad_Opcode },
4398     { "testui", { Skip_MODRM }, 0 },
4399   },
4400
4401   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4402   {
4403     { Bad_Opcode },
4404     { "clui",   { Skip_MODRM }, 0 },
4405   },
4406
4407   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4408   {
4409     { Bad_Opcode },
4410     { "stui",   { Skip_MODRM }, 0 },
4411   },
4412
4413   /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4414   {
4415     { Bad_Opcode },
4416     { "rmpquery", { Skip_MODRM }, 0 },
4417   },
4418
4419   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4420   {
4421     { Bad_Opcode },
4422     { "rmpadjust",      { Skip_MODRM }, 0 },
4423   },
4424
4425   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4426   {
4427     { Bad_Opcode },
4428     { "rmpupdate",      { Skip_MODRM }, 0 },
4429   },
4430
4431   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4432   {
4433     { Bad_Opcode },
4434     { "psmash", { Skip_MODRM }, 0 },
4435   },
4436
4437   /* X86_64_0F18_REG_6_MOD_0 */
4438   {
4439     { "nopQ",           { Ev }, 0 },
4440     { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4441   },
4442
4443   /* X86_64_0F18_REG_7_MOD_0 */
4444   {
4445     { "nopQ",           { Ev }, 0 },
4446     { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4447   },
4448
4449   {
4450     /* X86_64_0F24 */
4451     { "movZ",           { Em, Td }, 0 },
4452   },
4453
4454   {
4455     /* X86_64_0F26 */
4456     { "movZ",           { Td, Em }, 0 },
4457   },
4458
4459   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4460   {
4461     { Bad_Opcode },
4462     { "senduipi",       { Eq }, 0 },
4463   },
4464
4465   /* X86_64_VEX_0F3849 */
4466   {
4467     { Bad_Opcode },
4468     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4469   },
4470
4471   /* X86_64_VEX_0F384B */
4472   {
4473     { Bad_Opcode },
4474     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4475   },
4476
4477   /* X86_64_VEX_0F385C */
4478   {
4479     { Bad_Opcode },
4480     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4481   },
4482
4483   /* X86_64_VEX_0F385E */
4484   {
4485     { Bad_Opcode },
4486     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4487   },
4488
4489   /* X86_64_VEX_0F38E0 */
4490   {
4491     { Bad_Opcode },
4492     { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4493   },
4494
4495   /* X86_64_VEX_0F38E1 */
4496   {
4497     { Bad_Opcode },
4498     { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4499   },
4500
4501   /* X86_64_VEX_0F38E2 */
4502   {
4503     { Bad_Opcode },
4504     { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4505   },
4506
4507   /* X86_64_VEX_0F38E3 */
4508   {
4509     { Bad_Opcode },
4510     { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4511   },
4512
4513   /* X86_64_VEX_0F38E4 */
4514   {
4515     { Bad_Opcode },
4516     { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4517   },
4518
4519   /* X86_64_VEX_0F38E5 */
4520   {
4521     { Bad_Opcode },
4522     { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4523   },
4524
4525   /* X86_64_VEX_0F38E6 */
4526   {
4527     { Bad_Opcode },
4528     { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4529   },
4530
4531   /* X86_64_VEX_0F38E7 */
4532   {
4533     { Bad_Opcode },
4534     { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4535   },
4536
4537   /* X86_64_VEX_0F38E8 */
4538   {
4539     { Bad_Opcode },
4540     { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4541   },
4542
4543   /* X86_64_VEX_0F38E9 */
4544   {
4545     { Bad_Opcode },
4546     { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4547   },
4548
4549   /* X86_64_VEX_0F38EA */
4550   {
4551     { Bad_Opcode },
4552     { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4553   },
4554
4555   /* X86_64_VEX_0F38EB */
4556   {
4557     { Bad_Opcode },
4558     { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4559   },
4560
4561   /* X86_64_VEX_0F38EC */
4562   {
4563     { Bad_Opcode },
4564     { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4565   },
4566
4567   /* X86_64_VEX_0F38ED */
4568   {
4569     { Bad_Opcode },
4570     { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4571   },
4572
4573   /* X86_64_VEX_0F38EE */
4574   {
4575     { Bad_Opcode },
4576     { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4577   },
4578
4579   /* X86_64_VEX_0F38EF */
4580   {
4581     { Bad_Opcode },
4582     { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4583   },
4584 };
4585
4586 static const struct dis386 three_byte_table[][256] = {
4587
4588   /* THREE_BYTE_0F38 */
4589   {
4590     /* 00 */
4591     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4592     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4593     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4594     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4595     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4596     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4597     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4598     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4599     /* 08 */
4600     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4601     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4602     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4603     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     /* 10 */
4609     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4614     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4615     { Bad_Opcode },
4616     { "ptest",  { XM, EXx }, PREFIX_DATA },
4617     /* 18 */
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4623     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4624     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4625     { Bad_Opcode },
4626     /* 20 */
4627     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4628     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4629     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4630     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4631     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4632     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     /* 28 */
4636     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4637     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4638     { MOD_TABLE (MOD_0F382A) },
4639     { "packusdw", { XM, EXx }, PREFIX_DATA },
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     /* 30 */
4645     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4646     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4647     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4648     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4649     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4650     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4651     { Bad_Opcode },
4652     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4653     /* 38 */
4654     { "pminsb", { XM, EXx }, PREFIX_DATA },
4655     { "pminsd", { XM, EXx }, PREFIX_DATA },
4656     { "pminuw", { XM, EXx }, PREFIX_DATA },
4657     { "pminud", { XM, EXx }, PREFIX_DATA },
4658     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4659     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4660     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4661     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4662     /* 40 */
4663     { "pmulld", { XM, EXx }, PREFIX_DATA },
4664     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     /* 48 */
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     /* 50 */
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     /* 58 */
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     /* 60 */
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     /* 68 */
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     /* 70 */
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     /* 78 */
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     /* 80 */
4735     { "invept", { Gm, Mo }, PREFIX_DATA },
4736     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4737     { "invpcid", { Gm, M }, PREFIX_DATA },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     /* 88 */
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     /* 90 */
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     /* 98 */
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     /* a0 */
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     /* a8 */
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     /* b0 */
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     /* b8 */
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     /* c0 */
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     /* c8 */
4816     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4817     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4818     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4819     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4820     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4821     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4822     { Bad_Opcode },
4823     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4824     /* d0 */
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     /* d8 */
4834     { PREFIX_TABLE (PREFIX_0F38D8) },
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { "aesimc", { XM, EXx }, PREFIX_DATA },
4838     { PREFIX_TABLE (PREFIX_0F38DC) },
4839     { PREFIX_TABLE (PREFIX_0F38DD) },
4840     { PREFIX_TABLE (PREFIX_0F38DE) },
4841     { PREFIX_TABLE (PREFIX_0F38DF) },
4842     /* e0 */
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     /* e8 */
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     /* f0 */
4861     { PREFIX_TABLE (PREFIX_0F38F0) },
4862     { PREFIX_TABLE (PREFIX_0F38F1) },
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { MOD_TABLE (MOD_0F38F5) },
4867     { PREFIX_TABLE (PREFIX_0F38F6) },
4868     { Bad_Opcode },
4869     /* f8 */
4870     { PREFIX_TABLE (PREFIX_0F38F8) },
4871     { MOD_TABLE (MOD_0F38F9) },
4872     { PREFIX_TABLE (PREFIX_0F38FA) },
4873     { PREFIX_TABLE (PREFIX_0F38FB) },
4874     { PREFIX_TABLE (PREFIX_0F38FC) },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878   },
4879   /* THREE_BYTE_0F3A */
4880   {
4881     /* 00 */
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     /* 08 */
4891     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4892     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4893     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4894     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4895     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4896     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4897     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4898     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4899     /* 10 */
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4905     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4906     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4907     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4908     /* 18 */
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     /* 20 */
4918     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4919     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4920     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     /* 28 */
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     /* 30 */
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     /* 38 */
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     /* 40 */
4954     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4955     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4956     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4957     { Bad_Opcode },
4958     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     /* 48 */
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     /* 50 */
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     /* 58 */
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     /* 60 */
4990     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4991     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4992     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4993     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     /* 68 */
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     /* 70 */
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     /* 78 */
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     /* 80 */
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     /* 88 */
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     /* 90 */
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     /* 98 */
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     /* a0 */
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     /* a8 */
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     /* b0 */
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     /* b8 */
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     /* c0 */
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     /* c8 */
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5112     { Bad_Opcode },
5113     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5114     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5115     /* d0 */
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     /* d8 */
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5133     /* e0 */
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     /* e8 */
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     /* f0 */
5152     { PREFIX_TABLE (PREFIX_0F3A0F) },
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     /* f8 */
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169   },
5170 };
5171
5172 static const struct dis386 xop_table[][256] = {
5173   /* XOP_08 */
5174   {
5175     /* 00 */
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     /* 08 */
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     /* 10 */
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     /* 18 */
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     /* 20 */
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     /* 28 */
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     /* 30 */
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     /* 38 */
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     /* 40 */
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     /* 48 */
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     /* 50 */
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     /* 58 */
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     /* 60 */
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     /* 68 */
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     /* 70 */
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     /* 78 */
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     /* 80 */
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5326     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5327     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5328     /* 88 */
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5336     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5337     /* 90 */
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5344     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5345     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5346     /* 98 */
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5354     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5355     /* a0 */
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5359     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5363     { Bad_Opcode },
5364     /* a8 */
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     /* b0 */
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5381     { Bad_Opcode },
5382     /* b8 */
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     /* c0 */
5392     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5393     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5394     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5395     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     /* c8 */
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5406     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5407     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5408     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5409     /* d0 */
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     /* d8 */
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     /* e0 */
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     /* e8 */
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5442     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5443     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5444     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5445     /* f0 */
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     /* f8 */
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463   },
5464   /* XOP_09 */
5465   {
5466     /* 00 */
5467     { Bad_Opcode },
5468     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5469     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     /* 08 */
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     /* 10 */
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { MOD_TABLE (MOD_XOP_09_12) },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     /* 18 */
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     /* 20 */
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     /* 28 */
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     /* 30 */
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     /* 38 */
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     /* 40 */
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     /* 48 */
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     /* 50 */
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     /* 58 */
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     /* 60 */
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     /* 68 */
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     /* 70 */
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     /* 78 */
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     /* 80 */
5611     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5612     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5613     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5614     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     /* 88 */
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     /* 90 */
5629     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5630     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5631     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5632     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5633     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5634     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5635     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5636     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5637     /* 98 */
5638     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5639     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5640     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5641     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     /* a0 */
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     /* a8 */
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     /* b0 */
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     /* b8 */
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     /* c0 */
5683     { Bad_Opcode },
5684     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5685     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5686     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5690     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5691     /* c8 */
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     /* d0 */
5701     { Bad_Opcode },
5702     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5703     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5704     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5708     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5709     /* d8 */
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     /* e0 */
5719     { Bad_Opcode },
5720     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5721     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5722     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     /* e8 */
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     /* f0 */
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     /* f8 */
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754   },
5755   /* XOP_0A */
5756   {
5757     /* 00 */
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     /* 08 */
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     /* 10 */
5776     { "bextrS", { Gdq, Edq, Id }, 0 },
5777     { Bad_Opcode },
5778     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     /* 18 */
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     /* 20 */
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     /* 28 */
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     /* 30 */
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     /* 38 */
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     /* 40 */
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     /* 48 */
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     /* 50 */
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     /* 58 */
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     /* 60 */
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     /* 68 */
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     /* 70 */
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     /* 78 */
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     /* 80 */
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     /* 88 */
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     /* 90 */
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     /* 98 */
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     /* a0 */
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     /* a8 */
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     /* b0 */
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     /* b8 */
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     /* c0 */
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     /* c8 */
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     /* d0 */
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     /* d8 */
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     /* e0 */
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     /* e8 */
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     /* f0 */
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     /* f8 */
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045   },
6046 };
6047
6048 static const struct dis386 vex_table[][256] = {
6049   /* VEX_0F */
6050   {
6051     /* 00 */
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     /* 08 */
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     /* 10 */
6070     { PREFIX_TABLE (PREFIX_VEX_0F10) },
6071     { PREFIX_TABLE (PREFIX_VEX_0F11) },
6072     { PREFIX_TABLE (PREFIX_VEX_0F12) },
6073     { MOD_TABLE (MOD_VEX_0F13) },
6074     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6075     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6076     { PREFIX_TABLE (PREFIX_VEX_0F16) },
6077     { MOD_TABLE (MOD_VEX_0F17) },
6078     /* 18 */
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     /* 20 */
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     /* 28 */
6097     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
6098     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
6099     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6100     { MOD_TABLE (MOD_VEX_0F2B) },
6101     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6102     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6103     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
6104     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
6105     /* 30 */
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     /* 38 */
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     /* 40 */
6124     { Bad_Opcode },
6125     { VEX_LEN_TABLE (VEX_LEN_0F41) },
6126     { VEX_LEN_TABLE (VEX_LEN_0F42) },
6127     { Bad_Opcode },
6128     { VEX_LEN_TABLE (VEX_LEN_0F44) },
6129     { VEX_LEN_TABLE (VEX_LEN_0F45) },
6130     { VEX_LEN_TABLE (VEX_LEN_0F46) },
6131     { VEX_LEN_TABLE (VEX_LEN_0F47) },
6132     /* 48 */
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6136     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     /* 50 */
6142     { MOD_TABLE (MOD_VEX_0F50) },
6143     { PREFIX_TABLE (PREFIX_VEX_0F51) },
6144     { PREFIX_TABLE (PREFIX_VEX_0F52) },
6145     { PREFIX_TABLE (PREFIX_VEX_0F53) },
6146     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6147     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
6148     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
6149     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6150     /* 58 */
6151     { PREFIX_TABLE (PREFIX_VEX_0F58) },
6152     { PREFIX_TABLE (PREFIX_VEX_0F59) },
6153     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
6154     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
6155     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
6156     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
6157     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
6158     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
6159     /* 60 */
6160     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
6161     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
6162     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
6163     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
6164     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
6165     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
6166     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
6167     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
6168     /* 68 */
6169     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
6170     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
6171     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
6172     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
6173     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6174     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6175     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6176     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6177     /* 70 */
6178     { PREFIX_TABLE (PREFIX_VEX_0F70) },
6179     { MOD_TABLE (MOD_VEX_0F71) },
6180     { MOD_TABLE (MOD_VEX_0F72) },
6181     { MOD_TABLE (MOD_VEX_0F73) },
6182     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
6183     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
6184     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
6185     { VEX_LEN_TABLE (VEX_LEN_0F77) },
6186     /* 78 */
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6192     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6193     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6194     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6195     /* 80 */
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     /* 88 */
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     /* 90 */
6214     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6215     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6216     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6217     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     /* 98 */
6223     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6224     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     /* a0 */
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     /* a8 */
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { REG_TABLE (REG_VEX_0FAE) },
6248     { Bad_Opcode },
6249     /* b0 */
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     /* b8 */
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     /* c0 */
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6271     { Bad_Opcode },
6272     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6273     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6274     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6275     { Bad_Opcode },
6276     /* c8 */
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     /* d0 */
6286     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6287     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6288     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6289     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6290     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6291     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6292     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6293     { MOD_TABLE (MOD_VEX_0FD7) },
6294     /* d8 */
6295     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6296     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6297     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6298     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6299     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6300     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6301     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6302     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6303     /* e0 */
6304     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6305     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6306     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6307     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6308     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6309     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6310     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6311     { MOD_TABLE (MOD_VEX_0FE7) },
6312     /* e8 */
6313     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6314     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6315     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6316     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6317     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6318     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6319     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6320     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6321     /* f0 */
6322     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6323     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6324     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6325     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6326     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6327     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6328     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6329     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6330     /* f8 */
6331     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6332     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6333     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6334     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6335     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6336     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6337     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6338     { Bad_Opcode },
6339   },
6340   /* VEX_0F38 */
6341   {
6342     /* 00 */
6343     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6344     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6345     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6346     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6347     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6348     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6349     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6350     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6351     /* 08 */
6352     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6353     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6354     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6355     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6356     { VEX_W_TABLE (VEX_W_0F380C) },
6357     { VEX_W_TABLE (VEX_W_0F380D) },
6358     { VEX_W_TABLE (VEX_W_0F380E) },
6359     { VEX_W_TABLE (VEX_W_0F380F) },
6360     /* 10 */
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { VEX_W_TABLE (VEX_W_0F3813) },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6368     { "vptest",         { XM, EXx }, PREFIX_DATA },
6369     /* 18 */
6370     { VEX_W_TABLE (VEX_W_0F3818) },
6371     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6372     { MOD_TABLE (MOD_VEX_0F381A) },
6373     { Bad_Opcode },
6374     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6375     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6376     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6377     { Bad_Opcode },
6378     /* 20 */
6379     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6380     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6381     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6382     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6383     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6384     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     /* 28 */
6388     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6389     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6390     { MOD_TABLE (MOD_VEX_0F382A) },
6391     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6392     { MOD_TABLE (MOD_VEX_0F382C) },
6393     { MOD_TABLE (MOD_VEX_0F382D) },
6394     { MOD_TABLE (MOD_VEX_0F382E) },
6395     { MOD_TABLE (MOD_VEX_0F382F) },
6396     /* 30 */
6397     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6398     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6399     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6400     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6401     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6402     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6403     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6404     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6405     /* 38 */
6406     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6407     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6408     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6409     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6410     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6411     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6412     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6413     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6414     /* 40 */
6415     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6416     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6421     { VEX_W_TABLE (VEX_W_0F3846) },
6422     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6423     /* 48 */
6424     { Bad_Opcode },
6425     { X86_64_TABLE (X86_64_VEX_0F3849) },
6426     { Bad_Opcode },
6427     { X86_64_TABLE (X86_64_VEX_0F384B) },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     /* 50 */
6433     { VEX_W_TABLE (VEX_W_0F3850) },
6434     { VEX_W_TABLE (VEX_W_0F3851) },
6435     { VEX_W_TABLE (VEX_W_0F3852) },
6436     { VEX_W_TABLE (VEX_W_0F3853) },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     /* 58 */
6442     { VEX_W_TABLE (VEX_W_0F3858) },
6443     { VEX_W_TABLE (VEX_W_0F3859) },
6444     { MOD_TABLE (MOD_VEX_0F385A) },
6445     { Bad_Opcode },
6446     { X86_64_TABLE (X86_64_VEX_0F385C) },
6447     { Bad_Opcode },
6448     { X86_64_TABLE (X86_64_VEX_0F385E) },
6449     { Bad_Opcode },
6450     /* 60 */
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     /* 68 */
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     /* 70 */
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     /* 78 */
6478     { VEX_W_TABLE (VEX_W_0F3878) },
6479     { VEX_W_TABLE (VEX_W_0F3879) },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     /* 80 */
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     /* 88 */
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { MOD_TABLE (MOD_VEX_0F388C) },
6501     { Bad_Opcode },
6502     { MOD_TABLE (MOD_VEX_0F388E) },
6503     { Bad_Opcode },
6504     /* 90 */
6505     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6506     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6507     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6508     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6512     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6513     /* 98 */
6514     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6515     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6516     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6517     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6518     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6519     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6520     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6521     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6522     /* a0 */
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6530     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6531     /* a8 */
6532     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6533     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6534     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6535     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6536     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6537     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6538     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6539     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6540     /* b0 */
6541     { VEX_W_TABLE (VEX_W_0F38B0) },
6542     { VEX_W_TABLE (VEX_W_0F38B1) },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { VEX_W_TABLE (VEX_W_0F38B4) },
6546     { VEX_W_TABLE (VEX_W_0F38B5) },
6547     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6548     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6549     /* b8 */
6550     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6551     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6552     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6553     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6554     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6555     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6556     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6557     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6558     /* c0 */
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     /* c8 */
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { VEX_W_TABLE (VEX_W_0F38CF) },
6576     /* d0 */
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     /* d8 */
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6590     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6591     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6592     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6593     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6594     /* e0 */
6595     { X86_64_TABLE (X86_64_VEX_0F38E0) },
6596     { X86_64_TABLE (X86_64_VEX_0F38E1) },
6597     { X86_64_TABLE (X86_64_VEX_0F38E2) },
6598     { X86_64_TABLE (X86_64_VEX_0F38E3) },
6599     { X86_64_TABLE (X86_64_VEX_0F38E4) },
6600     { X86_64_TABLE (X86_64_VEX_0F38E5) },
6601     { X86_64_TABLE (X86_64_VEX_0F38E6) },
6602     { X86_64_TABLE (X86_64_VEX_0F38E7) },
6603     /* e8 */
6604     { X86_64_TABLE (X86_64_VEX_0F38E8) },
6605     { X86_64_TABLE (X86_64_VEX_0F38E9) },
6606     { X86_64_TABLE (X86_64_VEX_0F38EA) },
6607     { X86_64_TABLE (X86_64_VEX_0F38EB) },
6608     { X86_64_TABLE (X86_64_VEX_0F38EC) },
6609     { X86_64_TABLE (X86_64_VEX_0F38ED) },
6610     { X86_64_TABLE (X86_64_VEX_0F38EE) },
6611     { X86_64_TABLE (X86_64_VEX_0F38EF) },
6612     /* f0 */
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6616     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6617     { Bad_Opcode },
6618     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6619     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6620     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6621     /* f8 */
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630   },
6631   /* VEX_0F3A */
6632   {
6633     /* 00 */
6634     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6636     { VEX_W_TABLE (VEX_W_0F3A02) },
6637     { Bad_Opcode },
6638     { VEX_W_TABLE (VEX_W_0F3A04) },
6639     { VEX_W_TABLE (VEX_W_0F3A05) },
6640     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6641     { Bad_Opcode },
6642     /* 08 */
6643     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6644     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6645     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6646     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6647     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6648     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6649     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6650     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6651     /* 10 */
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6657     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6659     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6660     /* 18 */
6661     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6662     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { VEX_W_TABLE (VEX_W_0F3A1D) },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     /* 20 */
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6671     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     /* 28 */
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     /* 30 */
6688     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6689     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6690     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6691     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     /* 38 */
6697     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6698     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     /* 40 */
6706     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6707     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6708     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6709     { Bad_Opcode },
6710     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6711     { Bad_Opcode },
6712     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6713     { Bad_Opcode },
6714     /* 48 */
6715     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6716     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6717     { VEX_W_TABLE (VEX_W_0F3A4A) },
6718     { VEX_W_TABLE (VEX_W_0F3A4B) },
6719     { VEX_W_TABLE (VEX_W_0F3A4C) },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     /* 50 */
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     /* 58 */
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6738     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6739     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6740     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6741     /* 60 */
6742     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6743     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6744     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6745     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     /* 68 */
6751     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6752     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6753     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6754     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6755     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6756     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6757     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6758     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6759     /* 70 */
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     /* 78 */
6769     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6770     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6771     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6772     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6773     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6774     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6775     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6776     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6777     /* 80 */
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     /* 88 */
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     /* 90 */
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     /* 98 */
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     /* a0 */
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     /* a8 */
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     /* b0 */
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     /* b8 */
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     /* c0 */
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     /* c8 */
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { VEX_W_TABLE (VEX_W_0F3ACE) },
6866     { VEX_W_TABLE (VEX_W_0F3ACF) },
6867     /* d0 */
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     /* d8 */
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6885     /* e0 */
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     /* e8 */
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     /* f0 */
6904     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     /* f8 */
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921   },
6922 };
6923
6924 #include "i386-dis-evex.h"
6925
6926 static const struct dis386 vex_len_table[][2] = {
6927   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6928   {
6929     { "%XEvmovlpX",     { XM, Vex, EXq }, 0 },
6930   },
6931
6932   /* VEX_LEN_0F12_P_0_M_1 */
6933   {
6934     { "%XEvmovhlp%XS",  { XM, Vex, EXq }, 0 },
6935   },
6936
6937   /* VEX_LEN_0F13_M_0 */
6938   {
6939     { "%XEvmovlpX",     { EXq, XM }, PREFIX_OPCODE },
6940   },
6941
6942   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6943   {
6944     { "%XEvmovhpX",     { XM, Vex, EXq }, 0 },
6945   },
6946
6947   /* VEX_LEN_0F16_P_0_M_1 */
6948   {
6949     { "%XEvmovlhp%XS",  { XM, Vex, EXq }, 0 },
6950   },
6951
6952   /* VEX_LEN_0F17_M_0 */
6953   {
6954     { "%XEvmovhpX",     { EXq, XM }, PREFIX_OPCODE },
6955   },
6956
6957   /* VEX_LEN_0F41 */
6958   {
6959     { Bad_Opcode },
6960     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6961   },
6962
6963   /* VEX_LEN_0F42 */
6964   {
6965     { Bad_Opcode },
6966     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6967   },
6968
6969   /* VEX_LEN_0F44 */
6970   {
6971     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6972   },
6973
6974   /* VEX_LEN_0F45 */
6975   {
6976     { Bad_Opcode },
6977     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6978   },
6979
6980   /* VEX_LEN_0F46 */
6981   {
6982     { Bad_Opcode },
6983     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6984   },
6985
6986   /* VEX_LEN_0F47 */
6987   {
6988     { Bad_Opcode },
6989     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6990   },
6991
6992   /* VEX_LEN_0F4A */
6993   {
6994     { Bad_Opcode },
6995     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6996   },
6997
6998   /* VEX_LEN_0F4B */
6999   {
7000     { Bad_Opcode },
7001     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
7002   },
7003
7004   /* VEX_LEN_0F6E */
7005   {
7006     { "%XEvmovK",       { XMScalar, Edq }, PREFIX_DATA },
7007   },
7008
7009   /* VEX_LEN_0F77 */
7010   {
7011     { "vzeroupper",     { XX }, 0 },
7012     { "vzeroall",       { XX }, 0 },
7013   },
7014
7015   /* VEX_LEN_0F7E_P_1 */
7016   {
7017     { "%XEvmovq",       { XMScalar, EXq }, 0 },
7018   },
7019
7020   /* VEX_LEN_0F7E_P_2 */
7021   {
7022     { "%XEvmovK",       { Edq, XMScalar }, 0 },
7023   },
7024
7025   /* VEX_LEN_0F90 */
7026   {
7027     { VEX_W_TABLE (VEX_W_0F90_L_0) },
7028   },
7029
7030   /* VEX_LEN_0F91 */
7031   {
7032     { MOD_TABLE (MOD_VEX_0F91_L_0) },
7033   },
7034
7035   /* VEX_LEN_0F92 */
7036   {
7037     { MOD_TABLE (MOD_VEX_0F92_L_0) },
7038   },
7039
7040   /* VEX_LEN_0F93 */
7041   {
7042     { MOD_TABLE (MOD_VEX_0F93_L_0) },
7043   },
7044
7045   /* VEX_LEN_0F98 */
7046   {
7047     { MOD_TABLE (MOD_VEX_0F98_L_0) },
7048   },
7049
7050   /* VEX_LEN_0F99 */
7051   {
7052     { MOD_TABLE (MOD_VEX_0F99_L_0) },
7053   },
7054
7055   /* VEX_LEN_0FAE_R_2_M_0 */
7056   {
7057     { "vldmxcsr",       { Md }, 0 },
7058   },
7059
7060   /* VEX_LEN_0FAE_R_3_M_0 */
7061   {
7062     { "vstmxcsr",       { Md }, 0 },
7063   },
7064
7065   /* VEX_LEN_0FC4 */
7066   {
7067     { "%XEvpinsrw",     { XM, Vex, Edw, Ib }, PREFIX_DATA },
7068   },
7069
7070   /* VEX_LEN_0FC5 */
7071   {
7072     { "%XEvpextrw",     { Gd, XS, Ib }, PREFIX_DATA },
7073   },
7074
7075   /* VEX_LEN_0FD6 */
7076   {
7077     { "%XEvmovq",       { EXqS, XMScalar }, PREFIX_DATA },
7078   },
7079
7080   /* VEX_LEN_0FF7 */
7081   {
7082     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
7083   },
7084
7085   /* VEX_LEN_0F3816 */
7086   {
7087     { Bad_Opcode },
7088     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7089   },
7090
7091   /* VEX_LEN_0F3819 */
7092   {
7093     { Bad_Opcode },
7094     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7095   },
7096
7097   /* VEX_LEN_0F381A_M_0 */
7098   {
7099     { Bad_Opcode },
7100     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
7101   },
7102
7103   /* VEX_LEN_0F3836 */
7104   {
7105     { Bad_Opcode },
7106     { VEX_W_TABLE (VEX_W_0F3836) },
7107   },
7108
7109   /* VEX_LEN_0F3841 */
7110   {
7111     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
7112   },
7113
7114    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
7115   {
7116     { "ldtilecfg", { M }, 0 },
7117   },
7118
7119   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
7120   {
7121     { "tilerelease", { Skip_MODRM }, 0 },
7122   },
7123
7124   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
7125   {
7126     { "sttilecfg", { M }, 0 },
7127   },
7128
7129   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
7130   {
7131     { "tilezero", { TMM, Skip_MODRM }, 0 },
7132   },
7133
7134   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
7135   {
7136     { "tilestored", { MVexSIBMEM, TMM }, 0 },
7137   },
7138   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7139   {
7140     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
7141   },
7142
7143   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7144   {
7145     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
7146   },
7147
7148   /* VEX_LEN_0F385A_M_0 */
7149   {
7150     { Bad_Opcode },
7151     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7152   },
7153
7154   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7155   {
7156     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
7157   },
7158
7159   /* VEX_LEN_0F385C_X86_64_P_3_W_0_M_0 */
7160   {
7161     { "tdpfp16ps", { TMM, EXtmm, VexTmm }, 0 },
7162   },
7163
7164   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7165   {
7166     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
7167   },
7168
7169   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7170   {
7171     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
7172   },
7173
7174   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7175   {
7176     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7177   },
7178
7179   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7180   {
7181     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7182   },
7183
7184   /* VEX_LEN_0F38DB */
7185   {
7186     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7187   },
7188
7189   /* VEX_LEN_0F38F2 */
7190   {
7191     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7192   },
7193
7194   /* VEX_LEN_0F38F3 */
7195   {
7196     { REG_TABLE(REG_VEX_0F38F3_L_0) },
7197   },
7198
7199   /* VEX_LEN_0F38F5 */
7200   {
7201     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7202   },
7203
7204   /* VEX_LEN_0F38F6 */
7205   {
7206     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7207   },
7208
7209   /* VEX_LEN_0F38F7 */
7210   {
7211     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7212   },
7213
7214   /* VEX_LEN_0F3A00 */
7215   {
7216     { Bad_Opcode },
7217     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7218   },
7219
7220   /* VEX_LEN_0F3A01 */
7221   {
7222     { Bad_Opcode },
7223     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7224   },
7225
7226   /* VEX_LEN_0F3A06 */
7227   {
7228     { Bad_Opcode },
7229     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7230   },
7231
7232   /* VEX_LEN_0F3A14 */
7233   {
7234     { "%XEvpextrb",     { Edb, XM, Ib }, PREFIX_DATA },
7235   },
7236
7237   /* VEX_LEN_0F3A15 */
7238   {
7239     { "%XEvpextrw",     { Edw, XM, Ib }, PREFIX_DATA },
7240   },
7241
7242   /* VEX_LEN_0F3A16  */
7243   {
7244     { "%XEvpextrK",     { Edq, XM, Ib }, PREFIX_DATA },
7245   },
7246
7247   /* VEX_LEN_0F3A17 */
7248   {
7249     { "%XEvextractps",  { Ed, XM, Ib }, PREFIX_DATA },
7250   },
7251
7252   /* VEX_LEN_0F3A18 */
7253   {
7254     { Bad_Opcode },
7255     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7256   },
7257
7258   /* VEX_LEN_0F3A19 */
7259   {
7260     { Bad_Opcode },
7261     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7262   },
7263
7264   /* VEX_LEN_0F3A20 */
7265   {
7266     { "%XEvpinsrb",     { XM, Vex, Edb, Ib }, PREFIX_DATA },
7267   },
7268
7269   /* VEX_LEN_0F3A21 */
7270   {
7271     { "%XEvinsertps",   { XM, Vex, EXd, Ib }, PREFIX_DATA },
7272   },
7273
7274   /* VEX_LEN_0F3A22 */
7275   {
7276     { "%XEvpinsrK",     { XM, Vex, Edq, Ib }, PREFIX_DATA },
7277   },
7278
7279   /* VEX_LEN_0F3A30 */
7280   {
7281     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7282   },
7283
7284   /* VEX_LEN_0F3A31 */
7285   {
7286     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7287   },
7288
7289   /* VEX_LEN_0F3A32 */
7290   {
7291     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7292   },
7293
7294   /* VEX_LEN_0F3A33 */
7295   {
7296     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7297   },
7298
7299   /* VEX_LEN_0F3A38 */
7300   {
7301     { Bad_Opcode },
7302     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7303   },
7304
7305   /* VEX_LEN_0F3A39 */
7306   {
7307     { Bad_Opcode },
7308     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7309   },
7310
7311   /* VEX_LEN_0F3A41 */
7312   {
7313     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7314   },
7315
7316   /* VEX_LEN_0F3A46 */
7317   {
7318     { Bad_Opcode },
7319     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7320   },
7321
7322   /* VEX_LEN_0F3A60 */
7323   {
7324     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7325   },
7326
7327   /* VEX_LEN_0F3A61 */
7328   {
7329     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7330   },
7331
7332   /* VEX_LEN_0F3A62 */
7333   {
7334     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7335   },
7336
7337   /* VEX_LEN_0F3A63 */
7338   {
7339     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7340   },
7341
7342   /* VEX_LEN_0F3ADF */
7343   {
7344     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7345   },
7346
7347   /* VEX_LEN_0F3AF0 */
7348   {
7349     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7350   },
7351
7352   /* VEX_LEN_0FXOP_08_85 */
7353   {
7354     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7355   },
7356
7357   /* VEX_LEN_0FXOP_08_86 */
7358   {
7359     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7360   },
7361
7362   /* VEX_LEN_0FXOP_08_87 */
7363   {
7364     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7365   },
7366
7367   /* VEX_LEN_0FXOP_08_8E */
7368   {
7369     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7370   },
7371
7372   /* VEX_LEN_0FXOP_08_8F */
7373   {
7374     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7375   },
7376
7377   /* VEX_LEN_0FXOP_08_95 */
7378   {
7379     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7380   },
7381
7382   /* VEX_LEN_0FXOP_08_96 */
7383   {
7384     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7385   },
7386
7387   /* VEX_LEN_0FXOP_08_97 */
7388   {
7389     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7390   },
7391
7392   /* VEX_LEN_0FXOP_08_9E */
7393   {
7394     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7395   },
7396
7397   /* VEX_LEN_0FXOP_08_9F */
7398   {
7399     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7400   },
7401
7402   /* VEX_LEN_0FXOP_08_A3 */
7403   {
7404     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7405   },
7406
7407   /* VEX_LEN_0FXOP_08_A6 */
7408   {
7409     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7410   },
7411
7412   /* VEX_LEN_0FXOP_08_B6 */
7413   {
7414     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7415   },
7416
7417   /* VEX_LEN_0FXOP_08_C0 */
7418   {
7419     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7420   },
7421
7422   /* VEX_LEN_0FXOP_08_C1 */
7423   {
7424     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7425   },
7426
7427   /* VEX_LEN_0FXOP_08_C2 */
7428   {
7429     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7430   },
7431
7432   /* VEX_LEN_0FXOP_08_C3 */
7433   {
7434     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7435   },
7436
7437   /* VEX_LEN_0FXOP_08_CC */
7438   {
7439     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7440   },
7441
7442   /* VEX_LEN_0FXOP_08_CD */
7443   {
7444     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7445   },
7446
7447   /* VEX_LEN_0FXOP_08_CE */
7448   {
7449     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7450   },
7451
7452   /* VEX_LEN_0FXOP_08_CF */
7453   {
7454     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7455   },
7456
7457   /* VEX_LEN_0FXOP_08_EC */
7458   {
7459     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7460   },
7461
7462   /* VEX_LEN_0FXOP_08_ED */
7463   {
7464     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7465   },
7466
7467   /* VEX_LEN_0FXOP_08_EE */
7468   {
7469     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7470   },
7471
7472   /* VEX_LEN_0FXOP_08_EF */
7473   {
7474     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7475   },
7476
7477   /* VEX_LEN_0FXOP_09_01 */
7478   {
7479     { REG_TABLE (REG_XOP_09_01_L_0) },
7480   },
7481
7482   /* VEX_LEN_0FXOP_09_02 */
7483   {
7484     { REG_TABLE (REG_XOP_09_02_L_0) },
7485   },
7486
7487   /* VEX_LEN_0FXOP_09_12_M_1 */
7488   {
7489     { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7490   },
7491
7492   /* VEX_LEN_0FXOP_09_82_W_0 */
7493   {
7494     { "vfrczss",        { XM, EXd }, 0 },
7495   },
7496
7497   /* VEX_LEN_0FXOP_09_83_W_0 */
7498   {
7499     { "vfrczsd",        { XM, EXq }, 0 },
7500   },
7501
7502   /* VEX_LEN_0FXOP_09_90 */
7503   {
7504     { "vprotb",         { XM, EXx, VexW }, 0 },
7505   },
7506
7507   /* VEX_LEN_0FXOP_09_91 */
7508   {
7509     { "vprotw",         { XM, EXx, VexW }, 0 },
7510   },
7511
7512   /* VEX_LEN_0FXOP_09_92 */
7513   {
7514     { "vprotd",         { XM, EXx, VexW }, 0 },
7515   },
7516
7517   /* VEX_LEN_0FXOP_09_93 */
7518   {
7519     { "vprotq",         { XM, EXx, VexW }, 0 },
7520   },
7521
7522   /* VEX_LEN_0FXOP_09_94 */
7523   {
7524     { "vpshlb",         { XM, EXx, VexW }, 0 },
7525   },
7526
7527   /* VEX_LEN_0FXOP_09_95 */
7528   {
7529     { "vpshlw",         { XM, EXx, VexW }, 0 },
7530   },
7531
7532   /* VEX_LEN_0FXOP_09_96 */
7533   {
7534     { "vpshld",         { XM, EXx, VexW }, 0 },
7535   },
7536
7537   /* VEX_LEN_0FXOP_09_97 */
7538   {
7539     { "vpshlq",         { XM, EXx, VexW }, 0 },
7540   },
7541
7542   /* VEX_LEN_0FXOP_09_98 */
7543   {
7544     { "vpshab",         { XM, EXx, VexW }, 0 },
7545   },
7546
7547   /* VEX_LEN_0FXOP_09_99 */
7548   {
7549     { "vpshaw",         { XM, EXx, VexW }, 0 },
7550   },
7551
7552   /* VEX_LEN_0FXOP_09_9A */
7553   {
7554     { "vpshad",         { XM, EXx, VexW }, 0 },
7555   },
7556
7557   /* VEX_LEN_0FXOP_09_9B */
7558   {
7559     { "vpshaq",         { XM, EXx, VexW }, 0 },
7560   },
7561
7562   /* VEX_LEN_0FXOP_09_C1 */
7563   {
7564     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7565   },
7566
7567   /* VEX_LEN_0FXOP_09_C2 */
7568   {
7569     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7570   },
7571
7572   /* VEX_LEN_0FXOP_09_C3 */
7573   {
7574     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7575   },
7576
7577   /* VEX_LEN_0FXOP_09_C6 */
7578   {
7579     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7580   },
7581
7582   /* VEX_LEN_0FXOP_09_C7 */
7583   {
7584     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7585   },
7586
7587   /* VEX_LEN_0FXOP_09_CB */
7588   {
7589     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7590   },
7591
7592   /* VEX_LEN_0FXOP_09_D1 */
7593   {
7594     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7595   },
7596
7597   /* VEX_LEN_0FXOP_09_D2 */
7598   {
7599     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7600   },
7601
7602   /* VEX_LEN_0FXOP_09_D3 */
7603   {
7604     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7605   },
7606
7607   /* VEX_LEN_0FXOP_09_D6 */
7608   {
7609     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7610   },
7611
7612   /* VEX_LEN_0FXOP_09_D7 */
7613   {
7614     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7615   },
7616
7617   /* VEX_LEN_0FXOP_09_DB */
7618   {
7619     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7620   },
7621
7622   /* VEX_LEN_0FXOP_09_E1 */
7623   {
7624     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7625   },
7626
7627   /* VEX_LEN_0FXOP_09_E2 */
7628   {
7629     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7630   },
7631
7632   /* VEX_LEN_0FXOP_09_E3 */
7633   {
7634     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7635   },
7636
7637   /* VEX_LEN_0FXOP_0A_12 */
7638   {
7639     { REG_TABLE (REG_XOP_0A_12_L_0) },
7640   },
7641 };
7642
7643 #include "i386-dis-evex-len.h"
7644
7645 static const struct dis386 vex_w_table[][2] = {
7646   {
7647     /* VEX_W_0F41_L_1_M_1 */
7648     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7649     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7650   },
7651   {
7652     /* VEX_W_0F42_L_1_M_1 */
7653     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7654     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7655   },
7656   {
7657     /* VEX_W_0F44_L_0_M_1 */
7658     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7659     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7660   },
7661   {
7662     /* VEX_W_0F45_L_1_M_1 */
7663     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7664     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7665   },
7666   {
7667     /* VEX_W_0F46_L_1_M_1 */
7668     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7669     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7670   },
7671   {
7672     /* VEX_W_0F47_L_1_M_1 */
7673     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7674     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7675   },
7676   {
7677     /* VEX_W_0F4A_L_1_M_1 */
7678     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7679     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7680   },
7681   {
7682     /* VEX_W_0F4B_L_1_M_1 */
7683     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7684     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7685   },
7686   {
7687     /* VEX_W_0F90_L_0 */
7688     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7689     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7690   },
7691   {
7692     /* VEX_W_0F91_L_0_M_0 */
7693     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7694     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7695   },
7696   {
7697     /* VEX_W_0F92_L_0_M_1 */
7698     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7699     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7700   },
7701   {
7702     /* VEX_W_0F93_L_0_M_1 */
7703     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7704     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7705   },
7706   {
7707     /* VEX_W_0F98_L_0_M_1 */
7708     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7709     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7710   },
7711   {
7712     /* VEX_W_0F99_L_0_M_1 */
7713     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7714     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7715   },
7716   {
7717     /* VEX_W_0F380C  */
7718     { "%XEvpermilps",   { XM, Vex, EXx }, PREFIX_DATA },
7719   },
7720   {
7721     /* VEX_W_0F380D  */
7722     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7723   },
7724   {
7725     /* VEX_W_0F380E  */
7726     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7727   },
7728   {
7729     /* VEX_W_0F380F  */
7730     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7731   },
7732   {
7733     /* VEX_W_0F3813 */
7734     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7735   },
7736   {
7737     /* VEX_W_0F3816_L_1  */
7738     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7739   },
7740   {
7741     /* VEX_W_0F3818 */
7742     { "%XEvbroadcastss",        { XM, EXd }, PREFIX_DATA },
7743   },
7744   {
7745     /* VEX_W_0F3819_L_1 */
7746     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7747   },
7748   {
7749     /* VEX_W_0F381A_M_0_L_1 */
7750     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7751   },
7752   {
7753     /* VEX_W_0F382C_M_0 */
7754     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7755   },
7756   {
7757     /* VEX_W_0F382D_M_0 */
7758     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7759   },
7760   {
7761     /* VEX_W_0F382E_M_0 */
7762     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7763   },
7764   {
7765     /* VEX_W_0F382F_M_0 */
7766     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7767   },
7768   {
7769     /* VEX_W_0F3836  */
7770     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7771   },
7772   {
7773     /* VEX_W_0F3846 */
7774     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7775   },
7776   {
7777     /* VEX_W_0F3849_X86_64_P_0 */
7778     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7779   },
7780   {
7781     /* VEX_W_0F3849_X86_64_P_2 */
7782     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7783   },
7784   {
7785     /* VEX_W_0F3849_X86_64_P_3 */
7786     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7787   },
7788   {
7789     /* VEX_W_0F384B_X86_64_P_1 */
7790     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7791   },
7792   {
7793     /* VEX_W_0F384B_X86_64_P_2 */
7794     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7795   },
7796   {
7797     /* VEX_W_0F384B_X86_64_P_3 */
7798     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7799   },
7800   {
7801     /* VEX_W_0F3850 */
7802     { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7803   },
7804   {
7805     /* VEX_W_0F3851 */
7806     { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7807   },
7808   {
7809     /* VEX_W_0F3852 */
7810     { "%XVvpdpwssd",    { XM, Vex, EXx }, PREFIX_DATA },
7811   },
7812   {
7813     /* VEX_W_0F3853 */
7814     { "%XVvpdpwssds",   { XM, Vex, EXx }, PREFIX_DATA },
7815   },
7816   {
7817     /* VEX_W_0F3858 */
7818     { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7819   },
7820   {
7821     /* VEX_W_0F3859 */
7822     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7823   },
7824   {
7825     /* VEX_W_0F385A_M_0_L_0 */
7826     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7827   },
7828   {
7829     /* VEX_W_0F385C_X86_64_P_1 */
7830     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7831   },
7832   {
7833     /* VEX_W_0F385C_X86_64_P_3 */
7834     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_3_W_0) },
7835   },
7836   {
7837     /* VEX_W_0F385E_X86_64_P_0 */
7838     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7839   },
7840   {
7841     /* VEX_W_0F385E_X86_64_P_1 */
7842     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7843   },
7844   {
7845     /* VEX_W_0F385E_X86_64_P_2 */
7846     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7847   },
7848   {
7849     /* VEX_W_0F385E_X86_64_P_3 */
7850     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7851   },
7852   {
7853     /* VEX_W_0F3872_P_1 */
7854     { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7855   },
7856   {
7857     /* VEX_W_0F3878 */
7858     { "%XEvpbroadcastb",        { XM, EXb }, PREFIX_DATA },
7859   },
7860   {
7861     /* VEX_W_0F3879 */
7862     { "%XEvpbroadcastw",        { XM, EXw }, PREFIX_DATA },
7863   },
7864   {
7865     /* VEX_W_0F38B0 */
7866     { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7867   },
7868   {
7869     /* VEX_W_0F38B1 */
7870     { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7871   },
7872   {
7873     /* VEX_W_0F38B4 */
7874     { Bad_Opcode },
7875     { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7876   },
7877   {
7878     /* VEX_W_0F38B5 */
7879     { Bad_Opcode },
7880     { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7881   },
7882   {
7883     /* VEX_W_0F38CF */
7884     { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7885   },
7886   {
7887     /* VEX_W_0F3A00_L_1 */
7888     { Bad_Opcode },
7889     { "%XEvpermq",              { XM, EXx, Ib }, PREFIX_DATA },
7890   },
7891   {
7892     /* VEX_W_0F3A01_L_1 */
7893     { Bad_Opcode },
7894     { "%XEvpermpd",     { XM, EXx, Ib }, PREFIX_DATA },
7895   },
7896   {
7897     /* VEX_W_0F3A02 */
7898     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7899   },
7900   {
7901     /* VEX_W_0F3A04 */
7902     { "%XEvpermilps",   { XM, EXx, Ib }, PREFIX_DATA },
7903   },
7904   {
7905     /* VEX_W_0F3A05 */
7906     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7907   },
7908   {
7909     /* VEX_W_0F3A06_L_1 */
7910     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7911   },
7912   {
7913     /* VEX_W_0F3A18_L_1 */
7914     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7915   },
7916   {
7917     /* VEX_W_0F3A19_L_1 */
7918     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7919   },
7920   {
7921     /* VEX_W_0F3A1D */
7922     { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7923   },
7924   {
7925     /* VEX_W_0F3A38_L_1 */
7926     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7927   },
7928   {
7929     /* VEX_W_0F3A39_L_1 */
7930     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7931   },
7932   {
7933     /* VEX_W_0F3A46_L_1 */
7934     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7935   },
7936   {
7937     /* VEX_W_0F3A4A */
7938     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7939   },
7940   {
7941     /* VEX_W_0F3A4B */
7942     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7943   },
7944   {
7945     /* VEX_W_0F3A4C */
7946     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7947   },
7948   {
7949     /* VEX_W_0F3ACE */
7950     { Bad_Opcode },
7951     { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7952   },
7953   {
7954     /* VEX_W_0F3ACF */
7955     { Bad_Opcode },
7956     { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7957   },
7958   /* VEX_W_0FXOP_08_85_L_0 */
7959   {
7960     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7961   },
7962   /* VEX_W_0FXOP_08_86_L_0 */
7963   {
7964     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7965   },
7966   /* VEX_W_0FXOP_08_87_L_0 */
7967   {
7968     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7969   },
7970   /* VEX_W_0FXOP_08_8E_L_0 */
7971   {
7972     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7973   },
7974   /* VEX_W_0FXOP_08_8F_L_0 */
7975   {
7976     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7977   },
7978   /* VEX_W_0FXOP_08_95_L_0 */
7979   {
7980     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7981   },
7982   /* VEX_W_0FXOP_08_96_L_0 */
7983   {
7984     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7985   },
7986   /* VEX_W_0FXOP_08_97_L_0 */
7987   {
7988     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7989   },
7990   /* VEX_W_0FXOP_08_9E_L_0 */
7991   {
7992     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7993   },
7994   /* VEX_W_0FXOP_08_9F_L_0 */
7995   {
7996     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7997   },
7998   /* VEX_W_0FXOP_08_A6_L_0 */
7999   {
8000     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
8001   },
8002   /* VEX_W_0FXOP_08_B6_L_0 */
8003   {
8004     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
8005   },
8006   /* VEX_W_0FXOP_08_C0_L_0 */
8007   {
8008     { "vprotb",         { XM, EXx, Ib }, 0 },
8009   },
8010   /* VEX_W_0FXOP_08_C1_L_0 */
8011   {
8012     { "vprotw",         { XM, EXx, Ib }, 0 },
8013   },
8014   /* VEX_W_0FXOP_08_C2_L_0 */
8015   {
8016     { "vprotd",         { XM, EXx, Ib }, 0 },
8017   },
8018   /* VEX_W_0FXOP_08_C3_L_0 */
8019   {
8020     { "vprotq",         { XM, EXx, Ib }, 0 },
8021   },
8022   /* VEX_W_0FXOP_08_CC_L_0 */
8023   {
8024      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
8025   },
8026   /* VEX_W_0FXOP_08_CD_L_0 */
8027   {
8028      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
8029   },
8030   /* VEX_W_0FXOP_08_CE_L_0 */
8031   {
8032      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
8033   },
8034   /* VEX_W_0FXOP_08_CF_L_0 */
8035   {
8036      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
8037   },
8038   /* VEX_W_0FXOP_08_EC_L_0 */
8039   {
8040      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
8041   },
8042   /* VEX_W_0FXOP_08_ED_L_0 */
8043   {
8044      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
8045   },
8046   /* VEX_W_0FXOP_08_EE_L_0 */
8047   {
8048      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
8049   },
8050   /* VEX_W_0FXOP_08_EF_L_0 */
8051   {
8052      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
8053   },
8054   /* VEX_W_0FXOP_09_80 */
8055   {
8056     { "vfrczps",        { XM, EXx }, 0 },
8057   },
8058   /* VEX_W_0FXOP_09_81 */
8059   {
8060     { "vfrczpd",        { XM, EXx }, 0 },
8061   },
8062   /* VEX_W_0FXOP_09_82 */
8063   {
8064     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
8065   },
8066   /* VEX_W_0FXOP_09_83 */
8067   {
8068     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
8069   },
8070   /* VEX_W_0FXOP_09_C1_L_0 */
8071   {
8072     { "vphaddbw",       { XM, EXxmm }, 0 },
8073   },
8074   /* VEX_W_0FXOP_09_C2_L_0 */
8075   {
8076     { "vphaddbd",       { XM, EXxmm }, 0 },
8077   },
8078   /* VEX_W_0FXOP_09_C3_L_0 */
8079   {
8080     { "vphaddbq",       { XM, EXxmm }, 0 },
8081   },
8082   /* VEX_W_0FXOP_09_C6_L_0 */
8083   {
8084     { "vphaddwd",       { XM, EXxmm }, 0 },
8085   },
8086   /* VEX_W_0FXOP_09_C7_L_0 */
8087   {
8088     { "vphaddwq",       { XM, EXxmm }, 0 },
8089   },
8090   /* VEX_W_0FXOP_09_CB_L_0 */
8091   {
8092     { "vphadddq",       { XM, EXxmm }, 0 },
8093   },
8094   /* VEX_W_0FXOP_09_D1_L_0 */
8095   {
8096     { "vphaddubw",      { XM, EXxmm }, 0 },
8097   },
8098   /* VEX_W_0FXOP_09_D2_L_0 */
8099   {
8100     { "vphaddubd",      { XM, EXxmm }, 0 },
8101   },
8102   /* VEX_W_0FXOP_09_D3_L_0 */
8103   {
8104     { "vphaddubq",      { XM, EXxmm }, 0 },
8105   },
8106   /* VEX_W_0FXOP_09_D6_L_0 */
8107   {
8108     { "vphadduwd",      { XM, EXxmm }, 0 },
8109   },
8110   /* VEX_W_0FXOP_09_D7_L_0 */
8111   {
8112     { "vphadduwq",      { XM, EXxmm }, 0 },
8113   },
8114   /* VEX_W_0FXOP_09_DB_L_0 */
8115   {
8116     { "vphaddudq",      { XM, EXxmm }, 0 },
8117   },
8118   /* VEX_W_0FXOP_09_E1_L_0 */
8119   {
8120     { "vphsubbw",       { XM, EXxmm }, 0 },
8121   },
8122   /* VEX_W_0FXOP_09_E2_L_0 */
8123   {
8124     { "vphsubwd",       { XM, EXxmm }, 0 },
8125   },
8126   /* VEX_W_0FXOP_09_E3_L_0 */
8127   {
8128     { "vphsubdq",       { XM, EXxmm }, 0 },
8129   },
8130
8131 #include "i386-dis-evex-w.h"
8132 };
8133
8134 static const struct dis386 mod_table[][2] = {
8135   {
8136     /* MOD_62_32BIT */
8137     { "bound{S|}",      { Gv, Ma }, 0 },
8138     { EVEX_TABLE (EVEX_0F) },
8139   },
8140   {
8141     /* MOD_8D */
8142     { "leaS",           { Gv, M }, 0 },
8143   },
8144   {
8145     /* MOD_C4_32BIT */
8146     { "lesS",           { Gv, Mp }, 0 },
8147     { VEX_C4_TABLE (VEX_0F) },
8148   },
8149   {
8150     /* MOD_C5_32BIT */
8151     { "ldsS",           { Gv, Mp }, 0 },
8152     { VEX_C5_TABLE (VEX_0F) },
8153   },
8154   {
8155     /* MOD_C6_REG_7 */
8156     { Bad_Opcode },
8157     { RM_TABLE (RM_C6_REG_7) },
8158   },
8159   {
8160     /* MOD_C7_REG_7 */
8161     { Bad_Opcode },
8162     { RM_TABLE (RM_C7_REG_7) },
8163   },
8164   {
8165     /* MOD_FF_REG_3 */
8166     { "{l|}call^", { indirEp }, 0 },
8167   },
8168   {
8169     /* MOD_FF_REG_5 */
8170     { "{l|}jmp^", { indirEp }, 0 },
8171   },
8172   {
8173     /* MOD_0F01_REG_0 */
8174     { X86_64_TABLE (X86_64_0F01_REG_0) },
8175     { RM_TABLE (RM_0F01_REG_0) },
8176   },
8177   {
8178     /* MOD_0F01_REG_1 */
8179     { X86_64_TABLE (X86_64_0F01_REG_1) },
8180     { RM_TABLE (RM_0F01_REG_1) },
8181   },
8182   {
8183     /* MOD_0F01_REG_2 */
8184     { X86_64_TABLE (X86_64_0F01_REG_2) },
8185     { RM_TABLE (RM_0F01_REG_2) },
8186   },
8187   {
8188     /* MOD_0F01_REG_3 */
8189     { X86_64_TABLE (X86_64_0F01_REG_3) },
8190     { RM_TABLE (RM_0F01_REG_3) },
8191   },
8192   {
8193     /* MOD_0F01_REG_5 */
8194     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8195     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8196   },
8197   {
8198     /* MOD_0F01_REG_7 */
8199     { "invlpg",         { Mb }, 0 },
8200     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8201   },
8202   {
8203     /* MOD_0F02 */
8204     { "larS",           { Gv, Mw }, 0 },
8205     { "larS",           { Gv, Ev }, 0 },
8206   },
8207   {
8208     /* MOD_0F03 */
8209     { "lslS",           { Gv, Mw }, 0 },
8210     { "lslS",           { Gv, Ev }, 0 },
8211   },
8212   {
8213     /* MOD_0F12_PREFIX_0 */
8214     { "movlpX",         { XM, EXq }, 0 },
8215     { "movhlps",        { XM, EXq }, 0 },
8216   },
8217   {
8218     /* MOD_0F12_PREFIX_2 */
8219     { "movlpX", { XM, EXq }, 0 },
8220   },
8221   {
8222     /* MOD_0F13 */
8223     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
8224   },
8225   {
8226     /* MOD_0F16_PREFIX_0 */
8227     { "movhpX",         { XM, EXq }, 0 },
8228     { "movlhps",        { XM, EXq }, 0 },
8229   },
8230   {
8231     /* MOD_0F16_PREFIX_2 */
8232     { "movhpX", { XM, EXq }, 0 },
8233   },
8234   {
8235     /* MOD_0F17 */
8236     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8237   },
8238   {
8239     /* MOD_0F18_REG_0 */
8240     { "prefetchnta",    { Mb }, 0 },
8241     { "nopQ",           { Ev }, 0 },
8242   },
8243   {
8244     /* MOD_0F18_REG_1 */
8245     { "prefetcht0",     { Mb }, 0 },
8246     { "nopQ",           { Ev }, 0 },
8247   },
8248   {
8249     /* MOD_0F18_REG_2 */
8250     { "prefetcht1",     { Mb }, 0 },
8251     { "nopQ",           { Ev }, 0 },
8252   },
8253   {
8254     /* MOD_0F18_REG_3 */
8255     { "prefetcht2",     { Mb }, 0 },
8256     { "nopQ",           { Ev }, 0 },
8257   },
8258   {
8259     /* MOD_0F18_REG_6 */
8260     { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8261     { "nopQ",           { Ev }, 0 },
8262   },
8263   {
8264     /* MOD_0F18_REG_7 */
8265     { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8266     { "nopQ",           { Ev }, 0 },
8267   },
8268   {
8269     /* MOD_0F1A_PREFIX_0 */
8270     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8271     { "nopQ",           { Ev }, 0 },
8272   },
8273   {
8274     /* MOD_0F1B_PREFIX_0 */
8275     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8276     { "nopQ",           { Ev }, 0 },
8277   },
8278   {
8279     /* MOD_0F1B_PREFIX_1 */
8280     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8281     { "nopQ",           { Ev }, PREFIX_IGNORED },
8282   },
8283   {
8284     /* MOD_0F1C_PREFIX_0 */
8285     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8286     { "nopQ",           { Ev }, 0 },
8287   },
8288   {
8289     /* MOD_0F1E_PREFIX_1 */
8290     { "nopQ",           { Ev }, PREFIX_IGNORED },
8291     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8292   },
8293   {
8294     /* MOD_0F2B_PREFIX_0 */
8295     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8296   },
8297   {
8298     /* MOD_0F2B_PREFIX_1 */
8299     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8300   },
8301   {
8302     /* MOD_0F2B_PREFIX_2 */
8303     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8304   },
8305   {
8306     /* MOD_0F2B_PREFIX_3 */
8307     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8308   },
8309   {
8310     /* MOD_0F50 */
8311     { Bad_Opcode },
8312     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8313   },
8314   {
8315     /* MOD_0F71 */
8316     { Bad_Opcode },
8317     { REG_TABLE (REG_0F71_MOD_0) },
8318   },
8319   {
8320     /* MOD_0F72 */
8321     { Bad_Opcode },
8322     { REG_TABLE (REG_0F72_MOD_0) },
8323   },
8324   {
8325     /* MOD_0F73 */
8326     { Bad_Opcode },
8327     { REG_TABLE (REG_0F73_MOD_0) },
8328   },
8329   {
8330     /* MOD_0FAE_REG_0 */
8331     { "fxsave",         { FXSAVE }, 0 },
8332     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8333   },
8334   {
8335     /* MOD_0FAE_REG_1 */
8336     { "fxrstor",        { FXSAVE }, 0 },
8337     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8338   },
8339   {
8340     /* MOD_0FAE_REG_2 */
8341     { "ldmxcsr",        { Md }, 0 },
8342     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8343   },
8344   {
8345     /* MOD_0FAE_REG_3 */
8346     { "stmxcsr",        { Md }, 0 },
8347     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8348   },
8349   {
8350     /* MOD_0FAE_REG_4 */
8351     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8352     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8353   },
8354   {
8355     /* MOD_0FAE_REG_5 */
8356     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8357     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8358   },
8359   {
8360     /* MOD_0FAE_REG_6 */
8361     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8362     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8363   },
8364   {
8365     /* MOD_0FAE_REG_7 */
8366     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8367     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8368   },
8369   {
8370     /* MOD_0FB2 */
8371     { "lssS",           { Gv, Mp }, 0 },
8372   },
8373   {
8374     /* MOD_0FB4 */
8375     { "lfsS",           { Gv, Mp }, 0 },
8376   },
8377   {
8378     /* MOD_0FB5 */
8379     { "lgsS",           { Gv, Mp }, 0 },
8380   },
8381   {
8382     /* MOD_0FC3 */
8383     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8384   },
8385   {
8386     /* MOD_0FC7_REG_3 */
8387     { "xrstors",        { FXSAVE }, 0 },
8388   },
8389   {
8390     /* MOD_0FC7_REG_4 */
8391     { "xsavec",         { FXSAVE }, 0 },
8392   },
8393   {
8394     /* MOD_0FC7_REG_5 */
8395     { "xsaves",         { FXSAVE }, 0 },
8396   },
8397   {
8398     /* MOD_0FC7_REG_6 */
8399     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8400     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8401   },
8402   {
8403     /* MOD_0FC7_REG_7 */
8404     { "vmptrst",        { Mq }, 0 },
8405     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8406   },
8407   {
8408     /* MOD_0FD7 */
8409     { Bad_Opcode },
8410     { "pmovmskb",       { Gdq, MS }, 0 },
8411   },
8412   {
8413     /* MOD_0FE7_PREFIX_2 */
8414     { "movntdq",        { Mx, XM }, 0 },
8415   },
8416   {
8417     /* MOD_0FF0_PREFIX_3 */
8418     { "lddqu",          { XM, M }, 0 },
8419   },
8420   {
8421     /* MOD_0F382A */
8422     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8423   },
8424   {
8425     /* MOD_0F38DC_PREFIX_1 */
8426     { "aesenc128kl",    { XM, M }, 0 },
8427     { "loadiwkey",      { XM, EXx }, 0 },
8428   },
8429   {
8430     /* MOD_0F38DD_PREFIX_1 */
8431     { "aesdec128kl",    { XM, M }, 0 },
8432   },
8433   {
8434     /* MOD_0F38DE_PREFIX_1 */
8435     { "aesenc256kl",    { XM, M }, 0 },
8436   },
8437   {
8438     /* MOD_0F38DF_PREFIX_1 */
8439     { "aesdec256kl",    { XM, M }, 0 },
8440   },
8441   {
8442     /* MOD_0F38F5 */
8443     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8444   },
8445   {
8446     /* MOD_0F38F6_PREFIX_0 */
8447     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8448   },
8449   {
8450     /* MOD_0F38F8_PREFIX_1 */
8451     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8452   },
8453   {
8454     /* MOD_0F38F8_PREFIX_2 */
8455     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8456   },
8457   {
8458     /* MOD_0F38F8_PREFIX_3 */
8459     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8460   },
8461   {
8462     /* MOD_0F38F9 */
8463     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8464   },
8465   {
8466     /* MOD_0F38FA_PREFIX_1 */
8467     { Bad_Opcode },
8468     { "encodekey128", { Gd, Ed }, 0 },
8469   },
8470   {
8471     /* MOD_0F38FB_PREFIX_1 */
8472     { Bad_Opcode },
8473     { "encodekey256", { Gd, Ed }, 0 },
8474   },
8475   {
8476     /* MOD_0F3A0F_PREFIX_1 */
8477     { Bad_Opcode },
8478     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8479   },
8480   {
8481     /* MOD_VEX_0F12_PREFIX_0 */
8482     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8483     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8484   },
8485   {
8486     /* MOD_VEX_0F12_PREFIX_2 */
8487     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8488   },
8489   {
8490     /* MOD_VEX_0F13 */
8491     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8492   },
8493   {
8494     /* MOD_VEX_0F16_PREFIX_0 */
8495     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8496     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8497   },
8498   {
8499     /* MOD_VEX_0F16_PREFIX_2 */
8500     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8501   },
8502   {
8503     /* MOD_VEX_0F17 */
8504     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8505   },
8506   {
8507     /* MOD_VEX_0F2B */
8508     { "%XEvmovntpX",    { Mx, XM }, PREFIX_OPCODE },
8509   },
8510   {
8511     /* MOD_VEX_0F41_L_1 */
8512     { Bad_Opcode },
8513     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8514   },
8515   {
8516     /* MOD_VEX_0F42_L_1 */
8517     { Bad_Opcode },
8518     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8519   },
8520   {
8521     /* MOD_VEX_0F44_L_0 */
8522     { Bad_Opcode },
8523     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8524   },
8525   {
8526     /* MOD_VEX_0F45_L_1 */
8527     { Bad_Opcode },
8528     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8529   },
8530   {
8531     /* MOD_VEX_0F46_L_1 */
8532     { Bad_Opcode },
8533     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8534   },
8535   {
8536     /* MOD_VEX_0F47_L_1 */
8537     { Bad_Opcode },
8538     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8539   },
8540   {
8541     /* MOD_VEX_0F4A_L_1 */
8542     { Bad_Opcode },
8543     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8544   },
8545   {
8546     /* MOD_VEX_0F4B_L_1 */
8547     { Bad_Opcode },
8548     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8549   },
8550   {
8551     /* MOD_VEX_0F50 */
8552     { Bad_Opcode },
8553     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8554   },
8555   {
8556     /* MOD_VEX_0F71 */
8557     { Bad_Opcode },
8558     { REG_TABLE (REG_VEX_0F71_M_0) },
8559   },
8560   {
8561     /* MOD_VEX_0F72 */
8562     { Bad_Opcode },
8563     { REG_TABLE (REG_VEX_0F72_M_0) },
8564   },
8565   {
8566     /* MOD_VEX_0F73 */
8567     { Bad_Opcode },
8568     { REG_TABLE (REG_VEX_0F73_M_0) },
8569   },
8570   {
8571     /* MOD_VEX_0F91_L_0 */
8572     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8573   },
8574   {
8575     /* MOD_VEX_0F92_L_0 */
8576     { Bad_Opcode },
8577     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8578   },
8579   {
8580     /* MOD_VEX_0F93_L_0 */
8581     { Bad_Opcode },
8582     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8583   },
8584   {
8585     /* MOD_VEX_0F98_L_0 */
8586     { Bad_Opcode },
8587     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8588   },
8589   {
8590     /* MOD_VEX_0F99_L_0 */
8591     { Bad_Opcode },
8592     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8593   },
8594   {
8595     /* MOD_VEX_0FAE_REG_2 */
8596     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8597   },
8598   {
8599     /* MOD_VEX_0FAE_REG_3 */
8600     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8601   },
8602   {
8603     /* MOD_VEX_0FD7 */
8604     { Bad_Opcode },
8605     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8606   },
8607   {
8608     /* MOD_VEX_0FE7 */
8609     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8610   },
8611   {
8612     /* MOD_VEX_0FF0_PREFIX_3 */
8613     { "vlddqu",         { XM, M }, 0 },
8614   },
8615   {
8616     /* MOD_VEX_0F381A */
8617     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8618   },
8619   {
8620     /* MOD_VEX_0F382A */
8621     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8622   },
8623   {
8624     /* MOD_VEX_0F382C */
8625     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8626   },
8627   {
8628     /* MOD_VEX_0F382D */
8629     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8630   },
8631   {
8632     /* MOD_VEX_0F382E */
8633     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8634   },
8635   {
8636     /* MOD_VEX_0F382F */
8637     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8638   },
8639   {
8640     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8641     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8642     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8643   },
8644   {
8645     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8646     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8647   },
8648   {
8649     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8650     { Bad_Opcode },
8651     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8652   },
8653   {
8654     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8655     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8656   },
8657   {
8658     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8659     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8660   },
8661   {
8662     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8663     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8664   },
8665   {
8666     /* MOD_VEX_0F385A */
8667     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8668   },
8669   {
8670     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8671     { Bad_Opcode },
8672     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8673   },
8674   {
8675     /* MOD_VEX_0F385C_X86_64_P_3_W_0 */
8676     { Bad_Opcode },
8677     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0) },
8678   },
8679   {
8680     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8681     { Bad_Opcode },
8682     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8683   },
8684   {
8685     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8686     { Bad_Opcode },
8687     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8688   },
8689   {
8690     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8691     { Bad_Opcode },
8692     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8693   },
8694   {
8695     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8696     { Bad_Opcode },
8697     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8698   },
8699   {
8700     /* MOD_VEX_0F388C */
8701     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8702   },
8703   {
8704     /* MOD_VEX_0F388E */
8705     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8706   },
8707   {
8708     /* MOD_VEX_0F3A30_L_0 */
8709     { Bad_Opcode },
8710     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8711   },
8712   {
8713     /* MOD_VEX_0F3A31_L_0 */
8714     { Bad_Opcode },
8715     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8716   },
8717   {
8718     /* MOD_VEX_0F3A32_L_0 */
8719     { Bad_Opcode },
8720     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8721   },
8722   {
8723     /* MOD_VEX_0F3A33_L_0 */
8724     { Bad_Opcode },
8725     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8726   },
8727   {
8728     /* MOD_XOP_09_12 */
8729     { Bad_Opcode },
8730     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8731   },
8732
8733 #include "i386-dis-evex-mod.h"
8734 };
8735
8736 static const struct dis386 rm_table[][8] = {
8737   {
8738     /* RM_C6_REG_7 */
8739     { "xabort",         { Skip_MODRM, Ib }, 0 },
8740   },
8741   {
8742     /* RM_C7_REG_7 */
8743     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8744   },
8745   {
8746     /* RM_0F01_REG_0 */
8747     { "enclv",          { Skip_MODRM }, 0 },
8748     { "vmcall",         { Skip_MODRM }, 0 },
8749     { "vmlaunch",       { Skip_MODRM }, 0 },
8750     { "vmresume",       { Skip_MODRM }, 0 },
8751     { "vmxoff",         { Skip_MODRM }, 0 },
8752     { "pconfig",        { Skip_MODRM }, 0 },
8753     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8754   },
8755   {
8756     /* RM_0F01_REG_1 */
8757     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8758     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8759     { "clac",           { Skip_MODRM }, 0 },
8760     { "stac",           { Skip_MODRM }, 0 },
8761     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8762     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8763     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8764     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8765   },
8766   {
8767     /* RM_0F01_REG_2 */
8768     { "xgetbv",         { Skip_MODRM }, 0 },
8769     { "xsetbv",         { Skip_MODRM }, 0 },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { "vmfunc",         { Skip_MODRM }, 0 },
8773     { "xend",           { Skip_MODRM }, 0 },
8774     { "xtest",          { Skip_MODRM }, 0 },
8775     { "enclu",          { Skip_MODRM }, 0 },
8776   },
8777   {
8778     /* RM_0F01_REG_3 */
8779     { "vmrun",          { Skip_MODRM }, 0 },
8780     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8781     { "vmload",         { Skip_MODRM }, 0 },
8782     { "vmsave",         { Skip_MODRM }, 0 },
8783     { "stgi",           { Skip_MODRM }, 0 },
8784     { "clgi",           { Skip_MODRM }, 0 },
8785     { "skinit",         { Skip_MODRM }, 0 },
8786     { "invlpga",        { Skip_MODRM }, 0 },
8787   },
8788   {
8789     /* RM_0F01_REG_5_MOD_3 */
8790     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8791     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8792     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8793     { Bad_Opcode },
8794     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8795     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8796     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8797     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8798   },
8799   {
8800     /* RM_0F01_REG_7_MOD_3 */
8801     { "swapgs",         { Skip_MODRM }, 0  },
8802     { "rdtscp",         { Skip_MODRM }, 0  },
8803     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8804     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8805     { "clzero",         { Skip_MODRM }, 0  },
8806     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8807     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8808     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8809   },
8810   {
8811     /* RM_0F1E_P_1_MOD_3_REG_7 */
8812     { "nopQ",           { Ev }, PREFIX_IGNORED },
8813     { "nopQ",           { Ev }, PREFIX_IGNORED },
8814     { "endbr64",        { Skip_MODRM }, 0 },
8815     { "endbr32",        { Skip_MODRM }, 0 },
8816     { "nopQ",           { Ev }, PREFIX_IGNORED },
8817     { "nopQ",           { Ev }, PREFIX_IGNORED },
8818     { "nopQ",           { Ev }, PREFIX_IGNORED },
8819     { "nopQ",           { Ev }, PREFIX_IGNORED },
8820   },
8821   {
8822     /* RM_0FAE_REG_6_MOD_3 */
8823     { "mfence",         { Skip_MODRM }, 0 },
8824   },
8825   {
8826     /* RM_0FAE_REG_7_MOD_3 */
8827     { "sfence",         { Skip_MODRM }, 0 },
8828   },
8829   {
8830     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8831     { "hreset",         { Skip_MODRM, Ib }, 0 },
8832   },
8833   {
8834     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8835     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8836   },
8837 };
8838
8839 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8840
8841 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8842    in conflict with actual prefix opcodes.  */
8843 #define REP_PREFIX      0x01
8844 #define XACQUIRE_PREFIX 0x02
8845 #define XRELEASE_PREFIX 0x03
8846 #define BND_PREFIX      0x04
8847 #define NOTRACK_PREFIX  0x05
8848
8849 static int
8850 ckprefix (instr_info *ins)
8851 {
8852   int newrex, i, length;
8853
8854   i = 0;
8855   length = 0;
8856   /* The maximum instruction length is 15bytes.  */
8857   while (length < MAX_CODE_LENGTH - 1)
8858     {
8859       FETCH_DATA (ins->info, ins->codep + 1);
8860       newrex = 0;
8861       switch (*ins->codep)
8862         {
8863         /* REX prefixes family.  */
8864         case 0x40:
8865         case 0x41:
8866         case 0x42:
8867         case 0x43:
8868         case 0x44:
8869         case 0x45:
8870         case 0x46:
8871         case 0x47:
8872         case 0x48:
8873         case 0x49:
8874         case 0x4a:
8875         case 0x4b:
8876         case 0x4c:
8877         case 0x4d:
8878         case 0x4e:
8879         case 0x4f:
8880           if (ins->address_mode == mode_64bit)
8881             newrex = *ins->codep;
8882           else
8883             return 1;
8884           ins->last_rex_prefix = i;
8885           break;
8886         case 0xf3:
8887           ins->prefixes |= PREFIX_REPZ;
8888           ins->last_repz_prefix = i;
8889           break;
8890         case 0xf2:
8891           ins->prefixes |= PREFIX_REPNZ;
8892           ins->last_repnz_prefix = i;
8893           break;
8894         case 0xf0:
8895           ins->prefixes |= PREFIX_LOCK;
8896           ins->last_lock_prefix = i;
8897           break;
8898         case 0x2e:
8899           ins->prefixes |= PREFIX_CS;
8900           ins->last_seg_prefix = i;
8901           if (ins->address_mode != mode_64bit)
8902             ins->active_seg_prefix = PREFIX_CS;
8903           break;
8904         case 0x36:
8905           ins->prefixes |= PREFIX_SS;
8906           ins->last_seg_prefix = i;
8907           if (ins->address_mode != mode_64bit)
8908             ins->active_seg_prefix = PREFIX_SS;
8909           break;
8910         case 0x3e:
8911           ins->prefixes |= PREFIX_DS;
8912           ins->last_seg_prefix = i;
8913           if (ins->address_mode != mode_64bit)
8914             ins->active_seg_prefix = PREFIX_DS;
8915           break;
8916         case 0x26:
8917           ins->prefixes |= PREFIX_ES;
8918           ins->last_seg_prefix = i;
8919           if (ins->address_mode != mode_64bit)
8920             ins->active_seg_prefix = PREFIX_ES;
8921           break;
8922         case 0x64:
8923           ins->prefixes |= PREFIX_FS;
8924           ins->last_seg_prefix = i;
8925           ins->active_seg_prefix = PREFIX_FS;
8926           break;
8927         case 0x65:
8928           ins->prefixes |= PREFIX_GS;
8929           ins->last_seg_prefix = i;
8930           ins->active_seg_prefix = PREFIX_GS;
8931           break;
8932         case 0x66:
8933           ins->prefixes |= PREFIX_DATA;
8934           ins->last_data_prefix = i;
8935           break;
8936         case 0x67:
8937           ins->prefixes |= PREFIX_ADDR;
8938           ins->last_addr_prefix = i;
8939           break;
8940         case FWAIT_OPCODE:
8941           /* fwait is really an instruction.  If there are prefixes
8942              before the fwait, they belong to the fwait, *not* to the
8943              following instruction.  */
8944           ins->fwait_prefix = i;
8945           if (ins->prefixes || ins->rex)
8946             {
8947               ins->prefixes |= PREFIX_FWAIT;
8948               ins->codep++;
8949               /* This ensures that the previous REX prefixes are noticed
8950                  as unused prefixes, as in the return case below.  */
8951               ins->rex_used = ins->rex;
8952               return 1;
8953             }
8954           ins->prefixes = PREFIX_FWAIT;
8955           break;
8956         default:
8957           return 1;
8958         }
8959       /* Rex is ignored when followed by another prefix.  */
8960       if (ins->rex)
8961         {
8962           ins->rex_used = ins->rex;
8963           return 1;
8964         }
8965       if (*ins->codep != FWAIT_OPCODE)
8966         ins->all_prefixes[i++] = *ins->codep;
8967       ins->rex = newrex;
8968       ins->codep++;
8969       length++;
8970     }
8971   return 0;
8972 }
8973
8974 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8975    prefix byte.  */
8976
8977 static const char *
8978 prefix_name (instr_info *ins, int pref, int sizeflag)
8979 {
8980   static const char *rexes [16] =
8981     {
8982       "rex",            /* 0x40 */
8983       "rex.B",          /* 0x41 */
8984       "rex.X",          /* 0x42 */
8985       "rex.XB",         /* 0x43 */
8986       "rex.R",          /* 0x44 */
8987       "rex.RB",         /* 0x45 */
8988       "rex.RX",         /* 0x46 */
8989       "rex.RXB",        /* 0x47 */
8990       "rex.W",          /* 0x48 */
8991       "rex.WB",         /* 0x49 */
8992       "rex.WX",         /* 0x4a */
8993       "rex.WXB",        /* 0x4b */
8994       "rex.WR",         /* 0x4c */
8995       "rex.WRB",        /* 0x4d */
8996       "rex.WRX",        /* 0x4e */
8997       "rex.WRXB",       /* 0x4f */
8998     };
8999
9000   switch (pref)
9001     {
9002     /* REX prefixes family.  */
9003     case 0x40:
9004     case 0x41:
9005     case 0x42:
9006     case 0x43:
9007     case 0x44:
9008     case 0x45:
9009     case 0x46:
9010     case 0x47:
9011     case 0x48:
9012     case 0x49:
9013     case 0x4a:
9014     case 0x4b:
9015     case 0x4c:
9016     case 0x4d:
9017     case 0x4e:
9018     case 0x4f:
9019       return rexes [pref - 0x40];
9020     case 0xf3:
9021       return "repz";
9022     case 0xf2:
9023       return "repnz";
9024     case 0xf0:
9025       return "lock";
9026     case 0x2e:
9027       return "cs";
9028     case 0x36:
9029       return "ss";
9030     case 0x3e:
9031       return "ds";
9032     case 0x26:
9033       return "es";
9034     case 0x64:
9035       return "fs";
9036     case 0x65:
9037       return "gs";
9038     case 0x66:
9039       return (sizeflag & DFLAG) ? "data16" : "data32";
9040     case 0x67:
9041       if (ins->address_mode == mode_64bit)
9042         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9043       else
9044         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9045     case FWAIT_OPCODE:
9046       return "fwait";
9047     case REP_PREFIX:
9048       return "rep";
9049     case XACQUIRE_PREFIX:
9050       return "xacquire";
9051     case XRELEASE_PREFIX:
9052       return "xrelease";
9053     case BND_PREFIX:
9054       return "bnd";
9055     case NOTRACK_PREFIX:
9056       return "notrack";
9057     default:
9058       return NULL;
9059     }
9060 }
9061
9062 void
9063 print_i386_disassembler_options (FILE *stream)
9064 {
9065   fprintf (stream, _("\n\
9066 The following i386/x86-64 specific disassembler options are supported for use\n\
9067 with the -M switch (multiple options should be separated by commas):\n"));
9068
9069   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9070   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9071   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9072   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9073   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9074   fprintf (stream, _("  att-mnemonic\n"
9075                      "              Display instruction in AT&T mnemonic\n"));
9076   fprintf (stream, _("  intel-mnemonic\n"
9077                      "              Display instruction in Intel mnemonic\n"));
9078   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9079   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9080   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9081   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9082   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9083   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9084   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
9085   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
9086 }
9087
9088 /* Bad opcode.  */
9089 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9090
9091 /* Get a pointer to struct dis386 with a valid name.  */
9092
9093 static const struct dis386 *
9094 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
9095 {
9096   int vindex, vex_table_index;
9097
9098   if (dp->name != NULL)
9099     return dp;
9100
9101   switch (dp->op[0].bytemode)
9102     {
9103     case USE_REG_TABLE:
9104       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
9105       break;
9106
9107     case USE_MOD_TABLE:
9108       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
9109       dp = &mod_table[dp->op[1].bytemode][vindex];
9110       break;
9111
9112     case USE_RM_TABLE:
9113       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
9114       break;
9115
9116     case USE_PREFIX_TABLE:
9117       if (ins->need_vex)
9118         {
9119           /* The prefix in VEX is implicit.  */
9120           switch (ins->vex.prefix)
9121             {
9122             case 0:
9123               vindex = 0;
9124               break;
9125             case REPE_PREFIX_OPCODE:
9126               vindex = 1;
9127               break;
9128             case DATA_PREFIX_OPCODE:
9129               vindex = 2;
9130               break;
9131             case REPNE_PREFIX_OPCODE:
9132               vindex = 3;
9133               break;
9134             default:
9135               abort ();
9136               break;
9137             }
9138         }
9139       else
9140         {
9141           int last_prefix = -1;
9142           int prefix = 0;
9143           vindex = 0;
9144           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9145              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9146              last one wins.  */
9147           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9148             {
9149               if (ins->last_repz_prefix > ins->last_repnz_prefix)
9150                 {
9151                   vindex = 1;
9152                   prefix = PREFIX_REPZ;
9153                   last_prefix = ins->last_repz_prefix;
9154                 }
9155               else
9156                 {
9157                   vindex = 3;
9158                   prefix = PREFIX_REPNZ;
9159                   last_prefix = ins->last_repnz_prefix;
9160                 }
9161
9162               /* Check if prefix should be ignored.  */
9163               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9164                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9165                    & prefix) != 0
9166                   && !prefix_table[dp->op[1].bytemode][vindex].name)
9167                 vindex = 0;
9168             }
9169
9170           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
9171             {
9172               vindex = 2;
9173               prefix = PREFIX_DATA;
9174               last_prefix = ins->last_data_prefix;
9175             }
9176
9177           if (vindex != 0)
9178             {
9179               ins->used_prefixes |= prefix;
9180               ins->all_prefixes[last_prefix] = 0;
9181             }
9182         }
9183       dp = &prefix_table[dp->op[1].bytemode][vindex];
9184       break;
9185
9186     case USE_X86_64_TABLE:
9187       vindex = ins->address_mode == mode_64bit ? 1 : 0;
9188       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9189       break;
9190
9191     case USE_3BYTE_TABLE:
9192       FETCH_DATA (ins->info, ins->codep + 2);
9193       vindex = *ins->codep++;
9194       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9195       ins->end_codep = ins->codep;
9196       ins->modrm.mod = (*ins->codep >> 6) & 3;
9197       ins->modrm.reg = (*ins->codep >> 3) & 7;
9198       ins->modrm.rm = *ins->codep & 7;
9199       break;
9200
9201     case USE_VEX_LEN_TABLE:
9202       if (!ins->need_vex)
9203         abort ();
9204
9205       switch (ins->vex.length)
9206         {
9207         case 128:
9208           vindex = 0;
9209           break;
9210         case 512:
9211           /* This allows re-using in particular table entries where only
9212              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
9213           if (ins->vex.evex)
9214             {
9215         case 256:
9216               vindex = 1;
9217               break;
9218             }
9219         /* Fall through.  */
9220         default:
9221           abort ();
9222           break;
9223         }
9224
9225       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9226       break;
9227
9228     case USE_EVEX_LEN_TABLE:
9229       if (!ins->vex.evex)
9230         abort ();
9231
9232       switch (ins->vex.length)
9233         {
9234         case 128:
9235           vindex = 0;
9236           break;
9237         case 256:
9238           vindex = 1;
9239           break;
9240         case 512:
9241           vindex = 2;
9242           break;
9243         default:
9244           abort ();
9245           break;
9246         }
9247
9248       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9249       break;
9250
9251     case USE_XOP_8F_TABLE:
9252       FETCH_DATA (ins->info, ins->codep + 3);
9253       ins->rex = ~(*ins->codep >> 5) & 0x7;
9254
9255       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9256       switch ((*ins->codep & 0x1f))
9257         {
9258         default:
9259           dp = &bad_opcode;
9260           return dp;
9261         case 0x8:
9262           vex_table_index = XOP_08;
9263           break;
9264         case 0x9:
9265           vex_table_index = XOP_09;
9266           break;
9267         case 0xa:
9268           vex_table_index = XOP_0A;
9269           break;
9270         }
9271       ins->codep++;
9272       ins->vex.w = *ins->codep & 0x80;
9273       if (ins->vex.w && ins->address_mode == mode_64bit)
9274         ins->rex |= REX_W;
9275
9276       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9277       if (ins->address_mode != mode_64bit)
9278         {
9279           /* In 16/32-bit mode REX_B is silently ignored.  */
9280           ins->rex &= ~REX_B;
9281         }
9282
9283       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9284       switch ((*ins->codep & 0x3))
9285         {
9286         case 0:
9287           break;
9288         case 1:
9289           ins->vex.prefix = DATA_PREFIX_OPCODE;
9290           break;
9291         case 2:
9292           ins->vex.prefix = REPE_PREFIX_OPCODE;
9293           break;
9294         case 3:
9295           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9296           break;
9297         }
9298       ins->need_vex = true;
9299       ins->codep++;
9300       vindex = *ins->codep++;
9301       dp = &xop_table[vex_table_index][vindex];
9302
9303       ins->end_codep = ins->codep;
9304       FETCH_DATA (ins->info, ins->codep + 1);
9305       ins->modrm.mod = (*ins->codep >> 6) & 3;
9306       ins->modrm.reg = (*ins->codep >> 3) & 7;
9307       ins->modrm.rm = *ins->codep & 7;
9308
9309       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9310          having to decode the bits for every otherwise valid encoding.  */
9311       if (ins->vex.prefix)
9312         return &bad_opcode;
9313       break;
9314
9315     case USE_VEX_C4_TABLE:
9316       /* VEX prefix.  */
9317       FETCH_DATA (ins->info, ins->codep + 3);
9318       ins->rex = ~(*ins->codep >> 5) & 0x7;
9319       switch ((*ins->codep & 0x1f))
9320         {
9321         default:
9322           dp = &bad_opcode;
9323           return dp;
9324         case 0x1:
9325           vex_table_index = VEX_0F;
9326           break;
9327         case 0x2:
9328           vex_table_index = VEX_0F38;
9329           break;
9330         case 0x3:
9331           vex_table_index = VEX_0F3A;
9332           break;
9333         }
9334       ins->codep++;
9335       ins->vex.w = *ins->codep & 0x80;
9336       if (ins->address_mode == mode_64bit)
9337         {
9338           if (ins->vex.w)
9339             ins->rex |= REX_W;
9340         }
9341       else
9342         {
9343           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9344              is ignored, other REX bits are 0 and the highest bit in
9345              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9346           ins->rex = 0;
9347         }
9348       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9349       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9350       switch ((*ins->codep & 0x3))
9351         {
9352         case 0:
9353           break;
9354         case 1:
9355           ins->vex.prefix = DATA_PREFIX_OPCODE;
9356           break;
9357         case 2:
9358           ins->vex.prefix = REPE_PREFIX_OPCODE;
9359           break;
9360         case 3:
9361           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9362           break;
9363         }
9364       ins->need_vex = true;
9365       ins->codep++;
9366       vindex = *ins->codep++;
9367       dp = &vex_table[vex_table_index][vindex];
9368       ins->end_codep = ins->codep;
9369       /* There is no MODRM byte for VEX0F 77.  */
9370       if (vex_table_index != VEX_0F || vindex != 0x77)
9371         {
9372           FETCH_DATA (ins->info, ins->codep + 1);
9373           ins->modrm.mod = (*ins->codep >> 6) & 3;
9374           ins->modrm.reg = (*ins->codep >> 3) & 7;
9375           ins->modrm.rm = *ins->codep & 7;
9376         }
9377       break;
9378
9379     case USE_VEX_C5_TABLE:
9380       /* VEX prefix.  */
9381       FETCH_DATA (ins->info, ins->codep + 2);
9382       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9383
9384       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9385          VEX.vvvv is 1.  */
9386       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9387       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9388       switch ((*ins->codep & 0x3))
9389         {
9390         case 0:
9391           break;
9392         case 1:
9393           ins->vex.prefix = DATA_PREFIX_OPCODE;
9394           break;
9395         case 2:
9396           ins->vex.prefix = REPE_PREFIX_OPCODE;
9397           break;
9398         case 3:
9399           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9400           break;
9401         }
9402       ins->need_vex = true;
9403       ins->codep++;
9404       vindex = *ins->codep++;
9405       dp = &vex_table[dp->op[1].bytemode][vindex];
9406       ins->end_codep = ins->codep;
9407       /* There is no MODRM byte for VEX 77.  */
9408       if (vindex != 0x77)
9409         {
9410           FETCH_DATA (ins->info, ins->codep + 1);
9411           ins->modrm.mod = (*ins->codep >> 6) & 3;
9412           ins->modrm.reg = (*ins->codep >> 3) & 7;
9413           ins->modrm.rm = *ins->codep & 7;
9414         }
9415       break;
9416
9417     case USE_VEX_W_TABLE:
9418       if (!ins->need_vex)
9419         abort ();
9420
9421       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9422       break;
9423
9424     case USE_EVEX_TABLE:
9425       ins->two_source_ops = false;
9426       /* EVEX prefix.  */
9427       ins->vex.evex = true;
9428       FETCH_DATA (ins->info, ins->codep + 4);
9429       /* The first byte after 0x62.  */
9430       ins->rex = ~(*ins->codep >> 5) & 0x7;
9431       ins->vex.r = *ins->codep & 0x10;
9432       switch ((*ins->codep & 0xf))
9433         {
9434         default:
9435           return &bad_opcode;
9436         case 0x1:
9437           vex_table_index = EVEX_0F;
9438           break;
9439         case 0x2:
9440           vex_table_index = EVEX_0F38;
9441           break;
9442         case 0x3:
9443           vex_table_index = EVEX_0F3A;
9444           break;
9445         case 0x5:
9446           vex_table_index = EVEX_MAP5;
9447           break;
9448         case 0x6:
9449           vex_table_index = EVEX_MAP6;
9450           break;
9451         }
9452
9453       /* The second byte after 0x62.  */
9454       ins->codep++;
9455       ins->vex.w = *ins->codep & 0x80;
9456       if (ins->vex.w && ins->address_mode == mode_64bit)
9457         ins->rex |= REX_W;
9458
9459       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9460
9461       /* The U bit.  */
9462       if (!(*ins->codep & 0x4))
9463         return &bad_opcode;
9464
9465       switch ((*ins->codep & 0x3))
9466         {
9467         case 0:
9468           break;
9469         case 1:
9470           ins->vex.prefix = DATA_PREFIX_OPCODE;
9471           break;
9472         case 2:
9473           ins->vex.prefix = REPE_PREFIX_OPCODE;
9474           break;
9475         case 3:
9476           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9477           break;
9478         }
9479
9480       /* The third byte after 0x62.  */
9481       ins->codep++;
9482
9483       /* Remember the static rounding bits.  */
9484       ins->vex.ll = (*ins->codep >> 5) & 3;
9485       ins->vex.b = *ins->codep & 0x10;
9486
9487       ins->vex.v = *ins->codep & 0x8;
9488       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9489       ins->vex.zeroing = *ins->codep & 0x80;
9490
9491       if (ins->address_mode != mode_64bit)
9492         {
9493           /* In 16/32-bit mode silently ignore following bits.  */
9494           ins->rex &= ~REX_B;
9495           ins->vex.r = true;
9496         }
9497
9498       ins->need_vex = true;
9499       ins->codep++;
9500       vindex = *ins->codep++;
9501       dp = &evex_table[vex_table_index][vindex];
9502       ins->end_codep = ins->codep;
9503       FETCH_DATA (ins->info, ins->codep + 1);
9504       ins->modrm.mod = (*ins->codep >> 6) & 3;
9505       ins->modrm.reg = (*ins->codep >> 3) & 7;
9506       ins->modrm.rm = *ins->codep & 7;
9507
9508       /* Set vector length.  */
9509       if (ins->modrm.mod == 3 && ins->vex.b)
9510         ins->vex.length = 512;
9511       else
9512         {
9513           switch (ins->vex.ll)
9514             {
9515             case 0x0:
9516               ins->vex.length = 128;
9517               break;
9518             case 0x1:
9519               ins->vex.length = 256;
9520               break;
9521             case 0x2:
9522               ins->vex.length = 512;
9523               break;
9524             default:
9525               return &bad_opcode;
9526             }
9527         }
9528       break;
9529
9530     case 0:
9531       dp = &bad_opcode;
9532       break;
9533
9534     default:
9535       abort ();
9536     }
9537
9538   if (dp->name != NULL)
9539     return dp;
9540   else
9541     return get_valid_dis386 (dp, ins);
9542 }
9543
9544 static void
9545 get_sib (instr_info *ins, int sizeflag)
9546 {
9547   /* If modrm.mod == 3, operand must be register.  */
9548   if (ins->need_modrm
9549       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9550       && ins->modrm.mod != 3
9551       && ins->modrm.rm == 4)
9552     {
9553       FETCH_DATA (ins->info, ins->codep + 2);
9554       ins->sib.index = (ins->codep[1] >> 3) & 7;
9555       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9556       ins->sib.base = ins->codep[1] & 7;
9557       ins->has_sib = true;
9558     }
9559   else
9560     ins->has_sib = false;
9561 }
9562
9563 /* Like oappend (below), but S is a string starting with '%'.  In
9564    Intel syntax, the '%' is elided.  */
9565
9566 static void
9567 oappend_register (instr_info *ins, const char *s)
9568 {
9569   oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9570 }
9571
9572 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9573    STYLE is the default style to use in the fprintf_styled_func calls,
9574    however, FMT might include embedded style markers (see oappend_style),
9575    these embedded markers are not printed, but instead change the style
9576    used in the next fprintf_styled_func call.  */
9577
9578 static void ATTRIBUTE_PRINTF_3
9579 i386_dis_printf (instr_info *ins, enum disassembler_style style,
9580                  const char *fmt, ...)
9581 {
9582   va_list ap;
9583   enum disassembler_style curr_style = style;
9584   const char *start, *curr;
9585   char staging_area[40];
9586
9587   va_start (ap, fmt);
9588   /* In particular print_insn()'s processing of op_txt[] can hand rather long
9589      strings here.  Bypass vsnprintf() in such cases to avoid capacity issues
9590      with the staging area.  */
9591   if (strcmp (fmt, "%s"))
9592     {
9593       int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9594
9595       va_end (ap);
9596
9597       if (res < 0)
9598         return;
9599
9600       if ((size_t) res >= sizeof (staging_area))
9601         abort ();
9602
9603       start = curr = staging_area;
9604     }
9605   else
9606     {
9607       start = curr = va_arg (ap, const char *);
9608       va_end (ap);
9609     }
9610
9611   do
9612     {
9613       if (*curr == '\0'
9614           || (*curr == STYLE_MARKER_CHAR
9615               && ISXDIGIT (*(curr + 1))
9616               && *(curr + 2) == STYLE_MARKER_CHAR))
9617         {
9618           /* Output content between our START position and CURR.  */
9619           int len = curr - start;
9620           int n = (*ins->info->fprintf_styled_func) (ins->info->stream,
9621                                                      curr_style,
9622                                                      "%.*s", len, start);
9623           if (n < 0)
9624             break;
9625
9626           if (*curr == '\0')
9627             break;
9628
9629           /* Skip over the initial STYLE_MARKER_CHAR.  */
9630           ++curr;
9631
9632           /* Update the CURR_STYLE.  As there are less than 16 styles, it
9633              is possible, that if the input is corrupted in some way, that
9634              we might set CURR_STYLE to an invalid value.  Don't worry
9635              though, we check for this situation.  */
9636           if (*curr >= '0' && *curr <= '9')
9637             curr_style = (enum disassembler_style) (*curr - '0');
9638           else if (*curr >= 'a' && *curr <= 'f')
9639             curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9640           else
9641             curr_style = dis_style_text;
9642
9643           /* Check for an invalid style having been selected.  This should
9644              never happen, but it doesn't hurt to be a little paranoid.  */
9645           if (curr_style > dis_style_comment_start)
9646             curr_style = dis_style_text;
9647
9648           /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9649           curr += 2;
9650
9651           /* Reset the START to after the style marker.  */
9652           start = curr;
9653         }
9654       else
9655         ++curr;
9656     }
9657   while (true);
9658 }
9659
9660 static int
9661 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9662 {
9663   const struct dis386 *dp;
9664   int i;
9665   char *op_txt[MAX_OPERANDS];
9666   int needcomma;
9667   bool intel_swap_2_3;
9668   int sizeflag, orig_sizeflag;
9669   const char *p;
9670   struct dis_private priv;
9671   int prefix_length;
9672   int op_count;
9673   instr_info ins = {
9674     .info = info,
9675     .intel_syntax = intel_syntax >= 0
9676                     ? intel_syntax
9677                     : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9678     .intel_mnemonic = !SYSV386_COMPAT,
9679     .op_index[0 ... MAX_OPERANDS - 1] = -1,
9680     .start_pc = pc,
9681     .start_codep = priv.the_buffer,
9682     .codep = priv.the_buffer,
9683     .obufp = ins.obuf,
9684     .last_lock_prefix = -1,
9685     .last_repz_prefix = -1,
9686     .last_repnz_prefix = -1,
9687     .last_data_prefix = -1,
9688     .last_addr_prefix = -1,
9689     .last_rex_prefix = -1,
9690     .last_seg_prefix = -1,
9691     .fwait_prefix = -1,
9692   };
9693   char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9694
9695   priv.orig_sizeflag = AFLAG | DFLAG;
9696   if ((info->mach & bfd_mach_i386_i386) != 0)
9697     ins.address_mode = mode_32bit;
9698   else if (info->mach == bfd_mach_i386_i8086)
9699     {
9700       ins.address_mode = mode_16bit;
9701       priv.orig_sizeflag = 0;
9702     }
9703   else
9704     ins.address_mode = mode_64bit;
9705
9706   for (p = info->disassembler_options; p != NULL;)
9707     {
9708       if (startswith (p, "amd64"))
9709         ins.isa64 = amd64;
9710       else if (startswith (p, "intel64"))
9711         ins.isa64 = intel64;
9712       else if (startswith (p, "x86-64"))
9713         {
9714           ins.address_mode = mode_64bit;
9715           priv.orig_sizeflag |= AFLAG | DFLAG;
9716         }
9717       else if (startswith (p, "i386"))
9718         {
9719           ins.address_mode = mode_32bit;
9720           priv.orig_sizeflag |= AFLAG | DFLAG;
9721         }
9722       else if (startswith (p, "i8086"))
9723         {
9724           ins.address_mode = mode_16bit;
9725           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9726         }
9727       else if (startswith (p, "intel"))
9728         {
9729           ins.intel_syntax = 1;
9730           if (startswith (p + 5, "-mnemonic"))
9731             ins.intel_mnemonic = true;
9732         }
9733       else if (startswith (p, "att"))
9734         {
9735           ins.intel_syntax = 0;
9736           if (startswith (p + 3, "-mnemonic"))
9737             ins.intel_mnemonic = false;
9738         }
9739       else if (startswith (p, "addr"))
9740         {
9741           if (ins.address_mode == mode_64bit)
9742             {
9743               if (p[4] == '3' && p[5] == '2')
9744                 priv.orig_sizeflag &= ~AFLAG;
9745               else if (p[4] == '6' && p[5] == '4')
9746                 priv.orig_sizeflag |= AFLAG;
9747             }
9748           else
9749             {
9750               if (p[4] == '1' && p[5] == '6')
9751                 priv.orig_sizeflag &= ~AFLAG;
9752               else if (p[4] == '3' && p[5] == '2')
9753                 priv.orig_sizeflag |= AFLAG;
9754             }
9755         }
9756       else if (startswith (p, "data"))
9757         {
9758           if (p[4] == '1' && p[5] == '6')
9759             priv.orig_sizeflag &= ~DFLAG;
9760           else if (p[4] == '3' && p[5] == '2')
9761             priv.orig_sizeflag |= DFLAG;
9762         }
9763       else if (startswith (p, "suffix"))
9764         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9765
9766       p = strchr (p, ',');
9767       if (p != NULL)
9768         p++;
9769     }
9770
9771   if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9772     {
9773       i386_dis_printf (&ins, dis_style_text, _("64-bit address is disabled"));
9774       return -1;
9775     }
9776
9777   if (ins.intel_syntax)
9778     {
9779       ins.open_char = '[';
9780       ins.close_char = ']';
9781       ins.separator_char = '+';
9782       ins.scale_char = '*';
9783     }
9784   else
9785     {
9786       ins.open_char = '(';
9787       ins.close_char =  ')';
9788       ins.separator_char = ',';
9789       ins.scale_char = ',';
9790     }
9791
9792   /* The output looks better if we put 7 bytes on a line, since that
9793      puts most long word instructions on a single line.  */
9794   info->bytes_per_line = 7;
9795
9796   info->private_data = &priv;
9797   priv.max_fetched = priv.the_buffer;
9798   priv.insn_start = pc;
9799
9800   for (i = 0; i < MAX_OPERANDS; ++i)
9801     {
9802       op_out[i][0] = 0;
9803       ins.op_out[i] = op_out[i];
9804     }
9805
9806   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9807     {
9808       /* Getting here means we tried for data but didn't get it.  That
9809          means we have an incomplete instruction of some sort.  Just
9810          print the first byte as a prefix or a .byte pseudo-op.  */
9811       if (ins.codep > priv.the_buffer)
9812         {
9813           const char *name = NULL;
9814
9815           if (ins.prefixes || ins.fwait_prefix >= 0 || (ins.rex & REX_OPCODE))
9816             name = prefix_name (&ins, priv.the_buffer[0], priv.orig_sizeflag);
9817           if (name != NULL)
9818             i386_dis_printf (&ins, dis_style_mnemonic, "%s", name);
9819           else
9820             {
9821               /* Just print the first byte as a .byte instruction.  */
9822               i386_dis_printf (&ins, dis_style_assembler_directive,
9823                                ".byte ");
9824               i386_dis_printf (&ins, dis_style_immediate, "0x%x",
9825                                (unsigned int) priv.the_buffer[0]);
9826             }
9827
9828           return 1;
9829         }
9830
9831       return -1;
9832     }
9833
9834   sizeflag = priv.orig_sizeflag;
9835
9836   if (!ckprefix (&ins) || ins.rex_used)
9837     {
9838       /* Too many prefixes or unused REX prefixes.  */
9839       for (i = 0;
9840            i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9841            i++)
9842         i386_dis_printf (&ins, dis_style_mnemonic, "%s%s",
9843                          (i == 0 ? "" : " "),
9844                          prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9845       return i;
9846     }
9847
9848   ins.insn_codep = ins.codep;
9849
9850   FETCH_DATA (info, ins.codep + 1);
9851   ins.two_source_ops = (*ins.codep == 0x62) || (*ins.codep == 0xc8);
9852
9853   if (((ins.prefixes & PREFIX_FWAIT)
9854        && ((*ins.codep < 0xd8) || (*ins.codep > 0xdf))))
9855     {
9856       /* Handle ins.prefixes before fwait.  */
9857       for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9858            i++)
9859         i386_dis_printf (&ins, dis_style_mnemonic, "%s ",
9860                          prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9861       i386_dis_printf (&ins, dis_style_mnemonic, "fwait");
9862       return i + 1;
9863     }
9864
9865   if (*ins.codep == 0x0f)
9866     {
9867       unsigned char threebyte;
9868
9869       ins.codep++;
9870       FETCH_DATA (info, ins.codep + 1);
9871       threebyte = *ins.codep;
9872       dp = &dis386_twobyte[threebyte];
9873       ins.need_modrm = twobyte_has_modrm[threebyte];
9874       ins.codep++;
9875     }
9876   else
9877     {
9878       dp = &dis386[*ins.codep];
9879       ins.need_modrm = onebyte_has_modrm[*ins.codep];
9880       ins.codep++;
9881     }
9882
9883   /* Save sizeflag for printing the extra ins.prefixes later before updating
9884      it for mnemonic and operand processing.  The prefix names depend
9885      only on the address mode.  */
9886   orig_sizeflag = sizeflag;
9887   if (ins.prefixes & PREFIX_ADDR)
9888     sizeflag ^= AFLAG;
9889   if ((ins.prefixes & PREFIX_DATA))
9890     sizeflag ^= DFLAG;
9891
9892   ins.end_codep = ins.codep;
9893   if (ins.need_modrm)
9894     {
9895       FETCH_DATA (info, ins.codep + 1);
9896       ins.modrm.mod = (*ins.codep >> 6) & 3;
9897       ins.modrm.reg = (*ins.codep >> 3) & 7;
9898       ins.modrm.rm = *ins.codep & 7;
9899     }
9900
9901   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9902     {
9903       get_sib (&ins, sizeflag);
9904       dofloat (&ins, sizeflag);
9905     }
9906   else
9907     {
9908       dp = get_valid_dis386 (dp, &ins);
9909       if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9910         {
9911           get_sib (&ins, sizeflag);
9912           for (i = 0; i < MAX_OPERANDS; ++i)
9913             {
9914               ins.obufp = ins.op_out[i];
9915               ins.op_ad = MAX_OPERANDS - 1 - i;
9916               if (dp->op[i].rtn)
9917                 (*dp->op[i].rtn) (&ins, dp->op[i].bytemode, sizeflag);
9918               /* For EVEX instruction after the last operand masking
9919                  should be printed.  */
9920               if (i == 0 && ins.vex.evex)
9921                 {
9922                   /* Don't print {%k0}.  */
9923                   if (ins.vex.mask_register_specifier)
9924                     {
9925                       const char *reg_name
9926                         = att_names_mask[ins.vex.mask_register_specifier];
9927
9928                       oappend (&ins, "{");
9929                       oappend_register (&ins, reg_name);
9930                       oappend (&ins, "}");
9931                     }
9932                   if (ins.vex.zeroing)
9933                     oappend (&ins, "{z}");
9934
9935                   /* S/G insns require a mask and don't allow
9936                      zeroing-masking.  */
9937                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9938                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9939                       && (ins.vex.mask_register_specifier == 0
9940                           || ins.vex.zeroing))
9941                     oappend (&ins, "/(bad)");
9942                 }
9943             }
9944
9945           /* Check whether rounding control was enabled for an insn not
9946              supporting it.  */
9947           if (ins.modrm.mod == 3 && ins.vex.b
9948               && !(ins.evex_used & EVEX_b_used))
9949             {
9950               for (i = 0; i < MAX_OPERANDS; ++i)
9951                 {
9952                   ins.obufp = ins.op_out[i];
9953                   if (*ins.obufp)
9954                     continue;
9955                   oappend (&ins, names_rounding[ins.vex.ll]);
9956                   oappend (&ins, "bad}");
9957                   break;
9958                 }
9959             }
9960         }
9961     }
9962
9963   /* Clear instruction information.  */
9964   info->insn_info_valid = 0;
9965   info->branch_delay_insns = 0;
9966   info->data_size = 0;
9967   info->insn_type = dis_noninsn;
9968   info->target = 0;
9969   info->target2 = 0;
9970
9971   /* Reset jump operation indicator.  */
9972   ins.op_is_jump = false;
9973   {
9974     int jump_detection = 0;
9975
9976     /* Extract flags.  */
9977     for (i = 0; i < MAX_OPERANDS; ++i)
9978       {
9979         if ((dp->op[i].rtn == OP_J)
9980             || (dp->op[i].rtn == OP_indirE))
9981           jump_detection |= 1;
9982         else if ((dp->op[i].rtn == BND_Fixup)
9983                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9984           jump_detection |= 2;
9985         else if ((dp->op[i].bytemode == cond_jump_mode)
9986                  || (dp->op[i].bytemode == loop_jcxz_mode))
9987           jump_detection |= 4;
9988       }
9989
9990     /* Determine if this is a jump or branch.  */
9991     if ((jump_detection & 0x3) == 0x3)
9992       {
9993         ins.op_is_jump = true;
9994         if (jump_detection & 0x4)
9995           info->insn_type = dis_condbranch;
9996         else
9997           info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9998             ? dis_jsr : dis_branch;
9999       }
10000   }
10001
10002   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10003      are all 0s in inverted form.  */
10004   if (ins.need_vex && ins.vex.register_specifier != 0)
10005     {
10006       i386_dis_printf (&ins, dis_style_text, "(bad)");
10007       return ins.end_codep - priv.the_buffer;
10008     }
10009
10010   /* If EVEX.z is set, there must be an actual mask register in use.  */
10011   if (ins.vex.zeroing && ins.vex.mask_register_specifier == 0)
10012     {
10013       i386_dis_printf (&ins, dis_style_text, "(bad)");
10014       return ins.end_codep - priv.the_buffer;
10015     }
10016
10017   switch (dp->prefix_requirement)
10018     {
10019     case PREFIX_DATA:
10020       /* If only the data prefix is marked as mandatory, its absence renders
10021          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
10022       if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
10023         {
10024           i386_dis_printf (&ins, dis_style_text, "(bad)");
10025           return ins.end_codep - priv.the_buffer;
10026         }
10027       ins.used_prefixes |= PREFIX_DATA;
10028       /* Fall through.  */
10029     case PREFIX_OPCODE:
10030       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10031          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
10032          used by putop and MMX/SSE operand and may be overridden by the
10033          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10034          separately.  */
10035       if (((ins.need_vex
10036             ? ins.vex.prefix == REPE_PREFIX_OPCODE
10037               || ins.vex.prefix == REPNE_PREFIX_OPCODE
10038             : (ins.prefixes
10039                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10040            && (ins.used_prefixes
10041                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10042           || (((ins.need_vex
10043                 ? ins.vex.prefix == DATA_PREFIX_OPCODE
10044                 : ((ins.prefixes
10045                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10046                    == PREFIX_DATA))
10047                && (ins.used_prefixes & PREFIX_DATA) == 0))
10048           || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
10049               && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
10050         {
10051           i386_dis_printf (&ins, dis_style_text, "(bad)");
10052           return ins.end_codep - priv.the_buffer;
10053         }
10054       break;
10055
10056     case PREFIX_IGNORED:
10057       /* Zap data size and rep prefixes from used_prefixes and reinstate their
10058          origins in all_prefixes.  */
10059       ins.used_prefixes &= ~PREFIX_OPCODE;
10060       if (ins.last_data_prefix >= 0)
10061         ins.all_prefixes[ins.last_data_prefix] = 0x66;
10062       if (ins.last_repz_prefix >= 0)
10063         ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
10064       if (ins.last_repnz_prefix >= 0)
10065         ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
10066       break;
10067     }
10068
10069   /* Check if the REX prefix is used.  */
10070   if ((ins.rex ^ ins.rex_used) == 0
10071       && !ins.need_vex && ins.last_rex_prefix >= 0)
10072     ins.all_prefixes[ins.last_rex_prefix] = 0;
10073
10074   /* Check if the SEG prefix is used.  */
10075   if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10076                        | PREFIX_FS | PREFIX_GS)) != 0
10077       && (ins.used_prefixes & ins.active_seg_prefix) != 0)
10078     ins.all_prefixes[ins.last_seg_prefix] = 0;
10079
10080   /* Check if the ADDR prefix is used.  */
10081   if ((ins.prefixes & PREFIX_ADDR) != 0
10082       && (ins.used_prefixes & PREFIX_ADDR) != 0)
10083     ins.all_prefixes[ins.last_addr_prefix] = 0;
10084
10085   /* Check if the DATA prefix is used.  */
10086   if ((ins.prefixes & PREFIX_DATA) != 0
10087       && (ins.used_prefixes & PREFIX_DATA) != 0
10088       && !ins.need_vex)
10089     ins.all_prefixes[ins.last_data_prefix] = 0;
10090
10091   /* Print the extra ins.prefixes.  */
10092   prefix_length = 0;
10093   for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
10094     if (ins.all_prefixes[i])
10095       {
10096         const char *name;
10097         name = prefix_name (&ins, ins.all_prefixes[i], orig_sizeflag);
10098         if (name == NULL)
10099           abort ();
10100         prefix_length += strlen (name) + 1;
10101         i386_dis_printf (&ins, dis_style_mnemonic, "%s ", name);
10102       }
10103
10104   /* Check maximum code length.  */
10105   if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
10106     {
10107       i386_dis_printf (&ins, dis_style_text, "(bad)");
10108       return MAX_CODE_LENGTH;
10109     }
10110
10111   /* Calculate the number of operands this instruction has.  */
10112   op_count = 0;
10113   for (i = 0; i < MAX_OPERANDS; ++i)
10114     if (*ins.op_out[i] != '\0')
10115       ++op_count;
10116
10117   /* Calculate the number of spaces to print after the mnemonic.  */
10118   ins.obufp = ins.mnemonicendp;
10119   if (op_count > 0)
10120     {
10121       i = strlen (ins.obuf) + prefix_length;
10122       if (i < 7)
10123         i = 7 - i;
10124       else
10125         i = 1;
10126     }
10127   else
10128     i = 0;
10129
10130   /* Print the instruction mnemonic along with any trailing whitespace.  */
10131   i386_dis_printf (&ins, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
10132
10133   /* The enter and bound instructions are printed with operands in the same
10134      order as the intel book; everything else is printed in reverse order.  */
10135   intel_swap_2_3 = false;
10136   if (ins.intel_syntax || ins.two_source_ops)
10137     {
10138       for (i = 0; i < MAX_OPERANDS; ++i)
10139         op_txt[i] = ins.op_out[i];
10140
10141       if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10142           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10143         {
10144           op_txt[2] = ins.op_out[3];
10145           op_txt[3] = ins.op_out[2];
10146           intel_swap_2_3 = true;
10147         }
10148
10149       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10150         {
10151           bool riprel;
10152
10153           ins.op_ad = ins.op_index[i];
10154           ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
10155           ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
10156           riprel = ins.op_riprel[i];
10157           ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
10158           ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10159         }
10160     }
10161   else
10162     {
10163       for (i = 0; i < MAX_OPERANDS; ++i)
10164         op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
10165     }
10166
10167   needcomma = 0;
10168   for (i = 0; i < MAX_OPERANDS; ++i)
10169     if (*op_txt[i])
10170       {
10171         /* In Intel syntax embedded rounding / SAE are not separate operands.
10172            Instead they're attached to the prior register operand.  Simply
10173            suppress emission of the comma to achieve that effect.  */
10174         switch (i & -(ins.intel_syntax && dp))
10175           {
10176           case 2:
10177             if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
10178               needcomma = 0;
10179             break;
10180           case 3:
10181             if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
10182               needcomma = 0;
10183             break;
10184           }
10185         if (needcomma)
10186           i386_dis_printf (&ins, dis_style_text, ",");
10187         if (ins.op_index[i] != -1 && !ins.op_riprel[i])
10188           {
10189             bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
10190
10191             if (ins.op_is_jump)
10192               {
10193                 info->insn_info_valid = 1;
10194                 info->branch_delay_insns = 0;
10195                 info->data_size = 0;
10196                 info->target = target;
10197                 info->target2 = 0;
10198               }
10199             (*info->print_address_func) (target, info);
10200           }
10201         else
10202           i386_dis_printf (&ins, dis_style_text, "%s", op_txt[i]);
10203         needcomma = 1;
10204       }
10205
10206   for (i = 0; i < MAX_OPERANDS; i++)
10207     if (ins.op_index[i] != -1 && ins.op_riprel[i])
10208       {
10209         i386_dis_printf (&ins, dis_style_comment_start, "        # ");
10210         (*info->print_address_func)
10211           ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
10212                      + ins.op_address[ins.op_index[i]]),
10213           info);
10214         break;
10215       }
10216   return ins.codep - priv.the_buffer;
10217 }
10218
10219 /* Here for backwards compatibility.  When gdb stops using
10220    print_insn_i386_att and print_insn_i386_intel these functions can
10221    disappear, and print_insn_i386 be merged into print_insn.  */
10222 int
10223 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10224 {
10225   return print_insn (pc, info, 0);
10226 }
10227
10228 int
10229 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10230 {
10231   return print_insn (pc, info, 1);
10232 }
10233
10234 int
10235 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10236 {
10237   return print_insn (pc, info, -1);
10238 }
10239
10240 static const char *float_mem[] = {
10241   /* d8 */
10242   "fadd{s|}",
10243   "fmul{s|}",
10244   "fcom{s|}",
10245   "fcomp{s|}",
10246   "fsub{s|}",
10247   "fsubr{s|}",
10248   "fdiv{s|}",
10249   "fdivr{s|}",
10250   /* d9 */
10251   "fld{s|}",
10252   "(bad)",
10253   "fst{s|}",
10254   "fstp{s|}",
10255   "fldenv{C|C}",
10256   "fldcw",
10257   "fNstenv{C|C}",
10258   "fNstcw",
10259   /* da */
10260   "fiadd{l|}",
10261   "fimul{l|}",
10262   "ficom{l|}",
10263   "ficomp{l|}",
10264   "fisub{l|}",
10265   "fisubr{l|}",
10266   "fidiv{l|}",
10267   "fidivr{l|}",
10268   /* db */
10269   "fild{l|}",
10270   "fisttp{l|}",
10271   "fist{l|}",
10272   "fistp{l|}",
10273   "(bad)",
10274   "fld{t|}",
10275   "(bad)",
10276   "fstp{t|}",
10277   /* dc */
10278   "fadd{l|}",
10279   "fmul{l|}",
10280   "fcom{l|}",
10281   "fcomp{l|}",
10282   "fsub{l|}",
10283   "fsubr{l|}",
10284   "fdiv{l|}",
10285   "fdivr{l|}",
10286   /* dd */
10287   "fld{l|}",
10288   "fisttp{ll|}",
10289   "fst{l||}",
10290   "fstp{l|}",
10291   "frstor{C|C}",
10292   "(bad)",
10293   "fNsave{C|C}",
10294   "fNstsw",
10295   /* de */
10296   "fiadd{s|}",
10297   "fimul{s|}",
10298   "ficom{s|}",
10299   "ficomp{s|}",
10300   "fisub{s|}",
10301   "fisubr{s|}",
10302   "fidiv{s|}",
10303   "fidivr{s|}",
10304   /* df */
10305   "fild{s|}",
10306   "fisttp{s|}",
10307   "fist{s|}",
10308   "fistp{s|}",
10309   "fbld",
10310   "fild{ll|}",
10311   "fbstp",
10312   "fistp{ll|}",
10313 };
10314
10315 static const unsigned char float_mem_mode[] = {
10316   /* d8 */
10317   d_mode,
10318   d_mode,
10319   d_mode,
10320   d_mode,
10321   d_mode,
10322   d_mode,
10323   d_mode,
10324   d_mode,
10325   /* d9 */
10326   d_mode,
10327   0,
10328   d_mode,
10329   d_mode,
10330   0,
10331   w_mode,
10332   0,
10333   w_mode,
10334   /* da */
10335   d_mode,
10336   d_mode,
10337   d_mode,
10338   d_mode,
10339   d_mode,
10340   d_mode,
10341   d_mode,
10342   d_mode,
10343   /* db */
10344   d_mode,
10345   d_mode,
10346   d_mode,
10347   d_mode,
10348   0,
10349   t_mode,
10350   0,
10351   t_mode,
10352   /* dc */
10353   q_mode,
10354   q_mode,
10355   q_mode,
10356   q_mode,
10357   q_mode,
10358   q_mode,
10359   q_mode,
10360   q_mode,
10361   /* dd */
10362   q_mode,
10363   q_mode,
10364   q_mode,
10365   q_mode,
10366   0,
10367   0,
10368   0,
10369   w_mode,
10370   /* de */
10371   w_mode,
10372   w_mode,
10373   w_mode,
10374   w_mode,
10375   w_mode,
10376   w_mode,
10377   w_mode,
10378   w_mode,
10379   /* df */
10380   w_mode,
10381   w_mode,
10382   w_mode,
10383   w_mode,
10384   t_mode,
10385   q_mode,
10386   t_mode,
10387   q_mode
10388 };
10389
10390 #define ST { OP_ST, 0 }
10391 #define STi { OP_STi, 0 }
10392
10393 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10394 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10395 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10396 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10397 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10398 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10399 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10400 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10401 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10402
10403 static const struct dis386 float_reg[][8] = {
10404   /* d8 */
10405   {
10406     { "fadd",   { ST, STi }, 0 },
10407     { "fmul",   { ST, STi }, 0 },
10408     { "fcom",   { STi }, 0 },
10409     { "fcomp",  { STi }, 0 },
10410     { "fsub",   { ST, STi }, 0 },
10411     { "fsubr",  { ST, STi }, 0 },
10412     { "fdiv",   { ST, STi }, 0 },
10413     { "fdivr",  { ST, STi }, 0 },
10414   },
10415   /* d9 */
10416   {
10417     { "fld",    { STi }, 0 },
10418     { "fxch",   { STi }, 0 },
10419     { FGRPd9_2 },
10420     { Bad_Opcode },
10421     { FGRPd9_4 },
10422     { FGRPd9_5 },
10423     { FGRPd9_6 },
10424     { FGRPd9_7 },
10425   },
10426   /* da */
10427   {
10428     { "fcmovb", { ST, STi }, 0 },
10429     { "fcmove", { ST, STi }, 0 },
10430     { "fcmovbe",{ ST, STi }, 0 },
10431     { "fcmovu", { ST, STi }, 0 },
10432     { Bad_Opcode },
10433     { FGRPda_5 },
10434     { Bad_Opcode },
10435     { Bad_Opcode },
10436   },
10437   /* db */
10438   {
10439     { "fcmovnb",{ ST, STi }, 0 },
10440     { "fcmovne",{ ST, STi }, 0 },
10441     { "fcmovnbe",{ ST, STi }, 0 },
10442     { "fcmovnu",{ ST, STi }, 0 },
10443     { FGRPdb_4 },
10444     { "fucomi", { ST, STi }, 0 },
10445     { "fcomi",  { ST, STi }, 0 },
10446     { Bad_Opcode },
10447   },
10448   /* dc */
10449   {
10450     { "fadd",   { STi, ST }, 0 },
10451     { "fmul",   { STi, ST }, 0 },
10452     { Bad_Opcode },
10453     { Bad_Opcode },
10454     { "fsub{!M|r}",     { STi, ST }, 0 },
10455     { "fsub{M|}",       { STi, ST }, 0 },
10456     { "fdiv{!M|r}",     { STi, ST }, 0 },
10457     { "fdiv{M|}",       { STi, ST }, 0 },
10458   },
10459   /* dd */
10460   {
10461     { "ffree",  { STi }, 0 },
10462     { Bad_Opcode },
10463     { "fst",    { STi }, 0 },
10464     { "fstp",   { STi }, 0 },
10465     { "fucom",  { STi }, 0 },
10466     { "fucomp", { STi }, 0 },
10467     { Bad_Opcode },
10468     { Bad_Opcode },
10469   },
10470   /* de */
10471   {
10472     { "faddp",  { STi, ST }, 0 },
10473     { "fmulp",  { STi, ST }, 0 },
10474     { Bad_Opcode },
10475     { FGRPde_3 },
10476     { "fsub{!M|r}p",    { STi, ST }, 0 },
10477     { "fsub{M|}p",      { STi, ST }, 0 },
10478     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10479     { "fdiv{M|}p",      { STi, ST }, 0 },
10480   },
10481   /* df */
10482   {
10483     { "ffreep", { STi }, 0 },
10484     { Bad_Opcode },
10485     { Bad_Opcode },
10486     { Bad_Opcode },
10487     { FGRPdf_4 },
10488     { "fucomip", { ST, STi }, 0 },
10489     { "fcomip", { ST, STi }, 0 },
10490     { Bad_Opcode },
10491   },
10492 };
10493
10494 static const char *const fgrps[][8] = {
10495   /* Bad opcode 0 */
10496   {
10497     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10498   },
10499
10500   /* d9_2  1 */
10501   {
10502     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10503   },
10504
10505   /* d9_4  2 */
10506   {
10507     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10508   },
10509
10510   /* d9_5  3 */
10511   {
10512     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10513   },
10514
10515   /* d9_6  4 */
10516   {
10517     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10518   },
10519
10520   /* d9_7  5 */
10521   {
10522     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10523   },
10524
10525   /* da_5  6 */
10526   {
10527     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10528   },
10529
10530   /* db_4  7 */
10531   {
10532     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10533     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10534   },
10535
10536   /* de_3  8 */
10537   {
10538     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10539   },
10540
10541   /* df_4  9 */
10542   {
10543     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10544   },
10545 };
10546
10547 static void
10548 swap_operand (instr_info *ins)
10549 {
10550   ins->mnemonicendp[0] = '.';
10551   ins->mnemonicendp[1] = 's';
10552   ins->mnemonicendp[2] = '\0';
10553   ins->mnemonicendp += 2;
10554 }
10555
10556 static void
10557 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10558                int sizeflag ATTRIBUTE_UNUSED)
10559 {
10560   /* Skip mod/rm byte.  */
10561   MODRM_CHECK;
10562   ins->codep++;
10563 }
10564
10565 static void
10566 dofloat (instr_info *ins, int sizeflag)
10567 {
10568   const struct dis386 *dp;
10569   unsigned char floatop;
10570
10571   floatop = ins->codep[-1];
10572
10573   if (ins->modrm.mod != 3)
10574     {
10575       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10576
10577       putop (ins, float_mem[fp_indx], sizeflag);
10578       ins->obufp = ins->op_out[0];
10579       ins->op_ad = 2;
10580       OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10581       return;
10582     }
10583   /* Skip mod/rm byte.  */
10584   MODRM_CHECK;
10585   ins->codep++;
10586
10587   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10588   if (dp->name == NULL)
10589     {
10590       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10591
10592       /* Instruction fnstsw is only one with strange arg.  */
10593       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10594         strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10595     }
10596   else
10597     {
10598       putop (ins, dp->name, sizeflag);
10599
10600       ins->obufp = ins->op_out[0];
10601       ins->op_ad = 2;
10602       if (dp->op[0].rtn)
10603         (*dp->op[0].rtn) (ins, dp->op[0].bytemode, sizeflag);
10604
10605       ins->obufp = ins->op_out[1];
10606       ins->op_ad = 1;
10607       if (dp->op[1].rtn)
10608         (*dp->op[1].rtn) (ins, dp->op[1].bytemode, sizeflag);
10609     }
10610 }
10611
10612 static void
10613 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10614        int sizeflag ATTRIBUTE_UNUSED)
10615 {
10616   oappend_register (ins, "%st");
10617 }
10618
10619 static void
10620 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10621         int sizeflag ATTRIBUTE_UNUSED)
10622 {
10623   char scratch[8];
10624   int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10625
10626   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10627     abort ();
10628   oappend_register (ins, scratch);
10629 }
10630
10631 /* Capital letters in template are macros.  */
10632 static int
10633 putop (instr_info *ins, const char *in_template, int sizeflag)
10634 {
10635   const char *p;
10636   int alt = 0;
10637   int cond = 1;
10638   unsigned int l = 0, len = 0;
10639   char last[4];
10640
10641   for (p = in_template; *p; p++)
10642     {
10643       if (len > l)
10644         {
10645           if (l >= sizeof (last) || !ISUPPER (*p))
10646             abort ();
10647           last[l++] = *p;
10648           continue;
10649         }
10650       switch (*p)
10651         {
10652         default:
10653           *ins->obufp++ = *p;
10654           break;
10655         case '%':
10656           len++;
10657           break;
10658         case '!':
10659           cond = 0;
10660           break;
10661         case '{':
10662           if (ins->intel_syntax)
10663             {
10664               while (*++p != '|')
10665                 if (*p == '}' || *p == '\0')
10666                   abort ();
10667               alt = 1;
10668             }
10669           break;
10670         case '|':
10671           while (*++p != '}')
10672             {
10673               if (*p == '\0')
10674                 abort ();
10675             }
10676           break;
10677         case '}':
10678           alt = 0;
10679           break;
10680         case 'A':
10681           if (ins->intel_syntax)
10682             break;
10683           if ((ins->need_modrm && ins->modrm.mod != 3)
10684               || (sizeflag & SUFFIX_ALWAYS))
10685             *ins->obufp++ = 'b';
10686           break;
10687         case 'B':
10688           if (l == 0)
10689             {
10690             case_B:
10691               if (ins->intel_syntax)
10692                 break;
10693               if (sizeflag & SUFFIX_ALWAYS)
10694                 *ins->obufp++ = 'b';
10695             }
10696           else if (l == 1 && last[0] == 'L')
10697             {
10698               if (ins->address_mode == mode_64bit
10699                   && !(ins->prefixes & PREFIX_ADDR))
10700                 {
10701                   *ins->obufp++ = 'a';
10702                   *ins->obufp++ = 'b';
10703                   *ins->obufp++ = 's';
10704                 }
10705
10706               goto case_B;
10707             }
10708           else
10709             abort ();
10710           break;
10711         case 'C':
10712           if (ins->intel_syntax && !alt)
10713             break;
10714           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10715             {
10716               if (sizeflag & DFLAG)
10717                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10718               else
10719                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10720               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10721             }
10722           break;
10723         case 'D':
10724           if (l == 1)
10725             {
10726               switch (last[0])
10727               {
10728               case 'X':
10729                 if (!ins->vex.evex || ins->vex.w)
10730                   *ins->obufp++ = 'd';
10731                 else
10732                   oappend (ins, "{bad}");
10733                 break;
10734               default:
10735                 abort ();
10736               }
10737               break;
10738             }
10739           if (l)
10740             abort ();
10741           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10742             break;
10743           USED_REX (REX_W);
10744           if (ins->modrm.mod == 3)
10745             {
10746               if (ins->rex & REX_W)
10747                 *ins->obufp++ = 'q';
10748               else
10749                 {
10750                   if (sizeflag & DFLAG)
10751                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10752                   else
10753                     *ins->obufp++ = 'w';
10754                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10755                 }
10756             }
10757           else
10758             *ins->obufp++ = 'w';
10759           break;
10760         case 'E':
10761           if (l == 1)
10762             {
10763               switch (last[0])
10764                 {
10765                 case 'X':
10766                   if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10767                       || !ins->vex.r
10768                       || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10769                       || !ins->vex.v || ins->vex.mask_register_specifier)
10770                     break;
10771                   /* AVX512 extends a number of V*D insns to also have V*Q variants,
10772                      merely distinguished by EVEX.W.  Look for a use of the
10773                      respective macro.  */
10774                   if (ins->vex.w)
10775                     {
10776                       const char *pct = strchr (p + 1, '%');
10777
10778                       if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10779                         break;
10780                     }
10781                   *ins->obufp++ = '{';
10782                   *ins->obufp++ = 'e';
10783                   *ins->obufp++ = 'v';
10784                   *ins->obufp++ = 'e';
10785                   *ins->obufp++ = 'x';
10786                   *ins->obufp++ = '}';
10787                   *ins->obufp++ = ' ';
10788                   break;
10789                 default:
10790                   abort ();
10791                 }
10792                 break;
10793             }
10794           /* For jcxz/jecxz */
10795           if (ins->address_mode == mode_64bit)
10796             {
10797               if (sizeflag & AFLAG)
10798                 *ins->obufp++ = 'r';
10799               else
10800                 *ins->obufp++ = 'e';
10801             }
10802           else
10803             if (sizeflag & AFLAG)
10804               *ins->obufp++ = 'e';
10805           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10806           break;
10807         case 'F':
10808           if (ins->intel_syntax)
10809             break;
10810           if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10811             {
10812               if (sizeflag & AFLAG)
10813                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10814               else
10815                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10816               ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10817             }
10818           break;
10819         case 'G':
10820           if (ins->intel_syntax || (ins->obufp[-1] != 's'
10821                                     && !(sizeflag & SUFFIX_ALWAYS)))
10822             break;
10823           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10824             *ins->obufp++ = 'l';
10825           else
10826             *ins->obufp++ = 'w';
10827           if (!(ins->rex & REX_W))
10828             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10829           break;
10830         case 'H':
10831           if (l == 0)
10832             {
10833               if (ins->intel_syntax)
10834                 break;
10835               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10836                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10837                 {
10838                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10839                   *ins->obufp++ = ',';
10840                   *ins->obufp++ = 'p';
10841
10842                   /* Set active_seg_prefix even if not set in 64-bit mode
10843                      because here it is a valid branch hint. */
10844                   if (ins->prefixes & PREFIX_DS)
10845                     {
10846                       ins->active_seg_prefix = PREFIX_DS;
10847                       *ins->obufp++ = 't';
10848                     }
10849                   else
10850                     {
10851                       ins->active_seg_prefix = PREFIX_CS;
10852                       *ins->obufp++ = 'n';
10853                     }
10854                 }
10855             }
10856           else if (l == 1 && last[0] == 'X')
10857             {
10858               if (!ins->vex.w)
10859                 *ins->obufp++ = 'h';
10860               else
10861                 oappend (ins, "{bad}");
10862             }
10863           else
10864             abort ();
10865           break;
10866         case 'K':
10867           USED_REX (REX_W);
10868           if (ins->rex & REX_W)
10869             *ins->obufp++ = 'q';
10870           else
10871             *ins->obufp++ = 'd';
10872           break;
10873         case 'L':
10874           abort ();
10875         case 'M':
10876           if (ins->intel_mnemonic != cond)
10877             *ins->obufp++ = 'r';
10878           break;
10879         case 'N':
10880           if ((ins->prefixes & PREFIX_FWAIT) == 0)
10881             *ins->obufp++ = 'n';
10882           else
10883             ins->used_prefixes |= PREFIX_FWAIT;
10884           break;
10885         case 'O':
10886           USED_REX (REX_W);
10887           if (ins->rex & REX_W)
10888             *ins->obufp++ = 'o';
10889           else if (ins->intel_syntax && (sizeflag & DFLAG))
10890             *ins->obufp++ = 'q';
10891           else
10892             *ins->obufp++ = 'd';
10893           if (!(ins->rex & REX_W))
10894             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10895           break;
10896         case '@':
10897           if (ins->address_mode == mode_64bit
10898               && (ins->isa64 == intel64 || (ins->rex & REX_W)
10899                   || !(ins->prefixes & PREFIX_DATA)))
10900             {
10901               if (sizeflag & SUFFIX_ALWAYS)
10902                 *ins->obufp++ = 'q';
10903               break;
10904             }
10905           /* Fall through.  */
10906         case 'P':
10907           if (l == 0)
10908             {
10909               if ((ins->modrm.mod == 3 || !cond)
10910                   && !(sizeflag & SUFFIX_ALWAYS))
10911                 break;
10912           /* Fall through.  */
10913         case 'T':
10914               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10915                   || ((sizeflag & SUFFIX_ALWAYS)
10916                       && ins->address_mode != mode_64bit))
10917                 {
10918                   *ins->obufp++ = (sizeflag & DFLAG)
10919                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
10920                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10921                 }
10922               else if (sizeflag & SUFFIX_ALWAYS)
10923                 *ins->obufp++ = 'q';
10924             }
10925           else if (l == 1 && last[0] == 'L')
10926             {
10927               if ((ins->prefixes & PREFIX_DATA)
10928                   || (ins->rex & REX_W)
10929                   || (sizeflag & SUFFIX_ALWAYS))
10930                 {
10931                   USED_REX (REX_W);
10932                   if (ins->rex & REX_W)
10933                     *ins->obufp++ = 'q';
10934                   else
10935                     {
10936                       if (sizeflag & DFLAG)
10937                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10938                       else
10939                         *ins->obufp++ = 'w';
10940                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10941                     }
10942                 }
10943             }
10944           else
10945             abort ();
10946           break;
10947         case 'Q':
10948           if (l == 0)
10949             {
10950               if (ins->intel_syntax && !alt)
10951                 break;
10952               USED_REX (REX_W);
10953               if ((ins->need_modrm && ins->modrm.mod != 3)
10954                   || (sizeflag & SUFFIX_ALWAYS))
10955                 {
10956                   if (ins->rex & REX_W)
10957                     *ins->obufp++ = 'q';
10958                   else
10959                     {
10960                       if (sizeflag & DFLAG)
10961                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10962                       else
10963                         *ins->obufp++ = 'w';
10964                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10965                     }
10966                 }
10967             }
10968           else if (l == 1 && last[0] == 'D')
10969             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10970           else if (l == 1 && last[0] == 'L')
10971             {
10972               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10973                        : ins->address_mode != mode_64bit)
10974                 break;
10975               if ((ins->rex & REX_W))
10976                 {
10977                   USED_REX (REX_W);
10978                   *ins->obufp++ = 'q';
10979                 }
10980               else if ((ins->address_mode == mode_64bit && cond)
10981                       || (sizeflag & SUFFIX_ALWAYS))
10982                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10983             }
10984           else
10985             abort ();
10986           break;
10987         case 'R':
10988           USED_REX (REX_W);
10989           if (ins->rex & REX_W)
10990             *ins->obufp++ = 'q';
10991           else if (sizeflag & DFLAG)
10992             {
10993               if (ins->intel_syntax)
10994                   *ins->obufp++ = 'd';
10995               else
10996                   *ins->obufp++ = 'l';
10997             }
10998           else
10999             *ins->obufp++ = 'w';
11000           if (ins->intel_syntax && !p[1]
11001               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
11002             *ins->obufp++ = 'e';
11003           if (!(ins->rex & REX_W))
11004             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11005           break;
11006         case 'S':
11007           if (l == 0)
11008             {
11009             case_S:
11010               if (ins->intel_syntax)
11011                 break;
11012               if (sizeflag & SUFFIX_ALWAYS)
11013                 {
11014                   if (ins->rex & REX_W)
11015                     *ins->obufp++ = 'q';
11016                   else
11017                     {
11018                       if (sizeflag & DFLAG)
11019                         *ins->obufp++ = 'l';
11020                       else
11021                         *ins->obufp++ = 'w';
11022                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11023                     }
11024                 }
11025               break;
11026             }
11027           if (l != 1)
11028             abort ();
11029           switch (last[0])
11030             {
11031             case 'L':
11032               if (ins->address_mode == mode_64bit
11033                   && !(ins->prefixes & PREFIX_ADDR))
11034                 {
11035                   *ins->obufp++ = 'a';
11036                   *ins->obufp++ = 'b';
11037                   *ins->obufp++ = 's';
11038                 }
11039
11040               goto case_S;
11041             case 'X':
11042               if (!ins->vex.evex || !ins->vex.w)
11043                 *ins->obufp++ = 's';
11044               else
11045                 oappend (ins, "{bad}");
11046               break;
11047             default:
11048               abort ();
11049             }
11050           break;
11051         case 'V':
11052           if (l == 0)
11053             abort ();
11054           else if (l == 1)
11055             {
11056               switch (last[0])
11057                 {
11058                 case 'X':
11059                   if (ins->vex.evex)
11060                     break;
11061                   *ins->obufp++ = '{';
11062                   *ins->obufp++ = 'v';
11063                   *ins->obufp++ = 'e';
11064                   *ins->obufp++ = 'x';
11065                   *ins->obufp++ = '}';
11066                   *ins->obufp++ = ' ';
11067                   break;
11068                 case 'L':
11069                   if (!(ins->rex & REX_W))
11070                     break;
11071                   *ins->obufp++ = 'a';
11072                   *ins->obufp++ = 'b';
11073                   *ins->obufp++ = 's';
11074                   break;
11075                 default:
11076                   abort ();
11077                 }
11078             }
11079           else
11080             abort ();
11081           goto case_S;
11082         case 'W':
11083           if (l == 0)
11084             {
11085               /* operand size flag for cwtl, cbtw */
11086               USED_REX (REX_W);
11087               if (ins->rex & REX_W)
11088                 {
11089                   if (ins->intel_syntax)
11090                     *ins->obufp++ = 'd';
11091                   else
11092                     *ins->obufp++ = 'l';
11093                 }
11094               else if (sizeflag & DFLAG)
11095                 *ins->obufp++ = 'w';
11096               else
11097                 *ins->obufp++ = 'b';
11098               if (!(ins->rex & REX_W))
11099                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11100             }
11101           else if (l == 1)
11102             {
11103               if (!ins->need_vex)
11104                 abort ();
11105               if (last[0] == 'X')
11106                 *ins->obufp++ = ins->vex.w ? 'd': 's';
11107               else if (last[0] == 'B')
11108                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
11109               else
11110                 abort ();
11111             }
11112           else
11113             abort ();
11114           break;
11115         case 'X':
11116           if (l != 0)
11117             abort ();
11118           if (ins->need_vex
11119               ? ins->vex.prefix == DATA_PREFIX_OPCODE
11120               : ins->prefixes & PREFIX_DATA)
11121             {
11122               *ins->obufp++ = 'd';
11123               ins->used_prefixes |= PREFIX_DATA;
11124             }
11125           else
11126             *ins->obufp++ = 's';
11127           break;
11128         case 'Y':
11129           if (l == 1 && last[0] == 'X')
11130             {
11131               if (!ins->need_vex)
11132                 abort ();
11133               if (ins->intel_syntax
11134                   || ((ins->modrm.mod == 3 || ins->vex.b)
11135                       && !(sizeflag & SUFFIX_ALWAYS)))
11136                 break;
11137               switch (ins->vex.length)
11138                 {
11139                 case 128:
11140                   *ins->obufp++ = 'x';
11141                   break;
11142                 case 256:
11143                   *ins->obufp++ = 'y';
11144                   break;
11145                 case 512:
11146                   if (!ins->vex.evex)
11147                 default:
11148                     abort ();
11149                 }
11150             }
11151           else
11152             abort ();
11153           break;
11154         case 'Z':
11155           if (l == 0)
11156             {
11157               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
11158               ins->modrm.mod = 3;
11159               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11160                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11161             }
11162           else if (l == 1 && last[0] == 'X')
11163             {
11164               if (!ins->vex.evex)
11165                 abort ();
11166               if (ins->intel_syntax
11167                   || ((ins->modrm.mod == 3 || ins->vex.b)
11168                       && !(sizeflag & SUFFIX_ALWAYS)))
11169                 break;
11170               switch (ins->vex.length)
11171                 {
11172                 case 128:
11173                   *ins->obufp++ = 'x';
11174                   break;
11175                 case 256:
11176                   *ins->obufp++ = 'y';
11177                   break;
11178                 case 512:
11179                   *ins->obufp++ = 'z';
11180                   break;
11181                 default:
11182                   abort ();
11183                 }
11184             }
11185           else
11186             abort ();
11187           break;
11188         case '^':
11189           if (ins->intel_syntax)
11190             break;
11191           if (ins->isa64 == intel64 && (ins->rex & REX_W))
11192             {
11193               USED_REX (REX_W);
11194               *ins->obufp++ = 'q';
11195               break;
11196             }
11197           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11198             {
11199               if (sizeflag & DFLAG)
11200                 *ins->obufp++ = 'l';
11201               else
11202                 *ins->obufp++ = 'w';
11203               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11204             }
11205           break;
11206         }
11207
11208       if (len == l)
11209         len = l = 0;
11210     }
11211   *ins->obufp = 0;
11212   ins->mnemonicendp = ins->obufp;
11213   return 0;
11214 }
11215
11216 /* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
11217    the buffer pointed to by INS->obufp has space.  A style marker is made
11218    from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11219    digit, followed by another STYLE_MARKER_CHAR.  This function assumes
11220    that the number of styles is not greater than 16.  */
11221
11222 static void
11223 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11224 {
11225   unsigned num = (unsigned) style;
11226
11227   /* We currently assume that STYLE can be encoded as a single hex
11228      character.  If more styles are added then this might start to fail,
11229      and we'll need to expand this code.  */
11230   if (num > 0xf)
11231     abort ();
11232
11233   *ins->obufp++ = STYLE_MARKER_CHAR;
11234   *ins->obufp++ = (num < 10 ? ('0' + num)
11235                    : ((num < 16) ? ('a' + (num - 10)) : '0'));
11236   *ins->obufp++ = STYLE_MARKER_CHAR;
11237
11238   /* This final null character is not strictly necessary, after inserting a
11239      style marker we should always be inserting some additional content.
11240      However, having the buffer null terminated doesn't cost much, and make
11241      it easier to debug what's going on.  Also, if we do ever forget to add
11242      any additional content after this style marker, then the buffer will
11243      still be well formed.  */
11244   *ins->obufp = '\0';
11245 }
11246
11247 static void
11248 oappend_with_style (instr_info *ins, const char *s,
11249                     enum disassembler_style style)
11250 {
11251   oappend_insert_style (ins, style);
11252   ins->obufp = stpcpy (ins->obufp, s);
11253 }
11254
11255 /* Like oappend_with_style but always with text style.  */
11256
11257 static void
11258 oappend (instr_info *ins, const char *s)
11259 {
11260   oappend_with_style (ins, s, dis_style_text);
11261 }
11262
11263 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11264    the style for the character as STYLE.  */
11265
11266 static void
11267 oappend_char_with_style (instr_info *ins, const char c,
11268                          enum disassembler_style style)
11269 {
11270   oappend_insert_style (ins, style);
11271   *ins->obufp++ = c;
11272   *ins->obufp = '\0';
11273 }
11274
11275 /* Like oappend_char_with_style, but always uses dis_style_text.  */
11276
11277 static void
11278 oappend_char (instr_info *ins, const char c)
11279 {
11280   oappend_char_with_style (ins, c, dis_style_text);
11281 }
11282
11283 static void
11284 append_seg (instr_info *ins)
11285 {
11286   /* Only print the active segment register.  */
11287   if (!ins->active_seg_prefix)
11288     return;
11289
11290   ins->used_prefixes |= ins->active_seg_prefix;
11291   switch (ins->active_seg_prefix)
11292     {
11293     case PREFIX_CS:
11294       oappend_register (ins, "%cs");
11295       break;
11296     case PREFIX_DS:
11297       oappend_register (ins, "%ds");
11298       break;
11299     case PREFIX_SS:
11300       oappend_register (ins, "%ss");
11301       break;
11302     case PREFIX_ES:
11303       oappend_register (ins, "%es");
11304       break;
11305     case PREFIX_FS:
11306       oappend_register (ins, "%fs");
11307       break;
11308     case PREFIX_GS:
11309       oappend_register (ins, "%gs");
11310       break;
11311     default:
11312       break;
11313     }
11314   oappend_char (ins, ':');
11315 }
11316
11317 static void
11318 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
11319 {
11320   if (!ins->intel_syntax)
11321     oappend (ins, "*");
11322   OP_E (ins, bytemode, sizeflag);
11323 }
11324
11325 static void
11326 print_operand_value (instr_info *ins, bfd_vma disp,
11327                      enum disassembler_style style)
11328 {
11329   char tmp[30];
11330
11331   if (ins->address_mode == mode_64bit)
11332     sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11333   else
11334     sprintf (tmp, "0x%x", (unsigned int) disp);
11335   oappend_with_style (ins, tmp, style);
11336 }
11337
11338 /* Like oappend, but called for immediate operands.  */
11339
11340 static void
11341 oappend_immediate (instr_info *ins, bfd_vma imm)
11342 {
11343   if (!ins->intel_syntax)
11344     oappend_char_with_style (ins, '$', dis_style_immediate);
11345   print_operand_value (ins, imm, dis_style_immediate);
11346 }
11347
11348 /* Put DISP in BUF as signed hex number.  */
11349
11350 static void
11351 print_displacement (instr_info *ins, bfd_vma disp)
11352 {
11353   bfd_signed_vma val = disp;
11354   char tmp[30];
11355
11356   if (val < 0)
11357     {
11358       oappend_char_with_style (ins, '-', dis_style_address_offset);
11359       val = -disp;
11360
11361       /* Check for possible overflow.  */
11362       if (val < 0)
11363         {
11364           switch (ins->address_mode)
11365             {
11366             case mode_64bit:
11367               oappend_with_style (ins, "0x8000000000000000",
11368                                   dis_style_address_offset);
11369               break;
11370             case mode_32bit:
11371               oappend_with_style (ins, "0x80000000",
11372                                   dis_style_address_offset);
11373               break;
11374             case mode_16bit:
11375               oappend_with_style (ins, "0x8000",
11376                                   dis_style_address_offset);
11377               break;
11378             }
11379           return;
11380         }
11381     }
11382
11383   sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11384   oappend_with_style (ins, tmp, dis_style_address_offset);
11385 }
11386
11387 static void
11388 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11389 {
11390   if (ins->vex.b)
11391     {
11392       if (!ins->vex.no_broadcast)
11393         switch (bytemode)
11394           {
11395           case x_mode:
11396           case evex_half_bcst_xmmq_mode:
11397             if (ins->vex.w)
11398               oappend (ins, "QWORD BCST ");
11399             else
11400               oappend (ins, "DWORD BCST ");
11401             break;
11402           case xh_mode:
11403           case evex_half_bcst_xmmqh_mode:
11404           case evex_half_bcst_xmmqdh_mode:
11405             oappend (ins, "WORD BCST ");
11406             break;
11407           default:
11408             ins->vex.no_broadcast = true;
11409             break;
11410           }
11411       return;
11412     }
11413   switch (bytemode)
11414     {
11415     case b_mode:
11416     case b_swap_mode:
11417     case db_mode:
11418       oappend (ins, "BYTE PTR ");
11419       break;
11420     case w_mode:
11421     case w_swap_mode:
11422     case dw_mode:
11423       oappend (ins, "WORD PTR ");
11424       break;
11425     case indir_v_mode:
11426       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11427         {
11428           oappend (ins, "QWORD PTR ");
11429           break;
11430         }
11431       /* Fall through.  */
11432     case stack_v_mode:
11433       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11434                                               || (ins->rex & REX_W)))
11435         {
11436           oappend (ins, "QWORD PTR ");
11437           break;
11438         }
11439       /* Fall through.  */
11440     case v_mode:
11441     case v_swap_mode:
11442     case dq_mode:
11443       USED_REX (REX_W);
11444       if (ins->rex & REX_W)
11445         oappend (ins, "QWORD PTR ");
11446       else if (bytemode == dq_mode)
11447         oappend (ins, "DWORD PTR ");
11448       else
11449         {
11450           if (sizeflag & DFLAG)
11451             oappend (ins, "DWORD PTR ");
11452           else
11453             oappend (ins, "WORD PTR ");
11454           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11455         }
11456       break;
11457     case z_mode:
11458       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11459         *ins->obufp++ = 'D';
11460       oappend (ins, "WORD PTR ");
11461       if (!(ins->rex & REX_W))
11462         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11463       break;
11464     case a_mode:
11465       if (sizeflag & DFLAG)
11466         oappend (ins, "QWORD PTR ");
11467       else
11468         oappend (ins, "DWORD PTR ");
11469       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11470       break;
11471     case movsxd_mode:
11472       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11473         oappend (ins, "WORD PTR ");
11474       else
11475         oappend (ins, "DWORD PTR ");
11476       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11477       break;
11478     case d_mode:
11479     case d_swap_mode:
11480       oappend (ins, "DWORD PTR ");
11481       break;
11482     case q_mode:
11483     case q_swap_mode:
11484       oappend (ins, "QWORD PTR ");
11485       break;
11486     case m_mode:
11487       if (ins->address_mode == mode_64bit)
11488         oappend (ins, "QWORD PTR ");
11489       else
11490         oappend (ins, "DWORD PTR ");
11491       break;
11492     case f_mode:
11493       if (sizeflag & DFLAG)
11494         oappend (ins, "FWORD PTR ");
11495       else
11496         oappend (ins, "DWORD PTR ");
11497       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11498       break;
11499     case t_mode:
11500       oappend (ins, "TBYTE PTR ");
11501       break;
11502     case x_mode:
11503     case xh_mode:
11504     case x_swap_mode:
11505     case evex_x_gscat_mode:
11506     case evex_x_nobcst_mode:
11507     case bw_unit_mode:
11508       if (ins->need_vex)
11509         {
11510           switch (ins->vex.length)
11511             {
11512             case 128:
11513               oappend (ins, "XMMWORD PTR ");
11514               break;
11515             case 256:
11516               oappend (ins, "YMMWORD PTR ");
11517               break;
11518             case 512:
11519               oappend (ins, "ZMMWORD PTR ");
11520               break;
11521             default:
11522               abort ();
11523             }
11524         }
11525       else
11526         oappend (ins, "XMMWORD PTR ");
11527       break;
11528     case xmm_mode:
11529       oappend (ins, "XMMWORD PTR ");
11530       break;
11531     case ymm_mode:
11532       oappend (ins, "YMMWORD PTR ");
11533       break;
11534     case xmmq_mode:
11535     case evex_half_bcst_xmmqh_mode:
11536     case evex_half_bcst_xmmq_mode:
11537       if (!ins->need_vex)
11538         abort ();
11539
11540       switch (ins->vex.length)
11541         {
11542         case 128:
11543           oappend (ins, "QWORD PTR ");
11544           break;
11545         case 256:
11546           oappend (ins, "XMMWORD PTR ");
11547           break;
11548         case 512:
11549           oappend (ins, "YMMWORD PTR ");
11550           break;
11551         default:
11552           abort ();
11553         }
11554       break;
11555     case xmmdw_mode:
11556       if (!ins->need_vex)
11557         abort ();
11558
11559       switch (ins->vex.length)
11560         {
11561         case 128:
11562           oappend (ins, "WORD PTR ");
11563           break;
11564         case 256:
11565           oappend (ins, "DWORD PTR ");
11566           break;
11567         case 512:
11568           oappend (ins, "QWORD PTR ");
11569           break;
11570         default:
11571           abort ();
11572         }
11573       break;
11574     case xmmqd_mode:
11575     case evex_half_bcst_xmmqdh_mode:
11576       if (!ins->need_vex)
11577         abort ();
11578
11579       switch (ins->vex.length)
11580         {
11581         case 128:
11582           oappend (ins, "DWORD PTR ");
11583           break;
11584         case 256:
11585           oappend (ins, "QWORD PTR ");
11586           break;
11587         case 512:
11588           oappend (ins, "XMMWORD PTR ");
11589           break;
11590         default:
11591           abort ();
11592         }
11593       break;
11594     case ymmq_mode:
11595       if (!ins->need_vex)
11596         abort ();
11597
11598       switch (ins->vex.length)
11599         {
11600         case 128:
11601           oappend (ins, "QWORD PTR ");
11602           break;
11603         case 256:
11604           oappend (ins, "YMMWORD PTR ");
11605           break;
11606         case 512:
11607           oappend (ins, "ZMMWORD PTR ");
11608           break;
11609         default:
11610           abort ();
11611         }
11612       break;
11613     case o_mode:
11614       oappend (ins, "OWORD PTR ");
11615       break;
11616     case vex_vsib_d_w_dq_mode:
11617     case vex_vsib_q_w_dq_mode:
11618       if (!ins->need_vex)
11619         abort ();
11620       if (ins->vex.w)
11621         oappend (ins, "QWORD PTR ");
11622       else
11623         oappend (ins, "DWORD PTR ");
11624       break;
11625     case mask_bd_mode:
11626       if (!ins->need_vex || ins->vex.length != 128)
11627         abort ();
11628       if (ins->vex.w)
11629         oappend (ins, "DWORD PTR ");
11630       else
11631         oappend (ins, "BYTE PTR ");
11632       break;
11633     case mask_mode:
11634       if (!ins->need_vex)
11635         abort ();
11636       if (ins->vex.w)
11637         oappend (ins, "QWORD PTR ");
11638       else
11639         oappend (ins, "WORD PTR ");
11640       break;
11641     case v_bnd_mode:
11642     case v_bndmk_mode:
11643     default:
11644       break;
11645     }
11646 }
11647
11648 static void
11649 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11650                 int bytemode, int sizeflag)
11651 {
11652   const char *const *names;
11653
11654   USED_REX (rexmask);
11655   if (ins->rex & rexmask)
11656     reg += 8;
11657
11658   switch (bytemode)
11659     {
11660     case b_mode:
11661     case b_swap_mode:
11662       if (reg & 4)
11663         USED_REX (0);
11664       if (ins->rex)
11665         names = att_names8rex;
11666       else
11667         names = att_names8;
11668       break;
11669     case w_mode:
11670       names = att_names16;
11671       break;
11672     case d_mode:
11673     case dw_mode:
11674     case db_mode:
11675       names = att_names32;
11676       break;
11677     case q_mode:
11678       names = att_names64;
11679       break;
11680     case m_mode:
11681     case v_bnd_mode:
11682       names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11683       break;
11684     case bnd_mode:
11685     case bnd_swap_mode:
11686       if (reg > 0x3)
11687         {
11688           oappend (ins, "(bad)");
11689           return;
11690         }
11691       names = att_names_bnd;
11692       break;
11693     case indir_v_mode:
11694       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11695         {
11696           names = att_names64;
11697           break;
11698         }
11699       /* Fall through.  */
11700     case stack_v_mode:
11701       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11702                                               || (ins->rex & REX_W)))
11703         {
11704           names = att_names64;
11705           break;
11706         }
11707       bytemode = v_mode;
11708       /* Fall through.  */
11709     case v_mode:
11710     case v_swap_mode:
11711     case dq_mode:
11712       USED_REX (REX_W);
11713       if (ins->rex & REX_W)
11714         names = att_names64;
11715       else if (bytemode != v_mode && bytemode != v_swap_mode)
11716         names = att_names32;
11717       else
11718         {
11719           if (sizeflag & DFLAG)
11720             names = att_names32;
11721           else
11722             names = att_names16;
11723           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11724         }
11725       break;
11726     case movsxd_mode:
11727       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11728         names = att_names16;
11729       else
11730         names = att_names32;
11731       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11732       break;
11733     case va_mode:
11734       names = (ins->address_mode == mode_64bit
11735                ? att_names64 : att_names32);
11736       if (!(ins->prefixes & PREFIX_ADDR))
11737         names = (ins->address_mode == mode_16bit
11738                      ? att_names16 : names);
11739       else
11740         {
11741           /* Remove "addr16/addr32".  */
11742           ins->all_prefixes[ins->last_addr_prefix] = 0;
11743           names = (ins->address_mode != mode_32bit
11744                        ? att_names32 : att_names16);
11745           ins->used_prefixes |= PREFIX_ADDR;
11746         }
11747       break;
11748     case mask_bd_mode:
11749     case mask_mode:
11750       if (reg > 0x7)
11751         {
11752           oappend (ins, "(bad)");
11753           return;
11754         }
11755       names = att_names_mask;
11756       break;
11757     case 0:
11758       return;
11759     default:
11760       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11761       return;
11762     }
11763   oappend_register (ins, names[reg]);
11764 }
11765
11766 static void
11767 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11768 {
11769   bfd_vma disp = 0;
11770   int add = (ins->rex & REX_B) ? 8 : 0;
11771   int riprel = 0;
11772   int shift;
11773
11774   if (ins->vex.evex)
11775     {
11776       switch (bytemode)
11777         {
11778         case dw_mode:
11779         case w_mode:
11780         case w_swap_mode:
11781           shift = 1;
11782           break;
11783         case db_mode:
11784         case b_mode:
11785           shift = 0;
11786           break;
11787         case dq_mode:
11788           if (ins->address_mode != mode_64bit)
11789             {
11790         case d_mode:
11791         case d_swap_mode:
11792               shift = 2;
11793               break;
11794             }
11795             /* fall through */
11796         case vex_vsib_d_w_dq_mode:
11797         case vex_vsib_q_w_dq_mode:
11798         case evex_x_gscat_mode:
11799           shift = ins->vex.w ? 3 : 2;
11800           break;
11801         case xh_mode:
11802         case evex_half_bcst_xmmqh_mode:
11803         case evex_half_bcst_xmmqdh_mode:
11804           if (ins->vex.b)
11805             {
11806               shift = ins->vex.w ? 2 : 1;
11807               break;
11808             }
11809           /* Fall through.  */
11810         case x_mode:
11811         case evex_half_bcst_xmmq_mode:
11812           if (ins->vex.b)
11813             {
11814               shift = ins->vex.w ? 3 : 2;
11815               break;
11816             }
11817           /* Fall through.  */
11818         case xmmqd_mode:
11819         case xmmdw_mode:
11820         case xmmq_mode:
11821         case ymmq_mode:
11822         case evex_x_nobcst_mode:
11823         case x_swap_mode:
11824           switch (ins->vex.length)
11825             {
11826             case 128:
11827               shift = 4;
11828               break;
11829             case 256:
11830               shift = 5;
11831               break;
11832             case 512:
11833               shift = 6;
11834               break;
11835             default:
11836               abort ();
11837             }
11838           /* Make necessary corrections to shift for modes that need it.  */
11839           if (bytemode == xmmq_mode
11840               || bytemode == evex_half_bcst_xmmqh_mode
11841               || bytemode == evex_half_bcst_xmmq_mode
11842               || (bytemode == ymmq_mode && ins->vex.length == 128))
11843             shift -= 1;
11844           else if (bytemode == xmmqd_mode
11845                    || bytemode == evex_half_bcst_xmmqdh_mode)
11846             shift -= 2;
11847           else if (bytemode == xmmdw_mode)
11848             shift -= 3;
11849           break;
11850         case ymm_mode:
11851           shift = 5;
11852           break;
11853         case xmm_mode:
11854           shift = 4;
11855           break;
11856         case q_mode:
11857         case q_swap_mode:
11858           shift = 3;
11859           break;
11860         case bw_unit_mode:
11861           shift = ins->vex.w ? 1 : 0;
11862           break;
11863         default:
11864           abort ();
11865         }
11866     }
11867   else
11868     shift = 0;
11869
11870   USED_REX (REX_B);
11871   if (ins->intel_syntax)
11872     intel_operand_size (ins, bytemode, sizeflag);
11873   append_seg (ins);
11874
11875   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11876     {
11877       /* 32/64 bit address mode */
11878       int havedisp;
11879       int havebase;
11880       int needindex;
11881       int needaddr32;
11882       int base, rbase;
11883       int vindex = 0;
11884       int scale = 0;
11885       int addr32flag = !((sizeflag & AFLAG)
11886                          || bytemode == v_bnd_mode
11887                          || bytemode == v_bndmk_mode
11888                          || bytemode == bnd_mode
11889                          || bytemode == bnd_swap_mode);
11890       bool check_gather = false;
11891       const char *const *indexes = NULL;
11892
11893       havebase = 1;
11894       base = ins->modrm.rm;
11895
11896       if (base == 4)
11897         {
11898           vindex = ins->sib.index;
11899           USED_REX (REX_X);
11900           if (ins->rex & REX_X)
11901             vindex += 8;
11902           switch (bytemode)
11903             {
11904             case vex_vsib_d_w_dq_mode:
11905             case vex_vsib_q_w_dq_mode:
11906               if (!ins->need_vex)
11907                 abort ();
11908               if (ins->vex.evex)
11909                 {
11910                   if (!ins->vex.v)
11911                     vindex += 16;
11912                   check_gather = ins->obufp == ins->op_out[1];
11913                 }
11914
11915               switch (ins->vex.length)
11916                 {
11917                 case 128:
11918                   indexes = att_names_xmm;
11919                   break;
11920                 case 256:
11921                   if (!ins->vex.w
11922                       || bytemode == vex_vsib_q_w_dq_mode)
11923                     indexes = att_names_ymm;
11924                   else
11925                     indexes = att_names_xmm;
11926                   break;
11927                 case 512:
11928                   if (!ins->vex.w
11929                       || bytemode == vex_vsib_q_w_dq_mode)
11930                     indexes = att_names_zmm;
11931                   else
11932                     indexes = att_names_ymm;
11933                   break;
11934                 default:
11935                   abort ();
11936                 }
11937               break;
11938             default:
11939               if (vindex != 4)
11940                 indexes = ins->address_mode == mode_64bit && !addr32flag
11941                           ? att_names64 : att_names32;
11942               break;
11943             }
11944           scale = ins->sib.scale;
11945           base = ins->sib.base;
11946           ins->codep++;
11947         }
11948       else
11949         {
11950           /* Check for mandatory SIB.  */
11951           if (bytemode == vex_vsib_d_w_dq_mode
11952               || bytemode == vex_vsib_q_w_dq_mode
11953               || bytemode == vex_sibmem_mode)
11954             {
11955               oappend (ins, "(bad)");
11956               return;
11957             }
11958         }
11959       rbase = base + add;
11960
11961       switch (ins->modrm.mod)
11962         {
11963         case 0:
11964           if (base == 5)
11965             {
11966               havebase = 0;
11967               if (ins->address_mode == mode_64bit && !ins->has_sib)
11968                 riprel = 1;
11969               disp = get32s (ins);
11970               if (riprel && bytemode == v_bndmk_mode)
11971                 {
11972                   oappend (ins, "(bad)");
11973                   return;
11974                 }
11975             }
11976           break;
11977         case 1:
11978           FETCH_DATA (ins->info, ins->codep + 1);
11979           disp = *ins->codep++;
11980           if ((disp & 0x80) != 0)
11981             disp -= 0x100;
11982           if (ins->vex.evex && shift > 0)
11983             disp <<= shift;
11984           break;
11985         case 2:
11986           disp = get32s (ins);
11987           break;
11988         }
11989
11990       needindex = 0;
11991       needaddr32 = 0;
11992       if (ins->has_sib
11993           && !havebase
11994           && !indexes
11995           && ins->address_mode != mode_16bit)
11996         {
11997           if (ins->address_mode == mode_64bit)
11998             {
11999               if (addr32flag)
12000                 {
12001                   /* Without base nor index registers, zero-extend the
12002                      lower 32-bit displacement to 64 bits.  */
12003                   disp = (unsigned int) disp;
12004                   needindex = 1;
12005                 }
12006               needaddr32 = 1;
12007             }
12008           else
12009             {
12010               /* In 32-bit mode, we need index register to tell [offset]
12011                  from [eiz*1 + offset].  */
12012               needindex = 1;
12013             }
12014         }
12015
12016       havedisp = (havebase
12017                   || needindex
12018                   || (ins->has_sib && (indexes || scale != 0)));
12019
12020       if (!ins->intel_syntax)
12021         if (ins->modrm.mod != 0 || base == 5)
12022           {
12023             if (havedisp || riprel)
12024               print_displacement (ins, disp);
12025             else
12026               print_operand_value (ins, disp, dis_style_address_offset);
12027             if (riprel)
12028               {
12029                 set_op (ins, disp, true);
12030                 oappend_char (ins, '(');
12031                 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
12032                                     dis_style_register);
12033                 oappend_char (ins, ')');
12034               }
12035           }
12036
12037       if ((havebase || indexes || needindex || needaddr32 || riprel)
12038           && (ins->address_mode != mode_64bit
12039               || ((bytemode != v_bnd_mode)
12040                   && (bytemode != v_bndmk_mode)
12041                   && (bytemode != bnd_mode)
12042                   && (bytemode != bnd_swap_mode))))
12043         ins->used_prefixes |= PREFIX_ADDR;
12044
12045       if (havedisp || (ins->intel_syntax && riprel))
12046         {
12047           oappend_char (ins, ins->open_char);
12048           if (ins->intel_syntax && riprel)
12049             {
12050               set_op (ins, disp, true);
12051               oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12052                                   dis_style_register);
12053             }
12054           if (havebase)
12055             oappend_register
12056               (ins,
12057                (ins->address_mode == mode_64bit && !addr32flag
12058                 ? att_names64 : att_names32)[rbase]);
12059           if (ins->has_sib)
12060             {
12061               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12062                  print index to tell base + index from base.  */
12063               if (scale != 0
12064                   || needindex
12065                   || indexes
12066                   || (havebase && base != ESP_REG_NUM))
12067                 {
12068                   if (!ins->intel_syntax || havebase)
12069                     oappend_char (ins, ins->separator_char);
12070                   if (indexes)
12071                     {
12072                       if (ins->address_mode == mode_64bit || vindex < 16)
12073                         oappend_register (ins, indexes[vindex]);
12074                       else
12075                         oappend (ins, "(bad)");
12076                     }
12077                   else
12078                     oappend_register (ins,
12079                                       ins->address_mode == mode_64bit
12080                                       && !addr32flag
12081                                       ? att_index64
12082                                       : att_index32);
12083
12084                   oappend_char (ins, ins->scale_char);
12085                   oappend_char_with_style (ins, '0' + (1 << scale),
12086                                            dis_style_immediate);
12087                 }
12088             }
12089           if (ins->intel_syntax
12090               && (disp || ins->modrm.mod != 0 || base == 5))
12091             {
12092               if (!havedisp || (bfd_signed_vma) disp >= 0)
12093                   oappend_char (ins, '+');
12094               else if (ins->modrm.mod != 1 && disp != -disp)
12095                 {
12096                   oappend_char (ins, '-');
12097                   disp = -disp;
12098                 }
12099
12100               if (havedisp)
12101                 print_displacement (ins, disp);
12102               else
12103                 print_operand_value (ins, disp, dis_style_address_offset);
12104             }
12105
12106           oappend_char (ins, ins->close_char);
12107
12108           if (check_gather)
12109             {
12110               /* Both XMM/YMM/ZMM registers must be distinct.  */
12111               int modrm_reg = ins->modrm.reg;
12112
12113               if (ins->rex & REX_R)
12114                 modrm_reg += 8;
12115               if (!ins->vex.r)
12116                 modrm_reg += 16;
12117               if (vindex == modrm_reg)
12118                 oappend (ins, "/(bad)");
12119             }
12120         }
12121       else if (ins->intel_syntax)
12122         {
12123           if (ins->modrm.mod != 0 || base == 5)
12124             {
12125               if (!ins->active_seg_prefix)
12126                 {
12127                   oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12128                   oappend (ins, ":");
12129                 }
12130               print_operand_value (ins, disp, dis_style_text);
12131             }
12132         }
12133     }
12134   else if (bytemode == v_bnd_mode
12135            || bytemode == v_bndmk_mode
12136            || bytemode == bnd_mode
12137            || bytemode == bnd_swap_mode
12138            || bytemode == vex_vsib_d_w_dq_mode
12139            || bytemode == vex_vsib_q_w_dq_mode)
12140     {
12141       oappend (ins, "(bad)");
12142       return;
12143     }
12144   else
12145     {
12146       /* 16 bit address mode */
12147       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12148       switch (ins->modrm.mod)
12149         {
12150         case 0:
12151           if (ins->modrm.rm == 6)
12152             {
12153               disp = get16 (ins);
12154               if ((disp & 0x8000) != 0)
12155                 disp -= 0x10000;
12156             }
12157           break;
12158         case 1:
12159           FETCH_DATA (ins->info, ins->codep + 1);
12160           disp = *ins->codep++;
12161           if ((disp & 0x80) != 0)
12162             disp -= 0x100;
12163           if (ins->vex.evex && shift > 0)
12164             disp <<= shift;
12165           break;
12166         case 2:
12167           disp = get16 (ins);
12168           if ((disp & 0x8000) != 0)
12169             disp -= 0x10000;
12170           break;
12171         }
12172
12173       if (!ins->intel_syntax)
12174         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12175           print_displacement (ins, disp);
12176
12177       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12178         {
12179           oappend_char (ins, ins->open_char);
12180           oappend (ins, (ins->intel_syntax ? intel_index16
12181                          : att_index16)[ins->modrm.rm]);
12182           if (ins->intel_syntax
12183               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12184             {
12185               if ((bfd_signed_vma) disp >= 0)
12186                 oappend_char (ins, '+');
12187               else if (ins->modrm.mod != 1)
12188                 {
12189                   oappend_char (ins, '-');
12190                   disp = -disp;
12191                 }
12192
12193               print_displacement (ins, disp);
12194             }
12195
12196           oappend_char (ins, ins->close_char);
12197         }
12198       else if (ins->intel_syntax)
12199         {
12200           if (!ins->active_seg_prefix)
12201             {
12202               oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12203               oappend (ins, ":");
12204             }
12205           print_operand_value (ins, disp & 0xffff, dis_style_text);
12206         }
12207     }
12208   if (ins->vex.b)
12209     {
12210       ins->evex_used |= EVEX_b_used;
12211
12212       /* Broadcast can only ever be valid for memory sources.  */
12213       if (ins->obufp == ins->op_out[0])
12214         ins->vex.no_broadcast = true;
12215
12216       if (!ins->vex.no_broadcast
12217           && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12218         {
12219           if (bytemode == xh_mode)
12220             {
12221               switch (ins->vex.length)
12222                 {
12223                 case 128:
12224                   oappend (ins, "{1to8}");
12225                   break;
12226                 case 256:
12227                   oappend (ins, "{1to16}");
12228                   break;
12229                 case 512:
12230                   oappend (ins, "{1to32}");
12231                   break;
12232                 default:
12233                   abort ();
12234                 }
12235             }
12236           else if (bytemode == q_mode
12237                    || bytemode == ymmq_mode)
12238             ins->vex.no_broadcast = true;
12239           else if (ins->vex.w
12240                    || bytemode == evex_half_bcst_xmmqdh_mode
12241                    || bytemode == evex_half_bcst_xmmq_mode)
12242             {
12243               switch (ins->vex.length)
12244                 {
12245                 case 128:
12246                   oappend (ins, "{1to2}");
12247                   break;
12248                 case 256:
12249                   oappend (ins, "{1to4}");
12250                   break;
12251                 case 512:
12252                   oappend (ins, "{1to8}");
12253                   break;
12254                 default:
12255                   abort ();
12256                 }
12257             }
12258           else if (bytemode == x_mode
12259                    || bytemode == evex_half_bcst_xmmqh_mode)
12260             {
12261               switch (ins->vex.length)
12262                 {
12263                 case 128:
12264                   oappend (ins, "{1to4}");
12265                   break;
12266                 case 256:
12267                   oappend (ins, "{1to8}");
12268                   break;
12269                 case 512:
12270                   oappend (ins, "{1to16}");
12271                   break;
12272                 default:
12273                   abort ();
12274                 }
12275             }
12276           else
12277             ins->vex.no_broadcast = true;
12278         }
12279       if (ins->vex.no_broadcast)
12280         oappend (ins, "{bad}");
12281     }
12282 }
12283
12284 static void
12285 OP_E (instr_info *ins, int bytemode, int sizeflag)
12286 {
12287   /* Skip mod/rm byte.  */
12288   MODRM_CHECK;
12289   ins->codep++;
12290
12291   if (ins->modrm.mod == 3)
12292     {
12293       if ((sizeflag & SUFFIX_ALWAYS)
12294           && (bytemode == b_swap_mode
12295               || bytemode == bnd_swap_mode
12296               || bytemode == v_swap_mode))
12297         swap_operand (ins);
12298
12299       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12300     }
12301   else
12302     OP_E_memory (ins, bytemode, sizeflag);
12303 }
12304
12305 static void
12306 OP_G (instr_info *ins, int bytemode, int sizeflag)
12307 {
12308   if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
12309     {
12310       oappend (ins, "(bad)");
12311       return;
12312     }
12313
12314   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12315 }
12316
12317 #ifdef BFD64
12318 static bfd_vma
12319 get64 (instr_info *ins)
12320 {
12321   bfd_vma x;
12322   unsigned int a;
12323   unsigned int b;
12324
12325   FETCH_DATA (ins->info, ins->codep + 8);
12326   a = *ins->codep++ & 0xff;
12327   a |= (*ins->codep++ & 0xff) << 8;
12328   a |= (*ins->codep++ & 0xff) << 16;
12329   a |= (*ins->codep++ & 0xffu) << 24;
12330   b = *ins->codep++ & 0xff;
12331   b |= (*ins->codep++ & 0xff) << 8;
12332   b |= (*ins->codep++ & 0xff) << 16;
12333   b |= (*ins->codep++ & 0xffu) << 24;
12334   x = a + ((bfd_vma) b << 32);
12335   return x;
12336 }
12337 #else
12338 static bfd_vma
12339 get64 (instr_info *ins ATTRIBUTE_UNUSED)
12340 {
12341   abort ();
12342   return 0;
12343 }
12344 #endif
12345
12346 static bfd_signed_vma
12347 get32 (instr_info *ins)
12348 {
12349   bfd_vma x = 0;
12350
12351   FETCH_DATA (ins->info, ins->codep + 4);
12352   x = *ins->codep++ & (bfd_vma) 0xff;
12353   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12354   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12355   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12356   return x;
12357 }
12358
12359 static bfd_signed_vma
12360 get32s (instr_info *ins)
12361 {
12362   bfd_vma x = 0;
12363
12364   FETCH_DATA (ins->info, ins->codep + 4);
12365   x = *ins->codep++ & (bfd_vma) 0xff;
12366   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12367   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12368   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12369
12370   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12371
12372   return x;
12373 }
12374
12375 static int
12376 get16 (instr_info *ins)
12377 {
12378   int x = 0;
12379
12380   FETCH_DATA (ins->info, ins->codep + 2);
12381   x = *ins->codep++ & 0xff;
12382   x |= (*ins->codep++ & 0xff) << 8;
12383   return x;
12384 }
12385
12386 static void
12387 set_op (instr_info *ins, bfd_vma op, bool riprel)
12388 {
12389   ins->op_index[ins->op_ad] = ins->op_ad;
12390   if (ins->address_mode == mode_64bit)
12391     ins->op_address[ins->op_ad] = op;
12392   else /* Mask to get a 32-bit address.  */
12393     ins->op_address[ins->op_ad] = op & 0xffffffff;
12394   ins->op_riprel[ins->op_ad] = riprel;
12395 }
12396
12397 static void
12398 OP_REG (instr_info *ins, int code, int sizeflag)
12399 {
12400   const char *s;
12401   int add;
12402
12403   switch (code)
12404     {
12405     case es_reg: case ss_reg: case cs_reg:
12406     case ds_reg: case fs_reg: case gs_reg:
12407       oappend_register (ins, att_names_seg[code - es_reg]);
12408       return;
12409     }
12410
12411   USED_REX (REX_B);
12412   if (ins->rex & REX_B)
12413     add = 8;
12414   else
12415     add = 0;
12416
12417   switch (code)
12418     {
12419     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12420     case sp_reg: case bp_reg: case si_reg: case di_reg:
12421       s = att_names16[code - ax_reg + add];
12422       break;
12423     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12424       USED_REX (0);
12425       /* Fall through.  */
12426     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12427       if (ins->rex)
12428         s = att_names8rex[code - al_reg + add];
12429       else
12430         s = att_names8[code - al_reg];
12431       break;
12432     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12433     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12434       if (ins->address_mode == mode_64bit
12435           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12436         {
12437           s = att_names64[code - rAX_reg + add];
12438           break;
12439         }
12440       code += eAX_reg - rAX_reg;
12441       /* Fall through.  */
12442     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12443     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12444       USED_REX (REX_W);
12445       if (ins->rex & REX_W)
12446         s = att_names64[code - eAX_reg + add];
12447       else
12448         {
12449           if (sizeflag & DFLAG)
12450             s = att_names32[code - eAX_reg + add];
12451           else
12452             s = att_names16[code - eAX_reg + add];
12453           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12454         }
12455       break;
12456     default:
12457       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12458       return;
12459     }
12460   oappend_register (ins, s);
12461 }
12462
12463 static void
12464 OP_IMREG (instr_info *ins, int code, int sizeflag)
12465 {
12466   const char *s;
12467
12468   switch (code)
12469     {
12470     case indir_dx_reg:
12471       if (!ins->intel_syntax)
12472         {
12473           oappend (ins, "(%dx)");
12474           return;
12475         }
12476       s = att_names16[dx_reg - ax_reg];
12477       break;
12478     case al_reg: case cl_reg:
12479       s = att_names8[code - al_reg];
12480       break;
12481     case eAX_reg:
12482       USED_REX (REX_W);
12483       if (ins->rex & REX_W)
12484         {
12485           s = *att_names64;
12486           break;
12487         }
12488       /* Fall through.  */
12489     case z_mode_ax_reg:
12490       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12491         s = *att_names32;
12492       else
12493         s = *att_names16;
12494       if (!(ins->rex & REX_W))
12495         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12496       break;
12497     default:
12498       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12499       return;
12500     }
12501   oappend_register (ins, s);
12502 }
12503
12504 static void
12505 OP_I (instr_info *ins, int bytemode, int sizeflag)
12506 {
12507   bfd_signed_vma op;
12508   bfd_signed_vma mask = -1;
12509
12510   switch (bytemode)
12511     {
12512     case b_mode:
12513       FETCH_DATA (ins->info, ins->codep + 1);
12514       op = *ins->codep++;
12515       mask = 0xff;
12516       break;
12517     case v_mode:
12518       USED_REX (REX_W);
12519       if (ins->rex & REX_W)
12520         op = get32s (ins);
12521       else
12522         {
12523           if (sizeflag & DFLAG)
12524             {
12525               op = get32 (ins);
12526               mask = 0xffffffff;
12527             }
12528           else
12529             {
12530               op = get16 (ins);
12531               mask = 0xfffff;
12532             }
12533           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12534         }
12535       break;
12536     case d_mode:
12537       mask = 0xffffffff;
12538       op = get32 (ins);
12539       break;
12540     case w_mode:
12541       mask = 0xfffff;
12542       op = get16 (ins);
12543       break;
12544     case const_1_mode:
12545       if (ins->intel_syntax)
12546         oappend (ins, "1");
12547       return;
12548     default:
12549       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12550       return;
12551     }
12552
12553   op &= mask;
12554   oappend_immediate (ins, op);
12555 }
12556
12557 static void
12558 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12559 {
12560   if (bytemode != v_mode || ins->address_mode != mode_64bit
12561       || !(ins->rex & REX_W))
12562     {
12563       OP_I (ins, bytemode, sizeflag);
12564       return;
12565     }
12566
12567   USED_REX (REX_W);
12568
12569   oappend_immediate (ins, get64 (ins));
12570 }
12571
12572 static void
12573 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12574 {
12575   bfd_signed_vma op;
12576
12577   switch (bytemode)
12578     {
12579     case b_mode:
12580     case b_T_mode:
12581       FETCH_DATA (ins->info, ins->codep + 1);
12582       op = *ins->codep++;
12583       if ((op & 0x80) != 0)
12584         op -= 0x100;
12585       if (bytemode == b_T_mode)
12586         {
12587           if (ins->address_mode != mode_64bit
12588               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12589             {
12590               /* The operand-size prefix is overridden by a REX prefix.  */
12591               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12592                 op &= 0xffffffff;
12593               else
12594                 op &= 0xffff;
12595           }
12596         }
12597       else
12598         {
12599           if (!(ins->rex & REX_W))
12600             {
12601               if (sizeflag & DFLAG)
12602                 op &= 0xffffffff;
12603               else
12604                 op &= 0xffff;
12605             }
12606         }
12607       break;
12608     case v_mode:
12609       /* The operand-size prefix is overridden by a REX prefix.  */
12610       if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12611         op = get32s (ins);
12612       else
12613         op = get16 (ins);
12614       break;
12615     default:
12616       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12617       return;
12618     }
12619
12620   oappend_immediate (ins, op);
12621 }
12622
12623 static void
12624 OP_J (instr_info *ins, int bytemode, int sizeflag)
12625 {
12626   bfd_vma disp;
12627   bfd_vma mask = -1;
12628   bfd_vma segment = 0;
12629
12630   switch (bytemode)
12631     {
12632     case b_mode:
12633       FETCH_DATA (ins->info, ins->codep + 1);
12634       disp = *ins->codep++;
12635       if ((disp & 0x80) != 0)
12636         disp -= 0x100;
12637       break;
12638     case v_mode:
12639     case dqw_mode:
12640       if ((sizeflag & DFLAG)
12641           || (ins->address_mode == mode_64bit
12642               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12643                   || (ins->rex & REX_W))))
12644         disp = get32s (ins);
12645       else
12646         {
12647           disp = get16 (ins);
12648           if ((disp & 0x8000) != 0)
12649             disp -= 0x10000;
12650           /* In 16bit mode, address is wrapped around at 64k within
12651              the same segment.  Otherwise, a data16 prefix on a jump
12652              instruction means that the pc is masked to 16 bits after
12653              the displacement is added!  */
12654           mask = 0xffff;
12655           if ((ins->prefixes & PREFIX_DATA) == 0)
12656             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12657                        & ~((bfd_vma) 0xffff));
12658         }
12659       if (ins->address_mode != mode_64bit
12660           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12661         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12662       break;
12663     default:
12664       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12665       return;
12666     }
12667   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12668          | segment;
12669   set_op (ins, disp, false);
12670   print_operand_value (ins, disp, dis_style_text);
12671 }
12672
12673 static void
12674 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12675 {
12676   if (bytemode == w_mode)
12677     oappend_register (ins, att_names_seg[ins->modrm.reg]);
12678   else
12679     OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12680 }
12681
12682 static void
12683 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12684 {
12685   int seg, offset, res;
12686   char scratch[24];
12687
12688   if (sizeflag & DFLAG)
12689     {
12690       offset = get32 (ins);
12691       seg = get16 (ins);
12692     }
12693   else
12694     {
12695       offset = get16 (ins);
12696       seg = get16 (ins);
12697     }
12698   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12699
12700   res = snprintf (scratch, ARRAY_SIZE (scratch),
12701                   ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12702                   seg, offset);
12703   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12704     abort ();
12705   oappend (ins, scratch);
12706 }
12707
12708 static void
12709 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12710 {
12711   bfd_vma off;
12712
12713   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12714     intel_operand_size (ins, bytemode, sizeflag);
12715   append_seg (ins);
12716
12717   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12718     off = get32 (ins);
12719   else
12720     off = get16 (ins);
12721
12722   if (ins->intel_syntax)
12723     {
12724       if (!ins->active_seg_prefix)
12725         {
12726           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12727           oappend (ins, ":");
12728         }
12729     }
12730   print_operand_value (ins, off, dis_style_address_offset);
12731 }
12732
12733 static void
12734 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12735 {
12736   bfd_vma off;
12737
12738   if (ins->address_mode != mode_64bit
12739       || (ins->prefixes & PREFIX_ADDR))
12740     {
12741       OP_OFF (ins, bytemode, sizeflag);
12742       return;
12743     }
12744
12745   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12746     intel_operand_size (ins, bytemode, sizeflag);
12747   append_seg (ins);
12748
12749   off = get64 (ins);
12750
12751   if (ins->intel_syntax)
12752     {
12753       if (!ins->active_seg_prefix)
12754         {
12755           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12756           oappend (ins, ":");
12757         }
12758     }
12759   print_operand_value (ins, off, dis_style_address_offset);
12760 }
12761
12762 static void
12763 ptr_reg (instr_info *ins, int code, int sizeflag)
12764 {
12765   const char *s;
12766
12767   *ins->obufp++ = ins->open_char;
12768   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12769   if (ins->address_mode == mode_64bit)
12770     {
12771       if (!(sizeflag & AFLAG))
12772         s = att_names32[code - eAX_reg];
12773       else
12774         s = att_names64[code - eAX_reg];
12775     }
12776   else if (sizeflag & AFLAG)
12777     s = att_names32[code - eAX_reg];
12778   else
12779     s = att_names16[code - eAX_reg];
12780   oappend_register (ins, s);
12781   oappend_char (ins, ins->close_char);
12782 }
12783
12784 static void
12785 OP_ESreg (instr_info *ins, int code, int sizeflag)
12786 {
12787   if (ins->intel_syntax)
12788     {
12789       switch (ins->codep[-1])
12790         {
12791         case 0x6d:      /* insw/insl */
12792           intel_operand_size (ins, z_mode, sizeflag);
12793           break;
12794         case 0xa5:      /* movsw/movsl/movsq */
12795         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12796         case 0xab:      /* stosw/stosl */
12797         case 0xaf:      /* scasw/scasl */
12798           intel_operand_size (ins, v_mode, sizeflag);
12799           break;
12800         default:
12801           intel_operand_size (ins, b_mode, sizeflag);
12802         }
12803     }
12804   oappend_register (ins, "%es");
12805   oappend_char (ins, ':');
12806   ptr_reg (ins, code, sizeflag);
12807 }
12808
12809 static void
12810 OP_DSreg (instr_info *ins, int code, int sizeflag)
12811 {
12812   if (ins->intel_syntax)
12813     {
12814       switch (ins->codep[-1])
12815         {
12816         case 0x6f:      /* outsw/outsl */
12817           intel_operand_size (ins, z_mode, sizeflag);
12818           break;
12819         case 0xa5:      /* movsw/movsl/movsq */
12820         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12821         case 0xad:      /* lodsw/lodsl/lodsq */
12822           intel_operand_size (ins, v_mode, sizeflag);
12823           break;
12824         default:
12825           intel_operand_size (ins, b_mode, sizeflag);
12826         }
12827     }
12828   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12829      default segment register DS is printed.  */
12830   if (!ins->active_seg_prefix)
12831     ins->active_seg_prefix = PREFIX_DS;
12832   append_seg (ins);
12833   ptr_reg (ins, code, sizeflag);
12834 }
12835
12836 static void
12837 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12838       int sizeflag ATTRIBUTE_UNUSED)
12839 {
12840   int add, res;
12841   char scratch[8];
12842
12843   if (ins->rex & REX_R)
12844     {
12845       USED_REX (REX_R);
12846       add = 8;
12847     }
12848   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12849     {
12850       ins->all_prefixes[ins->last_lock_prefix] = 0;
12851       ins->used_prefixes |= PREFIX_LOCK;
12852       add = 8;
12853     }
12854   else
12855     add = 0;
12856   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12857                   ins->modrm.reg + add);
12858   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12859     abort ();
12860   oappend_register (ins, scratch);
12861 }
12862
12863 static void
12864 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12865       int sizeflag ATTRIBUTE_UNUSED)
12866 {
12867   int add, res;
12868   char scratch[8];
12869
12870   USED_REX (REX_R);
12871   if (ins->rex & REX_R)
12872     add = 8;
12873   else
12874     add = 0;
12875   res = snprintf (scratch, ARRAY_SIZE (scratch),
12876                   ins->intel_syntax ? "dr%d" : "%%db%d",
12877                   ins->modrm.reg + add);
12878   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12879     abort ();
12880   oappend (ins, scratch);
12881 }
12882
12883 static void
12884 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12885       int sizeflag ATTRIBUTE_UNUSED)
12886 {
12887   int res;
12888   char scratch[8];
12889
12890   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12891   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12892     abort ();
12893   oappend_register (ins, scratch);
12894 }
12895
12896 static void
12897 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12898         int sizeflag ATTRIBUTE_UNUSED)
12899 {
12900   int reg = ins->modrm.reg;
12901   const char *const *names;
12902
12903   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12904   if (ins->prefixes & PREFIX_DATA)
12905     {
12906       names = att_names_xmm;
12907       USED_REX (REX_R);
12908       if (ins->rex & REX_R)
12909         reg += 8;
12910     }
12911   else
12912     names = att_names_mm;
12913   oappend_register (ins, names[reg]);
12914 }
12915
12916 static void
12917 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12918 {
12919   const char *const *names;
12920
12921   if (bytemode == xmmq_mode
12922       || bytemode == evex_half_bcst_xmmqh_mode
12923       || bytemode == evex_half_bcst_xmmq_mode)
12924     {
12925       switch (ins->vex.length)
12926         {
12927         case 128:
12928         case 256:
12929           names = att_names_xmm;
12930           break;
12931         case 512:
12932           names = att_names_ymm;
12933           ins->evex_used |= EVEX_len_used;
12934           break;
12935         default:
12936           abort ();
12937         }
12938     }
12939   else if (bytemode == ymm_mode)
12940     names = att_names_ymm;
12941   else if (bytemode == tmm_mode)
12942     {
12943       if (reg >= 8)
12944         {
12945           oappend (ins, "(bad)");
12946           return;
12947         }
12948       names = att_names_tmm;
12949     }
12950   else if (ins->need_vex
12951            && bytemode != xmm_mode
12952            && bytemode != scalar_mode
12953            && bytemode != xmmdw_mode
12954            && bytemode != xmmqd_mode
12955            && bytemode != evex_half_bcst_xmmqdh_mode
12956            && bytemode != w_swap_mode
12957            && bytemode != b_mode
12958            && bytemode != w_mode
12959            && bytemode != d_mode
12960            && bytemode != q_mode)
12961     {
12962       ins->evex_used |= EVEX_len_used;
12963       switch (ins->vex.length)
12964         {
12965         case 128:
12966           names = att_names_xmm;
12967           break;
12968         case 256:
12969           if (ins->vex.w
12970               || bytemode != vex_vsib_q_w_dq_mode)
12971             names = att_names_ymm;
12972           else
12973             names = att_names_xmm;
12974           break;
12975         case 512:
12976           if (ins->vex.w
12977               || bytemode != vex_vsib_q_w_dq_mode)
12978             names = att_names_zmm;
12979           else
12980             names = att_names_ymm;
12981           break;
12982         default:
12983           abort ();
12984         }
12985     }
12986   else
12987     names = att_names_xmm;
12988   oappend_register (ins, names[reg]);
12989 }
12990
12991 static void
12992 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12993 {
12994   unsigned int reg = ins->modrm.reg;
12995
12996   USED_REX (REX_R);
12997   if (ins->rex & REX_R)
12998     reg += 8;
12999   if (ins->vex.evex)
13000     {
13001       if (!ins->vex.r)
13002         reg += 16;
13003     }
13004
13005   if (bytemode == tmm_mode)
13006     ins->modrm.reg = reg;
13007   else if (bytemode == scalar_mode)
13008     ins->vex.no_broadcast = true;
13009
13010   print_vector_reg (ins, reg, bytemode);
13011 }
13012
13013 static void
13014 OP_EM (instr_info *ins, int bytemode, int sizeflag)
13015 {
13016   int reg;
13017   const char *const *names;
13018
13019   if (ins->modrm.mod != 3)
13020     {
13021       if (ins->intel_syntax
13022           && (bytemode == v_mode || bytemode == v_swap_mode))
13023         {
13024           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13025           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13026         }
13027       OP_E (ins, bytemode, sizeflag);
13028       return;
13029     }
13030
13031   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13032     swap_operand (ins);
13033
13034   /* Skip mod/rm byte.  */
13035   MODRM_CHECK;
13036   ins->codep++;
13037   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13038   reg = ins->modrm.rm;
13039   if (ins->prefixes & PREFIX_DATA)
13040     {
13041       names = att_names_xmm;
13042       USED_REX (REX_B);
13043       if (ins->rex & REX_B)
13044         reg += 8;
13045     }
13046   else
13047     names = att_names_mm;
13048   oappend_register (ins, names[reg]);
13049 }
13050
13051 /* cvt* are the only instructions in sse2 which have
13052    both SSE and MMX operands and also have 0x66 prefix
13053    in their opcode. 0x66 was originally used to differentiate
13054    between SSE and MMX instruction(operands). So we have to handle the
13055    cvt* separately using OP_EMC and OP_MXC */
13056 static void
13057 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
13058 {
13059   if (ins->modrm.mod != 3)
13060     {
13061       if (ins->intel_syntax && bytemode == v_mode)
13062         {
13063           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13064           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13065         }
13066       OP_E (ins, bytemode, sizeflag);
13067       return;
13068     }
13069
13070   /* Skip mod/rm byte.  */
13071   MODRM_CHECK;
13072   ins->codep++;
13073   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13074   oappend_register (ins, att_names_mm[ins->modrm.rm]);
13075 }
13076
13077 static void
13078 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13079         int sizeflag ATTRIBUTE_UNUSED)
13080 {
13081   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13082   oappend_register (ins, att_names_mm[ins->modrm.reg]);
13083 }
13084
13085 static void
13086 OP_EX (instr_info *ins, int bytemode, int sizeflag)
13087 {
13088   int reg;
13089
13090   /* Skip mod/rm byte.  */
13091   MODRM_CHECK;
13092   ins->codep++;
13093
13094   if (bytemode == dq_mode)
13095     bytemode = ins->vex.w ? q_mode : d_mode;
13096
13097   if (ins->modrm.mod != 3)
13098     {
13099       OP_E_memory (ins, bytemode, sizeflag);
13100       return;
13101     }
13102
13103   reg = ins->modrm.rm;
13104   USED_REX (REX_B);
13105   if (ins->rex & REX_B)
13106     reg += 8;
13107   if (ins->vex.evex)
13108     {
13109       USED_REX (REX_X);
13110       if ((ins->rex & REX_X))
13111         reg += 16;
13112     }
13113
13114   if ((sizeflag & SUFFIX_ALWAYS)
13115       && (bytemode == x_swap_mode
13116           || bytemode == w_swap_mode
13117           || bytemode == d_swap_mode
13118           || bytemode == q_swap_mode))
13119     swap_operand (ins);
13120
13121   if (bytemode == tmm_mode)
13122     ins->modrm.rm = reg;
13123
13124   print_vector_reg (ins, reg, bytemode);
13125 }
13126
13127 static void
13128 OP_MS (instr_info *ins, int bytemode, int sizeflag)
13129 {
13130   if (ins->modrm.mod == 3)
13131     OP_EM (ins, bytemode, sizeflag);
13132   else
13133     BadOp (ins);
13134 }
13135
13136 static void
13137 OP_XS (instr_info *ins, int bytemode, int sizeflag)
13138 {
13139   if (ins->modrm.mod == 3)
13140     OP_EX (ins, bytemode, sizeflag);
13141   else
13142     BadOp (ins);
13143 }
13144
13145 static void
13146 OP_M (instr_info *ins, int bytemode, int sizeflag)
13147 {
13148   if (ins->modrm.mod == 3)
13149     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13150     BadOp (ins);
13151   else
13152     OP_E (ins, bytemode, sizeflag);
13153 }
13154
13155 static void
13156 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13157 {
13158   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13159     BadOp (ins);
13160   else
13161     OP_E (ins, bytemode, sizeflag);
13162 }
13163
13164 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13165    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13166
13167 static void
13168 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13169 {
13170   if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13171     ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13172   else if (opnd == 0)
13173     OP_REG (ins, eAX_reg, sizeflag);
13174   else
13175     OP_IMREG (ins, eAX_reg, sizeflag);
13176 }
13177
13178 static const char *const Suffix3DNow[] = {
13179 /* 00 */        NULL,           NULL,           NULL,           NULL,
13180 /* 04 */        NULL,           NULL,           NULL,           NULL,
13181 /* 08 */        NULL,           NULL,           NULL,           NULL,
13182 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13183 /* 10 */        NULL,           NULL,           NULL,           NULL,
13184 /* 14 */        NULL,           NULL,           NULL,           NULL,
13185 /* 18 */        NULL,           NULL,           NULL,           NULL,
13186 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13187 /* 20 */        NULL,           NULL,           NULL,           NULL,
13188 /* 24 */        NULL,           NULL,           NULL,           NULL,
13189 /* 28 */        NULL,           NULL,           NULL,           NULL,
13190 /* 2C */        NULL,           NULL,           NULL,           NULL,
13191 /* 30 */        NULL,           NULL,           NULL,           NULL,
13192 /* 34 */        NULL,           NULL,           NULL,           NULL,
13193 /* 38 */        NULL,           NULL,           NULL,           NULL,
13194 /* 3C */        NULL,           NULL,           NULL,           NULL,
13195 /* 40 */        NULL,           NULL,           NULL,           NULL,
13196 /* 44 */        NULL,           NULL,           NULL,           NULL,
13197 /* 48 */        NULL,           NULL,           NULL,           NULL,
13198 /* 4C */        NULL,           NULL,           NULL,           NULL,
13199 /* 50 */        NULL,           NULL,           NULL,           NULL,
13200 /* 54 */        NULL,           NULL,           NULL,           NULL,
13201 /* 58 */        NULL,           NULL,           NULL,           NULL,
13202 /* 5C */        NULL,           NULL,           NULL,           NULL,
13203 /* 60 */        NULL,           NULL,           NULL,           NULL,
13204 /* 64 */        NULL,           NULL,           NULL,           NULL,
13205 /* 68 */        NULL,           NULL,           NULL,           NULL,
13206 /* 6C */        NULL,           NULL,           NULL,           NULL,
13207 /* 70 */        NULL,           NULL,           NULL,           NULL,
13208 /* 74 */        NULL,           NULL,           NULL,           NULL,
13209 /* 78 */        NULL,           NULL,           NULL,           NULL,
13210 /* 7C */        NULL,           NULL,           NULL,           NULL,
13211 /* 80 */        NULL,           NULL,           NULL,           NULL,
13212 /* 84 */        NULL,           NULL,           NULL,           NULL,
13213 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13214 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13215 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13216 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13217 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13218 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13219 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13220 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13221 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13222 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13223 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13224 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13225 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13226 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13227 /* C0 */        NULL,           NULL,           NULL,           NULL,
13228 /* C4 */        NULL,           NULL,           NULL,           NULL,
13229 /* C8 */        NULL,           NULL,           NULL,           NULL,
13230 /* CC */        NULL,           NULL,           NULL,           NULL,
13231 /* D0 */        NULL,           NULL,           NULL,           NULL,
13232 /* D4 */        NULL,           NULL,           NULL,           NULL,
13233 /* D8 */        NULL,           NULL,           NULL,           NULL,
13234 /* DC */        NULL,           NULL,           NULL,           NULL,
13235 /* E0 */        NULL,           NULL,           NULL,           NULL,
13236 /* E4 */        NULL,           NULL,           NULL,           NULL,
13237 /* E8 */        NULL,           NULL,           NULL,           NULL,
13238 /* EC */        NULL,           NULL,           NULL,           NULL,
13239 /* F0 */        NULL,           NULL,           NULL,           NULL,
13240 /* F4 */        NULL,           NULL,           NULL,           NULL,
13241 /* F8 */        NULL,           NULL,           NULL,           NULL,
13242 /* FC */        NULL,           NULL,           NULL,           NULL,
13243 };
13244
13245 static void
13246 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13247                 int sizeflag ATTRIBUTE_UNUSED)
13248 {
13249   const char *mnemonic;
13250
13251   FETCH_DATA (ins->info, ins->codep + 1);
13252   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13253      place where an 8-bit immediate would normally go.  ie. the last
13254      byte of the instruction.  */
13255   ins->obufp = ins->mnemonicendp;
13256   mnemonic = Suffix3DNow[*ins->codep++ & 0xff];
13257   if (mnemonic)
13258     ins->obufp = stpcpy (ins->obufp, mnemonic);
13259   else
13260     {
13261       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13262          of the opcode (0x0f0f) and the opcode suffix, we need to do
13263          all the ins->modrm processing first, and don't know until now that
13264          we have a bad opcode.  This necessitates some cleaning up.  */
13265       ins->op_out[0][0] = '\0';
13266       ins->op_out[1][0] = '\0';
13267       BadOp (ins);
13268     }
13269   ins->mnemonicendp = ins->obufp;
13270 }
13271
13272 static const struct op simd_cmp_op[] =
13273 {
13274   { STRING_COMMA_LEN ("eq") },
13275   { STRING_COMMA_LEN ("lt") },
13276   { STRING_COMMA_LEN ("le") },
13277   { STRING_COMMA_LEN ("unord") },
13278   { STRING_COMMA_LEN ("neq") },
13279   { STRING_COMMA_LEN ("nlt") },
13280   { STRING_COMMA_LEN ("nle") },
13281   { STRING_COMMA_LEN ("ord") }
13282 };
13283
13284 static const struct op vex_cmp_op[] =
13285 {
13286   { STRING_COMMA_LEN ("eq_uq") },
13287   { STRING_COMMA_LEN ("nge") },
13288   { STRING_COMMA_LEN ("ngt") },
13289   { STRING_COMMA_LEN ("false") },
13290   { STRING_COMMA_LEN ("neq_oq") },
13291   { STRING_COMMA_LEN ("ge") },
13292   { STRING_COMMA_LEN ("gt") },
13293   { STRING_COMMA_LEN ("true") },
13294   { STRING_COMMA_LEN ("eq_os") },
13295   { STRING_COMMA_LEN ("lt_oq") },
13296   { STRING_COMMA_LEN ("le_oq") },
13297   { STRING_COMMA_LEN ("unord_s") },
13298   { STRING_COMMA_LEN ("neq_us") },
13299   { STRING_COMMA_LEN ("nlt_uq") },
13300   { STRING_COMMA_LEN ("nle_uq") },
13301   { STRING_COMMA_LEN ("ord_s") },
13302   { STRING_COMMA_LEN ("eq_us") },
13303   { STRING_COMMA_LEN ("nge_uq") },
13304   { STRING_COMMA_LEN ("ngt_uq") },
13305   { STRING_COMMA_LEN ("false_os") },
13306   { STRING_COMMA_LEN ("neq_os") },
13307   { STRING_COMMA_LEN ("ge_oq") },
13308   { STRING_COMMA_LEN ("gt_oq") },
13309   { STRING_COMMA_LEN ("true_us") },
13310 };
13311
13312 static void
13313 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13314            int sizeflag ATTRIBUTE_UNUSED)
13315 {
13316   unsigned int cmp_type;
13317
13318   FETCH_DATA (ins->info, ins->codep + 1);
13319   cmp_type = *ins->codep++ & 0xff;
13320   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13321     {
13322       char suffix[3];
13323       char *p = ins->mnemonicendp - 2;
13324       suffix[0] = p[0];
13325       suffix[1] = p[1];
13326       suffix[2] = '\0';
13327       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13328       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13329     }
13330   else if (ins->need_vex
13331            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13332     {
13333       char suffix[3];
13334       char *p = ins->mnemonicendp - 2;
13335       suffix[0] = p[0];
13336       suffix[1] = p[1];
13337       suffix[2] = '\0';
13338       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13339       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13340       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13341     }
13342   else
13343     {
13344       /* We have a reserved extension byte.  Output it directly.  */
13345       oappend_immediate (ins, cmp_type);
13346     }
13347 }
13348
13349 static void
13350 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13351 {
13352   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13353   if (!ins->intel_syntax)
13354     {
13355       strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13356       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13357       if (bytemode == eBX_reg)
13358         strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13359       ins->two_source_ops = true;
13360     }
13361   /* Skip mod/rm byte.  */
13362   MODRM_CHECK;
13363   ins->codep++;
13364 }
13365
13366 static void
13367 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13368             int sizeflag ATTRIBUTE_UNUSED)
13369 {
13370   /* monitor %{e,r,}ax,%ecx,%edx"  */
13371   if (!ins->intel_syntax)
13372     {
13373       const char *const *names = (ins->address_mode == mode_64bit
13374                                   ? att_names64 : att_names32);
13375
13376       if (ins->prefixes & PREFIX_ADDR)
13377         {
13378           /* Remove "addr16/addr32".  */
13379           ins->all_prefixes[ins->last_addr_prefix] = 0;
13380           names = (ins->address_mode != mode_32bit
13381                    ? att_names32 : att_names16);
13382           ins->used_prefixes |= PREFIX_ADDR;
13383         }
13384       else if (ins->address_mode == mode_16bit)
13385         names = att_names16;
13386       strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13387       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13388       strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13389       ins->two_source_ops = true;
13390     }
13391   /* Skip mod/rm byte.  */
13392   MODRM_CHECK;
13393   ins->codep++;
13394 }
13395
13396 static void
13397 BadOp (instr_info *ins)
13398 {
13399   /* Throw away prefixes and 1st. opcode byte.  */
13400   ins->codep = ins->insn_codep + 1;
13401   ins->obufp = stpcpy (ins->obufp, "(bad)");
13402 }
13403
13404 static void
13405 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13406 {
13407   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13408      lods and stos.  */
13409   if (ins->prefixes & PREFIX_REPZ)
13410     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13411
13412   switch (bytemode)
13413     {
13414     case al_reg:
13415     case eAX_reg:
13416     case indir_dx_reg:
13417       OP_IMREG (ins, bytemode, sizeflag);
13418       break;
13419     case eDI_reg:
13420       OP_ESreg (ins, bytemode, sizeflag);
13421       break;
13422     case eSI_reg:
13423       OP_DSreg (ins, bytemode, sizeflag);
13424       break;
13425     default:
13426       abort ();
13427       break;
13428     }
13429 }
13430
13431 static void
13432 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13433            int sizeflag ATTRIBUTE_UNUSED)
13434 {
13435   if (ins->isa64 != amd64)
13436     return;
13437
13438   ins->obufp = ins->obuf;
13439   BadOp (ins);
13440   ins->mnemonicendp = ins->obufp;
13441   ++ins->codep;
13442 }
13443
13444 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13445    "bnd".  */
13446
13447 static void
13448 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13449            int sizeflag ATTRIBUTE_UNUSED)
13450 {
13451   if (ins->prefixes & PREFIX_REPNZ)
13452     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13453 }
13454
13455 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13456    "notrack".  */
13457
13458 static void
13459 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13460                int sizeflag ATTRIBUTE_UNUSED)
13461 {
13462   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13463      we've seen a PREFIX_DS.  */
13464   if ((ins->prefixes & PREFIX_DS) != 0
13465       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13466     {
13467       /* NOTRACK prefix is only valid on indirect branch instructions.
13468          NB: DATA prefix is unsupported for Intel64.  */
13469       ins->active_seg_prefix = 0;
13470       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13471     }
13472 }
13473
13474 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13475    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13476  */
13477
13478 static void
13479 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13480 {
13481   if (ins->modrm.mod != 3
13482       && (ins->prefixes & PREFIX_LOCK) != 0)
13483     {
13484       if (ins->prefixes & PREFIX_REPZ)
13485         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13486       if (ins->prefixes & PREFIX_REPNZ)
13487         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13488     }
13489
13490   OP_E (ins, bytemode, sizeflag);
13491 }
13492
13493 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13494    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13495  */
13496
13497 static void
13498 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13499 {
13500   if (ins->modrm.mod != 3)
13501     {
13502       if (ins->prefixes & PREFIX_REPZ)
13503         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13504       if (ins->prefixes & PREFIX_REPNZ)
13505         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13506     }
13507
13508   OP_E (ins, bytemode, sizeflag);
13509 }
13510
13511 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13512    "xrelease" for memory operand.  No check for LOCK prefix.   */
13513
13514 static void
13515 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13516 {
13517   if (ins->modrm.mod != 3
13518       && ins->last_repz_prefix > ins->last_repnz_prefix
13519       && (ins->prefixes & PREFIX_REPZ) != 0)
13520     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13521
13522   OP_E (ins, bytemode, sizeflag);
13523 }
13524
13525 static void
13526 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13527 {
13528   USED_REX (REX_W);
13529   if (ins->rex & REX_W)
13530     {
13531       /* Change cmpxchg8b to cmpxchg16b.  */
13532       char *p = ins->mnemonicendp - 2;
13533       ins->mnemonicendp = stpcpy (p, "16b");
13534       bytemode = o_mode;
13535     }
13536   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13537     {
13538       if (ins->prefixes & PREFIX_REPZ)
13539         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13540       if (ins->prefixes & PREFIX_REPNZ)
13541         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13542     }
13543
13544   OP_M (ins, bytemode, sizeflag);
13545 }
13546
13547 static void
13548 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13549 {
13550   const char *const *names = att_names_xmm;
13551
13552   if (ins->need_vex)
13553     {
13554       switch (ins->vex.length)
13555         {
13556         case 128:
13557           break;
13558         case 256:
13559           names = att_names_ymm;
13560           break;
13561         default:
13562           abort ();
13563         }
13564     }
13565   oappend_register (ins, names[reg]);
13566 }
13567
13568 static void
13569 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13570 {
13571   /* Add proper suffix to "fxsave" and "fxrstor".  */
13572   USED_REX (REX_W);
13573   if (ins->rex & REX_W)
13574     {
13575       char *p = ins->mnemonicendp;
13576       *p++ = '6';
13577       *p++ = '4';
13578       *p = '\0';
13579       ins->mnemonicendp = p;
13580     }
13581   OP_M (ins, bytemode, sizeflag);
13582 }
13583
13584 /* Display the destination register operand for instructions with
13585    VEX. */
13586
13587 static void
13588 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13589 {
13590   int reg, modrm_reg, sib_index = -1;
13591   const char *const *names;
13592
13593   if (!ins->need_vex)
13594     abort ();
13595
13596   reg = ins->vex.register_specifier;
13597   ins->vex.register_specifier = 0;
13598   if (ins->address_mode != mode_64bit)
13599     {
13600       if (ins->vex.evex && !ins->vex.v)
13601         {
13602           oappend (ins, "(bad)");
13603           return;
13604         }
13605
13606       reg &= 7;
13607     }
13608   else if (ins->vex.evex && !ins->vex.v)
13609     reg += 16;
13610
13611   switch (bytemode)
13612     {
13613     case scalar_mode:
13614       oappend_register (ins, att_names_xmm[reg]);
13615       return;
13616
13617     case vex_vsib_d_w_dq_mode:
13618     case vex_vsib_q_w_dq_mode:
13619       /* This must be the 3rd operand.  */
13620       if (ins->obufp != ins->op_out[2])
13621         abort ();
13622       if (ins->vex.length == 128
13623           || (bytemode != vex_vsib_d_w_dq_mode
13624               && !ins->vex.w))
13625         oappend_register (ins, att_names_xmm[reg]);
13626       else
13627         oappend_register (ins, att_names_ymm[reg]);
13628
13629       /* All 3 XMM/YMM registers must be distinct.  */
13630       modrm_reg = ins->modrm.reg;
13631       if (ins->rex & REX_R)
13632         modrm_reg += 8;
13633
13634       if (ins->has_sib && ins->modrm.rm == 4)
13635         {
13636           sib_index = ins->sib.index;
13637           if (ins->rex & REX_X)
13638             sib_index += 8;
13639         }
13640
13641       if (reg == modrm_reg || reg == sib_index)
13642         strcpy (ins->obufp, "/(bad)");
13643       if (modrm_reg == sib_index || modrm_reg == reg)
13644         strcat (ins->op_out[0], "/(bad)");
13645       if (sib_index == modrm_reg || sib_index == reg)
13646         strcat (ins->op_out[1], "/(bad)");
13647
13648       return;
13649
13650     case tmm_mode:
13651       /* All 3 TMM registers must be distinct.  */
13652       if (reg >= 8)
13653         oappend (ins, "(bad)");
13654       else
13655         {
13656           /* This must be the 3rd operand.  */
13657           if (ins->obufp != ins->op_out[2])
13658             abort ();
13659           oappend_register (ins, att_names_tmm[reg]);
13660           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13661             strcpy (ins->obufp, "/(bad)");
13662         }
13663
13664       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13665           || ins->modrm.rm == reg)
13666         {
13667           if (ins->modrm.reg <= 8
13668               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13669             strcat (ins->op_out[0], "/(bad)");
13670           if (ins->modrm.rm <= 8
13671               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13672             strcat (ins->op_out[1], "/(bad)");
13673         }
13674
13675       return;
13676     }
13677
13678   switch (ins->vex.length)
13679     {
13680     case 128:
13681       switch (bytemode)
13682         {
13683         case x_mode:
13684           names = att_names_xmm;
13685           ins->evex_used |= EVEX_len_used;
13686           break;
13687         case dq_mode:
13688           if (ins->rex & REX_W)
13689             names = att_names64;
13690           else
13691             names = att_names32;
13692           break;
13693         case mask_bd_mode:
13694         case mask_mode:
13695           if (reg > 0x7)
13696             {
13697               oappend (ins, "(bad)");
13698               return;
13699             }
13700           names = att_names_mask;
13701           break;
13702         default:
13703           abort ();
13704           return;
13705         }
13706       break;
13707     case 256:
13708       switch (bytemode)
13709         {
13710         case x_mode:
13711           names = att_names_ymm;
13712           ins->evex_used |= EVEX_len_used;
13713           break;
13714         case mask_bd_mode:
13715         case mask_mode:
13716           if (reg > 0x7)
13717             {
13718               oappend (ins, "(bad)");
13719               return;
13720             }
13721           names = att_names_mask;
13722           break;
13723         default:
13724           /* See PR binutils/20893 for a reproducer.  */
13725           oappend (ins, "(bad)");
13726           return;
13727         }
13728       break;
13729     case 512:
13730       names = att_names_zmm;
13731       ins->evex_used |= EVEX_len_used;
13732       break;
13733     default:
13734       abort ();
13735       break;
13736     }
13737   oappend_register (ins, names[reg]);
13738 }
13739
13740 static void
13741 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13742 {
13743   if (ins->modrm.mod == 3)
13744     OP_VEX (ins, bytemode, sizeflag);
13745 }
13746
13747 static void
13748 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13749 {
13750   OP_VEX (ins, bytemode, sizeflag);
13751
13752   if (ins->vex.w)
13753     {
13754       /* Swap 2nd and 3rd operands.  */
13755       char *tmp = ins->op_out[2];
13756
13757       ins->op_out[2] = ins->op_out[1];
13758       ins->op_out[1] = tmp;
13759     }
13760 }
13761
13762 static void
13763 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13764 {
13765   int reg;
13766   const char *const *names = att_names_xmm;
13767
13768   FETCH_DATA (ins->info, ins->codep + 1);
13769   reg = *ins->codep++;
13770
13771   if (bytemode != x_mode && bytemode != scalar_mode)
13772     abort ();
13773
13774   reg >>= 4;
13775   if (ins->address_mode != mode_64bit)
13776     reg &= 7;
13777
13778   if (bytemode == x_mode && ins->vex.length == 256)
13779     names = att_names_ymm;
13780
13781   oappend_register (ins, names[reg]);
13782
13783   if (ins->vex.w)
13784     {
13785       /* Swap 3rd and 4th operands.  */
13786       char *tmp = ins->op_out[3];
13787
13788       ins->op_out[3] = ins->op_out[2];
13789       ins->op_out[2] = tmp;
13790     }
13791 }
13792
13793 static void
13794 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13795           int sizeflag ATTRIBUTE_UNUSED)
13796 {
13797   oappend_immediate (ins, ins->codep[-1] & 0xf);
13798 }
13799
13800 static void
13801 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13802              int sizeflag ATTRIBUTE_UNUSED)
13803 {
13804   unsigned int cmp_type;
13805
13806   if (!ins->vex.evex)
13807     abort ();
13808
13809   FETCH_DATA (ins->info, ins->codep + 1);
13810   cmp_type = *ins->codep++ & 0xff;
13811   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13812      If it's the case, print suffix, otherwise - print the immediate.  */
13813   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13814       && cmp_type != 3
13815       && cmp_type != 7)
13816     {
13817       char suffix[3];
13818       char *p = ins->mnemonicendp - 2;
13819
13820       /* vpcmp* can have both one- and two-lettered suffix.  */
13821       if (p[0] == 'p')
13822         {
13823           p++;
13824           suffix[0] = p[0];
13825           suffix[1] = '\0';
13826         }
13827       else
13828         {
13829           suffix[0] = p[0];
13830           suffix[1] = p[1];
13831           suffix[2] = '\0';
13832         }
13833
13834       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13835       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13836     }
13837   else
13838     {
13839       /* We have a reserved extension byte.  Output it directly.  */
13840       oappend_immediate (ins, cmp_type);
13841     }
13842 }
13843
13844 static const struct op xop_cmp_op[] =
13845 {
13846   { STRING_COMMA_LEN ("lt") },
13847   { STRING_COMMA_LEN ("le") },
13848   { STRING_COMMA_LEN ("gt") },
13849   { STRING_COMMA_LEN ("ge") },
13850   { STRING_COMMA_LEN ("eq") },
13851   { STRING_COMMA_LEN ("neq") },
13852   { STRING_COMMA_LEN ("false") },
13853   { STRING_COMMA_LEN ("true") }
13854 };
13855
13856 static void
13857 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13858              int sizeflag ATTRIBUTE_UNUSED)
13859 {
13860   unsigned int cmp_type;
13861
13862   FETCH_DATA (ins->info, ins->codep + 1);
13863   cmp_type = *ins->codep++ & 0xff;
13864   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13865     {
13866       char suffix[3];
13867       char *p = ins->mnemonicendp - 2;
13868
13869       /* vpcom* can have both one- and two-lettered suffix.  */
13870       if (p[0] == 'm')
13871         {
13872           p++;
13873           suffix[0] = p[0];
13874           suffix[1] = '\0';
13875         }
13876       else
13877         {
13878           suffix[0] = p[0];
13879           suffix[1] = p[1];
13880           suffix[2] = '\0';
13881         }
13882
13883       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13884       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13885     }
13886   else
13887     {
13888       /* We have a reserved extension byte.  Output it directly.  */
13889       oappend_immediate (ins, cmp_type);
13890     }
13891 }
13892
13893 static const struct op pclmul_op[] =
13894 {
13895   { STRING_COMMA_LEN ("lql") },
13896   { STRING_COMMA_LEN ("hql") },
13897   { STRING_COMMA_LEN ("lqh") },
13898   { STRING_COMMA_LEN ("hqh") }
13899 };
13900
13901 static void
13902 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13903               int sizeflag ATTRIBUTE_UNUSED)
13904 {
13905   unsigned int pclmul_type;
13906
13907   FETCH_DATA (ins->info, ins->codep + 1);
13908   pclmul_type = *ins->codep++ & 0xff;
13909   switch (pclmul_type)
13910     {
13911     case 0x10:
13912       pclmul_type = 2;
13913       break;
13914     case 0x11:
13915       pclmul_type = 3;
13916       break;
13917     default:
13918       break;
13919     }
13920   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13921     {
13922       char suffix[4];
13923       char *p = ins->mnemonicendp - 3;
13924       suffix[0] = p[0];
13925       suffix[1] = p[1];
13926       suffix[2] = p[2];
13927       suffix[3] = '\0';
13928       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13929       ins->mnemonicendp += pclmul_op[pclmul_type].len;
13930     }
13931   else
13932     {
13933       /* We have a reserved extension byte.  Output it directly.  */
13934       oappend_immediate (ins, pclmul_type);
13935     }
13936 }
13937
13938 static void
13939 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13940 {
13941   /* Add proper suffix to "movsxd".  */
13942   char *p = ins->mnemonicendp;
13943
13944   switch (bytemode)
13945     {
13946     case movsxd_mode:
13947       if (!ins->intel_syntax)
13948         {
13949           USED_REX (REX_W);
13950           if (ins->rex & REX_W)
13951             {
13952               *p++ = 'l';
13953               *p++ = 'q';
13954               break;
13955             }
13956         }
13957
13958       *p++ = 'x';
13959       *p++ = 'd';
13960       break;
13961     default:
13962       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13963       break;
13964     }
13965
13966   ins->mnemonicendp = p;
13967   *p = '\0';
13968   OP_E (ins, bytemode, sizeflag);
13969 }
13970
13971 static void
13972 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13973 {
13974   unsigned int reg = ins->vex.register_specifier;
13975   unsigned int modrm_reg = ins->modrm.reg;
13976   unsigned int modrm_rm = ins->modrm.rm;
13977
13978   /* Calc destination register number.  */
13979   if (ins->rex & REX_R)
13980     modrm_reg += 8;
13981   if (!ins->vex.r)
13982     modrm_reg += 16;
13983
13984   /* Calc src1 register number.  */
13985   if (ins->address_mode != mode_64bit)
13986     reg &= 7;
13987   else if (ins->vex.evex && !ins->vex.v)
13988     reg += 16;
13989
13990   /* Calc src2 register number.  */
13991   if (ins->modrm.mod == 3)
13992     {
13993       if (ins->rex & REX_B)
13994         modrm_rm += 8;
13995       if (ins->rex & REX_X)
13996         modrm_rm += 16;
13997     }
13998
13999   /* Destination and source registers must be distinct, output bad if
14000      dest == src1 or dest == src2.  */
14001   if (modrm_reg == reg
14002       || (ins->modrm.mod == 3
14003           && modrm_reg == modrm_rm))
14004     {
14005       oappend (ins, "(bad)");
14006     }
14007   else
14008     OP_XMM (ins, bytemode, sizeflag);
14009 }
14010
14011 static void
14012 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14013 {
14014   if (ins->modrm.mod != 3 || !ins->vex.b)
14015     return;
14016
14017   switch (bytemode)
14018     {
14019     case evex_rounding_64_mode:
14020       if (ins->address_mode != mode_64bit || !ins->vex.w)
14021         return;
14022       /* Fall through.  */
14023     case evex_rounding_mode:
14024       ins->evex_used |= EVEX_b_used;
14025       oappend (ins, names_rounding[ins->vex.ll]);
14026       break;
14027     case evex_sae_mode:
14028       ins->evex_used |= EVEX_b_used;
14029       oappend (ins, "{");
14030       break;
14031     default:
14032       abort ();
14033     }
14034   oappend (ins, "sae}");
14035 }
14036
14037 static void
14038 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
14039 {
14040   if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
14041     {
14042       if (ins->intel_syntax)
14043         {
14044           ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
14045         }
14046       else
14047         {
14048           USED_REX (REX_W);
14049           if (ins->rex & REX_W)
14050             ins->mnemonicendp = stpcpy (ins->obuf, "nopq  ");
14051           else
14052             {
14053               if (sizeflag & DFLAG)
14054                 ins->mnemonicendp = stpcpy (ins->obuf, "nopl  ");
14055               else
14056                 ins->mnemonicendp = stpcpy (ins->obuf, "nopw  ");
14057               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14058             }
14059         }
14060       bytemode = v_mode;
14061     }
14062
14063   OP_M (ins, bytemode, sizeflag);
14064 }