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Fix -Wmaybe-uninitialized warning in opcodes/i386-dis.c
[binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2023 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 typedef struct instr_info instr_info;
43
44 static bool dofloat (instr_info *, int);
45 static int putop (instr_info *, const char *, int);
46 static void oappend_with_style (instr_info *, const char *,
47 enum disassembler_style);
48 static void oappend (instr_info *, const char *);
49 static void append_seg (instr_info *);
50 static bool get32s (instr_info *, bfd_signed_vma *);
51 static bool get16 (instr_info *, int *);
52 static void set_op (instr_info *, bfd_vma, bool);
53
54 static bool OP_E (instr_info *, int, int);
55 static bool OP_E_memory (instr_info *, int, int);
56 static bool OP_indirE (instr_info *, int, int);
57 static bool OP_G (instr_info *, int, int);
58 static bool OP_ST (instr_info *, int, int);
59 static bool OP_STi (instr_info *, int, int);
60 static bool OP_Skip_MODRM (instr_info *, int, int);
61 static bool OP_REG (instr_info *, int, int);
62 static bool OP_IMREG (instr_info *, int, int);
63 static bool OP_I (instr_info *, int, int);
64 static bool OP_I64 (instr_info *, int, int);
65 static bool OP_sI (instr_info *, int, int);
66 static bool OP_J (instr_info *, int, int);
67 static bool OP_SEG (instr_info *, int, int);
68 static bool OP_DIR (instr_info *, int, int);
69 static bool OP_OFF (instr_info *, int, int);
70 static bool OP_OFF64 (instr_info *, int, int);
71 static bool OP_ESreg (instr_info *, int, int);
72 static bool OP_DSreg (instr_info *, int, int);
73 static bool OP_C (instr_info *, int, int);
74 static bool OP_D (instr_info *, int, int);
75 static bool OP_T (instr_info *, int, int);
76 static bool OP_MMX (instr_info *, int, int);
77 static bool OP_XMM (instr_info *, int, int);
78 static bool OP_EM (instr_info *, int, int);
79 static bool OP_EX (instr_info *, int, int);
80 static bool OP_EMC (instr_info *, int,int);
81 static bool OP_MXC (instr_info *, int,int);
82 static bool OP_MS (instr_info *, int, int);
83 static bool OP_XS (instr_info *, int, int);
84 static bool OP_M (instr_info *, int, int);
85 static bool OP_VEX (instr_info *, int, int);
86 static bool OP_VexR (instr_info *, int, int);
87 static bool OP_VexW (instr_info *, int, int);
88 static bool OP_Rounding (instr_info *, int, int);
89 static bool OP_REG_VexI4 (instr_info *, int, int);
90 static bool OP_VexI4 (instr_info *, int, int);
91 static bool OP_0f07 (instr_info *, int, int);
92 static bool OP_Monitor (instr_info *, int, int);
93 static bool OP_Mwait (instr_info *, int, int);
94
95 static bool BadOp (instr_info *);
96
97 static bool PCLMUL_Fixup (instr_info *, int, int);
98 static bool VPCMP_Fixup (instr_info *, int, int);
99 static bool VPCOM_Fixup (instr_info *, int, int);
100 static bool NOP_Fixup (instr_info *, int, int);
101 static bool OP_3DNowSuffix (instr_info *, int, int);
102 static bool CMP_Fixup (instr_info *, int, int);
103 static bool REP_Fixup (instr_info *, int, int);
104 static bool SEP_Fixup (instr_info *, int, int);
105 static bool BND_Fixup (instr_info *, int, int);
106 static bool NOTRACK_Fixup (instr_info *, int, int);
107 static bool HLE_Fixup1 (instr_info *, int, int);
108 static bool HLE_Fixup2 (instr_info *, int, int);
109 static bool HLE_Fixup3 (instr_info *, int, int);
110 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
111 static bool XMM_Fixup (instr_info *, int, int);
112 static bool FXSAVE_Fixup (instr_info *, int, int);
113 static bool MOVSXD_Fixup (instr_info *, int, int);
114 static bool DistinctDest_Fixup (instr_info *, int, int);
115 static bool PREFETCHI_Fixup (instr_info *, int, int);
116
117 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const instr_info *,
118 enum disassembler_style,
119 const char *, ...);
120 static const char *prefix_name (const instr_info *, int, int);
121
122 /* This character is used to encode style information within the output
123 buffers. See oappend_insert_style for more details. */
124 #define STYLE_MARKER_CHAR '\002'
125
126 /* The maximum operand buffer size. */
127 #define MAX_OPERAND_BUFFER_SIZE 128
128
129 struct dis_private {
130 /* Points to first byte not fetched. */
131 bfd_byte *max_fetched;
132 bfd_byte the_buffer[MAX_MNEM_SIZE];
133 bfd_vma insn_start;
134 int orig_sizeflag;
135 };
136
137 enum address_mode
138 {
139 mode_16bit,
140 mode_32bit,
141 mode_64bit
142 };
143
144 enum x86_64_isa
145 {
146 amd64 = 1,
147 intel64
148 };
149
150 struct instr_info
151 {
152 enum address_mode address_mode;
153
154 /* Flags for the prefixes for the current instruction. See below. */
155 int prefixes;
156
157 /* REX prefix the current instruction. See below. */
158 unsigned char rex;
159 /* Bits of REX we've already used. */
160 unsigned char rex_used;
161
162 bool need_modrm;
163 bool need_vex;
164 bool has_sib;
165
166 /* Flags for ins->prefixes which we somehow handled when printing the
167 current instruction. */
168 int used_prefixes;
169
170 /* Flags for EVEX bits which we somehow handled when printing the
171 current instruction. */
172 int evex_used;
173
174 char obuf[MAX_OPERAND_BUFFER_SIZE];
175 char *obufp;
176 char *mnemonicendp;
177 unsigned char *start_codep;
178 unsigned char *insn_codep;
179 unsigned char *codep;
180 unsigned char *end_codep;
181 signed char last_lock_prefix;
182 signed char last_repz_prefix;
183 signed char last_repnz_prefix;
184 signed char last_data_prefix;
185 signed char last_addr_prefix;
186 signed char last_rex_prefix;
187 signed char last_seg_prefix;
188 signed char fwait_prefix;
189 /* The active segment register prefix. */
190 unsigned char active_seg_prefix;
191
192 #define MAX_CODE_LENGTH 15
193 /* We can up to 14 ins->prefixes since the maximum instruction length is
194 15bytes. */
195 unsigned char all_prefixes[MAX_CODE_LENGTH - 1];
196 disassemble_info *info;
197
198 struct
199 {
200 int mod;
201 int reg;
202 int rm;
203 }
204 modrm;
205
206 struct
207 {
208 int scale;
209 int index;
210 int base;
211 }
212 sib;
213
214 struct
215 {
216 int register_specifier;
217 int length;
218 int prefix;
219 int mask_register_specifier;
220 int ll;
221 bool w;
222 bool evex;
223 bool r;
224 bool v;
225 bool zeroing;
226 bool b;
227 bool no_broadcast;
228 }
229 vex;
230
231 /* Remember if the current op is a jump instruction. */
232 bool op_is_jump;
233
234 bool two_source_ops;
235
236 unsigned char op_ad;
237 signed char op_index[MAX_OPERANDS];
238 bool op_riprel[MAX_OPERANDS];
239 char *op_out[MAX_OPERANDS];
240 bfd_vma op_address[MAX_OPERANDS];
241 bfd_vma start_pc;
242
243 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
244 * (see topic "Redundant ins->prefixes" in the "Differences from 8086"
245 * section of the "Virtual 8086 Mode" chapter.)
246 * 'pc' should be the address of this instruction, it will
247 * be used to print the target address if this is a relative jump or call
248 * The function returns the length of this instruction in bytes.
249 */
250 char intel_syntax;
251 bool intel_mnemonic;
252 char open_char;
253 char close_char;
254 char separator_char;
255 char scale_char;
256
257 enum x86_64_isa isa64;
258 };
259
260 /* Mark parts used in the REX prefix. When we are testing for
261 empty prefix (for 8bit register REX extension), just mask it
262 out. Otherwise test for REX bit is excuse for existence of REX
263 only in case value is nonzero. */
264 #define USED_REX(value) \
265 { \
266 if (value) \
267 { \
268 if ((ins->rex & value)) \
269 ins->rex_used |= (value) | REX_OPCODE; \
270 } \
271 else \
272 ins->rex_used |= REX_OPCODE; \
273 }
274
275
276 #define EVEX_b_used 1
277 #define EVEX_len_used 2
278
279 /* Flags stored in PREFIXES. */
280 #define PREFIX_REPZ 1
281 #define PREFIX_REPNZ 2
282 #define PREFIX_CS 4
283 #define PREFIX_SS 8
284 #define PREFIX_DS 0x10
285 #define PREFIX_ES 0x20
286 #define PREFIX_FS 0x40
287 #define PREFIX_GS 0x80
288 #define PREFIX_LOCK 0x100
289 #define PREFIX_DATA 0x200
290 #define PREFIX_ADDR 0x400
291 #define PREFIX_FWAIT 0x800
292
293 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
294 to ADDR (exclusive) are valid. Returns true for success, false
295 on error. */
296 static bool
297 fetch_code (struct disassemble_info *info, bfd_byte *until)
298 {
299 int status = -1;
300 struct dis_private *priv = info->private_data;
301 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
302
303 if (until <= priv->max_fetched)
304 return true;
305
306 if (until <= priv->the_buffer + MAX_MNEM_SIZE)
307 status = (*info->read_memory_func) (start,
308 priv->max_fetched,
309 until - priv->max_fetched,
310 info);
311 if (status != 0)
312 {
313 /* If we did manage to read at least one byte, then
314 print_insn_i386 will do something sensible. Otherwise, print
315 an error. We do that here because this is where we know
316 STATUS. */
317 if (priv->max_fetched == priv->the_buffer)
318 (*info->memory_error_func) (status, start, info);
319 return false;
320 }
321
322 priv->max_fetched = until;
323 return true;
324 }
325
326 static bool
327 fetch_modrm (instr_info *ins)
328 {
329 if (!fetch_code (ins->info, ins->codep + 1))
330 return false;
331
332 ins->modrm.mod = (*ins->codep >> 6) & 3;
333 ins->modrm.reg = (*ins->codep >> 3) & 7;
334 ins->modrm.rm = *ins->codep & 7;
335
336 return true;
337 }
338
339 static int
340 fetch_error (const instr_info *ins)
341 {
342 /* Getting here means we tried for data but didn't get it. That
343 means we have an incomplete instruction of some sort. Just
344 print the first byte as a prefix or a .byte pseudo-op. */
345 const struct dis_private *priv = ins->info->private_data;
346 const char *name = NULL;
347
348 if (ins->codep <= priv->the_buffer)
349 return -1;
350
351 if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
352 name = prefix_name (ins, priv->the_buffer[0], priv->orig_sizeflag);
353 if (name != NULL)
354 i386_dis_printf (ins, dis_style_mnemonic, "%s", name);
355 else
356 {
357 /* Just print the first byte as a .byte instruction. */
358 i386_dis_printf (ins, dis_style_assembler_directive, ".byte ");
359 i386_dis_printf (ins, dis_style_immediate, "%#x",
360 (unsigned int) priv->the_buffer[0]);
361 }
362
363 return 1;
364 }
365
366 /* Possible values for prefix requirement. */
367 #define PREFIX_IGNORED_SHIFT 16
368 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
369 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
370 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
371 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
372 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
373
374 /* Opcode prefixes. */
375 #define PREFIX_OPCODE (PREFIX_REPZ \
376 | PREFIX_REPNZ \
377 | PREFIX_DATA)
378
379 /* Prefixes ignored. */
380 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
381 | PREFIX_IGNORED_REPNZ \
382 | PREFIX_IGNORED_DATA)
383
384 #define XX { NULL, 0 }
385 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
386
387 #define Eb { OP_E, b_mode }
388 #define Ebnd { OP_E, bnd_mode }
389 #define EbS { OP_E, b_swap_mode }
390 #define EbndS { OP_E, bnd_swap_mode }
391 #define Ev { OP_E, v_mode }
392 #define Eva { OP_E, va_mode }
393 #define Ev_bnd { OP_E, v_bnd_mode }
394 #define EvS { OP_E, v_swap_mode }
395 #define Ed { OP_E, d_mode }
396 #define Edq { OP_E, dq_mode }
397 #define Edb { OP_E, db_mode }
398 #define Edw { OP_E, dw_mode }
399 #define Eq { OP_E, q_mode }
400 #define indirEv { OP_indirE, indir_v_mode }
401 #define indirEp { OP_indirE, f_mode }
402 #define stackEv { OP_E, stack_v_mode }
403 #define Em { OP_E, m_mode }
404 #define Ew { OP_E, w_mode }
405 #define M { OP_M, 0 } /* lea, lgdt, etc. */
406 #define Ma { OP_M, a_mode }
407 #define Mb { OP_M, b_mode }
408 #define Md { OP_M, d_mode }
409 #define Mdq { OP_M, dq_mode }
410 #define Mo { OP_M, o_mode }
411 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
412 #define Mq { OP_M, q_mode }
413 #define Mv { OP_M, v_mode }
414 #define Mv_bnd { OP_M, v_bndmk_mode }
415 #define Mw { OP_M, w_mode }
416 #define Mx { OP_M, x_mode }
417 #define Mxmm { OP_M, xmm_mode }
418 #define Gb { OP_G, b_mode }
419 #define Gbnd { OP_G, bnd_mode }
420 #define Gv { OP_G, v_mode }
421 #define Gd { OP_G, d_mode }
422 #define Gdq { OP_G, dq_mode }
423 #define Gm { OP_G, m_mode }
424 #define Gva { OP_G, va_mode }
425 #define Gw { OP_G, w_mode }
426 #define Ib { OP_I, b_mode }
427 #define sIb { OP_sI, b_mode } /* sign extened byte */
428 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
429 #define Iv { OP_I, v_mode }
430 #define sIv { OP_sI, v_mode }
431 #define Iv64 { OP_I64, v_mode }
432 #define Id { OP_I, d_mode }
433 #define Iw { OP_I, w_mode }
434 #define I1 { OP_I, const_1_mode }
435 #define Jb { OP_J, b_mode }
436 #define Jv { OP_J, v_mode }
437 #define Jdqw { OP_J, dqw_mode }
438 #define Cm { OP_C, m_mode }
439 #define Dm { OP_D, m_mode }
440 #define Td { OP_T, d_mode }
441 #define Skip_MODRM { OP_Skip_MODRM, 0 }
442
443 #define RMeAX { OP_REG, eAX_reg }
444 #define RMeBX { OP_REG, eBX_reg }
445 #define RMeCX { OP_REG, eCX_reg }
446 #define RMeDX { OP_REG, eDX_reg }
447 #define RMeSP { OP_REG, eSP_reg }
448 #define RMeBP { OP_REG, eBP_reg }
449 #define RMeSI { OP_REG, eSI_reg }
450 #define RMeDI { OP_REG, eDI_reg }
451 #define RMrAX { OP_REG, rAX_reg }
452 #define RMrBX { OP_REG, rBX_reg }
453 #define RMrCX { OP_REG, rCX_reg }
454 #define RMrDX { OP_REG, rDX_reg }
455 #define RMrSP { OP_REG, rSP_reg }
456 #define RMrBP { OP_REG, rBP_reg }
457 #define RMrSI { OP_REG, rSI_reg }
458 #define RMrDI { OP_REG, rDI_reg }
459 #define RMAL { OP_REG, al_reg }
460 #define RMCL { OP_REG, cl_reg }
461 #define RMDL { OP_REG, dl_reg }
462 #define RMBL { OP_REG, bl_reg }
463 #define RMAH { OP_REG, ah_reg }
464 #define RMCH { OP_REG, ch_reg }
465 #define RMDH { OP_REG, dh_reg }
466 #define RMBH { OP_REG, bh_reg }
467 #define RMAX { OP_REG, ax_reg }
468 #define RMDX { OP_REG, dx_reg }
469
470 #define eAX { OP_IMREG, eAX_reg }
471 #define AL { OP_IMREG, al_reg }
472 #define CL { OP_IMREG, cl_reg }
473 #define zAX { OP_IMREG, z_mode_ax_reg }
474 #define indirDX { OP_IMREG, indir_dx_reg }
475
476 #define Sw { OP_SEG, w_mode }
477 #define Sv { OP_SEG, v_mode }
478 #define Ap { OP_DIR, 0 }
479 #define Ob { OP_OFF64, b_mode }
480 #define Ov { OP_OFF64, v_mode }
481 #define Xb { OP_DSreg, eSI_reg }
482 #define Xv { OP_DSreg, eSI_reg }
483 #define Xz { OP_DSreg, eSI_reg }
484 #define Yb { OP_ESreg, eDI_reg }
485 #define Yv { OP_ESreg, eDI_reg }
486 #define DSBX { OP_DSreg, eBX_reg }
487
488 #define es { OP_REG, es_reg }
489 #define ss { OP_REG, ss_reg }
490 #define cs { OP_REG, cs_reg }
491 #define ds { OP_REG, ds_reg }
492 #define fs { OP_REG, fs_reg }
493 #define gs { OP_REG, gs_reg }
494
495 #define MX { OP_MMX, 0 }
496 #define XM { OP_XMM, 0 }
497 #define XMScalar { OP_XMM, scalar_mode }
498 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
499 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
500 #define XMM { OP_XMM, xmm_mode }
501 #define TMM { OP_XMM, tmm_mode }
502 #define XMxmmq { OP_XMM, xmmq_mode }
503 #define EM { OP_EM, v_mode }
504 #define EMS { OP_EM, v_swap_mode }
505 #define EMd { OP_EM, d_mode }
506 #define EMx { OP_EM, x_mode }
507 #define EXbwUnit { OP_EX, bw_unit_mode }
508 #define EXb { OP_EX, b_mode }
509 #define EXw { OP_EX, w_mode }
510 #define EXd { OP_EX, d_mode }
511 #define EXdS { OP_EX, d_swap_mode }
512 #define EXwS { OP_EX, w_swap_mode }
513 #define EXq { OP_EX, q_mode }
514 #define EXqS { OP_EX, q_swap_mode }
515 #define EXdq { OP_EX, dq_mode }
516 #define EXx { OP_EX, x_mode }
517 #define EXxh { OP_EX, xh_mode }
518 #define EXxS { OP_EX, x_swap_mode }
519 #define EXxmm { OP_EX, xmm_mode }
520 #define EXymm { OP_EX, ymm_mode }
521 #define EXtmm { OP_EX, tmm_mode }
522 #define EXxmmq { OP_EX, xmmq_mode }
523 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
524 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
525 #define EXxmmdw { OP_EX, xmmdw_mode }
526 #define EXxmmqd { OP_EX, xmmqd_mode }
527 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
528 #define EXymmq { OP_EX, ymmq_mode }
529 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
530 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
531 #define MS { OP_MS, v_mode }
532 #define XS { OP_XS, v_mode }
533 #define EMCq { OP_EMC, q_mode }
534 #define MXC { OP_MXC, 0 }
535 #define OPSUF { OP_3DNowSuffix, 0 }
536 #define SEP { SEP_Fixup, 0 }
537 #define CMP { CMP_Fixup, 0 }
538 #define XMM0 { XMM_Fixup, 0 }
539 #define FXSAVE { FXSAVE_Fixup, 0 }
540
541 #define Vex { OP_VEX, x_mode }
542 #define VexW { OP_VexW, x_mode }
543 #define VexScalar { OP_VEX, scalar_mode }
544 #define VexScalarR { OP_VexR, scalar_mode }
545 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
546 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
547 #define VexGdq { OP_VEX, dq_mode }
548 #define VexTmm { OP_VEX, tmm_mode }
549 #define XMVexI4 { OP_REG_VexI4, x_mode }
550 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
551 #define VexI4 { OP_VexI4, 0 }
552 #define PCLMUL { PCLMUL_Fixup, 0 }
553 #define VPCMP { VPCMP_Fixup, 0 }
554 #define VPCOM { VPCOM_Fixup, 0 }
555
556 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
557 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
558 #define EXxEVexS { OP_Rounding, evex_sae_mode }
559
560 #define MaskG { OP_G, mask_mode }
561 #define MaskE { OP_E, mask_mode }
562 #define MaskBDE { OP_E, mask_bd_mode }
563 #define MaskVex { OP_VEX, mask_mode }
564
565 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
566 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
567
568 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
569
570 /* Used handle "rep" prefix for string instructions. */
571 #define Xbr { REP_Fixup, eSI_reg }
572 #define Xvr { REP_Fixup, eSI_reg }
573 #define Ybr { REP_Fixup, eDI_reg }
574 #define Yvr { REP_Fixup, eDI_reg }
575 #define Yzr { REP_Fixup, eDI_reg }
576 #define indirDXr { REP_Fixup, indir_dx_reg }
577 #define ALr { REP_Fixup, al_reg }
578 #define eAXr { REP_Fixup, eAX_reg }
579
580 /* Used handle HLE prefix for lockable instructions. */
581 #define Ebh1 { HLE_Fixup1, b_mode }
582 #define Evh1 { HLE_Fixup1, v_mode }
583 #define Ebh2 { HLE_Fixup2, b_mode }
584 #define Evh2 { HLE_Fixup2, v_mode }
585 #define Ebh3 { HLE_Fixup3, b_mode }
586 #define Evh3 { HLE_Fixup3, v_mode }
587
588 #define BND { BND_Fixup, 0 }
589 #define NOTRACK { NOTRACK_Fixup, 0 }
590
591 #define cond_jump_flag { NULL, cond_jump_mode }
592 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
593
594 /* bits in sizeflag */
595 #define SUFFIX_ALWAYS 4
596 #define AFLAG 2
597 #define DFLAG 1
598
599 enum
600 {
601 /* byte operand */
602 b_mode = 1,
603 /* byte operand with operand swapped */
604 b_swap_mode,
605 /* byte operand, sign extend like 'T' suffix */
606 b_T_mode,
607 /* operand size depends on prefixes */
608 v_mode,
609 /* operand size depends on prefixes with operand swapped */
610 v_swap_mode,
611 /* operand size depends on address prefix */
612 va_mode,
613 /* word operand */
614 w_mode,
615 /* double word operand */
616 d_mode,
617 /* word operand with operand swapped */
618 w_swap_mode,
619 /* double word operand with operand swapped */
620 d_swap_mode,
621 /* quad word operand */
622 q_mode,
623 /* quad word operand with operand swapped */
624 q_swap_mode,
625 /* ten-byte operand */
626 t_mode,
627 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
628 broadcast enabled. */
629 x_mode,
630 /* Similar to x_mode, but with different EVEX mem shifts. */
631 evex_x_gscat_mode,
632 /* Similar to x_mode, but with yet different EVEX mem shifts. */
633 bw_unit_mode,
634 /* Similar to x_mode, but with disabled broadcast. */
635 evex_x_nobcst_mode,
636 /* Similar to x_mode, but with operands swapped and disabled broadcast
637 in EVEX. */
638 x_swap_mode,
639 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
640 broadcast of 16bit enabled. */
641 xh_mode,
642 /* 16-byte XMM operand */
643 xmm_mode,
644 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
645 memory operand (depending on vector length). Broadcast isn't
646 allowed. */
647 xmmq_mode,
648 /* Same as xmmq_mode, but broadcast is allowed. */
649 evex_half_bcst_xmmq_mode,
650 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
651 memory operand (depending on vector length). 16bit broadcast. */
652 evex_half_bcst_xmmqh_mode,
653 /* 16-byte XMM, word, double word or quad word operand. */
654 xmmdw_mode,
655 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
656 xmmqd_mode,
657 /* 16-byte XMM, double word, quad word operand or xmm word operand.
658 16bit broadcast. */
659 evex_half_bcst_xmmqdh_mode,
660 /* 32-byte YMM operand */
661 ymm_mode,
662 /* quad word, ymmword or zmmword memory operand. */
663 ymmq_mode,
664 /* TMM operand */
665 tmm_mode,
666 /* d_mode in 32bit, q_mode in 64bit mode. */
667 m_mode,
668 /* pair of v_mode operands */
669 a_mode,
670 cond_jump_mode,
671 loop_jcxz_mode,
672 movsxd_mode,
673 v_bnd_mode,
674 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
675 v_bndmk_mode,
676 /* operand size depends on REX.W / VEX.W. */
677 dq_mode,
678 /* Displacements like v_mode without considering Intel64 ISA. */
679 dqw_mode,
680 /* bounds operand */
681 bnd_mode,
682 /* bounds operand with operand swapped */
683 bnd_swap_mode,
684 /* 4- or 6-byte pointer operand */
685 f_mode,
686 const_1_mode,
687 /* v_mode for indirect branch opcodes. */
688 indir_v_mode,
689 /* v_mode for stack-related opcodes. */
690 stack_v_mode,
691 /* non-quad operand size depends on prefixes */
692 z_mode,
693 /* 16-byte operand */
694 o_mode,
695 /* registers like d_mode, memory like b_mode. */
696 db_mode,
697 /* registers like d_mode, memory like w_mode. */
698 dw_mode,
699
700 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
701 vex_vsib_d_w_dq_mode,
702 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
703 vex_vsib_q_w_dq_mode,
704 /* mandatory non-vector SIB. */
705 vex_sibmem_mode,
706
707 /* scalar, ignore vector length. */
708 scalar_mode,
709
710 /* Static rounding. */
711 evex_rounding_mode,
712 /* Static rounding, 64-bit mode only. */
713 evex_rounding_64_mode,
714 /* Supress all exceptions. */
715 evex_sae_mode,
716
717 /* Mask register operand. */
718 mask_mode,
719 /* Mask register operand. */
720 mask_bd_mode,
721
722 es_reg,
723 cs_reg,
724 ss_reg,
725 ds_reg,
726 fs_reg,
727 gs_reg,
728
729 eAX_reg,
730 eCX_reg,
731 eDX_reg,
732 eBX_reg,
733 eSP_reg,
734 eBP_reg,
735 eSI_reg,
736 eDI_reg,
737
738 al_reg,
739 cl_reg,
740 dl_reg,
741 bl_reg,
742 ah_reg,
743 ch_reg,
744 dh_reg,
745 bh_reg,
746
747 ax_reg,
748 cx_reg,
749 dx_reg,
750 bx_reg,
751 sp_reg,
752 bp_reg,
753 si_reg,
754 di_reg,
755
756 rAX_reg,
757 rCX_reg,
758 rDX_reg,
759 rBX_reg,
760 rSP_reg,
761 rBP_reg,
762 rSI_reg,
763 rDI_reg,
764
765 z_mode_ax_reg,
766 indir_dx_reg
767 };
768
769 enum
770 {
771 FLOATCODE = 1,
772 USE_REG_TABLE,
773 USE_MOD_TABLE,
774 USE_RM_TABLE,
775 USE_PREFIX_TABLE,
776 USE_X86_64_TABLE,
777 USE_3BYTE_TABLE,
778 USE_XOP_8F_TABLE,
779 USE_VEX_C4_TABLE,
780 USE_VEX_C5_TABLE,
781 USE_VEX_LEN_TABLE,
782 USE_VEX_W_TABLE,
783 USE_EVEX_TABLE,
784 USE_EVEX_LEN_TABLE
785 };
786
787 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
788
789 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
790 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
791 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
792 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
793 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
794 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
795 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
796 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
797 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
798 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
799 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
800 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
801 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
802 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
803 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
804 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
805
806 enum
807 {
808 REG_80 = 0,
809 REG_81,
810 REG_83,
811 REG_8F,
812 REG_C0,
813 REG_C1,
814 REG_C6,
815 REG_C7,
816 REG_D0,
817 REG_D1,
818 REG_D2,
819 REG_D3,
820 REG_F6,
821 REG_F7,
822 REG_FE,
823 REG_FF,
824 REG_0F00,
825 REG_0F01,
826 REG_0F0D,
827 REG_0F18,
828 REG_0F1C_P_0_MOD_0,
829 REG_0F1E_P_1_MOD_3,
830 REG_0F38D8_PREFIX_1,
831 REG_0F3A0F_PREFIX_1_MOD_3,
832 REG_0F71_MOD_0,
833 REG_0F72_MOD_0,
834 REG_0F73_MOD_0,
835 REG_0FA6,
836 REG_0FA7,
837 REG_0FAE,
838 REG_0FBA,
839 REG_0FC7,
840 REG_VEX_0F71_M_0,
841 REG_VEX_0F72_M_0,
842 REG_VEX_0F73_M_0,
843 REG_VEX_0FAE,
844 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
845 REG_VEX_0F38F3_L_0,
846
847 REG_XOP_09_01_L_0,
848 REG_XOP_09_02_L_0,
849 REG_XOP_09_12_M_1_L_0,
850 REG_XOP_0A_12_L_0,
851
852 REG_EVEX_0F71,
853 REG_EVEX_0F72,
854 REG_EVEX_0F73,
855 REG_EVEX_0F38C6_M_0_L_2,
856 REG_EVEX_0F38C7_M_0_L_2
857 };
858
859 enum
860 {
861 MOD_62_32BIT = 0,
862 MOD_8D,
863 MOD_C4_32BIT,
864 MOD_C5_32BIT,
865 MOD_C6_REG_7,
866 MOD_C7_REG_7,
867 MOD_FF_REG_3,
868 MOD_FF_REG_5,
869 MOD_0F01_REG_0,
870 MOD_0F01_REG_1,
871 MOD_0F01_REG_2,
872 MOD_0F01_REG_3,
873 MOD_0F01_REG_5,
874 MOD_0F01_REG_7,
875 MOD_0F02,
876 MOD_0F03,
877 MOD_0F12_PREFIX_0,
878 MOD_0F12_PREFIX_2,
879 MOD_0F13,
880 MOD_0F16_PREFIX_0,
881 MOD_0F16_PREFIX_2,
882 MOD_0F17,
883 MOD_0F18_REG_0,
884 MOD_0F18_REG_1,
885 MOD_0F18_REG_2,
886 MOD_0F18_REG_3,
887 MOD_0F18_REG_6,
888 MOD_0F18_REG_7,
889 MOD_0F1A_PREFIX_0,
890 MOD_0F1B_PREFIX_0,
891 MOD_0F1B_PREFIX_1,
892 MOD_0F1C_PREFIX_0,
893 MOD_0F1E_PREFIX_1,
894 MOD_0F2B_PREFIX_0,
895 MOD_0F2B_PREFIX_1,
896 MOD_0F2B_PREFIX_2,
897 MOD_0F2B_PREFIX_3,
898 MOD_0F50,
899 MOD_0F71,
900 MOD_0F72,
901 MOD_0F73,
902 MOD_0FAE_REG_0,
903 MOD_0FAE_REG_1,
904 MOD_0FAE_REG_2,
905 MOD_0FAE_REG_3,
906 MOD_0FAE_REG_4,
907 MOD_0FAE_REG_5,
908 MOD_0FAE_REG_6,
909 MOD_0FAE_REG_7,
910 MOD_0FB2,
911 MOD_0FB4,
912 MOD_0FB5,
913 MOD_0FC3,
914 MOD_0FC7_REG_3,
915 MOD_0FC7_REG_4,
916 MOD_0FC7_REG_5,
917 MOD_0FC7_REG_6,
918 MOD_0FC7_REG_7,
919 MOD_0FD7,
920 MOD_0FE7_PREFIX_2,
921 MOD_0FF0_PREFIX_3,
922 MOD_0F382A,
923 MOD_0F38DC_PREFIX_1,
924 MOD_0F38DD_PREFIX_1,
925 MOD_0F38DE_PREFIX_1,
926 MOD_0F38DF_PREFIX_1,
927 MOD_0F38F5,
928 MOD_0F38F6_PREFIX_0,
929 MOD_0F38F8_PREFIX_1,
930 MOD_0F38F8_PREFIX_2,
931 MOD_0F38F8_PREFIX_3,
932 MOD_0F38F9,
933 MOD_0F38FA_PREFIX_1,
934 MOD_0F38FB_PREFIX_1,
935 MOD_0F3A0F_PREFIX_1,
936
937 MOD_VEX_0F12_PREFIX_0,
938 MOD_VEX_0F12_PREFIX_2,
939 MOD_VEX_0F13,
940 MOD_VEX_0F16_PREFIX_0,
941 MOD_VEX_0F16_PREFIX_2,
942 MOD_VEX_0F17,
943 MOD_VEX_0F2B,
944 MOD_VEX_0F41_L_1,
945 MOD_VEX_0F42_L_1,
946 MOD_VEX_0F44_L_0,
947 MOD_VEX_0F45_L_1,
948 MOD_VEX_0F46_L_1,
949 MOD_VEX_0F47_L_1,
950 MOD_VEX_0F4A_L_1,
951 MOD_VEX_0F4B_L_1,
952 MOD_VEX_0F50,
953 MOD_VEX_0F71,
954 MOD_VEX_0F72,
955 MOD_VEX_0F73,
956 MOD_VEX_0F91_L_0,
957 MOD_VEX_0F92_L_0,
958 MOD_VEX_0F93_L_0,
959 MOD_VEX_0F98_L_0,
960 MOD_VEX_0F99_L_0,
961 MOD_VEX_0FAE_REG_2,
962 MOD_VEX_0FAE_REG_3,
963 MOD_VEX_0FD7,
964 MOD_VEX_0FE7,
965 MOD_VEX_0FF0_PREFIX_3,
966 MOD_VEX_0F381A,
967 MOD_VEX_0F382A,
968 MOD_VEX_0F382C,
969 MOD_VEX_0F382D,
970 MOD_VEX_0F382E,
971 MOD_VEX_0F382F,
972 MOD_VEX_0F3849_X86_64_P_0_W_0,
973 MOD_VEX_0F3849_X86_64_P_2_W_0,
974 MOD_VEX_0F3849_X86_64_P_3_W_0,
975 MOD_VEX_0F384B_X86_64_P_1_W_0,
976 MOD_VEX_0F384B_X86_64_P_2_W_0,
977 MOD_VEX_0F384B_X86_64_P_3_W_0,
978 MOD_VEX_0F385A,
979 MOD_VEX_0F385C_X86_64_P_1_W_0,
980 MOD_VEX_0F385C_X86_64_P_3_W_0,
981 MOD_VEX_0F385E_X86_64_P_0_W_0,
982 MOD_VEX_0F385E_X86_64_P_1_W_0,
983 MOD_VEX_0F385E_X86_64_P_2_W_0,
984 MOD_VEX_0F385E_X86_64_P_3_W_0,
985 MOD_VEX_0F386C_X86_64_W_0,
986 MOD_VEX_0F388C,
987 MOD_VEX_0F388E,
988 MOD_VEX_0F3A30_L_0,
989 MOD_VEX_0F3A31_L_0,
990 MOD_VEX_0F3A32_L_0,
991 MOD_VEX_0F3A33_L_0,
992
993 MOD_XOP_09_12,
994
995 MOD_EVEX_0F381A,
996 MOD_EVEX_0F381B,
997 MOD_EVEX_0F3828_P_1,
998 MOD_EVEX_0F382A_P_1_W_1,
999 MOD_EVEX_0F3838_P_1,
1000 MOD_EVEX_0F383A_P_1_W_0,
1001 MOD_EVEX_0F385A,
1002 MOD_EVEX_0F385B,
1003 MOD_EVEX_0F387A_W_0,
1004 MOD_EVEX_0F387B_W_0,
1005 MOD_EVEX_0F387C,
1006 MOD_EVEX_0F38C6,
1007 MOD_EVEX_0F38C7,
1008 };
1009
1010 enum
1011 {
1012 RM_C6_REG_7 = 0,
1013 RM_C7_REG_7,
1014 RM_0F01_REG_0,
1015 RM_0F01_REG_1,
1016 RM_0F01_REG_2,
1017 RM_0F01_REG_3,
1018 RM_0F01_REG_5_MOD_3,
1019 RM_0F01_REG_7_MOD_3,
1020 RM_0F1E_P_1_MOD_3_REG_7,
1021 RM_0FAE_REG_6_MOD_3_P_0,
1022 RM_0FAE_REG_7_MOD_3,
1023 RM_0F3A0F_P_1_MOD_3_REG_0,
1024
1025 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
1026 };
1027
1028 enum
1029 {
1030 PREFIX_90 = 0,
1031 PREFIX_0F01_REG_0_MOD_3_RM_6,
1032 PREFIX_0F01_REG_1_RM_4,
1033 PREFIX_0F01_REG_1_RM_5,
1034 PREFIX_0F01_REG_1_RM_6,
1035 PREFIX_0F01_REG_1_RM_7,
1036 PREFIX_0F01_REG_3_RM_1,
1037 PREFIX_0F01_REG_5_MOD_0,
1038 PREFIX_0F01_REG_5_MOD_3_RM_0,
1039 PREFIX_0F01_REG_5_MOD_3_RM_1,
1040 PREFIX_0F01_REG_5_MOD_3_RM_2,
1041 PREFIX_0F01_REG_5_MOD_3_RM_4,
1042 PREFIX_0F01_REG_5_MOD_3_RM_5,
1043 PREFIX_0F01_REG_5_MOD_3_RM_6,
1044 PREFIX_0F01_REG_5_MOD_3_RM_7,
1045 PREFIX_0F01_REG_7_MOD_3_RM_2,
1046 PREFIX_0F01_REG_7_MOD_3_RM_5,
1047 PREFIX_0F01_REG_7_MOD_3_RM_6,
1048 PREFIX_0F01_REG_7_MOD_3_RM_7,
1049 PREFIX_0F09,
1050 PREFIX_0F10,
1051 PREFIX_0F11,
1052 PREFIX_0F12,
1053 PREFIX_0F16,
1054 PREFIX_0F18_REG_6_MOD_0_X86_64,
1055 PREFIX_0F18_REG_7_MOD_0_X86_64,
1056 PREFIX_0F1A,
1057 PREFIX_0F1B,
1058 PREFIX_0F1C,
1059 PREFIX_0F1E,
1060 PREFIX_0F2A,
1061 PREFIX_0F2B,
1062 PREFIX_0F2C,
1063 PREFIX_0F2D,
1064 PREFIX_0F2E,
1065 PREFIX_0F2F,
1066 PREFIX_0F51,
1067 PREFIX_0F52,
1068 PREFIX_0F53,
1069 PREFIX_0F58,
1070 PREFIX_0F59,
1071 PREFIX_0F5A,
1072 PREFIX_0F5B,
1073 PREFIX_0F5C,
1074 PREFIX_0F5D,
1075 PREFIX_0F5E,
1076 PREFIX_0F5F,
1077 PREFIX_0F60,
1078 PREFIX_0F61,
1079 PREFIX_0F62,
1080 PREFIX_0F6F,
1081 PREFIX_0F70,
1082 PREFIX_0F78,
1083 PREFIX_0F79,
1084 PREFIX_0F7C,
1085 PREFIX_0F7D,
1086 PREFIX_0F7E,
1087 PREFIX_0F7F,
1088 PREFIX_0FAE_REG_0_MOD_3,
1089 PREFIX_0FAE_REG_1_MOD_3,
1090 PREFIX_0FAE_REG_2_MOD_3,
1091 PREFIX_0FAE_REG_3_MOD_3,
1092 PREFIX_0FAE_REG_4_MOD_0,
1093 PREFIX_0FAE_REG_4_MOD_3,
1094 PREFIX_0FAE_REG_5_MOD_3,
1095 PREFIX_0FAE_REG_6_MOD_0,
1096 PREFIX_0FAE_REG_6_MOD_3,
1097 PREFIX_0FAE_REG_7_MOD_0,
1098 PREFIX_0FB8,
1099 PREFIX_0FBC,
1100 PREFIX_0FBD,
1101 PREFIX_0FC2,
1102 PREFIX_0FC7_REG_6_MOD_0,
1103 PREFIX_0FC7_REG_6_MOD_3,
1104 PREFIX_0FC7_REG_7_MOD_3,
1105 PREFIX_0FD0,
1106 PREFIX_0FD6,
1107 PREFIX_0FE6,
1108 PREFIX_0FE7,
1109 PREFIX_0FF0,
1110 PREFIX_0FF7,
1111 PREFIX_0F38D8,
1112 PREFIX_0F38DC,
1113 PREFIX_0F38DD,
1114 PREFIX_0F38DE,
1115 PREFIX_0F38DF,
1116 PREFIX_0F38F0,
1117 PREFIX_0F38F1,
1118 PREFIX_0F38F6,
1119 PREFIX_0F38F8,
1120 PREFIX_0F38FA,
1121 PREFIX_0F38FB,
1122 PREFIX_0F38FC,
1123 PREFIX_0F3A0F,
1124 PREFIX_VEX_0F10,
1125 PREFIX_VEX_0F11,
1126 PREFIX_VEX_0F12,
1127 PREFIX_VEX_0F16,
1128 PREFIX_VEX_0F2A,
1129 PREFIX_VEX_0F2C,
1130 PREFIX_VEX_0F2D,
1131 PREFIX_VEX_0F2E,
1132 PREFIX_VEX_0F2F,
1133 PREFIX_VEX_0F41_L_1_M_1_W_0,
1134 PREFIX_VEX_0F41_L_1_M_1_W_1,
1135 PREFIX_VEX_0F42_L_1_M_1_W_0,
1136 PREFIX_VEX_0F42_L_1_M_1_W_1,
1137 PREFIX_VEX_0F44_L_0_M_1_W_0,
1138 PREFIX_VEX_0F44_L_0_M_1_W_1,
1139 PREFIX_VEX_0F45_L_1_M_1_W_0,
1140 PREFIX_VEX_0F45_L_1_M_1_W_1,
1141 PREFIX_VEX_0F46_L_1_M_1_W_0,
1142 PREFIX_VEX_0F46_L_1_M_1_W_1,
1143 PREFIX_VEX_0F47_L_1_M_1_W_0,
1144 PREFIX_VEX_0F47_L_1_M_1_W_1,
1145 PREFIX_VEX_0F4A_L_1_M_1_W_0,
1146 PREFIX_VEX_0F4A_L_1_M_1_W_1,
1147 PREFIX_VEX_0F4B_L_1_M_1_W_0,
1148 PREFIX_VEX_0F4B_L_1_M_1_W_1,
1149 PREFIX_VEX_0F51,
1150 PREFIX_VEX_0F52,
1151 PREFIX_VEX_0F53,
1152 PREFIX_VEX_0F58,
1153 PREFIX_VEX_0F59,
1154 PREFIX_VEX_0F5A,
1155 PREFIX_VEX_0F5B,
1156 PREFIX_VEX_0F5C,
1157 PREFIX_VEX_0F5D,
1158 PREFIX_VEX_0F5E,
1159 PREFIX_VEX_0F5F,
1160 PREFIX_VEX_0F6F,
1161 PREFIX_VEX_0F70,
1162 PREFIX_VEX_0F7C,
1163 PREFIX_VEX_0F7D,
1164 PREFIX_VEX_0F7E,
1165 PREFIX_VEX_0F7F,
1166 PREFIX_VEX_0F90_L_0_W_0,
1167 PREFIX_VEX_0F90_L_0_W_1,
1168 PREFIX_VEX_0F91_L_0_M_0_W_0,
1169 PREFIX_VEX_0F91_L_0_M_0_W_1,
1170 PREFIX_VEX_0F92_L_0_M_1_W_0,
1171 PREFIX_VEX_0F92_L_0_M_1_W_1,
1172 PREFIX_VEX_0F93_L_0_M_1_W_0,
1173 PREFIX_VEX_0F93_L_0_M_1_W_1,
1174 PREFIX_VEX_0F98_L_0_M_1_W_0,
1175 PREFIX_VEX_0F98_L_0_M_1_W_1,
1176 PREFIX_VEX_0F99_L_0_M_1_W_0,
1177 PREFIX_VEX_0F99_L_0_M_1_W_1,
1178 PREFIX_VEX_0FC2,
1179 PREFIX_VEX_0FD0,
1180 PREFIX_VEX_0FE6,
1181 PREFIX_VEX_0FF0,
1182 PREFIX_VEX_0F3849_X86_64,
1183 PREFIX_VEX_0F384B_X86_64,
1184 PREFIX_VEX_0F3850_W_0,
1185 PREFIX_VEX_0F3851_W_0,
1186 PREFIX_VEX_0F385C_X86_64,
1187 PREFIX_VEX_0F385E_X86_64,
1188 PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0,
1189 PREFIX_VEX_0F3872,
1190 PREFIX_VEX_0F38B0_W_0,
1191 PREFIX_VEX_0F38B1_W_0,
1192 PREFIX_VEX_0F38F5_L_0,
1193 PREFIX_VEX_0F38F6_L_0,
1194 PREFIX_VEX_0F38F7_L_0,
1195 PREFIX_VEX_0F3AF0_L_0,
1196
1197 PREFIX_EVEX_0F5B,
1198 PREFIX_EVEX_0F6F,
1199 PREFIX_EVEX_0F70,
1200 PREFIX_EVEX_0F78,
1201 PREFIX_EVEX_0F79,
1202 PREFIX_EVEX_0F7A,
1203 PREFIX_EVEX_0F7B,
1204 PREFIX_EVEX_0F7E,
1205 PREFIX_EVEX_0F7F,
1206 PREFIX_EVEX_0FC2,
1207 PREFIX_EVEX_0FE6,
1208 PREFIX_EVEX_0F3810,
1209 PREFIX_EVEX_0F3811,
1210 PREFIX_EVEX_0F3812,
1211 PREFIX_EVEX_0F3813,
1212 PREFIX_EVEX_0F3814,
1213 PREFIX_EVEX_0F3815,
1214 PREFIX_EVEX_0F3820,
1215 PREFIX_EVEX_0F3821,
1216 PREFIX_EVEX_0F3822,
1217 PREFIX_EVEX_0F3823,
1218 PREFIX_EVEX_0F3824,
1219 PREFIX_EVEX_0F3825,
1220 PREFIX_EVEX_0F3826,
1221 PREFIX_EVEX_0F3827,
1222 PREFIX_EVEX_0F3828,
1223 PREFIX_EVEX_0F3829,
1224 PREFIX_EVEX_0F382A,
1225 PREFIX_EVEX_0F3830,
1226 PREFIX_EVEX_0F3831,
1227 PREFIX_EVEX_0F3832,
1228 PREFIX_EVEX_0F3833,
1229 PREFIX_EVEX_0F3834,
1230 PREFIX_EVEX_0F3835,
1231 PREFIX_EVEX_0F3838,
1232 PREFIX_EVEX_0F3839,
1233 PREFIX_EVEX_0F383A,
1234 PREFIX_EVEX_0F3852,
1235 PREFIX_EVEX_0F3853,
1236 PREFIX_EVEX_0F3868,
1237 PREFIX_EVEX_0F3872,
1238 PREFIX_EVEX_0F389A,
1239 PREFIX_EVEX_0F389B,
1240 PREFIX_EVEX_0F38AA,
1241 PREFIX_EVEX_0F38AB,
1242
1243 PREFIX_EVEX_0F3A08,
1244 PREFIX_EVEX_0F3A0A,
1245 PREFIX_EVEX_0F3A26,
1246 PREFIX_EVEX_0F3A27,
1247 PREFIX_EVEX_0F3A56,
1248 PREFIX_EVEX_0F3A57,
1249 PREFIX_EVEX_0F3A66,
1250 PREFIX_EVEX_0F3A67,
1251 PREFIX_EVEX_0F3AC2,
1252
1253 PREFIX_EVEX_MAP5_10,
1254 PREFIX_EVEX_MAP5_11,
1255 PREFIX_EVEX_MAP5_1D,
1256 PREFIX_EVEX_MAP5_2A,
1257 PREFIX_EVEX_MAP5_2C,
1258 PREFIX_EVEX_MAP5_2D,
1259 PREFIX_EVEX_MAP5_2E,
1260 PREFIX_EVEX_MAP5_2F,
1261 PREFIX_EVEX_MAP5_51,
1262 PREFIX_EVEX_MAP5_58,
1263 PREFIX_EVEX_MAP5_59,
1264 PREFIX_EVEX_MAP5_5A,
1265 PREFIX_EVEX_MAP5_5B,
1266 PREFIX_EVEX_MAP5_5C,
1267 PREFIX_EVEX_MAP5_5D,
1268 PREFIX_EVEX_MAP5_5E,
1269 PREFIX_EVEX_MAP5_5F,
1270 PREFIX_EVEX_MAP5_78,
1271 PREFIX_EVEX_MAP5_79,
1272 PREFIX_EVEX_MAP5_7A,
1273 PREFIX_EVEX_MAP5_7B,
1274 PREFIX_EVEX_MAP5_7C,
1275 PREFIX_EVEX_MAP5_7D,
1276
1277 PREFIX_EVEX_MAP6_13,
1278 PREFIX_EVEX_MAP6_56,
1279 PREFIX_EVEX_MAP6_57,
1280 PREFIX_EVEX_MAP6_D6,
1281 PREFIX_EVEX_MAP6_D7,
1282 };
1283
1284 enum
1285 {
1286 X86_64_06 = 0,
1287 X86_64_07,
1288 X86_64_0E,
1289 X86_64_16,
1290 X86_64_17,
1291 X86_64_1E,
1292 X86_64_1F,
1293 X86_64_27,
1294 X86_64_2F,
1295 X86_64_37,
1296 X86_64_3F,
1297 X86_64_60,
1298 X86_64_61,
1299 X86_64_62,
1300 X86_64_63,
1301 X86_64_6D,
1302 X86_64_6F,
1303 X86_64_82,
1304 X86_64_9A,
1305 X86_64_C2,
1306 X86_64_C3,
1307 X86_64_C4,
1308 X86_64_C5,
1309 X86_64_CE,
1310 X86_64_D4,
1311 X86_64_D5,
1312 X86_64_E8,
1313 X86_64_E9,
1314 X86_64_EA,
1315 X86_64_0F01_REG_0,
1316 X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1317 X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1318 X86_64_0F01_REG_1,
1319 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1320 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1321 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1322 X86_64_0F01_REG_2,
1323 X86_64_0F01_REG_3,
1324 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1325 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1326 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1327 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1328 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1329 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1330 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1331 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1332 X86_64_0F18_REG_6_MOD_0,
1333 X86_64_0F18_REG_7_MOD_0,
1334 X86_64_0F24,
1335 X86_64_0F26,
1336 X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1337
1338 X86_64_VEX_0F3849,
1339 X86_64_VEX_0F384B,
1340 X86_64_VEX_0F385C,
1341 X86_64_VEX_0F385E,
1342 X86_64_VEX_0F386C,
1343 X86_64_VEX_0F38E0,
1344 X86_64_VEX_0F38E1,
1345 X86_64_VEX_0F38E2,
1346 X86_64_VEX_0F38E3,
1347 X86_64_VEX_0F38E4,
1348 X86_64_VEX_0F38E5,
1349 X86_64_VEX_0F38E6,
1350 X86_64_VEX_0F38E7,
1351 X86_64_VEX_0F38E8,
1352 X86_64_VEX_0F38E9,
1353 X86_64_VEX_0F38EA,
1354 X86_64_VEX_0F38EB,
1355 X86_64_VEX_0F38EC,
1356 X86_64_VEX_0F38ED,
1357 X86_64_VEX_0F38EE,
1358 X86_64_VEX_0F38EF,
1359 };
1360
1361 enum
1362 {
1363 THREE_BYTE_0F38 = 0,
1364 THREE_BYTE_0F3A
1365 };
1366
1367 enum
1368 {
1369 XOP_08 = 0,
1370 XOP_09,
1371 XOP_0A
1372 };
1373
1374 enum
1375 {
1376 VEX_0F = 0,
1377 VEX_0F38,
1378 VEX_0F3A
1379 };
1380
1381 enum
1382 {
1383 EVEX_0F = 0,
1384 EVEX_0F38,
1385 EVEX_0F3A,
1386 EVEX_MAP5,
1387 EVEX_MAP6,
1388 };
1389
1390 enum
1391 {
1392 VEX_LEN_0F12_P_0_M_0 = 0,
1393 VEX_LEN_0F12_P_0_M_1,
1394 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1395 VEX_LEN_0F13_M_0,
1396 VEX_LEN_0F16_P_0_M_0,
1397 VEX_LEN_0F16_P_0_M_1,
1398 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1399 VEX_LEN_0F17_M_0,
1400 VEX_LEN_0F41,
1401 VEX_LEN_0F42,
1402 VEX_LEN_0F44,
1403 VEX_LEN_0F45,
1404 VEX_LEN_0F46,
1405 VEX_LEN_0F47,
1406 VEX_LEN_0F4A,
1407 VEX_LEN_0F4B,
1408 VEX_LEN_0F6E,
1409 VEX_LEN_0F77,
1410 VEX_LEN_0F7E_P_1,
1411 VEX_LEN_0F7E_P_2,
1412 VEX_LEN_0F90,
1413 VEX_LEN_0F91,
1414 VEX_LEN_0F92,
1415 VEX_LEN_0F93,
1416 VEX_LEN_0F98,
1417 VEX_LEN_0F99,
1418 VEX_LEN_0FAE_R_2_M_0,
1419 VEX_LEN_0FAE_R_3_M_0,
1420 VEX_LEN_0FC4,
1421 VEX_LEN_0FC5,
1422 VEX_LEN_0FD6,
1423 VEX_LEN_0FF7,
1424 VEX_LEN_0F3816,
1425 VEX_LEN_0F3819,
1426 VEX_LEN_0F381A_M_0,
1427 VEX_LEN_0F3836,
1428 VEX_LEN_0F3841,
1429 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1430 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1431 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1432 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1433 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1434 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1435 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1436 VEX_LEN_0F385A_M_0,
1437 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1438 VEX_LEN_0F385C_X86_64_P_3_W_0_M_0,
1439 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1440 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1441 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1442 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1443 VEX_LEN_0F386C_X86_64_W_0_M_1,
1444 VEX_LEN_0F38DB,
1445 VEX_LEN_0F38F2,
1446 VEX_LEN_0F38F3,
1447 VEX_LEN_0F38F5,
1448 VEX_LEN_0F38F6,
1449 VEX_LEN_0F38F7,
1450 VEX_LEN_0F3A00,
1451 VEX_LEN_0F3A01,
1452 VEX_LEN_0F3A06,
1453 VEX_LEN_0F3A14,
1454 VEX_LEN_0F3A15,
1455 VEX_LEN_0F3A16,
1456 VEX_LEN_0F3A17,
1457 VEX_LEN_0F3A18,
1458 VEX_LEN_0F3A19,
1459 VEX_LEN_0F3A20,
1460 VEX_LEN_0F3A21,
1461 VEX_LEN_0F3A22,
1462 VEX_LEN_0F3A30,
1463 VEX_LEN_0F3A31,
1464 VEX_LEN_0F3A32,
1465 VEX_LEN_0F3A33,
1466 VEX_LEN_0F3A38,
1467 VEX_LEN_0F3A39,
1468 VEX_LEN_0F3A41,
1469 VEX_LEN_0F3A46,
1470 VEX_LEN_0F3A60,
1471 VEX_LEN_0F3A61,
1472 VEX_LEN_0F3A62,
1473 VEX_LEN_0F3A63,
1474 VEX_LEN_0F3ADF,
1475 VEX_LEN_0F3AF0,
1476 VEX_LEN_0FXOP_08_85,
1477 VEX_LEN_0FXOP_08_86,
1478 VEX_LEN_0FXOP_08_87,
1479 VEX_LEN_0FXOP_08_8E,
1480 VEX_LEN_0FXOP_08_8F,
1481 VEX_LEN_0FXOP_08_95,
1482 VEX_LEN_0FXOP_08_96,
1483 VEX_LEN_0FXOP_08_97,
1484 VEX_LEN_0FXOP_08_9E,
1485 VEX_LEN_0FXOP_08_9F,
1486 VEX_LEN_0FXOP_08_A3,
1487 VEX_LEN_0FXOP_08_A6,
1488 VEX_LEN_0FXOP_08_B6,
1489 VEX_LEN_0FXOP_08_C0,
1490 VEX_LEN_0FXOP_08_C1,
1491 VEX_LEN_0FXOP_08_C2,
1492 VEX_LEN_0FXOP_08_C3,
1493 VEX_LEN_0FXOP_08_CC,
1494 VEX_LEN_0FXOP_08_CD,
1495 VEX_LEN_0FXOP_08_CE,
1496 VEX_LEN_0FXOP_08_CF,
1497 VEX_LEN_0FXOP_08_EC,
1498 VEX_LEN_0FXOP_08_ED,
1499 VEX_LEN_0FXOP_08_EE,
1500 VEX_LEN_0FXOP_08_EF,
1501 VEX_LEN_0FXOP_09_01,
1502 VEX_LEN_0FXOP_09_02,
1503 VEX_LEN_0FXOP_09_12_M_1,
1504 VEX_LEN_0FXOP_09_82_W_0,
1505 VEX_LEN_0FXOP_09_83_W_0,
1506 VEX_LEN_0FXOP_09_90,
1507 VEX_LEN_0FXOP_09_91,
1508 VEX_LEN_0FXOP_09_92,
1509 VEX_LEN_0FXOP_09_93,
1510 VEX_LEN_0FXOP_09_94,
1511 VEX_LEN_0FXOP_09_95,
1512 VEX_LEN_0FXOP_09_96,
1513 VEX_LEN_0FXOP_09_97,
1514 VEX_LEN_0FXOP_09_98,
1515 VEX_LEN_0FXOP_09_99,
1516 VEX_LEN_0FXOP_09_9A,
1517 VEX_LEN_0FXOP_09_9B,
1518 VEX_LEN_0FXOP_09_C1,
1519 VEX_LEN_0FXOP_09_C2,
1520 VEX_LEN_0FXOP_09_C3,
1521 VEX_LEN_0FXOP_09_C6,
1522 VEX_LEN_0FXOP_09_C7,
1523 VEX_LEN_0FXOP_09_CB,
1524 VEX_LEN_0FXOP_09_D1,
1525 VEX_LEN_0FXOP_09_D2,
1526 VEX_LEN_0FXOP_09_D3,
1527 VEX_LEN_0FXOP_09_D6,
1528 VEX_LEN_0FXOP_09_D7,
1529 VEX_LEN_0FXOP_09_DB,
1530 VEX_LEN_0FXOP_09_E1,
1531 VEX_LEN_0FXOP_09_E2,
1532 VEX_LEN_0FXOP_09_E3,
1533 VEX_LEN_0FXOP_0A_12,
1534 };
1535
1536 enum
1537 {
1538 EVEX_LEN_0F3816 = 0,
1539 EVEX_LEN_0F3819,
1540 EVEX_LEN_0F381A_M_0,
1541 EVEX_LEN_0F381B_M_0,
1542 EVEX_LEN_0F3836,
1543 EVEX_LEN_0F385A_M_0,
1544 EVEX_LEN_0F385B_M_0,
1545 EVEX_LEN_0F38C6_M_0,
1546 EVEX_LEN_0F38C7_M_0,
1547 EVEX_LEN_0F3A00,
1548 EVEX_LEN_0F3A01,
1549 EVEX_LEN_0F3A18,
1550 EVEX_LEN_0F3A19,
1551 EVEX_LEN_0F3A1A,
1552 EVEX_LEN_0F3A1B,
1553 EVEX_LEN_0F3A23,
1554 EVEX_LEN_0F3A38,
1555 EVEX_LEN_0F3A39,
1556 EVEX_LEN_0F3A3A,
1557 EVEX_LEN_0F3A3B,
1558 EVEX_LEN_0F3A43
1559 };
1560
1561 enum
1562 {
1563 VEX_W_0F41_L_1_M_1 = 0,
1564 VEX_W_0F42_L_1_M_1,
1565 VEX_W_0F44_L_0_M_1,
1566 VEX_W_0F45_L_1_M_1,
1567 VEX_W_0F46_L_1_M_1,
1568 VEX_W_0F47_L_1_M_1,
1569 VEX_W_0F4A_L_1_M_1,
1570 VEX_W_0F4B_L_1_M_1,
1571 VEX_W_0F90_L_0,
1572 VEX_W_0F91_L_0_M_0,
1573 VEX_W_0F92_L_0_M_1,
1574 VEX_W_0F93_L_0_M_1,
1575 VEX_W_0F98_L_0_M_1,
1576 VEX_W_0F99_L_0_M_1,
1577 VEX_W_0F380C,
1578 VEX_W_0F380D,
1579 VEX_W_0F380E,
1580 VEX_W_0F380F,
1581 VEX_W_0F3813,
1582 VEX_W_0F3816_L_1,
1583 VEX_W_0F3818,
1584 VEX_W_0F3819_L_1,
1585 VEX_W_0F381A_M_0_L_1,
1586 VEX_W_0F382C_M_0,
1587 VEX_W_0F382D_M_0,
1588 VEX_W_0F382E_M_0,
1589 VEX_W_0F382F_M_0,
1590 VEX_W_0F3836,
1591 VEX_W_0F3846,
1592 VEX_W_0F3849_X86_64_P_0,
1593 VEX_W_0F3849_X86_64_P_2,
1594 VEX_W_0F3849_X86_64_P_3,
1595 VEX_W_0F384B_X86_64_P_1,
1596 VEX_W_0F384B_X86_64_P_2,
1597 VEX_W_0F384B_X86_64_P_3,
1598 VEX_W_0F3850,
1599 VEX_W_0F3851,
1600 VEX_W_0F3852,
1601 VEX_W_0F3853,
1602 VEX_W_0F3858,
1603 VEX_W_0F3859,
1604 VEX_W_0F385A_M_0_L_0,
1605 VEX_W_0F385C_X86_64_P_1,
1606 VEX_W_0F385C_X86_64_P_3,
1607 VEX_W_0F385E_X86_64_P_0,
1608 VEX_W_0F385E_X86_64_P_1,
1609 VEX_W_0F385E_X86_64_P_2,
1610 VEX_W_0F385E_X86_64_P_3,
1611 VEX_W_0F386C_X86_64,
1612 VEX_W_0F3872_P_1,
1613 VEX_W_0F3878,
1614 VEX_W_0F3879,
1615 VEX_W_0F38B0,
1616 VEX_W_0F38B1,
1617 VEX_W_0F38B4,
1618 VEX_W_0F38B5,
1619 VEX_W_0F38CF,
1620 VEX_W_0F3A00_L_1,
1621 VEX_W_0F3A01_L_1,
1622 VEX_W_0F3A02,
1623 VEX_W_0F3A04,
1624 VEX_W_0F3A05,
1625 VEX_W_0F3A06_L_1,
1626 VEX_W_0F3A18_L_1,
1627 VEX_W_0F3A19_L_1,
1628 VEX_W_0F3A1D,
1629 VEX_W_0F3A38_L_1,
1630 VEX_W_0F3A39_L_1,
1631 VEX_W_0F3A46_L_1,
1632 VEX_W_0F3A4A,
1633 VEX_W_0F3A4B,
1634 VEX_W_0F3A4C,
1635 VEX_W_0F3ACE,
1636 VEX_W_0F3ACF,
1637
1638 VEX_W_0FXOP_08_85_L_0,
1639 VEX_W_0FXOP_08_86_L_0,
1640 VEX_W_0FXOP_08_87_L_0,
1641 VEX_W_0FXOP_08_8E_L_0,
1642 VEX_W_0FXOP_08_8F_L_0,
1643 VEX_W_0FXOP_08_95_L_0,
1644 VEX_W_0FXOP_08_96_L_0,
1645 VEX_W_0FXOP_08_97_L_0,
1646 VEX_W_0FXOP_08_9E_L_0,
1647 VEX_W_0FXOP_08_9F_L_0,
1648 VEX_W_0FXOP_08_A6_L_0,
1649 VEX_W_0FXOP_08_B6_L_0,
1650 VEX_W_0FXOP_08_C0_L_0,
1651 VEX_W_0FXOP_08_C1_L_0,
1652 VEX_W_0FXOP_08_C2_L_0,
1653 VEX_W_0FXOP_08_C3_L_0,
1654 VEX_W_0FXOP_08_CC_L_0,
1655 VEX_W_0FXOP_08_CD_L_0,
1656 VEX_W_0FXOP_08_CE_L_0,
1657 VEX_W_0FXOP_08_CF_L_0,
1658 VEX_W_0FXOP_08_EC_L_0,
1659 VEX_W_0FXOP_08_ED_L_0,
1660 VEX_W_0FXOP_08_EE_L_0,
1661 VEX_W_0FXOP_08_EF_L_0,
1662
1663 VEX_W_0FXOP_09_80,
1664 VEX_W_0FXOP_09_81,
1665 VEX_W_0FXOP_09_82,
1666 VEX_W_0FXOP_09_83,
1667 VEX_W_0FXOP_09_C1_L_0,
1668 VEX_W_0FXOP_09_C2_L_0,
1669 VEX_W_0FXOP_09_C3_L_0,
1670 VEX_W_0FXOP_09_C6_L_0,
1671 VEX_W_0FXOP_09_C7_L_0,
1672 VEX_W_0FXOP_09_CB_L_0,
1673 VEX_W_0FXOP_09_D1_L_0,
1674 VEX_W_0FXOP_09_D2_L_0,
1675 VEX_W_0FXOP_09_D3_L_0,
1676 VEX_W_0FXOP_09_D6_L_0,
1677 VEX_W_0FXOP_09_D7_L_0,
1678 VEX_W_0FXOP_09_DB_L_0,
1679 VEX_W_0FXOP_09_E1_L_0,
1680 VEX_W_0FXOP_09_E2_L_0,
1681 VEX_W_0FXOP_09_E3_L_0,
1682
1683 EVEX_W_0F5B_P_0,
1684 EVEX_W_0F62,
1685 EVEX_W_0F66,
1686 EVEX_W_0F6A,
1687 EVEX_W_0F6B,
1688 EVEX_W_0F6C,
1689 EVEX_W_0F6D,
1690 EVEX_W_0F6F_P_1,
1691 EVEX_W_0F6F_P_2,
1692 EVEX_W_0F6F_P_3,
1693 EVEX_W_0F70_P_2,
1694 EVEX_W_0F72_R_2,
1695 EVEX_W_0F72_R_6,
1696 EVEX_W_0F73_R_2,
1697 EVEX_W_0F73_R_6,
1698 EVEX_W_0F76,
1699 EVEX_W_0F78_P_0,
1700 EVEX_W_0F78_P_2,
1701 EVEX_W_0F79_P_0,
1702 EVEX_W_0F79_P_2,
1703 EVEX_W_0F7A_P_1,
1704 EVEX_W_0F7A_P_2,
1705 EVEX_W_0F7A_P_3,
1706 EVEX_W_0F7B_P_2,
1707 EVEX_W_0F7E_P_1,
1708 EVEX_W_0F7F_P_1,
1709 EVEX_W_0F7F_P_2,
1710 EVEX_W_0F7F_P_3,
1711 EVEX_W_0FD2,
1712 EVEX_W_0FD3,
1713 EVEX_W_0FD4,
1714 EVEX_W_0FD6,
1715 EVEX_W_0FE6_P_1,
1716 EVEX_W_0FE7,
1717 EVEX_W_0FF2,
1718 EVEX_W_0FF3,
1719 EVEX_W_0FF4,
1720 EVEX_W_0FFA,
1721 EVEX_W_0FFB,
1722 EVEX_W_0FFE,
1723
1724 EVEX_W_0F3810_P_1,
1725 EVEX_W_0F3810_P_2,
1726 EVEX_W_0F3811_P_1,
1727 EVEX_W_0F3811_P_2,
1728 EVEX_W_0F3812_P_1,
1729 EVEX_W_0F3812_P_2,
1730 EVEX_W_0F3813_P_1,
1731 EVEX_W_0F3814_P_1,
1732 EVEX_W_0F3815_P_1,
1733 EVEX_W_0F3819_L_n,
1734 EVEX_W_0F381A_M_0_L_n,
1735 EVEX_W_0F381B_M_0_L_2,
1736 EVEX_W_0F381E,
1737 EVEX_W_0F381F,
1738 EVEX_W_0F3820_P_1,
1739 EVEX_W_0F3821_P_1,
1740 EVEX_W_0F3822_P_1,
1741 EVEX_W_0F3823_P_1,
1742 EVEX_W_0F3824_P_1,
1743 EVEX_W_0F3825_P_1,
1744 EVEX_W_0F3825_P_2,
1745 EVEX_W_0F3828_P_2,
1746 EVEX_W_0F3829_P_2,
1747 EVEX_W_0F382A_P_1,
1748 EVEX_W_0F382A_P_2,
1749 EVEX_W_0F382B,
1750 EVEX_W_0F3830_P_1,
1751 EVEX_W_0F3831_P_1,
1752 EVEX_W_0F3832_P_1,
1753 EVEX_W_0F3833_P_1,
1754 EVEX_W_0F3834_P_1,
1755 EVEX_W_0F3835_P_1,
1756 EVEX_W_0F3835_P_2,
1757 EVEX_W_0F3837,
1758 EVEX_W_0F383A_P_1,
1759 EVEX_W_0F3859,
1760 EVEX_W_0F385A_M_0_L_n,
1761 EVEX_W_0F385B_M_0_L_2,
1762 EVEX_W_0F3870,
1763 EVEX_W_0F3872_P_2,
1764 EVEX_W_0F387A,
1765 EVEX_W_0F387B,
1766 EVEX_W_0F3883,
1767
1768 EVEX_W_0F3A18_L_n,
1769 EVEX_W_0F3A19_L_n,
1770 EVEX_W_0F3A1A_L_2,
1771 EVEX_W_0F3A1B_L_2,
1772 EVEX_W_0F3A21,
1773 EVEX_W_0F3A23_L_n,
1774 EVEX_W_0F3A38_L_n,
1775 EVEX_W_0F3A39_L_n,
1776 EVEX_W_0F3A3A_L_2,
1777 EVEX_W_0F3A3B_L_2,
1778 EVEX_W_0F3A42,
1779 EVEX_W_0F3A43_L_n,
1780 EVEX_W_0F3A70,
1781 EVEX_W_0F3A72,
1782
1783 EVEX_W_MAP5_5B_P_0,
1784 EVEX_W_MAP5_7A_P_3,
1785 };
1786
1787 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1788
1789 struct dis386 {
1790 const char *name;
1791 struct
1792 {
1793 op_rtn rtn;
1794 int bytemode;
1795 } op[MAX_OPERANDS];
1796 unsigned int prefix_requirement;
1797 };
1798
1799 /* Upper case letters in the instruction names here are macros.
1800 'A' => print 'b' if no register operands or suffix_always is true
1801 'B' => print 'b' if suffix_always is true
1802 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1803 size prefix
1804 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1805 suffix_always is true
1806 'E' => print 'e' if 32-bit form of jcxz
1807 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1808 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1809 'H' => print ",pt" or ",pn" branch hint
1810 'I' unused.
1811 'J' unused.
1812 'K' => print 'd' or 'q' if rex prefix is present.
1813 'L' unused.
1814 'M' => print 'r' if intel_mnemonic is false.
1815 'N' => print 'n' if instruction has no wait "prefix"
1816 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1817 'P' => behave as 'T' except with register operand outside of suffix_always
1818 mode
1819 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1820 is true
1821 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1822 'S' => print 'w', 'l' or 'q' if suffix_always is true
1823 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1824 prefix or if suffix_always is true.
1825 'U' unused.
1826 'V' unused.
1827 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1828 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1829 'Y' unused.
1830 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1831 '!' => change condition from true to false or from false to true.
1832 '%' => add 1 upper case letter to the macro.
1833 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1834 prefix or suffix_always is true (lcall/ljmp).
1835 '@' => in 64bit mode for Intel64 ISA or if instruction
1836 has no operand sizing prefix, print 'q' if suffix_always is true or
1837 nothing otherwise; behave as 'P' in all other cases
1838
1839 2 upper case letter macros:
1840 "XY" => print 'x' or 'y' if suffix_always is true or no register
1841 operands and no broadcast.
1842 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1843 register operands and no broadcast.
1844 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1845 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1846 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1847 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1848 "XV" => print "{vex} " pseudo prefix
1849 "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1850 is used by an EVEX-encoded (AVX512VL) instruction.
1851 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1852 being false, or no operand at all in 64bit mode, or if suffix_always
1853 is true.
1854 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1855 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1856 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1857 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1858 "BW" => print 'b' or 'w' depending on the VEX.W bit
1859 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1860 an operand size prefix, or suffix_always is true. print
1861 'q' if rex prefix is present.
1862
1863 Many of the above letters print nothing in Intel mode. See "putop"
1864 for the details.
1865
1866 Braces '{' and '}', and vertical bars '|', indicate alternative
1867 mnemonic strings for AT&T and Intel. */
1868
1869 static const struct dis386 dis386[] = {
1870 /* 00 */
1871 { "addB", { Ebh1, Gb }, 0 },
1872 { "addS", { Evh1, Gv }, 0 },
1873 { "addB", { Gb, EbS }, 0 },
1874 { "addS", { Gv, EvS }, 0 },
1875 { "addB", { AL, Ib }, 0 },
1876 { "addS", { eAX, Iv }, 0 },
1877 { X86_64_TABLE (X86_64_06) },
1878 { X86_64_TABLE (X86_64_07) },
1879 /* 08 */
1880 { "orB", { Ebh1, Gb }, 0 },
1881 { "orS", { Evh1, Gv }, 0 },
1882 { "orB", { Gb, EbS }, 0 },
1883 { "orS", { Gv, EvS }, 0 },
1884 { "orB", { AL, Ib }, 0 },
1885 { "orS", { eAX, Iv }, 0 },
1886 { X86_64_TABLE (X86_64_0E) },
1887 { Bad_Opcode }, /* 0x0f extended opcode escape */
1888 /* 10 */
1889 { "adcB", { Ebh1, Gb }, 0 },
1890 { "adcS", { Evh1, Gv }, 0 },
1891 { "adcB", { Gb, EbS }, 0 },
1892 { "adcS", { Gv, EvS }, 0 },
1893 { "adcB", { AL, Ib }, 0 },
1894 { "adcS", { eAX, Iv }, 0 },
1895 { X86_64_TABLE (X86_64_16) },
1896 { X86_64_TABLE (X86_64_17) },
1897 /* 18 */
1898 { "sbbB", { Ebh1, Gb }, 0 },
1899 { "sbbS", { Evh1, Gv }, 0 },
1900 { "sbbB", { Gb, EbS }, 0 },
1901 { "sbbS", { Gv, EvS }, 0 },
1902 { "sbbB", { AL, Ib }, 0 },
1903 { "sbbS", { eAX, Iv }, 0 },
1904 { X86_64_TABLE (X86_64_1E) },
1905 { X86_64_TABLE (X86_64_1F) },
1906 /* 20 */
1907 { "andB", { Ebh1, Gb }, 0 },
1908 { "andS", { Evh1, Gv }, 0 },
1909 { "andB", { Gb, EbS }, 0 },
1910 { "andS", { Gv, EvS }, 0 },
1911 { "andB", { AL, Ib }, 0 },
1912 { "andS", { eAX, Iv }, 0 },
1913 { Bad_Opcode }, /* SEG ES prefix */
1914 { X86_64_TABLE (X86_64_27) },
1915 /* 28 */
1916 { "subB", { Ebh1, Gb }, 0 },
1917 { "subS", { Evh1, Gv }, 0 },
1918 { "subB", { Gb, EbS }, 0 },
1919 { "subS", { Gv, EvS }, 0 },
1920 { "subB", { AL, Ib }, 0 },
1921 { "subS", { eAX, Iv }, 0 },
1922 { Bad_Opcode }, /* SEG CS prefix */
1923 { X86_64_TABLE (X86_64_2F) },
1924 /* 30 */
1925 { "xorB", { Ebh1, Gb }, 0 },
1926 { "xorS", { Evh1, Gv }, 0 },
1927 { "xorB", { Gb, EbS }, 0 },
1928 { "xorS", { Gv, EvS }, 0 },
1929 { "xorB", { AL, Ib }, 0 },
1930 { "xorS", { eAX, Iv }, 0 },
1931 { Bad_Opcode }, /* SEG SS prefix */
1932 { X86_64_TABLE (X86_64_37) },
1933 /* 38 */
1934 { "cmpB", { Eb, Gb }, 0 },
1935 { "cmpS", { Ev, Gv }, 0 },
1936 { "cmpB", { Gb, EbS }, 0 },
1937 { "cmpS", { Gv, EvS }, 0 },
1938 { "cmpB", { AL, Ib }, 0 },
1939 { "cmpS", { eAX, Iv }, 0 },
1940 { Bad_Opcode }, /* SEG DS prefix */
1941 { X86_64_TABLE (X86_64_3F) },
1942 /* 40 */
1943 { "inc{S|}", { RMeAX }, 0 },
1944 { "inc{S|}", { RMeCX }, 0 },
1945 { "inc{S|}", { RMeDX }, 0 },
1946 { "inc{S|}", { RMeBX }, 0 },
1947 { "inc{S|}", { RMeSP }, 0 },
1948 { "inc{S|}", { RMeBP }, 0 },
1949 { "inc{S|}", { RMeSI }, 0 },
1950 { "inc{S|}", { RMeDI }, 0 },
1951 /* 48 */
1952 { "dec{S|}", { RMeAX }, 0 },
1953 { "dec{S|}", { RMeCX }, 0 },
1954 { "dec{S|}", { RMeDX }, 0 },
1955 { "dec{S|}", { RMeBX }, 0 },
1956 { "dec{S|}", { RMeSP }, 0 },
1957 { "dec{S|}", { RMeBP }, 0 },
1958 { "dec{S|}", { RMeSI }, 0 },
1959 { "dec{S|}", { RMeDI }, 0 },
1960 /* 50 */
1961 { "push{!P|}", { RMrAX }, 0 },
1962 { "push{!P|}", { RMrCX }, 0 },
1963 { "push{!P|}", { RMrDX }, 0 },
1964 { "push{!P|}", { RMrBX }, 0 },
1965 { "push{!P|}", { RMrSP }, 0 },
1966 { "push{!P|}", { RMrBP }, 0 },
1967 { "push{!P|}", { RMrSI }, 0 },
1968 { "push{!P|}", { RMrDI }, 0 },
1969 /* 58 */
1970 { "pop{!P|}", { RMrAX }, 0 },
1971 { "pop{!P|}", { RMrCX }, 0 },
1972 { "pop{!P|}", { RMrDX }, 0 },
1973 { "pop{!P|}", { RMrBX }, 0 },
1974 { "pop{!P|}", { RMrSP }, 0 },
1975 { "pop{!P|}", { RMrBP }, 0 },
1976 { "pop{!P|}", { RMrSI }, 0 },
1977 { "pop{!P|}", { RMrDI }, 0 },
1978 /* 60 */
1979 { X86_64_TABLE (X86_64_60) },
1980 { X86_64_TABLE (X86_64_61) },
1981 { X86_64_TABLE (X86_64_62) },
1982 { X86_64_TABLE (X86_64_63) },
1983 { Bad_Opcode }, /* seg fs */
1984 { Bad_Opcode }, /* seg gs */
1985 { Bad_Opcode }, /* op size prefix */
1986 { Bad_Opcode }, /* adr size prefix */
1987 /* 68 */
1988 { "pushP", { sIv }, 0 },
1989 { "imulS", { Gv, Ev, Iv }, 0 },
1990 { "pushP", { sIbT }, 0 },
1991 { "imulS", { Gv, Ev, sIb }, 0 },
1992 { "ins{b|}", { Ybr, indirDX }, 0 },
1993 { X86_64_TABLE (X86_64_6D) },
1994 { "outs{b|}", { indirDXr, Xb }, 0 },
1995 { X86_64_TABLE (X86_64_6F) },
1996 /* 70 */
1997 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1998 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1999 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2000 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2001 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2002 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2003 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2004 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2005 /* 78 */
2006 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2007 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2008 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2009 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2010 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2011 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2012 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2013 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2014 /* 80 */
2015 { REG_TABLE (REG_80) },
2016 { REG_TABLE (REG_81) },
2017 { X86_64_TABLE (X86_64_82) },
2018 { REG_TABLE (REG_83) },
2019 { "testB", { Eb, Gb }, 0 },
2020 { "testS", { Ev, Gv }, 0 },
2021 { "xchgB", { Ebh2, Gb }, 0 },
2022 { "xchgS", { Evh2, Gv }, 0 },
2023 /* 88 */
2024 { "movB", { Ebh3, Gb }, 0 },
2025 { "movS", { Evh3, Gv }, 0 },
2026 { "movB", { Gb, EbS }, 0 },
2027 { "movS", { Gv, EvS }, 0 },
2028 { "movD", { Sv, Sw }, 0 },
2029 { MOD_TABLE (MOD_8D) },
2030 { "movD", { Sw, Sv }, 0 },
2031 { REG_TABLE (REG_8F) },
2032 /* 90 */
2033 { PREFIX_TABLE (PREFIX_90) },
2034 { "xchgS", { RMeCX, eAX }, 0 },
2035 { "xchgS", { RMeDX, eAX }, 0 },
2036 { "xchgS", { RMeBX, eAX }, 0 },
2037 { "xchgS", { RMeSP, eAX }, 0 },
2038 { "xchgS", { RMeBP, eAX }, 0 },
2039 { "xchgS", { RMeSI, eAX }, 0 },
2040 { "xchgS", { RMeDI, eAX }, 0 },
2041 /* 98 */
2042 { "cW{t|}R", { XX }, 0 },
2043 { "cR{t|}O", { XX }, 0 },
2044 { X86_64_TABLE (X86_64_9A) },
2045 { Bad_Opcode }, /* fwait */
2046 { "pushfP", { XX }, 0 },
2047 { "popfP", { XX }, 0 },
2048 { "sahf", { XX }, 0 },
2049 { "lahf", { XX }, 0 },
2050 /* a0 */
2051 { "mov%LB", { AL, Ob }, 0 },
2052 { "mov%LS", { eAX, Ov }, 0 },
2053 { "mov%LB", { Ob, AL }, 0 },
2054 { "mov%LS", { Ov, eAX }, 0 },
2055 { "movs{b|}", { Ybr, Xb }, 0 },
2056 { "movs{R|}", { Yvr, Xv }, 0 },
2057 { "cmps{b|}", { Xb, Yb }, 0 },
2058 { "cmps{R|}", { Xv, Yv }, 0 },
2059 /* a8 */
2060 { "testB", { AL, Ib }, 0 },
2061 { "testS", { eAX, Iv }, 0 },
2062 { "stosB", { Ybr, AL }, 0 },
2063 { "stosS", { Yvr, eAX }, 0 },
2064 { "lodsB", { ALr, Xb }, 0 },
2065 { "lodsS", { eAXr, Xv }, 0 },
2066 { "scasB", { AL, Yb }, 0 },
2067 { "scasS", { eAX, Yv }, 0 },
2068 /* b0 */
2069 { "movB", { RMAL, Ib }, 0 },
2070 { "movB", { RMCL, Ib }, 0 },
2071 { "movB", { RMDL, Ib }, 0 },
2072 { "movB", { RMBL, Ib }, 0 },
2073 { "movB", { RMAH, Ib }, 0 },
2074 { "movB", { RMCH, Ib }, 0 },
2075 { "movB", { RMDH, Ib }, 0 },
2076 { "movB", { RMBH, Ib }, 0 },
2077 /* b8 */
2078 { "mov%LV", { RMeAX, Iv64 }, 0 },
2079 { "mov%LV", { RMeCX, Iv64 }, 0 },
2080 { "mov%LV", { RMeDX, Iv64 }, 0 },
2081 { "mov%LV", { RMeBX, Iv64 }, 0 },
2082 { "mov%LV", { RMeSP, Iv64 }, 0 },
2083 { "mov%LV", { RMeBP, Iv64 }, 0 },
2084 { "mov%LV", { RMeSI, Iv64 }, 0 },
2085 { "mov%LV", { RMeDI, Iv64 }, 0 },
2086 /* c0 */
2087 { REG_TABLE (REG_C0) },
2088 { REG_TABLE (REG_C1) },
2089 { X86_64_TABLE (X86_64_C2) },
2090 { X86_64_TABLE (X86_64_C3) },
2091 { X86_64_TABLE (X86_64_C4) },
2092 { X86_64_TABLE (X86_64_C5) },
2093 { REG_TABLE (REG_C6) },
2094 { REG_TABLE (REG_C7) },
2095 /* c8 */
2096 { "enterP", { Iw, Ib }, 0 },
2097 { "leaveP", { XX }, 0 },
2098 { "{l|}ret{|f}%LP", { Iw }, 0 },
2099 { "{l|}ret{|f}%LP", { XX }, 0 },
2100 { "int3", { XX }, 0 },
2101 { "int", { Ib }, 0 },
2102 { X86_64_TABLE (X86_64_CE) },
2103 { "iret%LP", { XX }, 0 },
2104 /* d0 */
2105 { REG_TABLE (REG_D0) },
2106 { REG_TABLE (REG_D1) },
2107 { REG_TABLE (REG_D2) },
2108 { REG_TABLE (REG_D3) },
2109 { X86_64_TABLE (X86_64_D4) },
2110 { X86_64_TABLE (X86_64_D5) },
2111 { Bad_Opcode },
2112 { "xlat", { DSBX }, 0 },
2113 /* d8 */
2114 { FLOAT },
2115 { FLOAT },
2116 { FLOAT },
2117 { FLOAT },
2118 { FLOAT },
2119 { FLOAT },
2120 { FLOAT },
2121 { FLOAT },
2122 /* e0 */
2123 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2124 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2125 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2126 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2127 { "inB", { AL, Ib }, 0 },
2128 { "inG", { zAX, Ib }, 0 },
2129 { "outB", { Ib, AL }, 0 },
2130 { "outG", { Ib, zAX }, 0 },
2131 /* e8 */
2132 { X86_64_TABLE (X86_64_E8) },
2133 { X86_64_TABLE (X86_64_E9) },
2134 { X86_64_TABLE (X86_64_EA) },
2135 { "jmp", { Jb, BND }, 0 },
2136 { "inB", { AL, indirDX }, 0 },
2137 { "inG", { zAX, indirDX }, 0 },
2138 { "outB", { indirDX, AL }, 0 },
2139 { "outG", { indirDX, zAX }, 0 },
2140 /* f0 */
2141 { Bad_Opcode }, /* lock prefix */
2142 { "int1", { XX }, 0 },
2143 { Bad_Opcode }, /* repne */
2144 { Bad_Opcode }, /* repz */
2145 { "hlt", { XX }, 0 },
2146 { "cmc", { XX }, 0 },
2147 { REG_TABLE (REG_F6) },
2148 { REG_TABLE (REG_F7) },
2149 /* f8 */
2150 { "clc", { XX }, 0 },
2151 { "stc", { XX }, 0 },
2152 { "cli", { XX }, 0 },
2153 { "sti", { XX }, 0 },
2154 { "cld", { XX }, 0 },
2155 { "std", { XX }, 0 },
2156 { REG_TABLE (REG_FE) },
2157 { REG_TABLE (REG_FF) },
2158 };
2159
2160 static const struct dis386 dis386_twobyte[] = {
2161 /* 00 */
2162 { REG_TABLE (REG_0F00 ) },
2163 { REG_TABLE (REG_0F01 ) },
2164 { MOD_TABLE (MOD_0F02) },
2165 { MOD_TABLE (MOD_0F03) },
2166 { Bad_Opcode },
2167 { "syscall", { XX }, 0 },
2168 { "clts", { XX }, 0 },
2169 { "sysret%LQ", { XX }, 0 },
2170 /* 08 */
2171 { "invd", { XX }, 0 },
2172 { PREFIX_TABLE (PREFIX_0F09) },
2173 { Bad_Opcode },
2174 { "ud2", { XX }, 0 },
2175 { Bad_Opcode },
2176 { REG_TABLE (REG_0F0D) },
2177 { "femms", { XX }, 0 },
2178 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2179 /* 10 */
2180 { PREFIX_TABLE (PREFIX_0F10) },
2181 { PREFIX_TABLE (PREFIX_0F11) },
2182 { PREFIX_TABLE (PREFIX_0F12) },
2183 { MOD_TABLE (MOD_0F13) },
2184 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2185 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2186 { PREFIX_TABLE (PREFIX_0F16) },
2187 { MOD_TABLE (MOD_0F17) },
2188 /* 18 */
2189 { REG_TABLE (REG_0F18) },
2190 { "nopQ", { Ev }, 0 },
2191 { PREFIX_TABLE (PREFIX_0F1A) },
2192 { PREFIX_TABLE (PREFIX_0F1B) },
2193 { PREFIX_TABLE (PREFIX_0F1C) },
2194 { "nopQ", { Ev }, 0 },
2195 { PREFIX_TABLE (PREFIX_0F1E) },
2196 { "nopQ", { Ev }, 0 },
2197 /* 20 */
2198 { "movZ", { Em, Cm }, 0 },
2199 { "movZ", { Em, Dm }, 0 },
2200 { "movZ", { Cm, Em }, 0 },
2201 { "movZ", { Dm, Em }, 0 },
2202 { X86_64_TABLE (X86_64_0F24) },
2203 { Bad_Opcode },
2204 { X86_64_TABLE (X86_64_0F26) },
2205 { Bad_Opcode },
2206 /* 28 */
2207 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2208 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2209 { PREFIX_TABLE (PREFIX_0F2A) },
2210 { PREFIX_TABLE (PREFIX_0F2B) },
2211 { PREFIX_TABLE (PREFIX_0F2C) },
2212 { PREFIX_TABLE (PREFIX_0F2D) },
2213 { PREFIX_TABLE (PREFIX_0F2E) },
2214 { PREFIX_TABLE (PREFIX_0F2F) },
2215 /* 30 */
2216 { "wrmsr", { XX }, 0 },
2217 { "rdtsc", { XX }, 0 },
2218 { "rdmsr", { XX }, 0 },
2219 { "rdpmc", { XX }, 0 },
2220 { "sysenter", { SEP }, 0 },
2221 { "sysexit%LQ", { SEP }, 0 },
2222 { Bad_Opcode },
2223 { "getsec", { XX }, 0 },
2224 /* 38 */
2225 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2226 { Bad_Opcode },
2227 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2228 { Bad_Opcode },
2229 { Bad_Opcode },
2230 { Bad_Opcode },
2231 { Bad_Opcode },
2232 { Bad_Opcode },
2233 /* 40 */
2234 { "cmovoS", { Gv, Ev }, 0 },
2235 { "cmovnoS", { Gv, Ev }, 0 },
2236 { "cmovbS", { Gv, Ev }, 0 },
2237 { "cmovaeS", { Gv, Ev }, 0 },
2238 { "cmoveS", { Gv, Ev }, 0 },
2239 { "cmovneS", { Gv, Ev }, 0 },
2240 { "cmovbeS", { Gv, Ev }, 0 },
2241 { "cmovaS", { Gv, Ev }, 0 },
2242 /* 48 */
2243 { "cmovsS", { Gv, Ev }, 0 },
2244 { "cmovnsS", { Gv, Ev }, 0 },
2245 { "cmovpS", { Gv, Ev }, 0 },
2246 { "cmovnpS", { Gv, Ev }, 0 },
2247 { "cmovlS", { Gv, Ev }, 0 },
2248 { "cmovgeS", { Gv, Ev }, 0 },
2249 { "cmovleS", { Gv, Ev }, 0 },
2250 { "cmovgS", { Gv, Ev }, 0 },
2251 /* 50 */
2252 { MOD_TABLE (MOD_0F50) },
2253 { PREFIX_TABLE (PREFIX_0F51) },
2254 { PREFIX_TABLE (PREFIX_0F52) },
2255 { PREFIX_TABLE (PREFIX_0F53) },
2256 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2257 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2258 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2259 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2260 /* 58 */
2261 { PREFIX_TABLE (PREFIX_0F58) },
2262 { PREFIX_TABLE (PREFIX_0F59) },
2263 { PREFIX_TABLE (PREFIX_0F5A) },
2264 { PREFIX_TABLE (PREFIX_0F5B) },
2265 { PREFIX_TABLE (PREFIX_0F5C) },
2266 { PREFIX_TABLE (PREFIX_0F5D) },
2267 { PREFIX_TABLE (PREFIX_0F5E) },
2268 { PREFIX_TABLE (PREFIX_0F5F) },
2269 /* 60 */
2270 { PREFIX_TABLE (PREFIX_0F60) },
2271 { PREFIX_TABLE (PREFIX_0F61) },
2272 { PREFIX_TABLE (PREFIX_0F62) },
2273 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2274 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2275 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2276 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2277 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2278 /* 68 */
2279 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2280 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2281 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2282 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2283 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2284 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2285 { "movK", { MX, Edq }, PREFIX_OPCODE },
2286 { PREFIX_TABLE (PREFIX_0F6F) },
2287 /* 70 */
2288 { PREFIX_TABLE (PREFIX_0F70) },
2289 { MOD_TABLE (MOD_0F71) },
2290 { MOD_TABLE (MOD_0F72) },
2291 { MOD_TABLE (MOD_0F73) },
2292 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2293 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2294 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2295 { "emms", { XX }, PREFIX_OPCODE },
2296 /* 78 */
2297 { PREFIX_TABLE (PREFIX_0F78) },
2298 { PREFIX_TABLE (PREFIX_0F79) },
2299 { Bad_Opcode },
2300 { Bad_Opcode },
2301 { PREFIX_TABLE (PREFIX_0F7C) },
2302 { PREFIX_TABLE (PREFIX_0F7D) },
2303 { PREFIX_TABLE (PREFIX_0F7E) },
2304 { PREFIX_TABLE (PREFIX_0F7F) },
2305 /* 80 */
2306 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2307 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2308 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2309 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2310 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2311 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2312 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2313 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2314 /* 88 */
2315 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2316 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2317 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2318 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2319 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2320 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2321 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2322 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2323 /* 90 */
2324 { "seto", { Eb }, 0 },
2325 { "setno", { Eb }, 0 },
2326 { "setb", { Eb }, 0 },
2327 { "setae", { Eb }, 0 },
2328 { "sete", { Eb }, 0 },
2329 { "setne", { Eb }, 0 },
2330 { "setbe", { Eb }, 0 },
2331 { "seta", { Eb }, 0 },
2332 /* 98 */
2333 { "sets", { Eb }, 0 },
2334 { "setns", { Eb }, 0 },
2335 { "setp", { Eb }, 0 },
2336 { "setnp", { Eb }, 0 },
2337 { "setl", { Eb }, 0 },
2338 { "setge", { Eb }, 0 },
2339 { "setle", { Eb }, 0 },
2340 { "setg", { Eb }, 0 },
2341 /* a0 */
2342 { "pushP", { fs }, 0 },
2343 { "popP", { fs }, 0 },
2344 { "cpuid", { XX }, 0 },
2345 { "btS", { Ev, Gv }, 0 },
2346 { "shldS", { Ev, Gv, Ib }, 0 },
2347 { "shldS", { Ev, Gv, CL }, 0 },
2348 { REG_TABLE (REG_0FA6) },
2349 { REG_TABLE (REG_0FA7) },
2350 /* a8 */
2351 { "pushP", { gs }, 0 },
2352 { "popP", { gs }, 0 },
2353 { "rsm", { XX }, 0 },
2354 { "btsS", { Evh1, Gv }, 0 },
2355 { "shrdS", { Ev, Gv, Ib }, 0 },
2356 { "shrdS", { Ev, Gv, CL }, 0 },
2357 { REG_TABLE (REG_0FAE) },
2358 { "imulS", { Gv, Ev }, 0 },
2359 /* b0 */
2360 { "cmpxchgB", { Ebh1, Gb }, 0 },
2361 { "cmpxchgS", { Evh1, Gv }, 0 },
2362 { MOD_TABLE (MOD_0FB2) },
2363 { "btrS", { Evh1, Gv }, 0 },
2364 { MOD_TABLE (MOD_0FB4) },
2365 { MOD_TABLE (MOD_0FB5) },
2366 { "movz{bR|x}", { Gv, Eb }, 0 },
2367 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2368 /* b8 */
2369 { PREFIX_TABLE (PREFIX_0FB8) },
2370 { "ud1S", { Gv, Ev }, 0 },
2371 { REG_TABLE (REG_0FBA) },
2372 { "btcS", { Evh1, Gv }, 0 },
2373 { PREFIX_TABLE (PREFIX_0FBC) },
2374 { PREFIX_TABLE (PREFIX_0FBD) },
2375 { "movs{bR|x}", { Gv, Eb }, 0 },
2376 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2377 /* c0 */
2378 { "xaddB", { Ebh1, Gb }, 0 },
2379 { "xaddS", { Evh1, Gv }, 0 },
2380 { PREFIX_TABLE (PREFIX_0FC2) },
2381 { MOD_TABLE (MOD_0FC3) },
2382 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
2383 { "pextrw", { Gd, MS, Ib }, PREFIX_OPCODE },
2384 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2385 { REG_TABLE (REG_0FC7) },
2386 /* c8 */
2387 { "bswap", { RMeAX }, 0 },
2388 { "bswap", { RMeCX }, 0 },
2389 { "bswap", { RMeDX }, 0 },
2390 { "bswap", { RMeBX }, 0 },
2391 { "bswap", { RMeSP }, 0 },
2392 { "bswap", { RMeBP }, 0 },
2393 { "bswap", { RMeSI }, 0 },
2394 { "bswap", { RMeDI }, 0 },
2395 /* d0 */
2396 { PREFIX_TABLE (PREFIX_0FD0) },
2397 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2398 { "psrld", { MX, EM }, PREFIX_OPCODE },
2399 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2400 { "paddq", { MX, EM }, PREFIX_OPCODE },
2401 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2402 { PREFIX_TABLE (PREFIX_0FD6) },
2403 { MOD_TABLE (MOD_0FD7) },
2404 /* d8 */
2405 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2406 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2407 { "pminub", { MX, EM }, PREFIX_OPCODE },
2408 { "pand", { MX, EM }, PREFIX_OPCODE },
2409 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2410 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2411 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2412 { "pandn", { MX, EM }, PREFIX_OPCODE },
2413 /* e0 */
2414 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2415 { "psraw", { MX, EM }, PREFIX_OPCODE },
2416 { "psrad", { MX, EM }, PREFIX_OPCODE },
2417 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2418 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2419 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2420 { PREFIX_TABLE (PREFIX_0FE6) },
2421 { PREFIX_TABLE (PREFIX_0FE7) },
2422 /* e8 */
2423 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2424 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2425 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2426 { "por", { MX, EM }, PREFIX_OPCODE },
2427 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2428 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2429 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2430 { "pxor", { MX, EM }, PREFIX_OPCODE },
2431 /* f0 */
2432 { PREFIX_TABLE (PREFIX_0FF0) },
2433 { "psllw", { MX, EM }, PREFIX_OPCODE },
2434 { "pslld", { MX, EM }, PREFIX_OPCODE },
2435 { "psllq", { MX, EM }, PREFIX_OPCODE },
2436 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2437 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2438 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2439 { PREFIX_TABLE (PREFIX_0FF7) },
2440 /* f8 */
2441 { "psubb", { MX, EM }, PREFIX_OPCODE },
2442 { "psubw", { MX, EM }, PREFIX_OPCODE },
2443 { "psubd", { MX, EM }, PREFIX_OPCODE },
2444 { "psubq", { MX, EM }, PREFIX_OPCODE },
2445 { "paddb", { MX, EM }, PREFIX_OPCODE },
2446 { "paddw", { MX, EM }, PREFIX_OPCODE },
2447 { "paddd", { MX, EM }, PREFIX_OPCODE },
2448 { "ud0S", { Gv, Ev }, 0 },
2449 };
2450
2451 static const bool onebyte_has_modrm[256] = {
2452 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2453 /* ------------------------------- */
2454 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2455 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2456 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2457 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2458 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2459 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2460 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2461 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2462 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2463 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2464 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2465 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2466 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2467 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2468 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2469 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2470 /* ------------------------------- */
2471 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2472 };
2473
2474 static const bool twobyte_has_modrm[256] = {
2475 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2476 /* ------------------------------- */
2477 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2478 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2479 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2480 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2481 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2482 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2483 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2484 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2485 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2486 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2487 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2488 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2489 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2490 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2491 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2492 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2493 /* ------------------------------- */
2494 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2495 };
2496
2497
2498 struct op
2499 {
2500 const char *name;
2501 unsigned int len;
2502 };
2503
2504 /* If we are accessing mod/rm/reg without need_modrm set, then the
2505 values are stale. Hitting this abort likely indicates that you
2506 need to update onebyte_has_modrm or twobyte_has_modrm. */
2507 #define MODRM_CHECK if (!ins->need_modrm) abort ()
2508
2509 static const char intel_index16[][6] = {
2510 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2511 };
2512
2513 static const char att_names64[][8] = {
2514 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2515 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2516 };
2517 static const char att_names32[][8] = {
2518 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2519 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2520 };
2521 static const char att_names16[][8] = {
2522 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2523 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2524 };
2525 static const char att_names8[][8] = {
2526 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2527 };
2528 static const char att_names8rex[][8] = {
2529 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2530 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2531 };
2532 static const char att_names_seg[][4] = {
2533 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2534 };
2535 static const char att_index64[] = "%riz";
2536 static const char att_index32[] = "%eiz";
2537 static const char att_index16[][8] = {
2538 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2539 };
2540
2541 static const char att_names_mm[][8] = {
2542 "%mm0", "%mm1", "%mm2", "%mm3",
2543 "%mm4", "%mm5", "%mm6", "%mm7"
2544 };
2545
2546 static const char att_names_bnd[][8] = {
2547 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2548 };
2549
2550 static const char att_names_xmm[][8] = {
2551 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2552 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2553 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2554 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2555 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2556 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2557 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2558 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2559 };
2560
2561 static const char att_names_ymm[][8] = {
2562 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2563 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2564 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2565 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2566 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2567 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2568 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2569 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2570 };
2571
2572 static const char att_names_zmm[][8] = {
2573 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2574 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2575 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2576 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2577 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2578 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2579 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2580 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2581 };
2582
2583 static const char att_names_tmm[][8] = {
2584 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2585 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2586 };
2587
2588 static const char att_names_mask[][8] = {
2589 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2590 };
2591
2592 static const char *const names_rounding[] =
2593 {
2594 "{rn-",
2595 "{rd-",
2596 "{ru-",
2597 "{rz-"
2598 };
2599
2600 static const struct dis386 reg_table[][8] = {
2601 /* REG_80 */
2602 {
2603 { "addA", { Ebh1, Ib }, 0 },
2604 { "orA", { Ebh1, Ib }, 0 },
2605 { "adcA", { Ebh1, Ib }, 0 },
2606 { "sbbA", { Ebh1, Ib }, 0 },
2607 { "andA", { Ebh1, Ib }, 0 },
2608 { "subA", { Ebh1, Ib }, 0 },
2609 { "xorA", { Ebh1, Ib }, 0 },
2610 { "cmpA", { Eb, Ib }, 0 },
2611 },
2612 /* REG_81 */
2613 {
2614 { "addQ", { Evh1, Iv }, 0 },
2615 { "orQ", { Evh1, Iv }, 0 },
2616 { "adcQ", { Evh1, Iv }, 0 },
2617 { "sbbQ", { Evh1, Iv }, 0 },
2618 { "andQ", { Evh1, Iv }, 0 },
2619 { "subQ", { Evh1, Iv }, 0 },
2620 { "xorQ", { Evh1, Iv }, 0 },
2621 { "cmpQ", { Ev, Iv }, 0 },
2622 },
2623 /* REG_83 */
2624 {
2625 { "addQ", { Evh1, sIb }, 0 },
2626 { "orQ", { Evh1, sIb }, 0 },
2627 { "adcQ", { Evh1, sIb }, 0 },
2628 { "sbbQ", { Evh1, sIb }, 0 },
2629 { "andQ", { Evh1, sIb }, 0 },
2630 { "subQ", { Evh1, sIb }, 0 },
2631 { "xorQ", { Evh1, sIb }, 0 },
2632 { "cmpQ", { Ev, sIb }, 0 },
2633 },
2634 /* REG_8F */
2635 {
2636 { "pop{P|}", { stackEv }, 0 },
2637 { XOP_8F_TABLE (XOP_09) },
2638 { Bad_Opcode },
2639 { Bad_Opcode },
2640 { Bad_Opcode },
2641 { XOP_8F_TABLE (XOP_09) },
2642 },
2643 /* REG_C0 */
2644 {
2645 { "rolA", { Eb, Ib }, 0 },
2646 { "rorA", { Eb, Ib }, 0 },
2647 { "rclA", { Eb, Ib }, 0 },
2648 { "rcrA", { Eb, Ib }, 0 },
2649 { "shlA", { Eb, Ib }, 0 },
2650 { "shrA", { Eb, Ib }, 0 },
2651 { "shlA", { Eb, Ib }, 0 },
2652 { "sarA", { Eb, Ib }, 0 },
2653 },
2654 /* REG_C1 */
2655 {
2656 { "rolQ", { Ev, Ib }, 0 },
2657 { "rorQ", { Ev, Ib }, 0 },
2658 { "rclQ", { Ev, Ib }, 0 },
2659 { "rcrQ", { Ev, Ib }, 0 },
2660 { "shlQ", { Ev, Ib }, 0 },
2661 { "shrQ", { Ev, Ib }, 0 },
2662 { "shlQ", { Ev, Ib }, 0 },
2663 { "sarQ", { Ev, Ib }, 0 },
2664 },
2665 /* REG_C6 */
2666 {
2667 { "movA", { Ebh3, Ib }, 0 },
2668 { Bad_Opcode },
2669 { Bad_Opcode },
2670 { Bad_Opcode },
2671 { Bad_Opcode },
2672 { Bad_Opcode },
2673 { Bad_Opcode },
2674 { MOD_TABLE (MOD_C6_REG_7) },
2675 },
2676 /* REG_C7 */
2677 {
2678 { "movQ", { Evh3, Iv }, 0 },
2679 { Bad_Opcode },
2680 { Bad_Opcode },
2681 { Bad_Opcode },
2682 { Bad_Opcode },
2683 { Bad_Opcode },
2684 { Bad_Opcode },
2685 { MOD_TABLE (MOD_C7_REG_7) },
2686 },
2687 /* REG_D0 */
2688 {
2689 { "rolA", { Eb, I1 }, 0 },
2690 { "rorA", { Eb, I1 }, 0 },
2691 { "rclA", { Eb, I1 }, 0 },
2692 { "rcrA", { Eb, I1 }, 0 },
2693 { "shlA", { Eb, I1 }, 0 },
2694 { "shrA", { Eb, I1 }, 0 },
2695 { "shlA", { Eb, I1 }, 0 },
2696 { "sarA", { Eb, I1 }, 0 },
2697 },
2698 /* REG_D1 */
2699 {
2700 { "rolQ", { Ev, I1 }, 0 },
2701 { "rorQ", { Ev, I1 }, 0 },
2702 { "rclQ", { Ev, I1 }, 0 },
2703 { "rcrQ", { Ev, I1 }, 0 },
2704 { "shlQ", { Ev, I1 }, 0 },
2705 { "shrQ", { Ev, I1 }, 0 },
2706 { "shlQ", { Ev, I1 }, 0 },
2707 { "sarQ", { Ev, I1 }, 0 },
2708 },
2709 /* REG_D2 */
2710 {
2711 { "rolA", { Eb, CL }, 0 },
2712 { "rorA", { Eb, CL }, 0 },
2713 { "rclA", { Eb, CL }, 0 },
2714 { "rcrA", { Eb, CL }, 0 },
2715 { "shlA", { Eb, CL }, 0 },
2716 { "shrA", { Eb, CL }, 0 },
2717 { "shlA", { Eb, CL }, 0 },
2718 { "sarA", { Eb, CL }, 0 },
2719 },
2720 /* REG_D3 */
2721 {
2722 { "rolQ", { Ev, CL }, 0 },
2723 { "rorQ", { Ev, CL }, 0 },
2724 { "rclQ", { Ev, CL }, 0 },
2725 { "rcrQ", { Ev, CL }, 0 },
2726 { "shlQ", { Ev, CL }, 0 },
2727 { "shrQ", { Ev, CL }, 0 },
2728 { "shlQ", { Ev, CL }, 0 },
2729 { "sarQ", { Ev, CL }, 0 },
2730 },
2731 /* REG_F6 */
2732 {
2733 { "testA", { Eb, Ib }, 0 },
2734 { "testA", { Eb, Ib }, 0 },
2735 { "notA", { Ebh1 }, 0 },
2736 { "negA", { Ebh1 }, 0 },
2737 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2738 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2739 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2740 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2741 },
2742 /* REG_F7 */
2743 {
2744 { "testQ", { Ev, Iv }, 0 },
2745 { "testQ", { Ev, Iv }, 0 },
2746 { "notQ", { Evh1 }, 0 },
2747 { "negQ", { Evh1 }, 0 },
2748 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2749 { "imulQ", { Ev }, 0 },
2750 { "divQ", { Ev }, 0 },
2751 { "idivQ", { Ev }, 0 },
2752 },
2753 /* REG_FE */
2754 {
2755 { "incA", { Ebh1 }, 0 },
2756 { "decA", { Ebh1 }, 0 },
2757 },
2758 /* REG_FF */
2759 {
2760 { "incQ", { Evh1 }, 0 },
2761 { "decQ", { Evh1 }, 0 },
2762 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2763 { MOD_TABLE (MOD_FF_REG_3) },
2764 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2765 { MOD_TABLE (MOD_FF_REG_5) },
2766 { "push{P|}", { stackEv }, 0 },
2767 { Bad_Opcode },
2768 },
2769 /* REG_0F00 */
2770 {
2771 { "sldtD", { Sv }, 0 },
2772 { "strD", { Sv }, 0 },
2773 { "lldt", { Ew }, 0 },
2774 { "ltr", { Ew }, 0 },
2775 { "verr", { Ew }, 0 },
2776 { "verw", { Ew }, 0 },
2777 { Bad_Opcode },
2778 { Bad_Opcode },
2779 },
2780 /* REG_0F01 */
2781 {
2782 { MOD_TABLE (MOD_0F01_REG_0) },
2783 { MOD_TABLE (MOD_0F01_REG_1) },
2784 { MOD_TABLE (MOD_0F01_REG_2) },
2785 { MOD_TABLE (MOD_0F01_REG_3) },
2786 { "smswD", { Sv }, 0 },
2787 { MOD_TABLE (MOD_0F01_REG_5) },
2788 { "lmsw", { Ew }, 0 },
2789 { MOD_TABLE (MOD_0F01_REG_7) },
2790 },
2791 /* REG_0F0D */
2792 {
2793 { "prefetch", { Mb }, 0 },
2794 { "prefetchw", { Mb }, 0 },
2795 { "prefetchwt1", { Mb }, 0 },
2796 { "prefetch", { Mb }, 0 },
2797 { "prefetch", { Mb }, 0 },
2798 { "prefetch", { Mb }, 0 },
2799 { "prefetch", { Mb }, 0 },
2800 { "prefetch", { Mb }, 0 },
2801 },
2802 /* REG_0F18 */
2803 {
2804 { MOD_TABLE (MOD_0F18_REG_0) },
2805 { MOD_TABLE (MOD_0F18_REG_1) },
2806 { MOD_TABLE (MOD_0F18_REG_2) },
2807 { MOD_TABLE (MOD_0F18_REG_3) },
2808 { "nopQ", { Ev }, 0 },
2809 { "nopQ", { Ev }, 0 },
2810 { MOD_TABLE (MOD_0F18_REG_6) },
2811 { MOD_TABLE (MOD_0F18_REG_7) },
2812 },
2813 /* REG_0F1C_P_0_MOD_0 */
2814 {
2815 { "cldemote", { Mb }, 0 },
2816 { "nopQ", { Ev }, 0 },
2817 { "nopQ", { Ev }, 0 },
2818 { "nopQ", { Ev }, 0 },
2819 { "nopQ", { Ev }, 0 },
2820 { "nopQ", { Ev }, 0 },
2821 { "nopQ", { Ev }, 0 },
2822 { "nopQ", { Ev }, 0 },
2823 },
2824 /* REG_0F1E_P_1_MOD_3 */
2825 {
2826 { "nopQ", { Ev }, PREFIX_IGNORED },
2827 { "rdsspK", { Edq }, 0 },
2828 { "nopQ", { Ev }, PREFIX_IGNORED },
2829 { "nopQ", { Ev }, PREFIX_IGNORED },
2830 { "nopQ", { Ev }, PREFIX_IGNORED },
2831 { "nopQ", { Ev }, PREFIX_IGNORED },
2832 { "nopQ", { Ev }, PREFIX_IGNORED },
2833 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2834 },
2835 /* REG_0F38D8_PREFIX_1 */
2836 {
2837 { "aesencwide128kl", { M }, 0 },
2838 { "aesdecwide128kl", { M }, 0 },
2839 { "aesencwide256kl", { M }, 0 },
2840 { "aesdecwide256kl", { M }, 0 },
2841 },
2842 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2843 {
2844 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2845 },
2846 /* REG_0F71_MOD_0 */
2847 {
2848 { Bad_Opcode },
2849 { Bad_Opcode },
2850 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
2851 { Bad_Opcode },
2852 { "psraw", { MS, Ib }, PREFIX_OPCODE },
2853 { Bad_Opcode },
2854 { "psllw", { MS, Ib }, PREFIX_OPCODE },
2855 },
2856 /* REG_0F72_MOD_0 */
2857 {
2858 { Bad_Opcode },
2859 { Bad_Opcode },
2860 { "psrld", { MS, Ib }, PREFIX_OPCODE },
2861 { Bad_Opcode },
2862 { "psrad", { MS, Ib }, PREFIX_OPCODE },
2863 { Bad_Opcode },
2864 { "pslld", { MS, Ib }, PREFIX_OPCODE },
2865 },
2866 /* REG_0F73_MOD_0 */
2867 {
2868 { Bad_Opcode },
2869 { Bad_Opcode },
2870 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
2871 { "psrldq", { XS, Ib }, PREFIX_DATA },
2872 { Bad_Opcode },
2873 { Bad_Opcode },
2874 { "psllq", { MS, Ib }, PREFIX_OPCODE },
2875 { "pslldq", { XS, Ib }, PREFIX_DATA },
2876 },
2877 /* REG_0FA6 */
2878 {
2879 { "montmul", { { OP_0f07, 0 } }, 0 },
2880 { "xsha1", { { OP_0f07, 0 } }, 0 },
2881 { "xsha256", { { OP_0f07, 0 } }, 0 },
2882 },
2883 /* REG_0FA7 */
2884 {
2885 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2886 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2887 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2888 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2889 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2890 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2891 },
2892 /* REG_0FAE */
2893 {
2894 { MOD_TABLE (MOD_0FAE_REG_0) },
2895 { MOD_TABLE (MOD_0FAE_REG_1) },
2896 { MOD_TABLE (MOD_0FAE_REG_2) },
2897 { MOD_TABLE (MOD_0FAE_REG_3) },
2898 { MOD_TABLE (MOD_0FAE_REG_4) },
2899 { MOD_TABLE (MOD_0FAE_REG_5) },
2900 { MOD_TABLE (MOD_0FAE_REG_6) },
2901 { MOD_TABLE (MOD_0FAE_REG_7) },
2902 },
2903 /* REG_0FBA */
2904 {
2905 { Bad_Opcode },
2906 { Bad_Opcode },
2907 { Bad_Opcode },
2908 { Bad_Opcode },
2909 { "btQ", { Ev, Ib }, 0 },
2910 { "btsQ", { Evh1, Ib }, 0 },
2911 { "btrQ", { Evh1, Ib }, 0 },
2912 { "btcQ", { Evh1, Ib }, 0 },
2913 },
2914 /* REG_0FC7 */
2915 {
2916 { Bad_Opcode },
2917 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2918 { Bad_Opcode },
2919 { MOD_TABLE (MOD_0FC7_REG_3) },
2920 { MOD_TABLE (MOD_0FC7_REG_4) },
2921 { MOD_TABLE (MOD_0FC7_REG_5) },
2922 { MOD_TABLE (MOD_0FC7_REG_6) },
2923 { MOD_TABLE (MOD_0FC7_REG_7) },
2924 },
2925 /* REG_VEX_0F71_M_0 */
2926 {
2927 { Bad_Opcode },
2928 { Bad_Opcode },
2929 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
2930 { Bad_Opcode },
2931 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
2932 { Bad_Opcode },
2933 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
2934 },
2935 /* REG_VEX_0F72_M_0 */
2936 {
2937 { Bad_Opcode },
2938 { Bad_Opcode },
2939 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
2940 { Bad_Opcode },
2941 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
2942 { Bad_Opcode },
2943 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
2944 },
2945 /* REG_VEX_0F73_M_0 */
2946 {
2947 { Bad_Opcode },
2948 { Bad_Opcode },
2949 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
2950 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
2951 { Bad_Opcode },
2952 { Bad_Opcode },
2953 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
2954 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
2955 },
2956 /* REG_VEX_0FAE */
2957 {
2958 { Bad_Opcode },
2959 { Bad_Opcode },
2960 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2961 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2962 },
2963 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2964 {
2965 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2966 },
2967 /* REG_VEX_0F38F3_L_0 */
2968 {
2969 { Bad_Opcode },
2970 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
2971 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
2972 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
2973 },
2974 /* REG_XOP_09_01_L_0 */
2975 {
2976 { Bad_Opcode },
2977 { "blcfill", { VexGdq, Edq }, 0 },
2978 { "blsfill", { VexGdq, Edq }, 0 },
2979 { "blcs", { VexGdq, Edq }, 0 },
2980 { "tzmsk", { VexGdq, Edq }, 0 },
2981 { "blcic", { VexGdq, Edq }, 0 },
2982 { "blsic", { VexGdq, Edq }, 0 },
2983 { "t1mskc", { VexGdq, Edq }, 0 },
2984 },
2985 /* REG_XOP_09_02_L_0 */
2986 {
2987 { Bad_Opcode },
2988 { "blcmsk", { VexGdq, Edq }, 0 },
2989 { Bad_Opcode },
2990 { Bad_Opcode },
2991 { Bad_Opcode },
2992 { Bad_Opcode },
2993 { "blci", { VexGdq, Edq }, 0 },
2994 },
2995 /* REG_XOP_09_12_M_1_L_0 */
2996 {
2997 { "llwpcb", { Edq }, 0 },
2998 { "slwpcb", { Edq }, 0 },
2999 },
3000 /* REG_XOP_0A_12_L_0 */
3001 {
3002 { "lwpins", { VexGdq, Ed, Id }, 0 },
3003 { "lwpval", { VexGdq, Ed, Id }, 0 },
3004 },
3005
3006 #include "i386-dis-evex-reg.h"
3007 };
3008
3009 static const struct dis386 prefix_table[][4] = {
3010 /* PREFIX_90 */
3011 {
3012 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3013 { "pause", { XX }, 0 },
3014 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3015 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3016 },
3017
3018 /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3019 {
3020 { "wrmsrns", { Skip_MODRM }, 0 },
3021 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3022 { Bad_Opcode },
3023 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3024 },
3025
3026 /* PREFIX_0F01_REG_1_RM_4 */
3027 {
3028 { Bad_Opcode },
3029 { Bad_Opcode },
3030 { "tdcall", { Skip_MODRM }, 0 },
3031 { Bad_Opcode },
3032 },
3033
3034 /* PREFIX_0F01_REG_1_RM_5 */
3035 {
3036 { Bad_Opcode },
3037 { Bad_Opcode },
3038 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3039 { Bad_Opcode },
3040 },
3041
3042 /* PREFIX_0F01_REG_1_RM_6 */
3043 {
3044 { Bad_Opcode },
3045 { Bad_Opcode },
3046 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3047 { Bad_Opcode },
3048 },
3049
3050 /* PREFIX_0F01_REG_1_RM_7 */
3051 {
3052 { "encls", { Skip_MODRM }, 0 },
3053 { Bad_Opcode },
3054 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3055 { Bad_Opcode },
3056 },
3057
3058 /* PREFIX_0F01_REG_3_RM_1 */
3059 {
3060 { "vmmcall", { Skip_MODRM }, 0 },
3061 { "vmgexit", { Skip_MODRM }, 0 },
3062 { Bad_Opcode },
3063 { "vmgexit", { Skip_MODRM }, 0 },
3064 },
3065
3066 /* PREFIX_0F01_REG_5_MOD_0 */
3067 {
3068 { Bad_Opcode },
3069 { "rstorssp", { Mq }, PREFIX_OPCODE },
3070 },
3071
3072 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3073 {
3074 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3075 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3076 { Bad_Opcode },
3077 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3078 },
3079
3080 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3081 {
3082 { Bad_Opcode },
3083 { Bad_Opcode },
3084 { Bad_Opcode },
3085 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3086 },
3087
3088 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3089 {
3090 { Bad_Opcode },
3091 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3092 },
3093
3094 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3095 {
3096 { Bad_Opcode },
3097 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3098 },
3099
3100 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3101 {
3102 { Bad_Opcode },
3103 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3104 },
3105
3106 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3107 {
3108 { "rdpkru", { Skip_MODRM }, 0 },
3109 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3110 },
3111
3112 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3113 {
3114 { "wrpkru", { Skip_MODRM }, 0 },
3115 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3116 },
3117
3118 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3119 {
3120 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3121 { "mcommit", { Skip_MODRM }, 0 },
3122 },
3123
3124 /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3125 {
3126 { "rdpru", { Skip_MODRM }, 0 },
3127 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3128 },
3129
3130 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3131 {
3132 { "invlpgb", { Skip_MODRM }, 0 },
3133 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3134 { Bad_Opcode },
3135 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3136 },
3137
3138 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3139 {
3140 { "tlbsync", { Skip_MODRM }, 0 },
3141 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3142 { Bad_Opcode },
3143 { "pvalidate", { Skip_MODRM }, 0 },
3144 },
3145
3146 /* PREFIX_0F09 */
3147 {
3148 { "wbinvd", { XX }, 0 },
3149 { "wbnoinvd", { XX }, 0 },
3150 },
3151
3152 /* PREFIX_0F10 */
3153 {
3154 { "movups", { XM, EXx }, PREFIX_OPCODE },
3155 { "movss", { XM, EXd }, PREFIX_OPCODE },
3156 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3157 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3158 },
3159
3160 /* PREFIX_0F11 */
3161 {
3162 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3163 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3164 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3165 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3166 },
3167
3168 /* PREFIX_0F12 */
3169 {
3170 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3171 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3172 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3173 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3174 },
3175
3176 /* PREFIX_0F16 */
3177 {
3178 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3179 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3180 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3181 },
3182
3183 /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3184 {
3185 { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
3186 { "nopQ", { Ev }, 0 },
3187 { "nopQ", { Ev }, 0 },
3188 { "nopQ", { Ev }, 0 },
3189 },
3190
3191 /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3192 {
3193 { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
3194 { "nopQ", { Ev }, 0 },
3195 { "nopQ", { Ev }, 0 },
3196 { "nopQ", { Ev }, 0 },
3197 },
3198
3199 /* PREFIX_0F1A */
3200 {
3201 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3202 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3203 { "bndmov", { Gbnd, Ebnd }, 0 },
3204 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3205 },
3206
3207 /* PREFIX_0F1B */
3208 {
3209 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3210 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3211 { "bndmov", { EbndS, Gbnd }, 0 },
3212 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3213 },
3214
3215 /* PREFIX_0F1C */
3216 {
3217 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3218 { "nopQ", { Ev }, PREFIX_IGNORED },
3219 { "nopQ", { Ev }, 0 },
3220 { "nopQ", { Ev }, PREFIX_IGNORED },
3221 },
3222
3223 /* PREFIX_0F1E */
3224 {
3225 { "nopQ", { Ev }, 0 },
3226 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3227 { "nopQ", { Ev }, 0 },
3228 { NULL, { XX }, PREFIX_IGNORED },
3229 },
3230
3231 /* PREFIX_0F2A */
3232 {
3233 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3234 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3235 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3236 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3237 },
3238
3239 /* PREFIX_0F2B */
3240 {
3241 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3242 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3243 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3244 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3245 },
3246
3247 /* PREFIX_0F2C */
3248 {
3249 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3250 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3251 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3252 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3253 },
3254
3255 /* PREFIX_0F2D */
3256 {
3257 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3258 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3259 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3260 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3261 },
3262
3263 /* PREFIX_0F2E */
3264 {
3265 { "ucomiss",{ XM, EXd }, 0 },
3266 { Bad_Opcode },
3267 { "ucomisd",{ XM, EXq }, 0 },
3268 },
3269
3270 /* PREFIX_0F2F */
3271 {
3272 { "comiss", { XM, EXd }, 0 },
3273 { Bad_Opcode },
3274 { "comisd", { XM, EXq }, 0 },
3275 },
3276
3277 /* PREFIX_0F51 */
3278 {
3279 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3280 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3281 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3282 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3283 },
3284
3285 /* PREFIX_0F52 */
3286 {
3287 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3288 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3289 },
3290
3291 /* PREFIX_0F53 */
3292 {
3293 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3294 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3295 },
3296
3297 /* PREFIX_0F58 */
3298 {
3299 { "addps", { XM, EXx }, PREFIX_OPCODE },
3300 { "addss", { XM, EXd }, PREFIX_OPCODE },
3301 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3302 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3303 },
3304
3305 /* PREFIX_0F59 */
3306 {
3307 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3308 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3309 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3310 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3311 },
3312
3313 /* PREFIX_0F5A */
3314 {
3315 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3316 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3317 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3318 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3319 },
3320
3321 /* PREFIX_0F5B */
3322 {
3323 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3324 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3325 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3326 },
3327
3328 /* PREFIX_0F5C */
3329 {
3330 { "subps", { XM, EXx }, PREFIX_OPCODE },
3331 { "subss", { XM, EXd }, PREFIX_OPCODE },
3332 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3333 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3334 },
3335
3336 /* PREFIX_0F5D */
3337 {
3338 { "minps", { XM, EXx }, PREFIX_OPCODE },
3339 { "minss", { XM, EXd }, PREFIX_OPCODE },
3340 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3341 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3342 },
3343
3344 /* PREFIX_0F5E */
3345 {
3346 { "divps", { XM, EXx }, PREFIX_OPCODE },
3347 { "divss", { XM, EXd }, PREFIX_OPCODE },
3348 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3349 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3350 },
3351
3352 /* PREFIX_0F5F */
3353 {
3354 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3355 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3356 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3357 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3358 },
3359
3360 /* PREFIX_0F60 */
3361 {
3362 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3363 { Bad_Opcode },
3364 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3365 },
3366
3367 /* PREFIX_0F61 */
3368 {
3369 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3370 { Bad_Opcode },
3371 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3372 },
3373
3374 /* PREFIX_0F62 */
3375 {
3376 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3377 { Bad_Opcode },
3378 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3379 },
3380
3381 /* PREFIX_0F6F */
3382 {
3383 { "movq", { MX, EM }, PREFIX_OPCODE },
3384 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3385 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3386 },
3387
3388 /* PREFIX_0F70 */
3389 {
3390 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3391 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3392 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3393 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3394 },
3395
3396 /* PREFIX_0F78 */
3397 {
3398 {"vmread", { Em, Gm }, 0 },
3399 { Bad_Opcode },
3400 {"extrq", { XS, Ib, Ib }, 0 },
3401 {"insertq", { XM, XS, Ib, Ib }, 0 },
3402 },
3403
3404 /* PREFIX_0F79 */
3405 {
3406 {"vmwrite", { Gm, Em }, 0 },
3407 { Bad_Opcode },
3408 {"extrq", { XM, XS }, 0 },
3409 {"insertq", { XM, XS }, 0 },
3410 },
3411
3412 /* PREFIX_0F7C */
3413 {
3414 { Bad_Opcode },
3415 { Bad_Opcode },
3416 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3417 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3418 },
3419
3420 /* PREFIX_0F7D */
3421 {
3422 { Bad_Opcode },
3423 { Bad_Opcode },
3424 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3425 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3426 },
3427
3428 /* PREFIX_0F7E */
3429 {
3430 { "movK", { Edq, MX }, PREFIX_OPCODE },
3431 { "movq", { XM, EXq }, PREFIX_OPCODE },
3432 { "movK", { Edq, XM }, PREFIX_OPCODE },
3433 },
3434
3435 /* PREFIX_0F7F */
3436 {
3437 { "movq", { EMS, MX }, PREFIX_OPCODE },
3438 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3439 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3440 },
3441
3442 /* PREFIX_0FAE_REG_0_MOD_3 */
3443 {
3444 { Bad_Opcode },
3445 { "rdfsbase", { Ev }, 0 },
3446 },
3447
3448 /* PREFIX_0FAE_REG_1_MOD_3 */
3449 {
3450 { Bad_Opcode },
3451 { "rdgsbase", { Ev }, 0 },
3452 },
3453
3454 /* PREFIX_0FAE_REG_2_MOD_3 */
3455 {
3456 { Bad_Opcode },
3457 { "wrfsbase", { Ev }, 0 },
3458 },
3459
3460 /* PREFIX_0FAE_REG_3_MOD_3 */
3461 {
3462 { Bad_Opcode },
3463 { "wrgsbase", { Ev }, 0 },
3464 },
3465
3466 /* PREFIX_0FAE_REG_4_MOD_0 */
3467 {
3468 { "xsave", { FXSAVE }, 0 },
3469 { "ptwrite{%LQ|}", { Edq }, 0 },
3470 },
3471
3472 /* PREFIX_0FAE_REG_4_MOD_3 */
3473 {
3474 { Bad_Opcode },
3475 { "ptwrite{%LQ|}", { Edq }, 0 },
3476 },
3477
3478 /* PREFIX_0FAE_REG_5_MOD_3 */
3479 {
3480 { "lfence", { Skip_MODRM }, 0 },
3481 { "incsspK", { Edq }, PREFIX_OPCODE },
3482 },
3483
3484 /* PREFIX_0FAE_REG_6_MOD_0 */
3485 {
3486 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3487 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3488 { "clwb", { Mb }, PREFIX_OPCODE },
3489 },
3490
3491 /* PREFIX_0FAE_REG_6_MOD_3 */
3492 {
3493 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3494 { "umonitor", { Eva }, PREFIX_OPCODE },
3495 { "tpause", { Edq }, PREFIX_OPCODE },
3496 { "umwait", { Edq }, PREFIX_OPCODE },
3497 },
3498
3499 /* PREFIX_0FAE_REG_7_MOD_0 */
3500 {
3501 { "clflush", { Mb }, 0 },
3502 { Bad_Opcode },
3503 { "clflushopt", { Mb }, 0 },
3504 },
3505
3506 /* PREFIX_0FB8 */
3507 {
3508 { Bad_Opcode },
3509 { "popcntS", { Gv, Ev }, 0 },
3510 },
3511
3512 /* PREFIX_0FBC */
3513 {
3514 { "bsfS", { Gv, Ev }, 0 },
3515 { "tzcntS", { Gv, Ev }, 0 },
3516 { "bsfS", { Gv, Ev }, 0 },
3517 },
3518
3519 /* PREFIX_0FBD */
3520 {
3521 { "bsrS", { Gv, Ev }, 0 },
3522 { "lzcntS", { Gv, Ev }, 0 },
3523 { "bsrS", { Gv, Ev }, 0 },
3524 },
3525
3526 /* PREFIX_0FC2 */
3527 {
3528 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3529 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3530 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3531 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3532 },
3533
3534 /* PREFIX_0FC7_REG_6_MOD_0 */
3535 {
3536 { "vmptrld",{ Mq }, 0 },
3537 { "vmxon", { Mq }, 0 },
3538 { "vmclear",{ Mq }, 0 },
3539 },
3540
3541 /* PREFIX_0FC7_REG_6_MOD_3 */
3542 {
3543 { "rdrand", { Ev }, 0 },
3544 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3545 { "rdrand", { Ev }, 0 }
3546 },
3547
3548 /* PREFIX_0FC7_REG_7_MOD_3 */
3549 {
3550 { "rdseed", { Ev }, 0 },
3551 { "rdpid", { Em }, 0 },
3552 { "rdseed", { Ev }, 0 },
3553 },
3554
3555 /* PREFIX_0FD0 */
3556 {
3557 { Bad_Opcode },
3558 { Bad_Opcode },
3559 { "addsubpd", { XM, EXx }, 0 },
3560 { "addsubps", { XM, EXx }, 0 },
3561 },
3562
3563 /* PREFIX_0FD6 */
3564 {
3565 { Bad_Opcode },
3566 { "movq2dq",{ XM, MS }, 0 },
3567 { "movq", { EXqS, XM }, 0 },
3568 { "movdq2q",{ MX, XS }, 0 },
3569 },
3570
3571 /* PREFIX_0FE6 */
3572 {
3573 { Bad_Opcode },
3574 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3575 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3576 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3577 },
3578
3579 /* PREFIX_0FE7 */
3580 {
3581 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3582 { Bad_Opcode },
3583 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3584 },
3585
3586 /* PREFIX_0FF0 */
3587 {
3588 { Bad_Opcode },
3589 { Bad_Opcode },
3590 { Bad_Opcode },
3591 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3592 },
3593
3594 /* PREFIX_0FF7 */
3595 {
3596 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3597 { Bad_Opcode },
3598 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3599 },
3600
3601 /* PREFIX_0F38D8 */
3602 {
3603 { Bad_Opcode },
3604 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3605 },
3606
3607 /* PREFIX_0F38DC */
3608 {
3609 { Bad_Opcode },
3610 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3611 { "aesenc", { XM, EXx }, 0 },
3612 },
3613
3614 /* PREFIX_0F38DD */
3615 {
3616 { Bad_Opcode },
3617 { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3618 { "aesenclast", { XM, EXx }, 0 },
3619 },
3620
3621 /* PREFIX_0F38DE */
3622 {
3623 { Bad_Opcode },
3624 { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3625 { "aesdec", { XM, EXx }, 0 },
3626 },
3627
3628 /* PREFIX_0F38DF */
3629 {
3630 { Bad_Opcode },
3631 { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3632 { "aesdeclast", { XM, EXx }, 0 },
3633 },
3634
3635 /* PREFIX_0F38F0 */
3636 {
3637 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3638 { Bad_Opcode },
3639 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3640 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3641 },
3642
3643 /* PREFIX_0F38F1 */
3644 {
3645 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3646 { Bad_Opcode },
3647 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3648 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3649 },
3650
3651 /* PREFIX_0F38F6 */
3652 {
3653 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3654 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3655 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3656 { Bad_Opcode },
3657 },
3658
3659 /* PREFIX_0F38F8 */
3660 {
3661 { Bad_Opcode },
3662 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3663 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3664 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3665 },
3666 /* PREFIX_0F38FA */
3667 {
3668 { Bad_Opcode },
3669 { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3670 },
3671
3672 /* PREFIX_0F38FB */
3673 {
3674 { Bad_Opcode },
3675 { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3676 },
3677
3678 /* PREFIX_0F38FC */
3679 {
3680 { "aadd", { Mdq, Gdq }, 0 },
3681 { "axor", { Mdq, Gdq }, 0 },
3682 { "aand", { Mdq, Gdq }, 0 },
3683 { "aor", { Mdq, Gdq }, 0 },
3684 },
3685
3686 /* PREFIX_0F3A0F */
3687 {
3688 { Bad_Opcode },
3689 { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3690 },
3691
3692 /* PREFIX_VEX_0F10 */
3693 {
3694 { "%XEvmovupX", { XM, EXEvexXNoBcst }, 0 },
3695 { "%XEvmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3696 { "%XEvmovupX", { XM, EXEvexXNoBcst }, 0 },
3697 { "%XEvmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
3698 },
3699
3700 /* PREFIX_VEX_0F11 */
3701 {
3702 { "%XEvmovupX", { EXxS, XM }, 0 },
3703 { "%XEvmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3704 { "%XEvmovupX", { EXxS, XM }, 0 },
3705 { "%XEvmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
3706 },
3707
3708 /* PREFIX_VEX_0F12 */
3709 {
3710 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3711 { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3712 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3713 { "%XEvmov%XDdup", { XM, EXymmq }, 0 },
3714 },
3715
3716 /* PREFIX_VEX_0F16 */
3717 {
3718 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3719 { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3720 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3721 },
3722
3723 /* PREFIX_VEX_0F2A */
3724 {
3725 { Bad_Opcode },
3726 { "%XEvcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3727 { Bad_Opcode },
3728 { "%XEvcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3729 },
3730
3731 /* PREFIX_VEX_0F2C */
3732 {
3733 { Bad_Opcode },
3734 { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
3735 { Bad_Opcode },
3736 { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
3737 },
3738
3739 /* PREFIX_VEX_0F2D */
3740 {
3741 { Bad_Opcode },
3742 { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3743 { Bad_Opcode },
3744 { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3745 },
3746
3747 /* PREFIX_VEX_0F2E */
3748 {
3749 { "%XEvucomisX", { XMScalar, EXd, EXxEVexS }, 0 },
3750 { Bad_Opcode },
3751 { "%XEvucomisX", { XMScalar, EXq, EXxEVexS }, 0 },
3752 },
3753
3754 /* PREFIX_VEX_0F2F */
3755 {
3756 { "%XEvcomisX", { XMScalar, EXd, EXxEVexS }, 0 },
3757 { Bad_Opcode },
3758 { "%XEvcomisX", { XMScalar, EXq, EXxEVexS }, 0 },
3759 },
3760
3761 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3762 {
3763 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
3764 { Bad_Opcode },
3765 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
3766 },
3767
3768 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3769 {
3770 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
3771 { Bad_Opcode },
3772 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
3773 },
3774
3775 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3776 {
3777 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
3778 { Bad_Opcode },
3779 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
3780 },
3781
3782 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3783 {
3784 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
3785 { Bad_Opcode },
3786 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
3787 },
3788
3789 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3790 {
3791 { "knotw", { MaskG, MaskE }, 0 },
3792 { Bad_Opcode },
3793 { "knotb", { MaskG, MaskE }, 0 },
3794 },
3795
3796 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3797 {
3798 { "knotq", { MaskG, MaskE }, 0 },
3799 { Bad_Opcode },
3800 { "knotd", { MaskG, MaskE }, 0 },
3801 },
3802
3803 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3804 {
3805 { "korw", { MaskG, MaskVex, MaskE }, 0 },
3806 { Bad_Opcode },
3807 { "korb", { MaskG, MaskVex, MaskE }, 0 },
3808 },
3809
3810 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3811 {
3812 { "korq", { MaskG, MaskVex, MaskE }, 0 },
3813 { Bad_Opcode },
3814 { "kord", { MaskG, MaskVex, MaskE }, 0 },
3815 },
3816
3817 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3818 {
3819 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
3820 { Bad_Opcode },
3821 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
3822 },
3823
3824 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3825 {
3826 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
3827 { Bad_Opcode },
3828 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
3829 },
3830
3831 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3832 {
3833 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
3834 { Bad_Opcode },
3835 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
3836 },
3837
3838 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3839 {
3840 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
3841 { Bad_Opcode },
3842 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
3843 },
3844
3845 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3846 {
3847 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
3848 { Bad_Opcode },
3849 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
3850 },
3851
3852 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3853 {
3854 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
3855 { Bad_Opcode },
3856 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
3857 },
3858
3859 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3860 {
3861 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
3862 { Bad_Opcode },
3863 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
3864 },
3865
3866 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3867 {
3868 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
3869 },
3870
3871 /* PREFIX_VEX_0F51 */
3872 {
3873 { "%XEvsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3874 { "%XEvsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3875 { "%XEvsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3876 { "%XEvsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3877 },
3878
3879 /* PREFIX_VEX_0F52 */
3880 {
3881 { "vrsqrtps", { XM, EXx }, 0 },
3882 { "vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3883 },
3884
3885 /* PREFIX_VEX_0F53 */
3886 {
3887 { "vrcpps", { XM, EXx }, 0 },
3888 { "vrcpss", { XMScalar, VexScalar, EXd }, 0 },
3889 },
3890
3891 /* PREFIX_VEX_0F58 */
3892 {
3893 { "%XEvaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3894 { "%XEvadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3895 { "%XEvaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3896 { "%XEvadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3897 },
3898
3899 /* PREFIX_VEX_0F59 */
3900 {
3901 { "%XEvmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3902 { "%XEvmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3903 { "%XEvmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3904 { "%XEvmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3905 },
3906
3907 /* PREFIX_VEX_0F5A */
3908 {
3909 { "%XEvcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3910 { "%XEvcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3911 { "%XEvcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3912 { "%XEvcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3913 },
3914
3915 /* PREFIX_VEX_0F5B */
3916 {
3917 { "vcvtdq2ps", { XM, EXx }, 0 },
3918 { "vcvttps2dq", { XM, EXx }, 0 },
3919 { "vcvtps2dq", { XM, EXx }, 0 },
3920 },
3921
3922 /* PREFIX_VEX_0F5C */
3923 {
3924 { "%XEvsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3925 { "%XEvsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3926 { "%XEvsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3927 { "%XEvsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3928 },
3929
3930 /* PREFIX_VEX_0F5D */
3931 {
3932 { "%XEvminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3933 { "%XEvmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3934 { "%XEvminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3935 { "%XEvmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3936 },
3937
3938 /* PREFIX_VEX_0F5E */
3939 {
3940 { "%XEvdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3941 { "%XEvdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3942 { "%XEvdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3943 { "%XEvdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3944 },
3945
3946 /* PREFIX_VEX_0F5F */
3947 {
3948 { "%XEvmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3949 { "%XEvmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3950 { "%XEvmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3951 { "%XEvmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3952 },
3953
3954 /* PREFIX_VEX_0F6F */
3955 {
3956 { Bad_Opcode },
3957 { "vmovdqu", { XM, EXx }, 0 },
3958 { "vmovdqa", { XM, EXx }, 0 },
3959 },
3960
3961 /* PREFIX_VEX_0F70 */
3962 {
3963 { Bad_Opcode },
3964 { "vpshufhw", { XM, EXx, Ib }, 0 },
3965 { "vpshufd", { XM, EXx, Ib }, 0 },
3966 { "vpshuflw", { XM, EXx, Ib }, 0 },
3967 },
3968
3969 /* PREFIX_VEX_0F7C */
3970 {
3971 { Bad_Opcode },
3972 { Bad_Opcode },
3973 { "vhaddpd", { XM, Vex, EXx }, 0 },
3974 { "vhaddps", { XM, Vex, EXx }, 0 },
3975 },
3976
3977 /* PREFIX_VEX_0F7D */
3978 {
3979 { Bad_Opcode },
3980 { Bad_Opcode },
3981 { "vhsubpd", { XM, Vex, EXx }, 0 },
3982 { "vhsubps", { XM, Vex, EXx }, 0 },
3983 },
3984
3985 /* PREFIX_VEX_0F7E */
3986 {
3987 { Bad_Opcode },
3988 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3989 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3990 },
3991
3992 /* PREFIX_VEX_0F7F */
3993 {
3994 { Bad_Opcode },
3995 { "vmovdqu", { EXxS, XM }, 0 },
3996 { "vmovdqa", { EXxS, XM }, 0 },
3997 },
3998
3999 /* PREFIX_VEX_0F90_L_0_W_0 */
4000 {
4001 { "kmovw", { MaskG, MaskE }, 0 },
4002 { Bad_Opcode },
4003 { "kmovb", { MaskG, MaskBDE }, 0 },
4004 },
4005
4006 /* PREFIX_VEX_0F90_L_0_W_1 */
4007 {
4008 { "kmovq", { MaskG, MaskE }, 0 },
4009 { Bad_Opcode },
4010 { "kmovd", { MaskG, MaskBDE }, 0 },
4011 },
4012
4013 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
4014 {
4015 { "kmovw", { Ew, MaskG }, 0 },
4016 { Bad_Opcode },
4017 { "kmovb", { Eb, MaskG }, 0 },
4018 },
4019
4020 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
4021 {
4022 { "kmovq", { Eq, MaskG }, 0 },
4023 { Bad_Opcode },
4024 { "kmovd", { Ed, MaskG }, 0 },
4025 },
4026
4027 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
4028 {
4029 { "kmovw", { MaskG, Edq }, 0 },
4030 { Bad_Opcode },
4031 { "kmovb", { MaskG, Edq }, 0 },
4032 { "kmovd", { MaskG, Edq }, 0 },
4033 },
4034
4035 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
4036 {
4037 { Bad_Opcode },
4038 { Bad_Opcode },
4039 { Bad_Opcode },
4040 { "kmovK", { MaskG, Edq }, 0 },
4041 },
4042
4043 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
4044 {
4045 { "kmovw", { Gdq, MaskE }, 0 },
4046 { Bad_Opcode },
4047 { "kmovb", { Gdq, MaskE }, 0 },
4048 { "kmovd", { Gdq, MaskE }, 0 },
4049 },
4050
4051 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
4052 {
4053 { Bad_Opcode },
4054 { Bad_Opcode },
4055 { Bad_Opcode },
4056 { "kmovK", { Gdq, MaskE }, 0 },
4057 },
4058
4059 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
4060 {
4061 { "kortestw", { MaskG, MaskE }, 0 },
4062 { Bad_Opcode },
4063 { "kortestb", { MaskG, MaskE }, 0 },
4064 },
4065
4066 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4067 {
4068 { "kortestq", { MaskG, MaskE }, 0 },
4069 { Bad_Opcode },
4070 { "kortestd", { MaskG, MaskE }, 0 },
4071 },
4072
4073 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4074 {
4075 { "ktestw", { MaskG, MaskE }, 0 },
4076 { Bad_Opcode },
4077 { "ktestb", { MaskG, MaskE }, 0 },
4078 },
4079
4080 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4081 {
4082 { "ktestq", { MaskG, MaskE }, 0 },
4083 { Bad_Opcode },
4084 { "ktestd", { MaskG, MaskE }, 0 },
4085 },
4086
4087 /* PREFIX_VEX_0FC2 */
4088 {
4089 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
4090 { "vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
4091 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
4092 { "vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
4093 },
4094
4095 /* PREFIX_VEX_0FD0 */
4096 {
4097 { Bad_Opcode },
4098 { Bad_Opcode },
4099 { "vaddsubpd", { XM, Vex, EXx }, 0 },
4100 { "vaddsubps", { XM, Vex, EXx }, 0 },
4101 },
4102
4103 /* PREFIX_VEX_0FE6 */
4104 {
4105 { Bad_Opcode },
4106 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
4107 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
4108 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
4109 },
4110
4111 /* PREFIX_VEX_0FF0 */
4112 {
4113 { Bad_Opcode },
4114 { Bad_Opcode },
4115 { Bad_Opcode },
4116 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4117 },
4118
4119 /* PREFIX_VEX_0F3849_X86_64 */
4120 {
4121 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4122 { Bad_Opcode },
4123 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4124 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4125 },
4126
4127 /* PREFIX_VEX_0F384B_X86_64 */
4128 {
4129 { Bad_Opcode },
4130 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4131 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4132 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4133 },
4134
4135 /* PREFIX_VEX_0F3850_W_0 */
4136 {
4137 { "vpdpbuud", { XM, Vex, EXx }, 0 },
4138 { "vpdpbsud", { XM, Vex, EXx }, 0 },
4139 { "%XVvpdpbusd", { XM, Vex, EXx }, 0 },
4140 { "vpdpbssd", { XM, Vex, EXx }, 0 },
4141 },
4142
4143 /* PREFIX_VEX_0F3851_W_0 */
4144 {
4145 { "vpdpbuuds", { XM, Vex, EXx }, 0 },
4146 { "vpdpbsuds", { XM, Vex, EXx }, 0 },
4147 { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
4148 { "vpdpbssds", { XM, Vex, EXx }, 0 },
4149 },
4150 /* PREFIX_VEX_0F385C_X86_64 */
4151 {
4152 { Bad_Opcode },
4153 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4154 { Bad_Opcode },
4155 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_3) },
4156 },
4157
4158 /* PREFIX_VEX_0F385E_X86_64 */
4159 {
4160 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4161 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4162 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4163 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4164 },
4165
4166 /* PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0 */
4167 {
4168 { "tcmmrlfp16ps", { TMM, EXtmm, VexTmm }, 0 },
4169 { Bad_Opcode },
4170 { "tcmmimfp16ps", { TMM, EXtmm, VexTmm }, 0 },
4171 },
4172
4173 /* PREFIX_VEX_0F3872 */
4174 {
4175 { Bad_Opcode },
4176 { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4177 },
4178
4179 /* PREFIX_VEX_0F38B0_W_0 */
4180 {
4181 { "vcvtneoph2ps", { XM, Mx }, 0 },
4182 { "vcvtneebf162ps", { XM, Mx }, 0 },
4183 { "vcvtneeph2ps", { XM, Mx }, 0 },
4184 { "vcvtneobf162ps", { XM, Mx }, 0 },
4185 },
4186
4187 /* PREFIX_VEX_0F38B1_W_0 */
4188 {
4189 { Bad_Opcode },
4190 { "vbcstnebf162ps", { XM, Mw }, 0 },
4191 { "vbcstnesh2ps", { XM, Mw }, 0 },
4192 },
4193
4194 /* PREFIX_VEX_0F38F5_L_0 */
4195 {
4196 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
4197 { "pextS", { Gdq, VexGdq, Edq }, 0 },
4198 { Bad_Opcode },
4199 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
4200 },
4201
4202 /* PREFIX_VEX_0F38F6_L_0 */
4203 {
4204 { Bad_Opcode },
4205 { Bad_Opcode },
4206 { Bad_Opcode },
4207 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
4208 },
4209
4210 /* PREFIX_VEX_0F38F7_L_0 */
4211 {
4212 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
4213 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
4214 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
4215 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
4216 },
4217
4218 /* PREFIX_VEX_0F3AF0_L_0 */
4219 {
4220 { Bad_Opcode },
4221 { Bad_Opcode },
4222 { Bad_Opcode },
4223 { "rorxS", { Gdq, Edq, Ib }, 0 },
4224 },
4225
4226 #include "i386-dis-evex-prefix.h"
4227 };
4228
4229 static const struct dis386 x86_64_table[][2] = {
4230 /* X86_64_06 */
4231 {
4232 { "pushP", { es }, 0 },
4233 },
4234
4235 /* X86_64_07 */
4236 {
4237 { "popP", { es }, 0 },
4238 },
4239
4240 /* X86_64_0E */
4241 {
4242 { "pushP", { cs }, 0 },
4243 },
4244
4245 /* X86_64_16 */
4246 {
4247 { "pushP", { ss }, 0 },
4248 },
4249
4250 /* X86_64_17 */
4251 {
4252 { "popP", { ss }, 0 },
4253 },
4254
4255 /* X86_64_1E */
4256 {
4257 { "pushP", { ds }, 0 },
4258 },
4259
4260 /* X86_64_1F */
4261 {
4262 { "popP", { ds }, 0 },
4263 },
4264
4265 /* X86_64_27 */
4266 {
4267 { "daa", { XX }, 0 },
4268 },
4269
4270 /* X86_64_2F */
4271 {
4272 { "das", { XX }, 0 },
4273 },
4274
4275 /* X86_64_37 */
4276 {
4277 { "aaa", { XX }, 0 },
4278 },
4279
4280 /* X86_64_3F */
4281 {
4282 { "aas", { XX }, 0 },
4283 },
4284
4285 /* X86_64_60 */
4286 {
4287 { "pushaP", { XX }, 0 },
4288 },
4289
4290 /* X86_64_61 */
4291 {
4292 { "popaP", { XX }, 0 },
4293 },
4294
4295 /* X86_64_62 */
4296 {
4297 { MOD_TABLE (MOD_62_32BIT) },
4298 { EVEX_TABLE (EVEX_0F) },
4299 },
4300
4301 /* X86_64_63 */
4302 {
4303 { "arpl", { Ew, Gw }, 0 },
4304 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4305 },
4306
4307 /* X86_64_6D */
4308 {
4309 { "ins{R|}", { Yzr, indirDX }, 0 },
4310 { "ins{G|}", { Yzr, indirDX }, 0 },
4311 },
4312
4313 /* X86_64_6F */
4314 {
4315 { "outs{R|}", { indirDXr, Xz }, 0 },
4316 { "outs{G|}", { indirDXr, Xz }, 0 },
4317 },
4318
4319 /* X86_64_82 */
4320 {
4321 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4322 { REG_TABLE (REG_80) },
4323 },
4324
4325 /* X86_64_9A */
4326 {
4327 { "{l|}call{P|}", { Ap }, 0 },
4328 },
4329
4330 /* X86_64_C2 */
4331 {
4332 { "retP", { Iw, BND }, 0 },
4333 { "ret@", { Iw, BND }, 0 },
4334 },
4335
4336 /* X86_64_C3 */
4337 {
4338 { "retP", { BND }, 0 },
4339 { "ret@", { BND }, 0 },
4340 },
4341
4342 /* X86_64_C4 */
4343 {
4344 { MOD_TABLE (MOD_C4_32BIT) },
4345 { VEX_C4_TABLE (VEX_0F) },
4346 },
4347
4348 /* X86_64_C5 */
4349 {
4350 { MOD_TABLE (MOD_C5_32BIT) },
4351 { VEX_C5_TABLE (VEX_0F) },
4352 },
4353
4354 /* X86_64_CE */
4355 {
4356 { "into", { XX }, 0 },
4357 },
4358
4359 /* X86_64_D4 */
4360 {
4361 { "aam", { Ib }, 0 },
4362 },
4363
4364 /* X86_64_D5 */
4365 {
4366 { "aad", { Ib }, 0 },
4367 },
4368
4369 /* X86_64_E8 */
4370 {
4371 { "callP", { Jv, BND }, 0 },
4372 { "call@", { Jv, BND }, 0 }
4373 },
4374
4375 /* X86_64_E9 */
4376 {
4377 { "jmpP", { Jv, BND }, 0 },
4378 { "jmp@", { Jv, BND }, 0 }
4379 },
4380
4381 /* X86_64_EA */
4382 {
4383 { "{l|}jmp{P|}", { Ap }, 0 },
4384 },
4385
4386 /* X86_64_0F01_REG_0 */
4387 {
4388 { "sgdt{Q|Q}", { M }, 0 },
4389 { "sgdt", { M }, 0 },
4390 },
4391
4392 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4393 {
4394 { Bad_Opcode },
4395 { "wrmsrlist", { Skip_MODRM }, 0 },
4396 },
4397
4398 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4399 {
4400 { Bad_Opcode },
4401 { "rdmsrlist", { Skip_MODRM }, 0 },
4402 },
4403
4404 /* X86_64_0F01_REG_1 */
4405 {
4406 { "sidt{Q|Q}", { M }, 0 },
4407 { "sidt", { M }, 0 },
4408 },
4409
4410 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4411 {
4412 { Bad_Opcode },
4413 { "seamret", { Skip_MODRM }, 0 },
4414 },
4415
4416 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4417 {
4418 { Bad_Opcode },
4419 { "seamops", { Skip_MODRM }, 0 },
4420 },
4421
4422 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4423 {
4424 { Bad_Opcode },
4425 { "seamcall", { Skip_MODRM }, 0 },
4426 },
4427
4428 /* X86_64_0F01_REG_2 */
4429 {
4430 { "lgdt{Q|Q}", { M }, 0 },
4431 { "lgdt", { M }, 0 },
4432 },
4433
4434 /* X86_64_0F01_REG_3 */
4435 {
4436 { "lidt{Q|Q}", { M }, 0 },
4437 { "lidt", { M }, 0 },
4438 },
4439
4440 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4441 {
4442 { Bad_Opcode },
4443 { "uiret", { Skip_MODRM }, 0 },
4444 },
4445
4446 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4447 {
4448 { Bad_Opcode },
4449 { "testui", { Skip_MODRM }, 0 },
4450 },
4451
4452 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4453 {
4454 { Bad_Opcode },
4455 { "clui", { Skip_MODRM }, 0 },
4456 },
4457
4458 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4459 {
4460 { Bad_Opcode },
4461 { "stui", { Skip_MODRM }, 0 },
4462 },
4463
4464 /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4465 {
4466 { Bad_Opcode },
4467 { "rmpquery", { Skip_MODRM }, 0 },
4468 },
4469
4470 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4471 {
4472 { Bad_Opcode },
4473 { "rmpadjust", { Skip_MODRM }, 0 },
4474 },
4475
4476 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4477 {
4478 { Bad_Opcode },
4479 { "rmpupdate", { Skip_MODRM }, 0 },
4480 },
4481
4482 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4483 {
4484 { Bad_Opcode },
4485 { "psmash", { Skip_MODRM }, 0 },
4486 },
4487
4488 /* X86_64_0F18_REG_6_MOD_0 */
4489 {
4490 { "nopQ", { Ev }, 0 },
4491 { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4492 },
4493
4494 /* X86_64_0F18_REG_7_MOD_0 */
4495 {
4496 { "nopQ", { Ev }, 0 },
4497 { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4498 },
4499
4500 {
4501 /* X86_64_0F24 */
4502 { "movZ", { Em, Td }, 0 },
4503 },
4504
4505 {
4506 /* X86_64_0F26 */
4507 { "movZ", { Td, Em }, 0 },
4508 },
4509
4510 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4511 {
4512 { Bad_Opcode },
4513 { "senduipi", { Eq }, 0 },
4514 },
4515
4516 /* X86_64_VEX_0F3849 */
4517 {
4518 { Bad_Opcode },
4519 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4520 },
4521
4522 /* X86_64_VEX_0F384B */
4523 {
4524 { Bad_Opcode },
4525 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4526 },
4527
4528 /* X86_64_VEX_0F385C */
4529 {
4530 { Bad_Opcode },
4531 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4532 },
4533
4534 /* X86_64_VEX_0F385E */
4535 {
4536 { Bad_Opcode },
4537 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4538 },
4539
4540 /* X86_64_VEX_0F386C */
4541 {
4542 { Bad_Opcode },
4543 { VEX_W_TABLE (VEX_W_0F386C_X86_64) },
4544 },
4545
4546 /* X86_64_VEX_0F38E0 */
4547 {
4548 { Bad_Opcode },
4549 { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4550 },
4551
4552 /* X86_64_VEX_0F38E1 */
4553 {
4554 { Bad_Opcode },
4555 { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4556 },
4557
4558 /* X86_64_VEX_0F38E2 */
4559 {
4560 { Bad_Opcode },
4561 { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4562 },
4563
4564 /* X86_64_VEX_0F38E3 */
4565 {
4566 { Bad_Opcode },
4567 { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4568 },
4569
4570 /* X86_64_VEX_0F38E4 */
4571 {
4572 { Bad_Opcode },
4573 { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4574 },
4575
4576 /* X86_64_VEX_0F38E5 */
4577 {
4578 { Bad_Opcode },
4579 { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4580 },
4581
4582 /* X86_64_VEX_0F38E6 */
4583 {
4584 { Bad_Opcode },
4585 { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4586 },
4587
4588 /* X86_64_VEX_0F38E7 */
4589 {
4590 { Bad_Opcode },
4591 { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4592 },
4593
4594 /* X86_64_VEX_0F38E8 */
4595 {
4596 { Bad_Opcode },
4597 { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4598 },
4599
4600 /* X86_64_VEX_0F38E9 */
4601 {
4602 { Bad_Opcode },
4603 { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4604 },
4605
4606 /* X86_64_VEX_0F38EA */
4607 {
4608 { Bad_Opcode },
4609 { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4610 },
4611
4612 /* X86_64_VEX_0F38EB */
4613 {
4614 { Bad_Opcode },
4615 { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4616 },
4617
4618 /* X86_64_VEX_0F38EC */
4619 {
4620 { Bad_Opcode },
4621 { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4622 },
4623
4624 /* X86_64_VEX_0F38ED */
4625 {
4626 { Bad_Opcode },
4627 { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4628 },
4629
4630 /* X86_64_VEX_0F38EE */
4631 {
4632 { Bad_Opcode },
4633 { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4634 },
4635
4636 /* X86_64_VEX_0F38EF */
4637 {
4638 { Bad_Opcode },
4639 { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4640 },
4641 };
4642
4643 static const struct dis386 three_byte_table[][256] = {
4644
4645 /* THREE_BYTE_0F38 */
4646 {
4647 /* 00 */
4648 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4649 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4650 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4651 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4652 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4653 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4654 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4655 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4656 /* 08 */
4657 { "psignb", { MX, EM }, PREFIX_OPCODE },
4658 { "psignw", { MX, EM }, PREFIX_OPCODE },
4659 { "psignd", { MX, EM }, PREFIX_OPCODE },
4660 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { Bad_Opcode },
4665 /* 10 */
4666 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4667 { Bad_Opcode },
4668 { Bad_Opcode },
4669 { Bad_Opcode },
4670 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4671 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4672 { Bad_Opcode },
4673 { "ptest", { XM, EXx }, PREFIX_DATA },
4674 /* 18 */
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4680 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4681 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4682 { Bad_Opcode },
4683 /* 20 */
4684 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4685 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4686 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4687 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4688 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4689 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 /* 28 */
4693 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4694 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4695 { MOD_TABLE (MOD_0F382A) },
4696 { "packusdw", { XM, EXx }, PREFIX_DATA },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 /* 30 */
4702 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4703 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4704 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4705 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4706 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4707 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4708 { Bad_Opcode },
4709 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4710 /* 38 */
4711 { "pminsb", { XM, EXx }, PREFIX_DATA },
4712 { "pminsd", { XM, EXx }, PREFIX_DATA },
4713 { "pminuw", { XM, EXx }, PREFIX_DATA },
4714 { "pminud", { XM, EXx }, PREFIX_DATA },
4715 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4716 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4717 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4718 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4719 /* 40 */
4720 { "pmulld", { XM, EXx }, PREFIX_DATA },
4721 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { Bad_Opcode },
4728 /* 48 */
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 /* 50 */
4738 { Bad_Opcode },
4739 { Bad_Opcode },
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 /* 58 */
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 /* 60 */
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 /* 68 */
4765 { Bad_Opcode },
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 /* 70 */
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 /* 78 */
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 /* 80 */
4792 { "invept", { Gm, Mo }, PREFIX_DATA },
4793 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4794 { "invpcid", { Gm, M }, PREFIX_DATA },
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 /* 88 */
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 /* 90 */
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 /* 98 */
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 /* a0 */
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 /* a8 */
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 /* b0 */
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 /* b8 */
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 /* c0 */
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 /* c8 */
4873 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4874 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4875 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4876 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4877 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4878 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4879 { Bad_Opcode },
4880 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4881 /* d0 */
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 /* d8 */
4891 { PREFIX_TABLE (PREFIX_0F38D8) },
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 { "aesimc", { XM, EXx }, PREFIX_DATA },
4895 { PREFIX_TABLE (PREFIX_0F38DC) },
4896 { PREFIX_TABLE (PREFIX_0F38DD) },
4897 { PREFIX_TABLE (PREFIX_0F38DE) },
4898 { PREFIX_TABLE (PREFIX_0F38DF) },
4899 /* e0 */
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 /* e8 */
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 { Bad_Opcode },
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 /* f0 */
4918 { PREFIX_TABLE (PREFIX_0F38F0) },
4919 { PREFIX_TABLE (PREFIX_0F38F1) },
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 { Bad_Opcode },
4923 { MOD_TABLE (MOD_0F38F5) },
4924 { PREFIX_TABLE (PREFIX_0F38F6) },
4925 { Bad_Opcode },
4926 /* f8 */
4927 { PREFIX_TABLE (PREFIX_0F38F8) },
4928 { MOD_TABLE (MOD_0F38F9) },
4929 { PREFIX_TABLE (PREFIX_0F38FA) },
4930 { PREFIX_TABLE (PREFIX_0F38FB) },
4931 { PREFIX_TABLE (PREFIX_0F38FC) },
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 },
4936 /* THREE_BYTE_0F3A */
4937 {
4938 /* 00 */
4939 { Bad_Opcode },
4940 { Bad_Opcode },
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 /* 08 */
4948 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4949 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4950 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4951 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4952 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4953 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4954 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4955 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4956 /* 10 */
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4962 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4963 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4964 { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4965 /* 18 */
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 /* 20 */
4975 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4976 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4977 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 /* 28 */
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 /* 30 */
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 /* 38 */
5002 { Bad_Opcode },
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 /* 40 */
5011 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
5012 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
5013 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
5014 { Bad_Opcode },
5015 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 /* 48 */
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 /* 50 */
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 /* 58 */
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 /* 60 */
5047 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5048 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5049 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
5050 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 /* 68 */
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 /* 70 */
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 /* 78 */
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 /* 80 */
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 /* 88 */
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 /* 90 */
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 /* 98 */
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 /* a0 */
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 /* a8 */
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 /* b0 */
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 /* b8 */
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 /* c0 */
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 /* c8 */
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5169 { Bad_Opcode },
5170 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5171 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5172 /* d0 */
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 /* d8 */
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5190 /* e0 */
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 /* e8 */
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 /* f0 */
5209 { PREFIX_TABLE (PREFIX_0F3A0F) },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 { Bad_Opcode },
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 /* f8 */
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 { Bad_Opcode },
5223 { Bad_Opcode },
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 },
5227 };
5228
5229 static const struct dis386 xop_table[][256] = {
5230 /* XOP_08 */
5231 {
5232 /* 00 */
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { Bad_Opcode },
5241 /* 08 */
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 { Bad_Opcode },
5250 /* 10 */
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 /* 18 */
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 /* 20 */
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 /* 28 */
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 /* 30 */
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 /* 38 */
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 /* 40 */
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { Bad_Opcode },
5313 /* 48 */
5314 { Bad_Opcode },
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 /* 50 */
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { Bad_Opcode },
5331 /* 58 */
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 /* 60 */
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 /* 68 */
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 /* 70 */
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 /* 78 */
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 /* 80 */
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5383 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5384 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5385 /* 88 */
5386 { Bad_Opcode },
5387 { Bad_Opcode },
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5393 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5394 /* 90 */
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5401 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5402 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5403 /* 98 */
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5411 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5412 /* a0 */
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5416 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5420 { Bad_Opcode },
5421 /* a8 */
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 /* b0 */
5431 { Bad_Opcode },
5432 { Bad_Opcode },
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5438 { Bad_Opcode },
5439 /* b8 */
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { Bad_Opcode },
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 /* c0 */
5449 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5450 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5451 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5452 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 /* c8 */
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 { Bad_Opcode },
5461 { Bad_Opcode },
5462 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5463 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5464 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5465 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5466 /* d0 */
5467 { Bad_Opcode },
5468 { Bad_Opcode },
5469 { Bad_Opcode },
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 /* d8 */
5476 { Bad_Opcode },
5477 { Bad_Opcode },
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 /* e0 */
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 /* e8 */
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5499 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5500 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5501 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5502 /* f0 */
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 /* f8 */
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 },
5521 /* XOP_09 */
5522 {
5523 /* 00 */
5524 { Bad_Opcode },
5525 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5526 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 /* 08 */
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 /* 10 */
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { MOD_TABLE (MOD_XOP_09_12) },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 /* 18 */
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 /* 20 */
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 /* 28 */
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 /* 30 */
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 /* 38 */
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 /* 40 */
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 /* 48 */
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 /* 50 */
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 /* 58 */
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 /* 60 */
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 /* 68 */
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 /* 70 */
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 /* 78 */
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 /* 80 */
5668 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5669 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5670 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5671 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 /* 88 */
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 /* 90 */
5686 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5687 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5688 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5689 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5690 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5691 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5692 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5693 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5694 /* 98 */
5695 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5696 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5697 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5698 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 /* a0 */
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 /* a8 */
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 /* b0 */
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 /* b8 */
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 /* c0 */
5740 { Bad_Opcode },
5741 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5742 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5743 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5747 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5748 /* c8 */
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 /* d0 */
5758 { Bad_Opcode },
5759 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5760 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5761 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5765 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5766 /* d8 */
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 /* e0 */
5776 { Bad_Opcode },
5777 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5778 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5779 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 /* e8 */
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 /* f0 */
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 { Bad_Opcode },
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 /* f8 */
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 },
5812 /* XOP_0A */
5813 {
5814 /* 00 */
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 /* 08 */
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 /* 10 */
5833 { "bextrS", { Gdq, Edq, Id }, 0 },
5834 { Bad_Opcode },
5835 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 /* 18 */
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 /* 20 */
5851 { Bad_Opcode },
5852 { Bad_Opcode },
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 /* 28 */
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 /* 30 */
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 /* 38 */
5878 { Bad_Opcode },
5879 { Bad_Opcode },
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 /* 40 */
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 /* 48 */
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 { Bad_Opcode },
5904 /* 50 */
5905 { Bad_Opcode },
5906 { Bad_Opcode },
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 /* 58 */
5914 { Bad_Opcode },
5915 { Bad_Opcode },
5916 { Bad_Opcode },
5917 { Bad_Opcode },
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 /* 60 */
5923 { Bad_Opcode },
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 { Bad_Opcode },
5931 /* 68 */
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 { Bad_Opcode },
5940 /* 70 */
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 /* 78 */
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 /* 80 */
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 { Bad_Opcode },
5967 /* 88 */
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 { Bad_Opcode },
5971 { Bad_Opcode },
5972 { Bad_Opcode },
5973 { Bad_Opcode },
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 /* 90 */
5977 { Bad_Opcode },
5978 { Bad_Opcode },
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 /* 98 */
5986 { Bad_Opcode },
5987 { Bad_Opcode },
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 { Bad_Opcode },
5991 { Bad_Opcode },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 /* a0 */
5995 { Bad_Opcode },
5996 { Bad_Opcode },
5997 { Bad_Opcode },
5998 { Bad_Opcode },
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 /* a8 */
6004 { Bad_Opcode },
6005 { Bad_Opcode },
6006 { Bad_Opcode },
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 /* b0 */
6013 { Bad_Opcode },
6014 { Bad_Opcode },
6015 { Bad_Opcode },
6016 { Bad_Opcode },
6017 { Bad_Opcode },
6018 { Bad_Opcode },
6019 { Bad_Opcode },
6020 { Bad_Opcode },
6021 /* b8 */
6022 { Bad_Opcode },
6023 { Bad_Opcode },
6024 { Bad_Opcode },
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 { Bad_Opcode },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 /* c0 */
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 { Bad_Opcode },
6035 { Bad_Opcode },
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 /* c8 */
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 { Bad_Opcode },
6047 { Bad_Opcode },
6048 /* d0 */
6049 { Bad_Opcode },
6050 { Bad_Opcode },
6051 { Bad_Opcode },
6052 { Bad_Opcode },
6053 { Bad_Opcode },
6054 { Bad_Opcode },
6055 { Bad_Opcode },
6056 { Bad_Opcode },
6057 /* d8 */
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 { Bad_Opcode },
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 /* e0 */
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 { Bad_Opcode },
6072 { Bad_Opcode },
6073 { Bad_Opcode },
6074 { Bad_Opcode },
6075 /* e8 */
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { Bad_Opcode },
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 { Bad_Opcode },
6082 { Bad_Opcode },
6083 { Bad_Opcode },
6084 /* f0 */
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 { Bad_Opcode },
6091 { Bad_Opcode },
6092 { Bad_Opcode },
6093 /* f8 */
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 { Bad_Opcode },
6099 { Bad_Opcode },
6100 { Bad_Opcode },
6101 { Bad_Opcode },
6102 },
6103 };
6104
6105 static const struct dis386 vex_table[][256] = {
6106 /* VEX_0F */
6107 {
6108 /* 00 */
6109 { Bad_Opcode },
6110 { Bad_Opcode },
6111 { Bad_Opcode },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { Bad_Opcode },
6115 { Bad_Opcode },
6116 { Bad_Opcode },
6117 /* 08 */
6118 { Bad_Opcode },
6119 { Bad_Opcode },
6120 { Bad_Opcode },
6121 { Bad_Opcode },
6122 { Bad_Opcode },
6123 { Bad_Opcode },
6124 { Bad_Opcode },
6125 { Bad_Opcode },
6126 /* 10 */
6127 { PREFIX_TABLE (PREFIX_VEX_0F10) },
6128 { PREFIX_TABLE (PREFIX_VEX_0F11) },
6129 { PREFIX_TABLE (PREFIX_VEX_0F12) },
6130 { MOD_TABLE (MOD_VEX_0F13) },
6131 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6132 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6133 { PREFIX_TABLE (PREFIX_VEX_0F16) },
6134 { MOD_TABLE (MOD_VEX_0F17) },
6135 /* 18 */
6136 { Bad_Opcode },
6137 { Bad_Opcode },
6138 { Bad_Opcode },
6139 { Bad_Opcode },
6140 { Bad_Opcode },
6141 { Bad_Opcode },
6142 { Bad_Opcode },
6143 { Bad_Opcode },
6144 /* 20 */
6145 { Bad_Opcode },
6146 { Bad_Opcode },
6147 { Bad_Opcode },
6148 { Bad_Opcode },
6149 { Bad_Opcode },
6150 { Bad_Opcode },
6151 { Bad_Opcode },
6152 { Bad_Opcode },
6153 /* 28 */
6154 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
6155 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
6156 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6157 { MOD_TABLE (MOD_VEX_0F2B) },
6158 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6159 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6160 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
6161 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
6162 /* 30 */
6163 { Bad_Opcode },
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { Bad_Opcode },
6169 { Bad_Opcode },
6170 { Bad_Opcode },
6171 /* 38 */
6172 { Bad_Opcode },
6173 { Bad_Opcode },
6174 { Bad_Opcode },
6175 { Bad_Opcode },
6176 { Bad_Opcode },
6177 { Bad_Opcode },
6178 { Bad_Opcode },
6179 { Bad_Opcode },
6180 /* 40 */
6181 { Bad_Opcode },
6182 { VEX_LEN_TABLE (VEX_LEN_0F41) },
6183 { VEX_LEN_TABLE (VEX_LEN_0F42) },
6184 { Bad_Opcode },
6185 { VEX_LEN_TABLE (VEX_LEN_0F44) },
6186 { VEX_LEN_TABLE (VEX_LEN_0F45) },
6187 { VEX_LEN_TABLE (VEX_LEN_0F46) },
6188 { VEX_LEN_TABLE (VEX_LEN_0F47) },
6189 /* 48 */
6190 { Bad_Opcode },
6191 { Bad_Opcode },
6192 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6193 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6194 { Bad_Opcode },
6195 { Bad_Opcode },
6196 { Bad_Opcode },
6197 { Bad_Opcode },
6198 /* 50 */
6199 { MOD_TABLE (MOD_VEX_0F50) },
6200 { PREFIX_TABLE (PREFIX_VEX_0F51) },
6201 { PREFIX_TABLE (PREFIX_VEX_0F52) },
6202 { PREFIX_TABLE (PREFIX_VEX_0F53) },
6203 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6204 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6205 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6206 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6207 /* 58 */
6208 { PREFIX_TABLE (PREFIX_VEX_0F58) },
6209 { PREFIX_TABLE (PREFIX_VEX_0F59) },
6210 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
6211 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
6212 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
6213 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
6214 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
6215 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
6216 /* 60 */
6217 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6218 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6219 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6220 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6221 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6222 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6223 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6224 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6225 /* 68 */
6226 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6227 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6228 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6229 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6230 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6231 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6232 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6233 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6234 /* 70 */
6235 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6236 { MOD_TABLE (MOD_VEX_0F71) },
6237 { MOD_TABLE (MOD_VEX_0F72) },
6238 { MOD_TABLE (MOD_VEX_0F73) },
6239 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6240 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6241 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6242 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6243 /* 78 */
6244 { Bad_Opcode },
6245 { Bad_Opcode },
6246 { Bad_Opcode },
6247 { Bad_Opcode },
6248 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6249 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6250 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6251 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6252 /* 80 */
6253 { Bad_Opcode },
6254 { Bad_Opcode },
6255 { Bad_Opcode },
6256 { Bad_Opcode },
6257 { Bad_Opcode },
6258 { Bad_Opcode },
6259 { Bad_Opcode },
6260 { Bad_Opcode },
6261 /* 88 */
6262 { Bad_Opcode },
6263 { Bad_Opcode },
6264 { Bad_Opcode },
6265 { Bad_Opcode },
6266 { Bad_Opcode },
6267 { Bad_Opcode },
6268 { Bad_Opcode },
6269 { Bad_Opcode },
6270 /* 90 */
6271 { VEX_LEN_TABLE (VEX_LEN_0F90) },
6272 { VEX_LEN_TABLE (VEX_LEN_0F91) },
6273 { VEX_LEN_TABLE (VEX_LEN_0F92) },
6274 { VEX_LEN_TABLE (VEX_LEN_0F93) },
6275 { Bad_Opcode },
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { Bad_Opcode },
6279 /* 98 */
6280 { VEX_LEN_TABLE (VEX_LEN_0F98) },
6281 { VEX_LEN_TABLE (VEX_LEN_0F99) },
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 /* a0 */
6289 { Bad_Opcode },
6290 { Bad_Opcode },
6291 { Bad_Opcode },
6292 { Bad_Opcode },
6293 { Bad_Opcode },
6294 { Bad_Opcode },
6295 { Bad_Opcode },
6296 { Bad_Opcode },
6297 /* a8 */
6298 { Bad_Opcode },
6299 { Bad_Opcode },
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 { Bad_Opcode },
6303 { Bad_Opcode },
6304 { REG_TABLE (REG_VEX_0FAE) },
6305 { Bad_Opcode },
6306 /* b0 */
6307 { Bad_Opcode },
6308 { Bad_Opcode },
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 { Bad_Opcode },
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 { Bad_Opcode },
6315 /* b8 */
6316 { Bad_Opcode },
6317 { Bad_Opcode },
6318 { Bad_Opcode },
6319 { Bad_Opcode },
6320 { Bad_Opcode },
6321 { Bad_Opcode },
6322 { Bad_Opcode },
6323 { Bad_Opcode },
6324 /* c0 */
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6328 { Bad_Opcode },
6329 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6330 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6331 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6332 { Bad_Opcode },
6333 /* c8 */
6334 { Bad_Opcode },
6335 { Bad_Opcode },
6336 { Bad_Opcode },
6337 { Bad_Opcode },
6338 { Bad_Opcode },
6339 { Bad_Opcode },
6340 { Bad_Opcode },
6341 { Bad_Opcode },
6342 /* d0 */
6343 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6344 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6345 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6346 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6347 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6348 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6349 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6350 { MOD_TABLE (MOD_VEX_0FD7) },
6351 /* d8 */
6352 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6353 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6354 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6355 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6356 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6357 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6358 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6359 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6360 /* e0 */
6361 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6362 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6363 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6364 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6365 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6366 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6367 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6368 { MOD_TABLE (MOD_VEX_0FE7) },
6369 /* e8 */
6370 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6371 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6372 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6373 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6374 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6375 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6376 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6377 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6378 /* f0 */
6379 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6380 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6381 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6382 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6383 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6384 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6385 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6386 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6387 /* f8 */
6388 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6389 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6390 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6391 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6392 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6393 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6394 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6395 { Bad_Opcode },
6396 },
6397 /* VEX_0F38 */
6398 {
6399 /* 00 */
6400 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6401 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6402 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6403 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6404 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6405 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6406 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6407 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6408 /* 08 */
6409 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6410 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6411 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6412 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6413 { VEX_W_TABLE (VEX_W_0F380C) },
6414 { VEX_W_TABLE (VEX_W_0F380D) },
6415 { VEX_W_TABLE (VEX_W_0F380E) },
6416 { VEX_W_TABLE (VEX_W_0F380F) },
6417 /* 10 */
6418 { Bad_Opcode },
6419 { Bad_Opcode },
6420 { Bad_Opcode },
6421 { VEX_W_TABLE (VEX_W_0F3813) },
6422 { Bad_Opcode },
6423 { Bad_Opcode },
6424 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6425 { "vptest", { XM, EXx }, PREFIX_DATA },
6426 /* 18 */
6427 { VEX_W_TABLE (VEX_W_0F3818) },
6428 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6429 { MOD_TABLE (MOD_VEX_0F381A) },
6430 { Bad_Opcode },
6431 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6432 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6433 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6434 { Bad_Opcode },
6435 /* 20 */
6436 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6437 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6438 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6439 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6440 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6441 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6442 { Bad_Opcode },
6443 { Bad_Opcode },
6444 /* 28 */
6445 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6446 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6447 { MOD_TABLE (MOD_VEX_0F382A) },
6448 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6449 { MOD_TABLE (MOD_VEX_0F382C) },
6450 { MOD_TABLE (MOD_VEX_0F382D) },
6451 { MOD_TABLE (MOD_VEX_0F382E) },
6452 { MOD_TABLE (MOD_VEX_0F382F) },
6453 /* 30 */
6454 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6455 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6456 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6457 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6458 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6459 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6460 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6461 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6462 /* 38 */
6463 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6464 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6465 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6466 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6467 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6468 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6469 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6470 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6471 /* 40 */
6472 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6473 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6478 { VEX_W_TABLE (VEX_W_0F3846) },
6479 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6480 /* 48 */
6481 { Bad_Opcode },
6482 { X86_64_TABLE (X86_64_VEX_0F3849) },
6483 { Bad_Opcode },
6484 { X86_64_TABLE (X86_64_VEX_0F384B) },
6485 { Bad_Opcode },
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 { Bad_Opcode },
6489 /* 50 */
6490 { VEX_W_TABLE (VEX_W_0F3850) },
6491 { VEX_W_TABLE (VEX_W_0F3851) },
6492 { VEX_W_TABLE (VEX_W_0F3852) },
6493 { VEX_W_TABLE (VEX_W_0F3853) },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 /* 58 */
6499 { VEX_W_TABLE (VEX_W_0F3858) },
6500 { VEX_W_TABLE (VEX_W_0F3859) },
6501 { MOD_TABLE (MOD_VEX_0F385A) },
6502 { Bad_Opcode },
6503 { X86_64_TABLE (X86_64_VEX_0F385C) },
6504 { Bad_Opcode },
6505 { X86_64_TABLE (X86_64_VEX_0F385E) },
6506 { Bad_Opcode },
6507 /* 60 */
6508 { Bad_Opcode },
6509 { Bad_Opcode },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 /* 68 */
6517 { Bad_Opcode },
6518 { Bad_Opcode },
6519 { Bad_Opcode },
6520 { Bad_Opcode },
6521 { X86_64_TABLE (X86_64_VEX_0F386C) },
6522 { Bad_Opcode },
6523 { Bad_Opcode },
6524 { Bad_Opcode },
6525 /* 70 */
6526 { Bad_Opcode },
6527 { Bad_Opcode },
6528 { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6529 { Bad_Opcode },
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 { Bad_Opcode },
6534 /* 78 */
6535 { VEX_W_TABLE (VEX_W_0F3878) },
6536 { VEX_W_TABLE (VEX_W_0F3879) },
6537 { Bad_Opcode },
6538 { Bad_Opcode },
6539 { Bad_Opcode },
6540 { Bad_Opcode },
6541 { Bad_Opcode },
6542 { Bad_Opcode },
6543 /* 80 */
6544 { Bad_Opcode },
6545 { Bad_Opcode },
6546 { Bad_Opcode },
6547 { Bad_Opcode },
6548 { Bad_Opcode },
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 { Bad_Opcode },
6552 /* 88 */
6553 { Bad_Opcode },
6554 { Bad_Opcode },
6555 { Bad_Opcode },
6556 { Bad_Opcode },
6557 { MOD_TABLE (MOD_VEX_0F388C) },
6558 { Bad_Opcode },
6559 { MOD_TABLE (MOD_VEX_0F388E) },
6560 { Bad_Opcode },
6561 /* 90 */
6562 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6563 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6564 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6565 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6566 { Bad_Opcode },
6567 { Bad_Opcode },
6568 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6569 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6570 /* 98 */
6571 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6572 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6573 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6574 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6575 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6576 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6577 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6578 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6579 /* a0 */
6580 { Bad_Opcode },
6581 { Bad_Opcode },
6582 { Bad_Opcode },
6583 { Bad_Opcode },
6584 { Bad_Opcode },
6585 { Bad_Opcode },
6586 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6587 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6588 /* a8 */
6589 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6590 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6591 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6592 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6593 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6594 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6595 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6596 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6597 /* b0 */
6598 { VEX_W_TABLE (VEX_W_0F38B0) },
6599 { VEX_W_TABLE (VEX_W_0F38B1) },
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 { VEX_W_TABLE (VEX_W_0F38B4) },
6603 { VEX_W_TABLE (VEX_W_0F38B5) },
6604 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6605 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6606 /* b8 */
6607 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6608 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6609 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6610 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6611 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6612 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6613 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6614 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6615 /* c0 */
6616 { Bad_Opcode },
6617 { Bad_Opcode },
6618 { Bad_Opcode },
6619 { Bad_Opcode },
6620 { Bad_Opcode },
6621 { Bad_Opcode },
6622 { Bad_Opcode },
6623 { Bad_Opcode },
6624 /* c8 */
6625 { Bad_Opcode },
6626 { Bad_Opcode },
6627 { Bad_Opcode },
6628 { Bad_Opcode },
6629 { Bad_Opcode },
6630 { Bad_Opcode },
6631 { Bad_Opcode },
6632 { VEX_W_TABLE (VEX_W_0F38CF) },
6633 /* d0 */
6634 { Bad_Opcode },
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 { Bad_Opcode },
6638 { Bad_Opcode },
6639 { Bad_Opcode },
6640 { Bad_Opcode },
6641 { Bad_Opcode },
6642 /* d8 */
6643 { Bad_Opcode },
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6647 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6648 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6649 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6650 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6651 /* e0 */
6652 { X86_64_TABLE (X86_64_VEX_0F38E0) },
6653 { X86_64_TABLE (X86_64_VEX_0F38E1) },
6654 { X86_64_TABLE (X86_64_VEX_0F38E2) },
6655 { X86_64_TABLE (X86_64_VEX_0F38E3) },
6656 { X86_64_TABLE (X86_64_VEX_0F38E4) },
6657 { X86_64_TABLE (X86_64_VEX_0F38E5) },
6658 { X86_64_TABLE (X86_64_VEX_0F38E6) },
6659 { X86_64_TABLE (X86_64_VEX_0F38E7) },
6660 /* e8 */
6661 { X86_64_TABLE (X86_64_VEX_0F38E8) },
6662 { X86_64_TABLE (X86_64_VEX_0F38E9) },
6663 { X86_64_TABLE (X86_64_VEX_0F38EA) },
6664 { X86_64_TABLE (X86_64_VEX_0F38EB) },
6665 { X86_64_TABLE (X86_64_VEX_0F38EC) },
6666 { X86_64_TABLE (X86_64_VEX_0F38ED) },
6667 { X86_64_TABLE (X86_64_VEX_0F38EE) },
6668 { X86_64_TABLE (X86_64_VEX_0F38EF) },
6669 /* f0 */
6670 { Bad_Opcode },
6671 { Bad_Opcode },
6672 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6673 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6674 { Bad_Opcode },
6675 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6676 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6677 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6678 /* f8 */
6679 { Bad_Opcode },
6680 { Bad_Opcode },
6681 { Bad_Opcode },
6682 { Bad_Opcode },
6683 { Bad_Opcode },
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 },
6688 /* VEX_0F3A */
6689 {
6690 /* 00 */
6691 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6692 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6693 { VEX_W_TABLE (VEX_W_0F3A02) },
6694 { Bad_Opcode },
6695 { VEX_W_TABLE (VEX_W_0F3A04) },
6696 { VEX_W_TABLE (VEX_W_0F3A05) },
6697 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6698 { Bad_Opcode },
6699 /* 08 */
6700 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6701 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6702 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6703 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6704 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6705 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6706 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6707 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6708 /* 10 */
6709 { Bad_Opcode },
6710 { Bad_Opcode },
6711 { Bad_Opcode },
6712 { Bad_Opcode },
6713 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6714 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6715 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6716 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6717 /* 18 */
6718 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6719 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6720 { Bad_Opcode },
6721 { Bad_Opcode },
6722 { Bad_Opcode },
6723 { VEX_W_TABLE (VEX_W_0F3A1D) },
6724 { Bad_Opcode },
6725 { Bad_Opcode },
6726 /* 20 */
6727 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6728 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6729 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6730 { Bad_Opcode },
6731 { Bad_Opcode },
6732 { Bad_Opcode },
6733 { Bad_Opcode },
6734 { Bad_Opcode },
6735 /* 28 */
6736 { Bad_Opcode },
6737 { Bad_Opcode },
6738 { Bad_Opcode },
6739 { Bad_Opcode },
6740 { Bad_Opcode },
6741 { Bad_Opcode },
6742 { Bad_Opcode },
6743 { Bad_Opcode },
6744 /* 30 */
6745 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6746 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6747 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6748 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6749 { Bad_Opcode },
6750 { Bad_Opcode },
6751 { Bad_Opcode },
6752 { Bad_Opcode },
6753 /* 38 */
6754 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6755 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { Bad_Opcode },
6759 { Bad_Opcode },
6760 { Bad_Opcode },
6761 { Bad_Opcode },
6762 /* 40 */
6763 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6764 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6765 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6766 { Bad_Opcode },
6767 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6768 { Bad_Opcode },
6769 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6770 { Bad_Opcode },
6771 /* 48 */
6772 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6773 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6774 { VEX_W_TABLE (VEX_W_0F3A4A) },
6775 { VEX_W_TABLE (VEX_W_0F3A4B) },
6776 { VEX_W_TABLE (VEX_W_0F3A4C) },
6777 { Bad_Opcode },
6778 { Bad_Opcode },
6779 { Bad_Opcode },
6780 /* 50 */
6781 { Bad_Opcode },
6782 { Bad_Opcode },
6783 { Bad_Opcode },
6784 { Bad_Opcode },
6785 { Bad_Opcode },
6786 { Bad_Opcode },
6787 { Bad_Opcode },
6788 { Bad_Opcode },
6789 /* 58 */
6790 { Bad_Opcode },
6791 { Bad_Opcode },
6792 { Bad_Opcode },
6793 { Bad_Opcode },
6794 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6795 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6796 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6797 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6798 /* 60 */
6799 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6800 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6801 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6802 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6803 { Bad_Opcode },
6804 { Bad_Opcode },
6805 { Bad_Opcode },
6806 { Bad_Opcode },
6807 /* 68 */
6808 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6809 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6810 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6811 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6812 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6813 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6814 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6815 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6816 /* 70 */
6817 { Bad_Opcode },
6818 { Bad_Opcode },
6819 { Bad_Opcode },
6820 { Bad_Opcode },
6821 { Bad_Opcode },
6822 { Bad_Opcode },
6823 { Bad_Opcode },
6824 { Bad_Opcode },
6825 /* 78 */
6826 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6827 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6828 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6829 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6830 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6831 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6832 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6833 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6834 /* 80 */
6835 { Bad_Opcode },
6836 { Bad_Opcode },
6837 { Bad_Opcode },
6838 { Bad_Opcode },
6839 { Bad_Opcode },
6840 { Bad_Opcode },
6841 { Bad_Opcode },
6842 { Bad_Opcode },
6843 /* 88 */
6844 { Bad_Opcode },
6845 { Bad_Opcode },
6846 { Bad_Opcode },
6847 { Bad_Opcode },
6848 { Bad_Opcode },
6849 { Bad_Opcode },
6850 { Bad_Opcode },
6851 { Bad_Opcode },
6852 /* 90 */
6853 { Bad_Opcode },
6854 { Bad_Opcode },
6855 { Bad_Opcode },
6856 { Bad_Opcode },
6857 { Bad_Opcode },
6858 { Bad_Opcode },
6859 { Bad_Opcode },
6860 { Bad_Opcode },
6861 /* 98 */
6862 { Bad_Opcode },
6863 { Bad_Opcode },
6864 { Bad_Opcode },
6865 { Bad_Opcode },
6866 { Bad_Opcode },
6867 { Bad_Opcode },
6868 { Bad_Opcode },
6869 { Bad_Opcode },
6870 /* a0 */
6871 { Bad_Opcode },
6872 { Bad_Opcode },
6873 { Bad_Opcode },
6874 { Bad_Opcode },
6875 { Bad_Opcode },
6876 { Bad_Opcode },
6877 { Bad_Opcode },
6878 { Bad_Opcode },
6879 /* a8 */
6880 { Bad_Opcode },
6881 { Bad_Opcode },
6882 { Bad_Opcode },
6883 { Bad_Opcode },
6884 { Bad_Opcode },
6885 { Bad_Opcode },
6886 { Bad_Opcode },
6887 { Bad_Opcode },
6888 /* b0 */
6889 { Bad_Opcode },
6890 { Bad_Opcode },
6891 { Bad_Opcode },
6892 { Bad_Opcode },
6893 { Bad_Opcode },
6894 { Bad_Opcode },
6895 { Bad_Opcode },
6896 { Bad_Opcode },
6897 /* b8 */
6898 { Bad_Opcode },
6899 { Bad_Opcode },
6900 { Bad_Opcode },
6901 { Bad_Opcode },
6902 { Bad_Opcode },
6903 { Bad_Opcode },
6904 { Bad_Opcode },
6905 { Bad_Opcode },
6906 /* c0 */
6907 { Bad_Opcode },
6908 { Bad_Opcode },
6909 { Bad_Opcode },
6910 { Bad_Opcode },
6911 { Bad_Opcode },
6912 { Bad_Opcode },
6913 { Bad_Opcode },
6914 { Bad_Opcode },
6915 /* c8 */
6916 { Bad_Opcode },
6917 { Bad_Opcode },
6918 { Bad_Opcode },
6919 { Bad_Opcode },
6920 { Bad_Opcode },
6921 { Bad_Opcode },
6922 { VEX_W_TABLE (VEX_W_0F3ACE) },
6923 { VEX_W_TABLE (VEX_W_0F3ACF) },
6924 /* d0 */
6925 { Bad_Opcode },
6926 { Bad_Opcode },
6927 { Bad_Opcode },
6928 { Bad_Opcode },
6929 { Bad_Opcode },
6930 { Bad_Opcode },
6931 { Bad_Opcode },
6932 { Bad_Opcode },
6933 /* d8 */
6934 { Bad_Opcode },
6935 { Bad_Opcode },
6936 { Bad_Opcode },
6937 { Bad_Opcode },
6938 { Bad_Opcode },
6939 { Bad_Opcode },
6940 { Bad_Opcode },
6941 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6942 /* e0 */
6943 { Bad_Opcode },
6944 { Bad_Opcode },
6945 { Bad_Opcode },
6946 { Bad_Opcode },
6947 { Bad_Opcode },
6948 { Bad_Opcode },
6949 { Bad_Opcode },
6950 { Bad_Opcode },
6951 /* e8 */
6952 { Bad_Opcode },
6953 { Bad_Opcode },
6954 { Bad_Opcode },
6955 { Bad_Opcode },
6956 { Bad_Opcode },
6957 { Bad_Opcode },
6958 { Bad_Opcode },
6959 { Bad_Opcode },
6960 /* f0 */
6961 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6962 { Bad_Opcode },
6963 { Bad_Opcode },
6964 { Bad_Opcode },
6965 { Bad_Opcode },
6966 { Bad_Opcode },
6967 { Bad_Opcode },
6968 { Bad_Opcode },
6969 /* f8 */
6970 { Bad_Opcode },
6971 { Bad_Opcode },
6972 { Bad_Opcode },
6973 { Bad_Opcode },
6974 { Bad_Opcode },
6975 { Bad_Opcode },
6976 { Bad_Opcode },
6977 { Bad_Opcode },
6978 },
6979 };
6980
6981 #include "i386-dis-evex.h"
6982
6983 static const struct dis386 vex_len_table[][2] = {
6984 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6985 {
6986 { "%XEvmovlpX", { XM, Vex, EXq }, 0 },
6987 },
6988
6989 /* VEX_LEN_0F12_P_0_M_1 */
6990 {
6991 { "%XEvmovhlp%XS", { XM, Vex, EXq }, 0 },
6992 },
6993
6994 /* VEX_LEN_0F13_M_0 */
6995 {
6996 { "%XEvmovlpX", { EXq, XM }, PREFIX_OPCODE },
6997 },
6998
6999 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
7000 {
7001 { "%XEvmovhpX", { XM, Vex, EXq }, 0 },
7002 },
7003
7004 /* VEX_LEN_0F16_P_0_M_1 */
7005 {
7006 { "%XEvmovlhp%XS", { XM, Vex, EXq }, 0 },
7007 },
7008
7009 /* VEX_LEN_0F17_M_0 */
7010 {
7011 { "%XEvmovhpX", { EXq, XM }, PREFIX_OPCODE },
7012 },
7013
7014 /* VEX_LEN_0F41 */
7015 {
7016 { Bad_Opcode },
7017 { MOD_TABLE (MOD_VEX_0F41_L_1) },
7018 },
7019
7020 /* VEX_LEN_0F42 */
7021 {
7022 { Bad_Opcode },
7023 { MOD_TABLE (MOD_VEX_0F42_L_1) },
7024 },
7025
7026 /* VEX_LEN_0F44 */
7027 {
7028 { MOD_TABLE (MOD_VEX_0F44_L_0) },
7029 },
7030
7031 /* VEX_LEN_0F45 */
7032 {
7033 { Bad_Opcode },
7034 { MOD_TABLE (MOD_VEX_0F45_L_1) },
7035 },
7036
7037 /* VEX_LEN_0F46 */
7038 {
7039 { Bad_Opcode },
7040 { MOD_TABLE (MOD_VEX_0F46_L_1) },
7041 },
7042
7043 /* VEX_LEN_0F47 */
7044 {
7045 { Bad_Opcode },
7046 { MOD_TABLE (MOD_VEX_0F47_L_1) },
7047 },
7048
7049 /* VEX_LEN_0F4A */
7050 {
7051 { Bad_Opcode },
7052 { MOD_TABLE (MOD_VEX_0F4A_L_1) },
7053 },
7054
7055 /* VEX_LEN_0F4B */
7056 {
7057 { Bad_Opcode },
7058 { MOD_TABLE (MOD_VEX_0F4B_L_1) },
7059 },
7060
7061 /* VEX_LEN_0F6E */
7062 {
7063 { "%XEvmovK", { XMScalar, Edq }, PREFIX_DATA },
7064 },
7065
7066 /* VEX_LEN_0F77 */
7067 {
7068 { "vzeroupper", { XX }, 0 },
7069 { "vzeroall", { XX }, 0 },
7070 },
7071
7072 /* VEX_LEN_0F7E_P_1 */
7073 {
7074 { "%XEvmovq", { XMScalar, EXq }, 0 },
7075 },
7076
7077 /* VEX_LEN_0F7E_P_2 */
7078 {
7079 { "%XEvmovK", { Edq, XMScalar }, 0 },
7080 },
7081
7082 /* VEX_LEN_0F90 */
7083 {
7084 { VEX_W_TABLE (VEX_W_0F90_L_0) },
7085 },
7086
7087 /* VEX_LEN_0F91 */
7088 {
7089 { MOD_TABLE (MOD_VEX_0F91_L_0) },
7090 },
7091
7092 /* VEX_LEN_0F92 */
7093 {
7094 { MOD_TABLE (MOD_VEX_0F92_L_0) },
7095 },
7096
7097 /* VEX_LEN_0F93 */
7098 {
7099 { MOD_TABLE (MOD_VEX_0F93_L_0) },
7100 },
7101
7102 /* VEX_LEN_0F98 */
7103 {
7104 { MOD_TABLE (MOD_VEX_0F98_L_0) },
7105 },
7106
7107 /* VEX_LEN_0F99 */
7108 {
7109 { MOD_TABLE (MOD_VEX_0F99_L_0) },
7110 },
7111
7112 /* VEX_LEN_0FAE_R_2_M_0 */
7113 {
7114 { "vldmxcsr", { Md }, 0 },
7115 },
7116
7117 /* VEX_LEN_0FAE_R_3_M_0 */
7118 {
7119 { "vstmxcsr", { Md }, 0 },
7120 },
7121
7122 /* VEX_LEN_0FC4 */
7123 {
7124 { "%XEvpinsrw", { XM, Vex, Edw, Ib }, PREFIX_DATA },
7125 },
7126
7127 /* VEX_LEN_0FC5 */
7128 {
7129 { "%XEvpextrw", { Gd, XS, Ib }, PREFIX_DATA },
7130 },
7131
7132 /* VEX_LEN_0FD6 */
7133 {
7134 { "%XEvmovq", { EXqS, XMScalar }, PREFIX_DATA },
7135 },
7136
7137 /* VEX_LEN_0FF7 */
7138 {
7139 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
7140 },
7141
7142 /* VEX_LEN_0F3816 */
7143 {
7144 { Bad_Opcode },
7145 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7146 },
7147
7148 /* VEX_LEN_0F3819 */
7149 {
7150 { Bad_Opcode },
7151 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7152 },
7153
7154 /* VEX_LEN_0F381A_M_0 */
7155 {
7156 { Bad_Opcode },
7157 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
7158 },
7159
7160 /* VEX_LEN_0F3836 */
7161 {
7162 { Bad_Opcode },
7163 { VEX_W_TABLE (VEX_W_0F3836) },
7164 },
7165
7166 /* VEX_LEN_0F3841 */
7167 {
7168 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
7169 },
7170
7171 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
7172 {
7173 { "ldtilecfg", { M }, 0 },
7174 },
7175
7176 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
7177 {
7178 { "tilerelease", { Skip_MODRM }, 0 },
7179 },
7180
7181 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
7182 {
7183 { "sttilecfg", { M }, 0 },
7184 },
7185
7186 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
7187 {
7188 { "tilezero", { TMM, Skip_MODRM }, 0 },
7189 },
7190
7191 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
7192 {
7193 { "tilestored", { MVexSIBMEM, TMM }, 0 },
7194 },
7195 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7196 {
7197 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
7198 },
7199
7200 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7201 {
7202 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
7203 },
7204
7205 /* VEX_LEN_0F385A_M_0 */
7206 {
7207 { Bad_Opcode },
7208 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7209 },
7210
7211 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7212 {
7213 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
7214 },
7215
7216 /* VEX_LEN_0F385C_X86_64_P_3_W_0_M_0 */
7217 {
7218 { "tdpfp16ps", { TMM, EXtmm, VexTmm }, 0 },
7219 },
7220
7221 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7222 {
7223 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
7224 },
7225
7226 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7227 {
7228 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
7229 },
7230
7231 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7232 {
7233 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7234 },
7235
7236 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7237 {
7238 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7239 },
7240
7241 /* VEX_LEN_0F386C_X86_64_W_0_M_1 */
7242 {
7243 { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0) },
7244 },
7245
7246 /* VEX_LEN_0F38DB */
7247 {
7248 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7249 },
7250
7251 /* VEX_LEN_0F38F2 */
7252 {
7253 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7254 },
7255
7256 /* VEX_LEN_0F38F3 */
7257 {
7258 { REG_TABLE(REG_VEX_0F38F3_L_0) },
7259 },
7260
7261 /* VEX_LEN_0F38F5 */
7262 {
7263 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7264 },
7265
7266 /* VEX_LEN_0F38F6 */
7267 {
7268 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7269 },
7270
7271 /* VEX_LEN_0F38F7 */
7272 {
7273 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7274 },
7275
7276 /* VEX_LEN_0F3A00 */
7277 {
7278 { Bad_Opcode },
7279 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7280 },
7281
7282 /* VEX_LEN_0F3A01 */
7283 {
7284 { Bad_Opcode },
7285 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7286 },
7287
7288 /* VEX_LEN_0F3A06 */
7289 {
7290 { Bad_Opcode },
7291 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7292 },
7293
7294 /* VEX_LEN_0F3A14 */
7295 {
7296 { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA },
7297 },
7298
7299 /* VEX_LEN_0F3A15 */
7300 {
7301 { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA },
7302 },
7303
7304 /* VEX_LEN_0F3A16 */
7305 {
7306 { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7307 },
7308
7309 /* VEX_LEN_0F3A17 */
7310 {
7311 { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA },
7312 },
7313
7314 /* VEX_LEN_0F3A18 */
7315 {
7316 { Bad_Opcode },
7317 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7318 },
7319
7320 /* VEX_LEN_0F3A19 */
7321 {
7322 { Bad_Opcode },
7323 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7324 },
7325
7326 /* VEX_LEN_0F3A20 */
7327 {
7328 { "%XEvpinsrb", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7329 },
7330
7331 /* VEX_LEN_0F3A21 */
7332 {
7333 { "%XEvinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7334 },
7335
7336 /* VEX_LEN_0F3A22 */
7337 {
7338 { "%XEvpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7339 },
7340
7341 /* VEX_LEN_0F3A30 */
7342 {
7343 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7344 },
7345
7346 /* VEX_LEN_0F3A31 */
7347 {
7348 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7349 },
7350
7351 /* VEX_LEN_0F3A32 */
7352 {
7353 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7354 },
7355
7356 /* VEX_LEN_0F3A33 */
7357 {
7358 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7359 },
7360
7361 /* VEX_LEN_0F3A38 */
7362 {
7363 { Bad_Opcode },
7364 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7365 },
7366
7367 /* VEX_LEN_0F3A39 */
7368 {
7369 { Bad_Opcode },
7370 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7371 },
7372
7373 /* VEX_LEN_0F3A41 */
7374 {
7375 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7376 },
7377
7378 /* VEX_LEN_0F3A46 */
7379 {
7380 { Bad_Opcode },
7381 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7382 },
7383
7384 /* VEX_LEN_0F3A60 */
7385 {
7386 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7387 },
7388
7389 /* VEX_LEN_0F3A61 */
7390 {
7391 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7392 },
7393
7394 /* VEX_LEN_0F3A62 */
7395 {
7396 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7397 },
7398
7399 /* VEX_LEN_0F3A63 */
7400 {
7401 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7402 },
7403
7404 /* VEX_LEN_0F3ADF */
7405 {
7406 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7407 },
7408
7409 /* VEX_LEN_0F3AF0 */
7410 {
7411 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7412 },
7413
7414 /* VEX_LEN_0FXOP_08_85 */
7415 {
7416 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7417 },
7418
7419 /* VEX_LEN_0FXOP_08_86 */
7420 {
7421 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7422 },
7423
7424 /* VEX_LEN_0FXOP_08_87 */
7425 {
7426 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7427 },
7428
7429 /* VEX_LEN_0FXOP_08_8E */
7430 {
7431 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7432 },
7433
7434 /* VEX_LEN_0FXOP_08_8F */
7435 {
7436 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7437 },
7438
7439 /* VEX_LEN_0FXOP_08_95 */
7440 {
7441 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7442 },
7443
7444 /* VEX_LEN_0FXOP_08_96 */
7445 {
7446 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7447 },
7448
7449 /* VEX_LEN_0FXOP_08_97 */
7450 {
7451 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7452 },
7453
7454 /* VEX_LEN_0FXOP_08_9E */
7455 {
7456 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7457 },
7458
7459 /* VEX_LEN_0FXOP_08_9F */
7460 {
7461 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7462 },
7463
7464 /* VEX_LEN_0FXOP_08_A3 */
7465 {
7466 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7467 },
7468
7469 /* VEX_LEN_0FXOP_08_A6 */
7470 {
7471 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7472 },
7473
7474 /* VEX_LEN_0FXOP_08_B6 */
7475 {
7476 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7477 },
7478
7479 /* VEX_LEN_0FXOP_08_C0 */
7480 {
7481 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7482 },
7483
7484 /* VEX_LEN_0FXOP_08_C1 */
7485 {
7486 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7487 },
7488
7489 /* VEX_LEN_0FXOP_08_C2 */
7490 {
7491 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7492 },
7493
7494 /* VEX_LEN_0FXOP_08_C3 */
7495 {
7496 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7497 },
7498
7499 /* VEX_LEN_0FXOP_08_CC */
7500 {
7501 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7502 },
7503
7504 /* VEX_LEN_0FXOP_08_CD */
7505 {
7506 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7507 },
7508
7509 /* VEX_LEN_0FXOP_08_CE */
7510 {
7511 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7512 },
7513
7514 /* VEX_LEN_0FXOP_08_CF */
7515 {
7516 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7517 },
7518
7519 /* VEX_LEN_0FXOP_08_EC */
7520 {
7521 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7522 },
7523
7524 /* VEX_LEN_0FXOP_08_ED */
7525 {
7526 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7527 },
7528
7529 /* VEX_LEN_0FXOP_08_EE */
7530 {
7531 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7532 },
7533
7534 /* VEX_LEN_0FXOP_08_EF */
7535 {
7536 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7537 },
7538
7539 /* VEX_LEN_0FXOP_09_01 */
7540 {
7541 { REG_TABLE (REG_XOP_09_01_L_0) },
7542 },
7543
7544 /* VEX_LEN_0FXOP_09_02 */
7545 {
7546 { REG_TABLE (REG_XOP_09_02_L_0) },
7547 },
7548
7549 /* VEX_LEN_0FXOP_09_12_M_1 */
7550 {
7551 { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7552 },
7553
7554 /* VEX_LEN_0FXOP_09_82_W_0 */
7555 {
7556 { "vfrczss", { XM, EXd }, 0 },
7557 },
7558
7559 /* VEX_LEN_0FXOP_09_83_W_0 */
7560 {
7561 { "vfrczsd", { XM, EXq }, 0 },
7562 },
7563
7564 /* VEX_LEN_0FXOP_09_90 */
7565 {
7566 { "vprotb", { XM, EXx, VexW }, 0 },
7567 },
7568
7569 /* VEX_LEN_0FXOP_09_91 */
7570 {
7571 { "vprotw", { XM, EXx, VexW }, 0 },
7572 },
7573
7574 /* VEX_LEN_0FXOP_09_92 */
7575 {
7576 { "vprotd", { XM, EXx, VexW }, 0 },
7577 },
7578
7579 /* VEX_LEN_0FXOP_09_93 */
7580 {
7581 { "vprotq", { XM, EXx, VexW }, 0 },
7582 },
7583
7584 /* VEX_LEN_0FXOP_09_94 */
7585 {
7586 { "vpshlb", { XM, EXx, VexW }, 0 },
7587 },
7588
7589 /* VEX_LEN_0FXOP_09_95 */
7590 {
7591 { "vpshlw", { XM, EXx, VexW }, 0 },
7592 },
7593
7594 /* VEX_LEN_0FXOP_09_96 */
7595 {
7596 { "vpshld", { XM, EXx, VexW }, 0 },
7597 },
7598
7599 /* VEX_LEN_0FXOP_09_97 */
7600 {
7601 { "vpshlq", { XM, EXx, VexW }, 0 },
7602 },
7603
7604 /* VEX_LEN_0FXOP_09_98 */
7605 {
7606 { "vpshab", { XM, EXx, VexW }, 0 },
7607 },
7608
7609 /* VEX_LEN_0FXOP_09_99 */
7610 {
7611 { "vpshaw", { XM, EXx, VexW }, 0 },
7612 },
7613
7614 /* VEX_LEN_0FXOP_09_9A */
7615 {
7616 { "vpshad", { XM, EXx, VexW }, 0 },
7617 },
7618
7619 /* VEX_LEN_0FXOP_09_9B */
7620 {
7621 { "vpshaq", { XM, EXx, VexW }, 0 },
7622 },
7623
7624 /* VEX_LEN_0FXOP_09_C1 */
7625 {
7626 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7627 },
7628
7629 /* VEX_LEN_0FXOP_09_C2 */
7630 {
7631 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7632 },
7633
7634 /* VEX_LEN_0FXOP_09_C3 */
7635 {
7636 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7637 },
7638
7639 /* VEX_LEN_0FXOP_09_C6 */
7640 {
7641 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7642 },
7643
7644 /* VEX_LEN_0FXOP_09_C7 */
7645 {
7646 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7647 },
7648
7649 /* VEX_LEN_0FXOP_09_CB */
7650 {
7651 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7652 },
7653
7654 /* VEX_LEN_0FXOP_09_D1 */
7655 {
7656 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7657 },
7658
7659 /* VEX_LEN_0FXOP_09_D2 */
7660 {
7661 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7662 },
7663
7664 /* VEX_LEN_0FXOP_09_D3 */
7665 {
7666 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7667 },
7668
7669 /* VEX_LEN_0FXOP_09_D6 */
7670 {
7671 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7672 },
7673
7674 /* VEX_LEN_0FXOP_09_D7 */
7675 {
7676 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7677 },
7678
7679 /* VEX_LEN_0FXOP_09_DB */
7680 {
7681 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7682 },
7683
7684 /* VEX_LEN_0FXOP_09_E1 */
7685 {
7686 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7687 },
7688
7689 /* VEX_LEN_0FXOP_09_E2 */
7690 {
7691 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7692 },
7693
7694 /* VEX_LEN_0FXOP_09_E3 */
7695 {
7696 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7697 },
7698
7699 /* VEX_LEN_0FXOP_0A_12 */
7700 {
7701 { REG_TABLE (REG_XOP_0A_12_L_0) },
7702 },
7703 };
7704
7705 #include "i386-dis-evex-len.h"
7706
7707 static const struct dis386 vex_w_table[][2] = {
7708 {
7709 /* VEX_W_0F41_L_1_M_1 */
7710 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7711 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7712 },
7713 {
7714 /* VEX_W_0F42_L_1_M_1 */
7715 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7716 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7717 },
7718 {
7719 /* VEX_W_0F44_L_0_M_1 */
7720 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7721 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7722 },
7723 {
7724 /* VEX_W_0F45_L_1_M_1 */
7725 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7726 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7727 },
7728 {
7729 /* VEX_W_0F46_L_1_M_1 */
7730 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7731 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7732 },
7733 {
7734 /* VEX_W_0F47_L_1_M_1 */
7735 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7736 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7737 },
7738 {
7739 /* VEX_W_0F4A_L_1_M_1 */
7740 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7741 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7742 },
7743 {
7744 /* VEX_W_0F4B_L_1_M_1 */
7745 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7746 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7747 },
7748 {
7749 /* VEX_W_0F90_L_0 */
7750 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7751 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7752 },
7753 {
7754 /* VEX_W_0F91_L_0_M_0 */
7755 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7756 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7757 },
7758 {
7759 /* VEX_W_0F92_L_0_M_1 */
7760 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7761 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7762 },
7763 {
7764 /* VEX_W_0F93_L_0_M_1 */
7765 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7766 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7767 },
7768 {
7769 /* VEX_W_0F98_L_0_M_1 */
7770 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7771 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7772 },
7773 {
7774 /* VEX_W_0F99_L_0_M_1 */
7775 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7776 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7777 },
7778 {
7779 /* VEX_W_0F380C */
7780 { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7781 },
7782 {
7783 /* VEX_W_0F380D */
7784 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7785 },
7786 {
7787 /* VEX_W_0F380E */
7788 { "vtestps", { XM, EXx }, PREFIX_DATA },
7789 },
7790 {
7791 /* VEX_W_0F380F */
7792 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7793 },
7794 {
7795 /* VEX_W_0F3813 */
7796 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7797 },
7798 {
7799 /* VEX_W_0F3816_L_1 */
7800 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7801 },
7802 {
7803 /* VEX_W_0F3818 */
7804 { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA },
7805 },
7806 {
7807 /* VEX_W_0F3819_L_1 */
7808 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
7809 },
7810 {
7811 /* VEX_W_0F381A_M_0_L_1 */
7812 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7813 },
7814 {
7815 /* VEX_W_0F382C_M_0 */
7816 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7817 },
7818 {
7819 /* VEX_W_0F382D_M_0 */
7820 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7821 },
7822 {
7823 /* VEX_W_0F382E_M_0 */
7824 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7825 },
7826 {
7827 /* VEX_W_0F382F_M_0 */
7828 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7829 },
7830 {
7831 /* VEX_W_0F3836 */
7832 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7833 },
7834 {
7835 /* VEX_W_0F3846 */
7836 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7837 },
7838 {
7839 /* VEX_W_0F3849_X86_64_P_0 */
7840 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7841 },
7842 {
7843 /* VEX_W_0F3849_X86_64_P_2 */
7844 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7845 },
7846 {
7847 /* VEX_W_0F3849_X86_64_P_3 */
7848 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7849 },
7850 {
7851 /* VEX_W_0F384B_X86_64_P_1 */
7852 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7853 },
7854 {
7855 /* VEX_W_0F384B_X86_64_P_2 */
7856 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7857 },
7858 {
7859 /* VEX_W_0F384B_X86_64_P_3 */
7860 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7861 },
7862 {
7863 /* VEX_W_0F3850 */
7864 { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7865 },
7866 {
7867 /* VEX_W_0F3851 */
7868 { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7869 },
7870 {
7871 /* VEX_W_0F3852 */
7872 { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA },
7873 },
7874 {
7875 /* VEX_W_0F3853 */
7876 { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA },
7877 },
7878 {
7879 /* VEX_W_0F3858 */
7880 { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7881 },
7882 {
7883 /* VEX_W_0F3859 */
7884 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7885 },
7886 {
7887 /* VEX_W_0F385A_M_0_L_0 */
7888 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7889 },
7890 {
7891 /* VEX_W_0F385C_X86_64_P_1 */
7892 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7893 },
7894 {
7895 /* VEX_W_0F385C_X86_64_P_3 */
7896 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_3_W_0) },
7897 },
7898 {
7899 /* VEX_W_0F385E_X86_64_P_0 */
7900 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7901 },
7902 {
7903 /* VEX_W_0F385E_X86_64_P_1 */
7904 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7905 },
7906 {
7907 /* VEX_W_0F385E_X86_64_P_2 */
7908 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7909 },
7910 {
7911 /* VEX_W_0F385E_X86_64_P_3 */
7912 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7913 },
7914 {
7915 /* VEX_W_0F386C_X86_64 */
7916 { MOD_TABLE (MOD_VEX_0F386C_X86_64_W_0) },
7917 },
7918 {
7919 /* VEX_W_0F3872_P_1 */
7920 { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7921 },
7922 {
7923 /* VEX_W_0F3878 */
7924 { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA },
7925 },
7926 {
7927 /* VEX_W_0F3879 */
7928 { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA },
7929 },
7930 {
7931 /* VEX_W_0F38B0 */
7932 { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7933 },
7934 {
7935 /* VEX_W_0F38B1 */
7936 { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7937 },
7938 {
7939 /* VEX_W_0F38B4 */
7940 { Bad_Opcode },
7941 { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7942 },
7943 {
7944 /* VEX_W_0F38B5 */
7945 { Bad_Opcode },
7946 { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7947 },
7948 {
7949 /* VEX_W_0F38CF */
7950 { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7951 },
7952 {
7953 /* VEX_W_0F3A00_L_1 */
7954 { Bad_Opcode },
7955 { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA },
7956 },
7957 {
7958 /* VEX_W_0F3A01_L_1 */
7959 { Bad_Opcode },
7960 { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7961 },
7962 {
7963 /* VEX_W_0F3A02 */
7964 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7965 },
7966 {
7967 /* VEX_W_0F3A04 */
7968 { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7969 },
7970 {
7971 /* VEX_W_0F3A05 */
7972 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7973 },
7974 {
7975 /* VEX_W_0F3A06_L_1 */
7976 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7977 },
7978 {
7979 /* VEX_W_0F3A18_L_1 */
7980 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7981 },
7982 {
7983 /* VEX_W_0F3A19_L_1 */
7984 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7985 },
7986 {
7987 /* VEX_W_0F3A1D */
7988 { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7989 },
7990 {
7991 /* VEX_W_0F3A38_L_1 */
7992 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7993 },
7994 {
7995 /* VEX_W_0F3A39_L_1 */
7996 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7997 },
7998 {
7999 /* VEX_W_0F3A46_L_1 */
8000 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8001 },
8002 {
8003 /* VEX_W_0F3A4A */
8004 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8005 },
8006 {
8007 /* VEX_W_0F3A4B */
8008 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8009 },
8010 {
8011 /* VEX_W_0F3A4C */
8012 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8013 },
8014 {
8015 /* VEX_W_0F3ACE */
8016 { Bad_Opcode },
8017 { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8018 },
8019 {
8020 /* VEX_W_0F3ACF */
8021 { Bad_Opcode },
8022 { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8023 },
8024 /* VEX_W_0FXOP_08_85_L_0 */
8025 {
8026 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
8027 },
8028 /* VEX_W_0FXOP_08_86_L_0 */
8029 {
8030 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8031 },
8032 /* VEX_W_0FXOP_08_87_L_0 */
8033 {
8034 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
8035 },
8036 /* VEX_W_0FXOP_08_8E_L_0 */
8037 {
8038 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
8039 },
8040 /* VEX_W_0FXOP_08_8F_L_0 */
8041 {
8042 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
8043 },
8044 /* VEX_W_0FXOP_08_95_L_0 */
8045 {
8046 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
8047 },
8048 /* VEX_W_0FXOP_08_96_L_0 */
8049 {
8050 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8051 },
8052 /* VEX_W_0FXOP_08_97_L_0 */
8053 {
8054 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
8055 },
8056 /* VEX_W_0FXOP_08_9E_L_0 */
8057 {
8058 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
8059 },
8060 /* VEX_W_0FXOP_08_9F_L_0 */
8061 {
8062 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
8063 },
8064 /* VEX_W_0FXOP_08_A6_L_0 */
8065 {
8066 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8067 },
8068 /* VEX_W_0FXOP_08_B6_L_0 */
8069 {
8070 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8071 },
8072 /* VEX_W_0FXOP_08_C0_L_0 */
8073 {
8074 { "vprotb", { XM, EXx, Ib }, 0 },
8075 },
8076 /* VEX_W_0FXOP_08_C1_L_0 */
8077 {
8078 { "vprotw", { XM, EXx, Ib }, 0 },
8079 },
8080 /* VEX_W_0FXOP_08_C2_L_0 */
8081 {
8082 { "vprotd", { XM, EXx, Ib }, 0 },
8083 },
8084 /* VEX_W_0FXOP_08_C3_L_0 */
8085 {
8086 { "vprotq", { XM, EXx, Ib }, 0 },
8087 },
8088 /* VEX_W_0FXOP_08_CC_L_0 */
8089 {
8090 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
8091 },
8092 /* VEX_W_0FXOP_08_CD_L_0 */
8093 {
8094 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
8095 },
8096 /* VEX_W_0FXOP_08_CE_L_0 */
8097 {
8098 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
8099 },
8100 /* VEX_W_0FXOP_08_CF_L_0 */
8101 {
8102 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
8103 },
8104 /* VEX_W_0FXOP_08_EC_L_0 */
8105 {
8106 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
8107 },
8108 /* VEX_W_0FXOP_08_ED_L_0 */
8109 {
8110 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
8111 },
8112 /* VEX_W_0FXOP_08_EE_L_0 */
8113 {
8114 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
8115 },
8116 /* VEX_W_0FXOP_08_EF_L_0 */
8117 {
8118 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
8119 },
8120 /* VEX_W_0FXOP_09_80 */
8121 {
8122 { "vfrczps", { XM, EXx }, 0 },
8123 },
8124 /* VEX_W_0FXOP_09_81 */
8125 {
8126 { "vfrczpd", { XM, EXx }, 0 },
8127 },
8128 /* VEX_W_0FXOP_09_82 */
8129 {
8130 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
8131 },
8132 /* VEX_W_0FXOP_09_83 */
8133 {
8134 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
8135 },
8136 /* VEX_W_0FXOP_09_C1_L_0 */
8137 {
8138 { "vphaddbw", { XM, EXxmm }, 0 },
8139 },
8140 /* VEX_W_0FXOP_09_C2_L_0 */
8141 {
8142 { "vphaddbd", { XM, EXxmm }, 0 },
8143 },
8144 /* VEX_W_0FXOP_09_C3_L_0 */
8145 {
8146 { "vphaddbq", { XM, EXxmm }, 0 },
8147 },
8148 /* VEX_W_0FXOP_09_C6_L_0 */
8149 {
8150 { "vphaddwd", { XM, EXxmm }, 0 },
8151 },
8152 /* VEX_W_0FXOP_09_C7_L_0 */
8153 {
8154 { "vphaddwq", { XM, EXxmm }, 0 },
8155 },
8156 /* VEX_W_0FXOP_09_CB_L_0 */
8157 {
8158 { "vphadddq", { XM, EXxmm }, 0 },
8159 },
8160 /* VEX_W_0FXOP_09_D1_L_0 */
8161 {
8162 { "vphaddubw", { XM, EXxmm }, 0 },
8163 },
8164 /* VEX_W_0FXOP_09_D2_L_0 */
8165 {
8166 { "vphaddubd", { XM, EXxmm }, 0 },
8167 },
8168 /* VEX_W_0FXOP_09_D3_L_0 */
8169 {
8170 { "vphaddubq", { XM, EXxmm }, 0 },
8171 },
8172 /* VEX_W_0FXOP_09_D6_L_0 */
8173 {
8174 { "vphadduwd", { XM, EXxmm }, 0 },
8175 },
8176 /* VEX_W_0FXOP_09_D7_L_0 */
8177 {
8178 { "vphadduwq", { XM, EXxmm }, 0 },
8179 },
8180 /* VEX_W_0FXOP_09_DB_L_0 */
8181 {
8182 { "vphaddudq", { XM, EXxmm }, 0 },
8183 },
8184 /* VEX_W_0FXOP_09_E1_L_0 */
8185 {
8186 { "vphsubbw", { XM, EXxmm }, 0 },
8187 },
8188 /* VEX_W_0FXOP_09_E2_L_0 */
8189 {
8190 { "vphsubwd", { XM, EXxmm }, 0 },
8191 },
8192 /* VEX_W_0FXOP_09_E3_L_0 */
8193 {
8194 { "vphsubdq", { XM, EXxmm }, 0 },
8195 },
8196
8197 #include "i386-dis-evex-w.h"
8198 };
8199
8200 static const struct dis386 mod_table[][2] = {
8201 {
8202 /* MOD_62_32BIT */
8203 { "bound{S|}", { Gv, Ma }, 0 },
8204 { EVEX_TABLE (EVEX_0F) },
8205 },
8206 {
8207 /* MOD_8D */
8208 { "leaS", { Gv, M }, 0 },
8209 },
8210 {
8211 /* MOD_C4_32BIT */
8212 { "lesS", { Gv, Mp }, 0 },
8213 { VEX_C4_TABLE (VEX_0F) },
8214 },
8215 {
8216 /* MOD_C5_32BIT */
8217 { "ldsS", { Gv, Mp }, 0 },
8218 { VEX_C5_TABLE (VEX_0F) },
8219 },
8220 {
8221 /* MOD_C6_REG_7 */
8222 { Bad_Opcode },
8223 { RM_TABLE (RM_C6_REG_7) },
8224 },
8225 {
8226 /* MOD_C7_REG_7 */
8227 { Bad_Opcode },
8228 { RM_TABLE (RM_C7_REG_7) },
8229 },
8230 {
8231 /* MOD_FF_REG_3 */
8232 { "{l|}call^", { indirEp }, 0 },
8233 },
8234 {
8235 /* MOD_FF_REG_5 */
8236 { "{l|}jmp^", { indirEp }, 0 },
8237 },
8238 {
8239 /* MOD_0F01_REG_0 */
8240 { X86_64_TABLE (X86_64_0F01_REG_0) },
8241 { RM_TABLE (RM_0F01_REG_0) },
8242 },
8243 {
8244 /* MOD_0F01_REG_1 */
8245 { X86_64_TABLE (X86_64_0F01_REG_1) },
8246 { RM_TABLE (RM_0F01_REG_1) },
8247 },
8248 {
8249 /* MOD_0F01_REG_2 */
8250 { X86_64_TABLE (X86_64_0F01_REG_2) },
8251 { RM_TABLE (RM_0F01_REG_2) },
8252 },
8253 {
8254 /* MOD_0F01_REG_3 */
8255 { X86_64_TABLE (X86_64_0F01_REG_3) },
8256 { RM_TABLE (RM_0F01_REG_3) },
8257 },
8258 {
8259 /* MOD_0F01_REG_5 */
8260 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8261 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8262 },
8263 {
8264 /* MOD_0F01_REG_7 */
8265 { "invlpg", { Mb }, 0 },
8266 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8267 },
8268 {
8269 /* MOD_0F02 */
8270 { "larS", { Gv, Mw }, 0 },
8271 { "larS", { Gv, Ev }, 0 },
8272 },
8273 {
8274 /* MOD_0F03 */
8275 { "lslS", { Gv, Mw }, 0 },
8276 { "lslS", { Gv, Ev }, 0 },
8277 },
8278 {
8279 /* MOD_0F12_PREFIX_0 */
8280 { "movlpX", { XM, EXq }, 0 },
8281 { "movhlps", { XM, EXq }, 0 },
8282 },
8283 {
8284 /* MOD_0F12_PREFIX_2 */
8285 { "movlpX", { XM, EXq }, 0 },
8286 },
8287 {
8288 /* MOD_0F13 */
8289 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
8290 },
8291 {
8292 /* MOD_0F16_PREFIX_0 */
8293 { "movhpX", { XM, EXq }, 0 },
8294 { "movlhps", { XM, EXq }, 0 },
8295 },
8296 {
8297 /* MOD_0F16_PREFIX_2 */
8298 { "movhpX", { XM, EXq }, 0 },
8299 },
8300 {
8301 /* MOD_0F17 */
8302 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
8303 },
8304 {
8305 /* MOD_0F18_REG_0 */
8306 { "prefetchnta", { Mb }, 0 },
8307 { "nopQ", { Ev }, 0 },
8308 },
8309 {
8310 /* MOD_0F18_REG_1 */
8311 { "prefetcht0", { Mb }, 0 },
8312 { "nopQ", { Ev }, 0 },
8313 },
8314 {
8315 /* MOD_0F18_REG_2 */
8316 { "prefetcht1", { Mb }, 0 },
8317 { "nopQ", { Ev }, 0 },
8318 },
8319 {
8320 /* MOD_0F18_REG_3 */
8321 { "prefetcht2", { Mb }, 0 },
8322 { "nopQ", { Ev }, 0 },
8323 },
8324 {
8325 /* MOD_0F18_REG_6 */
8326 { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8327 { "nopQ", { Ev }, 0 },
8328 },
8329 {
8330 /* MOD_0F18_REG_7 */
8331 { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8332 { "nopQ", { Ev }, 0 },
8333 },
8334 {
8335 /* MOD_0F1A_PREFIX_0 */
8336 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8337 { "nopQ", { Ev }, 0 },
8338 },
8339 {
8340 /* MOD_0F1B_PREFIX_0 */
8341 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8342 { "nopQ", { Ev }, 0 },
8343 },
8344 {
8345 /* MOD_0F1B_PREFIX_1 */
8346 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8347 { "nopQ", { Ev }, PREFIX_IGNORED },
8348 },
8349 {
8350 /* MOD_0F1C_PREFIX_0 */
8351 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8352 { "nopQ", { Ev }, 0 },
8353 },
8354 {
8355 /* MOD_0F1E_PREFIX_1 */
8356 { "nopQ", { Ev }, PREFIX_IGNORED },
8357 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8358 },
8359 {
8360 /* MOD_0F2B_PREFIX_0 */
8361 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8362 },
8363 {
8364 /* MOD_0F2B_PREFIX_1 */
8365 {"movntss", { Md, XM }, PREFIX_OPCODE },
8366 },
8367 {
8368 /* MOD_0F2B_PREFIX_2 */
8369 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8370 },
8371 {
8372 /* MOD_0F2B_PREFIX_3 */
8373 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8374 },
8375 {
8376 /* MOD_0F50 */
8377 { Bad_Opcode },
8378 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8379 },
8380 {
8381 /* MOD_0F71 */
8382 { Bad_Opcode },
8383 { REG_TABLE (REG_0F71_MOD_0) },
8384 },
8385 {
8386 /* MOD_0F72 */
8387 { Bad_Opcode },
8388 { REG_TABLE (REG_0F72_MOD_0) },
8389 },
8390 {
8391 /* MOD_0F73 */
8392 { Bad_Opcode },
8393 { REG_TABLE (REG_0F73_MOD_0) },
8394 },
8395 {
8396 /* MOD_0FAE_REG_0 */
8397 { "fxsave", { FXSAVE }, 0 },
8398 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8399 },
8400 {
8401 /* MOD_0FAE_REG_1 */
8402 { "fxrstor", { FXSAVE }, 0 },
8403 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8404 },
8405 {
8406 /* MOD_0FAE_REG_2 */
8407 { "ldmxcsr", { Md }, 0 },
8408 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8409 },
8410 {
8411 /* MOD_0FAE_REG_3 */
8412 { "stmxcsr", { Md }, 0 },
8413 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8414 },
8415 {
8416 /* MOD_0FAE_REG_4 */
8417 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8418 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8419 },
8420 {
8421 /* MOD_0FAE_REG_5 */
8422 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8423 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8424 },
8425 {
8426 /* MOD_0FAE_REG_6 */
8427 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8428 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8429 },
8430 {
8431 /* MOD_0FAE_REG_7 */
8432 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8433 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8434 },
8435 {
8436 /* MOD_0FB2 */
8437 { "lssS", { Gv, Mp }, 0 },
8438 },
8439 {
8440 /* MOD_0FB4 */
8441 { "lfsS", { Gv, Mp }, 0 },
8442 },
8443 {
8444 /* MOD_0FB5 */
8445 { "lgsS", { Gv, Mp }, 0 },
8446 },
8447 {
8448 /* MOD_0FC3 */
8449 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8450 },
8451 {
8452 /* MOD_0FC7_REG_3 */
8453 { "xrstors", { FXSAVE }, 0 },
8454 },
8455 {
8456 /* MOD_0FC7_REG_4 */
8457 { "xsavec", { FXSAVE }, 0 },
8458 },
8459 {
8460 /* MOD_0FC7_REG_5 */
8461 { "xsaves", { FXSAVE }, 0 },
8462 },
8463 {
8464 /* MOD_0FC7_REG_6 */
8465 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8466 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8467 },
8468 {
8469 /* MOD_0FC7_REG_7 */
8470 { "vmptrst", { Mq }, 0 },
8471 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8472 },
8473 {
8474 /* MOD_0FD7 */
8475 { Bad_Opcode },
8476 { "pmovmskb", { Gdq, MS }, 0 },
8477 },
8478 {
8479 /* MOD_0FE7_PREFIX_2 */
8480 { "movntdq", { Mx, XM }, 0 },
8481 },
8482 {
8483 /* MOD_0FF0_PREFIX_3 */
8484 { "lddqu", { XM, M }, 0 },
8485 },
8486 {
8487 /* MOD_0F382A */
8488 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8489 },
8490 {
8491 /* MOD_0F38DC_PREFIX_1 */
8492 { "aesenc128kl", { XM, M }, 0 },
8493 { "loadiwkey", { XM, EXx }, 0 },
8494 },
8495 {
8496 /* MOD_0F38DD_PREFIX_1 */
8497 { "aesdec128kl", { XM, M }, 0 },
8498 },
8499 {
8500 /* MOD_0F38DE_PREFIX_1 */
8501 { "aesenc256kl", { XM, M }, 0 },
8502 },
8503 {
8504 /* MOD_0F38DF_PREFIX_1 */
8505 { "aesdec256kl", { XM, M }, 0 },
8506 },
8507 {
8508 /* MOD_0F38F5 */
8509 { "wrussK", { M, Gdq }, PREFIX_DATA },
8510 },
8511 {
8512 /* MOD_0F38F6_PREFIX_0 */
8513 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8514 },
8515 {
8516 /* MOD_0F38F8_PREFIX_1 */
8517 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8518 },
8519 {
8520 /* MOD_0F38F8_PREFIX_2 */
8521 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8522 },
8523 {
8524 /* MOD_0F38F8_PREFIX_3 */
8525 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8526 },
8527 {
8528 /* MOD_0F38F9 */
8529 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8530 },
8531 {
8532 /* MOD_0F38FA_PREFIX_1 */
8533 { Bad_Opcode },
8534 { "encodekey128", { Gd, Ed }, 0 },
8535 },
8536 {
8537 /* MOD_0F38FB_PREFIX_1 */
8538 { Bad_Opcode },
8539 { "encodekey256", { Gd, Ed }, 0 },
8540 },
8541 {
8542 /* MOD_0F3A0F_PREFIX_1 */
8543 { Bad_Opcode },
8544 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8545 },
8546 {
8547 /* MOD_VEX_0F12_PREFIX_0 */
8548 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8549 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8550 },
8551 {
8552 /* MOD_VEX_0F12_PREFIX_2 */
8553 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8554 },
8555 {
8556 /* MOD_VEX_0F13 */
8557 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8558 },
8559 {
8560 /* MOD_VEX_0F16_PREFIX_0 */
8561 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8562 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8563 },
8564 {
8565 /* MOD_VEX_0F16_PREFIX_2 */
8566 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8567 },
8568 {
8569 /* MOD_VEX_0F17 */
8570 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8571 },
8572 {
8573 /* MOD_VEX_0F2B */
8574 { "%XEvmovntpX", { Mx, XM }, PREFIX_OPCODE },
8575 },
8576 {
8577 /* MOD_VEX_0F41_L_1 */
8578 { Bad_Opcode },
8579 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8580 },
8581 {
8582 /* MOD_VEX_0F42_L_1 */
8583 { Bad_Opcode },
8584 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8585 },
8586 {
8587 /* MOD_VEX_0F44_L_0 */
8588 { Bad_Opcode },
8589 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8590 },
8591 {
8592 /* MOD_VEX_0F45_L_1 */
8593 { Bad_Opcode },
8594 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8595 },
8596 {
8597 /* MOD_VEX_0F46_L_1 */
8598 { Bad_Opcode },
8599 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8600 },
8601 {
8602 /* MOD_VEX_0F47_L_1 */
8603 { Bad_Opcode },
8604 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8605 },
8606 {
8607 /* MOD_VEX_0F4A_L_1 */
8608 { Bad_Opcode },
8609 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8610 },
8611 {
8612 /* MOD_VEX_0F4B_L_1 */
8613 { Bad_Opcode },
8614 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8615 },
8616 {
8617 /* MOD_VEX_0F50 */
8618 { Bad_Opcode },
8619 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8620 },
8621 {
8622 /* MOD_VEX_0F71 */
8623 { Bad_Opcode },
8624 { REG_TABLE (REG_VEX_0F71_M_0) },
8625 },
8626 {
8627 /* MOD_VEX_0F72 */
8628 { Bad_Opcode },
8629 { REG_TABLE (REG_VEX_0F72_M_0) },
8630 },
8631 {
8632 /* MOD_VEX_0F73 */
8633 { Bad_Opcode },
8634 { REG_TABLE (REG_VEX_0F73_M_0) },
8635 },
8636 {
8637 /* MOD_VEX_0F91_L_0 */
8638 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8639 },
8640 {
8641 /* MOD_VEX_0F92_L_0 */
8642 { Bad_Opcode },
8643 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8644 },
8645 {
8646 /* MOD_VEX_0F93_L_0 */
8647 { Bad_Opcode },
8648 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8649 },
8650 {
8651 /* MOD_VEX_0F98_L_0 */
8652 { Bad_Opcode },
8653 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8654 },
8655 {
8656 /* MOD_VEX_0F99_L_0 */
8657 { Bad_Opcode },
8658 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8659 },
8660 {
8661 /* MOD_VEX_0FAE_REG_2 */
8662 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8663 },
8664 {
8665 /* MOD_VEX_0FAE_REG_3 */
8666 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8667 },
8668 {
8669 /* MOD_VEX_0FD7 */
8670 { Bad_Opcode },
8671 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8672 },
8673 {
8674 /* MOD_VEX_0FE7 */
8675 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8676 },
8677 {
8678 /* MOD_VEX_0FF0_PREFIX_3 */
8679 { "vlddqu", { XM, M }, 0 },
8680 },
8681 {
8682 /* MOD_VEX_0F381A */
8683 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8684 },
8685 {
8686 /* MOD_VEX_0F382A */
8687 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8688 },
8689 {
8690 /* MOD_VEX_0F382C */
8691 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8692 },
8693 {
8694 /* MOD_VEX_0F382D */
8695 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8696 },
8697 {
8698 /* MOD_VEX_0F382E */
8699 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8700 },
8701 {
8702 /* MOD_VEX_0F382F */
8703 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8704 },
8705 {
8706 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8707 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8708 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8709 },
8710 {
8711 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8712 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8713 },
8714 {
8715 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8716 { Bad_Opcode },
8717 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8718 },
8719 {
8720 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8721 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8722 },
8723 {
8724 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8725 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8726 },
8727 {
8728 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8729 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8730 },
8731 {
8732 /* MOD_VEX_0F385A */
8733 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8734 },
8735 {
8736 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8737 { Bad_Opcode },
8738 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8739 },
8740 {
8741 /* MOD_VEX_0F385C_X86_64_P_3_W_0 */
8742 { Bad_Opcode },
8743 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0) },
8744 },
8745 {
8746 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8747 { Bad_Opcode },
8748 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8749 },
8750 {
8751 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8752 { Bad_Opcode },
8753 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8754 },
8755 {
8756 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8757 { Bad_Opcode },
8758 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8759 },
8760 {
8761 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8762 { Bad_Opcode },
8763 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8764 },
8765 {
8766 /* MOD_VEX_0F386C_X86_64_W_0 */
8767 { Bad_Opcode },
8768 { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64_W_0_M_1) },
8769 },
8770 {
8771 /* MOD_VEX_0F388C */
8772 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8773 },
8774 {
8775 /* MOD_VEX_0F388E */
8776 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8777 },
8778 {
8779 /* MOD_VEX_0F3A30_L_0 */
8780 { Bad_Opcode },
8781 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8782 },
8783 {
8784 /* MOD_VEX_0F3A31_L_0 */
8785 { Bad_Opcode },
8786 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8787 },
8788 {
8789 /* MOD_VEX_0F3A32_L_0 */
8790 { Bad_Opcode },
8791 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8792 },
8793 {
8794 /* MOD_VEX_0F3A33_L_0 */
8795 { Bad_Opcode },
8796 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8797 },
8798 {
8799 /* MOD_XOP_09_12 */
8800 { Bad_Opcode },
8801 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8802 },
8803
8804 #include "i386-dis-evex-mod.h"
8805 };
8806
8807 static const struct dis386 rm_table[][8] = {
8808 {
8809 /* RM_C6_REG_7 */
8810 { "xabort", { Skip_MODRM, Ib }, 0 },
8811 },
8812 {
8813 /* RM_C7_REG_7 */
8814 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8815 },
8816 {
8817 /* RM_0F01_REG_0 */
8818 { "enclv", { Skip_MODRM }, 0 },
8819 { "vmcall", { Skip_MODRM }, 0 },
8820 { "vmlaunch", { Skip_MODRM }, 0 },
8821 { "vmresume", { Skip_MODRM }, 0 },
8822 { "vmxoff", { Skip_MODRM }, 0 },
8823 { "pconfig", { Skip_MODRM }, 0 },
8824 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8825 },
8826 {
8827 /* RM_0F01_REG_1 */
8828 { "monitor", { { OP_Monitor, 0 } }, 0 },
8829 { "mwait", { { OP_Mwait, 0 } }, 0 },
8830 { "clac", { Skip_MODRM }, 0 },
8831 { "stac", { Skip_MODRM }, 0 },
8832 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8833 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8834 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8835 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8836 },
8837 {
8838 /* RM_0F01_REG_2 */
8839 { "xgetbv", { Skip_MODRM }, 0 },
8840 { "xsetbv", { Skip_MODRM }, 0 },
8841 { Bad_Opcode },
8842 { Bad_Opcode },
8843 { "vmfunc", { Skip_MODRM }, 0 },
8844 { "xend", { Skip_MODRM }, 0 },
8845 { "xtest", { Skip_MODRM }, 0 },
8846 { "enclu", { Skip_MODRM }, 0 },
8847 },
8848 {
8849 /* RM_0F01_REG_3 */
8850 { "vmrun", { Skip_MODRM }, 0 },
8851 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8852 { "vmload", { Skip_MODRM }, 0 },
8853 { "vmsave", { Skip_MODRM }, 0 },
8854 { "stgi", { Skip_MODRM }, 0 },
8855 { "clgi", { Skip_MODRM }, 0 },
8856 { "skinit", { Skip_MODRM }, 0 },
8857 { "invlpga", { Skip_MODRM }, 0 },
8858 },
8859 {
8860 /* RM_0F01_REG_5_MOD_3 */
8861 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8862 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8863 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8864 { Bad_Opcode },
8865 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8866 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8867 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8868 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8869 },
8870 {
8871 /* RM_0F01_REG_7_MOD_3 */
8872 { "swapgs", { Skip_MODRM }, 0 },
8873 { "rdtscp", { Skip_MODRM }, 0 },
8874 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8875 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8876 { "clzero", { Skip_MODRM }, 0 },
8877 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8878 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8879 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8880 },
8881 {
8882 /* RM_0F1E_P_1_MOD_3_REG_7 */
8883 { "nopQ", { Ev }, PREFIX_IGNORED },
8884 { "nopQ", { Ev }, PREFIX_IGNORED },
8885 { "endbr64", { Skip_MODRM }, 0 },
8886 { "endbr32", { Skip_MODRM }, 0 },
8887 { "nopQ", { Ev }, PREFIX_IGNORED },
8888 { "nopQ", { Ev }, PREFIX_IGNORED },
8889 { "nopQ", { Ev }, PREFIX_IGNORED },
8890 { "nopQ", { Ev }, PREFIX_IGNORED },
8891 },
8892 {
8893 /* RM_0FAE_REG_6_MOD_3 */
8894 { "mfence", { Skip_MODRM }, 0 },
8895 },
8896 {
8897 /* RM_0FAE_REG_7_MOD_3 */
8898 { "sfence", { Skip_MODRM }, 0 },
8899 },
8900 {
8901 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8902 { "hreset", { Skip_MODRM, Ib }, 0 },
8903 },
8904 {
8905 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8906 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8907 },
8908 };
8909
8910 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8911
8912 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8913 in conflict with actual prefix opcodes. */
8914 #define REP_PREFIX 0x01
8915 #define XACQUIRE_PREFIX 0x02
8916 #define XRELEASE_PREFIX 0x03
8917 #define BND_PREFIX 0x04
8918 #define NOTRACK_PREFIX 0x05
8919
8920 static enum {
8921 ckp_okay,
8922 ckp_bogus,
8923 ckp_fetch_error,
8924 }
8925 ckprefix (instr_info *ins)
8926 {
8927 int newrex, i, length;
8928
8929 i = 0;
8930 length = 0;
8931 /* The maximum instruction length is 15bytes. */
8932 while (length < MAX_CODE_LENGTH - 1)
8933 {
8934 if (!fetch_code (ins->info, ins->codep + 1))
8935 return ckp_fetch_error;
8936 newrex = 0;
8937 switch (*ins->codep)
8938 {
8939 /* REX prefixes family. */
8940 case 0x40:
8941 case 0x41:
8942 case 0x42:
8943 case 0x43:
8944 case 0x44:
8945 case 0x45:
8946 case 0x46:
8947 case 0x47:
8948 case 0x48:
8949 case 0x49:
8950 case 0x4a:
8951 case 0x4b:
8952 case 0x4c:
8953 case 0x4d:
8954 case 0x4e:
8955 case 0x4f:
8956 if (ins->address_mode == mode_64bit)
8957 newrex = *ins->codep;
8958 else
8959 return ckp_okay;
8960 ins->last_rex_prefix = i;
8961 break;
8962 case 0xf3:
8963 ins->prefixes |= PREFIX_REPZ;
8964 ins->last_repz_prefix = i;
8965 break;
8966 case 0xf2:
8967 ins->prefixes |= PREFIX_REPNZ;
8968 ins->last_repnz_prefix = i;
8969 break;
8970 case 0xf0:
8971 ins->prefixes |= PREFIX_LOCK;
8972 ins->last_lock_prefix = i;
8973 break;
8974 case 0x2e:
8975 ins->prefixes |= PREFIX_CS;
8976 ins->last_seg_prefix = i;
8977 if (ins->address_mode != mode_64bit)
8978 ins->active_seg_prefix = PREFIX_CS;
8979 break;
8980 case 0x36:
8981 ins->prefixes |= PREFIX_SS;
8982 ins->last_seg_prefix = i;
8983 if (ins->address_mode != mode_64bit)
8984 ins->active_seg_prefix = PREFIX_SS;
8985 break;
8986 case 0x3e:
8987 ins->prefixes |= PREFIX_DS;
8988 ins->last_seg_prefix = i;
8989 if (ins->address_mode != mode_64bit)
8990 ins->active_seg_prefix = PREFIX_DS;
8991 break;
8992 case 0x26:
8993 ins->prefixes |= PREFIX_ES;
8994 ins->last_seg_prefix = i;
8995 if (ins->address_mode != mode_64bit)
8996 ins->active_seg_prefix = PREFIX_ES;
8997 break;
8998 case 0x64:
8999 ins->prefixes |= PREFIX_FS;
9000 ins->last_seg_prefix = i;
9001 ins->active_seg_prefix = PREFIX_FS;
9002 break;
9003 case 0x65:
9004 ins->prefixes |= PREFIX_GS;
9005 ins->last_seg_prefix = i;
9006 ins->active_seg_prefix = PREFIX_GS;
9007 break;
9008 case 0x66:
9009 ins->prefixes |= PREFIX_DATA;
9010 ins->last_data_prefix = i;
9011 break;
9012 case 0x67:
9013 ins->prefixes |= PREFIX_ADDR;
9014 ins->last_addr_prefix = i;
9015 break;
9016 case FWAIT_OPCODE:
9017 /* fwait is really an instruction. If there are prefixes
9018 before the fwait, they belong to the fwait, *not* to the
9019 following instruction. */
9020 ins->fwait_prefix = i;
9021 if (ins->prefixes || ins->rex)
9022 {
9023 ins->prefixes |= PREFIX_FWAIT;
9024 ins->codep++;
9025 /* This ensures that the previous REX prefixes are noticed
9026 as unused prefixes, as in the return case below. */
9027 return ins->rex ? ckp_bogus : ckp_okay;
9028 }
9029 ins->prefixes = PREFIX_FWAIT;
9030 break;
9031 default:
9032 return ckp_okay;
9033 }
9034 /* Rex is ignored when followed by another prefix. */
9035 if (ins->rex)
9036 return ckp_bogus;
9037 if (*ins->codep != FWAIT_OPCODE)
9038 ins->all_prefixes[i++] = *ins->codep;
9039 ins->rex = newrex;
9040 ins->codep++;
9041 length++;
9042 }
9043 return ckp_bogus;
9044 }
9045
9046 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9047 prefix byte. */
9048
9049 static const char *
9050 prefix_name (const instr_info *ins, int pref, int sizeflag)
9051 {
9052 static const char *rexes [16] =
9053 {
9054 "rex", /* 0x40 */
9055 "rex.B", /* 0x41 */
9056 "rex.X", /* 0x42 */
9057 "rex.XB", /* 0x43 */
9058 "rex.R", /* 0x44 */
9059 "rex.RB", /* 0x45 */
9060 "rex.RX", /* 0x46 */
9061 "rex.RXB", /* 0x47 */
9062 "rex.W", /* 0x48 */
9063 "rex.WB", /* 0x49 */
9064 "rex.WX", /* 0x4a */
9065 "rex.WXB", /* 0x4b */
9066 "rex.WR", /* 0x4c */
9067 "rex.WRB", /* 0x4d */
9068 "rex.WRX", /* 0x4e */
9069 "rex.WRXB", /* 0x4f */
9070 };
9071
9072 switch (pref)
9073 {
9074 /* REX prefixes family. */
9075 case 0x40:
9076 case 0x41:
9077 case 0x42:
9078 case 0x43:
9079 case 0x44:
9080 case 0x45:
9081 case 0x46:
9082 case 0x47:
9083 case 0x48:
9084 case 0x49:
9085 case 0x4a:
9086 case 0x4b:
9087 case 0x4c:
9088 case 0x4d:
9089 case 0x4e:
9090 case 0x4f:
9091 return rexes [pref - 0x40];
9092 case 0xf3:
9093 return "repz";
9094 case 0xf2:
9095 return "repnz";
9096 case 0xf0:
9097 return "lock";
9098 case 0x2e:
9099 return "cs";
9100 case 0x36:
9101 return "ss";
9102 case 0x3e:
9103 return "ds";
9104 case 0x26:
9105 return "es";
9106 case 0x64:
9107 return "fs";
9108 case 0x65:
9109 return "gs";
9110 case 0x66:
9111 return (sizeflag & DFLAG) ? "data16" : "data32";
9112 case 0x67:
9113 if (ins->address_mode == mode_64bit)
9114 return (sizeflag & AFLAG) ? "addr32" : "addr64";
9115 else
9116 return (sizeflag & AFLAG) ? "addr16" : "addr32";
9117 case FWAIT_OPCODE:
9118 return "fwait";
9119 case REP_PREFIX:
9120 return "rep";
9121 case XACQUIRE_PREFIX:
9122 return "xacquire";
9123 case XRELEASE_PREFIX:
9124 return "xrelease";
9125 case BND_PREFIX:
9126 return "bnd";
9127 case NOTRACK_PREFIX:
9128 return "notrack";
9129 default:
9130 return NULL;
9131 }
9132 }
9133
9134 void
9135 print_i386_disassembler_options (FILE *stream)
9136 {
9137 fprintf (stream, _("\n\
9138 The following i386/x86-64 specific disassembler options are supported for use\n\
9139 with the -M switch (multiple options should be separated by commas):\n"));
9140
9141 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9142 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9143 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9144 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9145 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9146 fprintf (stream, _(" att-mnemonic\n"
9147 " Display instruction in AT&T mnemonic\n"));
9148 fprintf (stream, _(" intel-mnemonic\n"
9149 " Display instruction in Intel mnemonic\n"));
9150 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9151 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9152 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9153 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9154 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9155 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9156 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
9157 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
9158 }
9159
9160 /* Bad opcode. */
9161 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9162
9163 /* Fetch error indicator. */
9164 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
9165
9166 /* Get a pointer to struct dis386 with a valid name. */
9167
9168 static const struct dis386 *
9169 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
9170 {
9171 int vindex, vex_table_index;
9172
9173 if (dp->name != NULL)
9174 return dp;
9175
9176 switch (dp->op[0].bytemode)
9177 {
9178 case USE_REG_TABLE:
9179 dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
9180 break;
9181
9182 case USE_MOD_TABLE:
9183 vindex = ins->modrm.mod == 0x3 ? 1 : 0;
9184 dp = &mod_table[dp->op[1].bytemode][vindex];
9185 break;
9186
9187 case USE_RM_TABLE:
9188 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
9189 break;
9190
9191 case USE_PREFIX_TABLE:
9192 if (ins->need_vex)
9193 {
9194 /* The prefix in VEX is implicit. */
9195 switch (ins->vex.prefix)
9196 {
9197 case 0:
9198 vindex = 0;
9199 break;
9200 case REPE_PREFIX_OPCODE:
9201 vindex = 1;
9202 break;
9203 case DATA_PREFIX_OPCODE:
9204 vindex = 2;
9205 break;
9206 case REPNE_PREFIX_OPCODE:
9207 vindex = 3;
9208 break;
9209 default:
9210 abort ();
9211 break;
9212 }
9213 }
9214 else
9215 {
9216 int last_prefix = -1;
9217 int prefix = 0;
9218 vindex = 0;
9219 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9220 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9221 last one wins. */
9222 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9223 {
9224 if (ins->last_repz_prefix > ins->last_repnz_prefix)
9225 {
9226 vindex = 1;
9227 prefix = PREFIX_REPZ;
9228 last_prefix = ins->last_repz_prefix;
9229 }
9230 else
9231 {
9232 vindex = 3;
9233 prefix = PREFIX_REPNZ;
9234 last_prefix = ins->last_repnz_prefix;
9235 }
9236
9237 /* Check if prefix should be ignored. */
9238 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9239 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9240 & prefix) != 0
9241 && !prefix_table[dp->op[1].bytemode][vindex].name)
9242 vindex = 0;
9243 }
9244
9245 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
9246 {
9247 vindex = 2;
9248 prefix = PREFIX_DATA;
9249 last_prefix = ins->last_data_prefix;
9250 }
9251
9252 if (vindex != 0)
9253 {
9254 ins->used_prefixes |= prefix;
9255 ins->all_prefixes[last_prefix] = 0;
9256 }
9257 }
9258 dp = &prefix_table[dp->op[1].bytemode][vindex];
9259 break;
9260
9261 case USE_X86_64_TABLE:
9262 vindex = ins->address_mode == mode_64bit ? 1 : 0;
9263 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9264 break;
9265
9266 case USE_3BYTE_TABLE:
9267 if (!fetch_code (ins->info, ins->codep + 2))
9268 return &err_opcode;
9269 vindex = *ins->codep++;
9270 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9271 ins->end_codep = ins->codep;
9272 if (!fetch_modrm (ins))
9273 return &err_opcode;
9274 break;
9275
9276 case USE_VEX_LEN_TABLE:
9277 if (!ins->need_vex)
9278 abort ();
9279
9280 switch (ins->vex.length)
9281 {
9282 case 128:
9283 vindex = 0;
9284 break;
9285 case 512:
9286 /* This allows re-using in particular table entries where only
9287 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
9288 if (ins->vex.evex)
9289 {
9290 case 256:
9291 vindex = 1;
9292 break;
9293 }
9294 /* Fall through. */
9295 default:
9296 abort ();
9297 break;
9298 }
9299
9300 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9301 break;
9302
9303 case USE_EVEX_LEN_TABLE:
9304 if (!ins->vex.evex)
9305 abort ();
9306
9307 switch (ins->vex.length)
9308 {
9309 case 128:
9310 vindex = 0;
9311 break;
9312 case 256:
9313 vindex = 1;
9314 break;
9315 case 512:
9316 vindex = 2;
9317 break;
9318 default:
9319 abort ();
9320 break;
9321 }
9322
9323 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9324 break;
9325
9326 case USE_XOP_8F_TABLE:
9327 if (!fetch_code (ins->info, ins->codep + 3))
9328 return &err_opcode;
9329 ins->rex = ~(*ins->codep >> 5) & 0x7;
9330
9331 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9332 switch ((*ins->codep & 0x1f))
9333 {
9334 default:
9335 dp = &bad_opcode;
9336 return dp;
9337 case 0x8:
9338 vex_table_index = XOP_08;
9339 break;
9340 case 0x9:
9341 vex_table_index = XOP_09;
9342 break;
9343 case 0xa:
9344 vex_table_index = XOP_0A;
9345 break;
9346 }
9347 ins->codep++;
9348 ins->vex.w = *ins->codep & 0x80;
9349 if (ins->vex.w && ins->address_mode == mode_64bit)
9350 ins->rex |= REX_W;
9351
9352 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9353 if (ins->address_mode != mode_64bit)
9354 {
9355 /* In 16/32-bit mode REX_B is silently ignored. */
9356 ins->rex &= ~REX_B;
9357 }
9358
9359 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9360 switch ((*ins->codep & 0x3))
9361 {
9362 case 0:
9363 break;
9364 case 1:
9365 ins->vex.prefix = DATA_PREFIX_OPCODE;
9366 break;
9367 case 2:
9368 ins->vex.prefix = REPE_PREFIX_OPCODE;
9369 break;
9370 case 3:
9371 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9372 break;
9373 }
9374 ins->need_vex = true;
9375 ins->codep++;
9376 vindex = *ins->codep++;
9377 dp = &xop_table[vex_table_index][vindex];
9378
9379 ins->end_codep = ins->codep;
9380 if (!fetch_modrm (ins))
9381 return &err_opcode;
9382
9383 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9384 having to decode the bits for every otherwise valid encoding. */
9385 if (ins->vex.prefix)
9386 return &bad_opcode;
9387 break;
9388
9389 case USE_VEX_C4_TABLE:
9390 /* VEX prefix. */
9391 if (!fetch_code (ins->info, ins->codep + 3))
9392 return &err_opcode;
9393 ins->rex = ~(*ins->codep >> 5) & 0x7;
9394 switch ((*ins->codep & 0x1f))
9395 {
9396 default:
9397 dp = &bad_opcode;
9398 return dp;
9399 case 0x1:
9400 vex_table_index = VEX_0F;
9401 break;
9402 case 0x2:
9403 vex_table_index = VEX_0F38;
9404 break;
9405 case 0x3:
9406 vex_table_index = VEX_0F3A;
9407 break;
9408 }
9409 ins->codep++;
9410 ins->vex.w = *ins->codep & 0x80;
9411 if (ins->address_mode == mode_64bit)
9412 {
9413 if (ins->vex.w)
9414 ins->rex |= REX_W;
9415 }
9416 else
9417 {
9418 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9419 is ignored, other REX bits are 0 and the highest bit in
9420 VEX.vvvv is also ignored (but we mustn't clear it here). */
9421 ins->rex = 0;
9422 }
9423 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9424 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9425 switch ((*ins->codep & 0x3))
9426 {
9427 case 0:
9428 break;
9429 case 1:
9430 ins->vex.prefix = DATA_PREFIX_OPCODE;
9431 break;
9432 case 2:
9433 ins->vex.prefix = REPE_PREFIX_OPCODE;
9434 break;
9435 case 3:
9436 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9437 break;
9438 }
9439 ins->need_vex = true;
9440 ins->codep++;
9441 vindex = *ins->codep++;
9442 dp = &vex_table[vex_table_index][vindex];
9443 ins->end_codep = ins->codep;
9444 /* There is no MODRM byte for VEX0F 77. */
9445 if ((vex_table_index != VEX_0F || vindex != 0x77)
9446 && !fetch_modrm (ins))
9447 return &err_opcode;
9448 break;
9449
9450 case USE_VEX_C5_TABLE:
9451 /* VEX prefix. */
9452 if (!fetch_code (ins->info, ins->codep + 2))
9453 return &err_opcode;
9454 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9455
9456 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9457 VEX.vvvv is 1. */
9458 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9459 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9460 switch ((*ins->codep & 0x3))
9461 {
9462 case 0:
9463 break;
9464 case 1:
9465 ins->vex.prefix = DATA_PREFIX_OPCODE;
9466 break;
9467 case 2:
9468 ins->vex.prefix = REPE_PREFIX_OPCODE;
9469 break;
9470 case 3:
9471 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9472 break;
9473 }
9474 ins->need_vex = true;
9475 ins->codep++;
9476 vindex = *ins->codep++;
9477 dp = &vex_table[dp->op[1].bytemode][vindex];
9478 ins->end_codep = ins->codep;
9479 /* There is no MODRM byte for VEX 77. */
9480 if (vindex != 0x77 && !fetch_modrm (ins))
9481 return &err_opcode;
9482 break;
9483
9484 case USE_VEX_W_TABLE:
9485 if (!ins->need_vex)
9486 abort ();
9487
9488 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9489 break;
9490
9491 case USE_EVEX_TABLE:
9492 ins->two_source_ops = false;
9493 /* EVEX prefix. */
9494 ins->vex.evex = true;
9495 if (!fetch_code (ins->info, ins->codep + 4))
9496 return &err_opcode;
9497 /* The first byte after 0x62. */
9498 ins->rex = ~(*ins->codep >> 5) & 0x7;
9499 ins->vex.r = *ins->codep & 0x10;
9500 switch ((*ins->codep & 0xf))
9501 {
9502 default:
9503 return &bad_opcode;
9504 case 0x1:
9505 vex_table_index = EVEX_0F;
9506 break;
9507 case 0x2:
9508 vex_table_index = EVEX_0F38;
9509 break;
9510 case 0x3:
9511 vex_table_index = EVEX_0F3A;
9512 break;
9513 case 0x5:
9514 vex_table_index = EVEX_MAP5;
9515 break;
9516 case 0x6:
9517 vex_table_index = EVEX_MAP6;
9518 break;
9519 }
9520
9521 /* The second byte after 0x62. */
9522 ins->codep++;
9523 ins->vex.w = *ins->codep & 0x80;
9524 if (ins->vex.w && ins->address_mode == mode_64bit)
9525 ins->rex |= REX_W;
9526
9527 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9528
9529 /* The U bit. */
9530 if (!(*ins->codep & 0x4))
9531 return &bad_opcode;
9532
9533 switch ((*ins->codep & 0x3))
9534 {
9535 case 0:
9536 break;
9537 case 1:
9538 ins->vex.prefix = DATA_PREFIX_OPCODE;
9539 break;
9540 case 2:
9541 ins->vex.prefix = REPE_PREFIX_OPCODE;
9542 break;
9543 case 3:
9544 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9545 break;
9546 }
9547
9548 /* The third byte after 0x62. */
9549 ins->codep++;
9550
9551 /* Remember the static rounding bits. */
9552 ins->vex.ll = (*ins->codep >> 5) & 3;
9553 ins->vex.b = *ins->codep & 0x10;
9554
9555 ins->vex.v = *ins->codep & 0x8;
9556 ins->vex.mask_register_specifier = *ins->codep & 0x7;
9557 ins->vex.zeroing = *ins->codep & 0x80;
9558
9559 if (ins->address_mode != mode_64bit)
9560 {
9561 /* In 16/32-bit mode silently ignore following bits. */
9562 ins->rex &= ~REX_B;
9563 ins->vex.r = true;
9564 }
9565
9566 ins->need_vex = true;
9567 ins->codep++;
9568 vindex = *ins->codep++;
9569 dp = &evex_table[vex_table_index][vindex];
9570 ins->end_codep = ins->codep;
9571 if (!fetch_modrm (ins))
9572 return &err_opcode;
9573
9574 /* Set vector length. */
9575 if (ins->modrm.mod == 3 && ins->vex.b)
9576 ins->vex.length = 512;
9577 else
9578 {
9579 switch (ins->vex.ll)
9580 {
9581 case 0x0:
9582 ins->vex.length = 128;
9583 break;
9584 case 0x1:
9585 ins->vex.length = 256;
9586 break;
9587 case 0x2:
9588 ins->vex.length = 512;
9589 break;
9590 default:
9591 return &bad_opcode;
9592 }
9593 }
9594 break;
9595
9596 case 0:
9597 dp = &bad_opcode;
9598 break;
9599
9600 default:
9601 abort ();
9602 }
9603
9604 if (dp->name != NULL)
9605 return dp;
9606 else
9607 return get_valid_dis386 (dp, ins);
9608 }
9609
9610 static bool
9611 get_sib (instr_info *ins, int sizeflag)
9612 {
9613 /* If modrm.mod == 3, operand must be register. */
9614 if (ins->need_modrm
9615 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9616 && ins->modrm.mod != 3
9617 && ins->modrm.rm == 4)
9618 {
9619 if (!fetch_code (ins->info, ins->codep + 2))
9620 return false;
9621 ins->sib.index = (ins->codep[1] >> 3) & 7;
9622 ins->sib.scale = (ins->codep[1] >> 6) & 3;
9623 ins->sib.base = ins->codep[1] & 7;
9624 ins->has_sib = true;
9625 }
9626 else
9627 ins->has_sib = false;
9628
9629 return true;
9630 }
9631
9632 /* Like oappend (below), but S is a string starting with '%'. In
9633 Intel syntax, the '%' is elided. */
9634
9635 static void
9636 oappend_register (instr_info *ins, const char *s)
9637 {
9638 oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9639 }
9640
9641 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9642 STYLE is the default style to use in the fprintf_styled_func calls,
9643 however, FMT might include embedded style markers (see oappend_style),
9644 these embedded markers are not printed, but instead change the style
9645 used in the next fprintf_styled_func call. */
9646
9647 static void ATTRIBUTE_PRINTF_3
9648 i386_dis_printf (const instr_info *ins, enum disassembler_style style,
9649 const char *fmt, ...)
9650 {
9651 va_list ap;
9652 enum disassembler_style curr_style = style;
9653 const char *start, *curr;
9654 char staging_area[40];
9655
9656 va_start (ap, fmt);
9657 /* In particular print_insn()'s processing of op_txt[] can hand rather long
9658 strings here. Bypass vsnprintf() in such cases to avoid capacity issues
9659 with the staging area. */
9660 if (strcmp (fmt, "%s"))
9661 {
9662 int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9663
9664 va_end (ap);
9665
9666 if (res < 0)
9667 return;
9668
9669 if ((size_t) res >= sizeof (staging_area))
9670 abort ();
9671
9672 start = curr = staging_area;
9673 }
9674 else
9675 {
9676 start = curr = va_arg (ap, const char *);
9677 va_end (ap);
9678 }
9679
9680 do
9681 {
9682 if (*curr == '\0'
9683 || (*curr == STYLE_MARKER_CHAR
9684 && ISXDIGIT (*(curr + 1))
9685 && *(curr + 2) == STYLE_MARKER_CHAR))
9686 {
9687 /* Output content between our START position and CURR. */
9688 int len = curr - start;
9689 int n = (*ins->info->fprintf_styled_func) (ins->info->stream,
9690 curr_style,
9691 "%.*s", len, start);
9692 if (n < 0)
9693 break;
9694
9695 if (*curr == '\0')
9696 break;
9697
9698 /* Skip over the initial STYLE_MARKER_CHAR. */
9699 ++curr;
9700
9701 /* Update the CURR_STYLE. As there are less than 16 styles, it
9702 is possible, that if the input is corrupted in some way, that
9703 we might set CURR_STYLE to an invalid value. Don't worry
9704 though, we check for this situation. */
9705 if (*curr >= '0' && *curr <= '9')
9706 curr_style = (enum disassembler_style) (*curr - '0');
9707 else if (*curr >= 'a' && *curr <= 'f')
9708 curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9709 else
9710 curr_style = dis_style_text;
9711
9712 /* Check for an invalid style having been selected. This should
9713 never happen, but it doesn't hurt to be a little paranoid. */
9714 if (curr_style > dis_style_comment_start)
9715 curr_style = dis_style_text;
9716
9717 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */
9718 curr += 2;
9719
9720 /* Reset the START to after the style marker. */
9721 start = curr;
9722 }
9723 else
9724 ++curr;
9725 }
9726 while (true);
9727 }
9728
9729 static int
9730 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9731 {
9732 const struct dis386 *dp;
9733 int i;
9734 char *op_txt[MAX_OPERANDS];
9735 int needcomma;
9736 bool intel_swap_2_3;
9737 int sizeflag, orig_sizeflag;
9738 const char *p;
9739 struct dis_private priv;
9740 int prefix_length;
9741 int op_count;
9742 instr_info ins = {
9743 .info = info,
9744 .intel_syntax = intel_syntax >= 0
9745 ? intel_syntax
9746 : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9747 .intel_mnemonic = !SYSV386_COMPAT,
9748 .op_index[0 ... MAX_OPERANDS - 1] = -1,
9749 .start_pc = pc,
9750 .start_codep = priv.the_buffer,
9751 .codep = priv.the_buffer,
9752 .obufp = ins.obuf,
9753 .last_lock_prefix = -1,
9754 .last_repz_prefix = -1,
9755 .last_repnz_prefix = -1,
9756 .last_data_prefix = -1,
9757 .last_addr_prefix = -1,
9758 .last_rex_prefix = -1,
9759 .last_seg_prefix = -1,
9760 .fwait_prefix = -1,
9761 };
9762 char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9763
9764 priv.orig_sizeflag = AFLAG | DFLAG;
9765 if ((info->mach & bfd_mach_i386_i386) != 0)
9766 ins.address_mode = mode_32bit;
9767 else if (info->mach == bfd_mach_i386_i8086)
9768 {
9769 ins.address_mode = mode_16bit;
9770 priv.orig_sizeflag = 0;
9771 }
9772 else
9773 ins.address_mode = mode_64bit;
9774
9775 for (p = info->disassembler_options; p != NULL;)
9776 {
9777 if (startswith (p, "amd64"))
9778 ins.isa64 = amd64;
9779 else if (startswith (p, "intel64"))
9780 ins.isa64 = intel64;
9781 else if (startswith (p, "x86-64"))
9782 {
9783 ins.address_mode = mode_64bit;
9784 priv.orig_sizeflag |= AFLAG | DFLAG;
9785 }
9786 else if (startswith (p, "i386"))
9787 {
9788 ins.address_mode = mode_32bit;
9789 priv.orig_sizeflag |= AFLAG | DFLAG;
9790 }
9791 else if (startswith (p, "i8086"))
9792 {
9793 ins.address_mode = mode_16bit;
9794 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9795 }
9796 else if (startswith (p, "intel"))
9797 {
9798 ins.intel_syntax = 1;
9799 if (startswith (p + 5, "-mnemonic"))
9800 ins.intel_mnemonic = true;
9801 }
9802 else if (startswith (p, "att"))
9803 {
9804 ins.intel_syntax = 0;
9805 if (startswith (p + 3, "-mnemonic"))
9806 ins.intel_mnemonic = false;
9807 }
9808 else if (startswith (p, "addr"))
9809 {
9810 if (ins.address_mode == mode_64bit)
9811 {
9812 if (p[4] == '3' && p[5] == '2')
9813 priv.orig_sizeflag &= ~AFLAG;
9814 else if (p[4] == '6' && p[5] == '4')
9815 priv.orig_sizeflag |= AFLAG;
9816 }
9817 else
9818 {
9819 if (p[4] == '1' && p[5] == '6')
9820 priv.orig_sizeflag &= ~AFLAG;
9821 else if (p[4] == '3' && p[5] == '2')
9822 priv.orig_sizeflag |= AFLAG;
9823 }
9824 }
9825 else if (startswith (p, "data"))
9826 {
9827 if (p[4] == '1' && p[5] == '6')
9828 priv.orig_sizeflag &= ~DFLAG;
9829 else if (p[4] == '3' && p[5] == '2')
9830 priv.orig_sizeflag |= DFLAG;
9831 }
9832 else if (startswith (p, "suffix"))
9833 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9834
9835 p = strchr (p, ',');
9836 if (p != NULL)
9837 p++;
9838 }
9839
9840 if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9841 {
9842 i386_dis_printf (&ins, dis_style_text, _("64-bit address is disabled"));
9843 return -1;
9844 }
9845
9846 if (ins.intel_syntax)
9847 {
9848 ins.open_char = '[';
9849 ins.close_char = ']';
9850 ins.separator_char = '+';
9851 ins.scale_char = '*';
9852 }
9853 else
9854 {
9855 ins.open_char = '(';
9856 ins.close_char = ')';
9857 ins.separator_char = ',';
9858 ins.scale_char = ',';
9859 }
9860
9861 /* The output looks better if we put 7 bytes on a line, since that
9862 puts most long word instructions on a single line. */
9863 info->bytes_per_line = 7;
9864
9865 info->private_data = &priv;
9866 priv.max_fetched = priv.the_buffer;
9867 priv.insn_start = pc;
9868
9869 for (i = 0; i < MAX_OPERANDS; ++i)
9870 {
9871 op_out[i][0] = 0;
9872 ins.op_out[i] = op_out[i];
9873 }
9874
9875 sizeflag = priv.orig_sizeflag;
9876
9877 switch (ckprefix (&ins))
9878 {
9879 case ckp_okay:
9880 break;
9881
9882 case ckp_bogus:
9883 /* Too many prefixes or unused REX prefixes. */
9884 for (i = 0;
9885 i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9886 i++)
9887 i386_dis_printf (&ins, dis_style_mnemonic, "%s%s",
9888 (i == 0 ? "" : " "),
9889 prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9890 return i;
9891
9892 case ckp_fetch_error:
9893 return fetch_error (&ins);
9894 }
9895
9896 ins.insn_codep = ins.codep;
9897
9898 if (!fetch_code (info, ins.codep + 1))
9899 return fetch_error (&ins);
9900
9901 ins.two_source_ops = (*ins.codep == 0x62) || (*ins.codep == 0xc8);
9902
9903 if (((ins.prefixes & PREFIX_FWAIT)
9904 && ((*ins.codep < 0xd8) || (*ins.codep > 0xdf))))
9905 {
9906 /* Handle ins.prefixes before fwait. */
9907 for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9908 i++)
9909 i386_dis_printf (&ins, dis_style_mnemonic, "%s ",
9910 prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9911 i386_dis_printf (&ins, dis_style_mnemonic, "fwait");
9912 return i + 1;
9913 }
9914
9915 if (*ins.codep == 0x0f)
9916 {
9917 unsigned char threebyte;
9918
9919 ins.codep++;
9920 if (!fetch_code (info, ins.codep + 1))
9921 return fetch_error (&ins);
9922 threebyte = *ins.codep;
9923 dp = &dis386_twobyte[threebyte];
9924 ins.need_modrm = twobyte_has_modrm[threebyte];
9925 ins.codep++;
9926 }
9927 else
9928 {
9929 dp = &dis386[*ins.codep];
9930 ins.need_modrm = onebyte_has_modrm[*ins.codep];
9931 ins.codep++;
9932 }
9933
9934 /* Save sizeflag for printing the extra ins.prefixes later before updating
9935 it for mnemonic and operand processing. The prefix names depend
9936 only on the address mode. */
9937 orig_sizeflag = sizeflag;
9938 if (ins.prefixes & PREFIX_ADDR)
9939 sizeflag ^= AFLAG;
9940 if ((ins.prefixes & PREFIX_DATA))
9941 sizeflag ^= DFLAG;
9942
9943 ins.end_codep = ins.codep;
9944 if (ins.need_modrm && !fetch_modrm (&ins))
9945 return fetch_error (&ins);
9946
9947 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9948 {
9949 if (!get_sib (&ins, sizeflag)
9950 || !dofloat (&ins, sizeflag))
9951 return fetch_error (&ins);
9952 }
9953 else
9954 {
9955 dp = get_valid_dis386 (dp, &ins);
9956 if (dp == &err_opcode)
9957 return fetch_error (&ins);
9958 if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9959 {
9960 if (!get_sib (&ins, sizeflag))
9961 return fetch_error (&ins);
9962 for (i = 0; i < MAX_OPERANDS; ++i)
9963 {
9964 ins.obufp = ins.op_out[i];
9965 ins.op_ad = MAX_OPERANDS - 1 - i;
9966 if (dp->op[i].rtn
9967 && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9968 return fetch_error (&ins);
9969 /* For EVEX instruction after the last operand masking
9970 should be printed. */
9971 if (i == 0 && ins.vex.evex)
9972 {
9973 /* Don't print {%k0}. */
9974 if (ins.vex.mask_register_specifier)
9975 {
9976 const char *reg_name
9977 = att_names_mask[ins.vex.mask_register_specifier];
9978
9979 oappend (&ins, "{");
9980 oappend_register (&ins, reg_name);
9981 oappend (&ins, "}");
9982 }
9983 if (ins.vex.zeroing)
9984 oappend (&ins, "{z}");
9985
9986 /* S/G insns require a mask and don't allow
9987 zeroing-masking. */
9988 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9989 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9990 && (ins.vex.mask_register_specifier == 0
9991 || ins.vex.zeroing))
9992 oappend (&ins, "/(bad)");
9993 }
9994 }
9995
9996 /* Check whether rounding control was enabled for an insn not
9997 supporting it. */
9998 if (ins.modrm.mod == 3 && ins.vex.b
9999 && !(ins.evex_used & EVEX_b_used))
10000 {
10001 for (i = 0; i < MAX_OPERANDS; ++i)
10002 {
10003 ins.obufp = ins.op_out[i];
10004 if (*ins.obufp)
10005 continue;
10006 oappend (&ins, names_rounding[ins.vex.ll]);
10007 oappend (&ins, "bad}");
10008 break;
10009 }
10010 }
10011 }
10012 }
10013
10014 /* Clear instruction information. */
10015 info->insn_info_valid = 0;
10016 info->branch_delay_insns = 0;
10017 info->data_size = 0;
10018 info->insn_type = dis_noninsn;
10019 info->target = 0;
10020 info->target2 = 0;
10021
10022 /* Reset jump operation indicator. */
10023 ins.op_is_jump = false;
10024 {
10025 int jump_detection = 0;
10026
10027 /* Extract flags. */
10028 for (i = 0; i < MAX_OPERANDS; ++i)
10029 {
10030 if ((dp->op[i].rtn == OP_J)
10031 || (dp->op[i].rtn == OP_indirE))
10032 jump_detection |= 1;
10033 else if ((dp->op[i].rtn == BND_Fixup)
10034 || (!dp->op[i].rtn && !dp->op[i].bytemode))
10035 jump_detection |= 2;
10036 else if ((dp->op[i].bytemode == cond_jump_mode)
10037 || (dp->op[i].bytemode == loop_jcxz_mode))
10038 jump_detection |= 4;
10039 }
10040
10041 /* Determine if this is a jump or branch. */
10042 if ((jump_detection & 0x3) == 0x3)
10043 {
10044 ins.op_is_jump = true;
10045 if (jump_detection & 0x4)
10046 info->insn_type = dis_condbranch;
10047 else
10048 info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
10049 ? dis_jsr : dis_branch;
10050 }
10051 }
10052
10053 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10054 are all 0s in inverted form. */
10055 if (ins.need_vex && ins.vex.register_specifier != 0)
10056 {
10057 i386_dis_printf (&ins, dis_style_text, "(bad)");
10058 return ins.end_codep - priv.the_buffer;
10059 }
10060
10061 /* If EVEX.z is set, there must be an actual mask register in use. */
10062 if (ins.vex.zeroing && ins.vex.mask_register_specifier == 0)
10063 {
10064 i386_dis_printf (&ins, dis_style_text, "(bad)");
10065 return ins.end_codep - priv.the_buffer;
10066 }
10067
10068 switch (dp->prefix_requirement)
10069 {
10070 case PREFIX_DATA:
10071 /* If only the data prefix is marked as mandatory, its absence renders
10072 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
10073 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
10074 {
10075 i386_dis_printf (&ins, dis_style_text, "(bad)");
10076 return ins.end_codep - priv.the_buffer;
10077 }
10078 ins.used_prefixes |= PREFIX_DATA;
10079 /* Fall through. */
10080 case PREFIX_OPCODE:
10081 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10082 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
10083 used by putop and MMX/SSE operand and may be overridden by the
10084 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10085 separately. */
10086 if (((ins.need_vex
10087 ? ins.vex.prefix == REPE_PREFIX_OPCODE
10088 || ins.vex.prefix == REPNE_PREFIX_OPCODE
10089 : (ins.prefixes
10090 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10091 && (ins.used_prefixes
10092 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10093 || (((ins.need_vex
10094 ? ins.vex.prefix == DATA_PREFIX_OPCODE
10095 : ((ins.prefixes
10096 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10097 == PREFIX_DATA))
10098 && (ins.used_prefixes & PREFIX_DATA) == 0))
10099 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
10100 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
10101 {
10102 i386_dis_printf (&ins, dis_style_text, "(bad)");
10103 return ins.end_codep - priv.the_buffer;
10104 }
10105 break;
10106
10107 case PREFIX_IGNORED:
10108 /* Zap data size and rep prefixes from used_prefixes and reinstate their
10109 origins in all_prefixes. */
10110 ins.used_prefixes &= ~PREFIX_OPCODE;
10111 if (ins.last_data_prefix >= 0)
10112 ins.all_prefixes[ins.last_data_prefix] = 0x66;
10113 if (ins.last_repz_prefix >= 0)
10114 ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
10115 if (ins.last_repnz_prefix >= 0)
10116 ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
10117 break;
10118 }
10119
10120 /* Check if the REX prefix is used. */
10121 if ((ins.rex ^ ins.rex_used) == 0
10122 && !ins.need_vex && ins.last_rex_prefix >= 0)
10123 ins.all_prefixes[ins.last_rex_prefix] = 0;
10124
10125 /* Check if the SEG prefix is used. */
10126 if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10127 | PREFIX_FS | PREFIX_GS)) != 0
10128 && (ins.used_prefixes & ins.active_seg_prefix) != 0)
10129 ins.all_prefixes[ins.last_seg_prefix] = 0;
10130
10131 /* Check if the ADDR prefix is used. */
10132 if ((ins.prefixes & PREFIX_ADDR) != 0
10133 && (ins.used_prefixes & PREFIX_ADDR) != 0)
10134 ins.all_prefixes[ins.last_addr_prefix] = 0;
10135
10136 /* Check if the DATA prefix is used. */
10137 if ((ins.prefixes & PREFIX_DATA) != 0
10138 && (ins.used_prefixes & PREFIX_DATA) != 0
10139 && !ins.need_vex)
10140 ins.all_prefixes[ins.last_data_prefix] = 0;
10141
10142 /* Print the extra ins.prefixes. */
10143 prefix_length = 0;
10144 for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
10145 if (ins.all_prefixes[i])
10146 {
10147 const char *name;
10148 name = prefix_name (&ins, ins.all_prefixes[i], orig_sizeflag);
10149 if (name == NULL)
10150 abort ();
10151 prefix_length += strlen (name) + 1;
10152 i386_dis_printf (&ins, dis_style_mnemonic, "%s ", name);
10153 }
10154
10155 /* Check maximum code length. */
10156 if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
10157 {
10158 i386_dis_printf (&ins, dis_style_text, "(bad)");
10159 return MAX_CODE_LENGTH;
10160 }
10161
10162 /* Calculate the number of operands this instruction has. */
10163 op_count = 0;
10164 for (i = 0; i < MAX_OPERANDS; ++i)
10165 if (*ins.op_out[i] != '\0')
10166 ++op_count;
10167
10168 /* Calculate the number of spaces to print after the mnemonic. */
10169 ins.obufp = ins.mnemonicendp;
10170 if (op_count > 0)
10171 {
10172 i = strlen (ins.obuf) + prefix_length;
10173 if (i < 7)
10174 i = 7 - i;
10175 else
10176 i = 1;
10177 }
10178 else
10179 i = 0;
10180
10181 /* Print the instruction mnemonic along with any trailing whitespace. */
10182 i386_dis_printf (&ins, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
10183
10184 /* The enter and bound instructions are printed with operands in the same
10185 order as the intel book; everything else is printed in reverse order. */
10186 intel_swap_2_3 = false;
10187 if (ins.intel_syntax || ins.two_source_ops)
10188 {
10189 for (i = 0; i < MAX_OPERANDS; ++i)
10190 op_txt[i] = ins.op_out[i];
10191
10192 if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10193 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10194 {
10195 op_txt[2] = ins.op_out[3];
10196 op_txt[3] = ins.op_out[2];
10197 intel_swap_2_3 = true;
10198 }
10199
10200 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10201 {
10202 bool riprel;
10203
10204 ins.op_ad = ins.op_index[i];
10205 ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
10206 ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
10207 riprel = ins.op_riprel[i];
10208 ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
10209 ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10210 }
10211 }
10212 else
10213 {
10214 for (i = 0; i < MAX_OPERANDS; ++i)
10215 op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
10216 }
10217
10218 needcomma = 0;
10219 for (i = 0; i < MAX_OPERANDS; ++i)
10220 if (*op_txt[i])
10221 {
10222 /* In Intel syntax embedded rounding / SAE are not separate operands.
10223 Instead they're attached to the prior register operand. Simply
10224 suppress emission of the comma to achieve that effect. */
10225 switch (i & -(ins.intel_syntax && dp))
10226 {
10227 case 2:
10228 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
10229 needcomma = 0;
10230 break;
10231 case 3:
10232 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
10233 needcomma = 0;
10234 break;
10235 }
10236 if (needcomma)
10237 i386_dis_printf (&ins, dis_style_text, ",");
10238 if (ins.op_index[i] != -1 && !ins.op_riprel[i])
10239 {
10240 bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
10241
10242 if (ins.op_is_jump)
10243 {
10244 info->insn_info_valid = 1;
10245 info->branch_delay_insns = 0;
10246 info->data_size = 0;
10247 info->target = target;
10248 info->target2 = 0;
10249 }
10250 (*info->print_address_func) (target, info);
10251 }
10252 else
10253 i386_dis_printf (&ins, dis_style_text, "%s", op_txt[i]);
10254 needcomma = 1;
10255 }
10256
10257 for (i = 0; i < MAX_OPERANDS; i++)
10258 if (ins.op_index[i] != -1 && ins.op_riprel[i])
10259 {
10260 i386_dis_printf (&ins, dis_style_comment_start, " # ");
10261 (*info->print_address_func)
10262 ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
10263 + ins.op_address[ins.op_index[i]]),
10264 info);
10265 break;
10266 }
10267 return ins.codep - priv.the_buffer;
10268 }
10269
10270 /* Here for backwards compatibility. When gdb stops using
10271 print_insn_i386_att and print_insn_i386_intel these functions can
10272 disappear, and print_insn_i386 be merged into print_insn. */
10273 int
10274 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10275 {
10276 return print_insn (pc, info, 0);
10277 }
10278
10279 int
10280 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10281 {
10282 return print_insn (pc, info, 1);
10283 }
10284
10285 int
10286 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10287 {
10288 return print_insn (pc, info, -1);
10289 }
10290
10291 static const char *float_mem[] = {
10292 /* d8 */
10293 "fadd{s|}",
10294 "fmul{s|}",
10295 "fcom{s|}",
10296 "fcomp{s|}",
10297 "fsub{s|}",
10298 "fsubr{s|}",
10299 "fdiv{s|}",
10300 "fdivr{s|}",
10301 /* d9 */
10302 "fld{s|}",
10303 "(bad)",
10304 "fst{s|}",
10305 "fstp{s|}",
10306 "fldenv{C|C}",
10307 "fldcw",
10308 "fNstenv{C|C}",
10309 "fNstcw",
10310 /* da */
10311 "fiadd{l|}",
10312 "fimul{l|}",
10313 "ficom{l|}",
10314 "ficomp{l|}",
10315 "fisub{l|}",
10316 "fisubr{l|}",
10317 "fidiv{l|}",
10318 "fidivr{l|}",
10319 /* db */
10320 "fild{l|}",
10321 "fisttp{l|}",
10322 "fist{l|}",
10323 "fistp{l|}",
10324 "(bad)",
10325 "fld{t|}",
10326 "(bad)",
10327 "fstp{t|}",
10328 /* dc */
10329 "fadd{l|}",
10330 "fmul{l|}",
10331 "fcom{l|}",
10332 "fcomp{l|}",
10333 "fsub{l|}",
10334 "fsubr{l|}",
10335 "fdiv{l|}",
10336 "fdivr{l|}",
10337 /* dd */
10338 "fld{l|}",
10339 "fisttp{ll|}",
10340 "fst{l||}",
10341 "fstp{l|}",
10342 "frstor{C|C}",
10343 "(bad)",
10344 "fNsave{C|C}",
10345 "fNstsw",
10346 /* de */
10347 "fiadd{s|}",
10348 "fimul{s|}",
10349 "ficom{s|}",
10350 "ficomp{s|}",
10351 "fisub{s|}",
10352 "fisubr{s|}",
10353 "fidiv{s|}",
10354 "fidivr{s|}",
10355 /* df */
10356 "fild{s|}",
10357 "fisttp{s|}",
10358 "fist{s|}",
10359 "fistp{s|}",
10360 "fbld",
10361 "fild{ll|}",
10362 "fbstp",
10363 "fistp{ll|}",
10364 };
10365
10366 static const unsigned char float_mem_mode[] = {
10367 /* d8 */
10368 d_mode,
10369 d_mode,
10370 d_mode,
10371 d_mode,
10372 d_mode,
10373 d_mode,
10374 d_mode,
10375 d_mode,
10376 /* d9 */
10377 d_mode,
10378 0,
10379 d_mode,
10380 d_mode,
10381 0,
10382 w_mode,
10383 0,
10384 w_mode,
10385 /* da */
10386 d_mode,
10387 d_mode,
10388 d_mode,
10389 d_mode,
10390 d_mode,
10391 d_mode,
10392 d_mode,
10393 d_mode,
10394 /* db */
10395 d_mode,
10396 d_mode,
10397 d_mode,
10398 d_mode,
10399 0,
10400 t_mode,
10401 0,
10402 t_mode,
10403 /* dc */
10404 q_mode,
10405 q_mode,
10406 q_mode,
10407 q_mode,
10408 q_mode,
10409 q_mode,
10410 q_mode,
10411 q_mode,
10412 /* dd */
10413 q_mode,
10414 q_mode,
10415 q_mode,
10416 q_mode,
10417 0,
10418 0,
10419 0,
10420 w_mode,
10421 /* de */
10422 w_mode,
10423 w_mode,
10424 w_mode,
10425 w_mode,
10426 w_mode,
10427 w_mode,
10428 w_mode,
10429 w_mode,
10430 /* df */
10431 w_mode,
10432 w_mode,
10433 w_mode,
10434 w_mode,
10435 t_mode,
10436 q_mode,
10437 t_mode,
10438 q_mode
10439 };
10440
10441 #define ST { OP_ST, 0 }
10442 #define STi { OP_STi, 0 }
10443
10444 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10445 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10446 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10447 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10448 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10449 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10450 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10451 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10452 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10453
10454 static const struct dis386 float_reg[][8] = {
10455 /* d8 */
10456 {
10457 { "fadd", { ST, STi }, 0 },
10458 { "fmul", { ST, STi }, 0 },
10459 { "fcom", { STi }, 0 },
10460 { "fcomp", { STi }, 0 },
10461 { "fsub", { ST, STi }, 0 },
10462 { "fsubr", { ST, STi }, 0 },
10463 { "fdiv", { ST, STi }, 0 },
10464 { "fdivr", { ST, STi }, 0 },
10465 },
10466 /* d9 */
10467 {
10468 { "fld", { STi }, 0 },
10469 { "fxch", { STi }, 0 },
10470 { FGRPd9_2 },
10471 { Bad_Opcode },
10472 { FGRPd9_4 },
10473 { FGRPd9_5 },
10474 { FGRPd9_6 },
10475 { FGRPd9_7 },
10476 },
10477 /* da */
10478 {
10479 { "fcmovb", { ST, STi }, 0 },
10480 { "fcmove", { ST, STi }, 0 },
10481 { "fcmovbe",{ ST, STi }, 0 },
10482 { "fcmovu", { ST, STi }, 0 },
10483 { Bad_Opcode },
10484 { FGRPda_5 },
10485 { Bad_Opcode },
10486 { Bad_Opcode },
10487 },
10488 /* db */
10489 {
10490 { "fcmovnb",{ ST, STi }, 0 },
10491 { "fcmovne",{ ST, STi }, 0 },
10492 { "fcmovnbe",{ ST, STi }, 0 },
10493 { "fcmovnu",{ ST, STi }, 0 },
10494 { FGRPdb_4 },
10495 { "fucomi", { ST, STi }, 0 },
10496 { "fcomi", { ST, STi }, 0 },
10497 { Bad_Opcode },
10498 },
10499 /* dc */
10500 {
10501 { "fadd", { STi, ST }, 0 },
10502 { "fmul", { STi, ST }, 0 },
10503 { Bad_Opcode },
10504 { Bad_Opcode },
10505 { "fsub{!M|r}", { STi, ST }, 0 },
10506 { "fsub{M|}", { STi, ST }, 0 },
10507 { "fdiv{!M|r}", { STi, ST }, 0 },
10508 { "fdiv{M|}", { STi, ST }, 0 },
10509 },
10510 /* dd */
10511 {
10512 { "ffree", { STi }, 0 },
10513 { Bad_Opcode },
10514 { "fst", { STi }, 0 },
10515 { "fstp", { STi }, 0 },
10516 { "fucom", { STi }, 0 },
10517 { "fucomp", { STi }, 0 },
10518 { Bad_Opcode },
10519 { Bad_Opcode },
10520 },
10521 /* de */
10522 {
10523 { "faddp", { STi, ST }, 0 },
10524 { "fmulp", { STi, ST }, 0 },
10525 { Bad_Opcode },
10526 { FGRPde_3 },
10527 { "fsub{!M|r}p", { STi, ST }, 0 },
10528 { "fsub{M|}p", { STi, ST }, 0 },
10529 { "fdiv{!M|r}p", { STi, ST }, 0 },
10530 { "fdiv{M|}p", { STi, ST }, 0 },
10531 },
10532 /* df */
10533 {
10534 { "ffreep", { STi }, 0 },
10535 { Bad_Opcode },
10536 { Bad_Opcode },
10537 { Bad_Opcode },
10538 { FGRPdf_4 },
10539 { "fucomip", { ST, STi }, 0 },
10540 { "fcomip", { ST, STi }, 0 },
10541 { Bad_Opcode },
10542 },
10543 };
10544
10545 static const char *const fgrps[][8] = {
10546 /* Bad opcode 0 */
10547 {
10548 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10549 },
10550
10551 /* d9_2 1 */
10552 {
10553 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10554 },
10555
10556 /* d9_4 2 */
10557 {
10558 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10559 },
10560
10561 /* d9_5 3 */
10562 {
10563 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10564 },
10565
10566 /* d9_6 4 */
10567 {
10568 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10569 },
10570
10571 /* d9_7 5 */
10572 {
10573 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10574 },
10575
10576 /* da_5 6 */
10577 {
10578 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10579 },
10580
10581 /* db_4 7 */
10582 {
10583 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10584 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10585 },
10586
10587 /* de_3 8 */
10588 {
10589 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10590 },
10591
10592 /* df_4 9 */
10593 {
10594 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10595 },
10596 };
10597
10598 static void
10599 swap_operand (instr_info *ins)
10600 {
10601 ins->mnemonicendp[0] = '.';
10602 ins->mnemonicendp[1] = 's';
10603 ins->mnemonicendp[2] = '\0';
10604 ins->mnemonicendp += 2;
10605 }
10606
10607 static bool
10608 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10609 int sizeflag ATTRIBUTE_UNUSED)
10610 {
10611 /* Skip mod/rm byte. */
10612 MODRM_CHECK;
10613 ins->codep++;
10614 return true;
10615 }
10616
10617 static bool
10618 dofloat (instr_info *ins, int sizeflag)
10619 {
10620 const struct dis386 *dp;
10621 unsigned char floatop;
10622
10623 floatop = ins->codep[-1];
10624
10625 if (ins->modrm.mod != 3)
10626 {
10627 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10628
10629 putop (ins, float_mem[fp_indx], sizeflag);
10630 ins->obufp = ins->op_out[0];
10631 ins->op_ad = 2;
10632 return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10633 }
10634 /* Skip mod/rm byte. */
10635 MODRM_CHECK;
10636 ins->codep++;
10637
10638 dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10639 if (dp->name == NULL)
10640 {
10641 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10642
10643 /* Instruction fnstsw is only one with strange arg. */
10644 if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10645 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10646 }
10647 else
10648 {
10649 putop (ins, dp->name, sizeflag);
10650
10651 ins->obufp = ins->op_out[0];
10652 ins->op_ad = 2;
10653 if (dp->op[0].rtn
10654 && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10655 return false;
10656
10657 ins->obufp = ins->op_out[1];
10658 ins->op_ad = 1;
10659 if (dp->op[1].rtn
10660 && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10661 return false;
10662 }
10663 return true;
10664 }
10665
10666 static bool
10667 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10668 int sizeflag ATTRIBUTE_UNUSED)
10669 {
10670 oappend_register (ins, "%st");
10671 return true;
10672 }
10673
10674 static bool
10675 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10676 int sizeflag ATTRIBUTE_UNUSED)
10677 {
10678 char scratch[8];
10679 int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10680
10681 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10682 abort ();
10683 oappend_register (ins, scratch);
10684 return true;
10685 }
10686
10687 /* Capital letters in template are macros. */
10688 static int
10689 putop (instr_info *ins, const char *in_template, int sizeflag)
10690 {
10691 const char *p;
10692 int alt = 0;
10693 int cond = 1;
10694 unsigned int l = 0, len = 0;
10695 char last[4];
10696
10697 for (p = in_template; *p; p++)
10698 {
10699 if (len > l)
10700 {
10701 if (l >= sizeof (last) || !ISUPPER (*p))
10702 abort ();
10703 last[l++] = *p;
10704 continue;
10705 }
10706 switch (*p)
10707 {
10708 default:
10709 *ins->obufp++ = *p;
10710 break;
10711 case '%':
10712 len++;
10713 break;
10714 case '!':
10715 cond = 0;
10716 break;
10717 case '{':
10718 if (ins->intel_syntax)
10719 {
10720 while (*++p != '|')
10721 if (*p == '}' || *p == '\0')
10722 abort ();
10723 alt = 1;
10724 }
10725 break;
10726 case '|':
10727 while (*++p != '}')
10728 {
10729 if (*p == '\0')
10730 abort ();
10731 }
10732 break;
10733 case '}':
10734 alt = 0;
10735 break;
10736 case 'A':
10737 if (ins->intel_syntax)
10738 break;
10739 if ((ins->need_modrm && ins->modrm.mod != 3)
10740 || (sizeflag & SUFFIX_ALWAYS))
10741 *ins->obufp++ = 'b';
10742 break;
10743 case 'B':
10744 if (l == 0)
10745 {
10746 case_B:
10747 if (ins->intel_syntax)
10748 break;
10749 if (sizeflag & SUFFIX_ALWAYS)
10750 *ins->obufp++ = 'b';
10751 }
10752 else if (l == 1 && last[0] == 'L')
10753 {
10754 if (ins->address_mode == mode_64bit
10755 && !(ins->prefixes & PREFIX_ADDR))
10756 {
10757 *ins->obufp++ = 'a';
10758 *ins->obufp++ = 'b';
10759 *ins->obufp++ = 's';
10760 }
10761
10762 goto case_B;
10763 }
10764 else
10765 abort ();
10766 break;
10767 case 'C':
10768 if (ins->intel_syntax && !alt)
10769 break;
10770 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10771 {
10772 if (sizeflag & DFLAG)
10773 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10774 else
10775 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10776 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10777 }
10778 break;
10779 case 'D':
10780 if (l == 1)
10781 {
10782 switch (last[0])
10783 {
10784 case 'X':
10785 if (!ins->vex.evex || ins->vex.w)
10786 *ins->obufp++ = 'd';
10787 else
10788 oappend (ins, "{bad}");
10789 break;
10790 default:
10791 abort ();
10792 }
10793 break;
10794 }
10795 if (l)
10796 abort ();
10797 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10798 break;
10799 USED_REX (REX_W);
10800 if (ins->modrm.mod == 3)
10801 {
10802 if (ins->rex & REX_W)
10803 *ins->obufp++ = 'q';
10804 else
10805 {
10806 if (sizeflag & DFLAG)
10807 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10808 else
10809 *ins->obufp++ = 'w';
10810 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10811 }
10812 }
10813 else
10814 *ins->obufp++ = 'w';
10815 break;
10816 case 'E':
10817 if (l == 1)
10818 {
10819 switch (last[0])
10820 {
10821 case 'X':
10822 if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10823 || !ins->vex.r
10824 || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10825 || !ins->vex.v || ins->vex.mask_register_specifier)
10826 break;
10827 /* AVX512 extends a number of V*D insns to also have V*Q variants,
10828 merely distinguished by EVEX.W. Look for a use of the
10829 respective macro. */
10830 if (ins->vex.w)
10831 {
10832 const char *pct = strchr (p + 1, '%');
10833
10834 if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10835 break;
10836 }
10837 *ins->obufp++ = '{';
10838 *ins->obufp++ = 'e';
10839 *ins->obufp++ = 'v';
10840 *ins->obufp++ = 'e';
10841 *ins->obufp++ = 'x';
10842 *ins->obufp++ = '}';
10843 *ins->obufp++ = ' ';
10844 break;
10845 default:
10846 abort ();
10847 }
10848 break;
10849 }
10850 /* For jcxz/jecxz */
10851 if (ins->address_mode == mode_64bit)
10852 {
10853 if (sizeflag & AFLAG)
10854 *ins->obufp++ = 'r';
10855 else
10856 *ins->obufp++ = 'e';
10857 }
10858 else
10859 if (sizeflag & AFLAG)
10860 *ins->obufp++ = 'e';
10861 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10862 break;
10863 case 'F':
10864 if (ins->intel_syntax)
10865 break;
10866 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10867 {
10868 if (sizeflag & AFLAG)
10869 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10870 else
10871 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10872 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10873 }
10874 break;
10875 case 'G':
10876 if (ins->intel_syntax || (ins->obufp[-1] != 's'
10877 && !(sizeflag & SUFFIX_ALWAYS)))
10878 break;
10879 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10880 *ins->obufp++ = 'l';
10881 else
10882 *ins->obufp++ = 'w';
10883 if (!(ins->rex & REX_W))
10884 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10885 break;
10886 case 'H':
10887 if (l == 0)
10888 {
10889 if (ins->intel_syntax)
10890 break;
10891 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10892 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10893 {
10894 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10895 *ins->obufp++ = ',';
10896 *ins->obufp++ = 'p';
10897
10898 /* Set active_seg_prefix even if not set in 64-bit mode
10899 because here it is a valid branch hint. */
10900 if (ins->prefixes & PREFIX_DS)
10901 {
10902 ins->active_seg_prefix = PREFIX_DS;
10903 *ins->obufp++ = 't';
10904 }
10905 else
10906 {
10907 ins->active_seg_prefix = PREFIX_CS;
10908 *ins->obufp++ = 'n';
10909 }
10910 }
10911 }
10912 else if (l == 1 && last[0] == 'X')
10913 {
10914 if (!ins->vex.w)
10915 *ins->obufp++ = 'h';
10916 else
10917 oappend (ins, "{bad}");
10918 }
10919 else
10920 abort ();
10921 break;
10922 case 'K':
10923 USED_REX (REX_W);
10924 if (ins->rex & REX_W)
10925 *ins->obufp++ = 'q';
10926 else
10927 *ins->obufp++ = 'd';
10928 break;
10929 case 'L':
10930 abort ();
10931 case 'M':
10932 if (ins->intel_mnemonic != cond)
10933 *ins->obufp++ = 'r';
10934 break;
10935 case 'N':
10936 if ((ins->prefixes & PREFIX_FWAIT) == 0)
10937 *ins->obufp++ = 'n';
10938 else
10939 ins->used_prefixes |= PREFIX_FWAIT;
10940 break;
10941 case 'O':
10942 USED_REX (REX_W);
10943 if (ins->rex & REX_W)
10944 *ins->obufp++ = 'o';
10945 else if (ins->intel_syntax && (sizeflag & DFLAG))
10946 *ins->obufp++ = 'q';
10947 else
10948 *ins->obufp++ = 'd';
10949 if (!(ins->rex & REX_W))
10950 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10951 break;
10952 case '@':
10953 if (ins->address_mode == mode_64bit
10954 && (ins->isa64 == intel64 || (ins->rex & REX_W)
10955 || !(ins->prefixes & PREFIX_DATA)))
10956 {
10957 if (sizeflag & SUFFIX_ALWAYS)
10958 *ins->obufp++ = 'q';
10959 break;
10960 }
10961 /* Fall through. */
10962 case 'P':
10963 if (l == 0)
10964 {
10965 if ((ins->modrm.mod == 3 || !cond)
10966 && !(sizeflag & SUFFIX_ALWAYS))
10967 break;
10968 /* Fall through. */
10969 case 'T':
10970 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10971 || ((sizeflag & SUFFIX_ALWAYS)
10972 && ins->address_mode != mode_64bit))
10973 {
10974 *ins->obufp++ = (sizeflag & DFLAG)
10975 ? ins->intel_syntax ? 'd' : 'l' : 'w';
10976 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10977 }
10978 else if (sizeflag & SUFFIX_ALWAYS)
10979 *ins->obufp++ = 'q';
10980 }
10981 else if (l == 1 && last[0] == 'L')
10982 {
10983 if ((ins->prefixes & PREFIX_DATA)
10984 || (ins->rex & REX_W)
10985 || (sizeflag & SUFFIX_ALWAYS))
10986 {
10987 USED_REX (REX_W);
10988 if (ins->rex & REX_W)
10989 *ins->obufp++ = 'q';
10990 else
10991 {
10992 if (sizeflag & DFLAG)
10993 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10994 else
10995 *ins->obufp++ = 'w';
10996 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10997 }
10998 }
10999 }
11000 else
11001 abort ();
11002 break;
11003 case 'Q':
11004 if (l == 0)
11005 {
11006 if (ins->intel_syntax && !alt)
11007 break;
11008 USED_REX (REX_W);
11009 if ((ins->need_modrm && ins->modrm.mod != 3)
11010 || (sizeflag & SUFFIX_ALWAYS))
11011 {
11012 if (ins->rex & REX_W)
11013 *ins->obufp++ = 'q';
11014 else
11015 {
11016 if (sizeflag & DFLAG)
11017 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
11018 else
11019 *ins->obufp++ = 'w';
11020 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11021 }
11022 }
11023 }
11024 else if (l == 1 && last[0] == 'D')
11025 *ins->obufp++ = ins->vex.w ? 'q' : 'd';
11026 else if (l == 1 && last[0] == 'L')
11027 {
11028 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
11029 : ins->address_mode != mode_64bit)
11030 break;
11031 if ((ins->rex & REX_W))
11032 {
11033 USED_REX (REX_W);
11034 *ins->obufp++ = 'q';
11035 }
11036 else if ((ins->address_mode == mode_64bit && cond)
11037 || (sizeflag & SUFFIX_ALWAYS))
11038 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
11039 }
11040 else
11041 abort ();
11042 break;
11043 case 'R':
11044 USED_REX (REX_W);
11045 if (ins->rex & REX_W)
11046 *ins->obufp++ = 'q';
11047 else if (sizeflag & DFLAG)
11048 {
11049 if (ins->intel_syntax)
11050 *ins->obufp++ = 'd';
11051 else
11052 *ins->obufp++ = 'l';
11053 }
11054 else
11055 *ins->obufp++ = 'w';
11056 if (ins->intel_syntax && !p[1]
11057 && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
11058 *ins->obufp++ = 'e';
11059 if (!(ins->rex & REX_W))
11060 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11061 break;
11062 case 'S':
11063 if (l == 0)
11064 {
11065 case_S:
11066 if (ins->intel_syntax)
11067 break;
11068 if (sizeflag & SUFFIX_ALWAYS)
11069 {
11070 if (ins->rex & REX_W)
11071 *ins->obufp++ = 'q';
11072 else
11073 {
11074 if (sizeflag & DFLAG)
11075 *ins->obufp++ = 'l';
11076 else
11077 *ins->obufp++ = 'w';
11078 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11079 }
11080 }
11081 break;
11082 }
11083 if (l != 1)
11084 abort ();
11085 switch (last[0])
11086 {
11087 case 'L':
11088 if (ins->address_mode == mode_64bit
11089 && !(ins->prefixes & PREFIX_ADDR))
11090 {
11091 *ins->obufp++ = 'a';
11092 *ins->obufp++ = 'b';
11093 *ins->obufp++ = 's';
11094 }
11095
11096 goto case_S;
11097 case 'X':
11098 if (!ins->vex.evex || !ins->vex.w)
11099 *ins->obufp++ = 's';
11100 else
11101 oappend (ins, "{bad}");
11102 break;
11103 default:
11104 abort ();
11105 }
11106 break;
11107 case 'V':
11108 if (l == 0)
11109 abort ();
11110 else if (l == 1)
11111 {
11112 switch (last[0])
11113 {
11114 case 'X':
11115 if (ins->vex.evex)
11116 break;
11117 *ins->obufp++ = '{';
11118 *ins->obufp++ = 'v';
11119 *ins->obufp++ = 'e';
11120 *ins->obufp++ = 'x';
11121 *ins->obufp++ = '}';
11122 *ins->obufp++ = ' ';
11123 break;
11124 case 'L':
11125 if (!(ins->rex & REX_W))
11126 break;
11127 *ins->obufp++ = 'a';
11128 *ins->obufp++ = 'b';
11129 *ins->obufp++ = 's';
11130 break;
11131 default:
11132 abort ();
11133 }
11134 }
11135 else
11136 abort ();
11137 goto case_S;
11138 case 'W':
11139 if (l == 0)
11140 {
11141 /* operand size flag for cwtl, cbtw */
11142 USED_REX (REX_W);
11143 if (ins->rex & REX_W)
11144 {
11145 if (ins->intel_syntax)
11146 *ins->obufp++ = 'd';
11147 else
11148 *ins->obufp++ = 'l';
11149 }
11150 else if (sizeflag & DFLAG)
11151 *ins->obufp++ = 'w';
11152 else
11153 *ins->obufp++ = 'b';
11154 if (!(ins->rex & REX_W))
11155 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11156 }
11157 else if (l == 1)
11158 {
11159 if (!ins->need_vex)
11160 abort ();
11161 if (last[0] == 'X')
11162 *ins->obufp++ = ins->vex.w ? 'd': 's';
11163 else if (last[0] == 'B')
11164 *ins->obufp++ = ins->vex.w ? 'w': 'b';
11165 else
11166 abort ();
11167 }
11168 else
11169 abort ();
11170 break;
11171 case 'X':
11172 if (l != 0)
11173 abort ();
11174 if (ins->need_vex
11175 ? ins->vex.prefix == DATA_PREFIX_OPCODE
11176 : ins->prefixes & PREFIX_DATA)
11177 {
11178 *ins->obufp++ = 'd';
11179 ins->used_prefixes |= PREFIX_DATA;
11180 }
11181 else
11182 *ins->obufp++ = 's';
11183 break;
11184 case 'Y':
11185 if (l == 1 && last[0] == 'X')
11186 {
11187 if (!ins->need_vex)
11188 abort ();
11189 if (ins->intel_syntax
11190 || ((ins->modrm.mod == 3 || ins->vex.b)
11191 && !(sizeflag & SUFFIX_ALWAYS)))
11192 break;
11193 switch (ins->vex.length)
11194 {
11195 case 128:
11196 *ins->obufp++ = 'x';
11197 break;
11198 case 256:
11199 *ins->obufp++ = 'y';
11200 break;
11201 case 512:
11202 if (!ins->vex.evex)
11203 default:
11204 abort ();
11205 }
11206 }
11207 else
11208 abort ();
11209 break;
11210 case 'Z':
11211 if (l == 0)
11212 {
11213 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
11214 ins->modrm.mod = 3;
11215 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11216 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11217 }
11218 else if (l == 1 && last[0] == 'X')
11219 {
11220 if (!ins->vex.evex)
11221 abort ();
11222 if (ins->intel_syntax
11223 || ((ins->modrm.mod == 3 || ins->vex.b)
11224 && !(sizeflag & SUFFIX_ALWAYS)))
11225 break;
11226 switch (ins->vex.length)
11227 {
11228 case 128:
11229 *ins->obufp++ = 'x';
11230 break;
11231 case 256:
11232 *ins->obufp++ = 'y';
11233 break;
11234 case 512:
11235 *ins->obufp++ = 'z';
11236 break;
11237 default:
11238 abort ();
11239 }
11240 }
11241 else
11242 abort ();
11243 break;
11244 case '^':
11245 if (ins->intel_syntax)
11246 break;
11247 if (ins->isa64 == intel64 && (ins->rex & REX_W))
11248 {
11249 USED_REX (REX_W);
11250 *ins->obufp++ = 'q';
11251 break;
11252 }
11253 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11254 {
11255 if (sizeflag & DFLAG)
11256 *ins->obufp++ = 'l';
11257 else
11258 *ins->obufp++ = 'w';
11259 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11260 }
11261 break;
11262 }
11263
11264 if (len == l)
11265 len = l = 0;
11266 }
11267 *ins->obufp = 0;
11268 ins->mnemonicendp = ins->obufp;
11269 return 0;
11270 }
11271
11272 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that
11273 the buffer pointed to by INS->obufp has space. A style marker is made
11274 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11275 digit, followed by another STYLE_MARKER_CHAR. This function assumes
11276 that the number of styles is not greater than 16. */
11277
11278 static void
11279 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11280 {
11281 unsigned num = (unsigned) style;
11282
11283 /* We currently assume that STYLE can be encoded as a single hex
11284 character. If more styles are added then this might start to fail,
11285 and we'll need to expand this code. */
11286 if (num > 0xf)
11287 abort ();
11288
11289 *ins->obufp++ = STYLE_MARKER_CHAR;
11290 *ins->obufp++ = (num < 10 ? ('0' + num)
11291 : ((num < 16) ? ('a' + (num - 10)) : '0'));
11292 *ins->obufp++ = STYLE_MARKER_CHAR;
11293
11294 /* This final null character is not strictly necessary, after inserting a
11295 style marker we should always be inserting some additional content.
11296 However, having the buffer null terminated doesn't cost much, and make
11297 it easier to debug what's going on. Also, if we do ever forget to add
11298 any additional content after this style marker, then the buffer will
11299 still be well formed. */
11300 *ins->obufp = '\0';
11301 }
11302
11303 static void
11304 oappend_with_style (instr_info *ins, const char *s,
11305 enum disassembler_style style)
11306 {
11307 oappend_insert_style (ins, style);
11308 ins->obufp = stpcpy (ins->obufp, s);
11309 }
11310
11311 /* Like oappend_with_style but always with text style. */
11312
11313 static void
11314 oappend (instr_info *ins, const char *s)
11315 {
11316 oappend_with_style (ins, s, dis_style_text);
11317 }
11318
11319 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11320 the style for the character as STYLE. */
11321
11322 static void
11323 oappend_char_with_style (instr_info *ins, const char c,
11324 enum disassembler_style style)
11325 {
11326 oappend_insert_style (ins, style);
11327 *ins->obufp++ = c;
11328 *ins->obufp = '\0';
11329 }
11330
11331 /* Like oappend_char_with_style, but always uses dis_style_text. */
11332
11333 static void
11334 oappend_char (instr_info *ins, const char c)
11335 {
11336 oappend_char_with_style (ins, c, dis_style_text);
11337 }
11338
11339 static void
11340 append_seg (instr_info *ins)
11341 {
11342 /* Only print the active segment register. */
11343 if (!ins->active_seg_prefix)
11344 return;
11345
11346 ins->used_prefixes |= ins->active_seg_prefix;
11347 switch (ins->active_seg_prefix)
11348 {
11349 case PREFIX_CS:
11350 oappend_register (ins, att_names_seg[1]);
11351 break;
11352 case PREFIX_DS:
11353 oappend_register (ins, att_names_seg[3]);
11354 break;
11355 case PREFIX_SS:
11356 oappend_register (ins, att_names_seg[2]);
11357 break;
11358 case PREFIX_ES:
11359 oappend_register (ins, att_names_seg[0]);
11360 break;
11361 case PREFIX_FS:
11362 oappend_register (ins, att_names_seg[4]);
11363 break;
11364 case PREFIX_GS:
11365 oappend_register (ins, att_names_seg[5]);
11366 break;
11367 default:
11368 break;
11369 }
11370 oappend_char (ins, ':');
11371 }
11372
11373 static bool
11374 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
11375 {
11376 if (!ins->intel_syntax)
11377 oappend (ins, "*");
11378 return OP_E (ins, bytemode, sizeflag);
11379 }
11380
11381 static void
11382 print_operand_value (instr_info *ins, bfd_vma disp,
11383 enum disassembler_style style)
11384 {
11385 char tmp[30];
11386
11387 if (ins->address_mode == mode_64bit)
11388 sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11389 else
11390 sprintf (tmp, "0x%x", (unsigned int) disp);
11391 oappend_with_style (ins, tmp, style);
11392 }
11393
11394 /* Like oappend, but called for immediate operands. */
11395
11396 static void
11397 oappend_immediate (instr_info *ins, bfd_vma imm)
11398 {
11399 if (!ins->intel_syntax)
11400 oappend_char_with_style (ins, '$', dis_style_immediate);
11401 print_operand_value (ins, imm, dis_style_immediate);
11402 }
11403
11404 /* Put DISP in BUF as signed hex number. */
11405
11406 static void
11407 print_displacement (instr_info *ins, bfd_signed_vma val)
11408 {
11409 char tmp[30];
11410
11411 if (val < 0)
11412 {
11413 oappend_char_with_style (ins, '-', dis_style_address_offset);
11414 val = (bfd_vma) 0 - val;
11415
11416 /* Check for possible overflow. */
11417 if (val < 0)
11418 {
11419 switch (ins->address_mode)
11420 {
11421 case mode_64bit:
11422 oappend_with_style (ins, "0x8000000000000000",
11423 dis_style_address_offset);
11424 break;
11425 case mode_32bit:
11426 oappend_with_style (ins, "0x80000000",
11427 dis_style_address_offset);
11428 break;
11429 case mode_16bit:
11430 oappend_with_style (ins, "0x8000",
11431 dis_style_address_offset);
11432 break;
11433 }
11434 return;
11435 }
11436 }
11437
11438 sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11439 oappend_with_style (ins, tmp, dis_style_address_offset);
11440 }
11441
11442 static void
11443 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11444 {
11445 if (ins->vex.b)
11446 {
11447 if (!ins->vex.no_broadcast)
11448 switch (bytemode)
11449 {
11450 case x_mode:
11451 case evex_half_bcst_xmmq_mode:
11452 if (ins->vex.w)
11453 oappend (ins, "QWORD BCST ");
11454 else
11455 oappend (ins, "DWORD BCST ");
11456 break;
11457 case xh_mode:
11458 case evex_half_bcst_xmmqh_mode:
11459 case evex_half_bcst_xmmqdh_mode:
11460 oappend (ins, "WORD BCST ");
11461 break;
11462 default:
11463 ins->vex.no_broadcast = true;
11464 break;
11465 }
11466 return;
11467 }
11468 switch (bytemode)
11469 {
11470 case b_mode:
11471 case b_swap_mode:
11472 case db_mode:
11473 oappend (ins, "BYTE PTR ");
11474 break;
11475 case w_mode:
11476 case w_swap_mode:
11477 case dw_mode:
11478 oappend (ins, "WORD PTR ");
11479 break;
11480 case indir_v_mode:
11481 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11482 {
11483 oappend (ins, "QWORD PTR ");
11484 break;
11485 }
11486 /* Fall through. */
11487 case stack_v_mode:
11488 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11489 || (ins->rex & REX_W)))
11490 {
11491 oappend (ins, "QWORD PTR ");
11492 break;
11493 }
11494 /* Fall through. */
11495 case v_mode:
11496 case v_swap_mode:
11497 case dq_mode:
11498 USED_REX (REX_W);
11499 if (ins->rex & REX_W)
11500 oappend (ins, "QWORD PTR ");
11501 else if (bytemode == dq_mode)
11502 oappend (ins, "DWORD PTR ");
11503 else
11504 {
11505 if (sizeflag & DFLAG)
11506 oappend (ins, "DWORD PTR ");
11507 else
11508 oappend (ins, "WORD PTR ");
11509 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11510 }
11511 break;
11512 case z_mode:
11513 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11514 *ins->obufp++ = 'D';
11515 oappend (ins, "WORD PTR ");
11516 if (!(ins->rex & REX_W))
11517 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11518 break;
11519 case a_mode:
11520 if (sizeflag & DFLAG)
11521 oappend (ins, "QWORD PTR ");
11522 else
11523 oappend (ins, "DWORD PTR ");
11524 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11525 break;
11526 case movsxd_mode:
11527 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11528 oappend (ins, "WORD PTR ");
11529 else
11530 oappend (ins, "DWORD PTR ");
11531 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11532 break;
11533 case d_mode:
11534 case d_swap_mode:
11535 oappend (ins, "DWORD PTR ");
11536 break;
11537 case q_mode:
11538 case q_swap_mode:
11539 oappend (ins, "QWORD PTR ");
11540 break;
11541 case m_mode:
11542 if (ins->address_mode == mode_64bit)
11543 oappend (ins, "QWORD PTR ");
11544 else
11545 oappend (ins, "DWORD PTR ");
11546 break;
11547 case f_mode:
11548 if (sizeflag & DFLAG)
11549 oappend (ins, "FWORD PTR ");
11550 else
11551 oappend (ins, "DWORD PTR ");
11552 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11553 break;
11554 case t_mode:
11555 oappend (ins, "TBYTE PTR ");
11556 break;
11557 case x_mode:
11558 case xh_mode:
11559 case x_swap_mode:
11560 case evex_x_gscat_mode:
11561 case evex_x_nobcst_mode:
11562 case bw_unit_mode:
11563 if (ins->need_vex)
11564 {
11565 switch (ins->vex.length)
11566 {
11567 case 128:
11568 oappend (ins, "XMMWORD PTR ");
11569 break;
11570 case 256:
11571 oappend (ins, "YMMWORD PTR ");
11572 break;
11573 case 512:
11574 oappend (ins, "ZMMWORD PTR ");
11575 break;
11576 default:
11577 abort ();
11578 }
11579 }
11580 else
11581 oappend (ins, "XMMWORD PTR ");
11582 break;
11583 case xmm_mode:
11584 oappend (ins, "XMMWORD PTR ");
11585 break;
11586 case ymm_mode:
11587 oappend (ins, "YMMWORD PTR ");
11588 break;
11589 case xmmq_mode:
11590 case evex_half_bcst_xmmqh_mode:
11591 case evex_half_bcst_xmmq_mode:
11592 if (!ins->need_vex)
11593 abort ();
11594
11595 switch (ins->vex.length)
11596 {
11597 case 128:
11598 oappend (ins, "QWORD PTR ");
11599 break;
11600 case 256:
11601 oappend (ins, "XMMWORD PTR ");
11602 break;
11603 case 512:
11604 oappend (ins, "YMMWORD PTR ");
11605 break;
11606 default:
11607 abort ();
11608 }
11609 break;
11610 case xmmdw_mode:
11611 if (!ins->need_vex)
11612 abort ();
11613
11614 switch (ins->vex.length)
11615 {
11616 case 128:
11617 oappend (ins, "WORD PTR ");
11618 break;
11619 case 256:
11620 oappend (ins, "DWORD PTR ");
11621 break;
11622 case 512:
11623 oappend (ins, "QWORD PTR ");
11624 break;
11625 default:
11626 abort ();
11627 }
11628 break;
11629 case xmmqd_mode:
11630 case evex_half_bcst_xmmqdh_mode:
11631 if (!ins->need_vex)
11632 abort ();
11633
11634 switch (ins->vex.length)
11635 {
11636 case 128:
11637 oappend (ins, "DWORD PTR ");
11638 break;
11639 case 256:
11640 oappend (ins, "QWORD PTR ");
11641 break;
11642 case 512:
11643 oappend (ins, "XMMWORD PTR ");
11644 break;
11645 default:
11646 abort ();
11647 }
11648 break;
11649 case ymmq_mode:
11650 if (!ins->need_vex)
11651 abort ();
11652
11653 switch (ins->vex.length)
11654 {
11655 case 128:
11656 oappend (ins, "QWORD PTR ");
11657 break;
11658 case 256:
11659 oappend (ins, "YMMWORD PTR ");
11660 break;
11661 case 512:
11662 oappend (ins, "ZMMWORD PTR ");
11663 break;
11664 default:
11665 abort ();
11666 }
11667 break;
11668 case o_mode:
11669 oappend (ins, "OWORD PTR ");
11670 break;
11671 case vex_vsib_d_w_dq_mode:
11672 case vex_vsib_q_w_dq_mode:
11673 if (!ins->need_vex)
11674 abort ();
11675 if (ins->vex.w)
11676 oappend (ins, "QWORD PTR ");
11677 else
11678 oappend (ins, "DWORD PTR ");
11679 break;
11680 case mask_bd_mode:
11681 if (!ins->need_vex || ins->vex.length != 128)
11682 abort ();
11683 if (ins->vex.w)
11684 oappend (ins, "DWORD PTR ");
11685 else
11686 oappend (ins, "BYTE PTR ");
11687 break;
11688 case mask_mode:
11689 if (!ins->need_vex)
11690 abort ();
11691 if (ins->vex.w)
11692 oappend (ins, "QWORD PTR ");
11693 else
11694 oappend (ins, "WORD PTR ");
11695 break;
11696 case v_bnd_mode:
11697 case v_bndmk_mode:
11698 default:
11699 break;
11700 }
11701 }
11702
11703 static void
11704 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11705 int bytemode, int sizeflag)
11706 {
11707 const char (*names)[8];
11708
11709 USED_REX (rexmask);
11710 if (ins->rex & rexmask)
11711 reg += 8;
11712
11713 switch (bytemode)
11714 {
11715 case b_mode:
11716 case b_swap_mode:
11717 if (reg & 4)
11718 USED_REX (0);
11719 if (ins->rex)
11720 names = att_names8rex;
11721 else
11722 names = att_names8;
11723 break;
11724 case w_mode:
11725 names = att_names16;
11726 break;
11727 case d_mode:
11728 case dw_mode:
11729 case db_mode:
11730 names = att_names32;
11731 break;
11732 case q_mode:
11733 names = att_names64;
11734 break;
11735 case m_mode:
11736 case v_bnd_mode:
11737 names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11738 break;
11739 case bnd_mode:
11740 case bnd_swap_mode:
11741 if (reg > 0x3)
11742 {
11743 oappend (ins, "(bad)");
11744 return;
11745 }
11746 names = att_names_bnd;
11747 break;
11748 case indir_v_mode:
11749 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11750 {
11751 names = att_names64;
11752 break;
11753 }
11754 /* Fall through. */
11755 case stack_v_mode:
11756 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11757 || (ins->rex & REX_W)))
11758 {
11759 names = att_names64;
11760 break;
11761 }
11762 bytemode = v_mode;
11763 /* Fall through. */
11764 case v_mode:
11765 case v_swap_mode:
11766 case dq_mode:
11767 USED_REX (REX_W);
11768 if (ins->rex & REX_W)
11769 names = att_names64;
11770 else if (bytemode != v_mode && bytemode != v_swap_mode)
11771 names = att_names32;
11772 else
11773 {
11774 if (sizeflag & DFLAG)
11775 names = att_names32;
11776 else
11777 names = att_names16;
11778 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11779 }
11780 break;
11781 case movsxd_mode:
11782 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11783 names = att_names16;
11784 else
11785 names = att_names32;
11786 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11787 break;
11788 case va_mode:
11789 names = (ins->address_mode == mode_64bit
11790 ? att_names64 : att_names32);
11791 if (!(ins->prefixes & PREFIX_ADDR))
11792 names = (ins->address_mode == mode_16bit
11793 ? att_names16 : names);
11794 else
11795 {
11796 /* Remove "addr16/addr32". */
11797 ins->all_prefixes[ins->last_addr_prefix] = 0;
11798 names = (ins->address_mode != mode_32bit
11799 ? att_names32 : att_names16);
11800 ins->used_prefixes |= PREFIX_ADDR;
11801 }
11802 break;
11803 case mask_bd_mode:
11804 case mask_mode:
11805 if (reg > 0x7)
11806 {
11807 oappend (ins, "(bad)");
11808 return;
11809 }
11810 names = att_names_mask;
11811 break;
11812 case 0:
11813 return;
11814 default:
11815 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11816 return;
11817 }
11818 oappend_register (ins, names[reg]);
11819 }
11820
11821 static bool
11822 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11823 {
11824 int add = (ins->rex & REX_B) ? 8 : 0;
11825 int riprel = 0;
11826 int shift;
11827
11828 if (ins->vex.evex)
11829 {
11830 switch (bytemode)
11831 {
11832 case dw_mode:
11833 case w_mode:
11834 case w_swap_mode:
11835 shift = 1;
11836 break;
11837 case db_mode:
11838 case b_mode:
11839 shift = 0;
11840 break;
11841 case dq_mode:
11842 if (ins->address_mode != mode_64bit)
11843 {
11844 case d_mode:
11845 case d_swap_mode:
11846 shift = 2;
11847 break;
11848 }
11849 /* fall through */
11850 case vex_vsib_d_w_dq_mode:
11851 case vex_vsib_q_w_dq_mode:
11852 case evex_x_gscat_mode:
11853 shift = ins->vex.w ? 3 : 2;
11854 break;
11855 case xh_mode:
11856 case evex_half_bcst_xmmqh_mode:
11857 case evex_half_bcst_xmmqdh_mode:
11858 if (ins->vex.b)
11859 {
11860 shift = ins->vex.w ? 2 : 1;
11861 break;
11862 }
11863 /* Fall through. */
11864 case x_mode:
11865 case evex_half_bcst_xmmq_mode:
11866 if (ins->vex.b)
11867 {
11868 shift = ins->vex.w ? 3 : 2;
11869 break;
11870 }
11871 /* Fall through. */
11872 case xmmqd_mode:
11873 case xmmdw_mode:
11874 case xmmq_mode:
11875 case ymmq_mode:
11876 case evex_x_nobcst_mode:
11877 case x_swap_mode:
11878 switch (ins->vex.length)
11879 {
11880 case 128:
11881 shift = 4;
11882 break;
11883 case 256:
11884 shift = 5;
11885 break;
11886 case 512:
11887 shift = 6;
11888 break;
11889 default:
11890 abort ();
11891 }
11892 /* Make necessary corrections to shift for modes that need it. */
11893 if (bytemode == xmmq_mode
11894 || bytemode == evex_half_bcst_xmmqh_mode
11895 || bytemode == evex_half_bcst_xmmq_mode
11896 || (bytemode == ymmq_mode && ins->vex.length == 128))
11897 shift -= 1;
11898 else if (bytemode == xmmqd_mode
11899 || bytemode == evex_half_bcst_xmmqdh_mode)
11900 shift -= 2;
11901 else if (bytemode == xmmdw_mode)
11902 shift -= 3;
11903 break;
11904 case ymm_mode:
11905 shift = 5;
11906 break;
11907 case xmm_mode:
11908 shift = 4;
11909 break;
11910 case q_mode:
11911 case q_swap_mode:
11912 shift = 3;
11913 break;
11914 case bw_unit_mode:
11915 shift = ins->vex.w ? 1 : 0;
11916 break;
11917 default:
11918 abort ();
11919 }
11920 }
11921 else
11922 shift = 0;
11923
11924 USED_REX (REX_B);
11925 if (ins->intel_syntax)
11926 intel_operand_size (ins, bytemode, sizeflag);
11927 append_seg (ins);
11928
11929 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11930 {
11931 /* 32/64 bit address mode */
11932 bfd_signed_vma disp = 0;
11933 int havedisp;
11934 int havebase;
11935 int needindex;
11936 int needaddr32;
11937 int base, rbase;
11938 int vindex = 0;
11939 int scale = 0;
11940 int addr32flag = !((sizeflag & AFLAG)
11941 || bytemode == v_bnd_mode
11942 || bytemode == v_bndmk_mode
11943 || bytemode == bnd_mode
11944 || bytemode == bnd_swap_mode);
11945 bool check_gather = false;
11946 const char (*indexes)[8] = NULL;
11947
11948 havebase = 1;
11949 base = ins->modrm.rm;
11950
11951 if (base == 4)
11952 {
11953 vindex = ins->sib.index;
11954 USED_REX (REX_X);
11955 if (ins->rex & REX_X)
11956 vindex += 8;
11957 switch (bytemode)
11958 {
11959 case vex_vsib_d_w_dq_mode:
11960 case vex_vsib_q_w_dq_mode:
11961 if (!ins->need_vex)
11962 abort ();
11963 if (ins->vex.evex)
11964 {
11965 if (!ins->vex.v)
11966 vindex += 16;
11967 check_gather = ins->obufp == ins->op_out[1];
11968 }
11969
11970 switch (ins->vex.length)
11971 {
11972 case 128:
11973 indexes = att_names_xmm;
11974 break;
11975 case 256:
11976 if (!ins->vex.w
11977 || bytemode == vex_vsib_q_w_dq_mode)
11978 indexes = att_names_ymm;
11979 else
11980 indexes = att_names_xmm;
11981 break;
11982 case 512:
11983 if (!ins->vex.w
11984 || bytemode == vex_vsib_q_w_dq_mode)
11985 indexes = att_names_zmm;
11986 else
11987 indexes = att_names_ymm;
11988 break;
11989 default:
11990 abort ();
11991 }
11992 break;
11993 default:
11994 if (vindex != 4)
11995 indexes = ins->address_mode == mode_64bit && !addr32flag
11996 ? att_names64 : att_names32;
11997 break;
11998 }
11999 scale = ins->sib.scale;
12000 base = ins->sib.base;
12001 ins->codep++;
12002 }
12003 else
12004 {
12005 /* Check for mandatory SIB. */
12006 if (bytemode == vex_vsib_d_w_dq_mode
12007 || bytemode == vex_vsib_q_w_dq_mode
12008 || bytemode == vex_sibmem_mode)
12009 {
12010 oappend (ins, "(bad)");
12011 return true;
12012 }
12013 }
12014 rbase = base + add;
12015
12016 switch (ins->modrm.mod)
12017 {
12018 case 0:
12019 if (base == 5)
12020 {
12021 havebase = 0;
12022 if (ins->address_mode == mode_64bit && !ins->has_sib)
12023 riprel = 1;
12024 if (!get32s (ins, &disp))
12025 return false;
12026 if (riprel && bytemode == v_bndmk_mode)
12027 {
12028 oappend (ins, "(bad)");
12029 return true;
12030 }
12031 }
12032 break;
12033 case 1:
12034 if (!fetch_code (ins->info, ins->codep + 1))
12035 return false;
12036 disp = *ins->codep++;
12037 if ((disp & 0x80) != 0)
12038 disp -= 0x100;
12039 if (ins->vex.evex && shift > 0)
12040 disp <<= shift;
12041 break;
12042 case 2:
12043 if (!get32s (ins, &disp))
12044 return false;
12045 break;
12046 }
12047
12048 needindex = 0;
12049 needaddr32 = 0;
12050 if (ins->has_sib
12051 && !havebase
12052 && !indexes
12053 && ins->address_mode != mode_16bit)
12054 {
12055 if (ins->address_mode == mode_64bit)
12056 {
12057 if (addr32flag)
12058 {
12059 /* Without base nor index registers, zero-extend the
12060 lower 32-bit displacement to 64 bits. */
12061 disp = (unsigned int) disp;
12062 needindex = 1;
12063 }
12064 needaddr32 = 1;
12065 }
12066 else
12067 {
12068 /* In 32-bit mode, we need index register to tell [offset]
12069 from [eiz*1 + offset]. */
12070 needindex = 1;
12071 }
12072 }
12073
12074 havedisp = (havebase
12075 || needindex
12076 || (ins->has_sib && (indexes || scale != 0)));
12077
12078 if (!ins->intel_syntax)
12079 if (ins->modrm.mod != 0 || base == 5)
12080 {
12081 if (havedisp || riprel)
12082 print_displacement (ins, disp);
12083 else
12084 print_operand_value (ins, disp, dis_style_address_offset);
12085 if (riprel)
12086 {
12087 set_op (ins, disp, true);
12088 oappend_char (ins, '(');
12089 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
12090 dis_style_register);
12091 oappend_char (ins, ')');
12092 }
12093 }
12094
12095 if ((havebase || indexes || needindex || needaddr32 || riprel)
12096 && (ins->address_mode != mode_64bit
12097 || ((bytemode != v_bnd_mode)
12098 && (bytemode != v_bndmk_mode)
12099 && (bytemode != bnd_mode)
12100 && (bytemode != bnd_swap_mode))))
12101 ins->used_prefixes |= PREFIX_ADDR;
12102
12103 if (havedisp || (ins->intel_syntax && riprel))
12104 {
12105 oappend_char (ins, ins->open_char);
12106 if (ins->intel_syntax && riprel)
12107 {
12108 set_op (ins, disp, true);
12109 oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12110 dis_style_register);
12111 }
12112 if (havebase)
12113 oappend_register
12114 (ins,
12115 (ins->address_mode == mode_64bit && !addr32flag
12116 ? att_names64 : att_names32)[rbase]);
12117 if (ins->has_sib)
12118 {
12119 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12120 print index to tell base + index from base. */
12121 if (scale != 0
12122 || needindex
12123 || indexes
12124 || (havebase && base != ESP_REG_NUM))
12125 {
12126 if (!ins->intel_syntax || havebase)
12127 oappend_char (ins, ins->separator_char);
12128 if (indexes)
12129 {
12130 if (ins->address_mode == mode_64bit || vindex < 16)
12131 oappend_register (ins, indexes[vindex]);
12132 else
12133 oappend (ins, "(bad)");
12134 }
12135 else
12136 oappend_register (ins,
12137 ins->address_mode == mode_64bit
12138 && !addr32flag
12139 ? att_index64
12140 : att_index32);
12141
12142 oappend_char (ins, ins->scale_char);
12143 oappend_char_with_style (ins, '0' + (1 << scale),
12144 dis_style_immediate);
12145 }
12146 }
12147 if (ins->intel_syntax
12148 && (disp || ins->modrm.mod != 0 || base == 5))
12149 {
12150 if (!havedisp || disp >= 0)
12151 oappend_char (ins, '+');
12152 if (havedisp)
12153 print_displacement (ins, disp);
12154 else
12155 print_operand_value (ins, disp, dis_style_address_offset);
12156 }
12157
12158 oappend_char (ins, ins->close_char);
12159
12160 if (check_gather)
12161 {
12162 /* Both XMM/YMM/ZMM registers must be distinct. */
12163 int modrm_reg = ins->modrm.reg;
12164
12165 if (ins->rex & REX_R)
12166 modrm_reg += 8;
12167 if (!ins->vex.r)
12168 modrm_reg += 16;
12169 if (vindex == modrm_reg)
12170 oappend (ins, "/(bad)");
12171 }
12172 }
12173 else if (ins->intel_syntax)
12174 {
12175 if (ins->modrm.mod != 0 || base == 5)
12176 {
12177 if (!ins->active_seg_prefix)
12178 {
12179 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12180 oappend (ins, ":");
12181 }
12182 print_operand_value (ins, disp, dis_style_text);
12183 }
12184 }
12185 }
12186 else if (bytemode == v_bnd_mode
12187 || bytemode == v_bndmk_mode
12188 || bytemode == bnd_mode
12189 || bytemode == bnd_swap_mode
12190 || bytemode == vex_vsib_d_w_dq_mode
12191 || bytemode == vex_vsib_q_w_dq_mode)
12192 {
12193 oappend (ins, "(bad)");
12194 return true;
12195 }
12196 else
12197 {
12198 /* 16 bit address mode */
12199 int disp = 0;
12200
12201 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12202 switch (ins->modrm.mod)
12203 {
12204 case 0:
12205 if (ins->modrm.rm == 6)
12206 {
12207 case 2:
12208 if (!get16 (ins, &disp))
12209 return false;
12210 if ((disp & 0x8000) != 0)
12211 disp -= 0x10000;
12212 }
12213 break;
12214 case 1:
12215 if (!fetch_code (ins->info, ins->codep + 1))
12216 return false;
12217 disp = *ins->codep++;
12218 if ((disp & 0x80) != 0)
12219 disp -= 0x100;
12220 if (ins->vex.evex && shift > 0)
12221 disp <<= shift;
12222 break;
12223 }
12224
12225 if (!ins->intel_syntax)
12226 if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12227 print_displacement (ins, disp);
12228
12229 if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12230 {
12231 oappend_char (ins, ins->open_char);
12232 oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12233 : att_index16[ins->modrm.rm]);
12234 if (ins->intel_syntax
12235 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12236 {
12237 if (disp >= 0)
12238 oappend_char (ins, '+');
12239 print_displacement (ins, disp);
12240 }
12241
12242 oappend_char (ins, ins->close_char);
12243 }
12244 else if (ins->intel_syntax)
12245 {
12246 if (!ins->active_seg_prefix)
12247 {
12248 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12249 oappend (ins, ":");
12250 }
12251 print_operand_value (ins, disp & 0xffff, dis_style_text);
12252 }
12253 }
12254 if (ins->vex.b)
12255 {
12256 ins->evex_used |= EVEX_b_used;
12257
12258 /* Broadcast can only ever be valid for memory sources. */
12259 if (ins->obufp == ins->op_out[0])
12260 ins->vex.no_broadcast = true;
12261
12262 if (!ins->vex.no_broadcast
12263 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12264 {
12265 if (bytemode == xh_mode)
12266 {
12267 switch (ins->vex.length)
12268 {
12269 case 128:
12270 oappend (ins, "{1to8}");
12271 break;
12272 case 256:
12273 oappend (ins, "{1to16}");
12274 break;
12275 case 512:
12276 oappend (ins, "{1to32}");
12277 break;
12278 default:
12279 abort ();
12280 }
12281 }
12282 else if (bytemode == q_mode
12283 || bytemode == ymmq_mode)
12284 ins->vex.no_broadcast = true;
12285 else if (ins->vex.w
12286 || bytemode == evex_half_bcst_xmmqdh_mode
12287 || bytemode == evex_half_bcst_xmmq_mode)
12288 {
12289 switch (ins->vex.length)
12290 {
12291 case 128:
12292 oappend (ins, "{1to2}");
12293 break;
12294 case 256:
12295 oappend (ins, "{1to4}");
12296 break;
12297 case 512:
12298 oappend (ins, "{1to8}");
12299 break;
12300 default:
12301 abort ();
12302 }
12303 }
12304 else if (bytemode == x_mode
12305 || bytemode == evex_half_bcst_xmmqh_mode)
12306 {
12307 switch (ins->vex.length)
12308 {
12309 case 128:
12310 oappend (ins, "{1to4}");
12311 break;
12312 case 256:
12313 oappend (ins, "{1to8}");
12314 break;
12315 case 512:
12316 oappend (ins, "{1to16}");
12317 break;
12318 default:
12319 abort ();
12320 }
12321 }
12322 else
12323 ins->vex.no_broadcast = true;
12324 }
12325 if (ins->vex.no_broadcast)
12326 oappend (ins, "{bad}");
12327 }
12328
12329 return true;
12330 }
12331
12332 static bool
12333 OP_E (instr_info *ins, int bytemode, int sizeflag)
12334 {
12335 /* Skip mod/rm byte. */
12336 MODRM_CHECK;
12337 ins->codep++;
12338
12339 if (ins->modrm.mod == 3)
12340 {
12341 if ((sizeflag & SUFFIX_ALWAYS)
12342 && (bytemode == b_swap_mode
12343 || bytemode == bnd_swap_mode
12344 || bytemode == v_swap_mode))
12345 swap_operand (ins);
12346
12347 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12348 return true;
12349 }
12350
12351 return OP_E_memory (ins, bytemode, sizeflag);
12352 }
12353
12354 static bool
12355 OP_G (instr_info *ins, int bytemode, int sizeflag)
12356 {
12357 if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
12358 oappend (ins, "(bad)");
12359 else
12360 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12361 return true;
12362 }
12363
12364 static bool
12365 get64 (instr_info *ins, uint64_t *res)
12366 {
12367 unsigned int a;
12368 unsigned int b;
12369
12370 if (!fetch_code (ins->info, ins->codep + 8))
12371 return false;
12372 a = *ins->codep++ & 0xff;
12373 a |= (*ins->codep++ & 0xff) << 8;
12374 a |= (*ins->codep++ & 0xff) << 16;
12375 a |= (*ins->codep++ & 0xffu) << 24;
12376 b = *ins->codep++ & 0xff;
12377 b |= (*ins->codep++ & 0xff) << 8;
12378 b |= (*ins->codep++ & 0xff) << 16;
12379 b |= (*ins->codep++ & 0xffu) << 24;
12380 *res = a + ((uint64_t) b << 32);
12381 return true;
12382 }
12383
12384 static bool
12385 get32 (instr_info *ins, bfd_signed_vma *res)
12386 {
12387 if (!fetch_code (ins->info, ins->codep + 4))
12388 return false;
12389 *res = *ins->codep++ & (bfd_vma) 0xff;
12390 *res |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12391 *res |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12392 *res |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12393 return true;
12394 }
12395
12396 static bool
12397 get32s (instr_info *ins, bfd_signed_vma *res)
12398 {
12399 if (!get32 (ins, res))
12400 return false;
12401
12402 *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12403
12404 return true;
12405 }
12406
12407 static bool
12408 get16 (instr_info *ins, int *res)
12409 {
12410 if (!fetch_code (ins->info, ins->codep + 2))
12411 return false;
12412 *res = *ins->codep++ & 0xff;
12413 *res |= (*ins->codep++ & 0xff) << 8;
12414 return true;
12415 }
12416
12417 static void
12418 set_op (instr_info *ins, bfd_vma op, bool riprel)
12419 {
12420 ins->op_index[ins->op_ad] = ins->op_ad;
12421 if (ins->address_mode == mode_64bit)
12422 ins->op_address[ins->op_ad] = op;
12423 else /* Mask to get a 32-bit address. */
12424 ins->op_address[ins->op_ad] = op & 0xffffffff;
12425 ins->op_riprel[ins->op_ad] = riprel;
12426 }
12427
12428 static bool
12429 OP_REG (instr_info *ins, int code, int sizeflag)
12430 {
12431 const char *s;
12432 int add;
12433
12434 switch (code)
12435 {
12436 case es_reg: case ss_reg: case cs_reg:
12437 case ds_reg: case fs_reg: case gs_reg:
12438 oappend_register (ins, att_names_seg[code - es_reg]);
12439 return true;
12440 }
12441
12442 USED_REX (REX_B);
12443 if (ins->rex & REX_B)
12444 add = 8;
12445 else
12446 add = 0;
12447
12448 switch (code)
12449 {
12450 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12451 case sp_reg: case bp_reg: case si_reg: case di_reg:
12452 s = att_names16[code - ax_reg + add];
12453 break;
12454 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12455 USED_REX (0);
12456 /* Fall through. */
12457 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12458 if (ins->rex)
12459 s = att_names8rex[code - al_reg + add];
12460 else
12461 s = att_names8[code - al_reg];
12462 break;
12463 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12464 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12465 if (ins->address_mode == mode_64bit
12466 && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12467 {
12468 s = att_names64[code - rAX_reg + add];
12469 break;
12470 }
12471 code += eAX_reg - rAX_reg;
12472 /* Fall through. */
12473 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12474 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12475 USED_REX (REX_W);
12476 if (ins->rex & REX_W)
12477 s = att_names64[code - eAX_reg + add];
12478 else
12479 {
12480 if (sizeflag & DFLAG)
12481 s = att_names32[code - eAX_reg + add];
12482 else
12483 s = att_names16[code - eAX_reg + add];
12484 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12485 }
12486 break;
12487 default:
12488 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12489 return true;
12490 }
12491 oappend_register (ins, s);
12492 return true;
12493 }
12494
12495 static bool
12496 OP_IMREG (instr_info *ins, int code, int sizeflag)
12497 {
12498 const char *s;
12499
12500 switch (code)
12501 {
12502 case indir_dx_reg:
12503 if (!ins->intel_syntax)
12504 {
12505 oappend (ins, "(%dx)");
12506 return true;
12507 }
12508 s = att_names16[dx_reg - ax_reg];
12509 break;
12510 case al_reg: case cl_reg:
12511 s = att_names8[code - al_reg];
12512 break;
12513 case eAX_reg:
12514 USED_REX (REX_W);
12515 if (ins->rex & REX_W)
12516 {
12517 s = *att_names64;
12518 break;
12519 }
12520 /* Fall through. */
12521 case z_mode_ax_reg:
12522 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12523 s = *att_names32;
12524 else
12525 s = *att_names16;
12526 if (!(ins->rex & REX_W))
12527 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12528 break;
12529 default:
12530 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12531 return true;
12532 }
12533 oappend_register (ins, s);
12534 return true;
12535 }
12536
12537 static bool
12538 OP_I (instr_info *ins, int bytemode, int sizeflag)
12539 {
12540 bfd_signed_vma op;
12541 bfd_signed_vma mask = -1;
12542
12543 switch (bytemode)
12544 {
12545 case b_mode:
12546 if (!fetch_code (ins->info, ins->codep + 1))
12547 return false;
12548 op = *ins->codep++;
12549 mask = 0xff;
12550 break;
12551 case v_mode:
12552 USED_REX (REX_W);
12553 if (ins->rex & REX_W)
12554 {
12555 if (!get32s (ins, &op))
12556 return false;
12557 }
12558 else
12559 {
12560 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12561 if (sizeflag & DFLAG)
12562 {
12563 case d_mode:
12564 if (!get32 (ins, &op))
12565 return false;
12566 mask = 0xffffffff;
12567 }
12568 else
12569 {
12570 int num;
12571
12572 case w_mode:
12573 if (!get16 (ins, &num))
12574 return false;
12575 op = num;
12576 mask = 0xfffff;
12577 }
12578 }
12579 break;
12580 case const_1_mode:
12581 if (ins->intel_syntax)
12582 oappend (ins, "1");
12583 return true;
12584 default:
12585 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12586 return true;
12587 }
12588
12589 op &= mask;
12590 oappend_immediate (ins, op);
12591 return true;
12592 }
12593
12594 static bool
12595 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12596 {
12597 uint64_t op;
12598
12599 if (bytemode != v_mode || ins->address_mode != mode_64bit
12600 || !(ins->rex & REX_W))
12601 return OP_I (ins, bytemode, sizeflag);
12602
12603 USED_REX (REX_W);
12604
12605 if (!get64 (ins, &op))
12606 return false;
12607
12608 oappend_immediate (ins, op);
12609 return true;
12610 }
12611
12612 static bool
12613 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12614 {
12615 bfd_signed_vma op;
12616
12617 switch (bytemode)
12618 {
12619 case b_mode:
12620 case b_T_mode:
12621 if (!fetch_code (ins->info, ins->codep + 1))
12622 return false;
12623 op = *ins->codep++;
12624 if ((op & 0x80) != 0)
12625 op -= 0x100;
12626 if (bytemode == b_T_mode)
12627 {
12628 if (ins->address_mode != mode_64bit
12629 || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12630 {
12631 /* The operand-size prefix is overridden by a REX prefix. */
12632 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12633 op &= 0xffffffff;
12634 else
12635 op &= 0xffff;
12636 }
12637 }
12638 else
12639 {
12640 if (!(ins->rex & REX_W))
12641 {
12642 if (sizeflag & DFLAG)
12643 op &= 0xffffffff;
12644 else
12645 op &= 0xffff;
12646 }
12647 }
12648 break;
12649 case v_mode:
12650 /* The operand-size prefix is overridden by a REX prefix. */
12651 if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12652 {
12653 int val;
12654
12655 if (!get16 (ins, &val))
12656 return false;
12657 op = val;
12658 }
12659 else if (!get32s (ins, &op))
12660 return false;
12661 break;
12662 default:
12663 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12664 return true;
12665 }
12666
12667 oappend_immediate (ins, op);
12668 return true;
12669 }
12670
12671 static bool
12672 OP_J (instr_info *ins, int bytemode, int sizeflag)
12673 {
12674 bfd_vma disp;
12675 bfd_vma mask = -1;
12676 bfd_vma segment = 0;
12677
12678 switch (bytemode)
12679 {
12680 case b_mode:
12681 if (!fetch_code (ins->info, ins->codep + 1))
12682 return false;
12683 disp = *ins->codep++;
12684 if ((disp & 0x80) != 0)
12685 disp -= 0x100;
12686 break;
12687 case v_mode:
12688 case dqw_mode:
12689 if ((sizeflag & DFLAG)
12690 || (ins->address_mode == mode_64bit
12691 && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12692 || (ins->rex & REX_W))))
12693 {
12694 bfd_signed_vma val;
12695
12696 if (!get32s (ins, &val))
12697 return false;
12698 disp = val;
12699 }
12700 else
12701 {
12702 int val;
12703
12704 if (!get16 (ins, &val))
12705 return false;
12706 disp = val & 0x8000 ? val - 0x10000 : val;
12707 /* In 16bit mode, address is wrapped around at 64k within
12708 the same segment. Otherwise, a data16 prefix on a jump
12709 instruction means that the pc is masked to 16 bits after
12710 the displacement is added! */
12711 mask = 0xffff;
12712 if ((ins->prefixes & PREFIX_DATA) == 0)
12713 segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12714 & ~((bfd_vma) 0xffff));
12715 }
12716 if (ins->address_mode != mode_64bit
12717 || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12718 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12719 break;
12720 default:
12721 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12722 return true;
12723 }
12724 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12725 | segment;
12726 set_op (ins, disp, false);
12727 print_operand_value (ins, disp, dis_style_text);
12728 return true;
12729 }
12730
12731 static bool
12732 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12733 {
12734 if (bytemode == w_mode)
12735 {
12736 oappend_register (ins, att_names_seg[ins->modrm.reg]);
12737 return true;
12738 }
12739 return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12740 }
12741
12742 static bool
12743 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12744 {
12745 int seg, offset, res;
12746 char scratch[24];
12747
12748 if (sizeflag & DFLAG)
12749 {
12750 bfd_signed_vma val;
12751
12752 if (!get32 (ins, &val))
12753 return false;;
12754 offset = val;
12755 }
12756 else if (!get16 (ins, &offset))
12757 return false;
12758 if (!get16 (ins, &seg))
12759 return false;;
12760 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12761
12762 res = snprintf (scratch, ARRAY_SIZE (scratch),
12763 ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12764 seg, offset);
12765 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12766 abort ();
12767 oappend (ins, scratch);
12768 return true;
12769 }
12770
12771 static bool
12772 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12773 {
12774 bfd_vma off;
12775
12776 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12777 intel_operand_size (ins, bytemode, sizeflag);
12778 append_seg (ins);
12779
12780 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12781 {
12782 bfd_signed_vma val;
12783
12784 if (!get32 (ins, &val))
12785 return false;
12786 off = val;
12787 }
12788 else
12789 {
12790 int val;
12791
12792 if (!get16 (ins, &val))
12793 return false;
12794 off = val;
12795 }
12796
12797 if (ins->intel_syntax)
12798 {
12799 if (!ins->active_seg_prefix)
12800 {
12801 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12802 oappend (ins, ":");
12803 }
12804 }
12805 print_operand_value (ins, off, dis_style_address_offset);
12806 return true;
12807 }
12808
12809 static bool
12810 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12811 {
12812 uint64_t off;
12813
12814 if (ins->address_mode != mode_64bit
12815 || (ins->prefixes & PREFIX_ADDR))
12816 return OP_OFF (ins, bytemode, sizeflag);
12817
12818 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12819 intel_operand_size (ins, bytemode, sizeflag);
12820 append_seg (ins);
12821
12822 if (!get64 (ins, &off))
12823 return false;
12824
12825 if (ins->intel_syntax)
12826 {
12827 if (!ins->active_seg_prefix)
12828 {
12829 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12830 oappend (ins, ":");
12831 }
12832 }
12833 print_operand_value (ins, off, dis_style_address_offset);
12834 return true;
12835 }
12836
12837 static void
12838 ptr_reg (instr_info *ins, int code, int sizeflag)
12839 {
12840 const char *s;
12841
12842 *ins->obufp++ = ins->open_char;
12843 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12844 if (ins->address_mode == mode_64bit)
12845 {
12846 if (!(sizeflag & AFLAG))
12847 s = att_names32[code - eAX_reg];
12848 else
12849 s = att_names64[code - eAX_reg];
12850 }
12851 else if (sizeflag & AFLAG)
12852 s = att_names32[code - eAX_reg];
12853 else
12854 s = att_names16[code - eAX_reg];
12855 oappend_register (ins, s);
12856 oappend_char (ins, ins->close_char);
12857 }
12858
12859 static bool
12860 OP_ESreg (instr_info *ins, int code, int sizeflag)
12861 {
12862 if (ins->intel_syntax)
12863 {
12864 switch (ins->codep[-1])
12865 {
12866 case 0x6d: /* insw/insl */
12867 intel_operand_size (ins, z_mode, sizeflag);
12868 break;
12869 case 0xa5: /* movsw/movsl/movsq */
12870 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12871 case 0xab: /* stosw/stosl */
12872 case 0xaf: /* scasw/scasl */
12873 intel_operand_size (ins, v_mode, sizeflag);
12874 break;
12875 default:
12876 intel_operand_size (ins, b_mode, sizeflag);
12877 }
12878 }
12879 oappend_register (ins, att_names_seg[0]);
12880 oappend_char (ins, ':');
12881 ptr_reg (ins, code, sizeflag);
12882 return true;
12883 }
12884
12885 static bool
12886 OP_DSreg (instr_info *ins, int code, int sizeflag)
12887 {
12888 if (ins->intel_syntax)
12889 {
12890 switch (ins->codep[-1])
12891 {
12892 case 0x6f: /* outsw/outsl */
12893 intel_operand_size (ins, z_mode, sizeflag);
12894 break;
12895 case 0xa5: /* movsw/movsl/movsq */
12896 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12897 case 0xad: /* lodsw/lodsl/lodsq */
12898 intel_operand_size (ins, v_mode, sizeflag);
12899 break;
12900 default:
12901 intel_operand_size (ins, b_mode, sizeflag);
12902 }
12903 }
12904 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12905 default segment register DS is printed. */
12906 if (!ins->active_seg_prefix)
12907 ins->active_seg_prefix = PREFIX_DS;
12908 append_seg (ins);
12909 ptr_reg (ins, code, sizeflag);
12910 return true;
12911 }
12912
12913 static bool
12914 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12915 int sizeflag ATTRIBUTE_UNUSED)
12916 {
12917 int add, res;
12918 char scratch[8];
12919
12920 if (ins->rex & REX_R)
12921 {
12922 USED_REX (REX_R);
12923 add = 8;
12924 }
12925 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12926 {
12927 ins->all_prefixes[ins->last_lock_prefix] = 0;
12928 ins->used_prefixes |= PREFIX_LOCK;
12929 add = 8;
12930 }
12931 else
12932 add = 0;
12933 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12934 ins->modrm.reg + add);
12935 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12936 abort ();
12937 oappend_register (ins, scratch);
12938 return true;
12939 }
12940
12941 static bool
12942 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12943 int sizeflag ATTRIBUTE_UNUSED)
12944 {
12945 int add, res;
12946 char scratch[8];
12947
12948 USED_REX (REX_R);
12949 if (ins->rex & REX_R)
12950 add = 8;
12951 else
12952 add = 0;
12953 res = snprintf (scratch, ARRAY_SIZE (scratch),
12954 ins->intel_syntax ? "dr%d" : "%%db%d",
12955 ins->modrm.reg + add);
12956 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12957 abort ();
12958 oappend (ins, scratch);
12959 return true;
12960 }
12961
12962 static bool
12963 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12964 int sizeflag ATTRIBUTE_UNUSED)
12965 {
12966 int res;
12967 char scratch[8];
12968
12969 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12970 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12971 abort ();
12972 oappend_register (ins, scratch);
12973 return true;
12974 }
12975
12976 static bool
12977 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12978 int sizeflag ATTRIBUTE_UNUSED)
12979 {
12980 int reg = ins->modrm.reg;
12981 const char (*names)[8];
12982
12983 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12984 if (ins->prefixes & PREFIX_DATA)
12985 {
12986 names = att_names_xmm;
12987 USED_REX (REX_R);
12988 if (ins->rex & REX_R)
12989 reg += 8;
12990 }
12991 else
12992 names = att_names_mm;
12993 oappend_register (ins, names[reg]);
12994 return true;
12995 }
12996
12997 static void
12998 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12999 {
13000 const char (*names)[8];
13001
13002 if (bytemode == xmmq_mode
13003 || bytemode == evex_half_bcst_xmmqh_mode
13004 || bytemode == evex_half_bcst_xmmq_mode)
13005 {
13006 switch (ins->vex.length)
13007 {
13008 case 128:
13009 case 256:
13010 names = att_names_xmm;
13011 break;
13012 case 512:
13013 names = att_names_ymm;
13014 ins->evex_used |= EVEX_len_used;
13015 break;
13016 default:
13017 abort ();
13018 }
13019 }
13020 else if (bytemode == ymm_mode)
13021 names = att_names_ymm;
13022 else if (bytemode == tmm_mode)
13023 {
13024 if (reg >= 8)
13025 {
13026 oappend (ins, "(bad)");
13027 return;
13028 }
13029 names = att_names_tmm;
13030 }
13031 else if (ins->need_vex
13032 && bytemode != xmm_mode
13033 && bytemode != scalar_mode
13034 && bytemode != xmmdw_mode
13035 && bytemode != xmmqd_mode
13036 && bytemode != evex_half_bcst_xmmqdh_mode
13037 && bytemode != w_swap_mode
13038 && bytemode != b_mode
13039 && bytemode != w_mode
13040 && bytemode != d_mode
13041 && bytemode != q_mode)
13042 {
13043 ins->evex_used |= EVEX_len_used;
13044 switch (ins->vex.length)
13045 {
13046 case 128:
13047 names = att_names_xmm;
13048 break;
13049 case 256:
13050 if (ins->vex.w
13051 || bytemode != vex_vsib_q_w_dq_mode)
13052 names = att_names_ymm;
13053 else
13054 names = att_names_xmm;
13055 break;
13056 case 512:
13057 if (ins->vex.w
13058 || bytemode != vex_vsib_q_w_dq_mode)
13059 names = att_names_zmm;
13060 else
13061 names = att_names_ymm;
13062 break;
13063 default:
13064 abort ();
13065 }
13066 }
13067 else
13068 names = att_names_xmm;
13069 oappend_register (ins, names[reg]);
13070 }
13071
13072 static bool
13073 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13074 {
13075 unsigned int reg = ins->modrm.reg;
13076
13077 USED_REX (REX_R);
13078 if (ins->rex & REX_R)
13079 reg += 8;
13080 if (ins->vex.evex)
13081 {
13082 if (!ins->vex.r)
13083 reg += 16;
13084 }
13085
13086 if (bytemode == tmm_mode)
13087 ins->modrm.reg = reg;
13088 else if (bytemode == scalar_mode)
13089 ins->vex.no_broadcast = true;
13090
13091 print_vector_reg (ins, reg, bytemode);
13092 return true;
13093 }
13094
13095 static bool
13096 OP_EM (instr_info *ins, int bytemode, int sizeflag)
13097 {
13098 int reg;
13099 const char (*names)[8];
13100
13101 if (ins->modrm.mod != 3)
13102 {
13103 if (ins->intel_syntax
13104 && (bytemode == v_mode || bytemode == v_swap_mode))
13105 {
13106 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13107 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13108 }
13109 return OP_E (ins, bytemode, sizeflag);
13110 }
13111
13112 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13113 swap_operand (ins);
13114
13115 /* Skip mod/rm byte. */
13116 MODRM_CHECK;
13117 ins->codep++;
13118 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13119 reg = ins->modrm.rm;
13120 if (ins->prefixes & PREFIX_DATA)
13121 {
13122 names = att_names_xmm;
13123 USED_REX (REX_B);
13124 if (ins->rex & REX_B)
13125 reg += 8;
13126 }
13127 else
13128 names = att_names_mm;
13129 oappend_register (ins, names[reg]);
13130 return true;
13131 }
13132
13133 /* cvt* are the only instructions in sse2 which have
13134 both SSE and MMX operands and also have 0x66 prefix
13135 in their opcode. 0x66 was originally used to differentiate
13136 between SSE and MMX instruction(operands). So we have to handle the
13137 cvt* separately using OP_EMC and OP_MXC */
13138 static bool
13139 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
13140 {
13141 if (ins->modrm.mod != 3)
13142 {
13143 if (ins->intel_syntax && bytemode == v_mode)
13144 {
13145 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13146 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13147 }
13148 return OP_E (ins, bytemode, sizeflag);
13149 }
13150
13151 /* Skip mod/rm byte. */
13152 MODRM_CHECK;
13153 ins->codep++;
13154 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13155 oappend_register (ins, att_names_mm[ins->modrm.rm]);
13156 return true;
13157 }
13158
13159 static bool
13160 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13161 int sizeflag ATTRIBUTE_UNUSED)
13162 {
13163 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13164 oappend_register (ins, att_names_mm[ins->modrm.reg]);
13165 return true;
13166 }
13167
13168 static bool
13169 OP_EX (instr_info *ins, int bytemode, int sizeflag)
13170 {
13171 int reg;
13172
13173 /* Skip mod/rm byte. */
13174 MODRM_CHECK;
13175 ins->codep++;
13176
13177 if (bytemode == dq_mode)
13178 bytemode = ins->vex.w ? q_mode : d_mode;
13179
13180 if (ins->modrm.mod != 3)
13181 return OP_E_memory (ins, bytemode, sizeflag);
13182
13183 reg = ins->modrm.rm;
13184 USED_REX (REX_B);
13185 if (ins->rex & REX_B)
13186 reg += 8;
13187 if (ins->vex.evex)
13188 {
13189 USED_REX (REX_X);
13190 if ((ins->rex & REX_X))
13191 reg += 16;
13192 }
13193
13194 if ((sizeflag & SUFFIX_ALWAYS)
13195 && (bytemode == x_swap_mode
13196 || bytemode == w_swap_mode
13197 || bytemode == d_swap_mode
13198 || bytemode == q_swap_mode))
13199 swap_operand (ins);
13200
13201 if (bytemode == tmm_mode)
13202 ins->modrm.rm = reg;
13203
13204 print_vector_reg (ins, reg, bytemode);
13205 return true;
13206 }
13207
13208 static bool
13209 OP_MS (instr_info *ins, int bytemode, int sizeflag)
13210 {
13211 if (ins->modrm.mod == 3)
13212 return OP_EM (ins, bytemode, sizeflag);
13213 return BadOp (ins);
13214 }
13215
13216 static bool
13217 OP_XS (instr_info *ins, int bytemode, int sizeflag)
13218 {
13219 if (ins->modrm.mod == 3)
13220 return OP_EX (ins, bytemode, sizeflag);
13221 return BadOp (ins);
13222 }
13223
13224 static bool
13225 OP_M (instr_info *ins, int bytemode, int sizeflag)
13226 {
13227 if (ins->modrm.mod == 3)
13228 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13229 return BadOp (ins);
13230 return OP_E (ins, bytemode, sizeflag);
13231 }
13232
13233 static bool
13234 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13235 {
13236 if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13237 return BadOp (ins);
13238 return OP_E (ins, bytemode, sizeflag);
13239 }
13240
13241 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13242 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13243
13244 static bool
13245 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13246 {
13247 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13248 {
13249 ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13250 return true;
13251 }
13252 if (opnd == 0)
13253 return OP_REG (ins, eAX_reg, sizeflag);
13254 return OP_IMREG (ins, eAX_reg, sizeflag);
13255 }
13256
13257 static const char *const Suffix3DNow[] = {
13258 /* 00 */ NULL, NULL, NULL, NULL,
13259 /* 04 */ NULL, NULL, NULL, NULL,
13260 /* 08 */ NULL, NULL, NULL, NULL,
13261 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13262 /* 10 */ NULL, NULL, NULL, NULL,
13263 /* 14 */ NULL, NULL, NULL, NULL,
13264 /* 18 */ NULL, NULL, NULL, NULL,
13265 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13266 /* 20 */ NULL, NULL, NULL, NULL,
13267 /* 24 */ NULL, NULL, NULL, NULL,
13268 /* 28 */ NULL, NULL, NULL, NULL,
13269 /* 2C */ NULL, NULL, NULL, NULL,
13270 /* 30 */ NULL, NULL, NULL, NULL,
13271 /* 34 */ NULL, NULL, NULL, NULL,
13272 /* 38 */ NULL, NULL, NULL, NULL,
13273 /* 3C */ NULL, NULL, NULL, NULL,
13274 /* 40 */ NULL, NULL, NULL, NULL,
13275 /* 44 */ NULL, NULL, NULL, NULL,
13276 /* 48 */ NULL, NULL, NULL, NULL,
13277 /* 4C */ NULL, NULL, NULL, NULL,
13278 /* 50 */ NULL, NULL, NULL, NULL,
13279 /* 54 */ NULL, NULL, NULL, NULL,
13280 /* 58 */ NULL, NULL, NULL, NULL,
13281 /* 5C */ NULL, NULL, NULL, NULL,
13282 /* 60 */ NULL, NULL, NULL, NULL,
13283 /* 64 */ NULL, NULL, NULL, NULL,
13284 /* 68 */ NULL, NULL, NULL, NULL,
13285 /* 6C */ NULL, NULL, NULL, NULL,
13286 /* 70 */ NULL, NULL, NULL, NULL,
13287 /* 74 */ NULL, NULL, NULL, NULL,
13288 /* 78 */ NULL, NULL, NULL, NULL,
13289 /* 7C */ NULL, NULL, NULL, NULL,
13290 /* 80 */ NULL, NULL, NULL, NULL,
13291 /* 84 */ NULL, NULL, NULL, NULL,
13292 /* 88 */ NULL, NULL, "pfnacc", NULL,
13293 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13294 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13295 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13296 /* 98 */ NULL, NULL, "pfsub", NULL,
13297 /* 9C */ NULL, NULL, "pfadd", NULL,
13298 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13299 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13300 /* A8 */ NULL, NULL, "pfsubr", NULL,
13301 /* AC */ NULL, NULL, "pfacc", NULL,
13302 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13303 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13304 /* B8 */ NULL, NULL, NULL, "pswapd",
13305 /* BC */ NULL, NULL, NULL, "pavgusb",
13306 /* C0 */ NULL, NULL, NULL, NULL,
13307 /* C4 */ NULL, NULL, NULL, NULL,
13308 /* C8 */ NULL, NULL, NULL, NULL,
13309 /* CC */ NULL, NULL, NULL, NULL,
13310 /* D0 */ NULL, NULL, NULL, NULL,
13311 /* D4 */ NULL, NULL, NULL, NULL,
13312 /* D8 */ NULL, NULL, NULL, NULL,
13313 /* DC */ NULL, NULL, NULL, NULL,
13314 /* E0 */ NULL, NULL, NULL, NULL,
13315 /* E4 */ NULL, NULL, NULL, NULL,
13316 /* E8 */ NULL, NULL, NULL, NULL,
13317 /* EC */ NULL, NULL, NULL, NULL,
13318 /* F0 */ NULL, NULL, NULL, NULL,
13319 /* F4 */ NULL, NULL, NULL, NULL,
13320 /* F8 */ NULL, NULL, NULL, NULL,
13321 /* FC */ NULL, NULL, NULL, NULL,
13322 };
13323
13324 static bool
13325 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13326 int sizeflag ATTRIBUTE_UNUSED)
13327 {
13328 const char *mnemonic;
13329
13330 if (!fetch_code (ins->info, ins->codep + 1))
13331 return false;
13332 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13333 place where an 8-bit immediate would normally go. ie. the last
13334 byte of the instruction. */
13335 ins->obufp = ins->mnemonicendp;
13336 mnemonic = Suffix3DNow[*ins->codep++ & 0xff];
13337 if (mnemonic)
13338 ins->obufp = stpcpy (ins->obufp, mnemonic);
13339 else
13340 {
13341 /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13342 of the opcode (0x0f0f) and the opcode suffix, we need to do
13343 all the ins->modrm processing first, and don't know until now that
13344 we have a bad opcode. This necessitates some cleaning up. */
13345 ins->op_out[0][0] = '\0';
13346 ins->op_out[1][0] = '\0';
13347 BadOp (ins);
13348 }
13349 ins->mnemonicendp = ins->obufp;
13350 return true;
13351 }
13352
13353 static const struct op simd_cmp_op[] =
13354 {
13355 { STRING_COMMA_LEN ("eq") },
13356 { STRING_COMMA_LEN ("lt") },
13357 { STRING_COMMA_LEN ("le") },
13358 { STRING_COMMA_LEN ("unord") },
13359 { STRING_COMMA_LEN ("neq") },
13360 { STRING_COMMA_LEN ("nlt") },
13361 { STRING_COMMA_LEN ("nle") },
13362 { STRING_COMMA_LEN ("ord") }
13363 };
13364
13365 static const struct op vex_cmp_op[] =
13366 {
13367 { STRING_COMMA_LEN ("eq_uq") },
13368 { STRING_COMMA_LEN ("nge") },
13369 { STRING_COMMA_LEN ("ngt") },
13370 { STRING_COMMA_LEN ("false") },
13371 { STRING_COMMA_LEN ("neq_oq") },
13372 { STRING_COMMA_LEN ("ge") },
13373 { STRING_COMMA_LEN ("gt") },
13374 { STRING_COMMA_LEN ("true") },
13375 { STRING_COMMA_LEN ("eq_os") },
13376 { STRING_COMMA_LEN ("lt_oq") },
13377 { STRING_COMMA_LEN ("le_oq") },
13378 { STRING_COMMA_LEN ("unord_s") },
13379 { STRING_COMMA_LEN ("neq_us") },
13380 { STRING_COMMA_LEN ("nlt_uq") },
13381 { STRING_COMMA_LEN ("nle_uq") },
13382 { STRING_COMMA_LEN ("ord_s") },
13383 { STRING_COMMA_LEN ("eq_us") },
13384 { STRING_COMMA_LEN ("nge_uq") },
13385 { STRING_COMMA_LEN ("ngt_uq") },
13386 { STRING_COMMA_LEN ("false_os") },
13387 { STRING_COMMA_LEN ("neq_os") },
13388 { STRING_COMMA_LEN ("ge_oq") },
13389 { STRING_COMMA_LEN ("gt_oq") },
13390 { STRING_COMMA_LEN ("true_us") },
13391 };
13392
13393 static bool
13394 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13395 int sizeflag ATTRIBUTE_UNUSED)
13396 {
13397 unsigned int cmp_type;
13398
13399 if (!fetch_code (ins->info, ins->codep + 1))
13400 return false;
13401 cmp_type = *ins->codep++ & 0xff;
13402 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13403 {
13404 char suffix[3];
13405 char *p = ins->mnemonicendp - 2;
13406 suffix[0] = p[0];
13407 suffix[1] = p[1];
13408 suffix[2] = '\0';
13409 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13410 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13411 }
13412 else if (ins->need_vex
13413 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13414 {
13415 char suffix[3];
13416 char *p = ins->mnemonicendp - 2;
13417 suffix[0] = p[0];
13418 suffix[1] = p[1];
13419 suffix[2] = '\0';
13420 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13421 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13422 ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13423 }
13424 else
13425 {
13426 /* We have a reserved extension byte. Output it directly. */
13427 oappend_immediate (ins, cmp_type);
13428 }
13429 return true;
13430 }
13431
13432 static bool
13433 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13434 {
13435 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13436 if (!ins->intel_syntax)
13437 {
13438 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13439 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13440 if (bytemode == eBX_reg)
13441 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13442 ins->two_source_ops = true;
13443 }
13444 /* Skip mod/rm byte. */
13445 MODRM_CHECK;
13446 ins->codep++;
13447 return true;
13448 }
13449
13450 static bool
13451 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13452 int sizeflag ATTRIBUTE_UNUSED)
13453 {
13454 /* monitor %{e,r,}ax,%ecx,%edx" */
13455 if (!ins->intel_syntax)
13456 {
13457 const char (*names)[8] = (ins->address_mode == mode_64bit
13458 ? att_names64 : att_names32);
13459
13460 if (ins->prefixes & PREFIX_ADDR)
13461 {
13462 /* Remove "addr16/addr32". */
13463 ins->all_prefixes[ins->last_addr_prefix] = 0;
13464 names = (ins->address_mode != mode_32bit
13465 ? att_names32 : att_names16);
13466 ins->used_prefixes |= PREFIX_ADDR;
13467 }
13468 else if (ins->address_mode == mode_16bit)
13469 names = att_names16;
13470 strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13471 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13472 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13473 ins->two_source_ops = true;
13474 }
13475 /* Skip mod/rm byte. */
13476 MODRM_CHECK;
13477 ins->codep++;
13478 return true;
13479 }
13480
13481 static bool
13482 BadOp (instr_info *ins)
13483 {
13484 /* Throw away prefixes and 1st. opcode byte. */
13485 ins->codep = ins->insn_codep + 1;
13486 ins->obufp = stpcpy (ins->obufp, "(bad)");
13487 return true;
13488 }
13489
13490 static bool
13491 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13492 {
13493 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13494 lods and stos. */
13495 if (ins->prefixes & PREFIX_REPZ)
13496 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13497
13498 switch (bytemode)
13499 {
13500 case al_reg:
13501 case eAX_reg:
13502 case indir_dx_reg:
13503 return OP_IMREG (ins, bytemode, sizeflag);
13504 case eDI_reg:
13505 return OP_ESreg (ins, bytemode, sizeflag);
13506 case eSI_reg:
13507 return OP_DSreg (ins, bytemode, sizeflag);
13508 default:
13509 abort ();
13510 break;
13511 }
13512 return true;
13513 }
13514
13515 static bool
13516 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13517 int sizeflag ATTRIBUTE_UNUSED)
13518 {
13519 if (ins->isa64 != amd64)
13520 return true;
13521
13522 ins->obufp = ins->obuf;
13523 BadOp (ins);
13524 ins->mnemonicendp = ins->obufp;
13525 ++ins->codep;
13526 return true;
13527 }
13528
13529 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13530 "bnd". */
13531
13532 static bool
13533 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13534 int sizeflag ATTRIBUTE_UNUSED)
13535 {
13536 if (ins->prefixes & PREFIX_REPNZ)
13537 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13538 return true;
13539 }
13540
13541 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13542 "notrack". */
13543
13544 static bool
13545 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13546 int sizeflag ATTRIBUTE_UNUSED)
13547 {
13548 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13549 we've seen a PREFIX_DS. */
13550 if ((ins->prefixes & PREFIX_DS) != 0
13551 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13552 {
13553 /* NOTRACK prefix is only valid on indirect branch instructions.
13554 NB: DATA prefix is unsupported for Intel64. */
13555 ins->active_seg_prefix = 0;
13556 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13557 }
13558 return true;
13559 }
13560
13561 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13562 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13563 */
13564
13565 static bool
13566 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13567 {
13568 if (ins->modrm.mod != 3
13569 && (ins->prefixes & PREFIX_LOCK) != 0)
13570 {
13571 if (ins->prefixes & PREFIX_REPZ)
13572 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13573 if (ins->prefixes & PREFIX_REPNZ)
13574 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13575 }
13576
13577 return OP_E (ins, bytemode, sizeflag);
13578 }
13579
13580 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13581 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13582 */
13583
13584 static bool
13585 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13586 {
13587 if (ins->modrm.mod != 3)
13588 {
13589 if (ins->prefixes & PREFIX_REPZ)
13590 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13591 if (ins->prefixes & PREFIX_REPNZ)
13592 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13593 }
13594
13595 return OP_E (ins, bytemode, sizeflag);
13596 }
13597
13598 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13599 "xrelease" for memory operand. No check for LOCK prefix. */
13600
13601 static bool
13602 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13603 {
13604 if (ins->modrm.mod != 3
13605 && ins->last_repz_prefix > ins->last_repnz_prefix
13606 && (ins->prefixes & PREFIX_REPZ) != 0)
13607 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13608
13609 return OP_E (ins, bytemode, sizeflag);
13610 }
13611
13612 static bool
13613 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13614 {
13615 USED_REX (REX_W);
13616 if (ins->rex & REX_W)
13617 {
13618 /* Change cmpxchg8b to cmpxchg16b. */
13619 char *p = ins->mnemonicendp - 2;
13620 ins->mnemonicendp = stpcpy (p, "16b");
13621 bytemode = o_mode;
13622 }
13623 else if ((ins->prefixes & PREFIX_LOCK) != 0)
13624 {
13625 if (ins->prefixes & PREFIX_REPZ)
13626 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13627 if (ins->prefixes & PREFIX_REPNZ)
13628 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13629 }
13630
13631 return OP_M (ins, bytemode, sizeflag);
13632 }
13633
13634 static bool
13635 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13636 {
13637 const char (*names)[8] = att_names_xmm;
13638
13639 if (ins->need_vex)
13640 {
13641 switch (ins->vex.length)
13642 {
13643 case 128:
13644 break;
13645 case 256:
13646 names = att_names_ymm;
13647 break;
13648 default:
13649 abort ();
13650 }
13651 }
13652 oappend_register (ins, names[reg]);
13653 return true;
13654 }
13655
13656 static bool
13657 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13658 {
13659 /* Add proper suffix to "fxsave" and "fxrstor". */
13660 USED_REX (REX_W);
13661 if (ins->rex & REX_W)
13662 {
13663 char *p = ins->mnemonicendp;
13664 *p++ = '6';
13665 *p++ = '4';
13666 *p = '\0';
13667 ins->mnemonicendp = p;
13668 }
13669 return OP_M (ins, bytemode, sizeflag);
13670 }
13671
13672 /* Display the destination register operand for instructions with
13673 VEX. */
13674
13675 static bool
13676 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13677 {
13678 int reg, modrm_reg, sib_index = -1;
13679 const char (*names)[8];
13680
13681 if (!ins->need_vex)
13682 abort ();
13683
13684 reg = ins->vex.register_specifier;
13685 ins->vex.register_specifier = 0;
13686 if (ins->address_mode != mode_64bit)
13687 {
13688 if (ins->vex.evex && !ins->vex.v)
13689 {
13690 oappend (ins, "(bad)");
13691 return true;
13692 }
13693
13694 reg &= 7;
13695 }
13696 else if (ins->vex.evex && !ins->vex.v)
13697 reg += 16;
13698
13699 switch (bytemode)
13700 {
13701 case scalar_mode:
13702 oappend_register (ins, att_names_xmm[reg]);
13703 return true;
13704
13705 case vex_vsib_d_w_dq_mode:
13706 case vex_vsib_q_w_dq_mode:
13707 /* This must be the 3rd operand. */
13708 if (ins->obufp != ins->op_out[2])
13709 abort ();
13710 if (ins->vex.length == 128
13711 || (bytemode != vex_vsib_d_w_dq_mode
13712 && !ins->vex.w))
13713 oappend_register (ins, att_names_xmm[reg]);
13714 else
13715 oappend_register (ins, att_names_ymm[reg]);
13716
13717 /* All 3 XMM/YMM registers must be distinct. */
13718 modrm_reg = ins->modrm.reg;
13719 if (ins->rex & REX_R)
13720 modrm_reg += 8;
13721
13722 if (ins->has_sib && ins->modrm.rm == 4)
13723 {
13724 sib_index = ins->sib.index;
13725 if (ins->rex & REX_X)
13726 sib_index += 8;
13727 }
13728
13729 if (reg == modrm_reg || reg == sib_index)
13730 strcpy (ins->obufp, "/(bad)");
13731 if (modrm_reg == sib_index || modrm_reg == reg)
13732 strcat (ins->op_out[0], "/(bad)");
13733 if (sib_index == modrm_reg || sib_index == reg)
13734 strcat (ins->op_out[1], "/(bad)");
13735
13736 return true;
13737
13738 case tmm_mode:
13739 /* All 3 TMM registers must be distinct. */
13740 if (reg >= 8)
13741 oappend (ins, "(bad)");
13742 else
13743 {
13744 /* This must be the 3rd operand. */
13745 if (ins->obufp != ins->op_out[2])
13746 abort ();
13747 oappend_register (ins, att_names_tmm[reg]);
13748 if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13749 strcpy (ins->obufp, "/(bad)");
13750 }
13751
13752 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13753 || ins->modrm.rm == reg)
13754 {
13755 if (ins->modrm.reg <= 8
13756 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13757 strcat (ins->op_out[0], "/(bad)");
13758 if (ins->modrm.rm <= 8
13759 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13760 strcat (ins->op_out[1], "/(bad)");
13761 }
13762
13763 return true;
13764 }
13765
13766 switch (ins->vex.length)
13767 {
13768 case 128:
13769 switch (bytemode)
13770 {
13771 case x_mode:
13772 names = att_names_xmm;
13773 ins->evex_used |= EVEX_len_used;
13774 break;
13775 case dq_mode:
13776 if (ins->rex & REX_W)
13777 names = att_names64;
13778 else
13779 names = att_names32;
13780 break;
13781 case mask_bd_mode:
13782 case mask_mode:
13783 if (reg > 0x7)
13784 {
13785 oappend (ins, "(bad)");
13786 return true;
13787 }
13788 names = att_names_mask;
13789 break;
13790 default:
13791 abort ();
13792 return true;
13793 }
13794 break;
13795 case 256:
13796 switch (bytemode)
13797 {
13798 case x_mode:
13799 names = att_names_ymm;
13800 ins->evex_used |= EVEX_len_used;
13801 break;
13802 case mask_bd_mode:
13803 case mask_mode:
13804 if (reg <= 0x7)
13805 {
13806 names = att_names_mask;
13807 break;
13808 }
13809 /* Fall through. */
13810 default:
13811 /* See PR binutils/20893 for a reproducer. */
13812 oappend (ins, "(bad)");
13813 return true;
13814 }
13815 break;
13816 case 512:
13817 names = att_names_zmm;
13818 ins->evex_used |= EVEX_len_used;
13819 break;
13820 default:
13821 abort ();
13822 break;
13823 }
13824 oappend_register (ins, names[reg]);
13825 return true;
13826 }
13827
13828 static bool
13829 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13830 {
13831 if (ins->modrm.mod == 3)
13832 return OP_VEX (ins, bytemode, sizeflag);
13833 return true;
13834 }
13835
13836 static bool
13837 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13838 {
13839 OP_VEX (ins, bytemode, sizeflag);
13840
13841 if (ins->vex.w)
13842 {
13843 /* Swap 2nd and 3rd operands. */
13844 char *tmp = ins->op_out[2];
13845
13846 ins->op_out[2] = ins->op_out[1];
13847 ins->op_out[1] = tmp;
13848 }
13849 return true;
13850 }
13851
13852 static bool
13853 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13854 {
13855 int reg;
13856 const char (*names)[8] = att_names_xmm;
13857
13858 if (!fetch_code (ins->info, ins->codep + 1))
13859 return false;
13860 reg = *ins->codep++;
13861
13862 if (bytemode != x_mode && bytemode != scalar_mode)
13863 abort ();
13864
13865 reg >>= 4;
13866 if (ins->address_mode != mode_64bit)
13867 reg &= 7;
13868
13869 if (bytemode == x_mode && ins->vex.length == 256)
13870 names = att_names_ymm;
13871
13872 oappend_register (ins, names[reg]);
13873
13874 if (ins->vex.w)
13875 {
13876 /* Swap 3rd and 4th operands. */
13877 char *tmp = ins->op_out[3];
13878
13879 ins->op_out[3] = ins->op_out[2];
13880 ins->op_out[2] = tmp;
13881 }
13882 return true;
13883 }
13884
13885 static bool
13886 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13887 int sizeflag ATTRIBUTE_UNUSED)
13888 {
13889 oappend_immediate (ins, ins->codep[-1] & 0xf);
13890 return true;
13891 }
13892
13893 static bool
13894 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13895 int sizeflag ATTRIBUTE_UNUSED)
13896 {
13897 unsigned int cmp_type;
13898
13899 if (!ins->vex.evex)
13900 abort ();
13901
13902 if (!fetch_code (ins->info, ins->codep + 1))
13903 return false;
13904 cmp_type = *ins->codep++ & 0xff;
13905 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13906 If it's the case, print suffix, otherwise - print the immediate. */
13907 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13908 && cmp_type != 3
13909 && cmp_type != 7)
13910 {
13911 char suffix[3];
13912 char *p = ins->mnemonicendp - 2;
13913
13914 /* vpcmp* can have both one- and two-lettered suffix. */
13915 if (p[0] == 'p')
13916 {
13917 p++;
13918 suffix[0] = p[0];
13919 suffix[1] = '\0';
13920 }
13921 else
13922 {
13923 suffix[0] = p[0];
13924 suffix[1] = p[1];
13925 suffix[2] = '\0';
13926 }
13927
13928 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13929 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13930 }
13931 else
13932 {
13933 /* We have a reserved extension byte. Output it directly. */
13934 oappend_immediate (ins, cmp_type);
13935 }
13936 return true;
13937 }
13938
13939 static const struct op xop_cmp_op[] =
13940 {
13941 { STRING_COMMA_LEN ("lt") },
13942 { STRING_COMMA_LEN ("le") },
13943 { STRING_COMMA_LEN ("gt") },
13944 { STRING_COMMA_LEN ("ge") },
13945 { STRING_COMMA_LEN ("eq") },
13946 { STRING_COMMA_LEN ("neq") },
13947 { STRING_COMMA_LEN ("false") },
13948 { STRING_COMMA_LEN ("true") }
13949 };
13950
13951 static bool
13952 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13953 int sizeflag ATTRIBUTE_UNUSED)
13954 {
13955 unsigned int cmp_type;
13956
13957 if (!fetch_code (ins->info, ins->codep + 1))
13958 return false;
13959 cmp_type = *ins->codep++ & 0xff;
13960 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13961 {
13962 char suffix[3];
13963 char *p = ins->mnemonicendp - 2;
13964
13965 /* vpcom* can have both one- and two-lettered suffix. */
13966 if (p[0] == 'm')
13967 {
13968 p++;
13969 suffix[0] = p[0];
13970 suffix[1] = '\0';
13971 }
13972 else
13973 {
13974 suffix[0] = p[0];
13975 suffix[1] = p[1];
13976 suffix[2] = '\0';
13977 }
13978
13979 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13980 ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13981 }
13982 else
13983 {
13984 /* We have a reserved extension byte. Output it directly. */
13985 oappend_immediate (ins, cmp_type);
13986 }
13987 return true;
13988 }
13989
13990 static const struct op pclmul_op[] =
13991 {
13992 { STRING_COMMA_LEN ("lql") },
13993 { STRING_COMMA_LEN ("hql") },
13994 { STRING_COMMA_LEN ("lqh") },
13995 { STRING_COMMA_LEN ("hqh") }
13996 };
13997
13998 static bool
13999 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
14000 int sizeflag ATTRIBUTE_UNUSED)
14001 {
14002 unsigned int pclmul_type;
14003
14004 if (!fetch_code (ins->info, ins->codep + 1))
14005 return false;
14006 pclmul_type = *ins->codep++ & 0xff;
14007 switch (pclmul_type)
14008 {
14009 case 0x10:
14010 pclmul_type = 2;
14011 break;
14012 case 0x11:
14013 pclmul_type = 3;
14014 break;
14015 default:
14016 break;
14017 }
14018 if (pclmul_type < ARRAY_SIZE (pclmul_op))
14019 {
14020 char suffix[4];
14021 char *p = ins->mnemonicendp - 3;
14022 suffix[0] = p[0];
14023 suffix[1] = p[1];
14024 suffix[2] = p[2];
14025 suffix[3] = '\0';
14026 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14027 ins->mnemonicendp += pclmul_op[pclmul_type].len;
14028 }
14029 else
14030 {
14031 /* We have a reserved extension byte. Output it directly. */
14032 oappend_immediate (ins, pclmul_type);
14033 }
14034 return true;
14035 }
14036
14037 static bool
14038 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
14039 {
14040 /* Add proper suffix to "movsxd". */
14041 char *p = ins->mnemonicendp;
14042
14043 switch (bytemode)
14044 {
14045 case movsxd_mode:
14046 if (!ins->intel_syntax)
14047 {
14048 USED_REX (REX_W);
14049 if (ins->rex & REX_W)
14050 {
14051 *p++ = 'l';
14052 *p++ = 'q';
14053 break;
14054 }
14055 }
14056
14057 *p++ = 'x';
14058 *p++ = 'd';
14059 break;
14060 default:
14061 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
14062 break;
14063 }
14064
14065 ins->mnemonicendp = p;
14066 *p = '\0';
14067 return OP_E (ins, bytemode, sizeflag);
14068 }
14069
14070 static bool
14071 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
14072 {
14073 unsigned int reg = ins->vex.register_specifier;
14074 unsigned int modrm_reg = ins->modrm.reg;
14075 unsigned int modrm_rm = ins->modrm.rm;
14076
14077 /* Calc destination register number. */
14078 if (ins->rex & REX_R)
14079 modrm_reg += 8;
14080 if (!ins->vex.r)
14081 modrm_reg += 16;
14082
14083 /* Calc src1 register number. */
14084 if (ins->address_mode != mode_64bit)
14085 reg &= 7;
14086 else if (ins->vex.evex && !ins->vex.v)
14087 reg += 16;
14088
14089 /* Calc src2 register number. */
14090 if (ins->modrm.mod == 3)
14091 {
14092 if (ins->rex & REX_B)
14093 modrm_rm += 8;
14094 if (ins->rex & REX_X)
14095 modrm_rm += 16;
14096 }
14097
14098 /* Destination and source registers must be distinct, output bad if
14099 dest == src1 or dest == src2. */
14100 if (modrm_reg == reg
14101 || (ins->modrm.mod == 3
14102 && modrm_reg == modrm_rm))
14103 {
14104 oappend (ins, "(bad)");
14105 return true;
14106 }
14107 return OP_XMM (ins, bytemode, sizeflag);
14108 }
14109
14110 static bool
14111 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14112 {
14113 if (ins->modrm.mod != 3 || !ins->vex.b)
14114 return true;
14115
14116 switch (bytemode)
14117 {
14118 case evex_rounding_64_mode:
14119 if (ins->address_mode != mode_64bit || !ins->vex.w)
14120 return true;
14121 /* Fall through. */
14122 case evex_rounding_mode:
14123 ins->evex_used |= EVEX_b_used;
14124 oappend (ins, names_rounding[ins->vex.ll]);
14125 break;
14126 case evex_sae_mode:
14127 ins->evex_used |= EVEX_b_used;
14128 oappend (ins, "{");
14129 break;
14130 default:
14131 abort ();
14132 }
14133 oappend (ins, "sae}");
14134 return true;
14135 }
14136
14137 static bool
14138 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
14139 {
14140 if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
14141 {
14142 if (ins->intel_syntax)
14143 {
14144 ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
14145 }
14146 else
14147 {
14148 USED_REX (REX_W);
14149 if (ins->rex & REX_W)
14150 ins->mnemonicendp = stpcpy (ins->obuf, "nopq ");
14151 else
14152 {
14153 if (sizeflag & DFLAG)
14154 ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
14155 else
14156 ins->mnemonicendp = stpcpy (ins->obuf, "nopw ");
14157 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14158 }
14159 }
14160 bytemode = v_mode;
14161 }
14162
14163 return OP_M (ins, bytemode, sizeflag);
14164 }