opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void HLE_Fixup1 (int, int);
 112 static void HLE_Fixup2 (int, int);
 113 static void HLE_Fixup3 (int, int);
 114 static void CMPXCHG8B_Fixup (int, int);
 115 static void XMM_Fixup (int, int);
 116 static void CRC32_Fixup (int, int);
 117 static void FXSAVE_Fixup (int, int);
 118 static void OP_LWPCB_E (int, int);
 119 static void OP_LWP_E (int, int);
 120 static void OP_Vex_2src_1 (int, int);
 121 static void OP_Vex_2src_2 (int, int);
 122
 123 static void MOVBE_Fixup (int, int);
 124
 125 struct dis_private {
 126   /* Points to first byte not fetched.  */
 127   bfd_byte *max_fetched;
 128   bfd_byte the_buffer[MAX_MNEM_SIZE];
 129   bfd_vma insn_start;
 130   int orig_sizeflag;
 131   jmp_buf bailout;
 132 };
 133
 134 enum address_mode
 135 {
 136   mode_16bit,
 137   mode_32bit,
 138   mode_64bit
 139 };
 140
 141 enum address_mode address_mode;
 142
 143 /* Flags for the prefixes for the current instruction.  See below.  */
 144 static int prefixes;
 145
 146 /* REX prefix the current instruction.  See below.  */
 147 static int rex;
 148 /* Bits of REX we've already used.  */
 149 static int rex_used;
 150 /* REX bits in original REX prefix ignored.  */
 151 static int rex_ignored;
 152 /* Mark parts used in the REX prefix.  When we are testing for
 153    empty prefix (for 8bit register REX extension), just mask it
 154    out.  Otherwise test for REX bit is excuse for existence of REX
 155    only in case value is nonzero.  */
 156 #define USED_REX(value)                                 \
 157   {                                                     \
 158     if (value)                                          \
 159       {                                                 \
 160         if ((rex & value))                              \
 161           rex_used |= (value) | REX_OPCODE;             \
 162       }                                                 \
 163     else                                                \
 164       rex_used |= REX_OPCODE;                           \
 165   }
 166
 167 /* Flags for prefixes which we somehow handled when printing the
 168    current instruction.  */
 169 static int used_prefixes;
 170
 171 /* Flags stored in PREFIXES.  */
 172 #define PREFIX_REPZ 1
 173 #define PREFIX_REPNZ 2
 174 #define PREFIX_LOCK 4
 175 #define PREFIX_CS 8
 176 #define PREFIX_SS 0x10
 177 #define PREFIX_DS 0x20
 178 #define PREFIX_ES 0x40
 179 #define PREFIX_FS 0x80
 180 #define PREFIX_GS 0x100
 181 #define PREFIX_DATA 0x200
 182 #define PREFIX_ADDR 0x400
 183 #define PREFIX_FWAIT 0x800
 184
 185 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 186    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 187    on error.  */
 188 #define FETCH_DATA(info, addr) \
 189   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 190    ? 1 : fetch_data ((info), (addr)))
 191
 192 static int
 193 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 194 {
 195   int status;
 196   struct dis_private *priv = (struct dis_private *) info->private_data;
 197   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 198
 199   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 200     status = (*info->read_memory_func) (start,
 201                                         priv->max_fetched,
 202                                         addr - priv->max_fetched,
 203                                         info);
 204   else
 205     status = -1;
 206   if (status != 0)
 207     {
 208       /* If we did manage to read at least one byte, then
 209          print_insn_i386 will do something sensible.  Otherwise, print
 210          an error.  We do that here because this is where we know
 211          STATUS.  */
 212       if (priv->max_fetched == priv->the_buffer)
 213         (*info->memory_error_func) (status, start, info);
 214       longjmp (priv->bailout, 1);
 215     }
 216   else
 217     priv->max_fetched = addr;
 218   return 1;
 219 }
 220
 221 #define XX { NULL, 0 }
 222 #define Bad_Opcode NULL, { { NULL, 0 } }
 223
 224 #define Eb { OP_E, b_mode }
 225 #define EbS { OP_E, b_swap_mode }
 226 #define Ev { OP_E, v_mode }
 227 #define EvS { OP_E, v_swap_mode }
 228 #define Ed { OP_E, d_mode }
 229 #define Edq { OP_E, dq_mode }
 230 #define Edqw { OP_E, dqw_mode }
 231 #define Edqb { OP_E, dqb_mode }
 232 #define Edqd { OP_E, dqd_mode }
 233 #define Eq { OP_E, q_mode }
 234 #define indirEv { OP_indirE, stack_v_mode }
 235 #define indirEp { OP_indirE, f_mode }
 236 #define stackEv { OP_E, stack_v_mode }
 237 #define Em { OP_E, m_mode }
 238 #define Ew { OP_E, w_mode }
 239 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 240 #define Ma { OP_M, a_mode }
 241 #define Mb { OP_M, b_mode }
 242 #define Md { OP_M, d_mode }
 243 #define Mo { OP_M, o_mode }
 244 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 245 #define Mq { OP_M, q_mode }
 246 #define Mx { OP_M, x_mode }
 247 #define Mxmm { OP_M, xmm_mode }
 248 #define Gb { OP_G, b_mode }
 249 #define Gv { OP_G, v_mode }
 250 #define Gd { OP_G, d_mode }
 251 #define Gdq { OP_G, dq_mode }
 252 #define Gm { OP_G, m_mode }
 253 #define Gw { OP_G, w_mode }
 254 #define Rd { OP_R, d_mode }
 255 #define Rm { OP_R, m_mode }
 256 #define Ib { OP_I, b_mode }
 257 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 258 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 259 #define Iv { OP_I, v_mode }
 260 #define sIv { OP_sI, v_mode }
 261 #define Iq { OP_I, q_mode }
 262 #define Iv64 { OP_I64, v_mode }
 263 #define Iw { OP_I, w_mode }
 264 #define I1 { OP_I, const_1_mode }
 265 #define Jb { OP_J, b_mode }
 266 #define Jv { OP_J, v_mode }
 267 #define Cm { OP_C, m_mode }
 268 #define Dm { OP_D, m_mode }
 269 #define Td { OP_T, d_mode }
 270 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 271
 272 #define RMeAX { OP_REG, eAX_reg }
 273 #define RMeBX { OP_REG, eBX_reg }
 274 #define RMeCX { OP_REG, eCX_reg }
 275 #define RMeDX { OP_REG, eDX_reg }
 276 #define RMeSP { OP_REG, eSP_reg }
 277 #define RMeBP { OP_REG, eBP_reg }
 278 #define RMeSI { OP_REG, eSI_reg }
 279 #define RMeDI { OP_REG, eDI_reg }
 280 #define RMrAX { OP_REG, rAX_reg }
 281 #define RMrBX { OP_REG, rBX_reg }
 282 #define RMrCX { OP_REG, rCX_reg }
 283 #define RMrDX { OP_REG, rDX_reg }
 284 #define RMrSP { OP_REG, rSP_reg }
 285 #define RMrBP { OP_REG, rBP_reg }
 286 #define RMrSI { OP_REG, rSI_reg }
 287 #define RMrDI { OP_REG, rDI_reg }
 288 #define RMAL { OP_REG, al_reg }
 289 #define RMCL { OP_REG, cl_reg }
 290 #define RMDL { OP_REG, dl_reg }
 291 #define RMBL { OP_REG, bl_reg }
 292 #define RMAH { OP_REG, ah_reg }
 293 #define RMCH { OP_REG, ch_reg }
 294 #define RMDH { OP_REG, dh_reg }
 295 #define RMBH { OP_REG, bh_reg }
 296 #define RMAX { OP_REG, ax_reg }
 297 #define RMDX { OP_REG, dx_reg }
 298
 299 #define eAX { OP_IMREG, eAX_reg }
 300 #define eBX { OP_IMREG, eBX_reg }
 301 #define eCX { OP_IMREG, eCX_reg }
 302 #define eDX { OP_IMREG, eDX_reg }
 303 #define eSP { OP_IMREG, eSP_reg }
 304 #define eBP { OP_IMREG, eBP_reg }
 305 #define eSI { OP_IMREG, eSI_reg }
 306 #define eDI { OP_IMREG, eDI_reg }
 307 #define AL { OP_IMREG, al_reg }
 308 #define CL { OP_IMREG, cl_reg }
 309 #define DL { OP_IMREG, dl_reg }
 310 #define BL { OP_IMREG, bl_reg }
 311 #define AH { OP_IMREG, ah_reg }
 312 #define CH { OP_IMREG, ch_reg }
 313 #define DH { OP_IMREG, dh_reg }
 314 #define BH { OP_IMREG, bh_reg }
 315 #define AX { OP_IMREG, ax_reg }
 316 #define DX { OP_IMREG, dx_reg }
 317 #define zAX { OP_IMREG, z_mode_ax_reg }
 318 #define indirDX { OP_IMREG, indir_dx_reg }
 319
 320 #define Sw { OP_SEG, w_mode }
 321 #define Sv { OP_SEG, v_mode }
 322 #define Ap { OP_DIR, 0 }
 323 #define Ob { OP_OFF64, b_mode }
 324 #define Ov { OP_OFF64, v_mode }
 325 #define Xb { OP_DSreg, eSI_reg }
 326 #define Xv { OP_DSreg, eSI_reg }
 327 #define Xz { OP_DSreg, eSI_reg }
 328 #define Yb { OP_ESreg, eDI_reg }
 329 #define Yv { OP_ESreg, eDI_reg }
 330 #define DSBX { OP_DSreg, eBX_reg }
 331
 332 #define es { OP_REG, es_reg }
 333 #define ss { OP_REG, ss_reg }
 334 #define cs { OP_REG, cs_reg }
 335 #define ds { OP_REG, ds_reg }
 336 #define fs { OP_REG, fs_reg }
 337 #define gs { OP_REG, gs_reg }
 338
 339 #define MX { OP_MMX, 0 }
 340 #define XM { OP_XMM, 0 }
 341 #define XMScalar { OP_XMM, scalar_mode }
 342 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 343 #define XMM { OP_XMM, xmm_mode }
 344 #define EM { OP_EM, v_mode }
 345 #define EMS { OP_EM, v_swap_mode }
 346 #define EMd { OP_EM, d_mode }
 347 #define EMx { OP_EM, x_mode }
 348 #define EXw { OP_EX, w_mode }
 349 #define EXd { OP_EX, d_mode }
 350 #define EXdScalar { OP_EX, d_scalar_mode }
 351 #define EXdS { OP_EX, d_swap_mode }
 352 #define EXq { OP_EX, q_mode }
 353 #define EXqScalar { OP_EX, q_scalar_mode }
 354 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 355 #define EXqS { OP_EX, q_swap_mode }
 356 #define EXx { OP_EX, x_mode }
 357 #define EXxS { OP_EX, x_swap_mode }
 358 #define EXxmm { OP_EX, xmm_mode }
 359 #define EXxmmq { OP_EX, xmmq_mode }
 360 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 361 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 362 #define EXxmm_md { OP_EX, xmm_md_mode }
 363 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 364 #define EXxmmdw { OP_EX, xmmdw_mode }
 365 #define EXxmmqd { OP_EX, xmmqd_mode }
 366 #define EXymmq { OP_EX, ymmq_mode }
 367 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 368 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 369 #define MS { OP_MS, v_mode }
 370 #define XS { OP_XS, v_mode }
 371 #define EMCq { OP_EMC, q_mode }
 372 #define MXC { OP_MXC, 0 }
 373 #define OPSUF { OP_3DNowSuffix, 0 }
 374 #define CMP { CMP_Fixup, 0 }
 375 #define XMM0 { XMM_Fixup, 0 }
 376 #define FXSAVE { FXSAVE_Fixup, 0 }
 377 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 378 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 379
 380 #define Vex { OP_VEX, vex_mode }
 381 #define VexScalar { OP_VEX, vex_scalar_mode }
 382 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 383 #define Vex128 { OP_VEX, vex128_mode }
 384 #define Vex256 { OP_VEX, vex256_mode }
 385 #define VexGdq { OP_VEX, dq_mode }
 386 #define VexI4 { VEXI4_Fixup, 0}
 387 #define EXdVex { OP_EX_Vex, d_mode }
 388 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 389 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 390 #define EXqVex { OP_EX_Vex, q_mode }
 391 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 392 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 393 #define EXVexW { OP_EX_VexW, x_mode }
 394 #define EXdVexW { OP_EX_VexW, d_mode }
 395 #define EXqVexW { OP_EX_VexW, q_mode }
 396 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 397 #define XMVex { OP_XMM_Vex, 0 }
 398 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 399 #define XMVexW { OP_XMM_VexW, 0 }
 400 #define XMVexI4 { OP_REG_VexI4, x_mode }
 401 #define PCLMUL { PCLMUL_Fixup, 0 }
 402 #define VZERO { VZERO_Fixup, 0 }
 403 #define VCMP { VCMP_Fixup, 0 }
 404
 405 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 406 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 407
 408 /* Used handle "rep" prefix for string instructions.  */
 409 #define Xbr { REP_Fixup, eSI_reg }
 410 #define Xvr { REP_Fixup, eSI_reg }
 411 #define Ybr { REP_Fixup, eDI_reg }
 412 #define Yvr { REP_Fixup, eDI_reg }
 413 #define Yzr { REP_Fixup, eDI_reg }
 414 #define indirDXr { REP_Fixup, indir_dx_reg }
 415 #define ALr { REP_Fixup, al_reg }
 416 #define eAXr { REP_Fixup, eAX_reg }
 417
 418 /* Used handle HLE prefix for lockable instructions.  */
 419 #define Ebh1 { HLE_Fixup1, b_mode }
 420 #define Evh1 { HLE_Fixup1, v_mode }
 421 #define Ebh2 { HLE_Fixup2, b_mode }
 422 #define Evh2 { HLE_Fixup2, v_mode }
 423 #define Ebh3 { HLE_Fixup3, b_mode }
 424 #define Evh3 { HLE_Fixup3, v_mode }
 425
 426 #define cond_jump_flag { NULL, cond_jump_mode }
 427 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 428
 429 /* bits in sizeflag */
 430 #define SUFFIX_ALWAYS 4
 431 #define AFLAG 2
 432 #define DFLAG 1
 433
 434 enum
 435 {
 436   /* byte operand */
 437   b_mode = 1,
 438   /* byte operand with operand swapped */
 439   b_swap_mode,
 440   /* byte operand, sign extend like 'T' suffix */
 441   b_T_mode,
 442   /* operand size depends on prefixes */
 443   v_mode,
 444   /* operand size depends on prefixes with operand swapped */
 445   v_swap_mode,
 446   /* word operand */
 447   w_mode,
 448   /* double word operand  */
 449   d_mode,
 450   /* double word operand with operand swapped */
 451   d_swap_mode,
 452   /* quad word operand */
 453   q_mode,
 454   /* quad word operand with operand swapped */
 455   q_swap_mode,
 456   /* ten-byte operand */
 457   t_mode,
 458   /* 16-byte XMM or 32-byte YMM operand */
 459   x_mode,
 460   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 461   x_swap_mode,
 462   /* 16-byte XMM operand */
 463   xmm_mode,
 464   /* 16-byte XMM or quad word operand */
 465   xmmq_mode,
 466   /* XMM register or byte memory operand */
 467   xmm_mb_mode,
 468   /* XMM register or word memory operand */
 469   xmm_mw_mode,
 470   /* XMM register or double word memory operand */
 471   xmm_md_mode,
 472   /* XMM register or quad word memory operand */
 473   xmm_mq_mode,
 474   /* 16-byte XMM, word or double word operand  */
 475   xmmdw_mode,
 476   /* 16-byte XMM, double word or quad word operand */
 477   xmmqd_mode,
 478   /* 32-byte YMM or quad word operand */
 479   ymmq_mode,
 480   /* 32-byte YMM or 16-byte word operand */
 481   ymmxmm_mode,
 482   /* d_mode in 32bit, q_mode in 64bit mode.  */
 483   m_mode,
 484   /* pair of v_mode operands */
 485   a_mode,
 486   cond_jump_mode,
 487   loop_jcxz_mode,
 488   /* operand size depends on REX prefixes.  */
 489   dq_mode,
 490   /* registers like dq_mode, memory like w_mode.  */
 491   dqw_mode,
 492   /* 4- or 6-byte pointer operand */
 493   f_mode,
 494   const_1_mode,
 495   /* v_mode for stack-related opcodes.  */
 496   stack_v_mode,
 497   /* non-quad operand size depends on prefixes */
 498   z_mode,
 499   /* 16-byte operand */
 500   o_mode,
 501   /* registers like dq_mode, memory like b_mode.  */
 502   dqb_mode,
 503   /* registers like dq_mode, memory like d_mode.  */
 504   dqd_mode,
 505   /* normal vex mode */
 506   vex_mode,
 507   /* 128bit vex mode */
 508   vex128_mode,
 509   /* 256bit vex mode */
 510   vex256_mode,
 511   /* operand size depends on the VEX.W bit.  */
 512   vex_w_dq_mode,
 513
 514   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 515   vex_vsib_d_w_dq_mode,
 516   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 517   vex_vsib_q_w_dq_mode,
 518
 519   /* scalar, ignore vector length.  */
 520   scalar_mode,
 521   /* like d_mode, ignore vector length.  */
 522   d_scalar_mode,
 523   /* like d_swap_mode, ignore vector length.  */
 524   d_scalar_swap_mode,
 525   /* like q_mode, ignore vector length.  */
 526   q_scalar_mode,
 527   /* like q_swap_mode, ignore vector length.  */
 528   q_scalar_swap_mode,
 529   /* like vex_mode, ignore vector length.  */
 530   vex_scalar_mode,
 531   /* like vex_w_dq_mode, ignore vector length.  */
 532   vex_scalar_w_dq_mode,
 533
 534   es_reg,
 535   cs_reg,
 536   ss_reg,
 537   ds_reg,
 538   fs_reg,
 539   gs_reg,
 540
 541   eAX_reg,
 542   eCX_reg,
 543   eDX_reg,
 544   eBX_reg,
 545   eSP_reg,
 546   eBP_reg,
 547   eSI_reg,
 548   eDI_reg,
 549
 550   al_reg,
 551   cl_reg,
 552   dl_reg,
 553   bl_reg,
 554   ah_reg,
 555   ch_reg,
 556   dh_reg,
 557   bh_reg,
 558
 559   ax_reg,
 560   cx_reg,
 561   dx_reg,
 562   bx_reg,
 563   sp_reg,
 564   bp_reg,
 565   si_reg,
 566   di_reg,
 567
 568   rAX_reg,
 569   rCX_reg,
 570   rDX_reg,
 571   rBX_reg,
 572   rSP_reg,
 573   rBP_reg,
 574   rSI_reg,
 575   rDI_reg,
 576
 577   z_mode_ax_reg,
 578   indir_dx_reg
 579 };
 580
 581 enum
 582 {
 583   FLOATCODE = 1,
 584   USE_REG_TABLE,
 585   USE_MOD_TABLE,
 586   USE_RM_TABLE,
 587   USE_PREFIX_TABLE,
 588   USE_X86_64_TABLE,
 589   USE_3BYTE_TABLE,
 590   USE_XOP_8F_TABLE,
 591   USE_VEX_C4_TABLE,
 592   USE_VEX_C5_TABLE,
 593   USE_VEX_LEN_TABLE,
 594   USE_VEX_W_TABLE
 595 };
 596
 597 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 598
 599 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 600 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 601 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 602 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 603 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 604 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 605 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 606 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 607 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 608 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 609 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 610 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 611
 612 enum
 613 {
 614   REG_80 = 0,
 615   REG_81,
 616   REG_82,
 617   REG_8F,
 618   REG_C0,
 619   REG_C1,
 620   REG_C6,
 621   REG_C7,
 622   REG_D0,
 623   REG_D1,
 624   REG_D2,
 625   REG_D3,
 626   REG_F6,
 627   REG_F7,
 628   REG_FE,
 629   REG_FF,
 630   REG_0F00,
 631   REG_0F01,
 632   REG_0F0D,
 633   REG_0F18,
 634   REG_0F71,
 635   REG_0F72,
 636   REG_0F73,
 637   REG_0FA6,
 638   REG_0FA7,
 639   REG_0FAE,
 640   REG_0FBA,
 641   REG_0FC7,
 642   REG_VEX_0F71,
 643   REG_VEX_0F72,
 644   REG_VEX_0F73,
 645   REG_VEX_0FAE,
 646   REG_VEX_0F38F3,
 647   REG_XOP_LWPCB,
 648   REG_XOP_LWP,
 649   REG_XOP_TBM_01,
 650   REG_XOP_TBM_02
 651 };
 652
 653 enum
 654 {
 655   MOD_8D = 0,
 656   MOD_C6_REG_7,
 657   MOD_C7_REG_7,
 658   MOD_0F01_REG_0,
 659   MOD_0F01_REG_1,
 660   MOD_0F01_REG_2,
 661   MOD_0F01_REG_3,
 662   MOD_0F01_REG_7,
 663   MOD_0F12_PREFIX_0,
 664   MOD_0F13,
 665   MOD_0F16_PREFIX_0,
 666   MOD_0F17,
 667   MOD_0F18_REG_0,
 668   MOD_0F18_REG_1,
 669   MOD_0F18_REG_2,
 670   MOD_0F18_REG_3,
 671   MOD_0F20,
 672   MOD_0F21,
 673   MOD_0F22,
 674   MOD_0F23,
 675   MOD_0F24,
 676   MOD_0F26,
 677   MOD_0F2B_PREFIX_0,
 678   MOD_0F2B_PREFIX_1,
 679   MOD_0F2B_PREFIX_2,
 680   MOD_0F2B_PREFIX_3,
 681   MOD_0F51,
 682   MOD_0F71_REG_2,
 683   MOD_0F71_REG_4,
 684   MOD_0F71_REG_6,
 685   MOD_0F72_REG_2,
 686   MOD_0F72_REG_4,
 687   MOD_0F72_REG_6,
 688   MOD_0F73_REG_2,
 689   MOD_0F73_REG_3,
 690   MOD_0F73_REG_6,
 691   MOD_0F73_REG_7,
 692   MOD_0FAE_REG_0,
 693   MOD_0FAE_REG_1,
 694   MOD_0FAE_REG_2,
 695   MOD_0FAE_REG_3,
 696   MOD_0FAE_REG_4,
 697   MOD_0FAE_REG_5,
 698   MOD_0FAE_REG_6,
 699   MOD_0FAE_REG_7,
 700   MOD_0FB2,
 701   MOD_0FB4,
 702   MOD_0FB5,
 703   MOD_0FC7_REG_6,
 704   MOD_0FC7_REG_7,
 705   MOD_0FD7,
 706   MOD_0FE7_PREFIX_2,
 707   MOD_0FF0_PREFIX_3,
 708   MOD_0F382A_PREFIX_2,
 709   MOD_62_32BIT,
 710   MOD_C4_32BIT,
 711   MOD_C5_32BIT,
 712   MOD_VEX_0F12_PREFIX_0,
 713   MOD_VEX_0F13,
 714   MOD_VEX_0F16_PREFIX_0,
 715   MOD_VEX_0F17,
 716   MOD_VEX_0F2B,
 717   MOD_VEX_0F50,
 718   MOD_VEX_0F71_REG_2,
 719   MOD_VEX_0F71_REG_4,
 720   MOD_VEX_0F71_REG_6,
 721   MOD_VEX_0F72_REG_2,
 722   MOD_VEX_0F72_REG_4,
 723   MOD_VEX_0F72_REG_6,
 724   MOD_VEX_0F73_REG_2,
 725   MOD_VEX_0F73_REG_3,
 726   MOD_VEX_0F73_REG_6,
 727   MOD_VEX_0F73_REG_7,
 728   MOD_VEX_0FAE_REG_2,
 729   MOD_VEX_0FAE_REG_3,
 730   MOD_VEX_0FD7_PREFIX_2,
 731   MOD_VEX_0FE7_PREFIX_2,
 732   MOD_VEX_0FF0_PREFIX_3,
 733   MOD_VEX_0F381A_PREFIX_2,
 734   MOD_VEX_0F382A_PREFIX_2,
 735   MOD_VEX_0F382C_PREFIX_2,
 736   MOD_VEX_0F382D_PREFIX_2,
 737   MOD_VEX_0F382E_PREFIX_2,
 738   MOD_VEX_0F382F_PREFIX_2,
 739   MOD_VEX_0F385A_PREFIX_2,
 740   MOD_VEX_0F388C_PREFIX_2,
 741   MOD_VEX_0F388E_PREFIX_2,
 742 };
 743
 744 enum
 745 {
 746   RM_C6_REG_7 = 0,
 747   RM_C7_REG_7,
 748   RM_0F01_REG_0,
 749   RM_0F01_REG_1,
 750   RM_0F01_REG_2,
 751   RM_0F01_REG_3,
 752   RM_0F01_REG_7,
 753   RM_0FAE_REG_5,
 754   RM_0FAE_REG_6,
 755   RM_0FAE_REG_7
 756 };
 757
 758 enum
 759 {
 760   PREFIX_90 = 0,
 761   PREFIX_0F10,
 762   PREFIX_0F11,
 763   PREFIX_0F12,
 764   PREFIX_0F16,
 765   PREFIX_0F2A,
 766   PREFIX_0F2B,
 767   PREFIX_0F2C,
 768   PREFIX_0F2D,
 769   PREFIX_0F2E,
 770   PREFIX_0F2F,
 771   PREFIX_0F51,
 772   PREFIX_0F52,
 773   PREFIX_0F53,
 774   PREFIX_0F58,
 775   PREFIX_0F59,
 776   PREFIX_0F5A,
 777   PREFIX_0F5B,
 778   PREFIX_0F5C,
 779   PREFIX_0F5D,
 780   PREFIX_0F5E,
 781   PREFIX_0F5F,
 782   PREFIX_0F60,
 783   PREFIX_0F61,
 784   PREFIX_0F62,
 785   PREFIX_0F6C,
 786   PREFIX_0F6D,
 787   PREFIX_0F6F,
 788   PREFIX_0F70,
 789   PREFIX_0F73_REG_3,
 790   PREFIX_0F73_REG_7,
 791   PREFIX_0F78,
 792   PREFIX_0F79,
 793   PREFIX_0F7C,
 794   PREFIX_0F7D,
 795   PREFIX_0F7E,
 796   PREFIX_0F7F,
 797   PREFIX_0FAE_REG_0,
 798   PREFIX_0FAE_REG_1,
 799   PREFIX_0FAE_REG_2,
 800   PREFIX_0FAE_REG_3,
 801   PREFIX_0FB8,
 802   PREFIX_0FBC,
 803   PREFIX_0FBD,
 804   PREFIX_0FC2,
 805   PREFIX_0FC3,
 806   PREFIX_0FC7_REG_6,
 807   PREFIX_0FD0,
 808   PREFIX_0FD6,
 809   PREFIX_0FE6,
 810   PREFIX_0FE7,
 811   PREFIX_0FF0,
 812   PREFIX_0FF7,
 813   PREFIX_0F3810,
 814   PREFIX_0F3814,
 815   PREFIX_0F3815,
 816   PREFIX_0F3817,
 817   PREFIX_0F3820,
 818   PREFIX_0F3821,
 819   PREFIX_0F3822,
 820   PREFIX_0F3823,
 821   PREFIX_0F3824,
 822   PREFIX_0F3825,
 823   PREFIX_0F3828,
 824   PREFIX_0F3829,
 825   PREFIX_0F382A,
 826   PREFIX_0F382B,
 827   PREFIX_0F3830,
 828   PREFIX_0F3831,
 829   PREFIX_0F3832,
 830   PREFIX_0F3833,
 831   PREFIX_0F3834,
 832   PREFIX_0F3835,
 833   PREFIX_0F3837,
 834   PREFIX_0F3838,
 835   PREFIX_0F3839,
 836   PREFIX_0F383A,
 837   PREFIX_0F383B,
 838   PREFIX_0F383C,
 839   PREFIX_0F383D,
 840   PREFIX_0F383E,
 841   PREFIX_0F383F,
 842   PREFIX_0F3840,
 843   PREFIX_0F3841,
 844   PREFIX_0F3880,
 845   PREFIX_0F3881,
 846   PREFIX_0F3882,
 847   PREFIX_0F38DB,
 848   PREFIX_0F38DC,
 849   PREFIX_0F38DD,
 850   PREFIX_0F38DE,
 851   PREFIX_0F38DF,
 852   PREFIX_0F38F0,
 853   PREFIX_0F38F1,
 854   PREFIX_0F38F6,
 855   PREFIX_0F3A08,
 856   PREFIX_0F3A09,
 857   PREFIX_0F3A0A,
 858   PREFIX_0F3A0B,
 859   PREFIX_0F3A0C,
 860   PREFIX_0F3A0D,
 861   PREFIX_0F3A0E,
 862   PREFIX_0F3A14,
 863   PREFIX_0F3A15,
 864   PREFIX_0F3A16,
 865   PREFIX_0F3A17,
 866   PREFIX_0F3A20,
 867   PREFIX_0F3A21,
 868   PREFIX_0F3A22,
 869   PREFIX_0F3A40,
 870   PREFIX_0F3A41,
 871   PREFIX_0F3A42,
 872   PREFIX_0F3A44,
 873   PREFIX_0F3A60,
 874   PREFIX_0F3A61,
 875   PREFIX_0F3A62,
 876   PREFIX_0F3A63,
 877   PREFIX_0F3ADF,
 878   PREFIX_VEX_0F10,
 879   PREFIX_VEX_0F11,
 880   PREFIX_VEX_0F12,
 881   PREFIX_VEX_0F16,
 882   PREFIX_VEX_0F2A,
 883   PREFIX_VEX_0F2C,
 884   PREFIX_VEX_0F2D,
 885   PREFIX_VEX_0F2E,
 886   PREFIX_VEX_0F2F,
 887   PREFIX_VEX_0F51,
 888   PREFIX_VEX_0F52,
 889   PREFIX_VEX_0F53,
 890   PREFIX_VEX_0F58,
 891   PREFIX_VEX_0F59,
 892   PREFIX_VEX_0F5A,
 893   PREFIX_VEX_0F5B,
 894   PREFIX_VEX_0F5C,
 895   PREFIX_VEX_0F5D,
 896   PREFIX_VEX_0F5E,
 897   PREFIX_VEX_0F5F,
 898   PREFIX_VEX_0F60,
 899   PREFIX_VEX_0F61,
 900   PREFIX_VEX_0F62,
 901   PREFIX_VEX_0F63,
 902   PREFIX_VEX_0F64,
 903   PREFIX_VEX_0F65,
 904   PREFIX_VEX_0F66,
 905   PREFIX_VEX_0F67,
 906   PREFIX_VEX_0F68,
 907   PREFIX_VEX_0F69,
 908   PREFIX_VEX_0F6A,
 909   PREFIX_VEX_0F6B,
 910   PREFIX_VEX_0F6C,
 911   PREFIX_VEX_0F6D,
 912   PREFIX_VEX_0F6E,
 913   PREFIX_VEX_0F6F,
 914   PREFIX_VEX_0F70,
 915   PREFIX_VEX_0F71_REG_2,
 916   PREFIX_VEX_0F71_REG_4,
 917   PREFIX_VEX_0F71_REG_6,
 918   PREFIX_VEX_0F72_REG_2,
 919   PREFIX_VEX_0F72_REG_4,
 920   PREFIX_VEX_0F72_REG_6,
 921   PREFIX_VEX_0F73_REG_2,
 922   PREFIX_VEX_0F73_REG_3,
 923   PREFIX_VEX_0F73_REG_6,
 924   PREFIX_VEX_0F73_REG_7,
 925   PREFIX_VEX_0F74,
 926   PREFIX_VEX_0F75,
 927   PREFIX_VEX_0F76,
 928   PREFIX_VEX_0F77,
 929   PREFIX_VEX_0F7C,
 930   PREFIX_VEX_0F7D,
 931   PREFIX_VEX_0F7E,
 932   PREFIX_VEX_0F7F,
 933   PREFIX_VEX_0FC2,
 934   PREFIX_VEX_0FC4,
 935   PREFIX_VEX_0FC5,
 936   PREFIX_VEX_0FD0,
 937   PREFIX_VEX_0FD1,
 938   PREFIX_VEX_0FD2,
 939   PREFIX_VEX_0FD3,
 940   PREFIX_VEX_0FD4,
 941   PREFIX_VEX_0FD5,
 942   PREFIX_VEX_0FD6,
 943   PREFIX_VEX_0FD7,
 944   PREFIX_VEX_0FD8,
 945   PREFIX_VEX_0FD9,
 946   PREFIX_VEX_0FDA,
 947   PREFIX_VEX_0FDB,
 948   PREFIX_VEX_0FDC,
 949   PREFIX_VEX_0FDD,
 950   PREFIX_VEX_0FDE,
 951   PREFIX_VEX_0FDF,
 952   PREFIX_VEX_0FE0,
 953   PREFIX_VEX_0FE1,
 954   PREFIX_VEX_0FE2,
 955   PREFIX_VEX_0FE3,
 956   PREFIX_VEX_0FE4,
 957   PREFIX_VEX_0FE5,
 958   PREFIX_VEX_0FE6,
 959   PREFIX_VEX_0FE7,
 960   PREFIX_VEX_0FE8,
 961   PREFIX_VEX_0FE9,
 962   PREFIX_VEX_0FEA,
 963   PREFIX_VEX_0FEB,
 964   PREFIX_VEX_0FEC,
 965   PREFIX_VEX_0FED,
 966   PREFIX_VEX_0FEE,
 967   PREFIX_VEX_0FEF,
 968   PREFIX_VEX_0FF0,
 969   PREFIX_VEX_0FF1,
 970   PREFIX_VEX_0FF2,
 971   PREFIX_VEX_0FF3,
 972   PREFIX_VEX_0FF4,
 973   PREFIX_VEX_0FF5,
 974   PREFIX_VEX_0FF6,
 975   PREFIX_VEX_0FF7,
 976   PREFIX_VEX_0FF8,
 977   PREFIX_VEX_0FF9,
 978   PREFIX_VEX_0FFA,
 979   PREFIX_VEX_0FFB,
 980   PREFIX_VEX_0FFC,
 981   PREFIX_VEX_0FFD,
 982   PREFIX_VEX_0FFE,
 983   PREFIX_VEX_0F3800,
 984   PREFIX_VEX_0F3801,
 985   PREFIX_VEX_0F3802,
 986   PREFIX_VEX_0F3803,
 987   PREFIX_VEX_0F3804,
 988   PREFIX_VEX_0F3805,
 989   PREFIX_VEX_0F3806,
 990   PREFIX_VEX_0F3807,
 991   PREFIX_VEX_0F3808,
 992   PREFIX_VEX_0F3809,
 993   PREFIX_VEX_0F380A,
 994   PREFIX_VEX_0F380B,
 995   PREFIX_VEX_0F380C,
 996   PREFIX_VEX_0F380D,
 997   PREFIX_VEX_0F380E,
 998   PREFIX_VEX_0F380F,
 999   PREFIX_VEX_0F3813,
1000   PREFIX_VEX_0F3816,
1001   PREFIX_VEX_0F3817,
1002   PREFIX_VEX_0F3818,
1003   PREFIX_VEX_0F3819,
1004   PREFIX_VEX_0F381A,
1005   PREFIX_VEX_0F381C,
1006   PREFIX_VEX_0F381D,
1007   PREFIX_VEX_0F381E,
1008   PREFIX_VEX_0F3820,
1009   PREFIX_VEX_0F3821,
1010   PREFIX_VEX_0F3822,
1011   PREFIX_VEX_0F3823,
1012   PREFIX_VEX_0F3824,
1013   PREFIX_VEX_0F3825,
1014   PREFIX_VEX_0F3828,
1015   PREFIX_VEX_0F3829,
1016   PREFIX_VEX_0F382A,
1017   PREFIX_VEX_0F382B,
1018   PREFIX_VEX_0F382C,
1019   PREFIX_VEX_0F382D,
1020   PREFIX_VEX_0F382E,
1021   PREFIX_VEX_0F382F,
1022   PREFIX_VEX_0F3830,
1023   PREFIX_VEX_0F3831,
1024   PREFIX_VEX_0F3832,
1025   PREFIX_VEX_0F3833,
1026   PREFIX_VEX_0F3834,
1027   PREFIX_VEX_0F3835,
1028   PREFIX_VEX_0F3836,
1029   PREFIX_VEX_0F3837,
1030   PREFIX_VEX_0F3838,
1031   PREFIX_VEX_0F3839,
1032   PREFIX_VEX_0F383A,
1033   PREFIX_VEX_0F383B,
1034   PREFIX_VEX_0F383C,
1035   PREFIX_VEX_0F383D,
1036   PREFIX_VEX_0F383E,
1037   PREFIX_VEX_0F383F,
1038   PREFIX_VEX_0F3840,
1039   PREFIX_VEX_0F3841,
1040   PREFIX_VEX_0F3845,
1041   PREFIX_VEX_0F3846,
1042   PREFIX_VEX_0F3847,
1043   PREFIX_VEX_0F3858,
1044   PREFIX_VEX_0F3859,
1045   PREFIX_VEX_0F385A,
1046   PREFIX_VEX_0F3878,
1047   PREFIX_VEX_0F3879,
1048   PREFIX_VEX_0F388C,
1049   PREFIX_VEX_0F388E,
1050   PREFIX_VEX_0F3890,
1051   PREFIX_VEX_0F3891,
1052   PREFIX_VEX_0F3892,
1053   PREFIX_VEX_0F3893,
1054   PREFIX_VEX_0F3896,
1055   PREFIX_VEX_0F3897,
1056   PREFIX_VEX_0F3898,
1057   PREFIX_VEX_0F3899,
1058   PREFIX_VEX_0F389A,
1059   PREFIX_VEX_0F389B,
1060   PREFIX_VEX_0F389C,
1061   PREFIX_VEX_0F389D,
1062   PREFIX_VEX_0F389E,
1063   PREFIX_VEX_0F389F,
1064   PREFIX_VEX_0F38A6,
1065   PREFIX_VEX_0F38A7,
1066   PREFIX_VEX_0F38A8,
1067   PREFIX_VEX_0F38A9,
1068   PREFIX_VEX_0F38AA,
1069   PREFIX_VEX_0F38AB,
1070   PREFIX_VEX_0F38AC,
1071   PREFIX_VEX_0F38AD,
1072   PREFIX_VEX_0F38AE,
1073   PREFIX_VEX_0F38AF,
1074   PREFIX_VEX_0F38B6,
1075   PREFIX_VEX_0F38B7,
1076   PREFIX_VEX_0F38B8,
1077   PREFIX_VEX_0F38B9,
1078   PREFIX_VEX_0F38BA,
1079   PREFIX_VEX_0F38BB,
1080   PREFIX_VEX_0F38BC,
1081   PREFIX_VEX_0F38BD,
1082   PREFIX_VEX_0F38BE,
1083   PREFIX_VEX_0F38BF,
1084   PREFIX_VEX_0F38DB,
1085   PREFIX_VEX_0F38DC,
1086   PREFIX_VEX_0F38DD,
1087   PREFIX_VEX_0F38DE,
1088   PREFIX_VEX_0F38DF,
1089   PREFIX_VEX_0F38F2,
1090   PREFIX_VEX_0F38F3_REG_1,
1091   PREFIX_VEX_0F38F3_REG_2,
1092   PREFIX_VEX_0F38F3_REG_3,
1093   PREFIX_VEX_0F38F5,
1094   PREFIX_VEX_0F38F6,
1095   PREFIX_VEX_0F38F7,
1096   PREFIX_VEX_0F3A00,
1097   PREFIX_VEX_0F3A01,
1098   PREFIX_VEX_0F3A02,
1099   PREFIX_VEX_0F3A04,
1100   PREFIX_VEX_0F3A05,
1101   PREFIX_VEX_0F3A06,
1102   PREFIX_VEX_0F3A08,
1103   PREFIX_VEX_0F3A09,
1104   PREFIX_VEX_0F3A0A,
1105   PREFIX_VEX_0F3A0B,
1106   PREFIX_VEX_0F3A0C,
1107   PREFIX_VEX_0F3A0D,
1108   PREFIX_VEX_0F3A0E,
1109   PREFIX_VEX_0F3A0F,
1110   PREFIX_VEX_0F3A14,
1111   PREFIX_VEX_0F3A15,
1112   PREFIX_VEX_0F3A16,
1113   PREFIX_VEX_0F3A17,
1114   PREFIX_VEX_0F3A18,
1115   PREFIX_VEX_0F3A19,
1116   PREFIX_VEX_0F3A1D,
1117   PREFIX_VEX_0F3A20,
1118   PREFIX_VEX_0F3A21,
1119   PREFIX_VEX_0F3A22,
1120   PREFIX_VEX_0F3A38,
1121   PREFIX_VEX_0F3A39,
1122   PREFIX_VEX_0F3A40,
1123   PREFIX_VEX_0F3A41,
1124   PREFIX_VEX_0F3A42,
1125   PREFIX_VEX_0F3A44,
1126   PREFIX_VEX_0F3A46,
1127   PREFIX_VEX_0F3A48,
1128   PREFIX_VEX_0F3A49,
1129   PREFIX_VEX_0F3A4A,
1130   PREFIX_VEX_0F3A4B,
1131   PREFIX_VEX_0F3A4C,
1132   PREFIX_VEX_0F3A5C,
1133   PREFIX_VEX_0F3A5D,
1134   PREFIX_VEX_0F3A5E,
1135   PREFIX_VEX_0F3A5F,
1136   PREFIX_VEX_0F3A60,
1137   PREFIX_VEX_0F3A61,
1138   PREFIX_VEX_0F3A62,
1139   PREFIX_VEX_0F3A63,
1140   PREFIX_VEX_0F3A68,
1141   PREFIX_VEX_0F3A69,
1142   PREFIX_VEX_0F3A6A,
1143   PREFIX_VEX_0F3A6B,
1144   PREFIX_VEX_0F3A6C,
1145   PREFIX_VEX_0F3A6D,
1146   PREFIX_VEX_0F3A6E,
1147   PREFIX_VEX_0F3A6F,
1148   PREFIX_VEX_0F3A78,
1149   PREFIX_VEX_0F3A79,
1150   PREFIX_VEX_0F3A7A,
1151   PREFIX_VEX_0F3A7B,
1152   PREFIX_VEX_0F3A7C,
1153   PREFIX_VEX_0F3A7D,
1154   PREFIX_VEX_0F3A7E,
1155   PREFIX_VEX_0F3A7F,
1156   PREFIX_VEX_0F3ADF,
1157   PREFIX_VEX_0F3AF0
1158 };
1159
1160 enum
1161 {
1162   X86_64_06 = 0,
1163   X86_64_07,
1164   X86_64_0D,
1165   X86_64_16,
1166   X86_64_17,
1167   X86_64_1E,
1168   X86_64_1F,
1169   X86_64_27,
1170   X86_64_2F,
1171   X86_64_37,
1172   X86_64_3F,
1173   X86_64_60,
1174   X86_64_61,
1175   X86_64_62,
1176   X86_64_63,
1177   X86_64_6D,
1178   X86_64_6F,
1179   X86_64_9A,
1180   X86_64_C4,
1181   X86_64_C5,
1182   X86_64_CE,
1183   X86_64_D4,
1184   X86_64_D5,
1185   X86_64_EA,
1186   X86_64_0F01_REG_0,
1187   X86_64_0F01_REG_1,
1188   X86_64_0F01_REG_2,
1189   X86_64_0F01_REG_3
1190 };
1191
1192 enum
1193 {
1194   THREE_BYTE_0F38 = 0,
1195   THREE_BYTE_0F3A,
1196   THREE_BYTE_0F7A
1197 };
1198
1199 enum
1200 {
1201   XOP_08 = 0,
1202   XOP_09,
1203   XOP_0A
1204 };
1205
1206 enum
1207 {
1208   VEX_0F = 0,
1209   VEX_0F38,
1210   VEX_0F3A
1211 };
1212
1213 enum
1214 {
1215   VEX_LEN_0F10_P_1 = 0,
1216   VEX_LEN_0F10_P_3,
1217   VEX_LEN_0F11_P_1,
1218   VEX_LEN_0F11_P_3,
1219   VEX_LEN_0F12_P_0_M_0,
1220   VEX_LEN_0F12_P_0_M_1,
1221   VEX_LEN_0F12_P_2,
1222   VEX_LEN_0F13_M_0,
1223   VEX_LEN_0F16_P_0_M_0,
1224   VEX_LEN_0F16_P_0_M_1,
1225   VEX_LEN_0F16_P_2,
1226   VEX_LEN_0F17_M_0,
1227   VEX_LEN_0F2A_P_1,
1228   VEX_LEN_0F2A_P_3,
1229   VEX_LEN_0F2C_P_1,
1230   VEX_LEN_0F2C_P_3,
1231   VEX_LEN_0F2D_P_1,
1232   VEX_LEN_0F2D_P_3,
1233   VEX_LEN_0F2E_P_0,
1234   VEX_LEN_0F2E_P_2,
1235   VEX_LEN_0F2F_P_0,
1236   VEX_LEN_0F2F_P_2,
1237   VEX_LEN_0F51_P_1,
1238   VEX_LEN_0F51_P_3,
1239   VEX_LEN_0F52_P_1,
1240   VEX_LEN_0F53_P_1,
1241   VEX_LEN_0F58_P_1,
1242   VEX_LEN_0F58_P_3,
1243   VEX_LEN_0F59_P_1,
1244   VEX_LEN_0F59_P_3,
1245   VEX_LEN_0F5A_P_1,
1246   VEX_LEN_0F5A_P_3,
1247   VEX_LEN_0F5C_P_1,
1248   VEX_LEN_0F5C_P_3,
1249   VEX_LEN_0F5D_P_1,
1250   VEX_LEN_0F5D_P_3,
1251   VEX_LEN_0F5E_P_1,
1252   VEX_LEN_0F5E_P_3,
1253   VEX_LEN_0F5F_P_1,
1254   VEX_LEN_0F5F_P_3,
1255   VEX_LEN_0F6E_P_2,
1256   VEX_LEN_0F7E_P_1,
1257   VEX_LEN_0F7E_P_2,
1258   VEX_LEN_0FAE_R_2_M_0,
1259   VEX_LEN_0FAE_R_3_M_0,
1260   VEX_LEN_0FC2_P_1,
1261   VEX_LEN_0FC2_P_3,
1262   VEX_LEN_0FC4_P_2,
1263   VEX_LEN_0FC5_P_2,
1264   VEX_LEN_0FD6_P_2,
1265   VEX_LEN_0FF7_P_2,
1266   VEX_LEN_0F3816_P_2,
1267   VEX_LEN_0F3819_P_2,
1268   VEX_LEN_0F381A_P_2_M_0,
1269   VEX_LEN_0F3836_P_2,
1270   VEX_LEN_0F3841_P_2,
1271   VEX_LEN_0F385A_P_2_M_0,
1272   VEX_LEN_0F38DB_P_2,
1273   VEX_LEN_0F38DC_P_2,
1274   VEX_LEN_0F38DD_P_2,
1275   VEX_LEN_0F38DE_P_2,
1276   VEX_LEN_0F38DF_P_2,
1277   VEX_LEN_0F38F2_P_0,
1278   VEX_LEN_0F38F3_R_1_P_0,
1279   VEX_LEN_0F38F3_R_2_P_0,
1280   VEX_LEN_0F38F3_R_3_P_0,
1281   VEX_LEN_0F38F5_P_0,
1282   VEX_LEN_0F38F5_P_1,
1283   VEX_LEN_0F38F5_P_3,
1284   VEX_LEN_0F38F6_P_3,
1285   VEX_LEN_0F38F7_P_0,
1286   VEX_LEN_0F38F7_P_1,
1287   VEX_LEN_0F38F7_P_2,
1288   VEX_LEN_0F38F7_P_3,
1289   VEX_LEN_0F3A00_P_2,
1290   VEX_LEN_0F3A01_P_2,
1291   VEX_LEN_0F3A06_P_2,
1292   VEX_LEN_0F3A0A_P_2,
1293   VEX_LEN_0F3A0B_P_2,
1294   VEX_LEN_0F3A14_P_2,
1295   VEX_LEN_0F3A15_P_2,
1296   VEX_LEN_0F3A16_P_2,
1297   VEX_LEN_0F3A17_P_2,
1298   VEX_LEN_0F3A18_P_2,
1299   VEX_LEN_0F3A19_P_2,
1300   VEX_LEN_0F3A20_P_2,
1301   VEX_LEN_0F3A21_P_2,
1302   VEX_LEN_0F3A22_P_2,
1303   VEX_LEN_0F3A38_P_2,
1304   VEX_LEN_0F3A39_P_2,
1305   VEX_LEN_0F3A41_P_2,
1306   VEX_LEN_0F3A44_P_2,
1307   VEX_LEN_0F3A46_P_2,
1308   VEX_LEN_0F3A60_P_2,
1309   VEX_LEN_0F3A61_P_2,
1310   VEX_LEN_0F3A62_P_2,
1311   VEX_LEN_0F3A63_P_2,
1312   VEX_LEN_0F3A6A_P_2,
1313   VEX_LEN_0F3A6B_P_2,
1314   VEX_LEN_0F3A6E_P_2,
1315   VEX_LEN_0F3A6F_P_2,
1316   VEX_LEN_0F3A7A_P_2,
1317   VEX_LEN_0F3A7B_P_2,
1318   VEX_LEN_0F3A7E_P_2,
1319   VEX_LEN_0F3A7F_P_2,
1320   VEX_LEN_0F3ADF_P_2,
1321   VEX_LEN_0F3AF0_P_3,
1322   VEX_LEN_0FXOP_09_80,
1323   VEX_LEN_0FXOP_09_81
1324 };
1325
1326 enum
1327 {
1328   VEX_W_0F10_P_0 = 0,
1329   VEX_W_0F10_P_1,
1330   VEX_W_0F10_P_2,
1331   VEX_W_0F10_P_3,
1332   VEX_W_0F11_P_0,
1333   VEX_W_0F11_P_1,
1334   VEX_W_0F11_P_2,
1335   VEX_W_0F11_P_3,
1336   VEX_W_0F12_P_0_M_0,
1337   VEX_W_0F12_P_0_M_1,
1338   VEX_W_0F12_P_1,
1339   VEX_W_0F12_P_2,
1340   VEX_W_0F12_P_3,
1341   VEX_W_0F13_M_0,
1342   VEX_W_0F14,
1343   VEX_W_0F15,
1344   VEX_W_0F16_P_0_M_0,
1345   VEX_W_0F16_P_0_M_1,
1346   VEX_W_0F16_P_1,
1347   VEX_W_0F16_P_2,
1348   VEX_W_0F17_M_0,
1349   VEX_W_0F28,
1350   VEX_W_0F29,
1351   VEX_W_0F2B_M_0,
1352   VEX_W_0F2E_P_0,
1353   VEX_W_0F2E_P_2,
1354   VEX_W_0F2F_P_0,
1355   VEX_W_0F2F_P_2,
1356   VEX_W_0F50_M_0,
1357   VEX_W_0F51_P_0,
1358   VEX_W_0F51_P_1,
1359   VEX_W_0F51_P_2,
1360   VEX_W_0F51_P_3,
1361   VEX_W_0F52_P_0,
1362   VEX_W_0F52_P_1,
1363   VEX_W_0F53_P_0,
1364   VEX_W_0F53_P_1,
1365   VEX_W_0F58_P_0,
1366   VEX_W_0F58_P_1,
1367   VEX_W_0F58_P_2,
1368   VEX_W_0F58_P_3,
1369   VEX_W_0F59_P_0,
1370   VEX_W_0F59_P_1,
1371   VEX_W_0F59_P_2,
1372   VEX_W_0F59_P_3,
1373   VEX_W_0F5A_P_0,
1374   VEX_W_0F5A_P_1,
1375   VEX_W_0F5A_P_3,
1376   VEX_W_0F5B_P_0,
1377   VEX_W_0F5B_P_1,
1378   VEX_W_0F5B_P_2,
1379   VEX_W_0F5C_P_0,
1380   VEX_W_0F5C_P_1,
1381   VEX_W_0F5C_P_2,
1382   VEX_W_0F5C_P_3,
1383   VEX_W_0F5D_P_0,
1384   VEX_W_0F5D_P_1,
1385   VEX_W_0F5D_P_2,
1386   VEX_W_0F5D_P_3,
1387   VEX_W_0F5E_P_0,
1388   VEX_W_0F5E_P_1,
1389   VEX_W_0F5E_P_2,
1390   VEX_W_0F5E_P_3,
1391   VEX_W_0F5F_P_0,
1392   VEX_W_0F5F_P_1,
1393   VEX_W_0F5F_P_2,
1394   VEX_W_0F5F_P_3,
1395   VEX_W_0F60_P_2,
1396   VEX_W_0F61_P_2,
1397   VEX_W_0F62_P_2,
1398   VEX_W_0F63_P_2,
1399   VEX_W_0F64_P_2,
1400   VEX_W_0F65_P_2,
1401   VEX_W_0F66_P_2,
1402   VEX_W_0F67_P_2,
1403   VEX_W_0F68_P_2,
1404   VEX_W_0F69_P_2,
1405   VEX_W_0F6A_P_2,
1406   VEX_W_0F6B_P_2,
1407   VEX_W_0F6C_P_2,
1408   VEX_W_0F6D_P_2,
1409   VEX_W_0F6F_P_1,
1410   VEX_W_0F6F_P_2,
1411   VEX_W_0F70_P_1,
1412   VEX_W_0F70_P_2,
1413   VEX_W_0F70_P_3,
1414   VEX_W_0F71_R_2_P_2,
1415   VEX_W_0F71_R_4_P_2,
1416   VEX_W_0F71_R_6_P_2,
1417   VEX_W_0F72_R_2_P_2,
1418   VEX_W_0F72_R_4_P_2,
1419   VEX_W_0F72_R_6_P_2,
1420   VEX_W_0F73_R_2_P_2,
1421   VEX_W_0F73_R_3_P_2,
1422   VEX_W_0F73_R_6_P_2,
1423   VEX_W_0F73_R_7_P_2,
1424   VEX_W_0F74_P_2,
1425   VEX_W_0F75_P_2,
1426   VEX_W_0F76_P_2,
1427   VEX_W_0F77_P_0,
1428   VEX_W_0F7C_P_2,
1429   VEX_W_0F7C_P_3,
1430   VEX_W_0F7D_P_2,
1431   VEX_W_0F7D_P_3,
1432   VEX_W_0F7E_P_1,
1433   VEX_W_0F7F_P_1,
1434   VEX_W_0F7F_P_2,
1435   VEX_W_0FAE_R_2_M_0,
1436   VEX_W_0FAE_R_3_M_0,
1437   VEX_W_0FC2_P_0,
1438   VEX_W_0FC2_P_1,
1439   VEX_W_0FC2_P_2,
1440   VEX_W_0FC2_P_3,
1441   VEX_W_0FC4_P_2,
1442   VEX_W_0FC5_P_2,
1443   VEX_W_0FD0_P_2,
1444   VEX_W_0FD0_P_3,
1445   VEX_W_0FD1_P_2,
1446   VEX_W_0FD2_P_2,
1447   VEX_W_0FD3_P_2,
1448   VEX_W_0FD4_P_2,
1449   VEX_W_0FD5_P_2,
1450   VEX_W_0FD6_P_2,
1451   VEX_W_0FD7_P_2_M_1,
1452   VEX_W_0FD8_P_2,
1453   VEX_W_0FD9_P_2,
1454   VEX_W_0FDA_P_2,
1455   VEX_W_0FDB_P_2,
1456   VEX_W_0FDC_P_2,
1457   VEX_W_0FDD_P_2,
1458   VEX_W_0FDE_P_2,
1459   VEX_W_0FDF_P_2,
1460   VEX_W_0FE0_P_2,
1461   VEX_W_0FE1_P_2,
1462   VEX_W_0FE2_P_2,
1463   VEX_W_0FE3_P_2,
1464   VEX_W_0FE4_P_2,
1465   VEX_W_0FE5_P_2,
1466   VEX_W_0FE6_P_1,
1467   VEX_W_0FE6_P_2,
1468   VEX_W_0FE6_P_3,
1469   VEX_W_0FE7_P_2_M_0,
1470   VEX_W_0FE8_P_2,
1471   VEX_W_0FE9_P_2,
1472   VEX_W_0FEA_P_2,
1473   VEX_W_0FEB_P_2,
1474   VEX_W_0FEC_P_2,
1475   VEX_W_0FED_P_2,
1476   VEX_W_0FEE_P_2,
1477   VEX_W_0FEF_P_2,
1478   VEX_W_0FF0_P_3_M_0,
1479   VEX_W_0FF1_P_2,
1480   VEX_W_0FF2_P_2,
1481   VEX_W_0FF3_P_2,
1482   VEX_W_0FF4_P_2,
1483   VEX_W_0FF5_P_2,
1484   VEX_W_0FF6_P_2,
1485   VEX_W_0FF7_P_2,
1486   VEX_W_0FF8_P_2,
1487   VEX_W_0FF9_P_2,
1488   VEX_W_0FFA_P_2,
1489   VEX_W_0FFB_P_2,
1490   VEX_W_0FFC_P_2,
1491   VEX_W_0FFD_P_2,
1492   VEX_W_0FFE_P_2,
1493   VEX_W_0F3800_P_2,
1494   VEX_W_0F3801_P_2,
1495   VEX_W_0F3802_P_2,
1496   VEX_W_0F3803_P_2,
1497   VEX_W_0F3804_P_2,
1498   VEX_W_0F3805_P_2,
1499   VEX_W_0F3806_P_2,
1500   VEX_W_0F3807_P_2,
1501   VEX_W_0F3808_P_2,
1502   VEX_W_0F3809_P_2,
1503   VEX_W_0F380A_P_2,
1504   VEX_W_0F380B_P_2,
1505   VEX_W_0F380C_P_2,
1506   VEX_W_0F380D_P_2,
1507   VEX_W_0F380E_P_2,
1508   VEX_W_0F380F_P_2,
1509   VEX_W_0F3816_P_2,
1510   VEX_W_0F3817_P_2,
1511   VEX_W_0F3818_P_2,
1512   VEX_W_0F3819_P_2,
1513   VEX_W_0F381A_P_2_M_0,
1514   VEX_W_0F381C_P_2,
1515   VEX_W_0F381D_P_2,
1516   VEX_W_0F381E_P_2,
1517   VEX_W_0F3820_P_2,
1518   VEX_W_0F3821_P_2,
1519   VEX_W_0F3822_P_2,
1520   VEX_W_0F3823_P_2,
1521   VEX_W_0F3824_P_2,
1522   VEX_W_0F3825_P_2,
1523   VEX_W_0F3828_P_2,
1524   VEX_W_0F3829_P_2,
1525   VEX_W_0F382A_P_2_M_0,
1526   VEX_W_0F382B_P_2,
1527   VEX_W_0F382C_P_2_M_0,
1528   VEX_W_0F382D_P_2_M_0,
1529   VEX_W_0F382E_P_2_M_0,
1530   VEX_W_0F382F_P_2_M_0,
1531   VEX_W_0F3830_P_2,
1532   VEX_W_0F3831_P_2,
1533   VEX_W_0F3832_P_2,
1534   VEX_W_0F3833_P_2,
1535   VEX_W_0F3834_P_2,
1536   VEX_W_0F3835_P_2,
1537   VEX_W_0F3836_P_2,
1538   VEX_W_0F3837_P_2,
1539   VEX_W_0F3838_P_2,
1540   VEX_W_0F3839_P_2,
1541   VEX_W_0F383A_P_2,
1542   VEX_W_0F383B_P_2,
1543   VEX_W_0F383C_P_2,
1544   VEX_W_0F383D_P_2,
1545   VEX_W_0F383E_P_2,
1546   VEX_W_0F383F_P_2,
1547   VEX_W_0F3840_P_2,
1548   VEX_W_0F3841_P_2,
1549   VEX_W_0F3846_P_2,
1550   VEX_W_0F3858_P_2,
1551   VEX_W_0F3859_P_2,
1552   VEX_W_0F385A_P_2_M_0,
1553   VEX_W_0F3878_P_2,
1554   VEX_W_0F3879_P_2,
1555   VEX_W_0F38DB_P_2,
1556   VEX_W_0F38DC_P_2,
1557   VEX_W_0F38DD_P_2,
1558   VEX_W_0F38DE_P_2,
1559   VEX_W_0F38DF_P_2,
1560   VEX_W_0F3A00_P_2,
1561   VEX_W_0F3A01_P_2,
1562   VEX_W_0F3A02_P_2,
1563   VEX_W_0F3A04_P_2,
1564   VEX_W_0F3A05_P_2,
1565   VEX_W_0F3A06_P_2,
1566   VEX_W_0F3A08_P_2,
1567   VEX_W_0F3A09_P_2,
1568   VEX_W_0F3A0A_P_2,
1569   VEX_W_0F3A0B_P_2,
1570   VEX_W_0F3A0C_P_2,
1571   VEX_W_0F3A0D_P_2,
1572   VEX_W_0F3A0E_P_2,
1573   VEX_W_0F3A0F_P_2,
1574   VEX_W_0F3A14_P_2,
1575   VEX_W_0F3A15_P_2,
1576   VEX_W_0F3A18_P_2,
1577   VEX_W_0F3A19_P_2,
1578   VEX_W_0F3A20_P_2,
1579   VEX_W_0F3A21_P_2,
1580   VEX_W_0F3A38_P_2,
1581   VEX_W_0F3A39_P_2,
1582   VEX_W_0F3A40_P_2,
1583   VEX_W_0F3A41_P_2,
1584   VEX_W_0F3A42_P_2,
1585   VEX_W_0F3A44_P_2,
1586   VEX_W_0F3A46_P_2,
1587   VEX_W_0F3A48_P_2,
1588   VEX_W_0F3A49_P_2,
1589   VEX_W_0F3A4A_P_2,
1590   VEX_W_0F3A4B_P_2,
1591   VEX_W_0F3A4C_P_2,
1592   VEX_W_0F3A60_P_2,
1593   VEX_W_0F3A61_P_2,
1594   VEX_W_0F3A62_P_2,
1595   VEX_W_0F3A63_P_2,
1596   VEX_W_0F3ADF_P_2
1597 };
1598
1599 typedef void (*op_rtn) (int bytemode, int sizeflag);
1600
1601 struct dis386 {
1602   const char *name;
1603   struct
1604     {
1605       op_rtn rtn;
1606       int bytemode;
1607     } op[MAX_OPERANDS];
1608 };
1609
1610 /* Upper case letters in the instruction names here are macros.
1611    'A' => print 'b' if no register operands or suffix_always is true
1612    'B' => print 'b' if suffix_always is true
1613    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1614           size prefix
1615    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1616           suffix_always is true
1617    'E' => print 'e' if 32-bit form of jcxz
1618    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1619    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1620    'H' => print ",pt" or ",pn" branch hint
1621    'I' => honor following macro letter even in Intel mode (implemented only
1622           for some of the macro letters)
1623    'J' => print 'l'
1624    'K' => print 'd' or 'q' if rex prefix is present.
1625    'L' => print 'l' if suffix_always is true
1626    'M' => print 'r' if intel_mnemonic is false.
1627    'N' => print 'n' if instruction has no wait "prefix"
1628    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1629    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1630           or suffix_always is true.  print 'q' if rex prefix is present.
1631    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1632           is true
1633    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1634    'S' => print 'w', 'l' or 'q' if suffix_always is true
1635    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1636    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1637    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1638    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1639    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1640    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1641           suffix_always is true.
1642    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1643    '!' => change condition from true to false or from false to true.
1644    '%' => add 1 upper case letter to the macro.
1645
1646    2 upper case letter macros:
1647    "XY" => print 'x' or 'y' if no register operands or suffix_always
1648            is true.
1649    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1650    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1651            or suffix_always is true
1652    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1653    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1654    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1655    "LW" => print 'd', 'q' depending on the VEX.W bit
1656
1657    Many of the above letters print nothing in Intel mode.  See "putop"
1658    for the details.
1659
1660    Braces '{' and '}', and vertical bars '|', indicate alternative
1661    mnemonic strings for AT&T and Intel.  */
1662
1663 static const struct dis386 dis386[] = {
1664   /* 00 */
1665   { "addB",             { Ebh1, Gb } },
1666   { "addS",             { Evh1, Gv } },
1667   { "addB",             { Gb, EbS } },
1668   { "addS",             { Gv, EvS } },
1669   { "addB",             { AL, Ib } },
1670   { "addS",             { eAX, Iv } },
1671   { X86_64_TABLE (X86_64_06) },
1672   { X86_64_TABLE (X86_64_07) },
1673   /* 08 */
1674   { "orB",              { Ebh1, Gb } },
1675   { "orS",              { Evh1, Gv } },
1676   { "orB",              { Gb, EbS } },
1677   { "orS",              { Gv, EvS } },
1678   { "orB",              { AL, Ib } },
1679   { "orS",              { eAX, Iv } },
1680   { X86_64_TABLE (X86_64_0D) },
1681   { Bad_Opcode },       /* 0x0f extended opcode escape */
1682   /* 10 */
1683   { "adcB",             { Ebh1, Gb } },
1684   { "adcS",             { Evh1, Gv } },
1685   { "adcB",             { Gb, EbS } },
1686   { "adcS",             { Gv, EvS } },
1687   { "adcB",             { AL, Ib } },
1688   { "adcS",             { eAX, Iv } },
1689   { X86_64_TABLE (X86_64_16) },
1690   { X86_64_TABLE (X86_64_17) },
1691   /* 18 */
1692   { "sbbB",             { Ebh1, Gb } },
1693   { "sbbS",             { Evh1, Gv } },
1694   { "sbbB",             { Gb, EbS } },
1695   { "sbbS",             { Gv, EvS } },
1696   { "sbbB",             { AL, Ib } },
1697   { "sbbS",             { eAX, Iv } },
1698   { X86_64_TABLE (X86_64_1E) },
1699   { X86_64_TABLE (X86_64_1F) },
1700   /* 20 */
1701   { "andB",             { Ebh1, Gb } },
1702   { "andS",             { Evh1, Gv } },
1703   { "andB",             { Gb, EbS } },
1704   { "andS",             { Gv, EvS } },
1705   { "andB",             { AL, Ib } },
1706   { "andS",             { eAX, Iv } },
1707   { Bad_Opcode },       /* SEG ES prefix */
1708   { X86_64_TABLE (X86_64_27) },
1709   /* 28 */
1710   { "subB",             { Ebh1, Gb } },
1711   { "subS",             { Evh1, Gv } },
1712   { "subB",             { Gb, EbS } },
1713   { "subS",             { Gv, EvS } },
1714   { "subB",             { AL, Ib } },
1715   { "subS",             { eAX, Iv } },
1716   { Bad_Opcode },       /* SEG CS prefix */
1717   { X86_64_TABLE (X86_64_2F) },
1718   /* 30 */
1719   { "xorB",             { Ebh1, Gb } },
1720   { "xorS",             { Evh1, Gv } },
1721   { "xorB",             { Gb, EbS } },
1722   { "xorS",             { Gv, EvS } },
1723   { "xorB",             { AL, Ib } },
1724   { "xorS",             { eAX, Iv } },
1725   { Bad_Opcode },       /* SEG SS prefix */
1726   { X86_64_TABLE (X86_64_37) },
1727   /* 38 */
1728   { "cmpB",             { Eb, Gb } },
1729   { "cmpS",             { Ev, Gv } },
1730   { "cmpB",             { Gb, EbS } },
1731   { "cmpS",             { Gv, EvS } },
1732   { "cmpB",             { AL, Ib } },
1733   { "cmpS",             { eAX, Iv } },
1734   { Bad_Opcode },       /* SEG DS prefix */
1735   { X86_64_TABLE (X86_64_3F) },
1736   /* 40 */
1737   { "inc{S|}",          { RMeAX } },
1738   { "inc{S|}",          { RMeCX } },
1739   { "inc{S|}",          { RMeDX } },
1740   { "inc{S|}",          { RMeBX } },
1741   { "inc{S|}",          { RMeSP } },
1742   { "inc{S|}",          { RMeBP } },
1743   { "inc{S|}",          { RMeSI } },
1744   { "inc{S|}",          { RMeDI } },
1745   /* 48 */
1746   { "dec{S|}",          { RMeAX } },
1747   { "dec{S|}",          { RMeCX } },
1748   { "dec{S|}",          { RMeDX } },
1749   { "dec{S|}",          { RMeBX } },
1750   { "dec{S|}",          { RMeSP } },
1751   { "dec{S|}",          { RMeBP } },
1752   { "dec{S|}",          { RMeSI } },
1753   { "dec{S|}",          { RMeDI } },
1754   /* 50 */
1755   { "pushV",            { RMrAX } },
1756   { "pushV",            { RMrCX } },
1757   { "pushV",            { RMrDX } },
1758   { "pushV",            { RMrBX } },
1759   { "pushV",            { RMrSP } },
1760   { "pushV",            { RMrBP } },
1761   { "pushV",            { RMrSI } },
1762   { "pushV",            { RMrDI } },
1763   /* 58 */
1764   { "popV",             { RMrAX } },
1765   { "popV",             { RMrCX } },
1766   { "popV",             { RMrDX } },
1767   { "popV",             { RMrBX } },
1768   { "popV",             { RMrSP } },
1769   { "popV",             { RMrBP } },
1770   { "popV",             { RMrSI } },
1771   { "popV",             { RMrDI } },
1772   /* 60 */
1773   { X86_64_TABLE (X86_64_60) },
1774   { X86_64_TABLE (X86_64_61) },
1775   { X86_64_TABLE (X86_64_62) },
1776   { X86_64_TABLE (X86_64_63) },
1777   { Bad_Opcode },       /* seg fs */
1778   { Bad_Opcode },       /* seg gs */
1779   { Bad_Opcode },       /* op size prefix */
1780   { Bad_Opcode },       /* adr size prefix */
1781   /* 68 */
1782   { "pushT",            { sIv } },
1783   { "imulS",            { Gv, Ev, Iv } },
1784   { "pushT",            { sIbT } },
1785   { "imulS",            { Gv, Ev, sIb } },
1786   { "ins{b|}",          { Ybr, indirDX } },
1787   { X86_64_TABLE (X86_64_6D) },
1788   { "outs{b|}",         { indirDXr, Xb } },
1789   { X86_64_TABLE (X86_64_6F) },
1790   /* 70 */
1791   { "joH",              { Jb, XX, cond_jump_flag } },
1792   { "jnoH",             { Jb, XX, cond_jump_flag } },
1793   { "jbH",              { Jb, XX, cond_jump_flag } },
1794   { "jaeH",             { Jb, XX, cond_jump_flag } },
1795   { "jeH",              { Jb, XX, cond_jump_flag } },
1796   { "jneH",             { Jb, XX, cond_jump_flag } },
1797   { "jbeH",             { Jb, XX, cond_jump_flag } },
1798   { "jaH",              { Jb, XX, cond_jump_flag } },
1799   /* 78 */
1800   { "jsH",              { Jb, XX, cond_jump_flag } },
1801   { "jnsH",             { Jb, XX, cond_jump_flag } },
1802   { "jpH",              { Jb, XX, cond_jump_flag } },
1803   { "jnpH",             { Jb, XX, cond_jump_flag } },
1804   { "jlH",              { Jb, XX, cond_jump_flag } },
1805   { "jgeH",             { Jb, XX, cond_jump_flag } },
1806   { "jleH",             { Jb, XX, cond_jump_flag } },
1807   { "jgH",              { Jb, XX, cond_jump_flag } },
1808   /* 80 */
1809   { REG_TABLE (REG_80) },
1810   { REG_TABLE (REG_81) },
1811   { Bad_Opcode },
1812   { REG_TABLE (REG_82) },
1813   { "testB",            { Eb, Gb } },
1814   { "testS",            { Ev, Gv } },
1815   { "xchgB",            { Ebh2, Gb } },
1816   { "xchgS",            { Evh2, Gv } },
1817   /* 88 */
1818   { "movB",             { Ebh3, Gb } },
1819   { "movS",             { Evh3, Gv } },
1820   { "movB",             { Gb, EbS } },
1821   { "movS",             { Gv, EvS } },
1822   { "movD",             { Sv, Sw } },
1823   { MOD_TABLE (MOD_8D) },
1824   { "movD",             { Sw, Sv } },
1825   { REG_TABLE (REG_8F) },
1826   /* 90 */
1827   { PREFIX_TABLE (PREFIX_90) },
1828   { "xchgS",            { RMeCX, eAX } },
1829   { "xchgS",            { RMeDX, eAX } },
1830   { "xchgS",            { RMeBX, eAX } },
1831   { "xchgS",            { RMeSP, eAX } },
1832   { "xchgS",            { RMeBP, eAX } },
1833   { "xchgS",            { RMeSI, eAX } },
1834   { "xchgS",            { RMeDI, eAX } },
1835   /* 98 */
1836   { "cW{t|}R",          { XX } },
1837   { "cR{t|}O",          { XX } },
1838   { X86_64_TABLE (X86_64_9A) },
1839   { Bad_Opcode },       /* fwait */
1840   { "pushfT",           { XX } },
1841   { "popfT",            { XX } },
1842   { "sahf",             { XX } },
1843   { "lahf",             { XX } },
1844   /* a0 */
1845   { "mov%LB",           { AL, Ob } },
1846   { "mov%LS",           { eAX, Ov } },
1847   { "mov%LB",           { Ob, AL } },
1848   { "mov%LS",           { Ov, eAX } },
1849   { "movs{b|}",         { Ybr, Xb } },
1850   { "movs{R|}",         { Yvr, Xv } },
1851   { "cmps{b|}",         { Xb, Yb } },
1852   { "cmps{R|}",         { Xv, Yv } },
1853   /* a8 */
1854   { "testB",            { AL, Ib } },
1855   { "testS",            { eAX, Iv } },
1856   { "stosB",            { Ybr, AL } },
1857   { "stosS",            { Yvr, eAX } },
1858   { "lodsB",            { ALr, Xb } },
1859   { "lodsS",            { eAXr, Xv } },
1860   { "scasB",            { AL, Yb } },
1861   { "scasS",            { eAX, Yv } },
1862   /* b0 */
1863   { "movB",             { RMAL, Ib } },
1864   { "movB",             { RMCL, Ib } },
1865   { "movB",             { RMDL, Ib } },
1866   { "movB",             { RMBL, Ib } },
1867   { "movB",             { RMAH, Ib } },
1868   { "movB",             { RMCH, Ib } },
1869   { "movB",             { RMDH, Ib } },
1870   { "movB",             { RMBH, Ib } },
1871   /* b8 */
1872   { "mov%LV",           { RMeAX, Iv64 } },
1873   { "mov%LV",           { RMeCX, Iv64 } },
1874   { "mov%LV",           { RMeDX, Iv64 } },
1875   { "mov%LV",           { RMeBX, Iv64 } },
1876   { "mov%LV",           { RMeSP, Iv64 } },
1877   { "mov%LV",           { RMeBP, Iv64 } },
1878   { "mov%LV",           { RMeSI, Iv64 } },
1879   { "mov%LV",           { RMeDI, Iv64 } },
1880   /* c0 */
1881   { REG_TABLE (REG_C0) },
1882   { REG_TABLE (REG_C1) },
1883   { "retT",             { Iw } },
1884   { "retT",             { XX } },
1885   { X86_64_TABLE (X86_64_C4) },
1886   { X86_64_TABLE (X86_64_C5) },
1887   { REG_TABLE (REG_C6) },
1888   { REG_TABLE (REG_C7) },
1889   /* c8 */
1890   { "enterT",           { Iw, Ib } },
1891   { "leaveT",           { XX } },
1892   { "Jret{|f}P",        { Iw } },
1893   { "Jret{|f}P",        { XX } },
1894   { "int3",             { XX } },
1895   { "int",              { Ib } },
1896   { X86_64_TABLE (X86_64_CE) },
1897   { "iretP",            { XX } },
1898   /* d0 */
1899   { REG_TABLE (REG_D0) },
1900   { REG_TABLE (REG_D1) },
1901   { REG_TABLE (REG_D2) },
1902   { REG_TABLE (REG_D3) },
1903   { X86_64_TABLE (X86_64_D4) },
1904   { X86_64_TABLE (X86_64_D5) },
1905   { Bad_Opcode },
1906   { "xlat",             { DSBX } },
1907   /* d8 */
1908   { FLOAT },
1909   { FLOAT },
1910   { FLOAT },
1911   { FLOAT },
1912   { FLOAT },
1913   { FLOAT },
1914   { FLOAT },
1915   { FLOAT },
1916   /* e0 */
1917   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1918   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1919   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1920   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1921   { "inB",              { AL, Ib } },
1922   { "inG",              { zAX, Ib } },
1923   { "outB",             { Ib, AL } },
1924   { "outG",             { Ib, zAX } },
1925   /* e8 */
1926   { "callT",            { Jv } },
1927   { "jmpT",             { Jv } },
1928   { X86_64_TABLE (X86_64_EA) },
1929   { "jmp",              { Jb } },
1930   { "inB",              { AL, indirDX } },
1931   { "inG",              { zAX, indirDX } },
1932   { "outB",             { indirDX, AL } },
1933   { "outG",             { indirDX, zAX } },
1934   /* f0 */
1935   { Bad_Opcode },       /* lock prefix */
1936   { "icebp",            { XX } },
1937   { Bad_Opcode },       /* repne */
1938   { Bad_Opcode },       /* repz */
1939   { "hlt",              { XX } },
1940   { "cmc",              { XX } },
1941   { REG_TABLE (REG_F6) },
1942   { REG_TABLE (REG_F7) },
1943   /* f8 */
1944   { "clc",              { XX } },
1945   { "stc",              { XX } },
1946   { "cli",              { XX } },
1947   { "sti",              { XX } },
1948   { "cld",              { XX } },
1949   { "std",              { XX } },
1950   { REG_TABLE (REG_FE) },
1951   { REG_TABLE (REG_FF) },
1952 };
1953
1954 static const struct dis386 dis386_twobyte[] = {
1955   /* 00 */
1956   { REG_TABLE (REG_0F00 ) },
1957   { REG_TABLE (REG_0F01 ) },
1958   { "larS",             { Gv, Ew } },
1959   { "lslS",             { Gv, Ew } },
1960   { Bad_Opcode },
1961   { "syscall",          { XX } },
1962   { "clts",             { XX } },
1963   { "sysretP",          { XX } },
1964   /* 08 */
1965   { "invd",             { XX } },
1966   { "wbinvd",           { XX } },
1967   { Bad_Opcode },
1968   { "ud2",              { XX } },
1969   { Bad_Opcode },
1970   { REG_TABLE (REG_0F0D) },
1971   { "femms",            { XX } },
1972   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1973   /* 10 */
1974   { PREFIX_TABLE (PREFIX_0F10) },
1975   { PREFIX_TABLE (PREFIX_0F11) },
1976   { PREFIX_TABLE (PREFIX_0F12) },
1977   { MOD_TABLE (MOD_0F13) },
1978   { "unpcklpX",         { XM, EXx } },
1979   { "unpckhpX",         { XM, EXx } },
1980   { PREFIX_TABLE (PREFIX_0F16) },
1981   { MOD_TABLE (MOD_0F17) },
1982   /* 18 */
1983   { REG_TABLE (REG_0F18) },
1984   { "nopQ",             { Ev } },
1985   { "nopQ",             { Ev } },
1986   { "nopQ",             { Ev } },
1987   { "nopQ",             { Ev } },
1988   { "nopQ",             { Ev } },
1989   { "nopQ",             { Ev } },
1990   { "nopQ",             { Ev } },
1991   /* 20 */
1992   { MOD_TABLE (MOD_0F20) },
1993   { MOD_TABLE (MOD_0F21) },
1994   { MOD_TABLE (MOD_0F22) },
1995   { MOD_TABLE (MOD_0F23) },
1996   { MOD_TABLE (MOD_0F24) },
1997   { Bad_Opcode },
1998   { MOD_TABLE (MOD_0F26) },
1999   { Bad_Opcode },
2000   /* 28 */
2001   { "movapX",           { XM, EXx } },
2002   { "movapX",           { EXxS, XM } },
2003   { PREFIX_TABLE (PREFIX_0F2A) },
2004   { PREFIX_TABLE (PREFIX_0F2B) },
2005   { PREFIX_TABLE (PREFIX_0F2C) },
2006   { PREFIX_TABLE (PREFIX_0F2D) },
2007   { PREFIX_TABLE (PREFIX_0F2E) },
2008   { PREFIX_TABLE (PREFIX_0F2F) },
2009   /* 30 */
2010   { "wrmsr",            { XX } },
2011   { "rdtsc",            { XX } },
2012   { "rdmsr",            { XX } },
2013   { "rdpmc",            { XX } },
2014   { "sysenter",         { XX } },
2015   { "sysexit",          { XX } },
2016   { Bad_Opcode },
2017   { "getsec",           { XX } },
2018   /* 38 */
2019   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2020   { Bad_Opcode },
2021   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2022   { Bad_Opcode },
2023   { Bad_Opcode },
2024   { Bad_Opcode },
2025   { Bad_Opcode },
2026   { Bad_Opcode },
2027   /* 40 */
2028   { "cmovoS",           { Gv, Ev } },
2029   { "cmovnoS",          { Gv, Ev } },
2030   { "cmovbS",           { Gv, Ev } },
2031   { "cmovaeS",          { Gv, Ev } },
2032   { "cmoveS",           { Gv, Ev } },
2033   { "cmovneS",          { Gv, Ev } },
2034   { "cmovbeS",          { Gv, Ev } },
2035   { "cmovaS",           { Gv, Ev } },
2036   /* 48 */
2037   { "cmovsS",           { Gv, Ev } },
2038   { "cmovnsS",          { Gv, Ev } },
2039   { "cmovpS",           { Gv, Ev } },
2040   { "cmovnpS",          { Gv, Ev } },
2041   { "cmovlS",           { Gv, Ev } },
2042   { "cmovgeS",          { Gv, Ev } },
2043   { "cmovleS",          { Gv, Ev } },
2044   { "cmovgS",           { Gv, Ev } },
2045   /* 50 */
2046   { MOD_TABLE (MOD_0F51) },
2047   { PREFIX_TABLE (PREFIX_0F51) },
2048   { PREFIX_TABLE (PREFIX_0F52) },
2049   { PREFIX_TABLE (PREFIX_0F53) },
2050   { "andpX",            { XM, EXx } },
2051   { "andnpX",           { XM, EXx } },
2052   { "orpX",             { XM, EXx } },
2053   { "xorpX",            { XM, EXx } },
2054   /* 58 */
2055   { PREFIX_TABLE (PREFIX_0F58) },
2056   { PREFIX_TABLE (PREFIX_0F59) },
2057   { PREFIX_TABLE (PREFIX_0F5A) },
2058   { PREFIX_TABLE (PREFIX_0F5B) },
2059   { PREFIX_TABLE (PREFIX_0F5C) },
2060   { PREFIX_TABLE (PREFIX_0F5D) },
2061   { PREFIX_TABLE (PREFIX_0F5E) },
2062   { PREFIX_TABLE (PREFIX_0F5F) },
2063   /* 60 */
2064   { PREFIX_TABLE (PREFIX_0F60) },
2065   { PREFIX_TABLE (PREFIX_0F61) },
2066   { PREFIX_TABLE (PREFIX_0F62) },
2067   { "packsswb",         { MX, EM } },
2068   { "pcmpgtb",          { MX, EM } },
2069   { "pcmpgtw",          { MX, EM } },
2070   { "pcmpgtd",          { MX, EM } },
2071   { "packuswb",         { MX, EM } },
2072   /* 68 */
2073   { "punpckhbw",        { MX, EM } },
2074   { "punpckhwd",        { MX, EM } },
2075   { "punpckhdq",        { MX, EM } },
2076   { "packssdw",         { MX, EM } },
2077   { PREFIX_TABLE (PREFIX_0F6C) },
2078   { PREFIX_TABLE (PREFIX_0F6D) },
2079   { "movK",             { MX, Edq } },
2080   { PREFIX_TABLE (PREFIX_0F6F) },
2081   /* 70 */
2082   { PREFIX_TABLE (PREFIX_0F70) },
2083   { REG_TABLE (REG_0F71) },
2084   { REG_TABLE (REG_0F72) },
2085   { REG_TABLE (REG_0F73) },
2086   { "pcmpeqb",          { MX, EM } },
2087   { "pcmpeqw",          { MX, EM } },
2088   { "pcmpeqd",          { MX, EM } },
2089   { "emms",             { XX } },
2090   /* 78 */
2091   { PREFIX_TABLE (PREFIX_0F78) },
2092   { PREFIX_TABLE (PREFIX_0F79) },
2093   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2094   { Bad_Opcode },
2095   { PREFIX_TABLE (PREFIX_0F7C) },
2096   { PREFIX_TABLE (PREFIX_0F7D) },
2097   { PREFIX_TABLE (PREFIX_0F7E) },
2098   { PREFIX_TABLE (PREFIX_0F7F) },
2099   /* 80 */
2100   { "joH",              { Jv, XX, cond_jump_flag } },
2101   { "jnoH",             { Jv, XX, cond_jump_flag } },
2102   { "jbH",              { Jv, XX, cond_jump_flag } },
2103   { "jaeH",             { Jv, XX, cond_jump_flag } },
2104   { "jeH",              { Jv, XX, cond_jump_flag } },
2105   { "jneH",             { Jv, XX, cond_jump_flag } },
2106   { "jbeH",             { Jv, XX, cond_jump_flag } },
2107   { "jaH",              { Jv, XX, cond_jump_flag } },
2108   /* 88 */
2109   { "jsH",              { Jv, XX, cond_jump_flag } },
2110   { "jnsH",             { Jv, XX, cond_jump_flag } },
2111   { "jpH",              { Jv, XX, cond_jump_flag } },
2112   { "jnpH",             { Jv, XX, cond_jump_flag } },
2113   { "jlH",              { Jv, XX, cond_jump_flag } },
2114   { "jgeH",             { Jv, XX, cond_jump_flag } },
2115   { "jleH",             { Jv, XX, cond_jump_flag } },
2116   { "jgH",              { Jv, XX, cond_jump_flag } },
2117   /* 90 */
2118   { "seto",             { Eb } },
2119   { "setno",            { Eb } },
2120   { "setb",             { Eb } },
2121   { "setae",            { Eb } },
2122   { "sete",             { Eb } },
2123   { "setne",            { Eb } },
2124   { "setbe",            { Eb } },
2125   { "seta",             { Eb } },
2126   /* 98 */
2127   { "sets",             { Eb } },
2128   { "setns",            { Eb } },
2129   { "setp",             { Eb } },
2130   { "setnp",            { Eb } },
2131   { "setl",             { Eb } },
2132   { "setge",            { Eb } },
2133   { "setle",            { Eb } },
2134   { "setg",             { Eb } },
2135   /* a0 */
2136   { "pushT",            { fs } },
2137   { "popT",             { fs } },
2138   { "cpuid",            { XX } },
2139   { "btS",              { Ev, Gv } },
2140   { "shldS",            { Ev, Gv, Ib } },
2141   { "shldS",            { Ev, Gv, CL } },
2142   { REG_TABLE (REG_0FA6) },
2143   { REG_TABLE (REG_0FA7) },
2144   /* a8 */
2145   { "pushT",            { gs } },
2146   { "popT",             { gs } },
2147   { "rsm",              { XX } },
2148   { "btsS",             { Evh1, Gv } },
2149   { "shrdS",            { Ev, Gv, Ib } },
2150   { "shrdS",            { Ev, Gv, CL } },
2151   { REG_TABLE (REG_0FAE) },
2152   { "imulS",            { Gv, Ev } },
2153   /* b0 */
2154   { "cmpxchgB",         { Ebh1, Gb } },
2155   { "cmpxchgS",         { Evh1, Gv } },
2156   { MOD_TABLE (MOD_0FB2) },
2157   { "btrS",             { Evh1, Gv } },
2158   { MOD_TABLE (MOD_0FB4) },
2159   { MOD_TABLE (MOD_0FB5) },
2160   { "movz{bR|x}",       { Gv, Eb } },
2161   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2162   /* b8 */
2163   { PREFIX_TABLE (PREFIX_0FB8) },
2164   { "ud1",              { XX } },
2165   { REG_TABLE (REG_0FBA) },
2166   { "btcS",             { Evh1, Gv } },
2167   { PREFIX_TABLE (PREFIX_0FBC) },
2168   { PREFIX_TABLE (PREFIX_0FBD) },
2169   { "movs{bR|x}",       { Gv, Eb } },
2170   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2171   /* c0 */
2172   { "xaddB",            { Ebh1, Gb } },
2173   { "xaddS",            { Evh1, Gv } },
2174   { PREFIX_TABLE (PREFIX_0FC2) },
2175   { PREFIX_TABLE (PREFIX_0FC3) },
2176   { "pinsrw",           { MX, Edqw, Ib } },
2177   { "pextrw",           { Gdq, MS, Ib } },
2178   { "shufpX",           { XM, EXx, Ib } },
2179   { REG_TABLE (REG_0FC7) },
2180   /* c8 */
2181   { "bswap",            { RMeAX } },
2182   { "bswap",            { RMeCX } },
2183   { "bswap",            { RMeDX } },
2184   { "bswap",            { RMeBX } },
2185   { "bswap",            { RMeSP } },
2186   { "bswap",            { RMeBP } },
2187   { "bswap",            { RMeSI } },
2188   { "bswap",            { RMeDI } },
2189   /* d0 */
2190   { PREFIX_TABLE (PREFIX_0FD0) },
2191   { "psrlw",            { MX, EM } },
2192   { "psrld",            { MX, EM } },
2193   { "psrlq",            { MX, EM } },
2194   { "paddq",            { MX, EM } },
2195   { "pmullw",           { MX, EM } },
2196   { PREFIX_TABLE (PREFIX_0FD6) },
2197   { MOD_TABLE (MOD_0FD7) },
2198   /* d8 */
2199   { "psubusb",          { MX, EM } },
2200   { "psubusw",          { MX, EM } },
2201   { "pminub",           { MX, EM } },
2202   { "pand",             { MX, EM } },
2203   { "paddusb",          { MX, EM } },
2204   { "paddusw",          { MX, EM } },
2205   { "pmaxub",           { MX, EM } },
2206   { "pandn",            { MX, EM } },
2207   /* e0 */
2208   { "pavgb",            { MX, EM } },
2209   { "psraw",            { MX, EM } },
2210   { "psrad",            { MX, EM } },
2211   { "pavgw",            { MX, EM } },
2212   { "pmulhuw",          { MX, EM } },
2213   { "pmulhw",           { MX, EM } },
2214   { PREFIX_TABLE (PREFIX_0FE6) },
2215   { PREFIX_TABLE (PREFIX_0FE7) },
2216   /* e8 */
2217   { "psubsb",           { MX, EM } },
2218   { "psubsw",           { MX, EM } },
2219   { "pminsw",           { MX, EM } },
2220   { "por",              { MX, EM } },
2221   { "paddsb",           { MX, EM } },
2222   { "paddsw",           { MX, EM } },
2223   { "pmaxsw",           { MX, EM } },
2224   { "pxor",             { MX, EM } },
2225   /* f0 */
2226   { PREFIX_TABLE (PREFIX_0FF0) },
2227   { "psllw",            { MX, EM } },
2228   { "pslld",            { MX, EM } },
2229   { "psllq",            { MX, EM } },
2230   { "pmuludq",          { MX, EM } },
2231   { "pmaddwd",          { MX, EM } },
2232   { "psadbw",           { MX, EM } },
2233   { PREFIX_TABLE (PREFIX_0FF7) },
2234   /* f8 */
2235   { "psubb",            { MX, EM } },
2236   { "psubw",            { MX, EM } },
2237   { "psubd",            { MX, EM } },
2238   { "psubq",            { MX, EM } },
2239   { "paddb",            { MX, EM } },
2240   { "paddw",            { MX, EM } },
2241   { "paddd",            { MX, EM } },
2242   { Bad_Opcode },
2243 };
2244
2245 static const unsigned char onebyte_has_modrm[256] = {
2246   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2247   /*       -------------------------------        */
2248   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2249   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2250   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2251   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2252   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2253   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2254   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2255   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2256   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2257   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2258   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2259   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2260   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2261   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2262   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2263   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2264   /*       -------------------------------        */
2265   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2266 };
2267
2268 static const unsigned char twobyte_has_modrm[256] = {
2269   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2270   /*       -------------------------------        */
2271   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2272   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2273   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2274   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2275   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2276   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2277   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2278   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2279   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2280   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2281   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2282   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2283   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2284   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2285   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2286   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2287   /*       -------------------------------        */
2288   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2289 };
2290
2291 static char obuf[100];
2292 static char *obufp;
2293 static char *mnemonicendp;
2294 static char scratchbuf[100];
2295 static unsigned char *start_codep;
2296 static unsigned char *insn_codep;
2297 static unsigned char *codep;
2298 static int last_lock_prefix;
2299 static int last_repz_prefix;
2300 static int last_repnz_prefix;
2301 static int last_data_prefix;
2302 static int last_addr_prefix;
2303 static int last_rex_prefix;
2304 static int last_seg_prefix;
2305 #define MAX_CODE_LENGTH 15
2306 /* We can up to 14 prefixes since the maximum instruction length is
2307    15bytes.  */
2308 static int all_prefixes[MAX_CODE_LENGTH - 1];
2309 static disassemble_info *the_info;
2310 static struct
2311   {
2312     int mod;
2313     int reg;
2314     int rm;
2315   }
2316 modrm;
2317 static unsigned char need_modrm;
2318 static struct
2319   {
2320     int scale;
2321     int index;
2322     int base;
2323   }
2324 sib;
2325 static struct
2326   {
2327     int register_specifier;
2328     int length;
2329     int prefix;
2330     int w;
2331   }
2332 vex;
2333 static unsigned char need_vex;
2334 static unsigned char need_vex_reg;
2335 static unsigned char vex_w_done;
2336
2337 struct op
2338   {
2339     const char *name;
2340     unsigned int len;
2341   };
2342
2343 /* If we are accessing mod/rm/reg without need_modrm set, then the
2344    values are stale.  Hitting this abort likely indicates that you
2345    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2346 #define MODRM_CHECK  if (!need_modrm) abort ()
2347
2348 static const char **names64;
2349 static const char **names32;
2350 static const char **names16;
2351 static const char **names8;
2352 static const char **names8rex;
2353 static const char **names_seg;
2354 static const char *index64;
2355 static const char *index32;
2356 static const char **index16;
2357
2358 static const char *intel_names64[] = {
2359   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2360   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2361 };
2362 static const char *intel_names32[] = {
2363   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2364   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2365 };
2366 static const char *intel_names16[] = {
2367   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2368   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2369 };
2370 static const char *intel_names8[] = {
2371   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2372 };
2373 static const char *intel_names8rex[] = {
2374   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2375   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2376 };
2377 static const char *intel_names_seg[] = {
2378   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2379 };
2380 static const char *intel_index64 = "riz";
2381 static const char *intel_index32 = "eiz";
2382 static const char *intel_index16[] = {
2383   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2384 };
2385
2386 static const char *att_names64[] = {
2387   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2388   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2389 };
2390 static const char *att_names32[] = {
2391   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2392   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2393 };
2394 static const char *att_names16[] = {
2395   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2396   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2397 };
2398 static const char *att_names8[] = {
2399   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2400 };
2401 static const char *att_names8rex[] = {
2402   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2403   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2404 };
2405 static const char *att_names_seg[] = {
2406   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2407 };
2408 static const char *att_index64 = "%riz";
2409 static const char *att_index32 = "%eiz";
2410 static const char *att_index16[] = {
2411   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2412 };
2413
2414 static const char **names_mm;
2415 static const char *intel_names_mm[] = {
2416   "mm0", "mm1", "mm2", "mm3",
2417   "mm4", "mm5", "mm6", "mm7"
2418 };
2419 static const char *att_names_mm[] = {
2420   "%mm0", "%mm1", "%mm2", "%mm3",
2421   "%mm4", "%mm5", "%mm6", "%mm7"
2422 };
2423
2424 static const char **names_xmm;
2425 static const char *intel_names_xmm[] = {
2426   "xmm0", "xmm1", "xmm2", "xmm3",
2427   "xmm4", "xmm5", "xmm6", "xmm7",
2428   "xmm8", "xmm9", "xmm10", "xmm11",
2429   "xmm12", "xmm13", "xmm14", "xmm15"
2430 };
2431 static const char *att_names_xmm[] = {
2432   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2433   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2434   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2435   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2436 };
2437
2438 static const char **names_ymm;
2439 static const char *intel_names_ymm[] = {
2440   "ymm0", "ymm1", "ymm2", "ymm3",
2441   "ymm4", "ymm5", "ymm6", "ymm7",
2442   "ymm8", "ymm9", "ymm10", "ymm11",
2443   "ymm12", "ymm13", "ymm14", "ymm15"
2444 };
2445 static const char *att_names_ymm[] = {
2446   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2447   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2448   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2449   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2450 };
2451
2452 static const struct dis386 reg_table[][8] = {
2453   /* REG_80 */
2454   {
2455     { "addA",   { Ebh1, Ib } },
2456     { "orA",    { Ebh1, Ib } },
2457     { "adcA",   { Ebh1, Ib } },
2458     { "sbbA",   { Ebh1, Ib } },
2459     { "andA",   { Ebh1, Ib } },
2460     { "subA",   { Ebh1, Ib } },
2461     { "xorA",   { Ebh1, Ib } },
2462     { "cmpA",   { Eb, Ib } },
2463   },
2464   /* REG_81 */
2465   {
2466     { "addQ",   { Evh1, Iv } },
2467     { "orQ",    { Evh1, Iv } },
2468     { "adcQ",   { Evh1, Iv } },
2469     { "sbbQ",   { Evh1, Iv } },
2470     { "andQ",   { Evh1, Iv } },
2471     { "subQ",   { Evh1, Iv } },
2472     { "xorQ",   { Evh1, Iv } },
2473     { "cmpQ",   { Ev, Iv } },
2474   },
2475   /* REG_82 */
2476   {
2477     { "addQ",   { Evh1, sIb } },
2478     { "orQ",    { Evh1, sIb } },
2479     { "adcQ",   { Evh1, sIb } },
2480     { "sbbQ",   { Evh1, sIb } },
2481     { "andQ",   { Evh1, sIb } },
2482     { "subQ",   { Evh1, sIb } },
2483     { "xorQ",   { Evh1, sIb } },
2484     { "cmpQ",   { Ev, sIb } },
2485   },
2486   /* REG_8F */
2487   {
2488     { "popU",   { stackEv } },
2489     { XOP_8F_TABLE (XOP_09) },
2490     { Bad_Opcode },
2491     { Bad_Opcode },
2492     { Bad_Opcode },
2493     { XOP_8F_TABLE (XOP_09) },
2494   },
2495   /* REG_C0 */
2496   {
2497     { "rolA",   { Eb, Ib } },
2498     { "rorA",   { Eb, Ib } },
2499     { "rclA",   { Eb, Ib } },
2500     { "rcrA",   { Eb, Ib } },
2501     { "shlA",   { Eb, Ib } },
2502     { "shrA",   { Eb, Ib } },
2503     { Bad_Opcode },
2504     { "sarA",   { Eb, Ib } },
2505   },
2506   /* REG_C1 */
2507   {
2508     { "rolQ",   { Ev, Ib } },
2509     { "rorQ",   { Ev, Ib } },
2510     { "rclQ",   { Ev, Ib } },
2511     { "rcrQ",   { Ev, Ib } },
2512     { "shlQ",   { Ev, Ib } },
2513     { "shrQ",   { Ev, Ib } },
2514     { Bad_Opcode },
2515     { "sarQ",   { Ev, Ib } },
2516   },
2517   /* REG_C6 */
2518   {
2519     { "movA",   { Ebh3, Ib } },
2520     { Bad_Opcode },
2521     { Bad_Opcode },
2522     { Bad_Opcode },
2523     { Bad_Opcode },
2524     { Bad_Opcode },
2525     { Bad_Opcode },
2526     { MOD_TABLE (MOD_C6_REG_7) },
2527   },
2528   /* REG_C7 */
2529   {
2530     { "movQ",   { Evh3, Iv } },
2531     { Bad_Opcode },
2532     { Bad_Opcode },
2533     { Bad_Opcode },
2534     { Bad_Opcode },
2535     { Bad_Opcode },
2536     { Bad_Opcode },
2537     { MOD_TABLE (MOD_C7_REG_7) },
2538   },
2539   /* REG_D0 */
2540   {
2541     { "rolA",   { Eb, I1 } },
2542     { "rorA",   { Eb, I1 } },
2543     { "rclA",   { Eb, I1 } },
2544     { "rcrA",   { Eb, I1 } },
2545     { "shlA",   { Eb, I1 } },
2546     { "shrA",   { Eb, I1 } },
2547     { Bad_Opcode },
2548     { "sarA",   { Eb, I1 } },
2549   },
2550   /* REG_D1 */
2551   {
2552     { "rolQ",   { Ev, I1 } },
2553     { "rorQ",   { Ev, I1 } },
2554     { "rclQ",   { Ev, I1 } },
2555     { "rcrQ",   { Ev, I1 } },
2556     { "shlQ",   { Ev, I1 } },
2557     { "shrQ",   { Ev, I1 } },
2558     { Bad_Opcode },
2559     { "sarQ",   { Ev, I1 } },
2560   },
2561   /* REG_D2 */
2562   {
2563     { "rolA",   { Eb, CL } },
2564     { "rorA",   { Eb, CL } },
2565     { "rclA",   { Eb, CL } },
2566     { "rcrA",   { Eb, CL } },
2567     { "shlA",   { Eb, CL } },
2568     { "shrA",   { Eb, CL } },
2569     { Bad_Opcode },
2570     { "sarA",   { Eb, CL } },
2571   },
2572   /* REG_D3 */
2573   {
2574     { "rolQ",   { Ev, CL } },
2575     { "rorQ",   { Ev, CL } },
2576     { "rclQ",   { Ev, CL } },
2577     { "rcrQ",   { Ev, CL } },
2578     { "shlQ",   { Ev, CL } },
2579     { "shrQ",   { Ev, CL } },
2580     { Bad_Opcode },
2581     { "sarQ",   { Ev, CL } },
2582   },
2583   /* REG_F6 */
2584   {
2585     { "testA",  { Eb, Ib } },
2586     { Bad_Opcode },
2587     { "notA",   { Ebh1 } },
2588     { "negA",   { Ebh1 } },
2589     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2590     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2591     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2592     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2593   },
2594   /* REG_F7 */
2595   {
2596     { "testQ",  { Ev, Iv } },
2597     { Bad_Opcode },
2598     { "notQ",   { Evh1 } },
2599     { "negQ",   { Evh1 } },
2600     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2601     { "imulQ",  { Ev } },
2602     { "divQ",   { Ev } },
2603     { "idivQ",  { Ev } },
2604   },
2605   /* REG_FE */
2606   {
2607     { "incA",   { Ebh1 } },
2608     { "decA",   { Ebh1 } },
2609   },
2610   /* REG_FF */
2611   {
2612     { "incQ",   { Evh1 } },
2613     { "decQ",   { Evh1 } },
2614     { "call{T|}", { indirEv } },
2615     { "Jcall{T|}", { indirEp } },
2616     { "jmp{T|}", { indirEv } },
2617     { "Jjmp{T|}", { indirEp } },
2618     { "pushU",  { stackEv } },
2619     { Bad_Opcode },
2620   },
2621   /* REG_0F00 */
2622   {
2623     { "sldtD",  { Sv } },
2624     { "strD",   { Sv } },
2625     { "lldt",   { Ew } },
2626     { "ltr",    { Ew } },
2627     { "verr",   { Ew } },
2628     { "verw",   { Ew } },
2629     { Bad_Opcode },
2630     { Bad_Opcode },
2631   },
2632   /* REG_0F01 */
2633   {
2634     { MOD_TABLE (MOD_0F01_REG_0) },
2635     { MOD_TABLE (MOD_0F01_REG_1) },
2636     { MOD_TABLE (MOD_0F01_REG_2) },
2637     { MOD_TABLE (MOD_0F01_REG_3) },
2638     { "smswD",  { Sv } },
2639     { Bad_Opcode },
2640     { "lmsw",   { Ew } },
2641     { MOD_TABLE (MOD_0F01_REG_7) },
2642   },
2643   /* REG_0F0D */
2644   {
2645     { "prefetch",       { Mb } },
2646     { "prefetchw",      { Mb } },
2647   },
2648   /* REG_0F18 */
2649   {
2650     { MOD_TABLE (MOD_0F18_REG_0) },
2651     { MOD_TABLE (MOD_0F18_REG_1) },
2652     { MOD_TABLE (MOD_0F18_REG_2) },
2653     { MOD_TABLE (MOD_0F18_REG_3) },
2654   },
2655   /* REG_0F71 */
2656   {
2657     { Bad_Opcode },
2658     { Bad_Opcode },
2659     { MOD_TABLE (MOD_0F71_REG_2) },
2660     { Bad_Opcode },
2661     { MOD_TABLE (MOD_0F71_REG_4) },
2662     { Bad_Opcode },
2663     { MOD_TABLE (MOD_0F71_REG_6) },
2664   },
2665   /* REG_0F72 */
2666   {
2667     { Bad_Opcode },
2668     { Bad_Opcode },
2669     { MOD_TABLE (MOD_0F72_REG_2) },
2670     { Bad_Opcode },
2671     { MOD_TABLE (MOD_0F72_REG_4) },
2672     { Bad_Opcode },
2673     { MOD_TABLE (MOD_0F72_REG_6) },
2674   },
2675   /* REG_0F73 */
2676   {
2677     { Bad_Opcode },
2678     { Bad_Opcode },
2679     { MOD_TABLE (MOD_0F73_REG_2) },
2680     { MOD_TABLE (MOD_0F73_REG_3) },
2681     { Bad_Opcode },
2682     { Bad_Opcode },
2683     { MOD_TABLE (MOD_0F73_REG_6) },
2684     { MOD_TABLE (MOD_0F73_REG_7) },
2685   },
2686   /* REG_0FA6 */
2687   {
2688     { "montmul",        { { OP_0f07, 0 } } },
2689     { "xsha1",          { { OP_0f07, 0 } } },
2690     { "xsha256",        { { OP_0f07, 0 } } },
2691   },
2692   /* REG_0FA7 */
2693   {
2694     { "xstore-rng",     { { OP_0f07, 0 } } },
2695     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2696     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2697     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2698     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2699     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2700   },
2701   /* REG_0FAE */
2702   {
2703     { MOD_TABLE (MOD_0FAE_REG_0) },
2704     { MOD_TABLE (MOD_0FAE_REG_1) },
2705     { MOD_TABLE (MOD_0FAE_REG_2) },
2706     { MOD_TABLE (MOD_0FAE_REG_3) },
2707     { MOD_TABLE (MOD_0FAE_REG_4) },
2708     { MOD_TABLE (MOD_0FAE_REG_5) },
2709     { MOD_TABLE (MOD_0FAE_REG_6) },
2710     { MOD_TABLE (MOD_0FAE_REG_7) },
2711   },
2712   /* REG_0FBA */
2713   {
2714     { Bad_Opcode },
2715     { Bad_Opcode },
2716     { Bad_Opcode },
2717     { Bad_Opcode },
2718     { "btQ",    { Ev, Ib } },
2719     { "btsQ",   { Evh1, Ib } },
2720     { "btrQ",   { Evh1, Ib } },
2721     { "btcQ",   { Evh1, Ib } },
2722   },
2723   /* REG_0FC7 */
2724   {
2725     { Bad_Opcode },
2726     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2727     { Bad_Opcode },
2728     { Bad_Opcode },
2729     { Bad_Opcode },
2730     { Bad_Opcode },
2731     { MOD_TABLE (MOD_0FC7_REG_6) },
2732     { MOD_TABLE (MOD_0FC7_REG_7) },
2733   },
2734   /* REG_VEX_0F71 */
2735   {
2736     { Bad_Opcode },
2737     { Bad_Opcode },
2738     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2739     { Bad_Opcode },
2740     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2741     { Bad_Opcode },
2742     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2743   },
2744   /* REG_VEX_0F72 */
2745   {
2746     { Bad_Opcode },
2747     { Bad_Opcode },
2748     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2749     { Bad_Opcode },
2750     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2751     { Bad_Opcode },
2752     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2753   },
2754   /* REG_VEX_0F73 */
2755   {
2756     { Bad_Opcode },
2757     { Bad_Opcode },
2758     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2759     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2760     { Bad_Opcode },
2761     { Bad_Opcode },
2762     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2763     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2764   },
2765   /* REG_VEX_0FAE */
2766   {
2767     { Bad_Opcode },
2768     { Bad_Opcode },
2769     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2770     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2771   },
2772   /* REG_VEX_0F38F3 */
2773   {
2774     { Bad_Opcode },
2775     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2776     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2777     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2778   },
2779   /* REG_XOP_LWPCB */
2780   {
2781     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2782     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2783   },
2784   /* REG_XOP_LWP */
2785   {
2786     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2787     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2788   },
2789   /* REG_XOP_TBM_01 */
2790   {
2791     { Bad_Opcode },
2792     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
2793     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
2794     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
2795     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
2796     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
2797     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
2798     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2799   },
2800   /* REG_XOP_TBM_02 */
2801   {
2802     { Bad_Opcode },
2803     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2804     { Bad_Opcode },
2805     { Bad_Opcode },
2806     { Bad_Opcode },
2807     { Bad_Opcode },
2808     { "blci",   { { OP_LWP_E, 0 }, Ev } },
2809   },
2810 };
2811
2812 static const struct dis386 prefix_table[][4] = {
2813   /* PREFIX_90 */
2814   {
2815     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2816     { "pause", { XX } },
2817     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2818   },
2819
2820   /* PREFIX_0F10 */
2821   {
2822     { "movups", { XM, EXx } },
2823     { "movss",  { XM, EXd } },
2824     { "movupd", { XM, EXx } },
2825     { "movsd",  { XM, EXq } },
2826   },
2827
2828   /* PREFIX_0F11 */
2829   {
2830     { "movups", { EXxS, XM } },
2831     { "movss",  { EXdS, XM } },
2832     { "movupd", { EXxS, XM } },
2833     { "movsd",  { EXqS, XM } },
2834   },
2835
2836   /* PREFIX_0F12 */
2837   {
2838     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2839     { "movsldup", { XM, EXx } },
2840     { "movlpd", { XM, EXq } },
2841     { "movddup", { XM, EXq } },
2842   },
2843
2844   /* PREFIX_0F16 */
2845   {
2846     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2847     { "movshdup", { XM, EXx } },
2848     { "movhpd", { XM, EXq } },
2849   },
2850
2851   /* PREFIX_0F2A */
2852   {
2853     { "cvtpi2ps", { XM, EMCq } },
2854     { "cvtsi2ss%LQ", { XM, Ev } },
2855     { "cvtpi2pd", { XM, EMCq } },
2856     { "cvtsi2sd%LQ", { XM, Ev } },
2857   },
2858
2859   /* PREFIX_0F2B */
2860   {
2861     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2862     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2863     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2864     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2865   },
2866
2867   /* PREFIX_0F2C */
2868   {
2869     { "cvttps2pi", { MXC, EXq } },
2870     { "cvttss2siY", { Gv, EXd } },
2871     { "cvttpd2pi", { MXC, EXx } },
2872     { "cvttsd2siY", { Gv, EXq } },
2873   },
2874
2875   /* PREFIX_0F2D */
2876   {
2877     { "cvtps2pi", { MXC, EXq } },
2878     { "cvtss2siY", { Gv, EXd } },
2879     { "cvtpd2pi", { MXC, EXx } },
2880     { "cvtsd2siY", { Gv, EXq } },
2881   },
2882
2883   /* PREFIX_0F2E */
2884   {
2885     { "ucomiss",{ XM, EXd } },
2886     { Bad_Opcode },
2887     { "ucomisd",{ XM, EXq } },
2888   },
2889
2890   /* PREFIX_0F2F */
2891   {
2892     { "comiss", { XM, EXd } },
2893     { Bad_Opcode },
2894     { "comisd", { XM, EXq } },
2895   },
2896
2897   /* PREFIX_0F51 */
2898   {
2899     { "sqrtps", { XM, EXx } },
2900     { "sqrtss", { XM, EXd } },
2901     { "sqrtpd", { XM, EXx } },
2902     { "sqrtsd", { XM, EXq } },
2903   },
2904
2905   /* PREFIX_0F52 */
2906   {
2907     { "rsqrtps",{ XM, EXx } },
2908     { "rsqrtss",{ XM, EXd } },
2909   },
2910
2911   /* PREFIX_0F53 */
2912   {
2913     { "rcpps",  { XM, EXx } },
2914     { "rcpss",  { XM, EXd } },
2915   },
2916
2917   /* PREFIX_0F58 */
2918   {
2919     { "addps", { XM, EXx } },
2920     { "addss", { XM, EXd } },
2921     { "addpd", { XM, EXx } },
2922     { "addsd", { XM, EXq } },
2923   },
2924
2925   /* PREFIX_0F59 */
2926   {
2927     { "mulps",  { XM, EXx } },
2928     { "mulss",  { XM, EXd } },
2929     { "mulpd",  { XM, EXx } },
2930     { "mulsd",  { XM, EXq } },
2931   },
2932
2933   /* PREFIX_0F5A */
2934   {
2935     { "cvtps2pd", { XM, EXq } },
2936     { "cvtss2sd", { XM, EXd } },
2937     { "cvtpd2ps", { XM, EXx } },
2938     { "cvtsd2ss", { XM, EXq } },
2939   },
2940
2941   /* PREFIX_0F5B */
2942   {
2943     { "cvtdq2ps", { XM, EXx } },
2944     { "cvttps2dq", { XM, EXx } },
2945     { "cvtps2dq", { XM, EXx } },
2946   },
2947
2948   /* PREFIX_0F5C */
2949   {
2950     { "subps",  { XM, EXx } },
2951     { "subss",  { XM, EXd } },
2952     { "subpd",  { XM, EXx } },
2953     { "subsd",  { XM, EXq } },
2954   },
2955
2956   /* PREFIX_0F5D */
2957   {
2958     { "minps",  { XM, EXx } },
2959     { "minss",  { XM, EXd } },
2960     { "minpd",  { XM, EXx } },
2961     { "minsd",  { XM, EXq } },
2962   },
2963
2964   /* PREFIX_0F5E */
2965   {
2966     { "divps",  { XM, EXx } },
2967     { "divss",  { XM, EXd } },
2968     { "divpd",  { XM, EXx } },
2969     { "divsd",  { XM, EXq } },
2970   },
2971
2972   /* PREFIX_0F5F */
2973   {
2974     { "maxps",  { XM, EXx } },
2975     { "maxss",  { XM, EXd } },
2976     { "maxpd",  { XM, EXx } },
2977     { "maxsd",  { XM, EXq } },
2978   },
2979
2980   /* PREFIX_0F60 */
2981   {
2982     { "punpcklbw",{ MX, EMd } },
2983     { Bad_Opcode },
2984     { "punpcklbw",{ MX, EMx } },
2985   },
2986
2987   /* PREFIX_0F61 */
2988   {
2989     { "punpcklwd",{ MX, EMd } },
2990     { Bad_Opcode },
2991     { "punpcklwd",{ MX, EMx } },
2992   },
2993
2994   /* PREFIX_0F62 */
2995   {
2996     { "punpckldq",{ MX, EMd } },
2997     { Bad_Opcode },
2998     { "punpckldq",{ MX, EMx } },
2999   },
3000
3001   /* PREFIX_0F6C */
3002   {
3003     { Bad_Opcode },
3004     { Bad_Opcode },
3005     { "punpcklqdq", { XM, EXx } },
3006   },
3007
3008   /* PREFIX_0F6D */
3009   {
3010     { Bad_Opcode },
3011     { Bad_Opcode },
3012     { "punpckhqdq", { XM, EXx } },
3013   },
3014
3015   /* PREFIX_0F6F */
3016   {
3017     { "movq",   { MX, EM } },
3018     { "movdqu", { XM, EXx } },
3019     { "movdqa", { XM, EXx } },
3020   },
3021
3022   /* PREFIX_0F70 */
3023   {
3024     { "pshufw", { MX, EM, Ib } },
3025     { "pshufhw",{ XM, EXx, Ib } },
3026     { "pshufd", { XM, EXx, Ib } },
3027     { "pshuflw",{ XM, EXx, Ib } },
3028   },
3029
3030   /* PREFIX_0F73_REG_3 */
3031   {
3032     { Bad_Opcode },
3033     { Bad_Opcode },
3034     { "psrldq", { XS, Ib } },
3035   },
3036
3037   /* PREFIX_0F73_REG_7 */
3038   {
3039     { Bad_Opcode },
3040     { Bad_Opcode },
3041     { "pslldq", { XS, Ib } },
3042   },
3043
3044   /* PREFIX_0F78 */
3045   {
3046     {"vmread",  { Em, Gm } },
3047     { Bad_Opcode },
3048     {"extrq",   { XS, Ib, Ib } },
3049     {"insertq", { XM, XS, Ib, Ib } },
3050   },
3051
3052   /* PREFIX_0F79 */
3053   {
3054     {"vmwrite", { Gm, Em } },
3055     { Bad_Opcode },
3056     {"extrq",   { XM, XS } },
3057     {"insertq", { XM, XS } },
3058   },
3059
3060   /* PREFIX_0F7C */
3061   {
3062     { Bad_Opcode },
3063     { Bad_Opcode },
3064     { "haddpd", { XM, EXx } },
3065     { "haddps", { XM, EXx } },
3066   },
3067
3068   /* PREFIX_0F7D */
3069   {
3070     { Bad_Opcode },
3071     { Bad_Opcode },
3072     { "hsubpd", { XM, EXx } },
3073     { "hsubps", { XM, EXx } },
3074   },
3075
3076   /* PREFIX_0F7E */
3077   {
3078     { "movK",   { Edq, MX } },
3079     { "movq",   { XM, EXq } },
3080     { "movK",   { Edq, XM } },
3081   },
3082
3083   /* PREFIX_0F7F */
3084   {
3085     { "movq",   { EMS, MX } },
3086     { "movdqu", { EXxS, XM } },
3087     { "movdqa", { EXxS, XM } },
3088   },
3089
3090   /* PREFIX_0FAE_REG_0 */
3091   {
3092     { Bad_Opcode },
3093     { "rdfsbase", { Ev } },
3094   },
3095
3096   /* PREFIX_0FAE_REG_1 */
3097   {
3098     { Bad_Opcode },
3099     { "rdgsbase", { Ev } },
3100   },
3101
3102   /* PREFIX_0FAE_REG_2 */
3103   {
3104     { Bad_Opcode },
3105     { "wrfsbase", { Ev } },
3106   },
3107
3108   /* PREFIX_0FAE_REG_3 */
3109   {
3110     { Bad_Opcode },
3111     { "wrgsbase", { Ev } },
3112   },
3113
3114   /* PREFIX_0FB8 */
3115   {
3116     { Bad_Opcode },
3117     { "popcntS", { Gv, Ev } },
3118   },
3119
3120   /* PREFIX_0FBC */
3121   {
3122     { "bsfS",   { Gv, Ev } },
3123     { "tzcntS", { Gv, Ev } },
3124     { "bsfS",   { Gv, Ev } },
3125   },
3126
3127   /* PREFIX_0FBD */
3128   {
3129     { "bsrS",   { Gv, Ev } },
3130     { "lzcntS", { Gv, Ev } },
3131     { "bsrS",   { Gv, Ev } },
3132   },
3133
3134   /* PREFIX_0FC2 */
3135   {
3136     { "cmpps",  { XM, EXx, CMP } },
3137     { "cmpss",  { XM, EXd, CMP } },
3138     { "cmppd",  { XM, EXx, CMP } },
3139     { "cmpsd",  { XM, EXq, CMP } },
3140   },
3141
3142   /* PREFIX_0FC3 */
3143   {
3144     { "movntiS", { Ma, Gv } },
3145   },
3146
3147   /* PREFIX_0FC7_REG_6 */
3148   {
3149     { "vmptrld",{ Mq } },
3150     { "vmxon",  { Mq } },
3151     { "vmclear",{ Mq } },
3152   },
3153
3154   /* PREFIX_0FD0 */
3155   {
3156     { Bad_Opcode },
3157     { Bad_Opcode },
3158     { "addsubpd", { XM, EXx } },
3159     { "addsubps", { XM, EXx } },
3160   },
3161
3162   /* PREFIX_0FD6 */
3163   {
3164     { Bad_Opcode },
3165     { "movq2dq",{ XM, MS } },
3166     { "movq",   { EXqS, XM } },
3167     { "movdq2q",{ MX, XS } },
3168   },
3169
3170   /* PREFIX_0FE6 */
3171   {
3172     { Bad_Opcode },
3173     { "cvtdq2pd", { XM, EXq } },
3174     { "cvttpd2dq", { XM, EXx } },
3175     { "cvtpd2dq", { XM, EXx } },
3176   },
3177
3178   /* PREFIX_0FE7 */
3179   {
3180     { "movntq", { Mq, MX } },
3181     { Bad_Opcode },
3182     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3183   },
3184
3185   /* PREFIX_0FF0 */
3186   {
3187     { Bad_Opcode },
3188     { Bad_Opcode },
3189     { Bad_Opcode },
3190     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3191   },
3192
3193   /* PREFIX_0FF7 */
3194   {
3195     { "maskmovq", { MX, MS } },
3196     { Bad_Opcode },
3197     { "maskmovdqu", { XM, XS } },
3198   },
3199
3200   /* PREFIX_0F3810 */
3201   {
3202     { Bad_Opcode },
3203     { Bad_Opcode },
3204     { "pblendvb", { XM, EXx, XMM0 } },
3205   },
3206
3207   /* PREFIX_0F3814 */
3208   {
3209     { Bad_Opcode },
3210     { Bad_Opcode },
3211     { "blendvps", { XM, EXx, XMM0 } },
3212   },
3213
3214   /* PREFIX_0F3815 */
3215   {
3216     { Bad_Opcode },
3217     { Bad_Opcode },
3218     { "blendvpd", { XM, EXx, XMM0 } },
3219   },
3220
3221   /* PREFIX_0F3817 */
3222   {
3223     { Bad_Opcode },
3224     { Bad_Opcode },
3225     { "ptest",  { XM, EXx } },
3226   },
3227
3228   /* PREFIX_0F3820 */
3229   {
3230     { Bad_Opcode },
3231     { Bad_Opcode },
3232     { "pmovsxbw", { XM, EXq } },
3233   },
3234
3235   /* PREFIX_0F3821 */
3236   {
3237     { Bad_Opcode },
3238     { Bad_Opcode },
3239     { "pmovsxbd", { XM, EXd } },
3240   },
3241
3242   /* PREFIX_0F3822 */
3243   {
3244     { Bad_Opcode },
3245     { Bad_Opcode },
3246     { "pmovsxbq", { XM, EXw } },
3247   },
3248
3249   /* PREFIX_0F3823 */
3250   {
3251     { Bad_Opcode },
3252     { Bad_Opcode },
3253     { "pmovsxwd", { XM, EXq } },
3254   },
3255
3256   /* PREFIX_0F3824 */
3257   {
3258     { Bad_Opcode },
3259     { Bad_Opcode },
3260     { "pmovsxwq", { XM, EXd } },
3261   },
3262
3263   /* PREFIX_0F3825 */
3264   {
3265     { Bad_Opcode },
3266     { Bad_Opcode },
3267     { "pmovsxdq", { XM, EXq } },
3268   },
3269
3270   /* PREFIX_0F3828 */
3271   {
3272     { Bad_Opcode },
3273     { Bad_Opcode },
3274     { "pmuldq", { XM, EXx } },
3275   },
3276
3277   /* PREFIX_0F3829 */
3278   {
3279     { Bad_Opcode },
3280     { Bad_Opcode },
3281     { "pcmpeqq", { XM, EXx } },
3282   },
3283
3284   /* PREFIX_0F382A */
3285   {
3286     { Bad_Opcode },
3287     { Bad_Opcode },
3288     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3289   },
3290
3291   /* PREFIX_0F382B */
3292   {
3293     { Bad_Opcode },
3294     { Bad_Opcode },
3295     { "packusdw", { XM, EXx } },
3296   },
3297
3298   /* PREFIX_0F3830 */
3299   {
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { "pmovzxbw", { XM, EXq } },
3303   },
3304
3305   /* PREFIX_0F3831 */
3306   {
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { "pmovzxbd", { XM, EXd } },
3310   },
3311
3312   /* PREFIX_0F3832 */
3313   {
3314     { Bad_Opcode },
3315     { Bad_Opcode },
3316     { "pmovzxbq", { XM, EXw } },
3317   },
3318
3319   /* PREFIX_0F3833 */
3320   {
3321     { Bad_Opcode },
3322     { Bad_Opcode },
3323     { "pmovzxwd", { XM, EXq } },
3324   },
3325
3326   /* PREFIX_0F3834 */
3327   {
3328     { Bad_Opcode },
3329     { Bad_Opcode },
3330     { "pmovzxwq", { XM, EXd } },
3331   },
3332
3333   /* PREFIX_0F3835 */
3334   {
3335     { Bad_Opcode },
3336     { Bad_Opcode },
3337     { "pmovzxdq", { XM, EXq } },
3338   },
3339
3340   /* PREFIX_0F3837 */
3341   {
3342     { Bad_Opcode },
3343     { Bad_Opcode },
3344     { "pcmpgtq", { XM, EXx } },
3345   },
3346
3347   /* PREFIX_0F3838 */
3348   {
3349     { Bad_Opcode },
3350     { Bad_Opcode },
3351     { "pminsb", { XM, EXx } },
3352   },
3353
3354   /* PREFIX_0F3839 */
3355   {
3356     { Bad_Opcode },
3357     { Bad_Opcode },
3358     { "pminsd", { XM, EXx } },
3359   },
3360
3361   /* PREFIX_0F383A */
3362   {
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { "pminuw", { XM, EXx } },
3366   },
3367
3368   /* PREFIX_0F383B */
3369   {
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { "pminud", { XM, EXx } },
3373   },
3374
3375   /* PREFIX_0F383C */
3376   {
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { "pmaxsb", { XM, EXx } },
3380   },
3381
3382   /* PREFIX_0F383D */
3383   {
3384     { Bad_Opcode },
3385     { Bad_Opcode },
3386     { "pmaxsd", { XM, EXx } },
3387   },
3388
3389   /* PREFIX_0F383E */
3390   {
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393     { "pmaxuw", { XM, EXx } },
3394   },
3395
3396   /* PREFIX_0F383F */
3397   {
3398     { Bad_Opcode },
3399     { Bad_Opcode },
3400     { "pmaxud", { XM, EXx } },
3401   },
3402
3403   /* PREFIX_0F3840 */
3404   {
3405     { Bad_Opcode },
3406     { Bad_Opcode },
3407     { "pmulld", { XM, EXx } },
3408   },
3409
3410   /* PREFIX_0F3841 */
3411   {
3412     { Bad_Opcode },
3413     { Bad_Opcode },
3414     { "phminposuw", { XM, EXx } },
3415   },
3416
3417   /* PREFIX_0F3880 */
3418   {
3419     { Bad_Opcode },
3420     { Bad_Opcode },
3421     { "invept", { Gm, Mo } },
3422   },
3423
3424   /* PREFIX_0F3881 */
3425   {
3426     { Bad_Opcode },
3427     { Bad_Opcode },
3428     { "invvpid", { Gm, Mo } },
3429   },
3430
3431   /* PREFIX_0F3882 */
3432   {
3433     { Bad_Opcode },
3434     { Bad_Opcode },
3435     { "invpcid", { Gm, M } },
3436   },
3437
3438   /* PREFIX_0F38DB */
3439   {
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { "aesimc", { XM, EXx } },
3443   },
3444
3445   /* PREFIX_0F38DC */
3446   {
3447     { Bad_Opcode },
3448     { Bad_Opcode },
3449     { "aesenc", { XM, EXx } },
3450   },
3451
3452   /* PREFIX_0F38DD */
3453   {
3454     { Bad_Opcode },
3455     { Bad_Opcode },
3456     { "aesenclast", { XM, EXx } },
3457   },
3458
3459   /* PREFIX_0F38DE */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { "aesdec", { XM, EXx } },
3464   },
3465
3466   /* PREFIX_0F38DF */
3467   {
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { "aesdeclast", { XM, EXx } },
3471   },
3472
3473   /* PREFIX_0F38F0 */
3474   {
3475     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3476     { Bad_Opcode },
3477     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3478     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3479   },
3480
3481   /* PREFIX_0F38F1 */
3482   {
3483     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3484     { Bad_Opcode },
3485     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3486     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3487   },
3488
3489   /* PREFIX_0F38F6 */
3490   {
3491     { Bad_Opcode },
3492     { "adoxS",  { Gdq, Edq} },
3493     { "adcxS",  { Gdq, Edq} },
3494     { Bad_Opcode },
3495   },
3496
3497   /* PREFIX_0F3A08 */
3498   {
3499     { Bad_Opcode },
3500     { Bad_Opcode },
3501     { "roundps", { XM, EXx, Ib } },
3502   },
3503
3504   /* PREFIX_0F3A09 */
3505   {
3506     { Bad_Opcode },
3507     { Bad_Opcode },
3508     { "roundpd", { XM, EXx, Ib } },
3509   },
3510
3511   /* PREFIX_0F3A0A */
3512   {
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { "roundss", { XM, EXd, Ib } },
3516   },
3517
3518   /* PREFIX_0F3A0B */
3519   {
3520     { Bad_Opcode },
3521     { Bad_Opcode },
3522     { "roundsd", { XM, EXq, Ib } },
3523   },
3524
3525   /* PREFIX_0F3A0C */
3526   {
3527     { Bad_Opcode },
3528     { Bad_Opcode },
3529     { "blendps", { XM, EXx, Ib } },
3530   },
3531
3532   /* PREFIX_0F3A0D */
3533   {
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { "blendpd", { XM, EXx, Ib } },
3537   },
3538
3539   /* PREFIX_0F3A0E */
3540   {
3541     { Bad_Opcode },
3542     { Bad_Opcode },
3543     { "pblendw", { XM, EXx, Ib } },
3544   },
3545
3546   /* PREFIX_0F3A14 */
3547   {
3548     { Bad_Opcode },
3549     { Bad_Opcode },
3550     { "pextrb", { Edqb, XM, Ib } },
3551   },
3552
3553   /* PREFIX_0F3A15 */
3554   {
3555     { Bad_Opcode },
3556     { Bad_Opcode },
3557     { "pextrw", { Edqw, XM, Ib } },
3558   },
3559
3560   /* PREFIX_0F3A16 */
3561   {
3562     { Bad_Opcode },
3563     { Bad_Opcode },
3564     { "pextrK", { Edq, XM, Ib } },
3565   },
3566
3567   /* PREFIX_0F3A17 */
3568   {
3569     { Bad_Opcode },
3570     { Bad_Opcode },
3571     { "extractps", { Edqd, XM, Ib } },
3572   },
3573
3574   /* PREFIX_0F3A20 */
3575   {
3576     { Bad_Opcode },
3577     { Bad_Opcode },
3578     { "pinsrb", { XM, Edqb, Ib } },
3579   },
3580
3581   /* PREFIX_0F3A21 */
3582   {
3583     { Bad_Opcode },
3584     { Bad_Opcode },
3585     { "insertps", { XM, EXd, Ib } },
3586   },
3587
3588   /* PREFIX_0F3A22 */
3589   {
3590     { Bad_Opcode },
3591     { Bad_Opcode },
3592     { "pinsrK", { XM, Edq, Ib } },
3593   },
3594
3595   /* PREFIX_0F3A40 */
3596   {
3597     { Bad_Opcode },
3598     { Bad_Opcode },
3599     { "dpps",   { XM, EXx, Ib } },
3600   },
3601
3602   /* PREFIX_0F3A41 */
3603   {
3604     { Bad_Opcode },
3605     { Bad_Opcode },
3606     { "dppd",   { XM, EXx, Ib } },
3607   },
3608
3609   /* PREFIX_0F3A42 */
3610   {
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613     { "mpsadbw", { XM, EXx, Ib } },
3614   },
3615
3616   /* PREFIX_0F3A44 */
3617   {
3618     { Bad_Opcode },
3619     { Bad_Opcode },
3620     { "pclmulqdq", { XM, EXx, PCLMUL } },
3621   },
3622
3623   /* PREFIX_0F3A60 */
3624   {
3625     { Bad_Opcode },
3626     { Bad_Opcode },
3627     { "pcmpestrm", { XM, EXx, Ib } },
3628   },
3629
3630   /* PREFIX_0F3A61 */
3631   {
3632     { Bad_Opcode },
3633     { Bad_Opcode },
3634     { "pcmpestri", { XM, EXx, Ib } },
3635   },
3636
3637   /* PREFIX_0F3A62 */
3638   {
3639     { Bad_Opcode },
3640     { Bad_Opcode },
3641     { "pcmpistrm", { XM, EXx, Ib } },
3642   },
3643
3644   /* PREFIX_0F3A63 */
3645   {
3646     { Bad_Opcode },
3647     { Bad_Opcode },
3648     { "pcmpistri", { XM, EXx, Ib } },
3649   },
3650
3651   /* PREFIX_0F3ADF */
3652   {
3653     { Bad_Opcode },
3654     { Bad_Opcode },
3655     { "aeskeygenassist", { XM, EXx, Ib } },
3656   },
3657
3658   /* PREFIX_VEX_0F10 */
3659   {
3660     { VEX_W_TABLE (VEX_W_0F10_P_0) },
3661     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3662     { VEX_W_TABLE (VEX_W_0F10_P_2) },
3663     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3664   },
3665
3666   /* PREFIX_VEX_0F11 */
3667   {
3668     { VEX_W_TABLE (VEX_W_0F11_P_0) },
3669     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3670     { VEX_W_TABLE (VEX_W_0F11_P_2) },
3671     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3672   },
3673
3674   /* PREFIX_VEX_0F12 */
3675   {
3676     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3677     { VEX_W_TABLE (VEX_W_0F12_P_1) },
3678     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3679     { VEX_W_TABLE (VEX_W_0F12_P_3) },
3680   },
3681
3682   /* PREFIX_VEX_0F16 */
3683   {
3684     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3685     { VEX_W_TABLE (VEX_W_0F16_P_1) },
3686     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3687   },
3688
3689   /* PREFIX_VEX_0F2A */
3690   {
3691     { Bad_Opcode },
3692     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3693     { Bad_Opcode },
3694     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3695   },
3696
3697   /* PREFIX_VEX_0F2C */
3698   {
3699     { Bad_Opcode },
3700     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3701     { Bad_Opcode },
3702     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3703   },
3704
3705   /* PREFIX_VEX_0F2D */
3706   {
3707     { Bad_Opcode },
3708     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3709     { Bad_Opcode },
3710     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3711   },
3712
3713   /* PREFIX_VEX_0F2E */
3714   {
3715     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3716     { Bad_Opcode },
3717     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3718   },
3719
3720   /* PREFIX_VEX_0F2F */
3721   {
3722     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3723     { Bad_Opcode },
3724     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3725   },
3726
3727   /* PREFIX_VEX_0F51 */
3728   {
3729     { VEX_W_TABLE (VEX_W_0F51_P_0) },
3730     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3731     { VEX_W_TABLE (VEX_W_0F51_P_2) },
3732     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3733   },
3734
3735   /* PREFIX_VEX_0F52 */
3736   {
3737     { VEX_W_TABLE (VEX_W_0F52_P_0) },
3738     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3739   },
3740
3741   /* PREFIX_VEX_0F53 */
3742   {
3743     { VEX_W_TABLE (VEX_W_0F53_P_0) },
3744     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3745   },
3746
3747   /* PREFIX_VEX_0F58 */
3748   {
3749     { VEX_W_TABLE (VEX_W_0F58_P_0) },
3750     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3751     { VEX_W_TABLE (VEX_W_0F58_P_2) },
3752     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3753   },
3754
3755   /* PREFIX_VEX_0F59 */
3756   {
3757     { VEX_W_TABLE (VEX_W_0F59_P_0) },
3758     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3759     { VEX_W_TABLE (VEX_W_0F59_P_2) },
3760     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3761   },
3762
3763   /* PREFIX_VEX_0F5A */
3764   {
3765     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3766     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3767     { "vcvtpd2ps%XY", { XMM, EXx } },
3768     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3769   },
3770
3771   /* PREFIX_VEX_0F5B */
3772   {
3773     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3774     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3775     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3776   },
3777
3778   /* PREFIX_VEX_0F5C */
3779   {
3780     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3781     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3782     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3783     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3784   },
3785
3786   /* PREFIX_VEX_0F5D */
3787   {
3788     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3789     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3790     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3791     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3792   },
3793
3794   /* PREFIX_VEX_0F5E */
3795   {
3796     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3797     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3798     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3799     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3800   },
3801
3802   /* PREFIX_VEX_0F5F */
3803   {
3804     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3805     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3806     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3807     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3808   },
3809
3810   /* PREFIX_VEX_0F60 */
3811   {
3812     { Bad_Opcode },
3813     { Bad_Opcode },
3814     { VEX_W_TABLE (VEX_W_0F60_P_2) },
3815   },
3816
3817   /* PREFIX_VEX_0F61 */
3818   {
3819     { Bad_Opcode },
3820     { Bad_Opcode },
3821     { VEX_W_TABLE (VEX_W_0F61_P_2) },
3822   },
3823
3824   /* PREFIX_VEX_0F62 */
3825   {
3826     { Bad_Opcode },
3827     { Bad_Opcode },
3828     { VEX_W_TABLE (VEX_W_0F62_P_2) },
3829   },
3830
3831   /* PREFIX_VEX_0F63 */
3832   {
3833     { Bad_Opcode },
3834     { Bad_Opcode },
3835     { VEX_W_TABLE (VEX_W_0F63_P_2) },
3836   },
3837
3838   /* PREFIX_VEX_0F64 */
3839   {
3840     { Bad_Opcode },
3841     { Bad_Opcode },
3842     { VEX_W_TABLE (VEX_W_0F64_P_2) },
3843   },
3844
3845   /* PREFIX_VEX_0F65 */
3846   {
3847     { Bad_Opcode },
3848     { Bad_Opcode },
3849     { VEX_W_TABLE (VEX_W_0F65_P_2) },
3850   },
3851
3852   /* PREFIX_VEX_0F66 */
3853   {
3854     { Bad_Opcode },
3855     { Bad_Opcode },
3856     { VEX_W_TABLE (VEX_W_0F66_P_2) },
3857   },
3858
3859   /* PREFIX_VEX_0F67 */
3860   {
3861     { Bad_Opcode },
3862     { Bad_Opcode },
3863     { VEX_W_TABLE (VEX_W_0F67_P_2) },
3864   },
3865
3866   /* PREFIX_VEX_0F68 */
3867   {
3868     { Bad_Opcode },
3869     { Bad_Opcode },
3870     { VEX_W_TABLE (VEX_W_0F68_P_2) },
3871   },
3872
3873   /* PREFIX_VEX_0F69 */
3874   {
3875     { Bad_Opcode },
3876     { Bad_Opcode },
3877     { VEX_W_TABLE (VEX_W_0F69_P_2) },
3878   },
3879
3880   /* PREFIX_VEX_0F6A */
3881   {
3882     { Bad_Opcode },
3883     { Bad_Opcode },
3884     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
3885   },
3886
3887   /* PREFIX_VEX_0F6B */
3888   {
3889     { Bad_Opcode },
3890     { Bad_Opcode },
3891     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
3892   },
3893
3894   /* PREFIX_VEX_0F6C */
3895   {
3896     { Bad_Opcode },
3897     { Bad_Opcode },
3898     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
3899   },
3900
3901   /* PREFIX_VEX_0F6D */
3902   {
3903     { Bad_Opcode },
3904     { Bad_Opcode },
3905     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
3906   },
3907
3908   /* PREFIX_VEX_0F6E */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3913   },
3914
3915   /* PREFIX_VEX_0F6F */
3916   {
3917     { Bad_Opcode },
3918     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3919     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3920   },
3921
3922   /* PREFIX_VEX_0F70 */
3923   {
3924     { Bad_Opcode },
3925     { VEX_W_TABLE (VEX_W_0F70_P_1) },
3926     { VEX_W_TABLE (VEX_W_0F70_P_2) },
3927     { VEX_W_TABLE (VEX_W_0F70_P_3) },
3928   },
3929
3930   /* PREFIX_VEX_0F71_REG_2 */
3931   {
3932     { Bad_Opcode },
3933     { Bad_Opcode },
3934     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
3935   },
3936
3937   /* PREFIX_VEX_0F71_REG_4 */
3938   {
3939     { Bad_Opcode },
3940     { Bad_Opcode },
3941     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
3942   },
3943
3944   /* PREFIX_VEX_0F71_REG_6 */
3945   {
3946     { Bad_Opcode },
3947     { Bad_Opcode },
3948     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
3949   },
3950
3951   /* PREFIX_VEX_0F72_REG_2 */
3952   {
3953     { Bad_Opcode },
3954     { Bad_Opcode },
3955     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
3956   },
3957
3958   /* PREFIX_VEX_0F72_REG_4 */
3959   {
3960     { Bad_Opcode },
3961     { Bad_Opcode },
3962     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
3963   },
3964
3965   /* PREFIX_VEX_0F72_REG_6 */
3966   {
3967     { Bad_Opcode },
3968     { Bad_Opcode },
3969     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
3970   },
3971
3972   /* PREFIX_VEX_0F73_REG_2 */
3973   {
3974     { Bad_Opcode },
3975     { Bad_Opcode },
3976     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
3977   },
3978
3979   /* PREFIX_VEX_0F73_REG_3 */
3980   {
3981     { Bad_Opcode },
3982     { Bad_Opcode },
3983     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
3984   },
3985
3986   /* PREFIX_VEX_0F73_REG_6 */
3987   {
3988     { Bad_Opcode },
3989     { Bad_Opcode },
3990     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
3991   },
3992
3993   /* PREFIX_VEX_0F73_REG_7 */
3994   {
3995     { Bad_Opcode },
3996     { Bad_Opcode },
3997     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
3998   },
3999
4000   /* PREFIX_VEX_0F74 */
4001   {
4002     { Bad_Opcode },
4003     { Bad_Opcode },
4004     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4005   },
4006
4007   /* PREFIX_VEX_0F75 */
4008   {
4009     { Bad_Opcode },
4010     { Bad_Opcode },
4011     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4012   },
4013
4014   /* PREFIX_VEX_0F76 */
4015   {
4016     { Bad_Opcode },
4017     { Bad_Opcode },
4018     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4019   },
4020
4021   /* PREFIX_VEX_0F77 */
4022   {
4023     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4024   },
4025
4026   /* PREFIX_VEX_0F7C */
4027   {
4028     { Bad_Opcode },
4029     { Bad_Opcode },
4030     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4031     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4032   },
4033
4034   /* PREFIX_VEX_0F7D */
4035   {
4036     { Bad_Opcode },
4037     { Bad_Opcode },
4038     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4039     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4040   },
4041
4042   /* PREFIX_VEX_0F7E */
4043   {
4044     { Bad_Opcode },
4045     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4046     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4047   },
4048
4049   /* PREFIX_VEX_0F7F */
4050   {
4051     { Bad_Opcode },
4052     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4053     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4054   },
4055
4056   /* PREFIX_VEX_0FC2 */
4057   {
4058     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4059     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4060     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4061     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4062   },
4063
4064   /* PREFIX_VEX_0FC4 */
4065   {
4066     { Bad_Opcode },
4067     { Bad_Opcode },
4068     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4069   },
4070
4071   /* PREFIX_VEX_0FC5 */
4072   {
4073     { Bad_Opcode },
4074     { Bad_Opcode },
4075     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4076   },
4077
4078   /* PREFIX_VEX_0FD0 */
4079   {
4080     { Bad_Opcode },
4081     { Bad_Opcode },
4082     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4083     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4084   },
4085
4086   /* PREFIX_VEX_0FD1 */
4087   {
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4091   },
4092
4093   /* PREFIX_VEX_0FD2 */
4094   {
4095     { Bad_Opcode },
4096     { Bad_Opcode },
4097     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4098   },
4099
4100   /* PREFIX_VEX_0FD3 */
4101   {
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4105   },
4106
4107   /* PREFIX_VEX_0FD4 */
4108   {
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4112   },
4113
4114   /* PREFIX_VEX_0FD5 */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4119   },
4120
4121   /* PREFIX_VEX_0FD6 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4126   },
4127
4128   /* PREFIX_VEX_0FD7 */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4133   },
4134
4135   /* PREFIX_VEX_0FD8 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4140   },
4141
4142   /* PREFIX_VEX_0FD9 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4147   },
4148
4149   /* PREFIX_VEX_0FDA */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4154   },
4155
4156   /* PREFIX_VEX_0FDB */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4161   },
4162
4163   /* PREFIX_VEX_0FDC */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4168   },
4169
4170   /* PREFIX_VEX_0FDD */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4175   },
4176
4177   /* PREFIX_VEX_0FDE */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4182   },
4183
4184   /* PREFIX_VEX_0FDF */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4189   },
4190
4191   /* PREFIX_VEX_0FE0 */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4196   },
4197
4198   /* PREFIX_VEX_0FE1 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4203   },
4204
4205   /* PREFIX_VEX_0FE2 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4210   },
4211
4212   /* PREFIX_VEX_0FE3 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4217   },
4218
4219   /* PREFIX_VEX_0FE4 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4224   },
4225
4226   /* PREFIX_VEX_0FE5 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4231   },
4232
4233   /* PREFIX_VEX_0FE6 */
4234   {
4235     { Bad_Opcode },
4236     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4237     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4238     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4239   },
4240
4241   /* PREFIX_VEX_0FE7 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4246   },
4247
4248   /* PREFIX_VEX_0FE8 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4253   },
4254
4255   /* PREFIX_VEX_0FE9 */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
4260   },
4261
4262   /* PREFIX_VEX_0FEA */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
4267   },
4268
4269   /* PREFIX_VEX_0FEB */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
4274   },
4275
4276   /* PREFIX_VEX_0FEC */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
4281   },
4282
4283   /* PREFIX_VEX_0FED */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { VEX_W_TABLE (VEX_W_0FED_P_2) },
4288   },
4289
4290   /* PREFIX_VEX_0FEE */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
4295   },
4296
4297   /* PREFIX_VEX_0FEF */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
4302   },
4303
4304   /* PREFIX_VEX_0FF0 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4310   },
4311
4312   /* PREFIX_VEX_0FF1 */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
4317   },
4318
4319   /* PREFIX_VEX_0FF2 */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
4324   },
4325
4326   /* PREFIX_VEX_0FF3 */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
4331   },
4332
4333   /* PREFIX_VEX_0FF4 */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
4338   },
4339
4340   /* PREFIX_VEX_0FF5 */
4341   {
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
4345   },
4346
4347   /* PREFIX_VEX_0FF6 */
4348   {
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
4352   },
4353
4354   /* PREFIX_VEX_0FF7 */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4359   },
4360
4361   /* PREFIX_VEX_0FF8 */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
4366   },
4367
4368   /* PREFIX_VEX_0FF9 */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
4373   },
4374
4375   /* PREFIX_VEX_0FFA */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
4380   },
4381
4382   /* PREFIX_VEX_0FFB */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
4387   },
4388
4389   /* PREFIX_VEX_0FFC */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
4394   },
4395
4396   /* PREFIX_VEX_0FFD */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
4401   },
4402
4403   /* PREFIX_VEX_0FFE */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
4408   },
4409
4410   /* PREFIX_VEX_0F3800 */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
4415   },
4416
4417   /* PREFIX_VEX_0F3801 */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
4422   },
4423
4424   /* PREFIX_VEX_0F3802 */
4425   {
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
4429   },
4430
4431   /* PREFIX_VEX_0F3803 */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
4436   },
4437
4438   /* PREFIX_VEX_0F3804 */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
4443   },
4444
4445   /* PREFIX_VEX_0F3805 */
4446   {
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
4450   },
4451
4452   /* PREFIX_VEX_0F3806 */
4453   {
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
4457   },
4458
4459   /* PREFIX_VEX_0F3807 */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
4464   },
4465
4466   /* PREFIX_VEX_0F3808 */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
4471   },
4472
4473   /* PREFIX_VEX_0F3809 */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
4478   },
4479
4480   /* PREFIX_VEX_0F380A */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
4485   },
4486
4487   /* PREFIX_VEX_0F380B */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
4492   },
4493
4494   /* PREFIX_VEX_0F380C */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4499   },
4500
4501   /* PREFIX_VEX_0F380D */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4506   },
4507
4508   /* PREFIX_VEX_0F380E */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4513   },
4514
4515   /* PREFIX_VEX_0F380F */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4520   },
4521
4522   /* PREFIX_VEX_0F3813 */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "vcvtph2ps", { XM, EXxmmq } },
4527   },
4528
4529   /* PREFIX_VEX_0F3816 */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
4534   },
4535
4536   /* PREFIX_VEX_0F3817 */
4537   {
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4541   },
4542
4543   /* PREFIX_VEX_0F3818 */
4544   {
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
4548   },
4549
4550   /* PREFIX_VEX_0F3819 */
4551   {
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
4555   },
4556
4557   /* PREFIX_VEX_0F381A */
4558   {
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4562   },
4563
4564   /* PREFIX_VEX_0F381C */
4565   {
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
4569   },
4570
4571   /* PREFIX_VEX_0F381D */
4572   {
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
4576   },
4577
4578   /* PREFIX_VEX_0F381E */
4579   {
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
4583   },
4584
4585   /* PREFIX_VEX_0F3820 */
4586   {
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
4590   },
4591
4592   /* PREFIX_VEX_0F3821 */
4593   {
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
4597   },
4598
4599   /* PREFIX_VEX_0F3822 */
4600   {
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
4604   },
4605
4606   /* PREFIX_VEX_0F3823 */
4607   {
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
4611   },
4612
4613   /* PREFIX_VEX_0F3824 */
4614   {
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
4618   },
4619
4620   /* PREFIX_VEX_0F3825 */
4621   {
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
4625   },
4626
4627   /* PREFIX_VEX_0F3828 */
4628   {
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
4632   },
4633
4634   /* PREFIX_VEX_0F3829 */
4635   {
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
4639   },
4640
4641   /* PREFIX_VEX_0F382A */
4642   {
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4646   },
4647
4648   /* PREFIX_VEX_0F382B */
4649   {
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
4653   },
4654
4655   /* PREFIX_VEX_0F382C */
4656   {
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4660   },
4661
4662   /* PREFIX_VEX_0F382D */
4663   {
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4667   },
4668
4669   /* PREFIX_VEX_0F382E */
4670   {
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4674   },
4675
4676   /* PREFIX_VEX_0F382F */
4677   {
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4681   },
4682
4683   /* PREFIX_VEX_0F3830 */
4684   {
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
4688   },
4689
4690   /* PREFIX_VEX_0F3831 */
4691   {
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
4695   },
4696
4697   /* PREFIX_VEX_0F3832 */
4698   {
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
4702   },
4703
4704   /* PREFIX_VEX_0F3833 */
4705   {
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
4709   },
4710
4711   /* PREFIX_VEX_0F3834 */
4712   {
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
4716   },
4717
4718   /* PREFIX_VEX_0F3835 */
4719   {
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
4723   },
4724
4725   /* PREFIX_VEX_0F3836 */
4726   {
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
4730   },
4731
4732   /* PREFIX_VEX_0F3837 */
4733   {
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
4737   },
4738
4739   /* PREFIX_VEX_0F3838 */
4740   {
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
4744   },
4745
4746   /* PREFIX_VEX_0F3839 */
4747   {
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
4751   },
4752
4753   /* PREFIX_VEX_0F383A */
4754   {
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
4758   },
4759
4760   /* PREFIX_VEX_0F383B */
4761   {
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
4765   },
4766
4767   /* PREFIX_VEX_0F383C */
4768   {
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
4772   },
4773
4774   /* PREFIX_VEX_0F383D */
4775   {
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
4779   },
4780
4781   /* PREFIX_VEX_0F383E */
4782   {
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
4786   },
4787
4788   /* PREFIX_VEX_0F383F */
4789   {
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
4793   },
4794
4795   /* PREFIX_VEX_0F3840 */
4796   {
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
4800   },
4801
4802   /* PREFIX_VEX_0F3841 */
4803   {
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4807   },
4808
4809   /* PREFIX_VEX_0F3845 */
4810   {
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { "vpsrlv%LW", { XM, Vex, EXx } },
4814   },
4815
4816   /* PREFIX_VEX_0F3846 */
4817   {
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
4821   },
4822
4823   /* PREFIX_VEX_0F3847 */
4824   {
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { "vpsllv%LW", { XM, Vex, EXx } },
4828   },
4829
4830   /* PREFIX_VEX_0F3858 */
4831   {
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
4835   },
4836
4837   /* PREFIX_VEX_0F3859 */
4838   {
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
4842   },
4843
4844   /* PREFIX_VEX_0F385A */
4845   {
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
4849   },
4850
4851   /* PREFIX_VEX_0F3878 */
4852   {
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
4856   },
4857
4858   /* PREFIX_VEX_0F3879 */
4859   {
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
4863   },
4864
4865   /* PREFIX_VEX_0F388C */
4866   {
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
4870   },
4871
4872   /* PREFIX_VEX_0F388E */
4873   {
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
4877   },
4878
4879   /* PREFIX_VEX_0F3890 */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
4884   },
4885
4886   /* PREFIX_VEX_0F3891 */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4891   },
4892
4893   /* PREFIX_VEX_0F3892 */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
4898   },
4899
4900   /* PREFIX_VEX_0F3893 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4905   },
4906
4907   /* PREFIX_VEX_0F3896 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4912   },
4913
4914   /* PREFIX_VEX_0F3897 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4919   },
4920
4921   /* PREFIX_VEX_0F3898 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { "vfmadd132p%XW", { XM, Vex, EXx } },
4926   },
4927
4928   /* PREFIX_VEX_0F3899 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4933   },
4934
4935   /* PREFIX_VEX_0F389A */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { "vfmsub132p%XW", { XM, Vex, EXx } },
4940   },
4941
4942   /* PREFIX_VEX_0F389B */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4947   },
4948
4949   /* PREFIX_VEX_0F389C */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4954   },
4955
4956   /* PREFIX_VEX_0F389D */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4961   },
4962
4963   /* PREFIX_VEX_0F389E */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4968   },
4969
4970   /* PREFIX_VEX_0F389F */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4975   },
4976
4977   /* PREFIX_VEX_0F38A6 */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4982     { Bad_Opcode },
4983   },
4984
4985   /* PREFIX_VEX_0F38A7 */
4986   {
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4990   },
4991
4992   /* PREFIX_VEX_0F38A8 */
4993   {
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { "vfmadd213p%XW", { XM, Vex, EXx } },
4997   },
4998
4999   /* PREFIX_VEX_0F38A9 */
5000   {
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5004   },
5005
5006   /* PREFIX_VEX_0F38AA */
5007   {
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { "vfmsub213p%XW", { XM, Vex, EXx } },
5011   },
5012
5013   /* PREFIX_VEX_0F38AB */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5018   },
5019
5020   /* PREFIX_VEX_0F38AC */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5025   },
5026
5027   /* PREFIX_VEX_0F38AD */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5032   },
5033
5034   /* PREFIX_VEX_0F38AE */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5039   },
5040
5041   /* PREFIX_VEX_0F38AF */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5046   },
5047
5048   /* PREFIX_VEX_0F38B6 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5053   },
5054
5055   /* PREFIX_VEX_0F38B7 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5060   },
5061
5062   /* PREFIX_VEX_0F38B8 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { "vfmadd231p%XW", { XM, Vex, EXx } },
5067   },
5068
5069   /* PREFIX_VEX_0F38B9 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5074   },
5075
5076   /* PREFIX_VEX_0F38BA */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { "vfmsub231p%XW", { XM, Vex, EXx } },
5081   },
5082
5083   /* PREFIX_VEX_0F38BB */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5088   },
5089
5090   /* PREFIX_VEX_0F38BC */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5095   },
5096
5097   /* PREFIX_VEX_0F38BD */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5102   },
5103
5104   /* PREFIX_VEX_0F38BE */
5105   {
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5109   },
5110
5111   /* PREFIX_VEX_0F38BF */
5112   {
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5116   },
5117
5118   /* PREFIX_VEX_0F38DB */
5119   {
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0F38DC */
5126   {
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0F38DD */
5133   {
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F38DE */
5140   {
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0F38DF */
5147   {
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5151   },
5152
5153   /* PREFIX_VEX_0F38F2 */
5154   {
5155     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5156   },
5157
5158   /* PREFIX_VEX_0F38F3_REG_1 */
5159   {
5160     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5161   },
5162
5163   /* PREFIX_VEX_0F38F3_REG_2 */
5164   {
5165     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5166   },
5167
5168   /* PREFIX_VEX_0F38F3_REG_3 */
5169   {
5170     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5171   },
5172
5173   /* PREFIX_VEX_0F38F5 */
5174   {
5175     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5176     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5177     { Bad_Opcode },
5178     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5179   },
5180
5181   /* PREFIX_VEX_0F38F6 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5187   },
5188
5189   /* PREFIX_VEX_0F38F7 */
5190   {
5191     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5192     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5193     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5194     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5195   },
5196
5197   /* PREFIX_VEX_0F3A00 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5202   },
5203
5204   /* PREFIX_VEX_0F3A01 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5209   },
5210
5211   /* PREFIX_VEX_0F3A02 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5216   },
5217
5218   /* PREFIX_VEX_0F3A04 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5223   },
5224
5225   /* PREFIX_VEX_0F3A05 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0F3A06 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0F3A08 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0F3A09 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5251   },
5252
5253   /* PREFIX_VEX_0F3A0A */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0F3A0B */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0F3A0C */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5272   },
5273
5274   /* PREFIX_VEX_0F3A0D */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5279   },
5280
5281   /* PREFIX_VEX_0F3A0E */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
5286   },
5287
5288   /* PREFIX_VEX_0F3A0F */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
5293   },
5294
5295   /* PREFIX_VEX_0F3A14 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5300   },
5301
5302   /* PREFIX_VEX_0F3A15 */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5307   },
5308
5309   /* PREFIX_VEX_0F3A16 */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5314   },
5315
5316   /* PREFIX_VEX_0F3A17 */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5321   },
5322
5323   /* PREFIX_VEX_0F3A18 */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5328   },
5329
5330   /* PREFIX_VEX_0F3A19 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5335   },
5336
5337   /* PREFIX_VEX_0F3A1D */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { "vcvtps2ph", { EXxmmq, XM, Ib } },
5342   },
5343
5344   /* PREFIX_VEX_0F3A20 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0F3A21 */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5356   },
5357
5358   /* PREFIX_VEX_0F3A22 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5363   },
5364
5365   /* PREFIX_VEX_0F3A38 */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
5370   },
5371
5372   /* PREFIX_VEX_0F3A39 */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
5377   },
5378
5379   /* PREFIX_VEX_0F3A40 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5384   },
5385
5386   /* PREFIX_VEX_0F3A41 */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5391   },
5392
5393   /* PREFIX_VEX_0F3A42 */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
5398   },
5399
5400   /* PREFIX_VEX_0F3A44 */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5405   },
5406
5407   /* PREFIX_VEX_0F3A46 */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
5412   },
5413
5414   /* PREFIX_VEX_0F3A48 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5419   },
5420
5421   /* PREFIX_VEX_0F3A49 */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5426   },
5427
5428   /* PREFIX_VEX_0F3A4A */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5433   },
5434
5435   /* PREFIX_VEX_0F3A4B */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5440   },
5441
5442   /* PREFIX_VEX_0F3A4C */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
5447   },
5448
5449   /* PREFIX_VEX_0F3A5C */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5454   },
5455
5456   /* PREFIX_VEX_0F3A5D */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5461   },
5462
5463   /* PREFIX_VEX_0F3A5E */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5468   },
5469
5470   /* PREFIX_VEX_0F3A5F */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5475   },
5476
5477   /* PREFIX_VEX_0F3A60 */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5482     { Bad_Opcode },
5483   },
5484
5485   /* PREFIX_VEX_0F3A61 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5490   },
5491
5492   /* PREFIX_VEX_0F3A62 */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5497   },
5498
5499   /* PREFIX_VEX_0F3A63 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5504   },
5505
5506   /* PREFIX_VEX_0F3A68 */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5511   },
5512
5513   /* PREFIX_VEX_0F3A69 */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5518   },
5519
5520   /* PREFIX_VEX_0F3A6A */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5525   },
5526
5527   /* PREFIX_VEX_0F3A6B */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5532   },
5533
5534   /* PREFIX_VEX_0F3A6C */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5539   },
5540
5541   /* PREFIX_VEX_0F3A6D */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5546   },
5547
5548   /* PREFIX_VEX_0F3A6E */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5553   },
5554
5555   /* PREFIX_VEX_0F3A6F */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5560   },
5561
5562   /* PREFIX_VEX_0F3A78 */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5567   },
5568
5569   /* PREFIX_VEX_0F3A79 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5574   },
5575
5576   /* PREFIX_VEX_0F3A7A */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5581   },
5582
5583   /* PREFIX_VEX_0F3A7B */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0F3A7C */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5595     { Bad_Opcode },
5596   },
5597
5598   /* PREFIX_VEX_0F3A7D */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5603   },
5604
5605   /* PREFIX_VEX_0F3A7E */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F3A7F */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F3ADF */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F3AF0 */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
5632   },
5633 };
5634
5635 static const struct dis386 x86_64_table[][2] = {
5636   /* X86_64_06 */
5637   {
5638     { "pushP", { es } },
5639   },
5640
5641   /* X86_64_07 */
5642   {
5643     { "popP", { es } },
5644   },
5645
5646   /* X86_64_0D */
5647   {
5648     { "pushP", { cs } },
5649   },
5650
5651   /* X86_64_16 */
5652   {
5653     { "pushP", { ss } },
5654   },
5655
5656   /* X86_64_17 */
5657   {
5658     { "popP", { ss } },
5659   },
5660
5661   /* X86_64_1E */
5662   {
5663     { "pushP", { ds } },
5664   },
5665
5666   /* X86_64_1F */
5667   {
5668     { "popP", { ds } },
5669   },
5670
5671   /* X86_64_27 */
5672   {
5673     { "daa", { XX } },
5674   },
5675
5676   /* X86_64_2F */
5677   {
5678     { "das", { XX } },
5679   },
5680
5681   /* X86_64_37 */
5682   {
5683     { "aaa", { XX } },
5684   },
5685
5686   /* X86_64_3F */
5687   {
5688     { "aas", { XX } },
5689   },
5690
5691   /* X86_64_60 */
5692   {
5693     { "pushaP", { XX } },
5694   },
5695
5696   /* X86_64_61 */
5697   {
5698     { "popaP", { XX } },
5699   },
5700
5701   /* X86_64_62 */
5702   {
5703     { MOD_TABLE (MOD_62_32BIT) },
5704   },
5705
5706   /* X86_64_63 */
5707   {
5708     { "arpl", { Ew, Gw } },
5709     { "movs{lq|xd}", { Gv, Ed } },
5710   },
5711
5712   /* X86_64_6D */
5713   {
5714     { "ins{R|}", { Yzr, indirDX } },
5715     { "ins{G|}", { Yzr, indirDX } },
5716   },
5717
5718   /* X86_64_6F */
5719   {
5720     { "outs{R|}", { indirDXr, Xz } },
5721     { "outs{G|}", { indirDXr, Xz } },
5722   },
5723
5724   /* X86_64_9A */
5725   {
5726     { "Jcall{T|}", { Ap } },
5727   },
5728
5729   /* X86_64_C4 */
5730   {
5731     { MOD_TABLE (MOD_C4_32BIT) },
5732     { VEX_C4_TABLE (VEX_0F) },
5733   },
5734
5735   /* X86_64_C5 */
5736   {
5737     { MOD_TABLE (MOD_C5_32BIT) },
5738     { VEX_C5_TABLE (VEX_0F) },
5739   },
5740
5741   /* X86_64_CE */
5742   {
5743     { "into", { XX } },
5744   },
5745
5746   /* X86_64_D4 */
5747   {
5748     { "aam", { Ib } },
5749   },
5750
5751   /* X86_64_D5 */
5752   {
5753     { "aad", { Ib } },
5754   },
5755
5756   /* X86_64_EA */
5757   {
5758     { "Jjmp{T|}", { Ap } },
5759   },
5760
5761   /* X86_64_0F01_REG_0 */
5762   {
5763     { "sgdt{Q|IQ}", { M } },
5764     { "sgdt", { M } },
5765   },
5766
5767   /* X86_64_0F01_REG_1 */
5768   {
5769     { "sidt{Q|IQ}", { M } },
5770     { "sidt", { M } },
5771   },
5772
5773   /* X86_64_0F01_REG_2 */
5774   {
5775     { "lgdt{Q|Q}", { M } },
5776     { "lgdt", { M } },
5777   },
5778
5779   /* X86_64_0F01_REG_3 */
5780   {
5781     { "lidt{Q|Q}", { M } },
5782     { "lidt", { M } },
5783   },
5784 };
5785
5786 static const struct dis386 three_byte_table[][256] = {
5787
5788   /* THREE_BYTE_0F38 */
5789   {
5790     /* 00 */
5791     { "pshufb",         { MX, EM } },
5792     { "phaddw",         { MX, EM } },
5793     { "phaddd",         { MX, EM } },
5794     { "phaddsw",        { MX, EM } },
5795     { "pmaddubsw",      { MX, EM } },
5796     { "phsubw",         { MX, EM } },
5797     { "phsubd",         { MX, EM } },
5798     { "phsubsw",        { MX, EM } },
5799     /* 08 */
5800     { "psignb",         { MX, EM } },
5801     { "psignw",         { MX, EM } },
5802     { "psignd",         { MX, EM } },
5803     { "pmulhrsw",       { MX, EM } },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     /* 10 */
5809     { PREFIX_TABLE (PREFIX_0F3810) },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { PREFIX_TABLE (PREFIX_0F3814) },
5814     { PREFIX_TABLE (PREFIX_0F3815) },
5815     { Bad_Opcode },
5816     { PREFIX_TABLE (PREFIX_0F3817) },
5817     /* 18 */
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { "pabsb",          { MX, EM } },
5823     { "pabsw",          { MX, EM } },
5824     { "pabsd",          { MX, EM } },
5825     { Bad_Opcode },
5826     /* 20 */
5827     { PREFIX_TABLE (PREFIX_0F3820) },
5828     { PREFIX_TABLE (PREFIX_0F3821) },
5829     { PREFIX_TABLE (PREFIX_0F3822) },
5830     { PREFIX_TABLE (PREFIX_0F3823) },
5831     { PREFIX_TABLE (PREFIX_0F3824) },
5832     { PREFIX_TABLE (PREFIX_0F3825) },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     /* 28 */
5836     { PREFIX_TABLE (PREFIX_0F3828) },
5837     { PREFIX_TABLE (PREFIX_0F3829) },
5838     { PREFIX_TABLE (PREFIX_0F382A) },
5839     { PREFIX_TABLE (PREFIX_0F382B) },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     /* 30 */
5845     { PREFIX_TABLE (PREFIX_0F3830) },
5846     { PREFIX_TABLE (PREFIX_0F3831) },
5847     { PREFIX_TABLE (PREFIX_0F3832) },
5848     { PREFIX_TABLE (PREFIX_0F3833) },
5849     { PREFIX_TABLE (PREFIX_0F3834) },
5850     { PREFIX_TABLE (PREFIX_0F3835) },
5851     { Bad_Opcode },
5852     { PREFIX_TABLE (PREFIX_0F3837) },
5853     /* 38 */
5854     { PREFIX_TABLE (PREFIX_0F3838) },
5855     { PREFIX_TABLE (PREFIX_0F3839) },
5856     { PREFIX_TABLE (PREFIX_0F383A) },
5857     { PREFIX_TABLE (PREFIX_0F383B) },
5858     { PREFIX_TABLE (PREFIX_0F383C) },
5859     { PREFIX_TABLE (PREFIX_0F383D) },
5860     { PREFIX_TABLE (PREFIX_0F383E) },
5861     { PREFIX_TABLE (PREFIX_0F383F) },
5862     /* 40 */
5863     { PREFIX_TABLE (PREFIX_0F3840) },
5864     { PREFIX_TABLE (PREFIX_0F3841) },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     /* 48 */
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     /* 50 */
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     /* 58 */
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     /* 60 */
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     /* 68 */
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     /* 70 */
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     /* 78 */
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     /* 80 */
5935     { PREFIX_TABLE (PREFIX_0F3880) },
5936     { PREFIX_TABLE (PREFIX_0F3881) },
5937     { PREFIX_TABLE (PREFIX_0F3882) },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     /* 88 */
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     /* 90 */
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     /* 98 */
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     /* a0 */
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     /* a8 */
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     /* b0 */
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     /* b8 */
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     /* c0 */
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     /* c8 */
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     /* d0 */
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     /* d8 */
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { PREFIX_TABLE (PREFIX_0F38DB) },
6038     { PREFIX_TABLE (PREFIX_0F38DC) },
6039     { PREFIX_TABLE (PREFIX_0F38DD) },
6040     { PREFIX_TABLE (PREFIX_0F38DE) },
6041     { PREFIX_TABLE (PREFIX_0F38DF) },
6042     /* e0 */
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     /* e8 */
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     /* f0 */
6061     { PREFIX_TABLE (PREFIX_0F38F0) },
6062     { PREFIX_TABLE (PREFIX_0F38F1) },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { PREFIX_TABLE (PREFIX_0F38F6) },
6068     { Bad_Opcode },
6069     /* f8 */
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078   },
6079   /* THREE_BYTE_0F3A */
6080   {
6081     /* 00 */
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     /* 08 */
6091     { PREFIX_TABLE (PREFIX_0F3A08) },
6092     { PREFIX_TABLE (PREFIX_0F3A09) },
6093     { PREFIX_TABLE (PREFIX_0F3A0A) },
6094     { PREFIX_TABLE (PREFIX_0F3A0B) },
6095     { PREFIX_TABLE (PREFIX_0F3A0C) },
6096     { PREFIX_TABLE (PREFIX_0F3A0D) },
6097     { PREFIX_TABLE (PREFIX_0F3A0E) },
6098     { "palignr",        { MX, EM, Ib } },
6099     /* 10 */
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { PREFIX_TABLE (PREFIX_0F3A14) },
6105     { PREFIX_TABLE (PREFIX_0F3A15) },
6106     { PREFIX_TABLE (PREFIX_0F3A16) },
6107     { PREFIX_TABLE (PREFIX_0F3A17) },
6108     /* 18 */
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     /* 20 */
6118     { PREFIX_TABLE (PREFIX_0F3A20) },
6119     { PREFIX_TABLE (PREFIX_0F3A21) },
6120     { PREFIX_TABLE (PREFIX_0F3A22) },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     /* 28 */
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     /* 30 */
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     /* 38 */
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     /* 40 */
6154     { PREFIX_TABLE (PREFIX_0F3A40) },
6155     { PREFIX_TABLE (PREFIX_0F3A41) },
6156     { PREFIX_TABLE (PREFIX_0F3A42) },
6157     { Bad_Opcode },
6158     { PREFIX_TABLE (PREFIX_0F3A44) },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     /* 48 */
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     /* 50 */
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     /* 58 */
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     /* 60 */
6190     { PREFIX_TABLE (PREFIX_0F3A60) },
6191     { PREFIX_TABLE (PREFIX_0F3A61) },
6192     { PREFIX_TABLE (PREFIX_0F3A62) },
6193     { PREFIX_TABLE (PREFIX_0F3A63) },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     /* 68 */
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     /* 70 */
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     /* 78 */
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     /* 80 */
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     /* 88 */
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     /* 90 */
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     /* 98 */
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     /* a0 */
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     /* a8 */
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     /* b0 */
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     /* b8 */
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     /* c0 */
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     /* c8 */
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     /* d0 */
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     /* d8 */
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { PREFIX_TABLE (PREFIX_0F3ADF) },
6333     /* e0 */
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     /* e8 */
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     /* f0 */
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     /* f8 */
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369   },
6370
6371   /* THREE_BYTE_0F7A */
6372   {
6373     /* 00 */
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     /* 08 */
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     /* 10 */
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     /* 18 */
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     /* 20 */
6410     { "ptest",          { XX } },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     /* 28 */
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     /* 30 */
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     /* 38 */
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     /* 40 */
6446     { Bad_Opcode },
6447     { "phaddbw",        { XM, EXq } },
6448     { "phaddbd",        { XM, EXq } },
6449     { "phaddbq",        { XM, EXq } },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { "phaddwd",        { XM, EXq } },
6453     { "phaddwq",        { XM, EXq } },
6454     /* 48 */
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { "phadddq",        { XM, EXq } },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     /* 50 */
6464     { Bad_Opcode },
6465     { "phaddubw",       { XM, EXq } },
6466     { "phaddubd",       { XM, EXq } },
6467     { "phaddubq",       { XM, EXq } },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { "phadduwd",       { XM, EXq } },
6471     { "phadduwq",       { XM, EXq } },
6472     /* 58 */
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { "phaddudq",       { XM, EXq } },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     /* 60 */
6482     { Bad_Opcode },
6483     { "phsubbw",        { XM, EXq } },
6484     { "phsubbd",        { XM, EXq } },
6485     { "phsubbq",        { XM, EXq } },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     /* 68 */
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     /* 70 */
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     /* 78 */
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     /* 80 */
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     /* 88 */
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     /* 90 */
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     /* 98 */
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     /* a0 */
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     /* a8 */
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     /* b0 */
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     /* b8 */
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     /* c0 */
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     /* c8 */
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     /* d0 */
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     /* d8 */
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     /* e0 */
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     /* e8 */
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     /* f0 */
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     /* f8 */
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661   },
6662 };
6663
6664 static const struct dis386 xop_table[][256] = {
6665   /* XOP_08 */
6666   {
6667     /* 00 */
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     /* 08 */
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     /* 10 */
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     /* 18 */
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     /* 20 */
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     /* 28 */
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     /* 30 */
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     /* 38 */
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     /* 40 */
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     /* 48 */
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     /* 50 */
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     /* 58 */
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     /* 60 */
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     /* 68 */
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     /* 70 */
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     /* 78 */
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     /* 80 */
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6818     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6819     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6820     /* 88 */
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6828     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6829     /* 90 */
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6836     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6837     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6838     /* 98 */
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6846     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6847     /* a0 */
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6851     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6855     { Bad_Opcode },
6856     /* a8 */
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     /* b0 */
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6873     { Bad_Opcode },
6874     /* b8 */
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     /* c0 */
6884     { "vprotb",         { XM, Vex_2src_1, Ib } },
6885     { "vprotw",         { XM, Vex_2src_1, Ib } },
6886     { "vprotd",         { XM, Vex_2src_1, Ib } },
6887     { "vprotq",         { XM, Vex_2src_1, Ib } },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     /* c8 */
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6898     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6899     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6900     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6901     /* d0 */
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     /* d8 */
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     /* e0 */
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     /* e8 */
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6934     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6935     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6936     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6937     /* f0 */
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     /* f8 */
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955   },
6956   /* XOP_09 */
6957   {
6958     /* 00 */
6959     { Bad_Opcode },
6960     { REG_TABLE (REG_XOP_TBM_01) },
6961     { REG_TABLE (REG_XOP_TBM_02) },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     /* 08 */
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     /* 10 */
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { REG_TABLE (REG_XOP_LWPCB) },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     /* 18 */
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     /* 20 */
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     /* 28 */
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     /* 30 */
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     /* 38 */
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     /* 40 */
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     /* 48 */
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     /* 50 */
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     /* 58 */
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     /* 60 */
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     /* 68 */
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     /* 70 */
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     /* 78 */
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     /* 80 */
7103     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7104     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7105     { "vfrczss",        { XM, EXd } },
7106     { "vfrczsd",        { XM, EXq } },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     /* 88 */
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     /* 90 */
7121     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7122     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7123     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7124     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7125     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7126     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7127     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7128     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7129     /* 98 */
7130     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7131     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7132     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7133     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     /* a0 */
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     /* a8 */
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     /* b0 */
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     /* b8 */
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     /* c0 */
7175     { Bad_Opcode },
7176     { "vphaddbw",       { XM, EXxmm } },
7177     { "vphaddbd",       { XM, EXxmm } },
7178     { "vphaddbq",       { XM, EXxmm } },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { "vphaddwd",       { XM, EXxmm } },
7182     { "vphaddwq",       { XM, EXxmm } },
7183     /* c8 */
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { "vphadddq",       { XM, EXxmm } },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     /* d0 */
7193     { Bad_Opcode },
7194     { "vphaddubw",      { XM, EXxmm } },
7195     { "vphaddubd",      { XM, EXxmm } },
7196     { "vphaddubq",      { XM, EXxmm } },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { "vphadduwd",      { XM, EXxmm } },
7200     { "vphadduwq",      { XM, EXxmm } },
7201     /* d8 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { "vphaddudq",      { XM, EXxmm } },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     /* e0 */
7211     { Bad_Opcode },
7212     { "vphsubbw",       { XM, EXxmm } },
7213     { "vphsubwd",       { XM, EXxmm } },
7214     { "vphsubdq",       { XM, EXxmm } },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     /* e8 */
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     /* f0 */
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     /* f8 */
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246   },
7247   /* XOP_0A */
7248   {
7249     /* 00 */
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     /* 08 */
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     /* 10 */
7268     { "bextr",  { Gv, Ev, Iq } },
7269     { Bad_Opcode },
7270     { REG_TABLE (REG_XOP_LWP) },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     /* 18 */
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     /* 20 */
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     /* 28 */
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     /* 30 */
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     /* 38 */
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     /* 40 */
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     /* 48 */
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     /* 50 */
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     /* 58 */
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     /* 60 */
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     /* 68 */
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     /* 70 */
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     /* 78 */
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     /* 80 */
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     /* 88 */
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     /* 90 */
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     /* 98 */
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     /* a0 */
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     /* a8 */
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     /* b0 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     /* b8 */
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     /* c0 */
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     /* c8 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     /* d0 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     /* d8 */
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     /* e0 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* e8 */
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     /* f0 */
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     /* f8 */
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537   },
7538 };
7539
7540 static const struct dis386 vex_table[][256] = {
7541   /* VEX_0F */
7542   {
7543     /* 00 */
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     /* 08 */
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     /* 10 */
7562     { PREFIX_TABLE (PREFIX_VEX_0F10) },
7563     { PREFIX_TABLE (PREFIX_VEX_0F11) },
7564     { PREFIX_TABLE (PREFIX_VEX_0F12) },
7565     { MOD_TABLE (MOD_VEX_0F13) },
7566     { VEX_W_TABLE (VEX_W_0F14) },
7567     { VEX_W_TABLE (VEX_W_0F15) },
7568     { PREFIX_TABLE (PREFIX_VEX_0F16) },
7569     { MOD_TABLE (MOD_VEX_0F17) },
7570     /* 18 */
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     /* 20 */
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     /* 28 */
7589     { VEX_W_TABLE (VEX_W_0F28) },
7590     { VEX_W_TABLE (VEX_W_0F29) },
7591     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7592     { MOD_TABLE (MOD_VEX_0F2B) },
7593     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7594     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7595     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7596     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7597     /* 30 */
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     /* 38 */
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     /* 40 */
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     /* 48 */
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     /* 50 */
7634     { MOD_TABLE (MOD_VEX_0F50) },
7635     { PREFIX_TABLE (PREFIX_VEX_0F51) },
7636     { PREFIX_TABLE (PREFIX_VEX_0F52) },
7637     { PREFIX_TABLE (PREFIX_VEX_0F53) },
7638     { "vandpX",         { XM, Vex, EXx } },
7639     { "vandnpX",        { XM, Vex, EXx } },
7640     { "vorpX",          { XM, Vex, EXx } },
7641     { "vxorpX",         { XM, Vex, EXx } },
7642     /* 58 */
7643     { PREFIX_TABLE (PREFIX_VEX_0F58) },
7644     { PREFIX_TABLE (PREFIX_VEX_0F59) },
7645     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7646     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7647     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7648     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7649     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7650     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7651     /* 60 */
7652     { PREFIX_TABLE (PREFIX_VEX_0F60) },
7653     { PREFIX_TABLE (PREFIX_VEX_0F61) },
7654     { PREFIX_TABLE (PREFIX_VEX_0F62) },
7655     { PREFIX_TABLE (PREFIX_VEX_0F63) },
7656     { PREFIX_TABLE (PREFIX_VEX_0F64) },
7657     { PREFIX_TABLE (PREFIX_VEX_0F65) },
7658     { PREFIX_TABLE (PREFIX_VEX_0F66) },
7659     { PREFIX_TABLE (PREFIX_VEX_0F67) },
7660     /* 68 */
7661     { PREFIX_TABLE (PREFIX_VEX_0F68) },
7662     { PREFIX_TABLE (PREFIX_VEX_0F69) },
7663     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7664     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7665     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7666     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7667     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7668     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7669     /* 70 */
7670     { PREFIX_TABLE (PREFIX_VEX_0F70) },
7671     { REG_TABLE (REG_VEX_0F71) },
7672     { REG_TABLE (REG_VEX_0F72) },
7673     { REG_TABLE (REG_VEX_0F73) },
7674     { PREFIX_TABLE (PREFIX_VEX_0F74) },
7675     { PREFIX_TABLE (PREFIX_VEX_0F75) },
7676     { PREFIX_TABLE (PREFIX_VEX_0F76) },
7677     { PREFIX_TABLE (PREFIX_VEX_0F77) },
7678     /* 78 */
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7684     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7685     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7686     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7687     /* 80 */
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     /* 88 */
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     /* 90 */
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     /* 98 */
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     /* a0 */
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     /* a8 */
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { REG_TABLE (REG_VEX_0FAE) },
7740     { Bad_Opcode },
7741     /* b0 */
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     /* b8 */
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     /* c0 */
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7763     { Bad_Opcode },
7764     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7765     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7766     { "vshufpX",        { XM, Vex, EXx, Ib } },
7767     { Bad_Opcode },
7768     /* c8 */
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     /* d0 */
7778     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7779     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7780     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7781     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7782     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7783     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7784     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7785     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7786     /* d8 */
7787     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7788     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7789     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7790     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7791     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7792     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7793     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7794     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7795     /* e0 */
7796     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7797     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7798     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7799     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7800     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7801     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7802     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7803     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7804     /* e8 */
7805     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7806     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7807     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7808     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7809     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7810     { PREFIX_TABLE (PREFIX_VEX_0FED) },
7811     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7812     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7813     /* f0 */
7814     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7815     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7816     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7817     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7818     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7819     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7820     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7821     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7822     /* f8 */
7823     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7824     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7825     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7826     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7827     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7828     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7829     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7830     { Bad_Opcode },
7831   },
7832   /* VEX_0F38 */
7833   {
7834     /* 00 */
7835     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7836     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7837     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7838     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7839     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7840     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7841     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7842     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7843     /* 08 */
7844     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7845     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7846     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7847     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7848     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7849     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7850     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7851     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7852     /* 10 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
7860     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7861     /* 18 */
7862     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7863     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7864     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7865     { Bad_Opcode },
7866     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7867     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7868     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7869     { Bad_Opcode },
7870     /* 20 */
7871     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7872     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7873     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7874     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7875     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7876     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     /* 28 */
7880     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7881     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7882     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7883     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7884     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7885     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7886     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7887     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7888     /* 30 */
7889     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7890     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7891     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7892     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7893     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7894     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7895     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
7896     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7897     /* 38 */
7898     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7899     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7900     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7901     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7902     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7903     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7904     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7905     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7906     /* 40 */
7907     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7908     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
7913     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
7914     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
7915     /* 48 */
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     /* 50 */
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     /* 58 */
7934     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
7935     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
7936     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     /* 60 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     /* 68 */
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     /* 70 */
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* 78 */
7970     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
7971     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     /* 80 */
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     /* 88 */
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
7993     { Bad_Opcode },
7994     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
7995     { Bad_Opcode },
7996     /* 90 */
7997     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
7998     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
7999     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8000     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8004     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8005     /* 98 */
8006     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8007     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8008     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8009     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8010     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8011     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8012     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8013     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8014     /* a0 */
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8022     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8023     /* a8 */
8024     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8025     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8026     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8027     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8028     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8029     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8030     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8031     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8032     /* b0 */
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8040     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8041     /* b8 */
8042     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8043     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8044     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8045     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8046     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8047     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8048     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8049     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8050     /* c0 */
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     /* c8 */
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     /* d0 */
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     /* d8 */
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8082     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8083     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8084     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8085     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8086     /* e0 */
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     /* e8 */
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     /* f0 */
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8108     { REG_TABLE (REG_VEX_0F38F3) },
8109     { Bad_Opcode },
8110     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8111     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8112     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8113     /* f8 */
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122   },
8123   /* VEX_0F3A */
8124   {
8125     /* 00 */
8126     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8127     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8128     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8129     { Bad_Opcode },
8130     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8131     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8132     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8133     { Bad_Opcode },
8134     /* 08 */
8135     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8136     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8137     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8138     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8139     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8140     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8141     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8142     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8143     /* 10 */
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8149     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8150     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8151     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8152     /* 18 */
8153     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8154     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     /* 20 */
8162     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8163     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8164     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     /* 28 */
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     /* 30 */
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     /* 38 */
8189     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8190     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     /* 40 */
8198     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8199     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8200     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8201     { Bad_Opcode },
8202     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8203     { Bad_Opcode },
8204     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8205     { Bad_Opcode },
8206     /* 48 */
8207     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8208     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8209     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8210     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8211     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     /* 50 */
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     /* 58 */
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8230     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8231     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8232     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8233     /* 60 */
8234     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8235     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8236     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8237     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     /* 68 */
8243     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8244     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8245     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8246     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8247     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8248     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8249     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8250     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8251     /* 70 */
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     /* 78 */
8261     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8262     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8263     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8264     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8265     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8266     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8267     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8268     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8269     /* 80 */
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     /* 88 */
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     /* 90 */
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     /* 98 */
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     /* a0 */
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     /* a8 */
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* b0 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* b8 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* c0 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* c8 */
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     /* d0 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* d8 */
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8377     /* e0 */
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     /* e8 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* f0 */
8396     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     /* f8 */
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413   },
8414 };
8415
8416 static const struct dis386 vex_len_table[][2] = {
8417   /* VEX_LEN_0F10_P_1 */
8418   {
8419     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8420     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8421   },
8422
8423   /* VEX_LEN_0F10_P_3 */
8424   {
8425     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8426     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8427   },
8428
8429   /* VEX_LEN_0F11_P_1 */
8430   {
8431     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8432     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8433   },
8434
8435   /* VEX_LEN_0F11_P_3 */
8436   {
8437     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8438     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8439   },
8440
8441   /* VEX_LEN_0F12_P_0_M_0 */
8442   {
8443     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8444   },
8445
8446   /* VEX_LEN_0F12_P_0_M_1 */
8447   {
8448     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8449   },
8450
8451   /* VEX_LEN_0F12_P_2 */
8452   {
8453     { VEX_W_TABLE (VEX_W_0F12_P_2) },
8454   },
8455
8456   /* VEX_LEN_0F13_M_0 */
8457   {
8458     { VEX_W_TABLE (VEX_W_0F13_M_0) },
8459   },
8460
8461   /* VEX_LEN_0F16_P_0_M_0 */
8462   {
8463     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8464   },
8465
8466   /* VEX_LEN_0F16_P_0_M_1 */
8467   {
8468     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8469   },
8470
8471   /* VEX_LEN_0F16_P_2 */
8472   {
8473     { VEX_W_TABLE (VEX_W_0F16_P_2) },
8474   },
8475
8476   /* VEX_LEN_0F17_M_0 */
8477   {
8478     { VEX_W_TABLE (VEX_W_0F17_M_0) },
8479   },
8480
8481   /* VEX_LEN_0F2A_P_1 */
8482   {
8483     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8484     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8485   },
8486
8487   /* VEX_LEN_0F2A_P_3 */
8488   {
8489     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8490     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8491   },
8492
8493   /* VEX_LEN_0F2C_P_1 */
8494   {
8495     { "vcvttss2siY",    { Gv, EXdScalar } },
8496     { "vcvttss2siY",    { Gv, EXdScalar } },
8497   },
8498
8499   /* VEX_LEN_0F2C_P_3 */
8500   {
8501     { "vcvttsd2siY",    { Gv, EXqScalar } },
8502     { "vcvttsd2siY",    { Gv, EXqScalar } },
8503   },
8504
8505   /* VEX_LEN_0F2D_P_1 */
8506   {
8507     { "vcvtss2siY",     { Gv, EXdScalar } },
8508     { "vcvtss2siY",     { Gv, EXdScalar } },
8509   },
8510
8511   /* VEX_LEN_0F2D_P_3 */
8512   {
8513     { "vcvtsd2siY",     { Gv, EXqScalar } },
8514     { "vcvtsd2siY",     { Gv, EXqScalar } },
8515   },
8516
8517   /* VEX_LEN_0F2E_P_0 */
8518   {
8519     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8520     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8521   },
8522
8523   /* VEX_LEN_0F2E_P_2 */
8524   {
8525     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8526     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8527   },
8528
8529   /* VEX_LEN_0F2F_P_0 */
8530   {
8531     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8532     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8533   },
8534
8535   /* VEX_LEN_0F2F_P_2 */
8536   {
8537     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8538     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8539   },
8540
8541   /* VEX_LEN_0F51_P_1 */
8542   {
8543     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8544     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8545   },
8546
8547   /* VEX_LEN_0F51_P_3 */
8548   {
8549     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8550     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8551   },
8552
8553   /* VEX_LEN_0F52_P_1 */
8554   {
8555     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8556     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8557   },
8558
8559   /* VEX_LEN_0F53_P_1 */
8560   {
8561     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8562     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8563   },
8564
8565   /* VEX_LEN_0F58_P_1 */
8566   {
8567     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8568     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8569   },
8570
8571   /* VEX_LEN_0F58_P_3 */
8572   {
8573     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8574     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8575   },
8576
8577   /* VEX_LEN_0F59_P_1 */
8578   {
8579     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8580     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8581   },
8582
8583   /* VEX_LEN_0F59_P_3 */
8584   {
8585     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8586     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8587   },
8588
8589   /* VEX_LEN_0F5A_P_1 */
8590   {
8591     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8592     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8593   },
8594
8595   /* VEX_LEN_0F5A_P_3 */
8596   {
8597     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8598     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8599   },
8600
8601   /* VEX_LEN_0F5C_P_1 */
8602   {
8603     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8604     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8605   },
8606
8607   /* VEX_LEN_0F5C_P_3 */
8608   {
8609     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8610     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8611   },
8612
8613   /* VEX_LEN_0F5D_P_1 */
8614   {
8615     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8616     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8617   },
8618
8619   /* VEX_LEN_0F5D_P_3 */
8620   {
8621     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8622     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8623   },
8624
8625   /* VEX_LEN_0F5E_P_1 */
8626   {
8627     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8628     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8629   },
8630
8631   /* VEX_LEN_0F5E_P_3 */
8632   {
8633     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8634     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8635   },
8636
8637   /* VEX_LEN_0F5F_P_1 */
8638   {
8639     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8640     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8641   },
8642
8643   /* VEX_LEN_0F5F_P_3 */
8644   {
8645     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8646     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8647   },
8648
8649   /* VEX_LEN_0F6E_P_2 */
8650   {
8651     { "vmovK",          { XMScalar, Edq } },
8652     { "vmovK",          { XMScalar, Edq } },
8653   },
8654
8655   /* VEX_LEN_0F7E_P_1 */
8656   {
8657     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8658     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8659   },
8660
8661   /* VEX_LEN_0F7E_P_2 */
8662   {
8663     { "vmovK",          { Edq, XMScalar } },
8664     { "vmovK",          { Edq, XMScalar } },
8665   },
8666
8667   /* VEX_LEN_0FAE_R_2_M_0 */
8668   {
8669     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8670   },
8671
8672   /* VEX_LEN_0FAE_R_3_M_0 */
8673   {
8674     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8675   },
8676
8677   /* VEX_LEN_0FC2_P_1 */
8678   {
8679     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8680     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8681   },
8682
8683   /* VEX_LEN_0FC2_P_3 */
8684   {
8685     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8686     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8687   },
8688
8689   /* VEX_LEN_0FC4_P_2 */
8690   {
8691     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8692   },
8693
8694   /* VEX_LEN_0FC5_P_2 */
8695   {
8696     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8697   },
8698
8699   /* VEX_LEN_0FD6_P_2 */
8700   {
8701     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8702     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8703   },
8704
8705   /* VEX_LEN_0FF7_P_2 */
8706   {
8707     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8708   },
8709
8710   /* VEX_LEN_0F3816_P_2 */
8711   {
8712     { Bad_Opcode },
8713     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
8714   },
8715
8716   /* VEX_LEN_0F3819_P_2 */
8717   {
8718     { Bad_Opcode },
8719     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
8720   },
8721
8722   /* VEX_LEN_0F381A_P_2_M_0 */
8723   {
8724     { Bad_Opcode },
8725     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8726   },
8727
8728   /* VEX_LEN_0F3836_P_2 */
8729   {
8730     { Bad_Opcode },
8731     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
8732   },
8733
8734   /* VEX_LEN_0F3841_P_2 */
8735   {
8736     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
8737   },
8738
8739   /* VEX_LEN_0F385A_P_2_M_0 */
8740   {
8741     { Bad_Opcode },
8742     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
8743   },
8744
8745   /* VEX_LEN_0F38DB_P_2 */
8746   {
8747     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
8748   },
8749
8750   /* VEX_LEN_0F38DC_P_2 */
8751   {
8752     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
8753   },
8754
8755   /* VEX_LEN_0F38DD_P_2 */
8756   {
8757     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
8758   },
8759
8760   /* VEX_LEN_0F38DE_P_2 */
8761   {
8762     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
8763   },
8764
8765   /* VEX_LEN_0F38DF_P_2 */
8766   {
8767     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
8768   },
8769
8770   /* VEX_LEN_0F38F2_P_0 */
8771   {
8772     { "andnS",          { Gdq, VexGdq, Edq } },
8773   },
8774
8775   /* VEX_LEN_0F38F3_R_1_P_0 */
8776   {
8777     { "blsrS",          { VexGdq, Edq } },
8778   },
8779
8780   /* VEX_LEN_0F38F3_R_2_P_0 */
8781   {
8782     { "blsmskS",        { VexGdq, Edq } },
8783   },
8784
8785   /* VEX_LEN_0F38F3_R_3_P_0 */
8786   {
8787     { "blsiS",          { VexGdq, Edq } },
8788   },
8789
8790   /* VEX_LEN_0F38F5_P_0 */
8791   {
8792     { "bzhiS",          { Gdq, Edq, VexGdq } },
8793   },
8794
8795   /* VEX_LEN_0F38F5_P_1 */
8796   {
8797     { "pextS",          { Gdq, VexGdq, Edq } },
8798   },
8799
8800   /* VEX_LEN_0F38F5_P_3 */
8801   {
8802     { "pdepS",          { Gdq, VexGdq, Edq } },
8803   },
8804
8805   /* VEX_LEN_0F38F6_P_3 */
8806   {
8807     { "mulxS",          { Gdq, VexGdq, Edq } },
8808   },
8809
8810   /* VEX_LEN_0F38F7_P_0 */
8811   {
8812     { "bextrS",         { Gdq, Edq, VexGdq } },
8813   },
8814
8815   /* VEX_LEN_0F38F7_P_1 */
8816   {
8817     { "sarxS",          { Gdq, Edq, VexGdq } },
8818   },
8819
8820   /* VEX_LEN_0F38F7_P_2 */
8821   {
8822     { "shlxS",          { Gdq, Edq, VexGdq } },
8823   },
8824
8825   /* VEX_LEN_0F38F7_P_3 */
8826   {
8827     { "shrxS",          { Gdq, Edq, VexGdq } },
8828   },
8829
8830   /* VEX_LEN_0F3A00_P_2 */
8831   {
8832     { Bad_Opcode },
8833     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
8834   },
8835
8836   /* VEX_LEN_0F3A01_P_2 */
8837   {
8838     { Bad_Opcode },
8839     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
8840   },
8841
8842   /* VEX_LEN_0F3A06_P_2 */
8843   {
8844     { Bad_Opcode },
8845     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
8846   },
8847
8848   /* VEX_LEN_0F3A0A_P_2 */
8849   {
8850     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8851     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8852   },
8853
8854   /* VEX_LEN_0F3A0B_P_2 */
8855   {
8856     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8857     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8858   },
8859
8860   /* VEX_LEN_0F3A14_P_2 */
8861   {
8862     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
8863   },
8864
8865   /* VEX_LEN_0F3A15_P_2 */
8866   {
8867     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
8868   },
8869
8870   /* VEX_LEN_0F3A16_P_2  */
8871   {
8872     { "vpextrK",        { Edq, XM, Ib } },
8873   },
8874
8875   /* VEX_LEN_0F3A17_P_2 */
8876   {
8877     { "vextractps",     { Edqd, XM, Ib } },
8878   },
8879
8880   /* VEX_LEN_0F3A18_P_2 */
8881   {
8882     { Bad_Opcode },
8883     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
8884   },
8885
8886   /* VEX_LEN_0F3A19_P_2 */
8887   {
8888     { Bad_Opcode },
8889     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
8890   },
8891
8892   /* VEX_LEN_0F3A20_P_2 */
8893   {
8894     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
8895   },
8896
8897   /* VEX_LEN_0F3A21_P_2 */
8898   {
8899     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
8900   },
8901
8902   /* VEX_LEN_0F3A22_P_2 */
8903   {
8904     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8905   },
8906
8907   /* VEX_LEN_0F3A38_P_2 */
8908   {
8909     { Bad_Opcode },
8910     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
8911   },
8912
8913   /* VEX_LEN_0F3A39_P_2 */
8914   {
8915     { Bad_Opcode },
8916     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
8917   },
8918
8919   /* VEX_LEN_0F3A41_P_2 */
8920   {
8921     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
8922   },
8923
8924   /* VEX_LEN_0F3A44_P_2 */
8925   {
8926     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
8927   },
8928
8929   /* VEX_LEN_0F3A46_P_2 */
8930   {
8931     { Bad_Opcode },
8932     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
8933   },
8934
8935   /* VEX_LEN_0F3A60_P_2 */
8936   {
8937     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
8938   },
8939
8940   /* VEX_LEN_0F3A61_P_2 */
8941   {
8942     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
8943   },
8944
8945   /* VEX_LEN_0F3A62_P_2 */
8946   {
8947     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
8948   },
8949
8950   /* VEX_LEN_0F3A63_P_2 */
8951   {
8952     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
8953   },
8954
8955   /* VEX_LEN_0F3A6A_P_2 */
8956   {
8957     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8958   },
8959
8960   /* VEX_LEN_0F3A6B_P_2 */
8961   {
8962     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8963   },
8964
8965   /* VEX_LEN_0F3A6E_P_2 */
8966   {
8967     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8968   },
8969
8970   /* VEX_LEN_0F3A6F_P_2 */
8971   {
8972     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8973   },
8974
8975   /* VEX_LEN_0F3A7A_P_2 */
8976   {
8977     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8978   },
8979
8980   /* VEX_LEN_0F3A7B_P_2 */
8981   {
8982     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8983   },
8984
8985   /* VEX_LEN_0F3A7E_P_2 */
8986   {
8987     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8988   },
8989
8990   /* VEX_LEN_0F3A7F_P_2 */
8991   {
8992     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8993   },
8994
8995   /* VEX_LEN_0F3ADF_P_2 */
8996   {
8997     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
8998   },
8999
9000   /* VEX_LEN_0F3AF0_P_3 */
9001   {
9002     { "rorxS",          { Gdq, Edq, Ib } },
9003   },
9004
9005   /* VEX_LEN_0FXOP_09_80 */
9006   {
9007     { "vfrczps",        { XM, EXxmm } },
9008     { "vfrczps",        { XM, EXymmq } },
9009   },
9010
9011   /* VEX_LEN_0FXOP_09_81 */
9012   {
9013     { "vfrczpd",        { XM, EXxmm } },
9014     { "vfrczpd",        { XM, EXymmq } },
9015   },
9016 };
9017
9018 static const struct dis386 vex_w_table[][2] = {
9019   {
9020     /* VEX_W_0F10_P_0 */
9021     { "vmovups",        { XM, EXx } },
9022   },
9023   {
9024     /* VEX_W_0F10_P_1 */
9025     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9026   },
9027   {
9028     /* VEX_W_0F10_P_2 */
9029     { "vmovupd",        { XM, EXx } },
9030   },
9031   {
9032     /* VEX_W_0F10_P_3 */
9033     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9034   },
9035   {
9036     /* VEX_W_0F11_P_0 */
9037     { "vmovups",        { EXxS, XM } },
9038   },
9039   {
9040     /* VEX_W_0F11_P_1 */
9041     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9042   },
9043   {
9044     /* VEX_W_0F11_P_2 */
9045     { "vmovupd",        { EXxS, XM } },
9046   },
9047   {
9048     /* VEX_W_0F11_P_3 */
9049     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9050   },
9051   {
9052     /* VEX_W_0F12_P_0_M_0 */
9053     { "vmovlps",        { XM, Vex128, EXq } },
9054   },
9055   {
9056     /* VEX_W_0F12_P_0_M_1 */
9057     { "vmovhlps",       { XM, Vex128, EXq } },
9058   },
9059   {
9060     /* VEX_W_0F12_P_1 */
9061     { "vmovsldup",      { XM, EXx } },
9062   },
9063   {
9064     /* VEX_W_0F12_P_2 */
9065     { "vmovlpd",        { XM, Vex128, EXq } },
9066   },
9067   {
9068     /* VEX_W_0F12_P_3 */
9069     { "vmovddup",       { XM, EXymmq } },
9070   },
9071   {
9072     /* VEX_W_0F13_M_0 */
9073     { "vmovlpX",        { EXq, XM } },
9074   },
9075   {
9076     /* VEX_W_0F14 */
9077     { "vunpcklpX",      { XM, Vex, EXx } },
9078   },
9079   {
9080     /* VEX_W_0F15 */
9081     { "vunpckhpX",      { XM, Vex, EXx } },
9082   },
9083   {
9084     /* VEX_W_0F16_P_0_M_0 */
9085     { "vmovhps",        { XM, Vex128, EXq } },
9086   },
9087   {
9088     /* VEX_W_0F16_P_0_M_1 */
9089     { "vmovlhps",       { XM, Vex128, EXq } },
9090   },
9091   {
9092     /* VEX_W_0F16_P_1 */
9093     { "vmovshdup",      { XM, EXx } },
9094   },
9095   {
9096     /* VEX_W_0F16_P_2 */
9097     { "vmovhpd",        { XM, Vex128, EXq } },
9098   },
9099   {
9100     /* VEX_W_0F17_M_0 */
9101     { "vmovhpX",        { EXq, XM } },
9102   },
9103   {
9104     /* VEX_W_0F28 */
9105     { "vmovapX",        { XM, EXx } },
9106   },
9107   {
9108     /* VEX_W_0F29 */
9109     { "vmovapX",        { EXxS, XM } },
9110   },
9111   {
9112     /* VEX_W_0F2B_M_0 */
9113     { "vmovntpX",       { Mx, XM } },
9114   },
9115   {
9116     /* VEX_W_0F2E_P_0 */
9117     { "vucomiss",       { XMScalar, EXdScalar } },
9118   },
9119   {
9120     /* VEX_W_0F2E_P_2 */
9121     { "vucomisd",       { XMScalar, EXqScalar } },
9122   },
9123   {
9124     /* VEX_W_0F2F_P_0 */
9125     { "vcomiss",        { XMScalar, EXdScalar } },
9126   },
9127   {
9128     /* VEX_W_0F2F_P_2 */
9129     { "vcomisd",        { XMScalar, EXqScalar } },
9130   },
9131   {
9132     /* VEX_W_0F50_M_0 */
9133     { "vmovmskpX",      { Gdq, XS } },
9134   },
9135   {
9136     /* VEX_W_0F51_P_0 */
9137     { "vsqrtps",        { XM, EXx } },
9138   },
9139   {
9140     /* VEX_W_0F51_P_1 */
9141     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9142   },
9143   {
9144     /* VEX_W_0F51_P_2  */
9145     { "vsqrtpd",        { XM, EXx } },
9146   },
9147   {
9148     /* VEX_W_0F51_P_3 */
9149     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9150   },
9151   {
9152     /* VEX_W_0F52_P_0 */
9153     { "vrsqrtps",       { XM, EXx } },
9154   },
9155   {
9156     /* VEX_W_0F52_P_1 */
9157     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9158   },
9159   {
9160     /* VEX_W_0F53_P_0  */
9161     { "vrcpps",         { XM, EXx } },
9162   },
9163   {
9164     /* VEX_W_0F53_P_1  */
9165     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9166   },
9167   {
9168     /* VEX_W_0F58_P_0  */
9169     { "vaddps",         { XM, Vex, EXx } },
9170   },
9171   {
9172     /* VEX_W_0F58_P_1  */
9173     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9174   },
9175   {
9176     /* VEX_W_0F58_P_2  */
9177     { "vaddpd",         { XM, Vex, EXx } },
9178   },
9179   {
9180     /* VEX_W_0F58_P_3  */
9181     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9182   },
9183   {
9184     /* VEX_W_0F59_P_0  */
9185     { "vmulps",         { XM, Vex, EXx } },
9186   },
9187   {
9188     /* VEX_W_0F59_P_1  */
9189     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9190   },
9191   {
9192     /* VEX_W_0F59_P_2  */
9193     { "vmulpd",         { XM, Vex, EXx } },
9194   },
9195   {
9196     /* VEX_W_0F59_P_3  */
9197     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9198   },
9199   {
9200     /* VEX_W_0F5A_P_0  */
9201     { "vcvtps2pd",      { XM, EXxmmq } },
9202   },
9203   {
9204     /* VEX_W_0F5A_P_1  */
9205     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9206   },
9207   {
9208     /* VEX_W_0F5A_P_3  */
9209     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9210   },
9211   {
9212     /* VEX_W_0F5B_P_0  */
9213     { "vcvtdq2ps",      { XM, EXx } },
9214   },
9215   {
9216     /* VEX_W_0F5B_P_1  */
9217     { "vcvttps2dq",     { XM, EXx } },
9218   },
9219   {
9220     /* VEX_W_0F5B_P_2  */
9221     { "vcvtps2dq",      { XM, EXx } },
9222   },
9223   {
9224     /* VEX_W_0F5C_P_0  */
9225     { "vsubps",         { XM, Vex, EXx } },
9226   },
9227   {
9228     /* VEX_W_0F5C_P_1  */
9229     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9230   },
9231   {
9232     /* VEX_W_0F5C_P_2  */
9233     { "vsubpd",         { XM, Vex, EXx } },
9234   },
9235   {
9236     /* VEX_W_0F5C_P_3  */
9237     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9238   },
9239   {
9240     /* VEX_W_0F5D_P_0  */
9241     { "vminps",         { XM, Vex, EXx } },
9242   },
9243   {
9244     /* VEX_W_0F5D_P_1  */
9245     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9246   },
9247   {
9248     /* VEX_W_0F5D_P_2  */
9249     { "vminpd",         { XM, Vex, EXx } },
9250   },
9251   {
9252     /* VEX_W_0F5D_P_3  */
9253     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9254   },
9255   {
9256     /* VEX_W_0F5E_P_0  */
9257     { "vdivps",         { XM, Vex, EXx } },
9258   },
9259   {
9260     /* VEX_W_0F5E_P_1  */
9261     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9262   },
9263   {
9264     /* VEX_W_0F5E_P_2  */
9265     { "vdivpd",         { XM, Vex, EXx } },
9266   },
9267   {
9268     /* VEX_W_0F5E_P_3  */
9269     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9270   },
9271   {
9272     /* VEX_W_0F5F_P_0  */
9273     { "vmaxps",         { XM, Vex, EXx } },
9274   },
9275   {
9276     /* VEX_W_0F5F_P_1  */
9277     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9278   },
9279   {
9280     /* VEX_W_0F5F_P_2  */
9281     { "vmaxpd",         { XM, Vex, EXx } },
9282   },
9283   {
9284     /* VEX_W_0F5F_P_3  */
9285     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9286   },
9287   {
9288     /* VEX_W_0F60_P_2  */
9289     { "vpunpcklbw",     { XM, Vex, EXx } },
9290   },
9291   {
9292     /* VEX_W_0F61_P_2  */
9293     { "vpunpcklwd",     { XM, Vex, EXx } },
9294   },
9295   {
9296     /* VEX_W_0F62_P_2  */
9297     { "vpunpckldq",     { XM, Vex, EXx } },
9298   },
9299   {
9300     /* VEX_W_0F63_P_2  */
9301     { "vpacksswb",      { XM, Vex, EXx } },
9302   },
9303   {
9304     /* VEX_W_0F64_P_2  */
9305     { "vpcmpgtb",       { XM, Vex, EXx } },
9306   },
9307   {
9308     /* VEX_W_0F65_P_2  */
9309     { "vpcmpgtw",       { XM, Vex, EXx } },
9310   },
9311   {
9312     /* VEX_W_0F66_P_2  */
9313     { "vpcmpgtd",       { XM, Vex, EXx } },
9314   },
9315   {
9316     /* VEX_W_0F67_P_2  */
9317     { "vpackuswb",      { XM, Vex, EXx } },
9318   },
9319   {
9320     /* VEX_W_0F68_P_2  */
9321     { "vpunpckhbw",     { XM, Vex, EXx } },
9322   },
9323   {
9324     /* VEX_W_0F69_P_2  */
9325     { "vpunpckhwd",     { XM, Vex, EXx } },
9326   },
9327   {
9328     /* VEX_W_0F6A_P_2  */
9329     { "vpunpckhdq",     { XM, Vex, EXx } },
9330   },
9331   {
9332     /* VEX_W_0F6B_P_2  */
9333     { "vpackssdw",      { XM, Vex, EXx } },
9334   },
9335   {
9336     /* VEX_W_0F6C_P_2  */
9337     { "vpunpcklqdq",    { XM, Vex, EXx } },
9338   },
9339   {
9340     /* VEX_W_0F6D_P_2  */
9341     { "vpunpckhqdq",    { XM, Vex, EXx } },
9342   },
9343   {
9344     /* VEX_W_0F6F_P_1  */
9345     { "vmovdqu",        { XM, EXx } },
9346   },
9347   {
9348     /* VEX_W_0F6F_P_2  */
9349     { "vmovdqa",        { XM, EXx } },
9350   },
9351   {
9352     /* VEX_W_0F70_P_1 */
9353     { "vpshufhw",       { XM, EXx, Ib } },
9354   },
9355   {
9356     /* VEX_W_0F70_P_2 */
9357     { "vpshufd",        { XM, EXx, Ib } },
9358   },
9359   {
9360     /* VEX_W_0F70_P_3 */
9361     { "vpshuflw",       { XM, EXx, Ib } },
9362   },
9363   {
9364     /* VEX_W_0F71_R_2_P_2  */
9365     { "vpsrlw",         { Vex, XS, Ib } },
9366   },
9367   {
9368     /* VEX_W_0F71_R_4_P_2  */
9369     { "vpsraw",         { Vex, XS, Ib } },
9370   },
9371   {
9372     /* VEX_W_0F71_R_6_P_2  */
9373     { "vpsllw",         { Vex, XS, Ib } },
9374   },
9375   {
9376     /* VEX_W_0F72_R_2_P_2  */
9377     { "vpsrld",         { Vex, XS, Ib } },
9378   },
9379   {
9380     /* VEX_W_0F72_R_4_P_2  */
9381     { "vpsrad",         { Vex, XS, Ib } },
9382   },
9383   {
9384     /* VEX_W_0F72_R_6_P_2  */
9385     { "vpslld",         { Vex, XS, Ib } },
9386   },
9387   {
9388     /* VEX_W_0F73_R_2_P_2  */
9389     { "vpsrlq",         { Vex, XS, Ib } },
9390   },
9391   {
9392     /* VEX_W_0F73_R_3_P_2  */
9393     { "vpsrldq",        { Vex, XS, Ib } },
9394   },
9395   {
9396     /* VEX_W_0F73_R_6_P_2  */
9397     { "vpsllq",         { Vex, XS, Ib } },
9398   },
9399   {
9400     /* VEX_W_0F73_R_7_P_2  */
9401     { "vpslldq",        { Vex, XS, Ib } },
9402   },
9403   {
9404     /* VEX_W_0F74_P_2 */
9405     { "vpcmpeqb",       { XM, Vex, EXx } },
9406   },
9407   {
9408     /* VEX_W_0F75_P_2 */
9409     { "vpcmpeqw",       { XM, Vex, EXx } },
9410   },
9411   {
9412     /* VEX_W_0F76_P_2 */
9413     { "vpcmpeqd",       { XM, Vex, EXx } },
9414   },
9415   {
9416     /* VEX_W_0F77_P_0 */
9417     { "",               { VZERO } },
9418   },
9419   {
9420     /* VEX_W_0F7C_P_2 */
9421     { "vhaddpd",        { XM, Vex, EXx } },
9422   },
9423   {
9424     /* VEX_W_0F7C_P_3 */
9425     { "vhaddps",        { XM, Vex, EXx } },
9426   },
9427   {
9428     /* VEX_W_0F7D_P_2 */
9429     { "vhsubpd",        { XM, Vex, EXx } },
9430   },
9431   {
9432     /* VEX_W_0F7D_P_3 */
9433     { "vhsubps",        { XM, Vex, EXx } },
9434   },
9435   {
9436     /* VEX_W_0F7E_P_1 */
9437     { "vmovq",          { XMScalar, EXqScalar } },
9438   },
9439   {
9440     /* VEX_W_0F7F_P_1 */
9441     { "vmovdqu",        { EXxS, XM } },
9442   },
9443   {
9444     /* VEX_W_0F7F_P_2 */
9445     { "vmovdqa",        { EXxS, XM } },
9446   },
9447   {
9448     /* VEX_W_0FAE_R_2_M_0 */
9449     { "vldmxcsr",       { Md } },
9450   },
9451   {
9452     /* VEX_W_0FAE_R_3_M_0 */
9453     { "vstmxcsr",       { Md } },
9454   },
9455   {
9456     /* VEX_W_0FC2_P_0 */
9457     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9458   },
9459   {
9460     /* VEX_W_0FC2_P_1 */
9461     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9462   },
9463   {
9464     /* VEX_W_0FC2_P_2 */
9465     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9466   },
9467   {
9468     /* VEX_W_0FC2_P_3 */
9469     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9470   },
9471   {
9472     /* VEX_W_0FC4_P_2 */
9473     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9474   },
9475   {
9476     /* VEX_W_0FC5_P_2 */
9477     { "vpextrw",        { Gdq, XS, Ib } },
9478   },
9479   {
9480     /* VEX_W_0FD0_P_2 */
9481     { "vaddsubpd",      { XM, Vex, EXx } },
9482   },
9483   {
9484     /* VEX_W_0FD0_P_3 */
9485     { "vaddsubps",      { XM, Vex, EXx } },
9486   },
9487   {
9488     /* VEX_W_0FD1_P_2 */
9489     { "vpsrlw",         { XM, Vex, EXxmm } },
9490   },
9491   {
9492     /* VEX_W_0FD2_P_2 */
9493     { "vpsrld",         { XM, Vex, EXxmm } },
9494   },
9495   {
9496     /* VEX_W_0FD3_P_2 */
9497     { "vpsrlq",         { XM, Vex, EXxmm } },
9498   },
9499   {
9500     /* VEX_W_0FD4_P_2 */
9501     { "vpaddq",         { XM, Vex, EXx } },
9502   },
9503   {
9504     /* VEX_W_0FD5_P_2 */
9505     { "vpmullw",        { XM, Vex, EXx } },
9506   },
9507   {
9508     /* VEX_W_0FD6_P_2 */
9509     { "vmovq",          { EXqScalarS, XMScalar } },
9510   },
9511   {
9512     /* VEX_W_0FD7_P_2_M_1 */
9513     { "vpmovmskb",      { Gdq, XS } },
9514   },
9515   {
9516     /* VEX_W_0FD8_P_2 */
9517     { "vpsubusb",       { XM, Vex, EXx } },
9518   },
9519   {
9520     /* VEX_W_0FD9_P_2 */
9521     { "vpsubusw",       { XM, Vex, EXx } },
9522   },
9523   {
9524     /* VEX_W_0FDA_P_2 */
9525     { "vpminub",        { XM, Vex, EXx } },
9526   },
9527   {
9528     /* VEX_W_0FDB_P_2 */
9529     { "vpand",          { XM, Vex, EXx } },
9530   },
9531   {
9532     /* VEX_W_0FDC_P_2 */
9533     { "vpaddusb",       { XM, Vex, EXx } },
9534   },
9535   {
9536     /* VEX_W_0FDD_P_2 */
9537     { "vpaddusw",       { XM, Vex, EXx } },
9538   },
9539   {
9540     /* VEX_W_0FDE_P_2 */
9541     { "vpmaxub",        { XM, Vex, EXx } },
9542   },
9543   {
9544     /* VEX_W_0FDF_P_2 */
9545     { "vpandn",         { XM, Vex, EXx } },
9546   },
9547   {
9548     /* VEX_W_0FE0_P_2  */
9549     { "vpavgb",         { XM, Vex, EXx } },
9550   },
9551   {
9552     /* VEX_W_0FE1_P_2  */
9553     { "vpsraw",         { XM, Vex, EXxmm } },
9554   },
9555   {
9556     /* VEX_W_0FE2_P_2  */
9557     { "vpsrad",         { XM, Vex, EXxmm } },
9558   },
9559   {
9560     /* VEX_W_0FE3_P_2  */
9561     { "vpavgw",         { XM, Vex, EXx } },
9562   },
9563   {
9564     /* VEX_W_0FE4_P_2  */
9565     { "vpmulhuw",       { XM, Vex, EXx } },
9566   },
9567   {
9568     /* VEX_W_0FE5_P_2  */
9569     { "vpmulhw",        { XM, Vex, EXx } },
9570   },
9571   {
9572     /* VEX_W_0FE6_P_1  */
9573     { "vcvtdq2pd",      { XM, EXxmmq } },
9574   },
9575   {
9576     /* VEX_W_0FE6_P_2  */
9577     { "vcvttpd2dq%XY",  { XMM, EXx } },
9578   },
9579   {
9580     /* VEX_W_0FE6_P_3  */
9581     { "vcvtpd2dq%XY",   { XMM, EXx } },
9582   },
9583   {
9584     /* VEX_W_0FE7_P_2_M_0 */
9585     { "vmovntdq",       { Mx, XM } },
9586   },
9587   {
9588     /* VEX_W_0FE8_P_2  */
9589     { "vpsubsb",        { XM, Vex, EXx } },
9590   },
9591   {
9592     /* VEX_W_0FE9_P_2  */
9593     { "vpsubsw",        { XM, Vex, EXx } },
9594   },
9595   {
9596     /* VEX_W_0FEA_P_2  */
9597     { "vpminsw",        { XM, Vex, EXx } },
9598   },
9599   {
9600     /* VEX_W_0FEB_P_2  */
9601     { "vpor",           { XM, Vex, EXx } },
9602   },
9603   {
9604     /* VEX_W_0FEC_P_2  */
9605     { "vpaddsb",        { XM, Vex, EXx } },
9606   },
9607   {
9608     /* VEX_W_0FED_P_2  */
9609     { "vpaddsw",        { XM, Vex, EXx } },
9610   },
9611   {
9612     /* VEX_W_0FEE_P_2  */
9613     { "vpmaxsw",        { XM, Vex, EXx } },
9614   },
9615   {
9616     /* VEX_W_0FEF_P_2  */
9617     { "vpxor",          { XM, Vex, EXx } },
9618   },
9619   {
9620     /* VEX_W_0FF0_P_3_M_0 */
9621     { "vlddqu",         { XM, M } },
9622   },
9623   {
9624     /* VEX_W_0FF1_P_2 */
9625     { "vpsllw",         { XM, Vex, EXxmm } },
9626   },
9627   {
9628     /* VEX_W_0FF2_P_2 */
9629     { "vpslld",         { XM, Vex, EXxmm } },
9630   },
9631   {
9632     /* VEX_W_0FF3_P_2 */
9633     { "vpsllq",         { XM, Vex, EXxmm } },
9634   },
9635   {
9636     /* VEX_W_0FF4_P_2 */
9637     { "vpmuludq",       { XM, Vex, EXx } },
9638   },
9639   {
9640     /* VEX_W_0FF5_P_2 */
9641     { "vpmaddwd",       { XM, Vex, EXx } },
9642   },
9643   {
9644     /* VEX_W_0FF6_P_2 */
9645     { "vpsadbw",        { XM, Vex, EXx } },
9646   },
9647   {
9648     /* VEX_W_0FF7_P_2 */
9649     { "vmaskmovdqu",    { XM, XS } },
9650   },
9651   {
9652     /* VEX_W_0FF8_P_2 */
9653     { "vpsubb",         { XM, Vex, EXx } },
9654   },
9655   {
9656     /* VEX_W_0FF9_P_2 */
9657     { "vpsubw",         { XM, Vex, EXx } },
9658   },
9659   {
9660     /* VEX_W_0FFA_P_2 */
9661     { "vpsubd",         { XM, Vex, EXx } },
9662   },
9663   {
9664     /* VEX_W_0FFB_P_2 */
9665     { "vpsubq",         { XM, Vex, EXx } },
9666   },
9667   {
9668     /* VEX_W_0FFC_P_2 */
9669     { "vpaddb",         { XM, Vex, EXx } },
9670   },
9671   {
9672     /* VEX_W_0FFD_P_2 */
9673     { "vpaddw",         { XM, Vex, EXx } },
9674   },
9675   {
9676     /* VEX_W_0FFE_P_2 */
9677     { "vpaddd",         { XM, Vex, EXx } },
9678   },
9679   {
9680     /* VEX_W_0F3800_P_2  */
9681     { "vpshufb",        { XM, Vex, EXx } },
9682   },
9683   {
9684     /* VEX_W_0F3801_P_2  */
9685     { "vphaddw",        { XM, Vex, EXx } },
9686   },
9687   {
9688     /* VEX_W_0F3802_P_2  */
9689     { "vphaddd",        { XM, Vex, EXx } },
9690   },
9691   {
9692     /* VEX_W_0F3803_P_2  */
9693     { "vphaddsw",       { XM, Vex, EXx } },
9694   },
9695   {
9696     /* VEX_W_0F3804_P_2  */
9697     { "vpmaddubsw",     { XM, Vex, EXx } },
9698   },
9699   {
9700     /* VEX_W_0F3805_P_2  */
9701     { "vphsubw",        { XM, Vex, EXx } },
9702   },
9703   {
9704     /* VEX_W_0F3806_P_2  */
9705     { "vphsubd",        { XM, Vex, EXx } },
9706   },
9707   {
9708     /* VEX_W_0F3807_P_2  */
9709     { "vphsubsw",       { XM, Vex, EXx } },
9710   },
9711   {
9712     /* VEX_W_0F3808_P_2  */
9713     { "vpsignb",        { XM, Vex, EXx } },
9714   },
9715   {
9716     /* VEX_W_0F3809_P_2  */
9717     { "vpsignw",        { XM, Vex, EXx } },
9718   },
9719   {
9720     /* VEX_W_0F380A_P_2  */
9721     { "vpsignd",        { XM, Vex, EXx } },
9722   },
9723   {
9724     /* VEX_W_0F380B_P_2  */
9725     { "vpmulhrsw",      { XM, Vex, EXx } },
9726   },
9727   {
9728     /* VEX_W_0F380C_P_2  */
9729     { "vpermilps",      { XM, Vex, EXx } },
9730   },
9731   {
9732     /* VEX_W_0F380D_P_2  */
9733     { "vpermilpd",      { XM, Vex, EXx } },
9734   },
9735   {
9736     /* VEX_W_0F380E_P_2  */
9737     { "vtestps",        { XM, EXx } },
9738   },
9739   {
9740     /* VEX_W_0F380F_P_2  */
9741     { "vtestpd",        { XM, EXx } },
9742   },
9743   {
9744     /* VEX_W_0F3816_P_2  */
9745     { "vpermps",        { XM, Vex, EXx } },
9746   },
9747   {
9748     /* VEX_W_0F3817_P_2 */
9749     { "vptest",         { XM, EXx } },
9750   },
9751   {
9752     /* VEX_W_0F3818_P_2 */
9753     { "vbroadcastss",   { XM, EXxmm_md } },
9754   },
9755   {
9756     /* VEX_W_0F3819_P_2 */
9757     { "vbroadcastsd",   { XM, EXxmm_mq } },
9758   },
9759   {
9760     /* VEX_W_0F381A_P_2_M_0 */
9761     { "vbroadcastf128", { XM, Mxmm } },
9762   },
9763   {
9764     /* VEX_W_0F381C_P_2 */
9765     { "vpabsb",         { XM, EXx } },
9766   },
9767   {
9768     /* VEX_W_0F381D_P_2 */
9769     { "vpabsw",         { XM, EXx } },
9770   },
9771   {
9772     /* VEX_W_0F381E_P_2 */
9773     { "vpabsd",         { XM, EXx } },
9774   },
9775   {
9776     /* VEX_W_0F3820_P_2 */
9777     { "vpmovsxbw",      { XM, EXxmmq } },
9778   },
9779   {
9780     /* VEX_W_0F3821_P_2 */
9781     { "vpmovsxbd",      { XM, EXxmmqd } },
9782   },
9783   {
9784     /* VEX_W_0F3822_P_2 */
9785     { "vpmovsxbq",      { XM, EXxmmdw } },
9786   },
9787   {
9788     /* VEX_W_0F3823_P_2 */
9789     { "vpmovsxwd",      { XM, EXxmmq } },
9790   },
9791   {
9792     /* VEX_W_0F3824_P_2 */
9793     { "vpmovsxwq",      { XM, EXxmmqd } },
9794   },
9795   {
9796     /* VEX_W_0F3825_P_2 */
9797     { "vpmovsxdq",      { XM, EXxmmq } },
9798   },
9799   {
9800     /* VEX_W_0F3828_P_2 */
9801     { "vpmuldq",        { XM, Vex, EXx } },
9802   },
9803   {
9804     /* VEX_W_0F3829_P_2 */
9805     { "vpcmpeqq",       { XM, Vex, EXx } },
9806   },
9807   {
9808     /* VEX_W_0F382A_P_2_M_0 */
9809     { "vmovntdqa",      { XM, Mx } },
9810   },
9811   {
9812     /* VEX_W_0F382B_P_2 */
9813     { "vpackusdw",      { XM, Vex, EXx } },
9814   },
9815   {
9816     /* VEX_W_0F382C_P_2_M_0 */
9817     { "vmaskmovps",     { XM, Vex, Mx } },
9818   },
9819   {
9820     /* VEX_W_0F382D_P_2_M_0 */
9821     { "vmaskmovpd",     { XM, Vex, Mx } },
9822   },
9823   {
9824     /* VEX_W_0F382E_P_2_M_0 */
9825     { "vmaskmovps",     { Mx, Vex, XM } },
9826   },
9827   {
9828     /* VEX_W_0F382F_P_2_M_0 */
9829     { "vmaskmovpd",     { Mx, Vex, XM } },
9830   },
9831   {
9832     /* VEX_W_0F3830_P_2 */
9833     { "vpmovzxbw",      { XM, EXxmmq } },
9834   },
9835   {
9836     /* VEX_W_0F3831_P_2 */
9837     { "vpmovzxbd",      { XM, EXxmmqd } },
9838   },
9839   {
9840     /* VEX_W_0F3832_P_2 */
9841     { "vpmovzxbq",      { XM, EXxmmdw } },
9842   },
9843   {
9844     /* VEX_W_0F3833_P_2 */
9845     { "vpmovzxwd",      { XM, EXxmmq } },
9846   },
9847   {
9848     /* VEX_W_0F3834_P_2 */
9849     { "vpmovzxwq",      { XM, EXxmmqd } },
9850   },
9851   {
9852     /* VEX_W_0F3835_P_2 */
9853     { "vpmovzxdq",      { XM, EXxmmq } },
9854   },
9855   {
9856     /* VEX_W_0F3836_P_2  */
9857     { "vpermd",         { XM, Vex, EXx } },
9858   },
9859   {
9860     /* VEX_W_0F3837_P_2 */
9861     { "vpcmpgtq",       { XM, Vex, EXx } },
9862   },
9863   {
9864     /* VEX_W_0F3838_P_2 */
9865     { "vpminsb",        { XM, Vex, EXx } },
9866   },
9867   {
9868     /* VEX_W_0F3839_P_2 */
9869     { "vpminsd",        { XM, Vex, EXx } },
9870   },
9871   {
9872     /* VEX_W_0F383A_P_2 */
9873     { "vpminuw",        { XM, Vex, EXx } },
9874   },
9875   {
9876     /* VEX_W_0F383B_P_2 */
9877     { "vpminud",        { XM, Vex, EXx } },
9878   },
9879   {
9880     /* VEX_W_0F383C_P_2 */
9881     { "vpmaxsb",        { XM, Vex, EXx } },
9882   },
9883   {
9884     /* VEX_W_0F383D_P_2 */
9885     { "vpmaxsd",        { XM, Vex, EXx } },
9886   },
9887   {
9888     /* VEX_W_0F383E_P_2 */
9889     { "vpmaxuw",        { XM, Vex, EXx } },
9890   },
9891   {
9892     /* VEX_W_0F383F_P_2 */
9893     { "vpmaxud",        { XM, Vex, EXx } },
9894   },
9895   {
9896     /* VEX_W_0F3840_P_2 */
9897     { "vpmulld",        { XM, Vex, EXx } },
9898   },
9899   {
9900     /* VEX_W_0F3841_P_2 */
9901     { "vphminposuw",    { XM, EXx } },
9902   },
9903   {
9904     /* VEX_W_0F3846_P_2 */
9905     { "vpsravd",        { XM, Vex, EXx } },
9906   },
9907   {
9908     /* VEX_W_0F3858_P_2 */
9909     { "vpbroadcastd", { XM, EXxmm_md } },
9910   },
9911   {
9912     /* VEX_W_0F3859_P_2 */
9913     { "vpbroadcastq",   { XM, EXxmm_mq } },
9914   },
9915   {
9916     /* VEX_W_0F385A_P_2_M_0 */
9917     { "vbroadcasti128", { XM, Mxmm } },
9918   },
9919   {
9920     /* VEX_W_0F3878_P_2 */
9921     { "vpbroadcastb",   { XM, EXxmm_mb } },
9922   },
9923   {
9924     /* VEX_W_0F3879_P_2 */
9925     { "vpbroadcastw",   { XM, EXxmm_mw } },
9926   },
9927   {
9928     /* VEX_W_0F38DB_P_2 */
9929     { "vaesimc",        { XM, EXx } },
9930   },
9931   {
9932     /* VEX_W_0F38DC_P_2 */
9933     { "vaesenc",        { XM, Vex128, EXx } },
9934   },
9935   {
9936     /* VEX_W_0F38DD_P_2 */
9937     { "vaesenclast",    { XM, Vex128, EXx } },
9938   },
9939   {
9940     /* VEX_W_0F38DE_P_2 */
9941     { "vaesdec",        { XM, Vex128, EXx } },
9942   },
9943   {
9944     /* VEX_W_0F38DF_P_2 */
9945     { "vaesdeclast",    { XM, Vex128, EXx } },
9946   },
9947   {
9948     /* VEX_W_0F3A00_P_2 */
9949     { Bad_Opcode },
9950     { "vpermq",         { XM, EXx, Ib } },
9951   },
9952   {
9953     /* VEX_W_0F3A01_P_2 */
9954     { Bad_Opcode },
9955     { "vpermpd",        { XM, EXx, Ib } },
9956   },
9957   {
9958     /* VEX_W_0F3A02_P_2 */
9959     { "vpblendd",       { XM, Vex, EXx, Ib } },
9960   },
9961   {
9962     /* VEX_W_0F3A04_P_2 */
9963     { "vpermilps",      { XM, EXx, Ib } },
9964   },
9965   {
9966     /* VEX_W_0F3A05_P_2 */
9967     { "vpermilpd",      { XM, EXx, Ib } },
9968   },
9969   {
9970     /* VEX_W_0F3A06_P_2 */
9971     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
9972   },
9973   {
9974     /* VEX_W_0F3A08_P_2 */
9975     { "vroundps",       { XM, EXx, Ib } },
9976   },
9977   {
9978     /* VEX_W_0F3A09_P_2 */
9979     { "vroundpd",       { XM, EXx, Ib } },
9980   },
9981   {
9982     /* VEX_W_0F3A0A_P_2 */
9983     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
9984   },
9985   {
9986     /* VEX_W_0F3A0B_P_2 */
9987     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
9988   },
9989   {
9990     /* VEX_W_0F3A0C_P_2 */
9991     { "vblendps",       { XM, Vex, EXx, Ib } },
9992   },
9993   {
9994     /* VEX_W_0F3A0D_P_2 */
9995     { "vblendpd",       { XM, Vex, EXx, Ib } },
9996   },
9997   {
9998     /* VEX_W_0F3A0E_P_2 */
9999     { "vpblendw",       { XM, Vex, EXx, Ib } },
10000   },
10001   {
10002     /* VEX_W_0F3A0F_P_2 */
10003     { "vpalignr",       { XM, Vex, EXx, Ib } },
10004   },
10005   {
10006     /* VEX_W_0F3A14_P_2 */
10007     { "vpextrb",        { Edqb, XM, Ib } },
10008   },
10009   {
10010     /* VEX_W_0F3A15_P_2 */
10011     { "vpextrw",        { Edqw, XM, Ib } },
10012   },
10013   {
10014     /* VEX_W_0F3A18_P_2 */
10015     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10016   },
10017   {
10018     /* VEX_W_0F3A19_P_2 */
10019     { "vextractf128",   { EXxmm, XM, Ib } },
10020   },
10021   {
10022     /* VEX_W_0F3A20_P_2 */
10023     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10024   },
10025   {
10026     /* VEX_W_0F3A21_P_2 */
10027     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10028   },
10029   {
10030     /* VEX_W_0F3A38_P_2 */
10031     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
10032   },
10033   {
10034     /* VEX_W_0F3A39_P_2 */
10035     { "vextracti128",   { EXxmm, XM, Ib } },
10036   },
10037   {
10038     /* VEX_W_0F3A40_P_2 */
10039     { "vdpps",          { XM, Vex, EXx, Ib } },
10040   },
10041   {
10042     /* VEX_W_0F3A41_P_2 */
10043     { "vdppd",          { XM, Vex128, EXx, Ib } },
10044   },
10045   {
10046     /* VEX_W_0F3A42_P_2 */
10047     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10048   },
10049   {
10050     /* VEX_W_0F3A44_P_2 */
10051     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10052   },
10053   {
10054     /* VEX_W_0F3A46_P_2 */
10055     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
10056   },
10057   {
10058     /* VEX_W_0F3A48_P_2 */
10059     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10060     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10061   },
10062   {
10063     /* VEX_W_0F3A49_P_2 */
10064     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10065     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10066   },
10067   {
10068     /* VEX_W_0F3A4A_P_2 */
10069     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10070   },
10071   {
10072     /* VEX_W_0F3A4B_P_2 */
10073     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10074   },
10075   {
10076     /* VEX_W_0F3A4C_P_2 */
10077     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
10078   },
10079   {
10080     /* VEX_W_0F3A60_P_2 */
10081     { "vpcmpestrm",     { XM, EXx, Ib } },
10082   },
10083   {
10084     /* VEX_W_0F3A61_P_2 */
10085     { "vpcmpestri",     { XM, EXx, Ib } },
10086   },
10087   {
10088     /* VEX_W_0F3A62_P_2 */
10089     { "vpcmpistrm",     { XM, EXx, Ib } },
10090   },
10091   {
10092     /* VEX_W_0F3A63_P_2 */
10093     { "vpcmpistri",     { XM, EXx, Ib } },
10094   },
10095   {
10096     /* VEX_W_0F3ADF_P_2 */
10097     { "vaeskeygenassist", { XM, EXx, Ib } },
10098   },
10099 };
10100
10101 static const struct dis386 mod_table[][2] = {
10102   {
10103     /* MOD_8D */
10104     { "leaS",           { Gv, M } },
10105   },
10106   {
10107     /* MOD_C6_REG_7 */
10108     { Bad_Opcode },
10109     { RM_TABLE (RM_C6_REG_7) },
10110   },
10111   {
10112     /* MOD_C7_REG_7 */
10113     { Bad_Opcode },
10114     { RM_TABLE (RM_C7_REG_7) },
10115   },
10116   {
10117     /* MOD_0F01_REG_0 */
10118     { X86_64_TABLE (X86_64_0F01_REG_0) },
10119     { RM_TABLE (RM_0F01_REG_0) },
10120   },
10121   {
10122     /* MOD_0F01_REG_1 */
10123     { X86_64_TABLE (X86_64_0F01_REG_1) },
10124     { RM_TABLE (RM_0F01_REG_1) },
10125   },
10126   {
10127     /* MOD_0F01_REG_2 */
10128     { X86_64_TABLE (X86_64_0F01_REG_2) },
10129     { RM_TABLE (RM_0F01_REG_2) },
10130   },
10131   {
10132     /* MOD_0F01_REG_3 */
10133     { X86_64_TABLE (X86_64_0F01_REG_3) },
10134     { RM_TABLE (RM_0F01_REG_3) },
10135   },
10136   {
10137     /* MOD_0F01_REG_7 */
10138     { "invlpg",         { Mb } },
10139     { RM_TABLE (RM_0F01_REG_7) },
10140   },
10141   {
10142     /* MOD_0F12_PREFIX_0 */
10143     { "movlps",         { XM, EXq } },
10144     { "movhlps",        { XM, EXq } },
10145   },
10146   {
10147     /* MOD_0F13 */
10148     { "movlpX",         { EXq, XM } },
10149   },
10150   {
10151     /* MOD_0F16_PREFIX_0 */
10152     { "movhps",         { XM, EXq } },
10153     { "movlhps",        { XM, EXq } },
10154   },
10155   {
10156     /* MOD_0F17 */
10157     { "movhpX",         { EXq, XM } },
10158   },
10159   {
10160     /* MOD_0F18_REG_0 */
10161     { "prefetchnta",    { Mb } },
10162   },
10163   {
10164     /* MOD_0F18_REG_1 */
10165     { "prefetcht0",     { Mb } },
10166   },
10167   {
10168     /* MOD_0F18_REG_2 */
10169     { "prefetcht1",     { Mb } },
10170   },
10171   {
10172     /* MOD_0F18_REG_3 */
10173     { "prefetcht2",     { Mb } },
10174   },
10175   {
10176     /* MOD_0F20 */
10177     { Bad_Opcode },
10178     { "movZ",           { Rm, Cm } },
10179   },
10180   {
10181     /* MOD_0F21 */
10182     { Bad_Opcode },
10183     { "movZ",           { Rm, Dm } },
10184   },
10185   {
10186     /* MOD_0F22 */
10187     { Bad_Opcode },
10188     { "movZ",           { Cm, Rm } },
10189   },
10190   {
10191     /* MOD_0F23 */
10192     { Bad_Opcode },
10193     { "movZ",           { Dm, Rm } },
10194   },
10195   {
10196     /* MOD_0F24 */
10197     { Bad_Opcode },
10198     { "movL",           { Rd, Td } },
10199   },
10200   {
10201     /* MOD_0F26 */
10202     { Bad_Opcode },
10203     { "movL",           { Td, Rd } },
10204   },
10205   {
10206     /* MOD_0F2B_PREFIX_0 */
10207     {"movntps",         { Mx, XM } },
10208   },
10209   {
10210     /* MOD_0F2B_PREFIX_1 */
10211     {"movntss",         { Md, XM } },
10212   },
10213   {
10214     /* MOD_0F2B_PREFIX_2 */
10215     {"movntpd",         { Mx, XM } },
10216   },
10217   {
10218     /* MOD_0F2B_PREFIX_3 */
10219     {"movntsd",         { Mq, XM } },
10220   },
10221   {
10222     /* MOD_0F51 */
10223     { Bad_Opcode },
10224     { "movmskpX",       { Gdq, XS } },
10225   },
10226   {
10227     /* MOD_0F71_REG_2 */
10228     { Bad_Opcode },
10229     { "psrlw",          { MS, Ib } },
10230   },
10231   {
10232     /* MOD_0F71_REG_4 */
10233     { Bad_Opcode },
10234     { "psraw",          { MS, Ib } },
10235   },
10236   {
10237     /* MOD_0F71_REG_6 */
10238     { Bad_Opcode },
10239     { "psllw",          { MS, Ib } },
10240   },
10241   {
10242     /* MOD_0F72_REG_2 */
10243     { Bad_Opcode },
10244     { "psrld",          { MS, Ib } },
10245   },
10246   {
10247     /* MOD_0F72_REG_4 */
10248     { Bad_Opcode },
10249     { "psrad",          { MS, Ib } },
10250   },
10251   {
10252     /* MOD_0F72_REG_6 */
10253     { Bad_Opcode },
10254     { "pslld",          { MS, Ib } },
10255   },
10256   {
10257     /* MOD_0F73_REG_2 */
10258     { Bad_Opcode },
10259     { "psrlq",          { MS, Ib } },
10260   },
10261   {
10262     /* MOD_0F73_REG_3 */
10263     { Bad_Opcode },
10264     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10265   },
10266   {
10267     /* MOD_0F73_REG_6 */
10268     { Bad_Opcode },
10269     { "psllq",          { MS, Ib } },
10270   },
10271   {
10272     /* MOD_0F73_REG_7 */
10273     { Bad_Opcode },
10274     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10275   },
10276   {
10277     /* MOD_0FAE_REG_0 */
10278     { "fxsave",         { FXSAVE } },
10279     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10280   },
10281   {
10282     /* MOD_0FAE_REG_1 */
10283     { "fxrstor",        { FXSAVE } },
10284     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10285   },
10286   {
10287     /* MOD_0FAE_REG_2 */
10288     { "ldmxcsr",        { Md } },
10289     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10290   },
10291   {
10292     /* MOD_0FAE_REG_3 */
10293     { "stmxcsr",        { Md } },
10294     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10295   },
10296   {
10297     /* MOD_0FAE_REG_4 */
10298     { "xsave",          { FXSAVE } },
10299   },
10300   {
10301     /* MOD_0FAE_REG_5 */
10302     { "xrstor",         { FXSAVE } },
10303     { RM_TABLE (RM_0FAE_REG_5) },
10304   },
10305   {
10306     /* MOD_0FAE_REG_6 */
10307     { "xsaveopt",       { FXSAVE } },
10308     { RM_TABLE (RM_0FAE_REG_6) },
10309   },
10310   {
10311     /* MOD_0FAE_REG_7 */
10312     { "clflush",        { Mb } },
10313     { RM_TABLE (RM_0FAE_REG_7) },
10314   },
10315   {
10316     /* MOD_0FB2 */
10317     { "lssS",           { Gv, Mp } },
10318   },
10319   {
10320     /* MOD_0FB4 */
10321     { "lfsS",           { Gv, Mp } },
10322   },
10323   {
10324     /* MOD_0FB5 */
10325     { "lgsS",           { Gv, Mp } },
10326   },
10327   {
10328     /* MOD_0FC7_REG_6 */
10329     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10330     { "rdrand",         { Ev } },
10331   },
10332   {
10333     /* MOD_0FC7_REG_7 */
10334     { "vmptrst",        { Mq } },
10335     { "rdseed",         { Ev } },
10336   },
10337   {
10338     /* MOD_0FD7 */
10339     { Bad_Opcode },
10340     { "pmovmskb",       { Gdq, MS } },
10341   },
10342   {
10343     /* MOD_0FE7_PREFIX_2 */
10344     { "movntdq",        { Mx, XM } },
10345   },
10346   {
10347     /* MOD_0FF0_PREFIX_3 */
10348     { "lddqu",          { XM, M } },
10349   },
10350   {
10351     /* MOD_0F382A_PREFIX_2 */
10352     { "movntdqa",       { XM, Mx } },
10353   },
10354   {
10355     /* MOD_62_32BIT */
10356     { "bound{S|}",      { Gv, Ma } },
10357   },
10358   {
10359     /* MOD_C4_32BIT */
10360     { "lesS",           { Gv, Mp } },
10361     { VEX_C4_TABLE (VEX_0F) },
10362   },
10363   {
10364     /* MOD_C5_32BIT */
10365     { "ldsS",           { Gv, Mp } },
10366     { VEX_C5_TABLE (VEX_0F) },
10367   },
10368   {
10369     /* MOD_VEX_0F12_PREFIX_0 */
10370     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10371     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10372   },
10373   {
10374     /* MOD_VEX_0F13 */
10375     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10376   },
10377   {
10378     /* MOD_VEX_0F16_PREFIX_0 */
10379     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10380     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10381   },
10382   {
10383     /* MOD_VEX_0F17 */
10384     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10385   },
10386   {
10387     /* MOD_VEX_0F2B */
10388     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10389   },
10390   {
10391     /* MOD_VEX_0F50 */
10392     { Bad_Opcode },
10393     { VEX_W_TABLE (VEX_W_0F50_M_0) },
10394   },
10395   {
10396     /* MOD_VEX_0F71_REG_2 */
10397     { Bad_Opcode },
10398     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10399   },
10400   {
10401     /* MOD_VEX_0F71_REG_4 */
10402     { Bad_Opcode },
10403     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10404   },
10405   {
10406     /* MOD_VEX_0F71_REG_6 */
10407     { Bad_Opcode },
10408     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10409   },
10410   {
10411     /* MOD_VEX_0F72_REG_2 */
10412     { Bad_Opcode },
10413     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10414   },
10415   {
10416     /* MOD_VEX_0F72_REG_4 */
10417     { Bad_Opcode },
10418     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10419   },
10420   {
10421     /* MOD_VEX_0F72_REG_6 */
10422     { Bad_Opcode },
10423     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10424   },
10425   {
10426     /* MOD_VEX_0F73_REG_2 */
10427     { Bad_Opcode },
10428     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10429   },
10430   {
10431     /* MOD_VEX_0F73_REG_3 */
10432     { Bad_Opcode },
10433     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10434   },
10435   {
10436     /* MOD_VEX_0F73_REG_6 */
10437     { Bad_Opcode },
10438     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10439   },
10440   {
10441     /* MOD_VEX_0F73_REG_7 */
10442     { Bad_Opcode },
10443     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10444   },
10445   {
10446     /* MOD_VEX_0FAE_REG_2 */
10447     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10448   },
10449   {
10450     /* MOD_VEX_0FAE_REG_3 */
10451     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10452   },
10453   {
10454     /* MOD_VEX_0FD7_PREFIX_2 */
10455     { Bad_Opcode },
10456     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
10457   },
10458   {
10459     /* MOD_VEX_0FE7_PREFIX_2 */
10460     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10461   },
10462   {
10463     /* MOD_VEX_0FF0_PREFIX_3 */
10464     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10465   },
10466   {
10467     /* MOD_VEX_0F381A_PREFIX_2 */
10468     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10469   },
10470   {
10471     /* MOD_VEX_0F382A_PREFIX_2 */
10472     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
10473   },
10474   {
10475     /* MOD_VEX_0F382C_PREFIX_2 */
10476     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10477   },
10478   {
10479     /* MOD_VEX_0F382D_PREFIX_2 */
10480     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10481   },
10482   {
10483     /* MOD_VEX_0F382E_PREFIX_2 */
10484     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10485   },
10486   {
10487     /* MOD_VEX_0F382F_PREFIX_2 */
10488     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10489   },
10490   {
10491     /* MOD_VEX_0F385A_PREFIX_2 */
10492     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10493   },
10494   {
10495     /* MOD_VEX_0F388C_PREFIX_2 */
10496     { "vpmaskmov%LW",   { XM, Vex, Mx } },
10497   },
10498   {
10499     /* MOD_VEX_0F388E_PREFIX_2 */
10500     { "vpmaskmov%LW",   { Mx, Vex, XM } },
10501   },
10502 };
10503
10504 static const struct dis386 rm_table[][8] = {
10505   {
10506     /* RM_C6_REG_7 */
10507     { "xabort",         { Skip_MODRM, Ib } },
10508   },
10509   {
10510     /* RM_C7_REG_7 */
10511     { "xbeginT",        { Skip_MODRM, Jv } },
10512   },
10513   {
10514     /* RM_0F01_REG_0 */
10515     { Bad_Opcode },
10516     { "vmcall",         { Skip_MODRM } },
10517     { "vmlaunch",       { Skip_MODRM } },
10518     { "vmresume",       { Skip_MODRM } },
10519     { "vmxoff",         { Skip_MODRM } },
10520   },
10521   {
10522     /* RM_0F01_REG_1 */
10523     { "monitor",        { { OP_Monitor, 0 } } },
10524     { "mwait",          { { OP_Mwait, 0 } } },
10525   },
10526   {
10527     /* RM_0F01_REG_2 */
10528     { "xgetbv",         { Skip_MODRM } },
10529     { "xsetbv",         { Skip_MODRM } },
10530     { Bad_Opcode },
10531     { Bad_Opcode },
10532     { "vmfunc",         { Skip_MODRM } },
10533     { "xend",           { Skip_MODRM } },
10534     { "xtest",          { Skip_MODRM } },
10535     { Bad_Opcode },
10536   },
10537   {
10538     /* RM_0F01_REG_3 */
10539     { "vmrun",          { Skip_MODRM } },
10540     { "vmmcall",        { Skip_MODRM } },
10541     { "vmload",         { Skip_MODRM } },
10542     { "vmsave",         { Skip_MODRM } },
10543     { "stgi",           { Skip_MODRM } },
10544     { "clgi",           { Skip_MODRM } },
10545     { "skinit",         { Skip_MODRM } },
10546     { "invlpga",        { Skip_MODRM } },
10547   },
10548   {
10549     /* RM_0F01_REG_7 */
10550     { "swapgs",         { Skip_MODRM } },
10551     { "rdtscp",         { Skip_MODRM } },
10552   },
10553   {
10554     /* RM_0FAE_REG_5 */
10555     { "lfence",         { Skip_MODRM } },
10556   },
10557   {
10558     /* RM_0FAE_REG_6 */
10559     { "mfence",         { Skip_MODRM } },
10560   },
10561   {
10562     /* RM_0FAE_REG_7 */
10563     { "sfence",         { Skip_MODRM } },
10564   },
10565 };
10566
10567 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10568
10569 /* We use the high bit to indicate different name for the same
10570    prefix.  */
10571 #define ADDR16_PREFIX   (0x67 | 0x100)
10572 #define ADDR32_PREFIX   (0x67 | 0x200)
10573 #define DATA16_PREFIX   (0x66 | 0x100)
10574 #define DATA32_PREFIX   (0x66 | 0x200)
10575 #define REP_PREFIX      (0xf3 | 0x100)
10576 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10577 #define XRELEASE_PREFIX (0xf3 | 0x400)
10578
10579 static int
10580 ckprefix (void)
10581 {
10582   int newrex, i, length;
10583   rex = 0;
10584   rex_ignored = 0;
10585   prefixes = 0;
10586   used_prefixes = 0;
10587   rex_used = 0;
10588   last_lock_prefix = -1;
10589   last_repz_prefix = -1;
10590   last_repnz_prefix = -1;
10591   last_data_prefix = -1;
10592   last_addr_prefix = -1;
10593   last_rex_prefix = -1;
10594   last_seg_prefix = -1;
10595   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10596     all_prefixes[i] = 0;
10597   i = 0;
10598   length = 0;
10599   /* The maximum instruction length is 15bytes.  */
10600   while (length < MAX_CODE_LENGTH - 1)
10601     {
10602       FETCH_DATA (the_info, codep + 1);
10603       newrex = 0;
10604       switch (*codep)
10605         {
10606         /* REX prefixes family.  */
10607         case 0x40:
10608         case 0x41:
10609         case 0x42:
10610         case 0x43:
10611         case 0x44:
10612         case 0x45:
10613         case 0x46:
10614         case 0x47:
10615         case 0x48:
10616         case 0x49:
10617         case 0x4a:
10618         case 0x4b:
10619         case 0x4c:
10620         case 0x4d:
10621         case 0x4e:
10622         case 0x4f:
10623           if (address_mode == mode_64bit)
10624             newrex = *codep;
10625           else
10626             return 1;
10627           last_rex_prefix = i;
10628           break;
10629         case 0xf3:
10630           prefixes |= PREFIX_REPZ;
10631           last_repz_prefix = i;
10632           break;
10633         case 0xf2:
10634           prefixes |= PREFIX_REPNZ;
10635           last_repnz_prefix = i;
10636           break;
10637         case 0xf0:
10638           prefixes |= PREFIX_LOCK;
10639           last_lock_prefix = i;
10640           break;
10641         case 0x2e:
10642           prefixes |= PREFIX_CS;
10643           last_seg_prefix = i;
10644           break;
10645         case 0x36:
10646           prefixes |= PREFIX_SS;
10647           last_seg_prefix = i;
10648           break;
10649         case 0x3e:
10650           prefixes |= PREFIX_DS;
10651           last_seg_prefix = i;
10652           break;
10653         case 0x26:
10654           prefixes |= PREFIX_ES;
10655           last_seg_prefix = i;
10656           break;
10657         case 0x64:
10658           prefixes |= PREFIX_FS;
10659           last_seg_prefix = i;
10660           break;
10661         case 0x65:
10662           prefixes |= PREFIX_GS;
10663           last_seg_prefix = i;
10664           break;
10665         case 0x66:
10666           prefixes |= PREFIX_DATA;
10667           last_data_prefix = i;
10668           break;
10669         case 0x67:
10670           prefixes |= PREFIX_ADDR;
10671           last_addr_prefix = i;
10672           break;
10673         case FWAIT_OPCODE:
10674           /* fwait is really an instruction.  If there are prefixes
10675              before the fwait, they belong to the fwait, *not* to the
10676              following instruction.  */
10677           if (prefixes || rex)
10678             {
10679               prefixes |= PREFIX_FWAIT;
10680               codep++;
10681               return 1;
10682             }
10683           prefixes = PREFIX_FWAIT;
10684           break;
10685         default:
10686           return 1;
10687         }
10688       /* Rex is ignored when followed by another prefix.  */
10689       if (rex)
10690         {
10691           rex_used = rex;
10692           return 1;
10693         }
10694       if (*codep != FWAIT_OPCODE)
10695         all_prefixes[i++] = *codep;
10696       rex = newrex;
10697       codep++;
10698       length++;
10699     }
10700   return 0;
10701 }
10702
10703 static int
10704 seg_prefix (int pref)
10705 {
10706   switch (pref)
10707     {
10708     case 0x2e:
10709       return PREFIX_CS;
10710     case 0x36:
10711       return PREFIX_SS;
10712     case 0x3e:
10713       return PREFIX_DS;
10714     case 0x26:
10715       return PREFIX_ES;
10716     case 0x64:
10717       return PREFIX_FS;
10718     case 0x65:
10719       return PREFIX_GS;
10720     default:
10721       return 0;
10722     }
10723 }
10724
10725 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10726    prefix byte.  */
10727
10728 static const char *
10729 prefix_name (int pref, int sizeflag)
10730 {
10731   static const char *rexes [16] =
10732     {
10733       "rex",            /* 0x40 */
10734       "rex.B",          /* 0x41 */
10735       "rex.X",          /* 0x42 */
10736       "rex.XB",         /* 0x43 */
10737       "rex.R",          /* 0x44 */
10738       "rex.RB",         /* 0x45 */
10739       "rex.RX",         /* 0x46 */
10740       "rex.RXB",        /* 0x47 */
10741       "rex.W",          /* 0x48 */
10742       "rex.WB",         /* 0x49 */
10743       "rex.WX",         /* 0x4a */
10744       "rex.WXB",        /* 0x4b */
10745       "rex.WR",         /* 0x4c */
10746       "rex.WRB",        /* 0x4d */
10747       "rex.WRX",        /* 0x4e */
10748       "rex.WRXB",       /* 0x4f */
10749     };
10750
10751   switch (pref)
10752     {
10753     /* REX prefixes family.  */
10754     case 0x40:
10755     case 0x41:
10756     case 0x42:
10757     case 0x43:
10758     case 0x44:
10759     case 0x45:
10760     case 0x46:
10761     case 0x47:
10762     case 0x48:
10763     case 0x49:
10764     case 0x4a:
10765     case 0x4b:
10766     case 0x4c:
10767     case 0x4d:
10768     case 0x4e:
10769     case 0x4f:
10770       return rexes [pref - 0x40];
10771     case 0xf3:
10772       return "repz";
10773     case 0xf2:
10774       return "repnz";
10775     case 0xf0:
10776       return "lock";
10777     case 0x2e:
10778       return "cs";
10779     case 0x36:
10780       return "ss";
10781     case 0x3e:
10782       return "ds";
10783     case 0x26:
10784       return "es";
10785     case 0x64:
10786       return "fs";
10787     case 0x65:
10788       return "gs";
10789     case 0x66:
10790       return (sizeflag & DFLAG) ? "data16" : "data32";
10791     case 0x67:
10792       if (address_mode == mode_64bit)
10793         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10794       else
10795         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10796     case FWAIT_OPCODE:
10797       return "fwait";
10798     case ADDR16_PREFIX:
10799       return "addr16";
10800     case ADDR32_PREFIX:
10801       return "addr32";
10802     case DATA16_PREFIX:
10803       return "data16";
10804     case DATA32_PREFIX:
10805       return "data32";
10806     case REP_PREFIX:
10807       return "rep";
10808     case XACQUIRE_PREFIX:
10809       return "xacquire";
10810     case XRELEASE_PREFIX:
10811       return "xrelease";
10812     default:
10813       return NULL;
10814     }
10815 }
10816
10817 static char op_out[MAX_OPERANDS][100];
10818 static int op_ad, op_index[MAX_OPERANDS];
10819 static int two_source_ops;
10820 static bfd_vma op_address[MAX_OPERANDS];
10821 static bfd_vma op_riprel[MAX_OPERANDS];
10822 static bfd_vma start_pc;
10823
10824 /*
10825  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10826  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10827  *   section of the "Virtual 8086 Mode" chapter.)
10828  * 'pc' should be the address of this instruction, it will
10829  *   be used to print the target address if this is a relative jump or call
10830  * The function returns the length of this instruction in bytes.
10831  */
10832
10833 static char intel_syntax;
10834 static char intel_mnemonic = !SYSV386_COMPAT;
10835 static char open_char;
10836 static char close_char;
10837 static char separator_char;
10838 static char scale_char;
10839
10840 /* Here for backwards compatibility.  When gdb stops using
10841    print_insn_i386_att and print_insn_i386_intel these functions can
10842    disappear, and print_insn_i386 be merged into print_insn.  */
10843 int
10844 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10845 {
10846   intel_syntax = 0;
10847
10848   return print_insn (pc, info);
10849 }
10850
10851 int
10852 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10853 {
10854   intel_syntax = 1;
10855
10856   return print_insn (pc, info);
10857 }
10858
10859 int
10860 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10861 {
10862   intel_syntax = -1;
10863
10864   return print_insn (pc, info);
10865 }
10866
10867 void
10868 print_i386_disassembler_options (FILE *stream)
10869 {
10870   fprintf (stream, _("\n\
10871 The following i386/x86-64 specific disassembler options are supported for use\n\
10872 with the -M switch (multiple options should be separated by commas):\n"));
10873
10874   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10875   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10876   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10877   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10878   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10879   fprintf (stream, _("  att-mnemonic\n"
10880                      "              Display instruction in AT&T mnemonic\n"));
10881   fprintf (stream, _("  intel-mnemonic\n"
10882                      "              Display instruction in Intel mnemonic\n"));
10883   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10884   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10885   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10886   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10887   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10888   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10889 }
10890
10891 /* Bad opcode.  */
10892 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10893
10894 /* Get a pointer to struct dis386 with a valid name.  */
10895
10896 static const struct dis386 *
10897 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10898 {
10899   int vindex, vex_table_index;
10900
10901   if (dp->name != NULL)
10902     return dp;
10903
10904   switch (dp->op[0].bytemode)
10905     {
10906     case USE_REG_TABLE:
10907       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10908       break;
10909
10910     case USE_MOD_TABLE:
10911       vindex = modrm.mod == 0x3 ? 1 : 0;
10912       dp = &mod_table[dp->op[1].bytemode][vindex];
10913       break;
10914
10915     case USE_RM_TABLE:
10916       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10917       break;
10918
10919     case USE_PREFIX_TABLE:
10920       if (need_vex)
10921         {
10922           /* The prefix in VEX is implicit.  */
10923           switch (vex.prefix)
10924             {
10925             case 0:
10926               vindex = 0;
10927               break;
10928             case REPE_PREFIX_OPCODE:
10929               vindex = 1;
10930               break;
10931             case DATA_PREFIX_OPCODE:
10932               vindex = 2;
10933               break;
10934             case REPNE_PREFIX_OPCODE:
10935               vindex = 3;
10936               break;
10937             default:
10938               abort ();
10939               break;
10940             }
10941         }
10942       else
10943         {
10944           vindex = 0;
10945           used_prefixes |= (prefixes & PREFIX_REPZ);
10946           if (prefixes & PREFIX_REPZ)
10947             {
10948               vindex = 1;
10949               all_prefixes[last_repz_prefix] = 0;
10950             }
10951           else
10952             {
10953               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10954                  PREFIX_DATA.  */
10955               used_prefixes |= (prefixes & PREFIX_REPNZ);
10956               if (prefixes & PREFIX_REPNZ)
10957                 {
10958                   vindex = 3;
10959                   all_prefixes[last_repnz_prefix] = 0;
10960                 }
10961               else
10962                 {
10963                   used_prefixes |= (prefixes & PREFIX_DATA);
10964                   if (prefixes & PREFIX_DATA)
10965                     {
10966                       vindex = 2;
10967                       all_prefixes[last_data_prefix] = 0;
10968                     }
10969                 }
10970             }
10971         }
10972       dp = &prefix_table[dp->op[1].bytemode][vindex];
10973       break;
10974
10975     case USE_X86_64_TABLE:
10976       vindex = address_mode == mode_64bit ? 1 : 0;
10977       dp = &x86_64_table[dp->op[1].bytemode][vindex];
10978       break;
10979
10980     case USE_3BYTE_TABLE:
10981       FETCH_DATA (info, codep + 2);
10982       vindex = *codep++;
10983       dp = &three_byte_table[dp->op[1].bytemode][vindex];
10984       modrm.mod = (*codep >> 6) & 3;
10985       modrm.reg = (*codep >> 3) & 7;
10986       modrm.rm = *codep & 7;
10987       break;
10988
10989     case USE_VEX_LEN_TABLE:
10990       if (!need_vex)
10991         abort ();
10992
10993       switch (vex.length)
10994         {
10995         case 128:
10996           vindex = 0;
10997           break;
10998         case 256:
10999           vindex = 1;
11000           break;
11001         default:
11002           abort ();
11003           break;
11004         }
11005
11006       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11007       break;
11008
11009     case USE_XOP_8F_TABLE:
11010       FETCH_DATA (info, codep + 3);
11011       /* All bits in the REX prefix are ignored.  */
11012       rex_ignored = rex;
11013       rex = ~(*codep >> 5) & 0x7;
11014
11015       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11016       switch ((*codep & 0x1f))
11017         {
11018         default:
11019           dp = &bad_opcode;
11020           return dp;
11021         case 0x8:
11022           vex_table_index = XOP_08;
11023           break;
11024         case 0x9:
11025           vex_table_index = XOP_09;
11026           break;
11027         case 0xa:
11028           vex_table_index = XOP_0A;
11029           break;
11030         }
11031       codep++;
11032       vex.w = *codep & 0x80;
11033       if (vex.w && address_mode == mode_64bit)
11034         rex |= REX_W;
11035
11036       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11037       if (address_mode != mode_64bit
11038           && vex.register_specifier > 0x7)
11039         {
11040           dp = &bad_opcode;
11041           return dp;
11042         }
11043
11044       vex.length = (*codep & 0x4) ? 256 : 128;
11045       switch ((*codep & 0x3))
11046         {
11047         case 0:
11048           vex.prefix = 0;
11049           break;
11050         case 1:
11051           vex.prefix = DATA_PREFIX_OPCODE;
11052           break;
11053         case 2:
11054           vex.prefix = REPE_PREFIX_OPCODE;
11055           break;
11056         case 3:
11057           vex.prefix = REPNE_PREFIX_OPCODE;
11058           break;
11059         }
11060       need_vex = 1;
11061       need_vex_reg = 1;
11062       codep++;
11063       vindex = *codep++;
11064       dp = &xop_table[vex_table_index][vindex];
11065
11066       FETCH_DATA (info, codep + 1);
11067       modrm.mod = (*codep >> 6) & 3;
11068       modrm.reg = (*codep >> 3) & 7;
11069       modrm.rm = *codep & 7;
11070       break;
11071
11072     case USE_VEX_C4_TABLE:
11073       FETCH_DATA (info, codep + 3);
11074       /* All bits in the REX prefix are ignored.  */
11075       rex_ignored = rex;
11076       rex = ~(*codep >> 5) & 0x7;
11077       switch ((*codep & 0x1f))
11078         {
11079         default:
11080           dp = &bad_opcode;
11081           return dp;
11082         case 0x1:
11083           vex_table_index = VEX_0F;
11084           break;
11085         case 0x2:
11086           vex_table_index = VEX_0F38;
11087           break;
11088         case 0x3:
11089           vex_table_index = VEX_0F3A;
11090           break;
11091         }
11092       codep++;
11093       vex.w = *codep & 0x80;
11094       if (vex.w && address_mode == mode_64bit)
11095         rex |= REX_W;
11096
11097       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11098       if (address_mode != mode_64bit
11099           && vex.register_specifier > 0x7)
11100         {
11101           dp = &bad_opcode;
11102           return dp;
11103         }
11104
11105       vex.length = (*codep & 0x4) ? 256 : 128;
11106       switch ((*codep & 0x3))
11107         {
11108         case 0:
11109           vex.prefix = 0;
11110           break;
11111         case 1:
11112           vex.prefix = DATA_PREFIX_OPCODE;
11113           break;
11114         case 2:
11115           vex.prefix = REPE_PREFIX_OPCODE;
11116           break;
11117         case 3:
11118           vex.prefix = REPNE_PREFIX_OPCODE;
11119           break;
11120         }
11121       need_vex = 1;
11122       need_vex_reg = 1;
11123       codep++;
11124       vindex = *codep++;
11125       dp = &vex_table[vex_table_index][vindex];
11126       /* There is no MODRM byte for VEX [82|77].  */
11127       if (vindex != 0x77 && vindex != 0x82)
11128         {
11129           FETCH_DATA (info, codep + 1);
11130           modrm.mod = (*codep >> 6) & 3;
11131           modrm.reg = (*codep >> 3) & 7;
11132           modrm.rm = *codep & 7;
11133         }
11134       break;
11135
11136     case USE_VEX_C5_TABLE:
11137       FETCH_DATA (info, codep + 2);
11138       /* All bits in the REX prefix are ignored.  */
11139       rex_ignored = rex;
11140       rex = (*codep & 0x80) ? 0 : REX_R;
11141
11142       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11143       if (address_mode != mode_64bit
11144           && vex.register_specifier > 0x7)
11145         {
11146           dp = &bad_opcode;
11147           return dp;
11148         }
11149
11150       vex.w = 0;
11151
11152       vex.length = (*codep & 0x4) ? 256 : 128;
11153       switch ((*codep & 0x3))
11154         {
11155         case 0:
11156           vex.prefix = 0;
11157           break;
11158         case 1:
11159           vex.prefix = DATA_PREFIX_OPCODE;
11160           break;
11161         case 2:
11162           vex.prefix = REPE_PREFIX_OPCODE;
11163           break;
11164         case 3:
11165           vex.prefix = REPNE_PREFIX_OPCODE;
11166           break;
11167         }
11168       need_vex = 1;
11169       need_vex_reg = 1;
11170       codep++;
11171       vindex = *codep++;
11172       dp = &vex_table[dp->op[1].bytemode][vindex];
11173       /* There is no MODRM byte for VEX [82|77].  */
11174       if (vindex != 0x77 && vindex != 0x82)
11175         {
11176           FETCH_DATA (info, codep + 1);
11177           modrm.mod = (*codep >> 6) & 3;
11178           modrm.reg = (*codep >> 3) & 7;
11179           modrm.rm = *codep & 7;
11180         }
11181       break;
11182
11183     case USE_VEX_W_TABLE:
11184       if (!need_vex)
11185         abort ();
11186
11187       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11188       break;
11189
11190     case 0:
11191       dp = &bad_opcode;
11192       break;
11193
11194     default:
11195       abort ();
11196     }
11197
11198   if (dp->name != NULL)
11199     return dp;
11200   else
11201     return get_valid_dis386 (dp, info);
11202 }
11203
11204 static void
11205 get_sib (disassemble_info *info)
11206 {
11207   /* If modrm.mod == 3, operand must be register.  */
11208   if (need_modrm
11209       && address_mode != mode_16bit
11210       && modrm.mod != 3
11211       && modrm.rm == 4)
11212     {
11213       FETCH_DATA (info, codep + 2);
11214       sib.index = (codep [1] >> 3) & 7;
11215       sib.scale = (codep [1] >> 6) & 3;
11216       sib.base = codep [1] & 7;
11217     }
11218 }
11219
11220 static int
11221 print_insn (bfd_vma pc, disassemble_info *info)
11222 {
11223   const struct dis386 *dp;
11224   int i;
11225   char *op_txt[MAX_OPERANDS];
11226   int needcomma;
11227   int sizeflag;
11228   const char *p;
11229   struct dis_private priv;
11230   int prefix_length;
11231   int default_prefixes;
11232
11233   priv.orig_sizeflag = AFLAG | DFLAG;
11234   if ((info->mach & bfd_mach_i386_i386) != 0)
11235     address_mode = mode_32bit;
11236   else if (info->mach == bfd_mach_i386_i8086)
11237     {
11238       address_mode = mode_16bit;
11239       priv.orig_sizeflag = 0;
11240     }
11241   else
11242     address_mode = mode_64bit;
11243
11244   if (intel_syntax == (char) -1)
11245     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11246
11247   for (p = info->disassembler_options; p != NULL; )
11248     {
11249       if (CONST_STRNEQ (p, "x86-64"))
11250         {
11251           address_mode = mode_64bit;
11252           priv.orig_sizeflag = AFLAG | DFLAG;
11253         }
11254       else if (CONST_STRNEQ (p, "i386"))
11255         {
11256           address_mode = mode_32bit;
11257           priv.orig_sizeflag = AFLAG | DFLAG;
11258         }
11259       else if (CONST_STRNEQ (p, "i8086"))
11260         {
11261           address_mode = mode_16bit;
11262           priv.orig_sizeflag = 0;
11263         }
11264       else if (CONST_STRNEQ (p, "intel"))
11265         {
11266           intel_syntax = 1;
11267           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11268             intel_mnemonic = 1;
11269         }
11270       else if (CONST_STRNEQ (p, "att"))
11271         {
11272           intel_syntax = 0;
11273           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11274             intel_mnemonic = 0;
11275         }
11276       else if (CONST_STRNEQ (p, "addr"))
11277         {
11278           if (address_mode == mode_64bit)
11279             {
11280               if (p[4] == '3' && p[5] == '2')
11281                 priv.orig_sizeflag &= ~AFLAG;
11282               else if (p[4] == '6' && p[5] == '4')
11283                 priv.orig_sizeflag |= AFLAG;
11284             }
11285           else
11286             {
11287               if (p[4] == '1' && p[5] == '6')
11288                 priv.orig_sizeflag &= ~AFLAG;
11289               else if (p[4] == '3' && p[5] == '2')
11290                 priv.orig_sizeflag |= AFLAG;
11291             }
11292         }
11293       else if (CONST_STRNEQ (p, "data"))
11294         {
11295           if (p[4] == '1' && p[5] == '6')
11296             priv.orig_sizeflag &= ~DFLAG;
11297           else if (p[4] == '3' && p[5] == '2')
11298             priv.orig_sizeflag |= DFLAG;
11299         }
11300       else if (CONST_STRNEQ (p, "suffix"))
11301         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11302
11303       p = strchr (p, ',');
11304       if (p != NULL)
11305         p++;
11306     }
11307
11308   if (intel_syntax)
11309     {
11310       names64 = intel_names64;
11311       names32 = intel_names32;
11312       names16 = intel_names16;
11313       names8 = intel_names8;
11314       names8rex = intel_names8rex;
11315       names_seg = intel_names_seg;
11316       names_mm = intel_names_mm;
11317       names_xmm = intel_names_xmm;
11318       names_ymm = intel_names_ymm;
11319       index64 = intel_index64;
11320       index32 = intel_index32;
11321       index16 = intel_index16;
11322       open_char = '[';
11323       close_char = ']';
11324       separator_char = '+';
11325       scale_char = '*';
11326     }
11327   else
11328     {
11329       names64 = att_names64;
11330       names32 = att_names32;
11331       names16 = att_names16;
11332       names8 = att_names8;
11333       names8rex = att_names8rex;
11334       names_seg = att_names_seg;
11335       names_mm = att_names_mm;
11336       names_xmm = att_names_xmm;
11337       names_ymm = att_names_ymm;
11338       index64 = att_index64;
11339       index32 = att_index32;
11340       index16 = att_index16;
11341       open_char = '(';
11342       close_char =  ')';
11343       separator_char = ',';
11344       scale_char = ',';
11345     }
11346
11347   /* The output looks better if we put 7 bytes on a line, since that
11348      puts most long word instructions on a single line.  Use 8 bytes
11349      for Intel L1OM.  */
11350   if ((info->mach & bfd_mach_l1om) != 0)
11351     info->bytes_per_line = 8;
11352   else
11353     info->bytes_per_line = 7;
11354
11355   info->private_data = &priv;
11356   priv.max_fetched = priv.the_buffer;
11357   priv.insn_start = pc;
11358
11359   obuf[0] = 0;
11360   for (i = 0; i < MAX_OPERANDS; ++i)
11361     {
11362       op_out[i][0] = 0;
11363       op_index[i] = -1;
11364     }
11365
11366   the_info = info;
11367   start_pc = pc;
11368   start_codep = priv.the_buffer;
11369   codep = priv.the_buffer;
11370
11371   if (setjmp (priv.bailout) != 0)
11372     {
11373       const char *name;
11374
11375       /* Getting here means we tried for data but didn't get it.  That
11376          means we have an incomplete instruction of some sort.  Just
11377          print the first byte as a prefix or a .byte pseudo-op.  */
11378       if (codep > priv.the_buffer)
11379         {
11380           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11381           if (name != NULL)
11382             (*info->fprintf_func) (info->stream, "%s", name);
11383           else
11384             {
11385               /* Just print the first byte as a .byte instruction.  */
11386               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11387                                      (unsigned int) priv.the_buffer[0]);
11388             }
11389
11390           return 1;
11391         }
11392
11393       return -1;
11394     }
11395
11396   obufp = obuf;
11397   sizeflag = priv.orig_sizeflag;
11398
11399   if (!ckprefix () || rex_used)
11400     {
11401       /* Too many prefixes or unused REX prefixes.  */
11402       for (i = 0;
11403            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11404            i++)
11405         (*info->fprintf_func) (info->stream, "%s",
11406                                prefix_name (all_prefixes[i], sizeflag));
11407       return 1;
11408     }
11409
11410   insn_codep = codep;
11411
11412   FETCH_DATA (info, codep + 1);
11413   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11414
11415   if (((prefixes & PREFIX_FWAIT)
11416        && ((*codep < 0xd8) || (*codep > 0xdf))))
11417     {
11418       (*info->fprintf_func) (info->stream, "fwait");
11419       return 1;
11420     }
11421
11422   if (*codep == 0x0f)
11423     {
11424       unsigned char threebyte;
11425       FETCH_DATA (info, codep + 2);
11426       threebyte = *++codep;
11427       dp = &dis386_twobyte[threebyte];
11428       need_modrm = twobyte_has_modrm[*codep];
11429       codep++;
11430     }
11431   else
11432     {
11433       dp = &dis386[*codep];
11434       need_modrm = onebyte_has_modrm[*codep];
11435       codep++;
11436     }
11437
11438   if ((prefixes & PREFIX_REPZ))
11439     used_prefixes |= PREFIX_REPZ;
11440   if ((prefixes & PREFIX_REPNZ))
11441     used_prefixes |= PREFIX_REPNZ;
11442   if ((prefixes & PREFIX_LOCK))
11443     used_prefixes |= PREFIX_LOCK;
11444
11445   default_prefixes = 0;
11446   if (prefixes & PREFIX_ADDR)
11447     {
11448       sizeflag ^= AFLAG;
11449       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11450         {
11451           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11452             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11453           else
11454             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11455           default_prefixes |= PREFIX_ADDR;
11456         }
11457     }
11458
11459   if ((prefixes & PREFIX_DATA))
11460     {
11461       sizeflag ^= DFLAG;
11462       if (dp->op[2].bytemode == cond_jump_mode
11463           && dp->op[0].bytemode == v_mode
11464           && !intel_syntax)
11465         {
11466           if (sizeflag & DFLAG)
11467             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11468           else
11469             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11470           default_prefixes |= PREFIX_DATA;
11471         }
11472       else if (rex & REX_W)
11473         {
11474           /* REX_W will override PREFIX_DATA.  */
11475           default_prefixes |= PREFIX_DATA;
11476         }
11477     }
11478
11479   if (need_modrm)
11480     {
11481       FETCH_DATA (info, codep + 1);
11482       modrm.mod = (*codep >> 6) & 3;
11483       modrm.reg = (*codep >> 3) & 7;
11484       modrm.rm = *codep & 7;
11485     }
11486
11487   need_vex = 0;
11488   need_vex_reg = 0;
11489   vex_w_done = 0;
11490
11491   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11492     {
11493       get_sib (info);
11494       dofloat (sizeflag);
11495     }
11496   else
11497     {
11498       dp = get_valid_dis386 (dp, info);
11499       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11500         {
11501           get_sib (info);
11502           for (i = 0; i < MAX_OPERANDS; ++i)
11503             {
11504               obufp = op_out[i];
11505               op_ad = MAX_OPERANDS - 1 - i;
11506               if (dp->op[i].rtn)
11507                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11508             }
11509         }
11510     }
11511
11512   /* See if any prefixes were not used.  If so, print the first one
11513      separately.  If we don't do this, we'll wind up printing an
11514      instruction stream which does not precisely correspond to the
11515      bytes we are disassembling.  */
11516   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11517     {
11518       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11519         if (all_prefixes[i])
11520           {
11521             const char *name;
11522             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11523             if (name == NULL)
11524               name = INTERNAL_DISASSEMBLER_ERROR;
11525             (*info->fprintf_func) (info->stream, "%s", name);
11526             return 1;
11527           }
11528     }
11529
11530   /* Check if the REX prefix is used.  */
11531   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11532     all_prefixes[last_rex_prefix] = 0;
11533
11534   /* Check if the SEG prefix is used.  */
11535   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11536                    | PREFIX_FS | PREFIX_GS)) != 0
11537       && (used_prefixes
11538           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11539     all_prefixes[last_seg_prefix] = 0;
11540
11541   /* Check if the ADDR prefix is used.  */
11542   if ((prefixes & PREFIX_ADDR) != 0
11543       && (used_prefixes & PREFIX_ADDR) != 0)
11544     all_prefixes[last_addr_prefix] = 0;
11545
11546   /* Check if the DATA prefix is used.  */
11547   if ((prefixes & PREFIX_DATA) != 0
11548       && (used_prefixes & PREFIX_DATA) != 0)
11549     all_prefixes[last_data_prefix] = 0;
11550
11551   prefix_length = 0;
11552   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11553     if (all_prefixes[i])
11554       {
11555         const char *name;
11556         name = prefix_name (all_prefixes[i], sizeflag);
11557         if (name == NULL)
11558           abort ();
11559         prefix_length += strlen (name) + 1;
11560         (*info->fprintf_func) (info->stream, "%s ", name);
11561       }
11562
11563   /* Check maximum code length.  */
11564   if ((codep - start_codep) > MAX_CODE_LENGTH)
11565     {
11566       (*info->fprintf_func) (info->stream, "(bad)");
11567       return MAX_CODE_LENGTH;
11568     }
11569
11570   obufp = mnemonicendp;
11571   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11572     oappend (" ");
11573   oappend (" ");
11574   (*info->fprintf_func) (info->stream, "%s", obuf);
11575
11576   /* The enter and bound instructions are printed with operands in the same
11577      order as the intel book; everything else is printed in reverse order.  */
11578   if (intel_syntax || two_source_ops)
11579     {
11580       bfd_vma riprel;
11581
11582       for (i = 0; i < MAX_OPERANDS; ++i)
11583         op_txt[i] = op_out[i];
11584
11585       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11586         {
11587           op_ad = op_index[i];
11588           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11589           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11590           riprel = op_riprel[i];
11591           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11592           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11593         }
11594     }
11595   else
11596     {
11597       for (i = 0; i < MAX_OPERANDS; ++i)
11598         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11599     }
11600
11601   needcomma = 0;
11602   for (i = 0; i < MAX_OPERANDS; ++i)
11603     if (*op_txt[i])
11604       {
11605         if (needcomma)
11606           (*info->fprintf_func) (info->stream, ",");
11607         if (op_index[i] != -1 && !op_riprel[i])
11608           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11609         else
11610           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11611         needcomma = 1;
11612       }
11613
11614   for (i = 0; i < MAX_OPERANDS; i++)
11615     if (op_index[i] != -1 && op_riprel[i])
11616       {
11617         (*info->fprintf_func) (info->stream, "        # ");
11618         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11619                                                 + op_address[op_index[i]]), info);
11620         break;
11621       }
11622   return codep - priv.the_buffer;
11623 }
11624
11625 static const char *float_mem[] = {
11626   /* d8 */
11627   "fadd{s|}",
11628   "fmul{s|}",
11629   "fcom{s|}",
11630   "fcomp{s|}",
11631   "fsub{s|}",
11632   "fsubr{s|}",
11633   "fdiv{s|}",
11634   "fdivr{s|}",
11635   /* d9 */
11636   "fld{s|}",
11637   "(bad)",
11638   "fst{s|}",
11639   "fstp{s|}",
11640   "fldenvIC",
11641   "fldcw",
11642   "fNstenvIC",
11643   "fNstcw",
11644   /* da */
11645   "fiadd{l|}",
11646   "fimul{l|}",
11647   "ficom{l|}",
11648   "ficomp{l|}",
11649   "fisub{l|}",
11650   "fisubr{l|}",
11651   "fidiv{l|}",
11652   "fidivr{l|}",
11653   /* db */
11654   "fild{l|}",
11655   "fisttp{l|}",
11656   "fist{l|}",
11657   "fistp{l|}",
11658   "(bad)",
11659   "fld{t||t|}",
11660   "(bad)",
11661   "fstp{t||t|}",
11662   /* dc */
11663   "fadd{l|}",
11664   "fmul{l|}",
11665   "fcom{l|}",
11666   "fcomp{l|}",
11667   "fsub{l|}",
11668   "fsubr{l|}",
11669   "fdiv{l|}",
11670   "fdivr{l|}",
11671   /* dd */
11672   "fld{l|}",
11673   "fisttp{ll|}",
11674   "fst{l||}",
11675   "fstp{l|}",
11676   "frstorIC",
11677   "(bad)",
11678   "fNsaveIC",
11679   "fNstsw",
11680   /* de */
11681   "fiadd",
11682   "fimul",
11683   "ficom",
11684   "ficomp",
11685   "fisub",
11686   "fisubr",
11687   "fidiv",
11688   "fidivr",
11689   /* df */
11690   "fild",
11691   "fisttp",
11692   "fist",
11693   "fistp",
11694   "fbld",
11695   "fild{ll|}",
11696   "fbstp",
11697   "fistp{ll|}",
11698 };
11699
11700 static const unsigned char float_mem_mode[] = {
11701   /* d8 */
11702   d_mode,
11703   d_mode,
11704   d_mode,
11705   d_mode,
11706   d_mode,
11707   d_mode,
11708   d_mode,
11709   d_mode,
11710   /* d9 */
11711   d_mode,
11712   0,
11713   d_mode,
11714   d_mode,
11715   0,
11716   w_mode,
11717   0,
11718   w_mode,
11719   /* da */
11720   d_mode,
11721   d_mode,
11722   d_mode,
11723   d_mode,
11724   d_mode,
11725   d_mode,
11726   d_mode,
11727   d_mode,
11728   /* db */
11729   d_mode,
11730   d_mode,
11731   d_mode,
11732   d_mode,
11733   0,
11734   t_mode,
11735   0,
11736   t_mode,
11737   /* dc */
11738   q_mode,
11739   q_mode,
11740   q_mode,
11741   q_mode,
11742   q_mode,
11743   q_mode,
11744   q_mode,
11745   q_mode,
11746   /* dd */
11747   q_mode,
11748   q_mode,
11749   q_mode,
11750   q_mode,
11751   0,
11752   0,
11753   0,
11754   w_mode,
11755   /* de */
11756   w_mode,
11757   w_mode,
11758   w_mode,
11759   w_mode,
11760   w_mode,
11761   w_mode,
11762   w_mode,
11763   w_mode,
11764   /* df */
11765   w_mode,
11766   w_mode,
11767   w_mode,
11768   w_mode,
11769   t_mode,
11770   q_mode,
11771   t_mode,
11772   q_mode
11773 };
11774
11775 #define ST { OP_ST, 0 }
11776 #define STi { OP_STi, 0 }
11777
11778 #define FGRPd9_2 NULL, { { NULL, 0 } }
11779 #define FGRPd9_4 NULL, { { NULL, 1 } }
11780 #define FGRPd9_5 NULL, { { NULL, 2 } }
11781 #define FGRPd9_6 NULL, { { NULL, 3 } }
11782 #define FGRPd9_7 NULL, { { NULL, 4 } }
11783 #define FGRPda_5 NULL, { { NULL, 5 } }
11784 #define FGRPdb_4 NULL, { { NULL, 6 } }
11785 #define FGRPde_3 NULL, { { NULL, 7 } }
11786 #define FGRPdf_4 NULL, { { NULL, 8 } }
11787
11788 static const struct dis386 float_reg[][8] = {
11789   /* d8 */
11790   {
11791     { "fadd",   { ST, STi } },
11792     { "fmul",   { ST, STi } },
11793     { "fcom",   { STi } },
11794     { "fcomp",  { STi } },
11795     { "fsub",   { ST, STi } },
11796     { "fsubr",  { ST, STi } },
11797     { "fdiv",   { ST, STi } },
11798     { "fdivr",  { ST, STi } },
11799   },
11800   /* d9 */
11801   {
11802     { "fld",    { STi } },
11803     { "fxch",   { STi } },
11804     { FGRPd9_2 },
11805     { Bad_Opcode },
11806     { FGRPd9_4 },
11807     { FGRPd9_5 },
11808     { FGRPd9_6 },
11809     { FGRPd9_7 },
11810   },
11811   /* da */
11812   {
11813     { "fcmovb", { ST, STi } },
11814     { "fcmove", { ST, STi } },
11815     { "fcmovbe",{ ST, STi } },
11816     { "fcmovu", { ST, STi } },
11817     { Bad_Opcode },
11818     { FGRPda_5 },
11819     { Bad_Opcode },
11820     { Bad_Opcode },
11821   },
11822   /* db */
11823   {
11824     { "fcmovnb",{ ST, STi } },
11825     { "fcmovne",{ ST, STi } },
11826     { "fcmovnbe",{ ST, STi } },
11827     { "fcmovnu",{ ST, STi } },
11828     { FGRPdb_4 },
11829     { "fucomi", { ST, STi } },
11830     { "fcomi",  { ST, STi } },
11831     { Bad_Opcode },
11832   },
11833   /* dc */
11834   {
11835     { "fadd",   { STi, ST } },
11836     { "fmul",   { STi, ST } },
11837     { Bad_Opcode },
11838     { Bad_Opcode },
11839     { "fsub!M", { STi, ST } },
11840     { "fsubM",  { STi, ST } },
11841     { "fdiv!M", { STi, ST } },
11842     { "fdivM",  { STi, ST } },
11843   },
11844   /* dd */
11845   {
11846     { "ffree",  { STi } },
11847     { Bad_Opcode },
11848     { "fst",    { STi } },
11849     { "fstp",   { STi } },
11850     { "fucom",  { STi } },
11851     { "fucomp", { STi } },
11852     { Bad_Opcode },
11853     { Bad_Opcode },
11854   },
11855   /* de */
11856   {
11857     { "faddp",  { STi, ST } },
11858     { "fmulp",  { STi, ST } },
11859     { Bad_Opcode },
11860     { FGRPde_3 },
11861     { "fsub!Mp", { STi, ST } },
11862     { "fsubMp", { STi, ST } },
11863     { "fdiv!Mp", { STi, ST } },
11864     { "fdivMp", { STi, ST } },
11865   },
11866   /* df */
11867   {
11868     { "ffreep", { STi } },
11869     { Bad_Opcode },
11870     { Bad_Opcode },
11871     { Bad_Opcode },
11872     { FGRPdf_4 },
11873     { "fucomip", { ST, STi } },
11874     { "fcomip", { ST, STi } },
11875     { Bad_Opcode },
11876   },
11877 };
11878
11879 static char *fgrps[][8] = {
11880   /* d9_2  0 */
11881   {
11882     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11883   },
11884
11885   /* d9_4  1 */
11886   {
11887     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11888   },
11889
11890   /* d9_5  2 */
11891   {
11892     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11893   },
11894
11895   /* d9_6  3 */
11896   {
11897     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11898   },
11899
11900   /* d9_7  4 */
11901   {
11902     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11903   },
11904
11905   /* da_5  5 */
11906   {
11907     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11908   },
11909
11910   /* db_4  6 */
11911   {
11912     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11913     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11914   },
11915
11916   /* de_3  7 */
11917   {
11918     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11919   },
11920
11921   /* df_4  8 */
11922   {
11923     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11924   },
11925 };
11926
11927 static void
11928 swap_operand (void)
11929 {
11930   mnemonicendp[0] = '.';
11931   mnemonicendp[1] = 's';
11932   mnemonicendp += 2;
11933 }
11934
11935 static void
11936 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11937                int sizeflag ATTRIBUTE_UNUSED)
11938 {
11939   /* Skip mod/rm byte.  */
11940   MODRM_CHECK;
11941   codep++;
11942 }
11943
11944 static void
11945 dofloat (int sizeflag)
11946 {
11947   const struct dis386 *dp;
11948   unsigned char floatop;
11949
11950   floatop = codep[-1];
11951
11952   if (modrm.mod != 3)
11953     {
11954       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11955
11956       putop (float_mem[fp_indx], sizeflag);
11957       obufp = op_out[0];
11958       op_ad = 2;
11959       OP_E (float_mem_mode[fp_indx], sizeflag);
11960       return;
11961     }
11962   /* Skip mod/rm byte.  */
11963   MODRM_CHECK;
11964   codep++;
11965
11966   dp = &float_reg[floatop - 0xd8][modrm.reg];
11967   if (dp->name == NULL)
11968     {
11969       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11970
11971       /* Instruction fnstsw is only one with strange arg.  */
11972       if (floatop == 0xdf && codep[-1] == 0xe0)
11973         strcpy (op_out[0], names16[0]);
11974     }
11975   else
11976     {
11977       putop (dp->name, sizeflag);
11978
11979       obufp = op_out[0];
11980       op_ad = 2;
11981       if (dp->op[0].rtn)
11982         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
11983
11984       obufp = op_out[1];
11985       op_ad = 1;
11986       if (dp->op[1].rtn)
11987         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
11988     }
11989 }
11990
11991 static void
11992 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11993 {
11994   oappend ("%st" + intel_syntax);
11995 }
11996
11997 static void
11998 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11999 {
12000   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12001   oappend (scratchbuf + intel_syntax);
12002 }
12003
12004 /* Capital letters in template are macros.  */
12005 static int
12006 putop (const char *in_template, int sizeflag)
12007 {
12008   const char *p;
12009   int alt = 0;
12010   int cond = 1;
12011   unsigned int l = 0, len = 1;
12012   char last[4];
12013
12014 #define SAVE_LAST(c)                    \
12015   if (l < len && l < sizeof (last))     \
12016     last[l++] = c;                      \
12017   else                                  \
12018     abort ();
12019
12020   for (p = in_template; *p; p++)
12021     {
12022       switch (*p)
12023         {
12024         default:
12025           *obufp++ = *p;
12026           break;
12027         case '%':
12028           len++;
12029           break;
12030         case '!':
12031           cond = 0;
12032           break;
12033         case '{':
12034           alt = 0;
12035           if (intel_syntax)
12036             {
12037               while (*++p != '|')
12038                 if (*p == '}' || *p == '\0')
12039                   abort ();
12040             }
12041           /* Fall through.  */
12042         case 'I':
12043           alt = 1;
12044           continue;
12045         case '|':
12046           while (*++p != '}')
12047             {
12048               if (*p == '\0')
12049                 abort ();
12050             }
12051           break;
12052         case '}':
12053           break;
12054         case 'A':
12055           if (intel_syntax)
12056             break;
12057           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12058             *obufp++ = 'b';
12059           break;
12060         case 'B':
12061           if (l == 0 && len == 1)
12062             {
12063 case_B:
12064               if (intel_syntax)
12065                 break;
12066               if (sizeflag & SUFFIX_ALWAYS)
12067                 *obufp++ = 'b';
12068             }
12069           else
12070             {
12071               if (l != 1
12072                   || len != 2
12073                   || last[0] != 'L')
12074                 {
12075                   SAVE_LAST (*p);
12076                   break;
12077                 }
12078
12079               if (address_mode == mode_64bit
12080                   && !(prefixes & PREFIX_ADDR))
12081                 {
12082                   *obufp++ = 'a';
12083                   *obufp++ = 'b';
12084                   *obufp++ = 's';
12085                 }
12086
12087               goto case_B;
12088             }
12089           break;
12090         case 'C':
12091           if (intel_syntax && !alt)
12092             break;
12093           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12094             {
12095               if (sizeflag & DFLAG)
12096                 *obufp++ = intel_syntax ? 'd' : 'l';
12097               else
12098                 *obufp++ = intel_syntax ? 'w' : 's';
12099               used_prefixes |= (prefixes & PREFIX_DATA);
12100             }
12101           break;
12102         case 'D':
12103           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12104             break;
12105           USED_REX (REX_W);
12106           if (modrm.mod == 3)
12107             {
12108               if (rex & REX_W)
12109                 *obufp++ = 'q';
12110               else
12111                 {
12112                   if (sizeflag & DFLAG)
12113                     *obufp++ = intel_syntax ? 'd' : 'l';
12114                   else
12115                     *obufp++ = 'w';
12116                   used_prefixes |= (prefixes & PREFIX_DATA);
12117                 }
12118             }
12119           else
12120             *obufp++ = 'w';
12121           break;
12122         case 'E':               /* For jcxz/jecxz */
12123           if (address_mode == mode_64bit)
12124             {
12125               if (sizeflag & AFLAG)
12126                 *obufp++ = 'r';
12127               else
12128                 *obufp++ = 'e';
12129             }
12130           else
12131             if (sizeflag & AFLAG)
12132               *obufp++ = 'e';
12133           used_prefixes |= (prefixes & PREFIX_ADDR);
12134           break;
12135         case 'F':
12136           if (intel_syntax)
12137             break;
12138           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12139             {
12140               if (sizeflag & AFLAG)
12141                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12142               else
12143                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12144               used_prefixes |= (prefixes & PREFIX_ADDR);
12145             }
12146           break;
12147         case 'G':
12148           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12149             break;
12150           if ((rex & REX_W) || (sizeflag & DFLAG))
12151             *obufp++ = 'l';
12152           else
12153             *obufp++ = 'w';
12154           if (!(rex & REX_W))
12155             used_prefixes |= (prefixes & PREFIX_DATA);
12156           break;
12157         case 'H':
12158           if (intel_syntax)
12159             break;
12160           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12161               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12162             {
12163               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12164               *obufp++ = ',';
12165               *obufp++ = 'p';
12166               if (prefixes & PREFIX_DS)
12167                 *obufp++ = 't';
12168               else
12169                 *obufp++ = 'n';
12170             }
12171           break;
12172         case 'J':
12173           if (intel_syntax)
12174             break;
12175           *obufp++ = 'l';
12176           break;
12177         case 'K':
12178           USED_REX (REX_W);
12179           if (rex & REX_W)
12180             *obufp++ = 'q';
12181           else
12182             *obufp++ = 'd';
12183           break;
12184         case 'Z':
12185           if (intel_syntax)
12186             break;
12187           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12188             {
12189               *obufp++ = 'q';
12190               break;
12191             }
12192           /* Fall through.  */
12193           goto case_L;
12194         case 'L':
12195           if (l != 0 || len != 1)
12196             {
12197               SAVE_LAST (*p);
12198               break;
12199             }
12200 case_L:
12201           if (intel_syntax)
12202             break;
12203           if (sizeflag & SUFFIX_ALWAYS)
12204             *obufp++ = 'l';
12205           break;
12206         case 'M':
12207           if (intel_mnemonic != cond)
12208             *obufp++ = 'r';
12209           break;
12210         case 'N':
12211           if ((prefixes & PREFIX_FWAIT) == 0)
12212             *obufp++ = 'n';
12213           else
12214             used_prefixes |= PREFIX_FWAIT;
12215           break;
12216         case 'O':
12217           USED_REX (REX_W);
12218           if (rex & REX_W)
12219             *obufp++ = 'o';
12220           else if (intel_syntax && (sizeflag & DFLAG))
12221             *obufp++ = 'q';
12222           else
12223             *obufp++ = 'd';
12224           if (!(rex & REX_W))
12225             used_prefixes |= (prefixes & PREFIX_DATA);
12226           break;
12227         case 'T':
12228           if (!intel_syntax
12229               && address_mode == mode_64bit
12230               && (sizeflag & DFLAG))
12231             {
12232               *obufp++ = 'q';
12233               break;
12234             }
12235           /* Fall through.  */
12236         case 'P':
12237           if (intel_syntax)
12238             {
12239               if ((rex & REX_W) == 0
12240                   && (prefixes & PREFIX_DATA))
12241                 {
12242                   if ((sizeflag & DFLAG) == 0)
12243                     *obufp++ = 'w';
12244                    used_prefixes |= (prefixes & PREFIX_DATA);
12245                 }
12246               break;
12247             }
12248           if ((prefixes & PREFIX_DATA)
12249               || (rex & REX_W)
12250               || (sizeflag & SUFFIX_ALWAYS))
12251             {
12252               USED_REX (REX_W);
12253               if (rex & REX_W)
12254                 *obufp++ = 'q';
12255               else
12256                 {
12257                    if (sizeflag & DFLAG)
12258                       *obufp++ = 'l';
12259                    else
12260                      *obufp++ = 'w';
12261                    used_prefixes |= (prefixes & PREFIX_DATA);
12262                 }
12263             }
12264           break;
12265         case 'U':
12266           if (intel_syntax)
12267             break;
12268           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12269             {
12270               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12271                 *obufp++ = 'q';
12272               break;
12273             }
12274           /* Fall through.  */
12275           goto case_Q;
12276         case 'Q':
12277           if (l == 0 && len == 1)
12278             {
12279 case_Q:
12280               if (intel_syntax && !alt)
12281                 break;
12282               USED_REX (REX_W);
12283               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12284                 {
12285                   if (rex & REX_W)
12286                     *obufp++ = 'q';
12287                   else
12288                     {
12289                       if (sizeflag & DFLAG)
12290                         *obufp++ = intel_syntax ? 'd' : 'l';
12291                       else
12292                         *obufp++ = 'w';
12293                       used_prefixes |= (prefixes & PREFIX_DATA);
12294                     }
12295                 }
12296             }
12297           else
12298             {
12299               if (l != 1 || len != 2 || last[0] != 'L')
12300                 {
12301                   SAVE_LAST (*p);
12302                   break;
12303                 }
12304               if (intel_syntax
12305                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12306                 break;
12307               if ((rex & REX_W))
12308                 {
12309                   USED_REX (REX_W);
12310                   *obufp++ = 'q';
12311                 }
12312               else
12313                 *obufp++ = 'l';
12314             }
12315           break;
12316         case 'R':
12317           USED_REX (REX_W);
12318           if (rex & REX_W)
12319             *obufp++ = 'q';
12320           else if (sizeflag & DFLAG)
12321             {
12322               if (intel_syntax)
12323                   *obufp++ = 'd';
12324               else
12325                   *obufp++ = 'l';
12326             }
12327           else
12328             *obufp++ = 'w';
12329           if (intel_syntax && !p[1]
12330               && ((rex & REX_W) || (sizeflag & DFLAG)))
12331             *obufp++ = 'e';
12332           if (!(rex & REX_W))
12333             used_prefixes |= (prefixes & PREFIX_DATA);
12334           break;
12335         case 'V':
12336           if (l == 0 && len == 1)
12337             {
12338               if (intel_syntax)
12339                 break;
12340               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12341                 {
12342                   if (sizeflag & SUFFIX_ALWAYS)
12343                     *obufp++ = 'q';
12344                   break;
12345                 }
12346             }
12347           else
12348             {
12349               if (l != 1
12350                   || len != 2
12351                   || last[0] != 'L')
12352                 {
12353                   SAVE_LAST (*p);
12354                   break;
12355                 }
12356
12357               if (rex & REX_W)
12358                 {
12359                   *obufp++ = 'a';
12360                   *obufp++ = 'b';
12361                   *obufp++ = 's';
12362                 }
12363             }
12364           /* Fall through.  */
12365           goto case_S;
12366         case 'S':
12367           if (l == 0 && len == 1)
12368             {
12369 case_S:
12370               if (intel_syntax)
12371                 break;
12372               if (sizeflag & SUFFIX_ALWAYS)
12373                 {
12374                   if (rex & REX_W)
12375                     *obufp++ = 'q';
12376                   else
12377                     {
12378                       if (sizeflag & DFLAG)
12379                         *obufp++ = 'l';
12380                       else
12381                         *obufp++ = 'w';
12382                       used_prefixes |= (prefixes & PREFIX_DATA);
12383                     }
12384                 }
12385             }
12386           else
12387             {
12388               if (l != 1
12389                   || len != 2
12390                   || last[0] != 'L')
12391                 {
12392                   SAVE_LAST (*p);
12393                   break;
12394                 }
12395
12396               if (address_mode == mode_64bit
12397                   && !(prefixes & PREFIX_ADDR))
12398                 {
12399                   *obufp++ = 'a';
12400                   *obufp++ = 'b';
12401                   *obufp++ = 's';
12402                 }
12403
12404               goto case_S;
12405             }
12406           break;
12407         case 'X':
12408           if (l != 0 || len != 1)
12409             {
12410               SAVE_LAST (*p);
12411               break;
12412             }
12413           if (need_vex && vex.prefix)
12414             {
12415               if (vex.prefix == DATA_PREFIX_OPCODE)
12416                 *obufp++ = 'd';
12417               else
12418                 *obufp++ = 's';
12419             }
12420           else
12421             {
12422               if (prefixes & PREFIX_DATA)
12423                 *obufp++ = 'd';
12424               else
12425                 *obufp++ = 's';
12426               used_prefixes |= (prefixes & PREFIX_DATA);
12427             }
12428           break;
12429         case 'Y':
12430           if (l == 0 && len == 1)
12431             {
12432               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12433                 break;
12434               if (rex & REX_W)
12435                 {
12436                   USED_REX (REX_W);
12437                   *obufp++ = 'q';
12438                 }
12439               break;
12440             }
12441           else
12442             {
12443               if (l != 1 || len != 2 || last[0] != 'X')
12444                 {
12445                   SAVE_LAST (*p);
12446                   break;
12447                 }
12448               if (!need_vex)
12449                 abort ();
12450               if (intel_syntax
12451                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12452                 break;
12453               switch (vex.length)
12454                 {
12455                 case 128:
12456                   *obufp++ = 'x';
12457                   break;
12458                 case 256:
12459                   *obufp++ = 'y';
12460                   break;
12461                 default:
12462                   abort ();
12463                 }
12464             }
12465           break;
12466         case 'W':
12467           if (l == 0 && len == 1)
12468             {
12469               /* operand size flag for cwtl, cbtw */
12470               USED_REX (REX_W);
12471               if (rex & REX_W)
12472                 {
12473                   if (intel_syntax)
12474                     *obufp++ = 'd';
12475                   else
12476                     *obufp++ = 'l';
12477                 }
12478               else if (sizeflag & DFLAG)
12479                 *obufp++ = 'w';
12480               else
12481                 *obufp++ = 'b';
12482               if (!(rex & REX_W))
12483                 used_prefixes |= (prefixes & PREFIX_DATA);
12484             }
12485           else
12486             {
12487               if (l != 1
12488                   || len != 2
12489                   || (last[0] != 'X'
12490                       && last[0] != 'L'))
12491                 {
12492                   SAVE_LAST (*p);
12493                   break;
12494                 }
12495               if (!need_vex)
12496                 abort ();
12497               if (last[0] == 'X')
12498                 *obufp++ = vex.w ? 'd': 's';
12499               else
12500                 *obufp++ = vex.w ? 'q': 'd';
12501             }
12502           break;
12503         }
12504       alt = 0;
12505     }
12506   *obufp = 0;
12507   mnemonicendp = obufp;
12508   return 0;
12509 }
12510
12511 static void
12512 oappend (const char *s)
12513 {
12514   obufp = stpcpy (obufp, s);
12515 }
12516
12517 static void
12518 append_seg (void)
12519 {
12520   if (prefixes & PREFIX_CS)
12521     {
12522       used_prefixes |= PREFIX_CS;
12523       oappend ("%cs:" + intel_syntax);
12524     }
12525   if (prefixes & PREFIX_DS)
12526     {
12527       used_prefixes |= PREFIX_DS;
12528       oappend ("%ds:" + intel_syntax);
12529     }
12530   if (prefixes & PREFIX_SS)
12531     {
12532       used_prefixes |= PREFIX_SS;
12533       oappend ("%ss:" + intel_syntax);
12534     }
12535   if (prefixes & PREFIX_ES)
12536     {
12537       used_prefixes |= PREFIX_ES;
12538       oappend ("%es:" + intel_syntax);
12539     }
12540   if (prefixes & PREFIX_FS)
12541     {
12542       used_prefixes |= PREFIX_FS;
12543       oappend ("%fs:" + intel_syntax);
12544     }
12545   if (prefixes & PREFIX_GS)
12546     {
12547       used_prefixes |= PREFIX_GS;
12548       oappend ("%gs:" + intel_syntax);
12549     }
12550 }
12551
12552 static void
12553 OP_indirE (int bytemode, int sizeflag)
12554 {
12555   if (!intel_syntax)
12556     oappend ("*");
12557   OP_E (bytemode, sizeflag);
12558 }
12559
12560 static void
12561 print_operand_value (char *buf, int hex, bfd_vma disp)
12562 {
12563   if (address_mode == mode_64bit)
12564     {
12565       if (hex)
12566         {
12567           char tmp[30];
12568           int i;
12569           buf[0] = '0';
12570           buf[1] = 'x';
12571           sprintf_vma (tmp, disp);
12572           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12573           strcpy (buf + 2, tmp + i);
12574         }
12575       else
12576         {
12577           bfd_signed_vma v = disp;
12578           char tmp[30];
12579           int i;
12580           if (v < 0)
12581             {
12582               *(buf++) = '-';
12583               v = -disp;
12584               /* Check for possible overflow on 0x8000000000000000.  */
12585               if (v < 0)
12586                 {
12587                   strcpy (buf, "9223372036854775808");
12588                   return;
12589                 }
12590             }
12591           if (!v)
12592             {
12593               strcpy (buf, "0");
12594               return;
12595             }
12596
12597           i = 0;
12598           tmp[29] = 0;
12599           while (v)
12600             {
12601               tmp[28 - i] = (v % 10) + '0';
12602               v /= 10;
12603               i++;
12604             }
12605           strcpy (buf, tmp + 29 - i);
12606         }
12607     }
12608   else
12609     {
12610       if (hex)
12611         sprintf (buf, "0x%x", (unsigned int) disp);
12612       else
12613         sprintf (buf, "%d", (int) disp);
12614     }
12615 }
12616
12617 /* Put DISP in BUF as signed hex number.  */
12618
12619 static void
12620 print_displacement (char *buf, bfd_vma disp)
12621 {
12622   bfd_signed_vma val = disp;
12623   char tmp[30];
12624   int i, j = 0;
12625
12626   if (val < 0)
12627     {
12628       buf[j++] = '-';
12629       val = -disp;
12630
12631       /* Check for possible overflow.  */
12632       if (val < 0)
12633         {
12634           switch (address_mode)
12635             {
12636             case mode_64bit:
12637               strcpy (buf + j, "0x8000000000000000");
12638               break;
12639             case mode_32bit:
12640               strcpy (buf + j, "0x80000000");
12641               break;
12642             case mode_16bit:
12643               strcpy (buf + j, "0x8000");
12644               break;
12645             }
12646           return;
12647         }
12648     }
12649
12650   buf[j++] = '0';
12651   buf[j++] = 'x';
12652
12653   sprintf_vma (tmp, (bfd_vma) val);
12654   for (i = 0; tmp[i] == '0'; i++)
12655     continue;
12656   if (tmp[i] == '\0')
12657     i--;
12658   strcpy (buf + j, tmp + i);
12659 }
12660
12661 static void
12662 intel_operand_size (int bytemode, int sizeflag)
12663 {
12664   switch (bytemode)
12665     {
12666     case b_mode:
12667     case b_swap_mode:
12668     case dqb_mode:
12669       oappend ("BYTE PTR ");
12670       break;
12671     case w_mode:
12672     case dqw_mode:
12673       oappend ("WORD PTR ");
12674       break;
12675     case stack_v_mode:
12676       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12677         {
12678           oappend ("QWORD PTR ");
12679           break;
12680         }
12681       /* FALLTHRU */
12682     case v_mode:
12683     case v_swap_mode:
12684     case dq_mode:
12685       USED_REX (REX_W);
12686       if (rex & REX_W)
12687         oappend ("QWORD PTR ");
12688       else
12689         {
12690           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12691             oappend ("DWORD PTR ");
12692           else
12693             oappend ("WORD PTR ");
12694           used_prefixes |= (prefixes & PREFIX_DATA);
12695         }
12696       break;
12697     case z_mode:
12698       if ((rex & REX_W) || (sizeflag & DFLAG))
12699         *obufp++ = 'D';
12700       oappend ("WORD PTR ");
12701       if (!(rex & REX_W))
12702         used_prefixes |= (prefixes & PREFIX_DATA);
12703       break;
12704     case a_mode:
12705       if (sizeflag & DFLAG)
12706         oappend ("QWORD PTR ");
12707       else
12708         oappend ("DWORD PTR ");
12709       used_prefixes |= (prefixes & PREFIX_DATA);
12710       break;
12711     case d_mode:
12712     case d_scalar_mode:
12713     case d_scalar_swap_mode:
12714     case d_swap_mode:
12715     case dqd_mode:
12716       oappend ("DWORD PTR ");
12717       break;
12718     case q_mode:
12719     case q_scalar_mode:
12720     case q_scalar_swap_mode:
12721     case q_swap_mode:
12722       oappend ("QWORD PTR ");
12723       break;
12724     case m_mode:
12725       if (address_mode == mode_64bit)
12726         oappend ("QWORD PTR ");
12727       else
12728         oappend ("DWORD PTR ");
12729       break;
12730     case f_mode:
12731       if (sizeflag & DFLAG)
12732         oappend ("FWORD PTR ");
12733       else
12734         oappend ("DWORD PTR ");
12735       used_prefixes |= (prefixes & PREFIX_DATA);
12736       break;
12737     case t_mode:
12738       oappend ("TBYTE PTR ");
12739       break;
12740     case x_mode:
12741     case x_swap_mode:
12742       if (need_vex)
12743         {
12744           switch (vex.length)
12745             {
12746             case 128:
12747               oappend ("XMMWORD PTR ");
12748               break;
12749             case 256:
12750               oappend ("YMMWORD PTR ");
12751               break;
12752             default:
12753               abort ();
12754             }
12755         }
12756       else
12757         oappend ("XMMWORD PTR ");
12758       break;
12759     case xmm_mode:
12760       oappend ("XMMWORD PTR ");
12761       break;
12762     case xmmq_mode:
12763       if (!need_vex)
12764         abort ();
12765
12766       switch (vex.length)
12767         {
12768         case 128:
12769           oappend ("QWORD PTR ");
12770           break;
12771         case 256:
12772           oappend ("XMMWORD PTR ");
12773           break;
12774         default:
12775           abort ();
12776         }
12777       break;
12778     case xmm_mb_mode:
12779       if (!need_vex)
12780         abort ();
12781
12782       switch (vex.length)
12783         {
12784         case 128:
12785         case 256:
12786           oappend ("BYTE PTR ");
12787           break;
12788         default:
12789           abort ();
12790         }
12791       break;
12792     case xmm_mw_mode:
12793       if (!need_vex)
12794         abort ();
12795
12796       switch (vex.length)
12797         {
12798         case 128:
12799         case 256:
12800           oappend ("WORD PTR ");
12801           break;
12802         default:
12803           abort ();
12804         }
12805       break;
12806     case xmm_md_mode:
12807       if (!need_vex)
12808         abort ();
12809
12810       switch (vex.length)
12811         {
12812         case 128:
12813         case 256:
12814           oappend ("DWORD PTR ");
12815           break;
12816         default:
12817           abort ();
12818         }
12819       break;
12820     case xmm_mq_mode:
12821       if (!need_vex)
12822         abort ();
12823
12824       switch (vex.length)
12825         {
12826         case 128:
12827         case 256:
12828           oappend ("QWORD PTR ");
12829           break;
12830         default:
12831           abort ();
12832         }
12833       break;
12834     case xmmdw_mode:
12835       if (!need_vex)
12836         abort ();
12837
12838       switch (vex.length)
12839         {
12840         case 128:
12841           oappend ("WORD PTR ");
12842           break;
12843         case 256:
12844           oappend ("DWORD PTR ");
12845           break;
12846         default:
12847           abort ();
12848         }
12849       break;
12850     case xmmqd_mode:
12851       if (!need_vex)
12852         abort ();
12853
12854       switch (vex.length)
12855         {
12856         case 128:
12857           oappend ("DWORD PTR ");
12858           break;
12859         case 256:
12860           oappend ("QWORD PTR ");
12861           break;
12862         default:
12863           abort ();
12864         }
12865       break;
12866     case ymmq_mode:
12867       if (!need_vex)
12868         abort ();
12869
12870       switch (vex.length)
12871         {
12872         case 128:
12873           oappend ("QWORD PTR ");
12874           break;
12875         case 256:
12876           oappend ("YMMWORD PTR ");
12877           break;
12878         default:
12879           abort ();
12880         }
12881       break;
12882     case ymmxmm_mode:
12883       if (!need_vex)
12884         abort ();
12885
12886       switch (vex.length)
12887         {
12888         case 128:
12889         case 256:
12890           oappend ("XMMWORD PTR ");
12891           break;
12892         default:
12893           abort ();
12894         }
12895       break;
12896     case o_mode:
12897       oappend ("OWORD PTR ");
12898       break;
12899     case vex_w_dq_mode:
12900     case vex_scalar_w_dq_mode:
12901     case vex_vsib_d_w_dq_mode:
12902     case vex_vsib_q_w_dq_mode:
12903       if (!need_vex)
12904         abort ();
12905
12906       if (vex.w)
12907         oappend ("QWORD PTR ");
12908       else
12909         oappend ("DWORD PTR ");
12910       break;
12911     default:
12912       break;
12913     }
12914 }
12915
12916 static void
12917 OP_E_register (int bytemode, int sizeflag)
12918 {
12919   int reg = modrm.rm;
12920   const char **names;
12921
12922   USED_REX (REX_B);
12923   if ((rex & REX_B))
12924     reg += 8;
12925
12926   if ((sizeflag & SUFFIX_ALWAYS)
12927       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12928     swap_operand ();
12929
12930   switch (bytemode)
12931     {
12932     case b_mode:
12933     case b_swap_mode:
12934       USED_REX (0);
12935       if (rex)
12936         names = names8rex;
12937       else
12938         names = names8;
12939       break;
12940     case w_mode:
12941       names = names16;
12942       break;
12943     case d_mode:
12944       names = names32;
12945       break;
12946     case q_mode:
12947       names = names64;
12948       break;
12949     case m_mode:
12950       names = address_mode == mode_64bit ? names64 : names32;
12951       break;
12952     case stack_v_mode:
12953       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12954         {
12955           names = names64;
12956           break;
12957         }
12958       bytemode = v_mode;
12959       /* FALLTHRU */
12960     case v_mode:
12961     case v_swap_mode:
12962     case dq_mode:
12963     case dqb_mode:
12964     case dqd_mode:
12965     case dqw_mode:
12966       USED_REX (REX_W);
12967       if (rex & REX_W)
12968         names = names64;
12969       else
12970         {
12971           if ((sizeflag & DFLAG)
12972               || (bytemode != v_mode
12973                   && bytemode != v_swap_mode))
12974             names = names32;
12975           else
12976             names = names16;
12977           used_prefixes |= (prefixes & PREFIX_DATA);
12978         }
12979       break;
12980     case 0:
12981       return;
12982     default:
12983       oappend (INTERNAL_DISASSEMBLER_ERROR);
12984       return;
12985     }
12986   oappend (names[reg]);
12987 }
12988
12989 static void
12990 OP_E_memory (int bytemode, int sizeflag)
12991 {
12992   bfd_vma disp = 0;
12993   int add = (rex & REX_B) ? 8 : 0;
12994   int riprel = 0;
12995
12996   USED_REX (REX_B);
12997   if (intel_syntax)
12998     intel_operand_size (bytemode, sizeflag);
12999   append_seg ();
13000
13001   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13002     {
13003       /* 32/64 bit address mode */
13004       int havedisp;
13005       int havesib;
13006       int havebase;
13007       int haveindex;
13008       int needindex;
13009       int base, rbase;
13010       int vindex = 0;
13011       int scale = 0;
13012       const char **indexes64 = names64;
13013       const char **indexes32 = names32;
13014
13015       havesib = 0;
13016       havebase = 1;
13017       haveindex = 0;
13018       base = modrm.rm;
13019
13020       if (base == 4)
13021         {
13022           havesib = 1;
13023           vindex = sib.index;
13024           USED_REX (REX_X);
13025           if (rex & REX_X)
13026             vindex += 8;
13027           switch (bytemode)
13028             {
13029             case vex_vsib_d_w_dq_mode:
13030             case vex_vsib_q_w_dq_mode:
13031               if (!need_vex)
13032                 abort ();
13033
13034               haveindex = 1;
13035               switch (vex.length)
13036                 {
13037                 case 128:
13038                   indexes64 = indexes32 = names_xmm;
13039                   break;
13040                 case 256:
13041                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
13042                     indexes64 = indexes32 = names_ymm;
13043                   else
13044                     indexes64 = indexes32 = names_xmm;
13045                   break;
13046                 default:
13047                   abort ();
13048                 }
13049               break;
13050             default:
13051               haveindex = vindex != 4;
13052               break;
13053             }
13054           scale = sib.scale;
13055           base = sib.base;
13056           codep++;
13057         }
13058       rbase = base + add;
13059
13060       switch (modrm.mod)
13061         {
13062         case 0:
13063           if (base == 5)
13064             {
13065               havebase = 0;
13066               if (address_mode == mode_64bit && !havesib)
13067                 riprel = 1;
13068               disp = get32s ();
13069             }
13070           break;
13071         case 1:
13072           FETCH_DATA (the_info, codep + 1);
13073           disp = *codep++;
13074           if ((disp & 0x80) != 0)
13075             disp -= 0x100;
13076           break;
13077         case 2:
13078           disp = get32s ();
13079           break;
13080         }
13081
13082       /* In 32bit mode, we need index register to tell [offset] from
13083          [eiz*1 + offset].  */
13084       needindex = (havesib
13085                    && !havebase
13086                    && !haveindex
13087                    && address_mode == mode_32bit);
13088       havedisp = (havebase
13089                   || needindex
13090                   || (havesib && (haveindex || scale != 0)));
13091
13092       if (!intel_syntax)
13093         if (modrm.mod != 0 || base == 5)
13094           {
13095             if (havedisp || riprel)
13096               print_displacement (scratchbuf, disp);
13097             else
13098               print_operand_value (scratchbuf, 1, disp);
13099             oappend (scratchbuf);
13100             if (riprel)
13101               {
13102                 set_op (disp, 1);
13103                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13104               }
13105           }
13106
13107       if (havebase || haveindex || riprel)
13108         used_prefixes |= PREFIX_ADDR;
13109
13110       if (havedisp || (intel_syntax && riprel))
13111         {
13112           *obufp++ = open_char;
13113           if (intel_syntax && riprel)
13114             {
13115               set_op (disp, 1);
13116               oappend (sizeflag & AFLAG ? "rip" : "eip");
13117             }
13118           *obufp = '\0';
13119           if (havebase)
13120             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13121                      ? names64[rbase] : names32[rbase]);
13122           if (havesib)
13123             {
13124               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13125                  print index to tell base + index from base.  */
13126               if (scale != 0
13127                   || needindex
13128                   || haveindex
13129                   || (havebase && base != ESP_REG_NUM))
13130                 {
13131                   if (!intel_syntax || havebase)
13132                     {
13133                       *obufp++ = separator_char;
13134                       *obufp = '\0';
13135                     }
13136                   if (haveindex)
13137                     oappend (address_mode == mode_64bit
13138                              && (sizeflag & AFLAG)
13139                              ? indexes64[vindex] : indexes32[vindex]);
13140                   else
13141                     oappend (address_mode == mode_64bit
13142                              && (sizeflag & AFLAG)
13143                              ? index64 : index32);
13144
13145                   *obufp++ = scale_char;
13146                   *obufp = '\0';
13147                   sprintf (scratchbuf, "%d", 1 << scale);
13148                   oappend (scratchbuf);
13149                 }
13150             }
13151           if (intel_syntax
13152               && (disp || modrm.mod != 0 || base == 5))
13153             {
13154               if (!havedisp || (bfd_signed_vma) disp >= 0)
13155                 {
13156                   *obufp++ = '+';
13157                   *obufp = '\0';
13158                 }
13159               else if (modrm.mod != 1 && disp != -disp)
13160                 {
13161                   *obufp++ = '-';
13162                   *obufp = '\0';
13163                   disp = - (bfd_signed_vma) disp;
13164                 }
13165
13166               if (havedisp)
13167                 print_displacement (scratchbuf, disp);
13168               else
13169                 print_operand_value (scratchbuf, 1, disp);
13170               oappend (scratchbuf);
13171             }
13172
13173           *obufp++ = close_char;
13174           *obufp = '\0';
13175         }
13176       else if (intel_syntax)
13177         {
13178           if (modrm.mod != 0 || base == 5)
13179             {
13180               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13181                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13182                 ;
13183               else
13184                 {
13185                   oappend (names_seg[ds_reg - es_reg]);
13186                   oappend (":");
13187                 }
13188               print_operand_value (scratchbuf, 1, disp);
13189               oappend (scratchbuf);
13190             }
13191         }
13192     }
13193   else
13194     {
13195       /* 16 bit address mode */
13196       used_prefixes |= prefixes & PREFIX_ADDR;
13197       switch (modrm.mod)
13198         {
13199         case 0:
13200           if (modrm.rm == 6)
13201             {
13202               disp = get16 ();
13203               if ((disp & 0x8000) != 0)
13204                 disp -= 0x10000;
13205             }
13206           break;
13207         case 1:
13208           FETCH_DATA (the_info, codep + 1);
13209           disp = *codep++;
13210           if ((disp & 0x80) != 0)
13211             disp -= 0x100;
13212           break;
13213         case 2:
13214           disp = get16 ();
13215           if ((disp & 0x8000) != 0)
13216             disp -= 0x10000;
13217           break;
13218         }
13219
13220       if (!intel_syntax)
13221         if (modrm.mod != 0 || modrm.rm == 6)
13222           {
13223             print_displacement (scratchbuf, disp);
13224             oappend (scratchbuf);
13225           }
13226
13227       if (modrm.mod != 0 || modrm.rm != 6)
13228         {
13229           *obufp++ = open_char;
13230           *obufp = '\0';
13231           oappend (index16[modrm.rm]);
13232           if (intel_syntax
13233               && (disp || modrm.mod != 0 || modrm.rm == 6))
13234             {
13235               if ((bfd_signed_vma) disp >= 0)
13236                 {
13237                   *obufp++ = '+';
13238                   *obufp = '\0';
13239                 }
13240               else if (modrm.mod != 1)
13241                 {
13242                   *obufp++ = '-';
13243                   *obufp = '\0';
13244                   disp = - (bfd_signed_vma) disp;
13245                 }
13246
13247               print_displacement (scratchbuf, disp);
13248               oappend (scratchbuf);
13249             }
13250
13251           *obufp++ = close_char;
13252           *obufp = '\0';
13253         }
13254       else if (intel_syntax)
13255         {
13256           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13257                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13258             ;
13259           else
13260             {
13261               oappend (names_seg[ds_reg - es_reg]);
13262               oappend (":");
13263             }
13264           print_operand_value (scratchbuf, 1, disp & 0xffff);
13265           oappend (scratchbuf);
13266         }
13267     }
13268 }
13269
13270 static void
13271 OP_E (int bytemode, int sizeflag)
13272 {
13273   /* Skip mod/rm byte.  */
13274   MODRM_CHECK;
13275   codep++;
13276
13277   if (modrm.mod == 3)
13278     OP_E_register (bytemode, sizeflag);
13279   else
13280     OP_E_memory (bytemode, sizeflag);
13281 }
13282
13283 static void
13284 OP_G (int bytemode, int sizeflag)
13285 {
13286   int add = 0;
13287   USED_REX (REX_R);
13288   if (rex & REX_R)
13289     add += 8;
13290   switch (bytemode)
13291     {
13292     case b_mode:
13293       USED_REX (0);
13294       if (rex)
13295         oappend (names8rex[modrm.reg + add]);
13296       else
13297         oappend (names8[modrm.reg + add]);
13298       break;
13299     case w_mode:
13300       oappend (names16[modrm.reg + add]);
13301       break;
13302     case d_mode:
13303       oappend (names32[modrm.reg + add]);
13304       break;
13305     case q_mode:
13306       oappend (names64[modrm.reg + add]);
13307       break;
13308     case v_mode:
13309     case dq_mode:
13310     case dqb_mode:
13311     case dqd_mode:
13312     case dqw_mode:
13313       USED_REX (REX_W);
13314       if (rex & REX_W)
13315         oappend (names64[modrm.reg + add]);
13316       else
13317         {
13318           if ((sizeflag & DFLAG) || bytemode != v_mode)
13319             oappend (names32[modrm.reg + add]);
13320           else
13321             oappend (names16[modrm.reg + add]);
13322           used_prefixes |= (prefixes & PREFIX_DATA);
13323         }
13324       break;
13325     case m_mode:
13326       if (address_mode == mode_64bit)
13327         oappend (names64[modrm.reg + add]);
13328       else
13329         oappend (names32[modrm.reg + add]);
13330       break;
13331     default:
13332       oappend (INTERNAL_DISASSEMBLER_ERROR);
13333       break;
13334     }
13335 }
13336
13337 static bfd_vma
13338 get64 (void)
13339 {
13340   bfd_vma x;
13341 #ifdef BFD64
13342   unsigned int a;
13343   unsigned int b;
13344
13345   FETCH_DATA (the_info, codep + 8);
13346   a = *codep++ & 0xff;
13347   a |= (*codep++ & 0xff) << 8;
13348   a |= (*codep++ & 0xff) << 16;
13349   a |= (*codep++ & 0xff) << 24;
13350   b = *codep++ & 0xff;
13351   b |= (*codep++ & 0xff) << 8;
13352   b |= (*codep++ & 0xff) << 16;
13353   b |= (*codep++ & 0xff) << 24;
13354   x = a + ((bfd_vma) b << 32);
13355 #else
13356   abort ();
13357   x = 0;
13358 #endif
13359   return x;
13360 }
13361
13362 static bfd_signed_vma
13363 get32 (void)
13364 {
13365   bfd_signed_vma x = 0;
13366
13367   FETCH_DATA (the_info, codep + 4);
13368   x = *codep++ & (bfd_signed_vma) 0xff;
13369   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13370   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13371   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13372   return x;
13373 }
13374
13375 static bfd_signed_vma
13376 get32s (void)
13377 {
13378   bfd_signed_vma x = 0;
13379
13380   FETCH_DATA (the_info, codep + 4);
13381   x = *codep++ & (bfd_signed_vma) 0xff;
13382   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13383   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13384   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13385
13386   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13387
13388   return x;
13389 }
13390
13391 static int
13392 get16 (void)
13393 {
13394   int x = 0;
13395
13396   FETCH_DATA (the_info, codep + 2);
13397   x = *codep++ & 0xff;
13398   x |= (*codep++ & 0xff) << 8;
13399   return x;
13400 }
13401
13402 static void
13403 set_op (bfd_vma op, int riprel)
13404 {
13405   op_index[op_ad] = op_ad;
13406   if (address_mode == mode_64bit)
13407     {
13408       op_address[op_ad] = op;
13409       op_riprel[op_ad] = riprel;
13410     }
13411   else
13412     {
13413       /* Mask to get a 32-bit address.  */
13414       op_address[op_ad] = op & 0xffffffff;
13415       op_riprel[op_ad] = riprel & 0xffffffff;
13416     }
13417 }
13418
13419 static void
13420 OP_REG (int code, int sizeflag)
13421 {
13422   const char *s;
13423   int add;
13424   USED_REX (REX_B);
13425   if (rex & REX_B)
13426     add = 8;
13427   else
13428     add = 0;
13429
13430   switch (code)
13431     {
13432     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13433     case sp_reg: case bp_reg: case si_reg: case di_reg:
13434       s = names16[code - ax_reg + add];
13435       break;
13436     case es_reg: case ss_reg: case cs_reg:
13437     case ds_reg: case fs_reg: case gs_reg:
13438       s = names_seg[code - es_reg + add];
13439       break;
13440     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13441     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13442       USED_REX (0);
13443       if (rex)
13444         s = names8rex[code - al_reg + add];
13445       else
13446         s = names8[code - al_reg];
13447       break;
13448     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13449     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13450       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13451         {
13452           s = names64[code - rAX_reg + add];
13453           break;
13454         }
13455       code += eAX_reg - rAX_reg;
13456       /* Fall through.  */
13457     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13458     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13459       USED_REX (REX_W);
13460       if (rex & REX_W)
13461         s = names64[code - eAX_reg + add];
13462       else
13463         {
13464           if (sizeflag & DFLAG)
13465             s = names32[code - eAX_reg + add];
13466           else
13467             s = names16[code - eAX_reg + add];
13468           used_prefixes |= (prefixes & PREFIX_DATA);
13469         }
13470       break;
13471     default:
13472       s = INTERNAL_DISASSEMBLER_ERROR;
13473       break;
13474     }
13475   oappend (s);
13476 }
13477
13478 static void
13479 OP_IMREG (int code, int sizeflag)
13480 {
13481   const char *s;
13482
13483   switch (code)
13484     {
13485     case indir_dx_reg:
13486       if (intel_syntax)
13487         s = "dx";
13488       else
13489         s = "(%dx)";
13490       break;
13491     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13492     case sp_reg: case bp_reg: case si_reg: case di_reg:
13493       s = names16[code - ax_reg];
13494       break;
13495     case es_reg: case ss_reg: case cs_reg:
13496     case ds_reg: case fs_reg: case gs_reg:
13497       s = names_seg[code - es_reg];
13498       break;
13499     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13500     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13501       USED_REX (0);
13502       if (rex)
13503         s = names8rex[code - al_reg];
13504       else
13505         s = names8[code - al_reg];
13506       break;
13507     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13508     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13509       USED_REX (REX_W);
13510       if (rex & REX_W)
13511         s = names64[code - eAX_reg];
13512       else
13513         {
13514           if (sizeflag & DFLAG)
13515             s = names32[code - eAX_reg];
13516           else
13517             s = names16[code - eAX_reg];
13518           used_prefixes |= (prefixes & PREFIX_DATA);
13519         }
13520       break;
13521     case z_mode_ax_reg:
13522       if ((rex & REX_W) || (sizeflag & DFLAG))
13523         s = *names32;
13524       else
13525         s = *names16;
13526       if (!(rex & REX_W))
13527         used_prefixes |= (prefixes & PREFIX_DATA);
13528       break;
13529     default:
13530       s = INTERNAL_DISASSEMBLER_ERROR;
13531       break;
13532     }
13533   oappend (s);
13534 }
13535
13536 static void
13537 OP_I (int bytemode, int sizeflag)
13538 {
13539   bfd_signed_vma op;
13540   bfd_signed_vma mask = -1;
13541
13542   switch (bytemode)
13543     {
13544     case b_mode:
13545       FETCH_DATA (the_info, codep + 1);
13546       op = *codep++;
13547       mask = 0xff;
13548       break;
13549     case q_mode:
13550       if (address_mode == mode_64bit)
13551         {
13552           op = get32s ();
13553           break;
13554         }
13555       /* Fall through.  */
13556     case v_mode:
13557       USED_REX (REX_W);
13558       if (rex & REX_W)
13559         op = get32s ();
13560       else
13561         {
13562           if (sizeflag & DFLAG)
13563             {
13564               op = get32 ();
13565               mask = 0xffffffff;
13566             }
13567           else
13568             {
13569               op = get16 ();
13570               mask = 0xfffff;
13571             }
13572           used_prefixes |= (prefixes & PREFIX_DATA);
13573         }
13574       break;
13575     case w_mode:
13576       mask = 0xfffff;
13577       op = get16 ();
13578       break;
13579     case const_1_mode:
13580       if (intel_syntax)
13581         oappend ("1");
13582       return;
13583     default:
13584       oappend (INTERNAL_DISASSEMBLER_ERROR);
13585       return;
13586     }
13587
13588   op &= mask;
13589   scratchbuf[0] = '$';
13590   print_operand_value (scratchbuf + 1, 1, op);
13591   oappend (scratchbuf + intel_syntax);
13592   scratchbuf[0] = '\0';
13593 }
13594
13595 static void
13596 OP_I64 (int bytemode, int sizeflag)
13597 {
13598   bfd_signed_vma op;
13599   bfd_signed_vma mask = -1;
13600
13601   if (address_mode != mode_64bit)
13602     {
13603       OP_I (bytemode, sizeflag);
13604       return;
13605     }
13606
13607   switch (bytemode)
13608     {
13609     case b_mode:
13610       FETCH_DATA (the_info, codep + 1);
13611       op = *codep++;
13612       mask = 0xff;
13613       break;
13614     case v_mode:
13615       USED_REX (REX_W);
13616       if (rex & REX_W)
13617         op = get64 ();
13618       else
13619         {
13620           if (sizeflag & DFLAG)
13621             {
13622               op = get32 ();
13623               mask = 0xffffffff;
13624             }
13625           else
13626             {
13627               op = get16 ();
13628               mask = 0xfffff;
13629             }
13630           used_prefixes |= (prefixes & PREFIX_DATA);
13631         }
13632       break;
13633     case w_mode:
13634       mask = 0xfffff;
13635       op = get16 ();
13636       break;
13637     default:
13638       oappend (INTERNAL_DISASSEMBLER_ERROR);
13639       return;
13640     }
13641
13642   op &= mask;
13643   scratchbuf[0] = '$';
13644   print_operand_value (scratchbuf + 1, 1, op);
13645   oappend (scratchbuf + intel_syntax);
13646   scratchbuf[0] = '\0';
13647 }
13648
13649 static void
13650 OP_sI (int bytemode, int sizeflag)
13651 {
13652   bfd_signed_vma op;
13653
13654   switch (bytemode)
13655     {
13656     case b_mode:
13657     case b_T_mode:
13658       FETCH_DATA (the_info, codep + 1);
13659       op = *codep++;
13660       if ((op & 0x80) != 0)
13661         op -= 0x100;
13662       if (bytemode == b_T_mode)
13663         {
13664           if (address_mode != mode_64bit
13665               || !(sizeflag & DFLAG))
13666             {
13667               if (sizeflag & DFLAG)
13668                 op &= 0xffffffff;
13669               else
13670                 op &= 0xffff;
13671           }
13672         }
13673       else
13674         {
13675           if (!(rex & REX_W))
13676             {
13677               if (sizeflag & DFLAG)
13678                 op &= 0xffffffff;
13679               else
13680                 op &= 0xffff;
13681             }
13682         }
13683       break;
13684     case v_mode:
13685       if (sizeflag & DFLAG)
13686         op = get32s ();
13687       else
13688         op = get16 ();
13689       break;
13690     default:
13691       oappend (INTERNAL_DISASSEMBLER_ERROR);
13692       return;
13693     }
13694
13695   scratchbuf[0] = '$';
13696   print_operand_value (scratchbuf + 1, 1, op);
13697   oappend (scratchbuf + intel_syntax);
13698 }
13699
13700 static void
13701 OP_J (int bytemode, int sizeflag)
13702 {
13703   bfd_vma disp;
13704   bfd_vma mask = -1;
13705   bfd_vma segment = 0;
13706
13707   switch (bytemode)
13708     {
13709     case b_mode:
13710       FETCH_DATA (the_info, codep + 1);
13711       disp = *codep++;
13712       if ((disp & 0x80) != 0)
13713         disp -= 0x100;
13714       break;
13715     case v_mode:
13716       USED_REX (REX_W);
13717       if ((sizeflag & DFLAG) || (rex & REX_W))
13718         disp = get32s ();
13719       else
13720         {
13721           disp = get16 ();
13722           if ((disp & 0x8000) != 0)
13723             disp -= 0x10000;
13724           /* In 16bit mode, address is wrapped around at 64k within
13725              the same segment.  Otherwise, a data16 prefix on a jump
13726              instruction means that the pc is masked to 16 bits after
13727              the displacement is added!  */
13728           mask = 0xffff;
13729           if ((prefixes & PREFIX_DATA) == 0)
13730             segment = ((start_pc + codep - start_codep)
13731                        & ~((bfd_vma) 0xffff));
13732         }
13733       if (!(rex & REX_W))
13734         used_prefixes |= (prefixes & PREFIX_DATA);
13735       break;
13736     default:
13737       oappend (INTERNAL_DISASSEMBLER_ERROR);
13738       return;
13739     }
13740   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
13741   set_op (disp, 0);
13742   print_operand_value (scratchbuf, 1, disp);
13743   oappend (scratchbuf);
13744 }
13745
13746 static void
13747 OP_SEG (int bytemode, int sizeflag)
13748 {
13749   if (bytemode == w_mode)
13750     oappend (names_seg[modrm.reg]);
13751   else
13752     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13753 }
13754
13755 static void
13756 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13757 {
13758   int seg, offset;
13759
13760   if (sizeflag & DFLAG)
13761     {
13762       offset = get32 ();
13763       seg = get16 ();
13764     }
13765   else
13766     {
13767       offset = get16 ();
13768       seg = get16 ();
13769     }
13770   used_prefixes |= (prefixes & PREFIX_DATA);
13771   if (intel_syntax)
13772     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13773   else
13774     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13775   oappend (scratchbuf);
13776 }
13777
13778 static void
13779 OP_OFF (int bytemode, int sizeflag)
13780 {
13781   bfd_vma off;
13782
13783   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13784     intel_operand_size (bytemode, sizeflag);
13785   append_seg ();
13786
13787   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13788     off = get32 ();
13789   else
13790     off = get16 ();
13791
13792   if (intel_syntax)
13793     {
13794       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13795                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13796         {
13797           oappend (names_seg[ds_reg - es_reg]);
13798           oappend (":");
13799         }
13800     }
13801   print_operand_value (scratchbuf, 1, off);
13802   oappend (scratchbuf);
13803 }
13804
13805 static void
13806 OP_OFF64 (int bytemode, int sizeflag)
13807 {
13808   bfd_vma off;
13809
13810   if (address_mode != mode_64bit
13811       || (prefixes & PREFIX_ADDR))
13812     {
13813       OP_OFF (bytemode, sizeflag);
13814       return;
13815     }
13816
13817   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13818     intel_operand_size (bytemode, sizeflag);
13819   append_seg ();
13820
13821   off = get64 ();
13822
13823   if (intel_syntax)
13824     {
13825       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13826                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13827         {
13828           oappend (names_seg[ds_reg - es_reg]);
13829           oappend (":");
13830         }
13831     }
13832   print_operand_value (scratchbuf, 1, off);
13833   oappend (scratchbuf);
13834 }
13835
13836 static void
13837 ptr_reg (int code, int sizeflag)
13838 {
13839   const char *s;
13840
13841   *obufp++ = open_char;
13842   used_prefixes |= (prefixes & PREFIX_ADDR);
13843   if (address_mode == mode_64bit)
13844     {
13845       if (!(sizeflag & AFLAG))
13846         s = names32[code - eAX_reg];
13847       else
13848         s = names64[code - eAX_reg];
13849     }
13850   else if (sizeflag & AFLAG)
13851     s = names32[code - eAX_reg];
13852   else
13853     s = names16[code - eAX_reg];
13854   oappend (s);
13855   *obufp++ = close_char;
13856   *obufp = 0;
13857 }
13858
13859 static void
13860 OP_ESreg (int code, int sizeflag)
13861 {
13862   if (intel_syntax)
13863     {
13864       switch (codep[-1])
13865         {
13866         case 0x6d:      /* insw/insl */
13867           intel_operand_size (z_mode, sizeflag);
13868           break;
13869         case 0xa5:      /* movsw/movsl/movsq */
13870         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13871         case 0xab:      /* stosw/stosl */
13872         case 0xaf:      /* scasw/scasl */
13873           intel_operand_size (v_mode, sizeflag);
13874           break;
13875         default:
13876           intel_operand_size (b_mode, sizeflag);
13877         }
13878     }
13879   oappend ("%es:" + intel_syntax);
13880   ptr_reg (code, sizeflag);
13881 }
13882
13883 static void
13884 OP_DSreg (int code, int sizeflag)
13885 {
13886   if (intel_syntax)
13887     {
13888       switch (codep[-1])
13889         {
13890         case 0x6f:      /* outsw/outsl */
13891           intel_operand_size (z_mode, sizeflag);
13892           break;
13893         case 0xa5:      /* movsw/movsl/movsq */
13894         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13895         case 0xad:      /* lodsw/lodsl/lodsq */
13896           intel_operand_size (v_mode, sizeflag);
13897           break;
13898         default:
13899           intel_operand_size (b_mode, sizeflag);
13900         }
13901     }
13902   if ((prefixes
13903        & (PREFIX_CS
13904           | PREFIX_DS
13905           | PREFIX_SS
13906           | PREFIX_ES
13907           | PREFIX_FS
13908           | PREFIX_GS)) == 0)
13909     prefixes |= PREFIX_DS;
13910   append_seg ();
13911   ptr_reg (code, sizeflag);
13912 }
13913
13914 static void
13915 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13916 {
13917   int add;
13918   if (rex & REX_R)
13919     {
13920       USED_REX (REX_R);
13921       add = 8;
13922     }
13923   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13924     {
13925       all_prefixes[last_lock_prefix] = 0;
13926       used_prefixes |= PREFIX_LOCK;
13927       add = 8;
13928     }
13929   else
13930     add = 0;
13931   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13932   oappend (scratchbuf + intel_syntax);
13933 }
13934
13935 static void
13936 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13937 {
13938   int add;
13939   USED_REX (REX_R);
13940   if (rex & REX_R)
13941     add = 8;
13942   else
13943     add = 0;
13944   if (intel_syntax)
13945     sprintf (scratchbuf, "db%d", modrm.reg + add);
13946   else
13947     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13948   oappend (scratchbuf);
13949 }
13950
13951 static void
13952 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13953 {
13954   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13955   oappend (scratchbuf + intel_syntax);
13956 }
13957
13958 static void
13959 OP_R (int bytemode, int sizeflag)
13960 {
13961   if (modrm.mod == 3)
13962     OP_E (bytemode, sizeflag);
13963   else
13964     BadOp ();
13965 }
13966
13967 static void
13968 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13969 {
13970   int reg = modrm.reg;
13971   const char **names;
13972
13973   used_prefixes |= (prefixes & PREFIX_DATA);
13974   if (prefixes & PREFIX_DATA)
13975     {
13976       names = names_xmm;
13977       USED_REX (REX_R);
13978       if (rex & REX_R)
13979         reg += 8;
13980     }
13981   else
13982     names = names_mm;
13983   oappend (names[reg]);
13984 }
13985
13986 static void
13987 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13988 {
13989   int reg = modrm.reg;
13990   const char **names;
13991
13992   USED_REX (REX_R);
13993   if (rex & REX_R)
13994     reg += 8;
13995   if (need_vex
13996       && bytemode != xmm_mode
13997       && bytemode != scalar_mode)
13998     {
13999       switch (vex.length)
14000         {
14001         case 128:
14002           names = names_xmm;
14003           break;
14004         case 256:
14005           if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
14006             names = names_ymm;
14007           else
14008             names = names_xmm;
14009           break;
14010         default:
14011           abort ();
14012         }
14013     }
14014   else
14015     names = names_xmm;
14016   oappend (names[reg]);
14017 }
14018
14019 static void
14020 OP_EM (int bytemode, int sizeflag)
14021 {
14022   int reg;
14023   const char **names;
14024
14025   if (modrm.mod != 3)
14026     {
14027       if (intel_syntax
14028           && (bytemode == v_mode || bytemode == v_swap_mode))
14029         {
14030           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14031           used_prefixes |= (prefixes & PREFIX_DATA);
14032         }
14033       OP_E (bytemode, sizeflag);
14034       return;
14035     }
14036
14037   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14038     swap_operand ();
14039
14040   /* Skip mod/rm byte.  */
14041   MODRM_CHECK;
14042   codep++;
14043   used_prefixes |= (prefixes & PREFIX_DATA);
14044   reg = modrm.rm;
14045   if (prefixes & PREFIX_DATA)
14046     {
14047       names = names_xmm;
14048       USED_REX (REX_B);
14049       if (rex & REX_B)
14050         reg += 8;
14051     }
14052   else
14053     names = names_mm;
14054   oappend (names[reg]);
14055 }
14056
14057 /* cvt* are the only instructions in sse2 which have
14058    both SSE and MMX operands and also have 0x66 prefix
14059    in their opcode. 0x66 was originally used to differentiate
14060    between SSE and MMX instruction(operands). So we have to handle the
14061    cvt* separately using OP_EMC and OP_MXC */
14062 static void
14063 OP_EMC (int bytemode, int sizeflag)
14064 {
14065   if (modrm.mod != 3)
14066     {
14067       if (intel_syntax && bytemode == v_mode)
14068         {
14069           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14070           used_prefixes |= (prefixes & PREFIX_DATA);
14071         }
14072       OP_E (bytemode, sizeflag);
14073       return;
14074     }
14075
14076   /* Skip mod/rm byte.  */
14077   MODRM_CHECK;
14078   codep++;
14079   used_prefixes |= (prefixes & PREFIX_DATA);
14080   oappend (names_mm[modrm.rm]);
14081 }
14082
14083 static void
14084 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14085 {
14086   used_prefixes |= (prefixes & PREFIX_DATA);
14087   oappend (names_mm[modrm.reg]);
14088 }
14089
14090 static void
14091 OP_EX (int bytemode, int sizeflag)
14092 {
14093   int reg;
14094   const char **names;
14095
14096   /* Skip mod/rm byte.  */
14097   MODRM_CHECK;
14098   codep++;
14099
14100   if (modrm.mod != 3)
14101     {
14102       OP_E_memory (bytemode, sizeflag);
14103       return;
14104     }
14105
14106   reg = modrm.rm;
14107   USED_REX (REX_B);
14108   if (rex & REX_B)
14109     reg += 8;
14110
14111   if ((sizeflag & SUFFIX_ALWAYS)
14112       && (bytemode == x_swap_mode
14113           || bytemode == d_swap_mode
14114           || bytemode == d_scalar_swap_mode
14115           || bytemode == q_swap_mode
14116           || bytemode == q_scalar_swap_mode))
14117     swap_operand ();
14118
14119   if (need_vex
14120       && bytemode != xmm_mode
14121       && bytemode != xmmdw_mode
14122       && bytemode != xmmqd_mode
14123       && bytemode != xmm_mb_mode
14124       && bytemode != xmm_mw_mode
14125       && bytemode != xmm_md_mode
14126       && bytemode != xmm_mq_mode
14127       && bytemode != xmmq_mode
14128       && bytemode != d_scalar_mode
14129       && bytemode != d_scalar_swap_mode
14130       && bytemode != q_scalar_mode
14131       && bytemode != q_scalar_swap_mode
14132       && bytemode != vex_scalar_w_dq_mode)
14133     {
14134       switch (vex.length)
14135         {
14136         case 128:
14137           names = names_xmm;
14138           break;
14139         case 256:
14140           names = names_ymm;
14141           break;
14142         default:
14143           abort ();
14144         }
14145     }
14146   else
14147     names = names_xmm;
14148   oappend (names[reg]);
14149 }
14150
14151 static void
14152 OP_MS (int bytemode, int sizeflag)
14153 {
14154   if (modrm.mod == 3)
14155     OP_EM (bytemode, sizeflag);
14156   else
14157     BadOp ();
14158 }
14159
14160 static void
14161 OP_XS (int bytemode, int sizeflag)
14162 {
14163   if (modrm.mod == 3)
14164     OP_EX (bytemode, sizeflag);
14165   else
14166     BadOp ();
14167 }
14168
14169 static void
14170 OP_M (int bytemode, int sizeflag)
14171 {
14172   if (modrm.mod == 3)
14173     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14174     BadOp ();
14175   else
14176     OP_E (bytemode, sizeflag);
14177 }
14178
14179 static void
14180 OP_0f07 (int bytemode, int sizeflag)
14181 {
14182   if (modrm.mod != 3 || modrm.rm != 0)
14183     BadOp ();
14184   else
14185     OP_E (bytemode, sizeflag);
14186 }
14187
14188 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14189    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14190
14191 static void
14192 NOP_Fixup1 (int bytemode, int sizeflag)
14193 {
14194   if ((prefixes & PREFIX_DATA) != 0
14195       || (rex != 0
14196           && rex != 0x48
14197           && address_mode == mode_64bit))
14198     OP_REG (bytemode, sizeflag);
14199   else
14200     strcpy (obuf, "nop");
14201 }
14202
14203 static void
14204 NOP_Fixup2 (int bytemode, int sizeflag)
14205 {
14206   if ((prefixes & PREFIX_DATA) != 0
14207       || (rex != 0
14208           && rex != 0x48
14209           && address_mode == mode_64bit))
14210     OP_IMREG (bytemode, sizeflag);
14211 }
14212
14213 static const char *const Suffix3DNow[] = {
14214 /* 00 */        NULL,           NULL,           NULL,           NULL,
14215 /* 04 */        NULL,           NULL,           NULL,           NULL,
14216 /* 08 */        NULL,           NULL,           NULL,           NULL,
14217 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14218 /* 10 */        NULL,           NULL,           NULL,           NULL,
14219 /* 14 */        NULL,           NULL,           NULL,           NULL,
14220 /* 18 */        NULL,           NULL,           NULL,           NULL,
14221 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14222 /* 20 */        NULL,           NULL,           NULL,           NULL,
14223 /* 24 */        NULL,           NULL,           NULL,           NULL,
14224 /* 28 */        NULL,           NULL,           NULL,           NULL,
14225 /* 2C */        NULL,           NULL,           NULL,           NULL,
14226 /* 30 */        NULL,           NULL,           NULL,           NULL,
14227 /* 34 */        NULL,           NULL,           NULL,           NULL,
14228 /* 38 */        NULL,           NULL,           NULL,           NULL,
14229 /* 3C */        NULL,           NULL,           NULL,           NULL,
14230 /* 40 */        NULL,           NULL,           NULL,           NULL,
14231 /* 44 */        NULL,           NULL,           NULL,           NULL,
14232 /* 48 */        NULL,           NULL,           NULL,           NULL,
14233 /* 4C */        NULL,           NULL,           NULL,           NULL,
14234 /* 50 */        NULL,           NULL,           NULL,           NULL,
14235 /* 54 */        NULL,           NULL,           NULL,           NULL,
14236 /* 58 */        NULL,           NULL,           NULL,           NULL,
14237 /* 5C */        NULL,           NULL,           NULL,           NULL,
14238 /* 60 */        NULL,           NULL,           NULL,           NULL,
14239 /* 64 */        NULL,           NULL,           NULL,           NULL,
14240 /* 68 */        NULL,           NULL,           NULL,           NULL,
14241 /* 6C */        NULL,           NULL,           NULL,           NULL,
14242 /* 70 */        NULL,           NULL,           NULL,           NULL,
14243 /* 74 */        NULL,           NULL,           NULL,           NULL,
14244 /* 78 */        NULL,           NULL,           NULL,           NULL,
14245 /* 7C */        NULL,           NULL,           NULL,           NULL,
14246 /* 80 */        NULL,           NULL,           NULL,           NULL,
14247 /* 84 */        NULL,           NULL,           NULL,           NULL,
14248 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14249 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14250 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14251 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14252 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14253 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14254 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14255 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14256 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14257 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14258 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14259 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14260 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14261 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14262 /* C0 */        NULL,           NULL,           NULL,           NULL,
14263 /* C4 */        NULL,           NULL,           NULL,           NULL,
14264 /* C8 */        NULL,           NULL,           NULL,           NULL,
14265 /* CC */        NULL,           NULL,           NULL,           NULL,
14266 /* D0 */        NULL,           NULL,           NULL,           NULL,
14267 /* D4 */        NULL,           NULL,           NULL,           NULL,
14268 /* D8 */        NULL,           NULL,           NULL,           NULL,
14269 /* DC */        NULL,           NULL,           NULL,           NULL,
14270 /* E0 */        NULL,           NULL,           NULL,           NULL,
14271 /* E4 */        NULL,           NULL,           NULL,           NULL,
14272 /* E8 */        NULL,           NULL,           NULL,           NULL,
14273 /* EC */        NULL,           NULL,           NULL,           NULL,
14274 /* F0 */        NULL,           NULL,           NULL,           NULL,
14275 /* F4 */        NULL,           NULL,           NULL,           NULL,
14276 /* F8 */        NULL,           NULL,           NULL,           NULL,
14277 /* FC */        NULL,           NULL,           NULL,           NULL,
14278 };
14279
14280 static void
14281 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14282 {
14283   const char *mnemonic;
14284
14285   FETCH_DATA (the_info, codep + 1);
14286   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14287      place where an 8-bit immediate would normally go.  ie. the last
14288      byte of the instruction.  */
14289   obufp = mnemonicendp;
14290   mnemonic = Suffix3DNow[*codep++ & 0xff];
14291   if (mnemonic)
14292     oappend (mnemonic);
14293   else
14294     {
14295       /* Since a variable sized modrm/sib chunk is between the start
14296          of the opcode (0x0f0f) and the opcode suffix, we need to do
14297          all the modrm processing first, and don't know until now that
14298          we have a bad opcode.  This necessitates some cleaning up.  */
14299       op_out[0][0] = '\0';
14300       op_out[1][0] = '\0';
14301       BadOp ();
14302     }
14303   mnemonicendp = obufp;
14304 }
14305
14306 static struct op simd_cmp_op[] =
14307 {
14308   { STRING_COMMA_LEN ("eq") },
14309   { STRING_COMMA_LEN ("lt") },
14310   { STRING_COMMA_LEN ("le") },
14311   { STRING_COMMA_LEN ("unord") },
14312   { STRING_COMMA_LEN ("neq") },
14313   { STRING_COMMA_LEN ("nlt") },
14314   { STRING_COMMA_LEN ("nle") },
14315   { STRING_COMMA_LEN ("ord") }
14316 };
14317
14318 static void
14319 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14320 {
14321   unsigned int cmp_type;
14322
14323   FETCH_DATA (the_info, codep + 1);
14324   cmp_type = *codep++ & 0xff;
14325   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14326     {
14327       char suffix [3];
14328       char *p = mnemonicendp - 2;
14329       suffix[0] = p[0];
14330       suffix[1] = p[1];
14331       suffix[2] = '\0';
14332       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14333       mnemonicendp += simd_cmp_op[cmp_type].len;
14334     }
14335   else
14336     {
14337       /* We have a reserved extension byte.  Output it directly.  */
14338       scratchbuf[0] = '$';
14339       print_operand_value (scratchbuf + 1, 1, cmp_type);
14340       oappend (scratchbuf + intel_syntax);
14341       scratchbuf[0] = '\0';
14342     }
14343 }
14344
14345 static void
14346 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14347           int sizeflag ATTRIBUTE_UNUSED)
14348 {
14349   /* mwait %eax,%ecx  */
14350   if (!intel_syntax)
14351     {
14352       const char **names = (address_mode == mode_64bit
14353                             ? names64 : names32);
14354       strcpy (op_out[0], names[0]);
14355       strcpy (op_out[1], names[1]);
14356       two_source_ops = 1;
14357     }
14358   /* Skip mod/rm byte.  */
14359   MODRM_CHECK;
14360   codep++;
14361 }
14362
14363 static void
14364 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14365             int sizeflag ATTRIBUTE_UNUSED)
14366 {
14367   /* monitor %eax,%ecx,%edx"  */
14368   if (!intel_syntax)
14369     {
14370       const char **op1_names;
14371       const char **names = (address_mode == mode_64bit
14372                             ? names64 : names32);
14373
14374       if (!(prefixes & PREFIX_ADDR))
14375         op1_names = (address_mode == mode_16bit
14376                      ? names16 : names);
14377       else
14378         {
14379           /* Remove "addr16/addr32".  */
14380           all_prefixes[last_addr_prefix] = 0;
14381           op1_names = (address_mode != mode_32bit
14382                        ? names32 : names16);
14383           used_prefixes |= PREFIX_ADDR;
14384         }
14385       strcpy (op_out[0], op1_names[0]);
14386       strcpy (op_out[1], names[1]);
14387       strcpy (op_out[2], names[2]);
14388       two_source_ops = 1;
14389     }
14390   /* Skip mod/rm byte.  */
14391   MODRM_CHECK;
14392   codep++;
14393 }
14394
14395 static void
14396 BadOp (void)
14397 {
14398   /* Throw away prefixes and 1st. opcode byte.  */
14399   codep = insn_codep + 1;
14400   oappend ("(bad)");
14401 }
14402
14403 static void
14404 REP_Fixup (int bytemode, int sizeflag)
14405 {
14406   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14407      lods and stos.  */
14408   if (prefixes & PREFIX_REPZ)
14409     all_prefixes[last_repz_prefix] = REP_PREFIX;
14410
14411   switch (bytemode)
14412     {
14413     case al_reg:
14414     case eAX_reg:
14415     case indir_dx_reg:
14416       OP_IMREG (bytemode, sizeflag);
14417       break;
14418     case eDI_reg:
14419       OP_ESreg (bytemode, sizeflag);
14420       break;
14421     case eSI_reg:
14422       OP_DSreg (bytemode, sizeflag);
14423       break;
14424     default:
14425       abort ();
14426       break;
14427     }
14428 }
14429
14430 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
14431    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
14432  */
14433
14434 static void
14435 HLE_Fixup1 (int bytemode, int sizeflag)
14436 {
14437   if (modrm.mod != 3
14438       && (prefixes & PREFIX_LOCK) != 0)
14439     {
14440       if (prefixes & PREFIX_REPZ)
14441         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14442       if (prefixes & PREFIX_REPNZ)
14443         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14444     }
14445
14446   OP_E (bytemode, sizeflag);
14447 }
14448
14449 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
14450    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
14451  */
14452
14453 static void
14454 HLE_Fixup2 (int bytemode, int sizeflag)
14455 {
14456   if (modrm.mod != 3)
14457     {
14458       if (prefixes & PREFIX_REPZ)
14459         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14460       if (prefixes & PREFIX_REPNZ)
14461         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14462     }
14463
14464   OP_E (bytemode, sizeflag);
14465 }
14466
14467 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
14468    "xrelease" for memory operand.  No check for LOCK prefix.   */
14469
14470 static void
14471 HLE_Fixup3 (int bytemode, int sizeflag)
14472 {
14473   if (modrm.mod != 3
14474       && last_repz_prefix > last_repnz_prefix
14475       && (prefixes & PREFIX_REPZ) != 0)
14476     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14477
14478   OP_E (bytemode, sizeflag);
14479 }
14480
14481 static void
14482 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14483 {
14484   USED_REX (REX_W);
14485   if (rex & REX_W)
14486     {
14487       /* Change cmpxchg8b to cmpxchg16b.  */
14488       char *p = mnemonicendp - 2;
14489       mnemonicendp = stpcpy (p, "16b");
14490       bytemode = o_mode;
14491     }
14492   else if ((prefixes & PREFIX_LOCK) != 0)
14493     {
14494       if (prefixes & PREFIX_REPZ)
14495         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14496       if (prefixes & PREFIX_REPNZ)
14497         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14498     }
14499
14500   OP_M (bytemode, sizeflag);
14501 }
14502
14503 static void
14504 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14505 {
14506   const char **names;
14507
14508   if (need_vex)
14509     {
14510       switch (vex.length)
14511         {
14512         case 128:
14513           names = names_xmm;
14514           break;
14515         case 256:
14516           names = names_ymm;
14517           break;
14518         default:
14519           abort ();
14520         }
14521     }
14522   else
14523     names = names_xmm;
14524   oappend (names[reg]);
14525 }
14526
14527 static void
14528 CRC32_Fixup (int bytemode, int sizeflag)
14529 {
14530   /* Add proper suffix to "crc32".  */
14531   char *p = mnemonicendp;
14532
14533   switch (bytemode)
14534     {
14535     case b_mode:
14536       if (intel_syntax)
14537         goto skip;
14538
14539       *p++ = 'b';
14540       break;
14541     case v_mode:
14542       if (intel_syntax)
14543         goto skip;
14544
14545       USED_REX (REX_W);
14546       if (rex & REX_W)
14547         *p++ = 'q';
14548       else
14549         {
14550           if (sizeflag & DFLAG)
14551             *p++ = 'l';
14552           else
14553             *p++ = 'w';
14554           used_prefixes |= (prefixes & PREFIX_DATA);
14555         }
14556       break;
14557     default:
14558       oappend (INTERNAL_DISASSEMBLER_ERROR);
14559       break;
14560     }
14561   mnemonicendp = p;
14562   *p = '\0';
14563
14564 skip:
14565   if (modrm.mod == 3)
14566     {
14567       int add;
14568
14569       /* Skip mod/rm byte.  */
14570       MODRM_CHECK;
14571       codep++;
14572
14573       USED_REX (REX_B);
14574       add = (rex & REX_B) ? 8 : 0;
14575       if (bytemode == b_mode)
14576         {
14577           USED_REX (0);
14578           if (rex)
14579             oappend (names8rex[modrm.rm + add]);
14580           else
14581             oappend (names8[modrm.rm + add]);
14582         }
14583       else
14584         {
14585           USED_REX (REX_W);
14586           if (rex & REX_W)
14587             oappend (names64[modrm.rm + add]);
14588           else if ((prefixes & PREFIX_DATA))
14589             oappend (names16[modrm.rm + add]);
14590           else
14591             oappend (names32[modrm.rm + add]);
14592         }
14593     }
14594   else
14595     OP_E (bytemode, sizeflag);
14596 }
14597
14598 static void
14599 FXSAVE_Fixup (int bytemode, int sizeflag)
14600 {
14601   /* Add proper suffix to "fxsave" and "fxrstor".  */
14602   USED_REX (REX_W);
14603   if (rex & REX_W)
14604     {
14605       char *p = mnemonicendp;
14606       *p++ = '6';
14607       *p++ = '4';
14608       *p = '\0';
14609       mnemonicendp = p;
14610     }
14611   OP_M (bytemode, sizeflag);
14612 }
14613
14614 /* Display the destination register operand for instructions with
14615    VEX. */
14616
14617 static void
14618 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14619 {
14620   int reg;
14621   const char **names;
14622
14623   if (!need_vex)
14624     abort ();
14625
14626   if (!need_vex_reg)
14627     return;
14628
14629   reg = vex.register_specifier;
14630   if (bytemode == vex_scalar_mode)
14631     {
14632       oappend (names_xmm[reg]);
14633       return;
14634     }
14635
14636   switch (vex.length)
14637     {
14638     case 128:
14639       switch (bytemode)
14640         {
14641         case vex_mode:
14642         case vex128_mode:
14643         case vex_vsib_q_w_dq_mode:
14644           names = names_xmm;
14645           break;
14646         case dq_mode:
14647           if (vex.w)
14648             names = names64;
14649           else
14650             names = names32;
14651           break;
14652         default:
14653           abort ();
14654           return;
14655         }
14656       break;
14657     case 256:
14658       switch (bytemode)
14659         {
14660         case vex_mode:
14661         case vex256_mode:
14662           names = names_ymm;
14663           break;
14664         case vex_vsib_q_w_dq_mode:
14665           names = vex.w ? names_ymm : names_xmm;
14666           break;
14667         default:
14668           abort ();
14669           return;
14670         }
14671       break;
14672     default:
14673       abort ();
14674       break;
14675     }
14676   oappend (names[reg]);
14677 }
14678
14679 /* Get the VEX immediate byte without moving codep.  */
14680
14681 static unsigned char
14682 get_vex_imm8 (int sizeflag, int opnum)
14683 {
14684   int bytes_before_imm = 0;
14685
14686   if (modrm.mod != 3)
14687     {
14688       /* There are SIB/displacement bytes.  */
14689       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14690         {
14691           /* 32/64 bit address mode */
14692           int base = modrm.rm;
14693
14694           /* Check SIB byte.  */
14695           if (base == 4)
14696             {
14697               FETCH_DATA (the_info, codep + 1);
14698               base = *codep & 7;
14699               /* When decoding the third source, don't increase
14700                  bytes_before_imm as this has already been incremented
14701                  by one in OP_E_memory while decoding the second
14702                  source operand.  */
14703               if (opnum == 0)
14704                 bytes_before_imm++;
14705             }
14706
14707           /* Don't increase bytes_before_imm when decoding the third source,
14708              it has already been incremented by OP_E_memory while decoding
14709              the second source operand.  */
14710           if (opnum == 0)
14711             {
14712               switch (modrm.mod)
14713                 {
14714                   case 0:
14715                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14716                        SIB == 5, there is a 4 byte displacement.  */
14717                     if (base != 5)
14718                       /* No displacement. */
14719                       break;
14720                   case 2:
14721                     /* 4 byte displacement.  */
14722                     bytes_before_imm += 4;
14723                     break;
14724                   case 1:
14725                     /* 1 byte displacement.  */
14726                     bytes_before_imm++;
14727                     break;
14728                 }
14729             }
14730         }
14731       else
14732         {
14733           /* 16 bit address mode */
14734           /* Don't increase bytes_before_imm when decoding the third source,
14735              it has already been incremented by OP_E_memory while decoding
14736              the second source operand.  */
14737           if (opnum == 0)
14738             {
14739               switch (modrm.mod)
14740                 {
14741                 case 0:
14742                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14743                   if (modrm.rm != 6)
14744                     /* No displacement. */
14745                     break;
14746                 case 2:
14747                   /* 2 byte displacement.  */
14748                   bytes_before_imm += 2;
14749                   break;
14750                 case 1:
14751                   /* 1 byte displacement: when decoding the third source,
14752                      don't increase bytes_before_imm as this has already
14753                      been incremented by one in OP_E_memory while decoding
14754                      the second source operand.  */
14755                   if (opnum == 0)
14756                     bytes_before_imm++;
14757
14758                   break;
14759                 }
14760             }
14761         }
14762     }
14763
14764   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14765   return codep [bytes_before_imm];
14766 }
14767
14768 static void
14769 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14770 {
14771   const char **names;
14772
14773   if (reg == -1 && modrm.mod != 3)
14774     {
14775       OP_E_memory (bytemode, sizeflag);
14776       return;
14777     }
14778   else
14779     {
14780       if (reg == -1)
14781         {
14782           reg = modrm.rm;
14783           USED_REX (REX_B);
14784           if (rex & REX_B)
14785             reg += 8;
14786         }
14787       else if (reg > 7 && address_mode != mode_64bit)
14788         BadOp ();
14789     }
14790
14791   switch (vex.length)
14792     {
14793     case 128:
14794       names = names_xmm;
14795       break;
14796     case 256:
14797       names = names_ymm;
14798       break;
14799     default:
14800       abort ();
14801     }
14802   oappend (names[reg]);
14803 }
14804
14805 static void
14806 OP_EX_VexImmW (int bytemode, int sizeflag)
14807 {
14808   int reg = -1;
14809   static unsigned char vex_imm8;
14810
14811   if (vex_w_done == 0)
14812     {
14813       vex_w_done = 1;
14814
14815       /* Skip mod/rm byte.  */
14816       MODRM_CHECK;
14817       codep++;
14818
14819       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14820
14821       if (vex.w)
14822           reg = vex_imm8 >> 4;
14823
14824       OP_EX_VexReg (bytemode, sizeflag, reg);
14825     }
14826   else if (vex_w_done == 1)
14827     {
14828       vex_w_done = 2;
14829
14830       if (!vex.w)
14831           reg = vex_imm8 >> 4;
14832
14833       OP_EX_VexReg (bytemode, sizeflag, reg);
14834     }
14835   else
14836     {
14837       /* Output the imm8 directly.  */
14838       scratchbuf[0] = '$';
14839       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14840       oappend (scratchbuf + intel_syntax);
14841       scratchbuf[0] = '\0';
14842       codep++;
14843     }
14844 }
14845
14846 static void
14847 OP_Vex_2src (int bytemode, int sizeflag)
14848 {
14849   if (modrm.mod == 3)
14850     {
14851       int reg = modrm.rm;
14852       USED_REX (REX_B);
14853       if (rex & REX_B)
14854         reg += 8;
14855       oappend (names_xmm[reg]);
14856     }
14857   else
14858     {
14859       if (intel_syntax
14860           && (bytemode == v_mode || bytemode == v_swap_mode))
14861         {
14862           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14863           used_prefixes |= (prefixes & PREFIX_DATA);
14864         }
14865       OP_E (bytemode, sizeflag);
14866     }
14867 }
14868
14869 static void
14870 OP_Vex_2src_1 (int bytemode, int sizeflag)
14871 {
14872   if (modrm.mod == 3)
14873     {
14874       /* Skip mod/rm byte.   */
14875       MODRM_CHECK;
14876       codep++;
14877     }
14878
14879   if (vex.w)
14880     oappend (names_xmm[vex.register_specifier]);
14881   else
14882     OP_Vex_2src (bytemode, sizeflag);
14883 }
14884
14885 static void
14886 OP_Vex_2src_2 (int bytemode, int sizeflag)
14887 {
14888   if (vex.w)
14889     OP_Vex_2src (bytemode, sizeflag);
14890   else
14891     oappend (names_xmm[vex.register_specifier]);
14892 }
14893
14894 static void
14895 OP_EX_VexW (int bytemode, int sizeflag)
14896 {
14897   int reg = -1;
14898
14899   if (!vex_w_done)
14900     {
14901       vex_w_done = 1;
14902
14903       /* Skip mod/rm byte.  */
14904       MODRM_CHECK;
14905       codep++;
14906
14907       if (vex.w)
14908         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14909     }
14910   else
14911     {
14912       if (!vex.w)
14913         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14914     }
14915
14916   OP_EX_VexReg (bytemode, sizeflag, reg);
14917 }
14918
14919 static void
14920 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14921              int sizeflag ATTRIBUTE_UNUSED)
14922 {
14923   /* Skip the immediate byte and check for invalid bits.  */
14924   FETCH_DATA (the_info, codep + 1);
14925   if (*codep++ & 0xf)
14926     BadOp ();
14927 }
14928
14929 static void
14930 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14931 {
14932   int reg;
14933   const char **names;
14934
14935   FETCH_DATA (the_info, codep + 1);
14936   reg = *codep++;
14937
14938   if (bytemode != x_mode)
14939     abort ();
14940
14941   if (reg & 0xf)
14942       BadOp ();
14943
14944   reg >>= 4;
14945   if (reg > 7 && address_mode != mode_64bit)
14946     BadOp ();
14947
14948   switch (vex.length)
14949     {
14950     case 128:
14951       names = names_xmm;
14952       break;
14953     case 256:
14954       names = names_ymm;
14955       break;
14956     default:
14957       abort ();
14958     }
14959   oappend (names[reg]);
14960 }
14961
14962 static void
14963 OP_XMM_VexW (int bytemode, int sizeflag)
14964 {
14965   /* Turn off the REX.W bit since it is used for swapping operands
14966      now.  */
14967   rex &= ~REX_W;
14968   OP_XMM (bytemode, sizeflag);
14969 }
14970
14971 static void
14972 OP_EX_Vex (int bytemode, int sizeflag)
14973 {
14974   if (modrm.mod != 3)
14975     {
14976       if (vex.register_specifier != 0)
14977         BadOp ();
14978       need_vex_reg = 0;
14979     }
14980   OP_EX (bytemode, sizeflag);
14981 }
14982
14983 static void
14984 OP_XMM_Vex (int bytemode, int sizeflag)
14985 {
14986   if (modrm.mod != 3)
14987     {
14988       if (vex.register_specifier != 0)
14989         BadOp ();
14990       need_vex_reg = 0;
14991     }
14992   OP_XMM (bytemode, sizeflag);
14993 }
14994
14995 static void
14996 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14997 {
14998   switch (vex.length)
14999     {
15000     case 128:
15001       mnemonicendp = stpcpy (obuf, "vzeroupper");
15002       break;
15003     case 256:
15004       mnemonicendp = stpcpy (obuf, "vzeroall");
15005       break;
15006     default:
15007       abort ();
15008     }
15009 }
15010
15011 static struct op vex_cmp_op[] =
15012 {
15013   { STRING_COMMA_LEN ("eq") },
15014   { STRING_COMMA_LEN ("lt") },
15015   { STRING_COMMA_LEN ("le") },
15016   { STRING_COMMA_LEN ("unord") },
15017   { STRING_COMMA_LEN ("neq") },
15018   { STRING_COMMA_LEN ("nlt") },
15019   { STRING_COMMA_LEN ("nle") },
15020   { STRING_COMMA_LEN ("ord") },
15021   { STRING_COMMA_LEN ("eq_uq") },
15022   { STRING_COMMA_LEN ("nge") },
15023   { STRING_COMMA_LEN ("ngt") },
15024   { STRING_COMMA_LEN ("false") },
15025   { STRING_COMMA_LEN ("neq_oq") },
15026   { STRING_COMMA_LEN ("ge") },
15027   { STRING_COMMA_LEN ("gt") },
15028   { STRING_COMMA_LEN ("true") },
15029   { STRING_COMMA_LEN ("eq_os") },
15030   { STRING_COMMA_LEN ("lt_oq") },
15031   { STRING_COMMA_LEN ("le_oq") },
15032   { STRING_COMMA_LEN ("unord_s") },
15033   { STRING_COMMA_LEN ("neq_us") },
15034   { STRING_COMMA_LEN ("nlt_uq") },
15035   { STRING_COMMA_LEN ("nle_uq") },
15036   { STRING_COMMA_LEN ("ord_s") },
15037   { STRING_COMMA_LEN ("eq_us") },
15038   { STRING_COMMA_LEN ("nge_uq") },
15039   { STRING_COMMA_LEN ("ngt_uq") },
15040   { STRING_COMMA_LEN ("false_os") },
15041   { STRING_COMMA_LEN ("neq_os") },
15042   { STRING_COMMA_LEN ("ge_oq") },
15043   { STRING_COMMA_LEN ("gt_oq") },
15044   { STRING_COMMA_LEN ("true_us") },
15045 };
15046
15047 static void
15048 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15049 {
15050   unsigned int cmp_type;
15051
15052   FETCH_DATA (the_info, codep + 1);
15053   cmp_type = *codep++ & 0xff;
15054   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15055     {
15056       char suffix [3];
15057       char *p = mnemonicendp - 2;
15058       suffix[0] = p[0];
15059       suffix[1] = p[1];
15060       suffix[2] = '\0';
15061       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15062       mnemonicendp += vex_cmp_op[cmp_type].len;
15063     }
15064   else
15065     {
15066       /* We have a reserved extension byte.  Output it directly.  */
15067       scratchbuf[0] = '$';
15068       print_operand_value (scratchbuf + 1, 1, cmp_type);
15069       oappend (scratchbuf + intel_syntax);
15070       scratchbuf[0] = '\0';
15071     }
15072 }
15073
15074 static const struct op pclmul_op[] =
15075 {
15076   { STRING_COMMA_LEN ("lql") },
15077   { STRING_COMMA_LEN ("hql") },
15078   { STRING_COMMA_LEN ("lqh") },
15079   { STRING_COMMA_LEN ("hqh") }
15080 };
15081
15082 static void
15083 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15084               int sizeflag ATTRIBUTE_UNUSED)
15085 {
15086   unsigned int pclmul_type;
15087
15088   FETCH_DATA (the_info, codep + 1);
15089   pclmul_type = *codep++ & 0xff;
15090   switch (pclmul_type)
15091     {
15092     case 0x10:
15093       pclmul_type = 2;
15094       break;
15095     case 0x11:
15096       pclmul_type = 3;
15097       break;
15098     default:
15099       break;
15100     }
15101   if (pclmul_type < ARRAY_SIZE (pclmul_op))
15102     {
15103       char suffix [4];
15104       char *p = mnemonicendp - 3;
15105       suffix[0] = p[0];
15106       suffix[1] = p[1];
15107       suffix[2] = p[2];
15108       suffix[3] = '\0';
15109       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15110       mnemonicendp += pclmul_op[pclmul_type].len;
15111     }
15112   else
15113     {
15114       /* We have a reserved extension byte.  Output it directly.  */
15115       scratchbuf[0] = '$';
15116       print_operand_value (scratchbuf + 1, 1, pclmul_type);
15117       oappend (scratchbuf + intel_syntax);
15118       scratchbuf[0] = '\0';
15119     }
15120 }
15121
15122 static void
15123 MOVBE_Fixup (int bytemode, int sizeflag)
15124 {
15125   /* Add proper suffix to "movbe".  */
15126   char *p = mnemonicendp;
15127
15128   switch (bytemode)
15129     {
15130     case v_mode:
15131       if (intel_syntax)
15132         goto skip;
15133
15134       USED_REX (REX_W);
15135       if (sizeflag & SUFFIX_ALWAYS)
15136         {
15137           if (rex & REX_W)
15138             *p++ = 'q';
15139           else
15140             {
15141               if (sizeflag & DFLAG)
15142                 *p++ = 'l';
15143               else
15144                 *p++ = 'w';
15145               used_prefixes |= (prefixes & PREFIX_DATA);
15146             }
15147         }
15148       break;
15149     default:
15150       oappend (INTERNAL_DISASSEMBLER_ERROR);
15151       break;
15152     }
15153   mnemonicendp = p;
15154   *p = '\0';
15155
15156 skip:
15157   OP_M (bytemode, sizeflag);
15158 }
15159
15160 static void
15161 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15162 {
15163   int reg;
15164   const char **names;
15165
15166   /* Skip mod/rm byte.  */
15167   MODRM_CHECK;
15168   codep++;
15169
15170   if (vex.w)
15171     names = names64;
15172   else
15173     names = names32;
15174
15175   reg = modrm.rm;
15176   USED_REX (REX_B);
15177   if (rex & REX_B)
15178     reg += 8;
15179
15180   oappend (names[reg]);
15181 }
15182
15183 static void
15184 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15185 {
15186   const char **names;
15187
15188   if (vex.w)
15189     names = names64;
15190   else
15191     names = names32;
15192
15193   oappend (names[vex.register_specifier]);
15194 }
15195