opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void CMPXCHG8B_Fixup (int, int);
 112 static void XMM_Fixup (int, int);
 113 static void CRC32_Fixup (int, int);
 114 static void FXSAVE_Fixup (int, int);
 115 static void OP_LWPCB_E (int, int);
 116 static void OP_LWP_E (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* REX bits in original REX prefix ignored.  */
 148 static int rex_ignored;
 149 /* Mark parts used in the REX prefix.  When we are testing for
 150    empty prefix (for 8bit register REX extension), just mask it
 151    out.  Otherwise test for REX bit is excuse for existence of REX
 152    only in case value is nonzero.  */
 153 #define USED_REX(value)                                 \
 154   {                                                     \
 155     if (value)                                          \
 156       {                                                 \
 157         if ((rex & value))                              \
 158           rex_used |= (value) | REX_OPCODE;             \
 159       }                                                 \
 160     else                                                \
 161       rex_used |= REX_OPCODE;                           \
 162   }
 163
 164 /* Flags for prefixes which we somehow handled when printing the
 165    current instruction.  */
 166 static int used_prefixes;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       longjmp (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 #define XX { NULL, 0 }
 219 #define Bad_Opcode NULL, { { NULL, 0 } }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define Iv { OP_I, v_mode }
 256 #define sIv { OP_sI, v_mode }
 257 #define Iq { OP_I, q_mode }
 258 #define Iv64 { OP_I64, v_mode }
 259 #define Iw { OP_I, w_mode }
 260 #define I1 { OP_I, const_1_mode }
 261 #define Jb { OP_J, b_mode }
 262 #define Jv { OP_J, v_mode }
 263 #define Cm { OP_C, m_mode }
 264 #define Dm { OP_D, m_mode }
 265 #define Td { OP_T, d_mode }
 266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 267
 268 #define RMeAX { OP_REG, eAX_reg }
 269 #define RMeBX { OP_REG, eBX_reg }
 270 #define RMeCX { OP_REG, eCX_reg }
 271 #define RMeDX { OP_REG, eDX_reg }
 272 #define RMeSP { OP_REG, eSP_reg }
 273 #define RMeBP { OP_REG, eBP_reg }
 274 #define RMeSI { OP_REG, eSI_reg }
 275 #define RMeDI { OP_REG, eDI_reg }
 276 #define RMrAX { OP_REG, rAX_reg }
 277 #define RMrBX { OP_REG, rBX_reg }
 278 #define RMrCX { OP_REG, rCX_reg }
 279 #define RMrDX { OP_REG, rDX_reg }
 280 #define RMrSP { OP_REG, rSP_reg }
 281 #define RMrBP { OP_REG, rBP_reg }
 282 #define RMrSI { OP_REG, rSI_reg }
 283 #define RMrDI { OP_REG, rDI_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMCL { OP_REG, cl_reg }
 286 #define RMDL { OP_REG, dl_reg }
 287 #define RMBL { OP_REG, bl_reg }
 288 #define RMAH { OP_REG, ah_reg }
 289 #define RMCH { OP_REG, ch_reg }
 290 #define RMDH { OP_REG, dh_reg }
 291 #define RMBH { OP_REG, bh_reg }
 292 #define RMAX { OP_REG, ax_reg }
 293 #define RMDX { OP_REG, dx_reg }
 294
 295 #define eAX { OP_IMREG, eAX_reg }
 296 #define eBX { OP_IMREG, eBX_reg }
 297 #define eCX { OP_IMREG, eCX_reg }
 298 #define eDX { OP_IMREG, eDX_reg }
 299 #define eSP { OP_IMREG, eSP_reg }
 300 #define eBP { OP_IMREG, eBP_reg }
 301 #define eSI { OP_IMREG, eSI_reg }
 302 #define eDI { OP_IMREG, eDI_reg }
 303 #define AL { OP_IMREG, al_reg }
 304 #define CL { OP_IMREG, cl_reg }
 305 #define DL { OP_IMREG, dl_reg }
 306 #define BL { OP_IMREG, bl_reg }
 307 #define AH { OP_IMREG, ah_reg }
 308 #define CH { OP_IMREG, ch_reg }
 309 #define DH { OP_IMREG, dh_reg }
 310 #define BH { OP_IMREG, bh_reg }
 311 #define AX { OP_IMREG, ax_reg }
 312 #define DX { OP_IMREG, dx_reg }
 313 #define zAX { OP_IMREG, z_mode_ax_reg }
 314 #define indirDX { OP_IMREG, indir_dx_reg }
 315
 316 #define Sw { OP_SEG, w_mode }
 317 #define Sv { OP_SEG, v_mode }
 318 #define Ap { OP_DIR, 0 }
 319 #define Ob { OP_OFF64, b_mode }
 320 #define Ov { OP_OFF64, v_mode }
 321 #define Xb { OP_DSreg, eSI_reg }
 322 #define Xv { OP_DSreg, eSI_reg }
 323 #define Xz { OP_DSreg, eSI_reg }
 324 #define Yb { OP_ESreg, eDI_reg }
 325 #define Yv { OP_ESreg, eDI_reg }
 326 #define DSBX { OP_DSreg, eBX_reg }
 327
 328 #define es { OP_REG, es_reg }
 329 #define ss { OP_REG, ss_reg }
 330 #define cs { OP_REG, cs_reg }
 331 #define ds { OP_REG, ds_reg }
 332 #define fs { OP_REG, fs_reg }
 333 #define gs { OP_REG, gs_reg }
 334
 335 #define MX { OP_MMX, 0 }
 336 #define XM { OP_XMM, 0 }
 337 #define XMScalar { OP_XMM, scalar_mode }
 338 #define XMM { OP_XMM, xmm_mode }
 339 #define EM { OP_EM, v_mode }
 340 #define EMS { OP_EM, v_swap_mode }
 341 #define EMd { OP_EM, d_mode }
 342 #define EMx { OP_EM, x_mode }
 343 #define EXw { OP_EX, w_mode }
 344 #define EXd { OP_EX, d_mode }
 345 #define EXdScalar { OP_EX, d_scalar_mode }
 346 #define EXdS { OP_EX, d_swap_mode }
 347 #define EXq { OP_EX, q_mode }
 348 #define EXqScalar { OP_EX, q_scalar_mode }
 349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 350 #define EXqS { OP_EX, q_swap_mode }
 351 #define EXx { OP_EX, x_mode }
 352 #define EXxS { OP_EX, x_swap_mode }
 353 #define EXxmm { OP_EX, xmm_mode }
 354 #define EXxmmq { OP_EX, xmmq_mode }
 355 #define EXymmq { OP_EX, ymmq_mode }
 356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 357 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 358 #define MS { OP_MS, v_mode }
 359 #define XS { OP_XS, v_mode }
 360 #define EMCq { OP_EMC, q_mode }
 361 #define MXC { OP_MXC, 0 }
 362 #define OPSUF { OP_3DNowSuffix, 0 }
 363 #define CMP { CMP_Fixup, 0 }
 364 #define XMM0 { XMM_Fixup, 0 }
 365 #define FXSAVE { FXSAVE_Fixup, 0 }
 366 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 367 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 368
 369 #define Vex { OP_VEX, vex_mode }
 370 #define VexScalar { OP_VEX, vex_scalar_mode }
 371 #define Vex128 { OP_VEX, vex128_mode }
 372 #define Vex256 { OP_VEX, vex256_mode }
 373 #define VexGdq { OP_VEX, dq_mode }
 374 #define VexI4 { VEXI4_Fixup, 0}
 375 #define EXdVex { OP_EX_Vex, d_mode }
 376 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 377 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 378 #define EXqVex { OP_EX_Vex, q_mode }
 379 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 380 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 381 #define EXVexW { OP_EX_VexW, x_mode }
 382 #define EXdVexW { OP_EX_VexW, d_mode }
 383 #define EXqVexW { OP_EX_VexW, q_mode }
 384 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 385 #define XMVex { OP_XMM_Vex, 0 }
 386 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 387 #define XMVexW { OP_XMM_VexW, 0 }
 388 #define XMVexI4 { OP_REG_VexI4, x_mode }
 389 #define PCLMUL { PCLMUL_Fixup, 0 }
 390 #define VZERO { VZERO_Fixup, 0 }
 391 #define VCMP { VCMP_Fixup, 0 }
 392
 393 /* Used handle "rep" prefix for string instructions.  */
 394 #define Xbr { REP_Fixup, eSI_reg }
 395 #define Xvr { REP_Fixup, eSI_reg }
 396 #define Ybr { REP_Fixup, eDI_reg }
 397 #define Yvr { REP_Fixup, eDI_reg }
 398 #define Yzr { REP_Fixup, eDI_reg }
 399 #define indirDXr { REP_Fixup, indir_dx_reg }
 400 #define ALr { REP_Fixup, al_reg }
 401 #define eAXr { REP_Fixup, eAX_reg }
 402
 403 #define cond_jump_flag { NULL, cond_jump_mode }
 404 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 405
 406 /* bits in sizeflag */
 407 #define SUFFIX_ALWAYS 4
 408 #define AFLAG 2
 409 #define DFLAG 1
 410
 411 enum
 412 {
 413   /* byte operand */
 414   b_mode = 1,
 415   /* byte operand with operand swapped */
 416   b_swap_mode,
 417   /* operand size depends on prefixes */
 418   v_mode,
 419   /* operand size depends on prefixes with operand swapped */
 420   v_swap_mode,
 421   /* word operand */
 422   w_mode,
 423   /* double word operand  */
 424   d_mode,
 425   /* double word operand with operand swapped */
 426   d_swap_mode,
 427   /* quad word operand */
 428   q_mode,
 429   /* quad word operand with operand swapped */
 430   q_swap_mode,
 431   /* ten-byte operand */
 432   t_mode,
 433   /* 16-byte XMM or 32-byte YMM operand */
 434   x_mode,
 435   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 436   x_swap_mode,
 437   /* 16-byte XMM operand */
 438   xmm_mode,
 439   /* 16-byte XMM or quad word operand */
 440   xmmq_mode,
 441   /* 32-byte YMM or quad word operand */
 442   ymmq_mode,
 443   /* d_mode in 32bit, q_mode in 64bit mode.  */
 444   m_mode,
 445   /* pair of v_mode operands */
 446   a_mode,
 447   cond_jump_mode,
 448   loop_jcxz_mode,
 449   /* operand size depends on REX prefixes.  */
 450   dq_mode,
 451   /* registers like dq_mode, memory like w_mode.  */
 452   dqw_mode,
 453   /* 4- or 6-byte pointer operand */
 454   f_mode,
 455   const_1_mode,
 456   /* v_mode for stack-related opcodes.  */
 457   stack_v_mode,
 458   /* non-quad operand size depends on prefixes */
 459   z_mode,
 460   /* 16-byte operand */
 461   o_mode,
 462   /* registers like dq_mode, memory like b_mode.  */
 463   dqb_mode,
 464   /* registers like dq_mode, memory like d_mode.  */
 465   dqd_mode,
 466   /* normal vex mode */
 467   vex_mode,
 468   /* 128bit vex mode */
 469   vex128_mode,
 470   /* 256bit vex mode */
 471   vex256_mode,
 472   /* operand size depends on the VEX.W bit.  */
 473   vex_w_dq_mode,
 474
 475   /* scalar, ignore vector length.  */
 476   scalar_mode,
 477   /* like d_mode, ignore vector length.  */
 478   d_scalar_mode,
 479   /* like d_swap_mode, ignore vector length.  */
 480   d_scalar_swap_mode,
 481   /* like q_mode, ignore vector length.  */
 482   q_scalar_mode,
 483   /* like q_swap_mode, ignore vector length.  */
 484   q_scalar_swap_mode,
 485   /* like vex_mode, ignore vector length.  */
 486   vex_scalar_mode,
 487   /* like vex_w_dq_mode, ignore vector length.  */
 488   vex_scalar_w_dq_mode,
 489
 490   es_reg,
 491   cs_reg,
 492   ss_reg,
 493   ds_reg,
 494   fs_reg,
 495   gs_reg,
 496
 497   eAX_reg,
 498   eCX_reg,
 499   eDX_reg,
 500   eBX_reg,
 501   eSP_reg,
 502   eBP_reg,
 503   eSI_reg,
 504   eDI_reg,
 505
 506   al_reg,
 507   cl_reg,
 508   dl_reg,
 509   bl_reg,
 510   ah_reg,
 511   ch_reg,
 512   dh_reg,
 513   bh_reg,
 514
 515   ax_reg,
 516   cx_reg,
 517   dx_reg,
 518   bx_reg,
 519   sp_reg,
 520   bp_reg,
 521   si_reg,
 522   di_reg,
 523
 524   rAX_reg,
 525   rCX_reg,
 526   rDX_reg,
 527   rBX_reg,
 528   rSP_reg,
 529   rBP_reg,
 530   rSI_reg,
 531   rDI_reg,
 532
 533   z_mode_ax_reg,
 534   indir_dx_reg
 535 };
 536
 537 enum
 538 {
 539   FLOATCODE = 1,
 540   USE_REG_TABLE,
 541   USE_MOD_TABLE,
 542   USE_RM_TABLE,
 543   USE_PREFIX_TABLE,
 544   USE_X86_64_TABLE,
 545   USE_3BYTE_TABLE,
 546   USE_XOP_8F_TABLE,
 547   USE_VEX_C4_TABLE,
 548   USE_VEX_C5_TABLE,
 549   USE_VEX_LEN_TABLE,
 550   USE_VEX_W_TABLE
 551 };
 552
 553 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 554
 555 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 556 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 557 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 558 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 559 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 560 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 561 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 562 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 563 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 564 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 565 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 566 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 567
 568 enum
 569 {
 570   REG_80 = 0,
 571   REG_81,
 572   REG_82,
 573   REG_8F,
 574   REG_C0,
 575   REG_C1,
 576   REG_C6,
 577   REG_C7,
 578   REG_D0,
 579   REG_D1,
 580   REG_D2,
 581   REG_D3,
 582   REG_F6,
 583   REG_F7,
 584   REG_FE,
 585   REG_FF,
 586   REG_0F00,
 587   REG_0F01,
 588   REG_0F0D,
 589   REG_0F18,
 590   REG_0F71,
 591   REG_0F72,
 592   REG_0F73,
 593   REG_0FA6,
 594   REG_0FA7,
 595   REG_0FAE,
 596   REG_0FBA,
 597   REG_0FC7,
 598   REG_VEX_0F71,
 599   REG_VEX_0F72,
 600   REG_VEX_0F73,
 601   REG_VEX_0FAE,
 602   REG_VEX_0F38F3,
 603   REG_XOP_LWPCB,
 604   REG_XOP_LWP
 605 };
 606
 607 enum
 608 {
 609   MOD_8D = 0,
 610   MOD_0F01_REG_0,
 611   MOD_0F01_REG_1,
 612   MOD_0F01_REG_2,
 613   MOD_0F01_REG_3,
 614   MOD_0F01_REG_7,
 615   MOD_0F12_PREFIX_0,
 616   MOD_0F13,
 617   MOD_0F16_PREFIX_0,
 618   MOD_0F17,
 619   MOD_0F18_REG_0,
 620   MOD_0F18_REG_1,
 621   MOD_0F18_REG_2,
 622   MOD_0F18_REG_3,
 623   MOD_0F20,
 624   MOD_0F21,
 625   MOD_0F22,
 626   MOD_0F23,
 627   MOD_0F24,
 628   MOD_0F26,
 629   MOD_0F2B_PREFIX_0,
 630   MOD_0F2B_PREFIX_1,
 631   MOD_0F2B_PREFIX_2,
 632   MOD_0F2B_PREFIX_3,
 633   MOD_0F51,
 634   MOD_0F71_REG_2,
 635   MOD_0F71_REG_4,
 636   MOD_0F71_REG_6,
 637   MOD_0F72_REG_2,
 638   MOD_0F72_REG_4,
 639   MOD_0F72_REG_6,
 640   MOD_0F73_REG_2,
 641   MOD_0F73_REG_3,
 642   MOD_0F73_REG_6,
 643   MOD_0F73_REG_7,
 644   MOD_0FAE_REG_0,
 645   MOD_0FAE_REG_1,
 646   MOD_0FAE_REG_2,
 647   MOD_0FAE_REG_3,
 648   MOD_0FAE_REG_4,
 649   MOD_0FAE_REG_5,
 650   MOD_0FAE_REG_6,
 651   MOD_0FAE_REG_7,
 652   MOD_0FB2,
 653   MOD_0FB4,
 654   MOD_0FB5,
 655   MOD_0FC7_REG_6,
 656   MOD_0FC7_REG_7,
 657   MOD_0FD7,
 658   MOD_0FE7_PREFIX_2,
 659   MOD_0FF0_PREFIX_3,
 660   MOD_0F382A_PREFIX_2,
 661   MOD_62_32BIT,
 662   MOD_C4_32BIT,
 663   MOD_C5_32BIT,
 664   MOD_VEX_0F12_PREFIX_0,
 665   MOD_VEX_0F13,
 666   MOD_VEX_0F16_PREFIX_0,
 667   MOD_VEX_0F17,
 668   MOD_VEX_0F2B,
 669   MOD_VEX_0F50,
 670   MOD_VEX_0F71_REG_2,
 671   MOD_VEX_0F71_REG_4,
 672   MOD_VEX_0F71_REG_6,
 673   MOD_VEX_0F72_REG_2,
 674   MOD_VEX_0F72_REG_4,
 675   MOD_VEX_0F72_REG_6,
 676   MOD_VEX_0F73_REG_2,
 677   MOD_VEX_0F73_REG_3,
 678   MOD_VEX_0F73_REG_6,
 679   MOD_VEX_0F73_REG_7,
 680   MOD_VEX_0FAE_REG_2,
 681   MOD_VEX_0FAE_REG_3,
 682   MOD_VEX_0FD7_PREFIX_2,
 683   MOD_VEX_0FE7_PREFIX_2,
 684   MOD_VEX_0FF0_PREFIX_3,
 685   MOD_VEX_0F3818_PREFIX_2,
 686   MOD_VEX_0F3819_PREFIX_2,
 687   MOD_VEX_0F381A_PREFIX_2,
 688   MOD_VEX_0F382A_PREFIX_2,
 689   MOD_VEX_0F382C_PREFIX_2,
 690   MOD_VEX_0F382D_PREFIX_2,
 691   MOD_VEX_0F382E_PREFIX_2,
 692   MOD_VEX_0F382F_PREFIX_2
 693 };
 694
 695 enum
 696 {
 697   RM_0F01_REG_0 = 0,
 698   RM_0F01_REG_1,
 699   RM_0F01_REG_2,
 700   RM_0F01_REG_3,
 701   RM_0F01_REG_7,
 702   RM_0FAE_REG_5,
 703   RM_0FAE_REG_6,
 704   RM_0FAE_REG_7
 705 };
 706
 707 enum
 708 {
 709   PREFIX_90 = 0,
 710   PREFIX_0F10,
 711   PREFIX_0F11,
 712   PREFIX_0F12,
 713   PREFIX_0F16,
 714   PREFIX_0F2A,
 715   PREFIX_0F2B,
 716   PREFIX_0F2C,
 717   PREFIX_0F2D,
 718   PREFIX_0F2E,
 719   PREFIX_0F2F,
 720   PREFIX_0F51,
 721   PREFIX_0F52,
 722   PREFIX_0F53,
 723   PREFIX_0F58,
 724   PREFIX_0F59,
 725   PREFIX_0F5A,
 726   PREFIX_0F5B,
 727   PREFIX_0F5C,
 728   PREFIX_0F5D,
 729   PREFIX_0F5E,
 730   PREFIX_0F5F,
 731   PREFIX_0F60,
 732   PREFIX_0F61,
 733   PREFIX_0F62,
 734   PREFIX_0F6C,
 735   PREFIX_0F6D,
 736   PREFIX_0F6F,
 737   PREFIX_0F70,
 738   PREFIX_0F73_REG_3,
 739   PREFIX_0F73_REG_7,
 740   PREFIX_0F78,
 741   PREFIX_0F79,
 742   PREFIX_0F7C,
 743   PREFIX_0F7D,
 744   PREFIX_0F7E,
 745   PREFIX_0F7F,
 746   PREFIX_0FAE_REG_0,
 747   PREFIX_0FAE_REG_1,
 748   PREFIX_0FAE_REG_2,
 749   PREFIX_0FAE_REG_3,
 750   PREFIX_0FB8,
 751   PREFIX_0FBC,
 752   PREFIX_0FBD,
 753   PREFIX_0FC2,
 754   PREFIX_0FC3,
 755   PREFIX_0FC7_REG_6,
 756   PREFIX_0FD0,
 757   PREFIX_0FD6,
 758   PREFIX_0FE6,
 759   PREFIX_0FE7,
 760   PREFIX_0FF0,
 761   PREFIX_0FF7,
 762   PREFIX_0F3810,
 763   PREFIX_0F3814,
 764   PREFIX_0F3815,
 765   PREFIX_0F3817,
 766   PREFIX_0F3820,
 767   PREFIX_0F3821,
 768   PREFIX_0F3822,
 769   PREFIX_0F3823,
 770   PREFIX_0F3824,
 771   PREFIX_0F3825,
 772   PREFIX_0F3828,
 773   PREFIX_0F3829,
 774   PREFIX_0F382A,
 775   PREFIX_0F382B,
 776   PREFIX_0F3830,
 777   PREFIX_0F3831,
 778   PREFIX_0F3832,
 779   PREFIX_0F3833,
 780   PREFIX_0F3834,
 781   PREFIX_0F3835,
 782   PREFIX_0F3837,
 783   PREFIX_0F3838,
 784   PREFIX_0F3839,
 785   PREFIX_0F383A,
 786   PREFIX_0F383B,
 787   PREFIX_0F383C,
 788   PREFIX_0F383D,
 789   PREFIX_0F383E,
 790   PREFIX_0F383F,
 791   PREFIX_0F3840,
 792   PREFIX_0F3841,
 793   PREFIX_0F3880,
 794   PREFIX_0F3881,
 795   PREFIX_0F38DB,
 796   PREFIX_0F38DC,
 797   PREFIX_0F38DD,
 798   PREFIX_0F38DE,
 799   PREFIX_0F38DF,
 800   PREFIX_0F38F0,
 801   PREFIX_0F38F1,
 802   PREFIX_0F3A08,
 803   PREFIX_0F3A09,
 804   PREFIX_0F3A0A,
 805   PREFIX_0F3A0B,
 806   PREFIX_0F3A0C,
 807   PREFIX_0F3A0D,
 808   PREFIX_0F3A0E,
 809   PREFIX_0F3A14,
 810   PREFIX_0F3A15,
 811   PREFIX_0F3A16,
 812   PREFIX_0F3A17,
 813   PREFIX_0F3A20,
 814   PREFIX_0F3A21,
 815   PREFIX_0F3A22,
 816   PREFIX_0F3A40,
 817   PREFIX_0F3A41,
 818   PREFIX_0F3A42,
 819   PREFIX_0F3A44,
 820   PREFIX_0F3A60,
 821   PREFIX_0F3A61,
 822   PREFIX_0F3A62,
 823   PREFIX_0F3A63,
 824   PREFIX_0F3ADF,
 825   PREFIX_VEX_0F10,
 826   PREFIX_VEX_0F11,
 827   PREFIX_VEX_0F12,
 828   PREFIX_VEX_0F16,
 829   PREFIX_VEX_0F2A,
 830   PREFIX_VEX_0F2C,
 831   PREFIX_VEX_0F2D,
 832   PREFIX_VEX_0F2E,
 833   PREFIX_VEX_0F2F,
 834   PREFIX_VEX_0F51,
 835   PREFIX_VEX_0F52,
 836   PREFIX_VEX_0F53,
 837   PREFIX_VEX_0F58,
 838   PREFIX_VEX_0F59,
 839   PREFIX_VEX_0F5A,
 840   PREFIX_VEX_0F5B,
 841   PREFIX_VEX_0F5C,
 842   PREFIX_VEX_0F5D,
 843   PREFIX_VEX_0F5E,
 844   PREFIX_VEX_0F5F,
 845   PREFIX_VEX_0F60,
 846   PREFIX_VEX_0F61,
 847   PREFIX_VEX_0F62,
 848   PREFIX_VEX_0F63,
 849   PREFIX_VEX_0F64,
 850   PREFIX_VEX_0F65,
 851   PREFIX_VEX_0F66,
 852   PREFIX_VEX_0F67,
 853   PREFIX_VEX_0F68,
 854   PREFIX_VEX_0F69,
 855   PREFIX_VEX_0F6A,
 856   PREFIX_VEX_0F6B,
 857   PREFIX_VEX_0F6C,
 858   PREFIX_VEX_0F6D,
 859   PREFIX_VEX_0F6E,
 860   PREFIX_VEX_0F6F,
 861   PREFIX_VEX_0F70,
 862   PREFIX_VEX_0F71_REG_2,
 863   PREFIX_VEX_0F71_REG_4,
 864   PREFIX_VEX_0F71_REG_6,
 865   PREFIX_VEX_0F72_REG_2,
 866   PREFIX_VEX_0F72_REG_4,
 867   PREFIX_VEX_0F72_REG_6,
 868   PREFIX_VEX_0F73_REG_2,
 869   PREFIX_VEX_0F73_REG_3,
 870   PREFIX_VEX_0F73_REG_6,
 871   PREFIX_VEX_0F73_REG_7,
 872   PREFIX_VEX_0F74,
 873   PREFIX_VEX_0F75,
 874   PREFIX_VEX_0F76,
 875   PREFIX_VEX_0F77,
 876   PREFIX_VEX_0F7C,
 877   PREFIX_VEX_0F7D,
 878   PREFIX_VEX_0F7E,
 879   PREFIX_VEX_0F7F,
 880   PREFIX_VEX_0FC2,
 881   PREFIX_VEX_0FC4,
 882   PREFIX_VEX_0FC5,
 883   PREFIX_VEX_0FD0,
 884   PREFIX_VEX_0FD1,
 885   PREFIX_VEX_0FD2,
 886   PREFIX_VEX_0FD3,
 887   PREFIX_VEX_0FD4,
 888   PREFIX_VEX_0FD5,
 889   PREFIX_VEX_0FD6,
 890   PREFIX_VEX_0FD7,
 891   PREFIX_VEX_0FD8,
 892   PREFIX_VEX_0FD9,
 893   PREFIX_VEX_0FDA,
 894   PREFIX_VEX_0FDB,
 895   PREFIX_VEX_0FDC,
 896   PREFIX_VEX_0FDD,
 897   PREFIX_VEX_0FDE,
 898   PREFIX_VEX_0FDF,
 899   PREFIX_VEX_0FE0,
 900   PREFIX_VEX_0FE1,
 901   PREFIX_VEX_0FE2,
 902   PREFIX_VEX_0FE3,
 903   PREFIX_VEX_0FE4,
 904   PREFIX_VEX_0FE5,
 905   PREFIX_VEX_0FE6,
 906   PREFIX_VEX_0FE7,
 907   PREFIX_VEX_0FE8,
 908   PREFIX_VEX_0FE9,
 909   PREFIX_VEX_0FEA,
 910   PREFIX_VEX_0FEB,
 911   PREFIX_VEX_0FEC,
 912   PREFIX_VEX_0FED,
 913   PREFIX_VEX_0FEE,
 914   PREFIX_VEX_0FEF,
 915   PREFIX_VEX_0FF0,
 916   PREFIX_VEX_0FF1,
 917   PREFIX_VEX_0FF2,
 918   PREFIX_VEX_0FF3,
 919   PREFIX_VEX_0FF4,
 920   PREFIX_VEX_0FF5,
 921   PREFIX_VEX_0FF6,
 922   PREFIX_VEX_0FF7,
 923   PREFIX_VEX_0FF8,
 924   PREFIX_VEX_0FF9,
 925   PREFIX_VEX_0FFA,
 926   PREFIX_VEX_0FFB,
 927   PREFIX_VEX_0FFC,
 928   PREFIX_VEX_0FFD,
 929   PREFIX_VEX_0FFE,
 930   PREFIX_VEX_0F3800,
 931   PREFIX_VEX_0F3801,
 932   PREFIX_VEX_0F3802,
 933   PREFIX_VEX_0F3803,
 934   PREFIX_VEX_0F3804,
 935   PREFIX_VEX_0F3805,
 936   PREFIX_VEX_0F3806,
 937   PREFIX_VEX_0F3807,
 938   PREFIX_VEX_0F3808,
 939   PREFIX_VEX_0F3809,
 940   PREFIX_VEX_0F380A,
 941   PREFIX_VEX_0F380B,
 942   PREFIX_VEX_0F380C,
 943   PREFIX_VEX_0F380D,
 944   PREFIX_VEX_0F380E,
 945   PREFIX_VEX_0F380F,
 946   PREFIX_VEX_0F3813,
 947   PREFIX_VEX_0F3817,
 948   PREFIX_VEX_0F3818,
 949   PREFIX_VEX_0F3819,
 950   PREFIX_VEX_0F381A,
 951   PREFIX_VEX_0F381C,
 952   PREFIX_VEX_0F381D,
 953   PREFIX_VEX_0F381E,
 954   PREFIX_VEX_0F3820,
 955   PREFIX_VEX_0F3821,
 956   PREFIX_VEX_0F3822,
 957   PREFIX_VEX_0F3823,
 958   PREFIX_VEX_0F3824,
 959   PREFIX_VEX_0F3825,
 960   PREFIX_VEX_0F3828,
 961   PREFIX_VEX_0F3829,
 962   PREFIX_VEX_0F382A,
 963   PREFIX_VEX_0F382B,
 964   PREFIX_VEX_0F382C,
 965   PREFIX_VEX_0F382D,
 966   PREFIX_VEX_0F382E,
 967   PREFIX_VEX_0F382F,
 968   PREFIX_VEX_0F3830,
 969   PREFIX_VEX_0F3831,
 970   PREFIX_VEX_0F3832,
 971   PREFIX_VEX_0F3833,
 972   PREFIX_VEX_0F3834,
 973   PREFIX_VEX_0F3835,
 974   PREFIX_VEX_0F3837,
 975   PREFIX_VEX_0F3838,
 976   PREFIX_VEX_0F3839,
 977   PREFIX_VEX_0F383A,
 978   PREFIX_VEX_0F383B,
 979   PREFIX_VEX_0F383C,
 980   PREFIX_VEX_0F383D,
 981   PREFIX_VEX_0F383E,
 982   PREFIX_VEX_0F383F,
 983   PREFIX_VEX_0F3840,
 984   PREFIX_VEX_0F3841,
 985   PREFIX_VEX_0F3896,
 986   PREFIX_VEX_0F3897,
 987   PREFIX_VEX_0F3898,
 988   PREFIX_VEX_0F3899,
 989   PREFIX_VEX_0F389A,
 990   PREFIX_VEX_0F389B,
 991   PREFIX_VEX_0F389C,
 992   PREFIX_VEX_0F389D,
 993   PREFIX_VEX_0F389E,
 994   PREFIX_VEX_0F389F,
 995   PREFIX_VEX_0F38A6,
 996   PREFIX_VEX_0F38A7,
 997   PREFIX_VEX_0F38A8,
 998   PREFIX_VEX_0F38A9,
 999   PREFIX_VEX_0F38AA,
1000   PREFIX_VEX_0F38AB,
1001   PREFIX_VEX_0F38AC,
1002   PREFIX_VEX_0F38AD,
1003   PREFIX_VEX_0F38AE,
1004   PREFIX_VEX_0F38AF,
1005   PREFIX_VEX_0F38B6,
1006   PREFIX_VEX_0F38B7,
1007   PREFIX_VEX_0F38B8,
1008   PREFIX_VEX_0F38B9,
1009   PREFIX_VEX_0F38BA,
1010   PREFIX_VEX_0F38BB,
1011   PREFIX_VEX_0F38BC,
1012   PREFIX_VEX_0F38BD,
1013   PREFIX_VEX_0F38BE,
1014   PREFIX_VEX_0F38BF,
1015   PREFIX_VEX_0F38DB,
1016   PREFIX_VEX_0F38DC,
1017   PREFIX_VEX_0F38DD,
1018   PREFIX_VEX_0F38DE,
1019   PREFIX_VEX_0F38DF,
1020   PREFIX_VEX_0F38F2,
1021   PREFIX_VEX_0F38F3_REG_1,
1022   PREFIX_VEX_0F38F3_REG_2,
1023   PREFIX_VEX_0F38F3_REG_3,
1024   PREFIX_VEX_0F38F7,
1025   PREFIX_VEX_0F3A04,
1026   PREFIX_VEX_0F3A05,
1027   PREFIX_VEX_0F3A06,
1028   PREFIX_VEX_0F3A08,
1029   PREFIX_VEX_0F3A09,
1030   PREFIX_VEX_0F3A0A,
1031   PREFIX_VEX_0F3A0B,
1032   PREFIX_VEX_0F3A0C,
1033   PREFIX_VEX_0F3A0D,
1034   PREFIX_VEX_0F3A0E,
1035   PREFIX_VEX_0F3A0F,
1036   PREFIX_VEX_0F3A14,
1037   PREFIX_VEX_0F3A15,
1038   PREFIX_VEX_0F3A16,
1039   PREFIX_VEX_0F3A17,
1040   PREFIX_VEX_0F3A18,
1041   PREFIX_VEX_0F3A19,
1042   PREFIX_VEX_0F3A1D,
1043   PREFIX_VEX_0F3A20,
1044   PREFIX_VEX_0F3A21,
1045   PREFIX_VEX_0F3A22,
1046   PREFIX_VEX_0F3A40,
1047   PREFIX_VEX_0F3A41,
1048   PREFIX_VEX_0F3A42,
1049   PREFIX_VEX_0F3A44,
1050   PREFIX_VEX_0F3A48,
1051   PREFIX_VEX_0F3A49,
1052   PREFIX_VEX_0F3A4A,
1053   PREFIX_VEX_0F3A4B,
1054   PREFIX_VEX_0F3A4C,
1055   PREFIX_VEX_0F3A5C,
1056   PREFIX_VEX_0F3A5D,
1057   PREFIX_VEX_0F3A5E,
1058   PREFIX_VEX_0F3A5F,
1059   PREFIX_VEX_0F3A60,
1060   PREFIX_VEX_0F3A61,
1061   PREFIX_VEX_0F3A62,
1062   PREFIX_VEX_0F3A63,
1063   PREFIX_VEX_0F3A68,
1064   PREFIX_VEX_0F3A69,
1065   PREFIX_VEX_0F3A6A,
1066   PREFIX_VEX_0F3A6B,
1067   PREFIX_VEX_0F3A6C,
1068   PREFIX_VEX_0F3A6D,
1069   PREFIX_VEX_0F3A6E,
1070   PREFIX_VEX_0F3A6F,
1071   PREFIX_VEX_0F3A78,
1072   PREFIX_VEX_0F3A79,
1073   PREFIX_VEX_0F3A7A,
1074   PREFIX_VEX_0F3A7B,
1075   PREFIX_VEX_0F3A7C,
1076   PREFIX_VEX_0F3A7D,
1077   PREFIX_VEX_0F3A7E,
1078   PREFIX_VEX_0F3A7F,
1079   PREFIX_VEX_0F3ADF
1080 };
1081
1082 enum
1083 {
1084   X86_64_06 = 0,
1085   X86_64_07,
1086   X86_64_0D,
1087   X86_64_16,
1088   X86_64_17,
1089   X86_64_1E,
1090   X86_64_1F,
1091   X86_64_27,
1092   X86_64_2F,
1093   X86_64_37,
1094   X86_64_3F,
1095   X86_64_60,
1096   X86_64_61,
1097   X86_64_62,
1098   X86_64_63,
1099   X86_64_6D,
1100   X86_64_6F,
1101   X86_64_9A,
1102   X86_64_C4,
1103   X86_64_C5,
1104   X86_64_CE,
1105   X86_64_D4,
1106   X86_64_D5,
1107   X86_64_EA,
1108   X86_64_0F01_REG_0,
1109   X86_64_0F01_REG_1,
1110   X86_64_0F01_REG_2,
1111   X86_64_0F01_REG_3
1112 };
1113
1114 enum
1115 {
1116   THREE_BYTE_0F38 = 0,
1117   THREE_BYTE_0F3A,
1118   THREE_BYTE_0F7A
1119 };
1120
1121 enum
1122 {
1123   XOP_08 = 0,
1124   XOP_09,
1125   XOP_0A
1126 };
1127
1128 enum
1129 {
1130   VEX_0F = 0,
1131   VEX_0F38,
1132   VEX_0F3A
1133 };
1134
1135 enum
1136 {
1137   VEX_LEN_0F10_P_1 = 0,
1138   VEX_LEN_0F10_P_3,
1139   VEX_LEN_0F11_P_1,
1140   VEX_LEN_0F11_P_3,
1141   VEX_LEN_0F12_P_0_M_0,
1142   VEX_LEN_0F12_P_0_M_1,
1143   VEX_LEN_0F12_P_2,
1144   VEX_LEN_0F13_M_0,
1145   VEX_LEN_0F16_P_0_M_0,
1146   VEX_LEN_0F16_P_0_M_1,
1147   VEX_LEN_0F16_P_2,
1148   VEX_LEN_0F17_M_0,
1149   VEX_LEN_0F2A_P_1,
1150   VEX_LEN_0F2A_P_3,
1151   VEX_LEN_0F2C_P_1,
1152   VEX_LEN_0F2C_P_3,
1153   VEX_LEN_0F2D_P_1,
1154   VEX_LEN_0F2D_P_3,
1155   VEX_LEN_0F2E_P_0,
1156   VEX_LEN_0F2E_P_2,
1157   VEX_LEN_0F2F_P_0,
1158   VEX_LEN_0F2F_P_2,
1159   VEX_LEN_0F51_P_1,
1160   VEX_LEN_0F51_P_3,
1161   VEX_LEN_0F52_P_1,
1162   VEX_LEN_0F53_P_1,
1163   VEX_LEN_0F58_P_1,
1164   VEX_LEN_0F58_P_3,
1165   VEX_LEN_0F59_P_1,
1166   VEX_LEN_0F59_P_3,
1167   VEX_LEN_0F5A_P_1,
1168   VEX_LEN_0F5A_P_3,
1169   VEX_LEN_0F5C_P_1,
1170   VEX_LEN_0F5C_P_3,
1171   VEX_LEN_0F5D_P_1,
1172   VEX_LEN_0F5D_P_3,
1173   VEX_LEN_0F5E_P_1,
1174   VEX_LEN_0F5E_P_3,
1175   VEX_LEN_0F5F_P_1,
1176   VEX_LEN_0F5F_P_3,
1177   VEX_LEN_0F60_P_2,
1178   VEX_LEN_0F61_P_2,
1179   VEX_LEN_0F62_P_2,
1180   VEX_LEN_0F63_P_2,
1181   VEX_LEN_0F64_P_2,
1182   VEX_LEN_0F65_P_2,
1183   VEX_LEN_0F66_P_2,
1184   VEX_LEN_0F67_P_2,
1185   VEX_LEN_0F68_P_2,
1186   VEX_LEN_0F69_P_2,
1187   VEX_LEN_0F6A_P_2,
1188   VEX_LEN_0F6B_P_2,
1189   VEX_LEN_0F6C_P_2,
1190   VEX_LEN_0F6D_P_2,
1191   VEX_LEN_0F6E_P_2,
1192   VEX_LEN_0F70_P_1,
1193   VEX_LEN_0F70_P_2,
1194   VEX_LEN_0F70_P_3,
1195   VEX_LEN_0F71_R_2_P_2,
1196   VEX_LEN_0F71_R_4_P_2,
1197   VEX_LEN_0F71_R_6_P_2,
1198   VEX_LEN_0F72_R_2_P_2,
1199   VEX_LEN_0F72_R_4_P_2,
1200   VEX_LEN_0F72_R_6_P_2,
1201   VEX_LEN_0F73_R_2_P_2,
1202   VEX_LEN_0F73_R_3_P_2,
1203   VEX_LEN_0F73_R_6_P_2,
1204   VEX_LEN_0F73_R_7_P_2,
1205   VEX_LEN_0F74_P_2,
1206   VEX_LEN_0F75_P_2,
1207   VEX_LEN_0F76_P_2,
1208   VEX_LEN_0F7E_P_1,
1209   VEX_LEN_0F7E_P_2,
1210   VEX_LEN_0FAE_R_2_M_0,
1211   VEX_LEN_0FAE_R_3_M_0,
1212   VEX_LEN_0FC2_P_1,
1213   VEX_LEN_0FC2_P_3,
1214   VEX_LEN_0FC4_P_2,
1215   VEX_LEN_0FC5_P_2,
1216   VEX_LEN_0FD1_P_2,
1217   VEX_LEN_0FD2_P_2,
1218   VEX_LEN_0FD3_P_2,
1219   VEX_LEN_0FD4_P_2,
1220   VEX_LEN_0FD5_P_2,
1221   VEX_LEN_0FD6_P_2,
1222   VEX_LEN_0FD7_P_2_M_1,
1223   VEX_LEN_0FD8_P_2,
1224   VEX_LEN_0FD9_P_2,
1225   VEX_LEN_0FDA_P_2,
1226   VEX_LEN_0FDB_P_2,
1227   VEX_LEN_0FDC_P_2,
1228   VEX_LEN_0FDD_P_2,
1229   VEX_LEN_0FDE_P_2,
1230   VEX_LEN_0FDF_P_2,
1231   VEX_LEN_0FE0_P_2,
1232   VEX_LEN_0FE1_P_2,
1233   VEX_LEN_0FE2_P_2,
1234   VEX_LEN_0FE3_P_2,
1235   VEX_LEN_0FE4_P_2,
1236   VEX_LEN_0FE5_P_2,
1237   VEX_LEN_0FE8_P_2,
1238   VEX_LEN_0FE9_P_2,
1239   VEX_LEN_0FEA_P_2,
1240   VEX_LEN_0FEB_P_2,
1241   VEX_LEN_0FEC_P_2,
1242   VEX_LEN_0FED_P_2,
1243   VEX_LEN_0FEE_P_2,
1244   VEX_LEN_0FEF_P_2,
1245   VEX_LEN_0FF1_P_2,
1246   VEX_LEN_0FF2_P_2,
1247   VEX_LEN_0FF3_P_2,
1248   VEX_LEN_0FF4_P_2,
1249   VEX_LEN_0FF5_P_2,
1250   VEX_LEN_0FF6_P_2,
1251   VEX_LEN_0FF7_P_2,
1252   VEX_LEN_0FF8_P_2,
1253   VEX_LEN_0FF9_P_2,
1254   VEX_LEN_0FFA_P_2,
1255   VEX_LEN_0FFB_P_2,
1256   VEX_LEN_0FFC_P_2,
1257   VEX_LEN_0FFD_P_2,
1258   VEX_LEN_0FFE_P_2,
1259   VEX_LEN_0F3800_P_2,
1260   VEX_LEN_0F3801_P_2,
1261   VEX_LEN_0F3802_P_2,
1262   VEX_LEN_0F3803_P_2,
1263   VEX_LEN_0F3804_P_2,
1264   VEX_LEN_0F3805_P_2,
1265   VEX_LEN_0F3806_P_2,
1266   VEX_LEN_0F3807_P_2,
1267   VEX_LEN_0F3808_P_2,
1268   VEX_LEN_0F3809_P_2,
1269   VEX_LEN_0F380A_P_2,
1270   VEX_LEN_0F380B_P_2,
1271   VEX_LEN_0F3819_P_2_M_0,
1272   VEX_LEN_0F381A_P_2_M_0,
1273   VEX_LEN_0F381C_P_2,
1274   VEX_LEN_0F381D_P_2,
1275   VEX_LEN_0F381E_P_2,
1276   VEX_LEN_0F3820_P_2,
1277   VEX_LEN_0F3821_P_2,
1278   VEX_LEN_0F3822_P_2,
1279   VEX_LEN_0F3823_P_2,
1280   VEX_LEN_0F3824_P_2,
1281   VEX_LEN_0F3825_P_2,
1282   VEX_LEN_0F3828_P_2,
1283   VEX_LEN_0F3829_P_2,
1284   VEX_LEN_0F382A_P_2_M_0,
1285   VEX_LEN_0F382B_P_2,
1286   VEX_LEN_0F3830_P_2,
1287   VEX_LEN_0F3831_P_2,
1288   VEX_LEN_0F3832_P_2,
1289   VEX_LEN_0F3833_P_2,
1290   VEX_LEN_0F3834_P_2,
1291   VEX_LEN_0F3835_P_2,
1292   VEX_LEN_0F3837_P_2,
1293   VEX_LEN_0F3838_P_2,
1294   VEX_LEN_0F3839_P_2,
1295   VEX_LEN_0F383A_P_2,
1296   VEX_LEN_0F383B_P_2,
1297   VEX_LEN_0F383C_P_2,
1298   VEX_LEN_0F383D_P_2,
1299   VEX_LEN_0F383E_P_2,
1300   VEX_LEN_0F383F_P_2,
1301   VEX_LEN_0F3840_P_2,
1302   VEX_LEN_0F3841_P_2,
1303   VEX_LEN_0F38DB_P_2,
1304   VEX_LEN_0F38DC_P_2,
1305   VEX_LEN_0F38DD_P_2,
1306   VEX_LEN_0F38DE_P_2,
1307   VEX_LEN_0F38DF_P_2,
1308   VEX_LEN_0F38F2_P_0,
1309   VEX_LEN_0F38F3_R_1_P_0,
1310   VEX_LEN_0F38F3_R_2_P_0,
1311   VEX_LEN_0F38F3_R_3_P_0,
1312   VEX_LEN_0F38F7_P_0,
1313   VEX_LEN_0F3A06_P_2,
1314   VEX_LEN_0F3A0A_P_2,
1315   VEX_LEN_0F3A0B_P_2,
1316   VEX_LEN_0F3A0E_P_2,
1317   VEX_LEN_0F3A0F_P_2,
1318   VEX_LEN_0F3A14_P_2,
1319   VEX_LEN_0F3A15_P_2,
1320   VEX_LEN_0F3A16_P_2,
1321   VEX_LEN_0F3A17_P_2,
1322   VEX_LEN_0F3A18_P_2,
1323   VEX_LEN_0F3A19_P_2,
1324   VEX_LEN_0F3A20_P_2,
1325   VEX_LEN_0F3A21_P_2,
1326   VEX_LEN_0F3A22_P_2,
1327   VEX_LEN_0F3A41_P_2,
1328   VEX_LEN_0F3A42_P_2,
1329   VEX_LEN_0F3A44_P_2,
1330   VEX_LEN_0F3A4C_P_2,
1331   VEX_LEN_0F3A60_P_2,
1332   VEX_LEN_0F3A61_P_2,
1333   VEX_LEN_0F3A62_P_2,
1334   VEX_LEN_0F3A63_P_2,
1335   VEX_LEN_0F3A6A_P_2,
1336   VEX_LEN_0F3A6B_P_2,
1337   VEX_LEN_0F3A6E_P_2,
1338   VEX_LEN_0F3A6F_P_2,
1339   VEX_LEN_0F3A7A_P_2,
1340   VEX_LEN_0F3A7B_P_2,
1341   VEX_LEN_0F3A7E_P_2,
1342   VEX_LEN_0F3A7F_P_2,
1343   VEX_LEN_0F3ADF_P_2,
1344   VEX_LEN_0FXOP_09_80,
1345   VEX_LEN_0FXOP_09_81
1346 };
1347
1348 enum
1349 {
1350   VEX_W_0F10_P_0 = 0,
1351   VEX_W_0F10_P_1,
1352   VEX_W_0F10_P_2,
1353   VEX_W_0F10_P_3,
1354   VEX_W_0F11_P_0,
1355   VEX_W_0F11_P_1,
1356   VEX_W_0F11_P_2,
1357   VEX_W_0F11_P_3,
1358   VEX_W_0F12_P_0_M_0,
1359   VEX_W_0F12_P_0_M_1,
1360   VEX_W_0F12_P_1,
1361   VEX_W_0F12_P_2,
1362   VEX_W_0F12_P_3,
1363   VEX_W_0F13_M_0,
1364   VEX_W_0F14,
1365   VEX_W_0F15,
1366   VEX_W_0F16_P_0_M_0,
1367   VEX_W_0F16_P_0_M_1,
1368   VEX_W_0F16_P_1,
1369   VEX_W_0F16_P_2,
1370   VEX_W_0F17_M_0,
1371   VEX_W_0F28,
1372   VEX_W_0F29,
1373   VEX_W_0F2B_M_0,
1374   VEX_W_0F2E_P_0,
1375   VEX_W_0F2E_P_2,
1376   VEX_W_0F2F_P_0,
1377   VEX_W_0F2F_P_2,
1378   VEX_W_0F50_M_0,
1379   VEX_W_0F51_P_0,
1380   VEX_W_0F51_P_1,
1381   VEX_W_0F51_P_2,
1382   VEX_W_0F51_P_3,
1383   VEX_W_0F52_P_0,
1384   VEX_W_0F52_P_1,
1385   VEX_W_0F53_P_0,
1386   VEX_W_0F53_P_1,
1387   VEX_W_0F58_P_0,
1388   VEX_W_0F58_P_1,
1389   VEX_W_0F58_P_2,
1390   VEX_W_0F58_P_3,
1391   VEX_W_0F59_P_0,
1392   VEX_W_0F59_P_1,
1393   VEX_W_0F59_P_2,
1394   VEX_W_0F59_P_3,
1395   VEX_W_0F5A_P_0,
1396   VEX_W_0F5A_P_1,
1397   VEX_W_0F5A_P_3,
1398   VEX_W_0F5B_P_0,
1399   VEX_W_0F5B_P_1,
1400   VEX_W_0F5B_P_2,
1401   VEX_W_0F5C_P_0,
1402   VEX_W_0F5C_P_1,
1403   VEX_W_0F5C_P_2,
1404   VEX_W_0F5C_P_3,
1405   VEX_W_0F5D_P_0,
1406   VEX_W_0F5D_P_1,
1407   VEX_W_0F5D_P_2,
1408   VEX_W_0F5D_P_3,
1409   VEX_W_0F5E_P_0,
1410   VEX_W_0F5E_P_1,
1411   VEX_W_0F5E_P_2,
1412   VEX_W_0F5E_P_3,
1413   VEX_W_0F5F_P_0,
1414   VEX_W_0F5F_P_1,
1415   VEX_W_0F5F_P_2,
1416   VEX_W_0F5F_P_3,
1417   VEX_W_0F60_P_2,
1418   VEX_W_0F61_P_2,
1419   VEX_W_0F62_P_2,
1420   VEX_W_0F63_P_2,
1421   VEX_W_0F64_P_2,
1422   VEX_W_0F65_P_2,
1423   VEX_W_0F66_P_2,
1424   VEX_W_0F67_P_2,
1425   VEX_W_0F68_P_2,
1426   VEX_W_0F69_P_2,
1427   VEX_W_0F6A_P_2,
1428   VEX_W_0F6B_P_2,
1429   VEX_W_0F6C_P_2,
1430   VEX_W_0F6D_P_2,
1431   VEX_W_0F6F_P_1,
1432   VEX_W_0F6F_P_2,
1433   VEX_W_0F70_P_1,
1434   VEX_W_0F70_P_2,
1435   VEX_W_0F70_P_3,
1436   VEX_W_0F71_R_2_P_2,
1437   VEX_W_0F71_R_4_P_2,
1438   VEX_W_0F71_R_6_P_2,
1439   VEX_W_0F72_R_2_P_2,
1440   VEX_W_0F72_R_4_P_2,
1441   VEX_W_0F72_R_6_P_2,
1442   VEX_W_0F73_R_2_P_2,
1443   VEX_W_0F73_R_3_P_2,
1444   VEX_W_0F73_R_6_P_2,
1445   VEX_W_0F73_R_7_P_2,
1446   VEX_W_0F74_P_2,
1447   VEX_W_0F75_P_2,
1448   VEX_W_0F76_P_2,
1449   VEX_W_0F77_P_0,
1450   VEX_W_0F7C_P_2,
1451   VEX_W_0F7C_P_3,
1452   VEX_W_0F7D_P_2,
1453   VEX_W_0F7D_P_3,
1454   VEX_W_0F7E_P_1,
1455   VEX_W_0F7F_P_1,
1456   VEX_W_0F7F_P_2,
1457   VEX_W_0FAE_R_2_M_0,
1458   VEX_W_0FAE_R_3_M_0,
1459   VEX_W_0FC2_P_0,
1460   VEX_W_0FC2_P_1,
1461   VEX_W_0FC2_P_2,
1462   VEX_W_0FC2_P_3,
1463   VEX_W_0FC4_P_2,
1464   VEX_W_0FC5_P_2,
1465   VEX_W_0FD0_P_2,
1466   VEX_W_0FD0_P_3,
1467   VEX_W_0FD1_P_2,
1468   VEX_W_0FD2_P_2,
1469   VEX_W_0FD3_P_2,
1470   VEX_W_0FD4_P_2,
1471   VEX_W_0FD5_P_2,
1472   VEX_W_0FD6_P_2,
1473   VEX_W_0FD7_P_2_M_1,
1474   VEX_W_0FD8_P_2,
1475   VEX_W_0FD9_P_2,
1476   VEX_W_0FDA_P_2,
1477   VEX_W_0FDB_P_2,
1478   VEX_W_0FDC_P_2,
1479   VEX_W_0FDD_P_2,
1480   VEX_W_0FDE_P_2,
1481   VEX_W_0FDF_P_2,
1482   VEX_W_0FE0_P_2,
1483   VEX_W_0FE1_P_2,
1484   VEX_W_0FE2_P_2,
1485   VEX_W_0FE3_P_2,
1486   VEX_W_0FE4_P_2,
1487   VEX_W_0FE5_P_2,
1488   VEX_W_0FE6_P_1,
1489   VEX_W_0FE6_P_2,
1490   VEX_W_0FE6_P_3,
1491   VEX_W_0FE7_P_2_M_0,
1492   VEX_W_0FE8_P_2,
1493   VEX_W_0FE9_P_2,
1494   VEX_W_0FEA_P_2,
1495   VEX_W_0FEB_P_2,
1496   VEX_W_0FEC_P_2,
1497   VEX_W_0FED_P_2,
1498   VEX_W_0FEE_P_2,
1499   VEX_W_0FEF_P_2,
1500   VEX_W_0FF0_P_3_M_0,
1501   VEX_W_0FF1_P_2,
1502   VEX_W_0FF2_P_2,
1503   VEX_W_0FF3_P_2,
1504   VEX_W_0FF4_P_2,
1505   VEX_W_0FF5_P_2,
1506   VEX_W_0FF6_P_2,
1507   VEX_W_0FF7_P_2,
1508   VEX_W_0FF8_P_2,
1509   VEX_W_0FF9_P_2,
1510   VEX_W_0FFA_P_2,
1511   VEX_W_0FFB_P_2,
1512   VEX_W_0FFC_P_2,
1513   VEX_W_0FFD_P_2,
1514   VEX_W_0FFE_P_2,
1515   VEX_W_0F3800_P_2,
1516   VEX_W_0F3801_P_2,
1517   VEX_W_0F3802_P_2,
1518   VEX_W_0F3803_P_2,
1519   VEX_W_0F3804_P_2,
1520   VEX_W_0F3805_P_2,
1521   VEX_W_0F3806_P_2,
1522   VEX_W_0F3807_P_2,
1523   VEX_W_0F3808_P_2,
1524   VEX_W_0F3809_P_2,
1525   VEX_W_0F380A_P_2,
1526   VEX_W_0F380B_P_2,
1527   VEX_W_0F380C_P_2,
1528   VEX_W_0F380D_P_2,
1529   VEX_W_0F380E_P_2,
1530   VEX_W_0F380F_P_2,
1531   VEX_W_0F3817_P_2,
1532   VEX_W_0F3818_P_2_M_0,
1533   VEX_W_0F3819_P_2_M_0,
1534   VEX_W_0F381A_P_2_M_0,
1535   VEX_W_0F381C_P_2,
1536   VEX_W_0F381D_P_2,
1537   VEX_W_0F381E_P_2,
1538   VEX_W_0F3820_P_2,
1539   VEX_W_0F3821_P_2,
1540   VEX_W_0F3822_P_2,
1541   VEX_W_0F3823_P_2,
1542   VEX_W_0F3824_P_2,
1543   VEX_W_0F3825_P_2,
1544   VEX_W_0F3828_P_2,
1545   VEX_W_0F3829_P_2,
1546   VEX_W_0F382A_P_2_M_0,
1547   VEX_W_0F382B_P_2,
1548   VEX_W_0F382C_P_2_M_0,
1549   VEX_W_0F382D_P_2_M_0,
1550   VEX_W_0F382E_P_2_M_0,
1551   VEX_W_0F382F_P_2_M_0,
1552   VEX_W_0F3830_P_2,
1553   VEX_W_0F3831_P_2,
1554   VEX_W_0F3832_P_2,
1555   VEX_W_0F3833_P_2,
1556   VEX_W_0F3834_P_2,
1557   VEX_W_0F3835_P_2,
1558   VEX_W_0F3837_P_2,
1559   VEX_W_0F3838_P_2,
1560   VEX_W_0F3839_P_2,
1561   VEX_W_0F383A_P_2,
1562   VEX_W_0F383B_P_2,
1563   VEX_W_0F383C_P_2,
1564   VEX_W_0F383D_P_2,
1565   VEX_W_0F383E_P_2,
1566   VEX_W_0F383F_P_2,
1567   VEX_W_0F3840_P_2,
1568   VEX_W_0F3841_P_2,
1569   VEX_W_0F38DB_P_2,
1570   VEX_W_0F38DC_P_2,
1571   VEX_W_0F38DD_P_2,
1572   VEX_W_0F38DE_P_2,
1573   VEX_W_0F38DF_P_2,
1574   VEX_W_0F3A04_P_2,
1575   VEX_W_0F3A05_P_2,
1576   VEX_W_0F3A06_P_2,
1577   VEX_W_0F3A08_P_2,
1578   VEX_W_0F3A09_P_2,
1579   VEX_W_0F3A0A_P_2,
1580   VEX_W_0F3A0B_P_2,
1581   VEX_W_0F3A0C_P_2,
1582   VEX_W_0F3A0D_P_2,
1583   VEX_W_0F3A0E_P_2,
1584   VEX_W_0F3A0F_P_2,
1585   VEX_W_0F3A14_P_2,
1586   VEX_W_0F3A15_P_2,
1587   VEX_W_0F3A18_P_2,
1588   VEX_W_0F3A19_P_2,
1589   VEX_W_0F3A20_P_2,
1590   VEX_W_0F3A21_P_2,
1591   VEX_W_0F3A40_P_2,
1592   VEX_W_0F3A41_P_2,
1593   VEX_W_0F3A42_P_2,
1594   VEX_W_0F3A44_P_2,
1595   VEX_W_0F3A48_P_2,
1596   VEX_W_0F3A49_P_2,
1597   VEX_W_0F3A4A_P_2,
1598   VEX_W_0F3A4B_P_2,
1599   VEX_W_0F3A4C_P_2,
1600   VEX_W_0F3A60_P_2,
1601   VEX_W_0F3A61_P_2,
1602   VEX_W_0F3A62_P_2,
1603   VEX_W_0F3A63_P_2,
1604   VEX_W_0F3ADF_P_2
1605 };
1606
1607 typedef void (*op_rtn) (int bytemode, int sizeflag);
1608
1609 struct dis386 {
1610   const char *name;
1611   struct
1612     {
1613       op_rtn rtn;
1614       int bytemode;
1615     } op[MAX_OPERANDS];
1616 };
1617
1618 /* Upper case letters in the instruction names here are macros.
1619    'A' => print 'b' if no register operands or suffix_always is true
1620    'B' => print 'b' if suffix_always is true
1621    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1622           size prefix
1623    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1624           suffix_always is true
1625    'E' => print 'e' if 32-bit form of jcxz
1626    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1627    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1628    'H' => print ",pt" or ",pn" branch hint
1629    'I' => honor following macro letter even in Intel mode (implemented only
1630           for some of the macro letters)
1631    'J' => print 'l'
1632    'K' => print 'd' or 'q' if rex prefix is present.
1633    'L' => print 'l' if suffix_always is true
1634    'M' => print 'r' if intel_mnemonic is false.
1635    'N' => print 'n' if instruction has no wait "prefix"
1636    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1637    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1638           or suffix_always is true.  print 'q' if rex prefix is present.
1639    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1640           is true
1641    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1642    'S' => print 'w', 'l' or 'q' if suffix_always is true
1643    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1644    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1645    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1646    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1647    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1648    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1649           suffix_always is true.
1650    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1651    '!' => change condition from true to false or from false to true.
1652    '%' => add 1 upper case letter to the macro.
1653
1654    2 upper case letter macros:
1655    "XY" => print 'x' or 'y' if no register operands or suffix_always
1656            is true.
1657    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1658    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1659            or suffix_always is true
1660    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1661    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1662    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1663
1664    Many of the above letters print nothing in Intel mode.  See "putop"
1665    for the details.
1666
1667    Braces '{' and '}', and vertical bars '|', indicate alternative
1668    mnemonic strings for AT&T and Intel.  */
1669
1670 static const struct dis386 dis386[] = {
1671   /* 00 */
1672   { "addB",             { Eb, Gb } },
1673   { "addS",             { Ev, Gv } },
1674   { "addB",             { Gb, EbS } },
1675   { "addS",             { Gv, EvS } },
1676   { "addB",             { AL, Ib } },
1677   { "addS",             { eAX, Iv } },
1678   { X86_64_TABLE (X86_64_06) },
1679   { X86_64_TABLE (X86_64_07) },
1680   /* 08 */
1681   { "orB",              { Eb, Gb } },
1682   { "orS",              { Ev, Gv } },
1683   { "orB",              { Gb, EbS } },
1684   { "orS",              { Gv, EvS } },
1685   { "orB",              { AL, Ib } },
1686   { "orS",              { eAX, Iv } },
1687   { X86_64_TABLE (X86_64_0D) },
1688   { Bad_Opcode },       /* 0x0f extended opcode escape */
1689   /* 10 */
1690   { "adcB",             { Eb, Gb } },
1691   { "adcS",             { Ev, Gv } },
1692   { "adcB",             { Gb, EbS } },
1693   { "adcS",             { Gv, EvS } },
1694   { "adcB",             { AL, Ib } },
1695   { "adcS",             { eAX, Iv } },
1696   { X86_64_TABLE (X86_64_16) },
1697   { X86_64_TABLE (X86_64_17) },
1698   /* 18 */
1699   { "sbbB",             { Eb, Gb } },
1700   { "sbbS",             { Ev, Gv } },
1701   { "sbbB",             { Gb, EbS } },
1702   { "sbbS",             { Gv, EvS } },
1703   { "sbbB",             { AL, Ib } },
1704   { "sbbS",             { eAX, Iv } },
1705   { X86_64_TABLE (X86_64_1E) },
1706   { X86_64_TABLE (X86_64_1F) },
1707   /* 20 */
1708   { "andB",             { Eb, Gb } },
1709   { "andS",             { Ev, Gv } },
1710   { "andB",             { Gb, EbS } },
1711   { "andS",             { Gv, EvS } },
1712   { "andB",             { AL, Ib } },
1713   { "andS",             { eAX, Iv } },
1714   { Bad_Opcode },       /* SEG ES prefix */
1715   { X86_64_TABLE (X86_64_27) },
1716   /* 28 */
1717   { "subB",             { Eb, Gb } },
1718   { "subS",             { Ev, Gv } },
1719   { "subB",             { Gb, EbS } },
1720   { "subS",             { Gv, EvS } },
1721   { "subB",             { AL, Ib } },
1722   { "subS",             { eAX, Iv } },
1723   { Bad_Opcode },       /* SEG CS prefix */
1724   { X86_64_TABLE (X86_64_2F) },
1725   /* 30 */
1726   { "xorB",             { Eb, Gb } },
1727   { "xorS",             { Ev, Gv } },
1728   { "xorB",             { Gb, EbS } },
1729   { "xorS",             { Gv, EvS } },
1730   { "xorB",             { AL, Ib } },
1731   { "xorS",             { eAX, Iv } },
1732   { Bad_Opcode },       /* SEG SS prefix */
1733   { X86_64_TABLE (X86_64_37) },
1734   /* 38 */
1735   { "cmpB",             { Eb, Gb } },
1736   { "cmpS",             { Ev, Gv } },
1737   { "cmpB",             { Gb, EbS } },
1738   { "cmpS",             { Gv, EvS } },
1739   { "cmpB",             { AL, Ib } },
1740   { "cmpS",             { eAX, Iv } },
1741   { Bad_Opcode },       /* SEG DS prefix */
1742   { X86_64_TABLE (X86_64_3F) },
1743   /* 40 */
1744   { "inc{S|}",          { RMeAX } },
1745   { "inc{S|}",          { RMeCX } },
1746   { "inc{S|}",          { RMeDX } },
1747   { "inc{S|}",          { RMeBX } },
1748   { "inc{S|}",          { RMeSP } },
1749   { "inc{S|}",          { RMeBP } },
1750   { "inc{S|}",          { RMeSI } },
1751   { "inc{S|}",          { RMeDI } },
1752   /* 48 */
1753   { "dec{S|}",          { RMeAX } },
1754   { "dec{S|}",          { RMeCX } },
1755   { "dec{S|}",          { RMeDX } },
1756   { "dec{S|}",          { RMeBX } },
1757   { "dec{S|}",          { RMeSP } },
1758   { "dec{S|}",          { RMeBP } },
1759   { "dec{S|}",          { RMeSI } },
1760   { "dec{S|}",          { RMeDI } },
1761   /* 50 */
1762   { "pushV",            { RMrAX } },
1763   { "pushV",            { RMrCX } },
1764   { "pushV",            { RMrDX } },
1765   { "pushV",            { RMrBX } },
1766   { "pushV",            { RMrSP } },
1767   { "pushV",            { RMrBP } },
1768   { "pushV",            { RMrSI } },
1769   { "pushV",            { RMrDI } },
1770   /* 58 */
1771   { "popV",             { RMrAX } },
1772   { "popV",             { RMrCX } },
1773   { "popV",             { RMrDX } },
1774   { "popV",             { RMrBX } },
1775   { "popV",             { RMrSP } },
1776   { "popV",             { RMrBP } },
1777   { "popV",             { RMrSI } },
1778   { "popV",             { RMrDI } },
1779   /* 60 */
1780   { X86_64_TABLE (X86_64_60) },
1781   { X86_64_TABLE (X86_64_61) },
1782   { X86_64_TABLE (X86_64_62) },
1783   { X86_64_TABLE (X86_64_63) },
1784   { Bad_Opcode },       /* seg fs */
1785   { Bad_Opcode },       /* seg gs */
1786   { Bad_Opcode },       /* op size prefix */
1787   { Bad_Opcode },       /* adr size prefix */
1788   /* 68 */
1789   { "pushT",            { sIv } },
1790   { "imulS",            { Gv, Ev, Iv } },
1791   { "pushT",            { sIb } },
1792   { "imulS",            { Gv, Ev, sIb } },
1793   { "ins{b|}",          { Ybr, indirDX } },
1794   { X86_64_TABLE (X86_64_6D) },
1795   { "outs{b|}",         { indirDXr, Xb } },
1796   { X86_64_TABLE (X86_64_6F) },
1797   /* 70 */
1798   { "joH",              { Jb, XX, cond_jump_flag } },
1799   { "jnoH",             { Jb, XX, cond_jump_flag } },
1800   { "jbH",              { Jb, XX, cond_jump_flag } },
1801   { "jaeH",             { Jb, XX, cond_jump_flag } },
1802   { "jeH",              { Jb, XX, cond_jump_flag } },
1803   { "jneH",             { Jb, XX, cond_jump_flag } },
1804   { "jbeH",             { Jb, XX, cond_jump_flag } },
1805   { "jaH",              { Jb, XX, cond_jump_flag } },
1806   /* 78 */
1807   { "jsH",              { Jb, XX, cond_jump_flag } },
1808   { "jnsH",             { Jb, XX, cond_jump_flag } },
1809   { "jpH",              { Jb, XX, cond_jump_flag } },
1810   { "jnpH",             { Jb, XX, cond_jump_flag } },
1811   { "jlH",              { Jb, XX, cond_jump_flag } },
1812   { "jgeH",             { Jb, XX, cond_jump_flag } },
1813   { "jleH",             { Jb, XX, cond_jump_flag } },
1814   { "jgH",              { Jb, XX, cond_jump_flag } },
1815   /* 80 */
1816   { REG_TABLE (REG_80) },
1817   { REG_TABLE (REG_81) },
1818   { Bad_Opcode },
1819   { REG_TABLE (REG_82) },
1820   { "testB",            { Eb, Gb } },
1821   { "testS",            { Ev, Gv } },
1822   { "xchgB",            { Eb, Gb } },
1823   { "xchgS",            { Ev, Gv } },
1824   /* 88 */
1825   { "movB",             { Eb, Gb } },
1826   { "movS",             { Ev, Gv } },
1827   { "movB",             { Gb, EbS } },
1828   { "movS",             { Gv, EvS } },
1829   { "movD",             { Sv, Sw } },
1830   { MOD_TABLE (MOD_8D) },
1831   { "movD",             { Sw, Sv } },
1832   { REG_TABLE (REG_8F) },
1833   /* 90 */
1834   { PREFIX_TABLE (PREFIX_90) },
1835   { "xchgS",            { RMeCX, eAX } },
1836   { "xchgS",            { RMeDX, eAX } },
1837   { "xchgS",            { RMeBX, eAX } },
1838   { "xchgS",            { RMeSP, eAX } },
1839   { "xchgS",            { RMeBP, eAX } },
1840   { "xchgS",            { RMeSI, eAX } },
1841   { "xchgS",            { RMeDI, eAX } },
1842   /* 98 */
1843   { "cW{t|}R",          { XX } },
1844   { "cR{t|}O",          { XX } },
1845   { X86_64_TABLE (X86_64_9A) },
1846   { Bad_Opcode },       /* fwait */
1847   { "pushfT",           { XX } },
1848   { "popfT",            { XX } },
1849   { "sahf",             { XX } },
1850   { "lahf",             { XX } },
1851   /* a0 */
1852   { "mov%LB",           { AL, Ob } },
1853   { "mov%LS",           { eAX, Ov } },
1854   { "mov%LB",           { Ob, AL } },
1855   { "mov%LS",           { Ov, eAX } },
1856   { "movs{b|}",         { Ybr, Xb } },
1857   { "movs{R|}",         { Yvr, Xv } },
1858   { "cmps{b|}",         { Xb, Yb } },
1859   { "cmps{R|}",         { Xv, Yv } },
1860   /* a8 */
1861   { "testB",            { AL, Ib } },
1862   { "testS",            { eAX, Iv } },
1863   { "stosB",            { Ybr, AL } },
1864   { "stosS",            { Yvr, eAX } },
1865   { "lodsB",            { ALr, Xb } },
1866   { "lodsS",            { eAXr, Xv } },
1867   { "scasB",            { AL, Yb } },
1868   { "scasS",            { eAX, Yv } },
1869   /* b0 */
1870   { "movB",             { RMAL, Ib } },
1871   { "movB",             { RMCL, Ib } },
1872   { "movB",             { RMDL, Ib } },
1873   { "movB",             { RMBL, Ib } },
1874   { "movB",             { RMAH, Ib } },
1875   { "movB",             { RMCH, Ib } },
1876   { "movB",             { RMDH, Ib } },
1877   { "movB",             { RMBH, Ib } },
1878   /* b8 */
1879   { "mov%LV",           { RMeAX, Iv64 } },
1880   { "mov%LV",           { RMeCX, Iv64 } },
1881   { "mov%LV",           { RMeDX, Iv64 } },
1882   { "mov%LV",           { RMeBX, Iv64 } },
1883   { "mov%LV",           { RMeSP, Iv64 } },
1884   { "mov%LV",           { RMeBP, Iv64 } },
1885   { "mov%LV",           { RMeSI, Iv64 } },
1886   { "mov%LV",           { RMeDI, Iv64 } },
1887   /* c0 */
1888   { REG_TABLE (REG_C0) },
1889   { REG_TABLE (REG_C1) },
1890   { "retT",             { Iw } },
1891   { "retT",             { XX } },
1892   { X86_64_TABLE (X86_64_C4) },
1893   { X86_64_TABLE (X86_64_C5) },
1894   { REG_TABLE (REG_C6) },
1895   { REG_TABLE (REG_C7) },
1896   /* c8 */
1897   { "enterT",           { Iw, Ib } },
1898   { "leaveT",           { XX } },
1899   { "Jret{|f}P",        { Iw } },
1900   { "Jret{|f}P",        { XX } },
1901   { "int3",             { XX } },
1902   { "int",              { Ib } },
1903   { X86_64_TABLE (X86_64_CE) },
1904   { "iretP",            { XX } },
1905   /* d0 */
1906   { REG_TABLE (REG_D0) },
1907   { REG_TABLE (REG_D1) },
1908   { REG_TABLE (REG_D2) },
1909   { REG_TABLE (REG_D3) },
1910   { X86_64_TABLE (X86_64_D4) },
1911   { X86_64_TABLE (X86_64_D5) },
1912   { Bad_Opcode },
1913   { "xlat",             { DSBX } },
1914   /* d8 */
1915   { FLOAT },
1916   { FLOAT },
1917   { FLOAT },
1918   { FLOAT },
1919   { FLOAT },
1920   { FLOAT },
1921   { FLOAT },
1922   { FLOAT },
1923   /* e0 */
1924   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1925   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1926   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1927   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1928   { "inB",              { AL, Ib } },
1929   { "inG",              { zAX, Ib } },
1930   { "outB",             { Ib, AL } },
1931   { "outG",             { Ib, zAX } },
1932   /* e8 */
1933   { "callT",            { Jv } },
1934   { "jmpT",             { Jv } },
1935   { X86_64_TABLE (X86_64_EA) },
1936   { "jmp",              { Jb } },
1937   { "inB",              { AL, indirDX } },
1938   { "inG",              { zAX, indirDX } },
1939   { "outB",             { indirDX, AL } },
1940   { "outG",             { indirDX, zAX } },
1941   /* f0 */
1942   { Bad_Opcode },       /* lock prefix */
1943   { "icebp",            { XX } },
1944   { Bad_Opcode },       /* repne */
1945   { Bad_Opcode },       /* repz */
1946   { "hlt",              { XX } },
1947   { "cmc",              { XX } },
1948   { REG_TABLE (REG_F6) },
1949   { REG_TABLE (REG_F7) },
1950   /* f8 */
1951   { "clc",              { XX } },
1952   { "stc",              { XX } },
1953   { "cli",              { XX } },
1954   { "sti",              { XX } },
1955   { "cld",              { XX } },
1956   { "std",              { XX } },
1957   { REG_TABLE (REG_FE) },
1958   { REG_TABLE (REG_FF) },
1959 };
1960
1961 static const struct dis386 dis386_twobyte[] = {
1962   /* 00 */
1963   { REG_TABLE (REG_0F00 ) },
1964   { REG_TABLE (REG_0F01 ) },
1965   { "larS",             { Gv, Ew } },
1966   { "lslS",             { Gv, Ew } },
1967   { Bad_Opcode },
1968   { "syscall",          { XX } },
1969   { "clts",             { XX } },
1970   { "sysretP",          { XX } },
1971   /* 08 */
1972   { "invd",             { XX } },
1973   { "wbinvd",           { XX } },
1974   { Bad_Opcode },
1975   { "ud2",              { XX } },
1976   { Bad_Opcode },
1977   { REG_TABLE (REG_0F0D) },
1978   { "femms",            { XX } },
1979   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1980   /* 10 */
1981   { PREFIX_TABLE (PREFIX_0F10) },
1982   { PREFIX_TABLE (PREFIX_0F11) },
1983   { PREFIX_TABLE (PREFIX_0F12) },
1984   { MOD_TABLE (MOD_0F13) },
1985   { "unpcklpX",         { XM, EXx } },
1986   { "unpckhpX",         { XM, EXx } },
1987   { PREFIX_TABLE (PREFIX_0F16) },
1988   { MOD_TABLE (MOD_0F17) },
1989   /* 18 */
1990   { REG_TABLE (REG_0F18) },
1991   { "nopQ",             { Ev } },
1992   { "nopQ",             { Ev } },
1993   { "nopQ",             { Ev } },
1994   { "nopQ",             { Ev } },
1995   { "nopQ",             { Ev } },
1996   { "nopQ",             { Ev } },
1997   { "nopQ",             { Ev } },
1998   /* 20 */
1999   { MOD_TABLE (MOD_0F20) },
2000   { MOD_TABLE (MOD_0F21) },
2001   { MOD_TABLE (MOD_0F22) },
2002   { MOD_TABLE (MOD_0F23) },
2003   { MOD_TABLE (MOD_0F24) },
2004   { Bad_Opcode },
2005   { MOD_TABLE (MOD_0F26) },
2006   { Bad_Opcode },
2007   /* 28 */
2008   { "movapX",           { XM, EXx } },
2009   { "movapX",           { EXxS, XM } },
2010   { PREFIX_TABLE (PREFIX_0F2A) },
2011   { PREFIX_TABLE (PREFIX_0F2B) },
2012   { PREFIX_TABLE (PREFIX_0F2C) },
2013   { PREFIX_TABLE (PREFIX_0F2D) },
2014   { PREFIX_TABLE (PREFIX_0F2E) },
2015   { PREFIX_TABLE (PREFIX_0F2F) },
2016   /* 30 */
2017   { "wrmsr",            { XX } },
2018   { "rdtsc",            { XX } },
2019   { "rdmsr",            { XX } },
2020   { "rdpmc",            { XX } },
2021   { "sysenter",         { XX } },
2022   { "sysexit",          { XX } },
2023   { Bad_Opcode },
2024   { "getsec",           { XX } },
2025   /* 38 */
2026   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2027   { Bad_Opcode },
2028   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2029   { Bad_Opcode },
2030   { Bad_Opcode },
2031   { Bad_Opcode },
2032   { Bad_Opcode },
2033   { Bad_Opcode },
2034   /* 40 */
2035   { "cmovoS",           { Gv, Ev } },
2036   { "cmovnoS",          { Gv, Ev } },
2037   { "cmovbS",           { Gv, Ev } },
2038   { "cmovaeS",          { Gv, Ev } },
2039   { "cmoveS",           { Gv, Ev } },
2040   { "cmovneS",          { Gv, Ev } },
2041   { "cmovbeS",          { Gv, Ev } },
2042   { "cmovaS",           { Gv, Ev } },
2043   /* 48 */
2044   { "cmovsS",           { Gv, Ev } },
2045   { "cmovnsS",          { Gv, Ev } },
2046   { "cmovpS",           { Gv, Ev } },
2047   { "cmovnpS",          { Gv, Ev } },
2048   { "cmovlS",           { Gv, Ev } },
2049   { "cmovgeS",          { Gv, Ev } },
2050   { "cmovleS",          { Gv, Ev } },
2051   { "cmovgS",           { Gv, Ev } },
2052   /* 50 */
2053   { MOD_TABLE (MOD_0F51) },
2054   { PREFIX_TABLE (PREFIX_0F51) },
2055   { PREFIX_TABLE (PREFIX_0F52) },
2056   { PREFIX_TABLE (PREFIX_0F53) },
2057   { "andpX",            { XM, EXx } },
2058   { "andnpX",           { XM, EXx } },
2059   { "orpX",             { XM, EXx } },
2060   { "xorpX",            { XM, EXx } },
2061   /* 58 */
2062   { PREFIX_TABLE (PREFIX_0F58) },
2063   { PREFIX_TABLE (PREFIX_0F59) },
2064   { PREFIX_TABLE (PREFIX_0F5A) },
2065   { PREFIX_TABLE (PREFIX_0F5B) },
2066   { PREFIX_TABLE (PREFIX_0F5C) },
2067   { PREFIX_TABLE (PREFIX_0F5D) },
2068   { PREFIX_TABLE (PREFIX_0F5E) },
2069   { PREFIX_TABLE (PREFIX_0F5F) },
2070   /* 60 */
2071   { PREFIX_TABLE (PREFIX_0F60) },
2072   { PREFIX_TABLE (PREFIX_0F61) },
2073   { PREFIX_TABLE (PREFIX_0F62) },
2074   { "packsswb",         { MX, EM } },
2075   { "pcmpgtb",          { MX, EM } },
2076   { "pcmpgtw",          { MX, EM } },
2077   { "pcmpgtd",          { MX, EM } },
2078   { "packuswb",         { MX, EM } },
2079   /* 68 */
2080   { "punpckhbw",        { MX, EM } },
2081   { "punpckhwd",        { MX, EM } },
2082   { "punpckhdq",        { MX, EM } },
2083   { "packssdw",         { MX, EM } },
2084   { PREFIX_TABLE (PREFIX_0F6C) },
2085   { PREFIX_TABLE (PREFIX_0F6D) },
2086   { "movK",             { MX, Edq } },
2087   { PREFIX_TABLE (PREFIX_0F6F) },
2088   /* 70 */
2089   { PREFIX_TABLE (PREFIX_0F70) },
2090   { REG_TABLE (REG_0F71) },
2091   { REG_TABLE (REG_0F72) },
2092   { REG_TABLE (REG_0F73) },
2093   { "pcmpeqb",          { MX, EM } },
2094   { "pcmpeqw",          { MX, EM } },
2095   { "pcmpeqd",          { MX, EM } },
2096   { "emms",             { XX } },
2097   /* 78 */
2098   { PREFIX_TABLE (PREFIX_0F78) },
2099   { PREFIX_TABLE (PREFIX_0F79) },
2100   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2101   { Bad_Opcode },
2102   { PREFIX_TABLE (PREFIX_0F7C) },
2103   { PREFIX_TABLE (PREFIX_0F7D) },
2104   { PREFIX_TABLE (PREFIX_0F7E) },
2105   { PREFIX_TABLE (PREFIX_0F7F) },
2106   /* 80 */
2107   { "joH",              { Jv, XX, cond_jump_flag } },
2108   { "jnoH",             { Jv, XX, cond_jump_flag } },
2109   { "jbH",              { Jv, XX, cond_jump_flag } },
2110   { "jaeH",             { Jv, XX, cond_jump_flag } },
2111   { "jeH",              { Jv, XX, cond_jump_flag } },
2112   { "jneH",             { Jv, XX, cond_jump_flag } },
2113   { "jbeH",             { Jv, XX, cond_jump_flag } },
2114   { "jaH",              { Jv, XX, cond_jump_flag } },
2115   /* 88 */
2116   { "jsH",              { Jv, XX, cond_jump_flag } },
2117   { "jnsH",             { Jv, XX, cond_jump_flag } },
2118   { "jpH",              { Jv, XX, cond_jump_flag } },
2119   { "jnpH",             { Jv, XX, cond_jump_flag } },
2120   { "jlH",              { Jv, XX, cond_jump_flag } },
2121   { "jgeH",             { Jv, XX, cond_jump_flag } },
2122   { "jleH",             { Jv, XX, cond_jump_flag } },
2123   { "jgH",              { Jv, XX, cond_jump_flag } },
2124   /* 90 */
2125   { "seto",             { Eb } },
2126   { "setno",            { Eb } },
2127   { "setb",             { Eb } },
2128   { "setae",            { Eb } },
2129   { "sete",             { Eb } },
2130   { "setne",            { Eb } },
2131   { "setbe",            { Eb } },
2132   { "seta",             { Eb } },
2133   /* 98 */
2134   { "sets",             { Eb } },
2135   { "setns",            { Eb } },
2136   { "setp",             { Eb } },
2137   { "setnp",            { Eb } },
2138   { "setl",             { Eb } },
2139   { "setge",            { Eb } },
2140   { "setle",            { Eb } },
2141   { "setg",             { Eb } },
2142   /* a0 */
2143   { "pushT",            { fs } },
2144   { "popT",             { fs } },
2145   { "cpuid",            { XX } },
2146   { "btS",              { Ev, Gv } },
2147   { "shldS",            { Ev, Gv, Ib } },
2148   { "shldS",            { Ev, Gv, CL } },
2149   { REG_TABLE (REG_0FA6) },
2150   { REG_TABLE (REG_0FA7) },
2151   /* a8 */
2152   { "pushT",            { gs } },
2153   { "popT",             { gs } },
2154   { "rsm",              { XX } },
2155   { "btsS",             { Ev, Gv } },
2156   { "shrdS",            { Ev, Gv, Ib } },
2157   { "shrdS",            { Ev, Gv, CL } },
2158   { REG_TABLE (REG_0FAE) },
2159   { "imulS",            { Gv, Ev } },
2160   /* b0 */
2161   { "cmpxchgB",         { Eb, Gb } },
2162   { "cmpxchgS",         { Ev, Gv } },
2163   { MOD_TABLE (MOD_0FB2) },
2164   { "btrS",             { Ev, Gv } },
2165   { MOD_TABLE (MOD_0FB4) },
2166   { MOD_TABLE (MOD_0FB5) },
2167   { "movz{bR|x}",       { Gv, Eb } },
2168   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2169   /* b8 */
2170   { PREFIX_TABLE (PREFIX_0FB8) },
2171   { "ud1",              { XX } },
2172   { REG_TABLE (REG_0FBA) },
2173   { "btcS",             { Ev, Gv } },
2174   { PREFIX_TABLE (PREFIX_0FBC) },
2175   { PREFIX_TABLE (PREFIX_0FBD) },
2176   { "movs{bR|x}",       { Gv, Eb } },
2177   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2178   /* c0 */
2179   { "xaddB",            { Eb, Gb } },
2180   { "xaddS",            { Ev, Gv } },
2181   { PREFIX_TABLE (PREFIX_0FC2) },
2182   { PREFIX_TABLE (PREFIX_0FC3) },
2183   { "pinsrw",           { MX, Edqw, Ib } },
2184   { "pextrw",           { Gdq, MS, Ib } },
2185   { "shufpX",           { XM, EXx, Ib } },
2186   { REG_TABLE (REG_0FC7) },
2187   /* c8 */
2188   { "bswap",            { RMeAX } },
2189   { "bswap",            { RMeCX } },
2190   { "bswap",            { RMeDX } },
2191   { "bswap",            { RMeBX } },
2192   { "bswap",            { RMeSP } },
2193   { "bswap",            { RMeBP } },
2194   { "bswap",            { RMeSI } },
2195   { "bswap",            { RMeDI } },
2196   /* d0 */
2197   { PREFIX_TABLE (PREFIX_0FD0) },
2198   { "psrlw",            { MX, EM } },
2199   { "psrld",            { MX, EM } },
2200   { "psrlq",            { MX, EM } },
2201   { "paddq",            { MX, EM } },
2202   { "pmullw",           { MX, EM } },
2203   { PREFIX_TABLE (PREFIX_0FD6) },
2204   { MOD_TABLE (MOD_0FD7) },
2205   /* d8 */
2206   { "psubusb",          { MX, EM } },
2207   { "psubusw",          { MX, EM } },
2208   { "pminub",           { MX, EM } },
2209   { "pand",             { MX, EM } },
2210   { "paddusb",          { MX, EM } },
2211   { "paddusw",          { MX, EM } },
2212   { "pmaxub",           { MX, EM } },
2213   { "pandn",            { MX, EM } },
2214   /* e0 */
2215   { "pavgb",            { MX, EM } },
2216   { "psraw",            { MX, EM } },
2217   { "psrad",            { MX, EM } },
2218   { "pavgw",            { MX, EM } },
2219   { "pmulhuw",          { MX, EM } },
2220   { "pmulhw",           { MX, EM } },
2221   { PREFIX_TABLE (PREFIX_0FE6) },
2222   { PREFIX_TABLE (PREFIX_0FE7) },
2223   /* e8 */
2224   { "psubsb",           { MX, EM } },
2225   { "psubsw",           { MX, EM } },
2226   { "pminsw",           { MX, EM } },
2227   { "por",              { MX, EM } },
2228   { "paddsb",           { MX, EM } },
2229   { "paddsw",           { MX, EM } },
2230   { "pmaxsw",           { MX, EM } },
2231   { "pxor",             { MX, EM } },
2232   /* f0 */
2233   { PREFIX_TABLE (PREFIX_0FF0) },
2234   { "psllw",            { MX, EM } },
2235   { "pslld",            { MX, EM } },
2236   { "psllq",            { MX, EM } },
2237   { "pmuludq",          { MX, EM } },
2238   { "pmaddwd",          { MX, EM } },
2239   { "psadbw",           { MX, EM } },
2240   { PREFIX_TABLE (PREFIX_0FF7) },
2241   /* f8 */
2242   { "psubb",            { MX, EM } },
2243   { "psubw",            { MX, EM } },
2244   { "psubd",            { MX, EM } },
2245   { "psubq",            { MX, EM } },
2246   { "paddb",            { MX, EM } },
2247   { "paddw",            { MX, EM } },
2248   { "paddd",            { MX, EM } },
2249   { Bad_Opcode },
2250 };
2251
2252 static const unsigned char onebyte_has_modrm[256] = {
2253   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2254   /*       -------------------------------        */
2255   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2256   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2257   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2258   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2259   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2260   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2261   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2262   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2263   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2264   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2265   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2266   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2267   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2268   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2269   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2270   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2271   /*       -------------------------------        */
2272   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2273 };
2274
2275 static const unsigned char twobyte_has_modrm[256] = {
2276   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2277   /*       -------------------------------        */
2278   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2279   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2280   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2281   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2282   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2283   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2284   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2285   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2286   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2287   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2288   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2289   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2290   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2291   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2292   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2293   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2294   /*       -------------------------------        */
2295   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2296 };
2297
2298 static char obuf[100];
2299 static char *obufp;
2300 static char *mnemonicendp;
2301 static char scratchbuf[100];
2302 static unsigned char *start_codep;
2303 static unsigned char *insn_codep;
2304 static unsigned char *codep;
2305 static int last_lock_prefix;
2306 static int last_repz_prefix;
2307 static int last_repnz_prefix;
2308 static int last_data_prefix;
2309 static int last_addr_prefix;
2310 static int last_rex_prefix;
2311 static int last_seg_prefix;
2312 #define MAX_CODE_LENGTH 15
2313 /* We can up to 14 prefixes since the maximum instruction length is
2314    15bytes.  */
2315 static int all_prefixes[MAX_CODE_LENGTH - 1];
2316 static disassemble_info *the_info;
2317 static struct
2318   {
2319     int mod;
2320     int reg;
2321     int rm;
2322   }
2323 modrm;
2324 static unsigned char need_modrm;
2325 static struct
2326   {
2327     int scale;
2328     int index;
2329     int base;
2330   }
2331 sib;
2332 static struct
2333   {
2334     int register_specifier;
2335     int length;
2336     int prefix;
2337     int w;
2338   }
2339 vex;
2340 static unsigned char need_vex;
2341 static unsigned char need_vex_reg;
2342 static unsigned char vex_w_done;
2343
2344 struct op
2345   {
2346     const char *name;
2347     unsigned int len;
2348   };
2349
2350 /* If we are accessing mod/rm/reg without need_modrm set, then the
2351    values are stale.  Hitting this abort likely indicates that you
2352    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2353 #define MODRM_CHECK  if (!need_modrm) abort ()
2354
2355 static const char **names64;
2356 static const char **names32;
2357 static const char **names16;
2358 static const char **names8;
2359 static const char **names8rex;
2360 static const char **names_seg;
2361 static const char *index64;
2362 static const char *index32;
2363 static const char **index16;
2364
2365 static const char *intel_names64[] = {
2366   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2367   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2368 };
2369 static const char *intel_names32[] = {
2370   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2371   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2372 };
2373 static const char *intel_names16[] = {
2374   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2375   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2376 };
2377 static const char *intel_names8[] = {
2378   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2379 };
2380 static const char *intel_names8rex[] = {
2381   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2382   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2383 };
2384 static const char *intel_names_seg[] = {
2385   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2386 };
2387 static const char *intel_index64 = "riz";
2388 static const char *intel_index32 = "eiz";
2389 static const char *intel_index16[] = {
2390   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2391 };
2392
2393 static const char *att_names64[] = {
2394   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2395   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2396 };
2397 static const char *att_names32[] = {
2398   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2399   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2400 };
2401 static const char *att_names16[] = {
2402   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2403   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2404 };
2405 static const char *att_names8[] = {
2406   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2407 };
2408 static const char *att_names8rex[] = {
2409   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2410   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2411 };
2412 static const char *att_names_seg[] = {
2413   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2414 };
2415 static const char *att_index64 = "%riz";
2416 static const char *att_index32 = "%eiz";
2417 static const char *att_index16[] = {
2418   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2419 };
2420
2421 static const char **names_mm;
2422 static const char *intel_names_mm[] = {
2423   "mm0", "mm1", "mm2", "mm3",
2424   "mm4", "mm5", "mm6", "mm7"
2425 };
2426 static const char *att_names_mm[] = {
2427   "%mm0", "%mm1", "%mm2", "%mm3",
2428   "%mm4", "%mm5", "%mm6", "%mm7"
2429 };
2430
2431 static const char **names_xmm;
2432 static const char *intel_names_xmm[] = {
2433   "xmm0", "xmm1", "xmm2", "xmm3",
2434   "xmm4", "xmm5", "xmm6", "xmm7",
2435   "xmm8", "xmm9", "xmm10", "xmm11",
2436   "xmm12", "xmm13", "xmm14", "xmm15"
2437 };
2438 static const char *att_names_xmm[] = {
2439   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2440   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2441   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2442   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2443 };
2444
2445 static const char **names_ymm;
2446 static const char *intel_names_ymm[] = {
2447   "ymm0", "ymm1", "ymm2", "ymm3",
2448   "ymm4", "ymm5", "ymm6", "ymm7",
2449   "ymm8", "ymm9", "ymm10", "ymm11",
2450   "ymm12", "ymm13", "ymm14", "ymm15"
2451 };
2452 static const char *att_names_ymm[] = {
2453   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2454   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2455   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2456   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2457 };
2458
2459 static const struct dis386 reg_table[][8] = {
2460   /* REG_80 */
2461   {
2462     { "addA",   { Eb, Ib } },
2463     { "orA",    { Eb, Ib } },
2464     { "adcA",   { Eb, Ib } },
2465     { "sbbA",   { Eb, Ib } },
2466     { "andA",   { Eb, Ib } },
2467     { "subA",   { Eb, Ib } },
2468     { "xorA",   { Eb, Ib } },
2469     { "cmpA",   { Eb, Ib } },
2470   },
2471   /* REG_81 */
2472   {
2473     { "addQ",   { Ev, Iv } },
2474     { "orQ",    { Ev, Iv } },
2475     { "adcQ",   { Ev, Iv } },
2476     { "sbbQ",   { Ev, Iv } },
2477     { "andQ",   { Ev, Iv } },
2478     { "subQ",   { Ev, Iv } },
2479     { "xorQ",   { Ev, Iv } },
2480     { "cmpQ",   { Ev, Iv } },
2481   },
2482   /* REG_82 */
2483   {
2484     { "addQ",   { Ev, sIb } },
2485     { "orQ",    { Ev, sIb } },
2486     { "adcQ",   { Ev, sIb } },
2487     { "sbbQ",   { Ev, sIb } },
2488     { "andQ",   { Ev, sIb } },
2489     { "subQ",   { Ev, sIb } },
2490     { "xorQ",   { Ev, sIb } },
2491     { "cmpQ",   { Ev, sIb } },
2492   },
2493   /* REG_8F */
2494   {
2495     { "popU",   { stackEv } },
2496     { XOP_8F_TABLE (XOP_09) },
2497     { Bad_Opcode },
2498     { Bad_Opcode },
2499     { Bad_Opcode },
2500     { XOP_8F_TABLE (XOP_09) },
2501   },
2502   /* REG_C0 */
2503   {
2504     { "rolA",   { Eb, Ib } },
2505     { "rorA",   { Eb, Ib } },
2506     { "rclA",   { Eb, Ib } },
2507     { "rcrA",   { Eb, Ib } },
2508     { "shlA",   { Eb, Ib } },
2509     { "shrA",   { Eb, Ib } },
2510     { Bad_Opcode },
2511     { "sarA",   { Eb, Ib } },
2512   },
2513   /* REG_C1 */
2514   {
2515     { "rolQ",   { Ev, Ib } },
2516     { "rorQ",   { Ev, Ib } },
2517     { "rclQ",   { Ev, Ib } },
2518     { "rcrQ",   { Ev, Ib } },
2519     { "shlQ",   { Ev, Ib } },
2520     { "shrQ",   { Ev, Ib } },
2521     { Bad_Opcode },
2522     { "sarQ",   { Ev, Ib } },
2523   },
2524   /* REG_C6 */
2525   {
2526     { "movA",   { Eb, Ib } },
2527   },
2528   /* REG_C7 */
2529   {
2530     { "movQ",   { Ev, Iv } },
2531   },
2532   /* REG_D0 */
2533   {
2534     { "rolA",   { Eb, I1 } },
2535     { "rorA",   { Eb, I1 } },
2536     { "rclA",   { Eb, I1 } },
2537     { "rcrA",   { Eb, I1 } },
2538     { "shlA",   { Eb, I1 } },
2539     { "shrA",   { Eb, I1 } },
2540     { Bad_Opcode },
2541     { "sarA",   { Eb, I1 } },
2542   },
2543   /* REG_D1 */
2544   {
2545     { "rolQ",   { Ev, I1 } },
2546     { "rorQ",   { Ev, I1 } },
2547     { "rclQ",   { Ev, I1 } },
2548     { "rcrQ",   { Ev, I1 } },
2549     { "shlQ",   { Ev, I1 } },
2550     { "shrQ",   { Ev, I1 } },
2551     { Bad_Opcode },
2552     { "sarQ",   { Ev, I1 } },
2553   },
2554   /* REG_D2 */
2555   {
2556     { "rolA",   { Eb, CL } },
2557     { "rorA",   { Eb, CL } },
2558     { "rclA",   { Eb, CL } },
2559     { "rcrA",   { Eb, CL } },
2560     { "shlA",   { Eb, CL } },
2561     { "shrA",   { Eb, CL } },
2562     { Bad_Opcode },
2563     { "sarA",   { Eb, CL } },
2564   },
2565   /* REG_D3 */
2566   {
2567     { "rolQ",   { Ev, CL } },
2568     { "rorQ",   { Ev, CL } },
2569     { "rclQ",   { Ev, CL } },
2570     { "rcrQ",   { Ev, CL } },
2571     { "shlQ",   { Ev, CL } },
2572     { "shrQ",   { Ev, CL } },
2573     { Bad_Opcode },
2574     { "sarQ",   { Ev, CL } },
2575   },
2576   /* REG_F6 */
2577   {
2578     { "testA",  { Eb, Ib } },
2579     { Bad_Opcode },
2580     { "notA",   { Eb } },
2581     { "negA",   { Eb } },
2582     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2583     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2584     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2585     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2586   },
2587   /* REG_F7 */
2588   {
2589     { "testQ",  { Ev, Iv } },
2590     { Bad_Opcode },
2591     { "notQ",   { Ev } },
2592     { "negQ",   { Ev } },
2593     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2594     { "imulQ",  { Ev } },
2595     { "divQ",   { Ev } },
2596     { "idivQ",  { Ev } },
2597   },
2598   /* REG_FE */
2599   {
2600     { "incA",   { Eb } },
2601     { "decA",   { Eb } },
2602   },
2603   /* REG_FF */
2604   {
2605     { "incQ",   { Ev } },
2606     { "decQ",   { Ev } },
2607     { "call{T|}", { indirEv } },
2608     { "Jcall{T|}", { indirEp } },
2609     { "jmp{T|}", { indirEv } },
2610     { "Jjmp{T|}", { indirEp } },
2611     { "pushU",  { stackEv } },
2612     { Bad_Opcode },
2613   },
2614   /* REG_0F00 */
2615   {
2616     { "sldtD",  { Sv } },
2617     { "strD",   { Sv } },
2618     { "lldt",   { Ew } },
2619     { "ltr",    { Ew } },
2620     { "verr",   { Ew } },
2621     { "verw",   { Ew } },
2622     { Bad_Opcode },
2623     { Bad_Opcode },
2624   },
2625   /* REG_0F01 */
2626   {
2627     { MOD_TABLE (MOD_0F01_REG_0) },
2628     { MOD_TABLE (MOD_0F01_REG_1) },
2629     { MOD_TABLE (MOD_0F01_REG_2) },
2630     { MOD_TABLE (MOD_0F01_REG_3) },
2631     { "smswD",  { Sv } },
2632     { Bad_Opcode },
2633     { "lmsw",   { Ew } },
2634     { MOD_TABLE (MOD_0F01_REG_7) },
2635   },
2636   /* REG_0F0D */
2637   {
2638     { "prefetch",       { Mb } },
2639     { "prefetchw",      { Mb } },
2640   },
2641   /* REG_0F18 */
2642   {
2643     { MOD_TABLE (MOD_0F18_REG_0) },
2644     { MOD_TABLE (MOD_0F18_REG_1) },
2645     { MOD_TABLE (MOD_0F18_REG_2) },
2646     { MOD_TABLE (MOD_0F18_REG_3) },
2647   },
2648   /* REG_0F71 */
2649   {
2650     { Bad_Opcode },
2651     { Bad_Opcode },
2652     { MOD_TABLE (MOD_0F71_REG_2) },
2653     { Bad_Opcode },
2654     { MOD_TABLE (MOD_0F71_REG_4) },
2655     { Bad_Opcode },
2656     { MOD_TABLE (MOD_0F71_REG_6) },
2657   },
2658   /* REG_0F72 */
2659   {
2660     { Bad_Opcode },
2661     { Bad_Opcode },
2662     { MOD_TABLE (MOD_0F72_REG_2) },
2663     { Bad_Opcode },
2664     { MOD_TABLE (MOD_0F72_REG_4) },
2665     { Bad_Opcode },
2666     { MOD_TABLE (MOD_0F72_REG_6) },
2667   },
2668   /* REG_0F73 */
2669   {
2670     { Bad_Opcode },
2671     { Bad_Opcode },
2672     { MOD_TABLE (MOD_0F73_REG_2) },
2673     { MOD_TABLE (MOD_0F73_REG_3) },
2674     { Bad_Opcode },
2675     { Bad_Opcode },
2676     { MOD_TABLE (MOD_0F73_REG_6) },
2677     { MOD_TABLE (MOD_0F73_REG_7) },
2678   },
2679   /* REG_0FA6 */
2680   {
2681     { "montmul",        { { OP_0f07, 0 } } },
2682     { "xsha1",          { { OP_0f07, 0 } } },
2683     { "xsha256",        { { OP_0f07, 0 } } },
2684   },
2685   /* REG_0FA7 */
2686   {
2687     { "xstore-rng",     { { OP_0f07, 0 } } },
2688     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2689     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2690     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2691     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2692     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2693   },
2694   /* REG_0FAE */
2695   {
2696     { MOD_TABLE (MOD_0FAE_REG_0) },
2697     { MOD_TABLE (MOD_0FAE_REG_1) },
2698     { MOD_TABLE (MOD_0FAE_REG_2) },
2699     { MOD_TABLE (MOD_0FAE_REG_3) },
2700     { MOD_TABLE (MOD_0FAE_REG_4) },
2701     { MOD_TABLE (MOD_0FAE_REG_5) },
2702     { MOD_TABLE (MOD_0FAE_REG_6) },
2703     { MOD_TABLE (MOD_0FAE_REG_7) },
2704   },
2705   /* REG_0FBA */
2706   {
2707     { Bad_Opcode },
2708     { Bad_Opcode },
2709     { Bad_Opcode },
2710     { Bad_Opcode },
2711     { "btQ",    { Ev, Ib } },
2712     { "btsQ",   { Ev, Ib } },
2713     { "btrQ",   { Ev, Ib } },
2714     { "btcQ",   { Ev, Ib } },
2715   },
2716   /* REG_0FC7 */
2717   {
2718     { Bad_Opcode },
2719     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2720     { Bad_Opcode },
2721     { Bad_Opcode },
2722     { Bad_Opcode },
2723     { Bad_Opcode },
2724     { MOD_TABLE (MOD_0FC7_REG_6) },
2725     { MOD_TABLE (MOD_0FC7_REG_7) },
2726   },
2727   /* REG_VEX_0F71 */
2728   {
2729     { Bad_Opcode },
2730     { Bad_Opcode },
2731     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2732     { Bad_Opcode },
2733     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2734     { Bad_Opcode },
2735     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2736   },
2737   /* REG_VEX_0F72 */
2738   {
2739     { Bad_Opcode },
2740     { Bad_Opcode },
2741     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2742     { Bad_Opcode },
2743     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2744     { Bad_Opcode },
2745     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2746   },
2747   /* REG_VEX_0F73 */
2748   {
2749     { Bad_Opcode },
2750     { Bad_Opcode },
2751     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2752     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2753     { Bad_Opcode },
2754     { Bad_Opcode },
2755     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2756     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2757   },
2758   /* REG_VEX_0FAE */
2759   {
2760     { Bad_Opcode },
2761     { Bad_Opcode },
2762     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2763     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2764   },
2765   /* REG_VEX_0F38F3 */
2766   {
2767     { Bad_Opcode },
2768     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2769     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2770     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2771   },
2772   /* REG_XOP_LWPCB */
2773   {
2774     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2775     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2776   },
2777   /* REG_XOP_LWP */
2778   {
2779     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2780     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2781   },
2782 };
2783
2784 static const struct dis386 prefix_table[][4] = {
2785   /* PREFIX_90 */
2786   {
2787     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2788     { "pause", { XX } },
2789     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2790   },
2791
2792   /* PREFIX_0F10 */
2793   {
2794     { "movups", { XM, EXx } },
2795     { "movss",  { XM, EXd } },
2796     { "movupd", { XM, EXx } },
2797     { "movsd",  { XM, EXq } },
2798   },
2799
2800   /* PREFIX_0F11 */
2801   {
2802     { "movups", { EXxS, XM } },
2803     { "movss",  { EXdS, XM } },
2804     { "movupd", { EXxS, XM } },
2805     { "movsd",  { EXqS, XM } },
2806   },
2807
2808   /* PREFIX_0F12 */
2809   {
2810     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2811     { "movsldup", { XM, EXx } },
2812     { "movlpd", { XM, EXq } },
2813     { "movddup", { XM, EXq } },
2814   },
2815
2816   /* PREFIX_0F16 */
2817   {
2818     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2819     { "movshdup", { XM, EXx } },
2820     { "movhpd", { XM, EXq } },
2821   },
2822
2823   /* PREFIX_0F2A */
2824   {
2825     { "cvtpi2ps", { XM, EMCq } },
2826     { "cvtsi2ss%LQ", { XM, Ev } },
2827     { "cvtpi2pd", { XM, EMCq } },
2828     { "cvtsi2sd%LQ", { XM, Ev } },
2829   },
2830
2831   /* PREFIX_0F2B */
2832   {
2833     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2834     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2835     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2836     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2837   },
2838
2839   /* PREFIX_0F2C */
2840   {
2841     { "cvttps2pi", { MXC, EXq } },
2842     { "cvttss2siY", { Gv, EXd } },
2843     { "cvttpd2pi", { MXC, EXx } },
2844     { "cvttsd2siY", { Gv, EXq } },
2845   },
2846
2847   /* PREFIX_0F2D */
2848   {
2849     { "cvtps2pi", { MXC, EXq } },
2850     { "cvtss2siY", { Gv, EXd } },
2851     { "cvtpd2pi", { MXC, EXx } },
2852     { "cvtsd2siY", { Gv, EXq } },
2853   },
2854
2855   /* PREFIX_0F2E */
2856   {
2857     { "ucomiss",{ XM, EXd } },
2858     { Bad_Opcode },
2859     { "ucomisd",{ XM, EXq } },
2860   },
2861
2862   /* PREFIX_0F2F */
2863   {
2864     { "comiss", { XM, EXd } },
2865     { Bad_Opcode },
2866     { "comisd", { XM, EXq } },
2867   },
2868
2869   /* PREFIX_0F51 */
2870   {
2871     { "sqrtps", { XM, EXx } },
2872     { "sqrtss", { XM, EXd } },
2873     { "sqrtpd", { XM, EXx } },
2874     { "sqrtsd", { XM, EXq } },
2875   },
2876
2877   /* PREFIX_0F52 */
2878   {
2879     { "rsqrtps",{ XM, EXx } },
2880     { "rsqrtss",{ XM, EXd } },
2881   },
2882
2883   /* PREFIX_0F53 */
2884   {
2885     { "rcpps",  { XM, EXx } },
2886     { "rcpss",  { XM, EXd } },
2887   },
2888
2889   /* PREFIX_0F58 */
2890   {
2891     { "addps", { XM, EXx } },
2892     { "addss", { XM, EXd } },
2893     { "addpd", { XM, EXx } },
2894     { "addsd", { XM, EXq } },
2895   },
2896
2897   /* PREFIX_0F59 */
2898   {
2899     { "mulps",  { XM, EXx } },
2900     { "mulss",  { XM, EXd } },
2901     { "mulpd",  { XM, EXx } },
2902     { "mulsd",  { XM, EXq } },
2903   },
2904
2905   /* PREFIX_0F5A */
2906   {
2907     { "cvtps2pd", { XM, EXq } },
2908     { "cvtss2sd", { XM, EXd } },
2909     { "cvtpd2ps", { XM, EXx } },
2910     { "cvtsd2ss", { XM, EXq } },
2911   },
2912
2913   /* PREFIX_0F5B */
2914   {
2915     { "cvtdq2ps", { XM, EXx } },
2916     { "cvttps2dq", { XM, EXx } },
2917     { "cvtps2dq", { XM, EXx } },
2918   },
2919
2920   /* PREFIX_0F5C */
2921   {
2922     { "subps",  { XM, EXx } },
2923     { "subss",  { XM, EXd } },
2924     { "subpd",  { XM, EXx } },
2925     { "subsd",  { XM, EXq } },
2926   },
2927
2928   /* PREFIX_0F5D */
2929   {
2930     { "minps",  { XM, EXx } },
2931     { "minss",  { XM, EXd } },
2932     { "minpd",  { XM, EXx } },
2933     { "minsd",  { XM, EXq } },
2934   },
2935
2936   /* PREFIX_0F5E */
2937   {
2938     { "divps",  { XM, EXx } },
2939     { "divss",  { XM, EXd } },
2940     { "divpd",  { XM, EXx } },
2941     { "divsd",  { XM, EXq } },
2942   },
2943
2944   /* PREFIX_0F5F */
2945   {
2946     { "maxps",  { XM, EXx } },
2947     { "maxss",  { XM, EXd } },
2948     { "maxpd",  { XM, EXx } },
2949     { "maxsd",  { XM, EXq } },
2950   },
2951
2952   /* PREFIX_0F60 */
2953   {
2954     { "punpcklbw",{ MX, EMd } },
2955     { Bad_Opcode },
2956     { "punpcklbw",{ MX, EMx } },
2957   },
2958
2959   /* PREFIX_0F61 */
2960   {
2961     { "punpcklwd",{ MX, EMd } },
2962     { Bad_Opcode },
2963     { "punpcklwd",{ MX, EMx } },
2964   },
2965
2966   /* PREFIX_0F62 */
2967   {
2968     { "punpckldq",{ MX, EMd } },
2969     { Bad_Opcode },
2970     { "punpckldq",{ MX, EMx } },
2971   },
2972
2973   /* PREFIX_0F6C */
2974   {
2975     { Bad_Opcode },
2976     { Bad_Opcode },
2977     { "punpcklqdq", { XM, EXx } },
2978   },
2979
2980   /* PREFIX_0F6D */
2981   {
2982     { Bad_Opcode },
2983     { Bad_Opcode },
2984     { "punpckhqdq", { XM, EXx } },
2985   },
2986
2987   /* PREFIX_0F6F */
2988   {
2989     { "movq",   { MX, EM } },
2990     { "movdqu", { XM, EXx } },
2991     { "movdqa", { XM, EXx } },
2992   },
2993
2994   /* PREFIX_0F70 */
2995   {
2996     { "pshufw", { MX, EM, Ib } },
2997     { "pshufhw",{ XM, EXx, Ib } },
2998     { "pshufd", { XM, EXx, Ib } },
2999     { "pshuflw",{ XM, EXx, Ib } },
3000   },
3001
3002   /* PREFIX_0F73_REG_3 */
3003   {
3004     { Bad_Opcode },
3005     { Bad_Opcode },
3006     { "psrldq", { XS, Ib } },
3007   },
3008
3009   /* PREFIX_0F73_REG_7 */
3010   {
3011     { Bad_Opcode },
3012     { Bad_Opcode },
3013     { "pslldq", { XS, Ib } },
3014   },
3015
3016   /* PREFIX_0F78 */
3017   {
3018     {"vmread",  { Em, Gm } },
3019     { Bad_Opcode },
3020     {"extrq",   { XS, Ib, Ib } },
3021     {"insertq", { XM, XS, Ib, Ib } },
3022   },
3023
3024   /* PREFIX_0F79 */
3025   {
3026     {"vmwrite", { Gm, Em } },
3027     { Bad_Opcode },
3028     {"extrq",   { XM, XS } },
3029     {"insertq", { XM, XS } },
3030   },
3031
3032   /* PREFIX_0F7C */
3033   {
3034     { Bad_Opcode },
3035     { Bad_Opcode },
3036     { "haddpd", { XM, EXx } },
3037     { "haddps", { XM, EXx } },
3038   },
3039
3040   /* PREFIX_0F7D */
3041   {
3042     { Bad_Opcode },
3043     { Bad_Opcode },
3044     { "hsubpd", { XM, EXx } },
3045     { "hsubps", { XM, EXx } },
3046   },
3047
3048   /* PREFIX_0F7E */
3049   {
3050     { "movK",   { Edq, MX } },
3051     { "movq",   { XM, EXq } },
3052     { "movK",   { Edq, XM } },
3053   },
3054
3055   /* PREFIX_0F7F */
3056   {
3057     { "movq",   { EMS, MX } },
3058     { "movdqu", { EXxS, XM } },
3059     { "movdqa", { EXxS, XM } },
3060   },
3061
3062   /* PREFIX_0FAE_REG_0 */
3063   {
3064     { Bad_Opcode },
3065     { "rdfsbase", { Ev } },
3066   },
3067
3068   /* PREFIX_0FAE_REG_1 */
3069   {
3070     { Bad_Opcode },
3071     { "rdgsbase", { Ev } },
3072   },
3073
3074   /* PREFIX_0FAE_REG_2 */
3075   {
3076     { Bad_Opcode },
3077     { "wrfsbase", { Ev } },
3078   },
3079
3080   /* PREFIX_0FAE_REG_3 */
3081   {
3082     { Bad_Opcode },
3083     { "wrgsbase", { Ev } },
3084   },
3085
3086   /* PREFIX_0FB8 */
3087   {
3088     { Bad_Opcode },
3089     { "popcntS", { Gv, Ev } },
3090   },
3091
3092   /* PREFIX_0FBC */
3093   {
3094     { "bsfS",   { Gv, Ev } },
3095     { "tzcntS", { Gv, Ev } },
3096     { "bsfS",   { Gv, Ev } },
3097   },
3098
3099   /* PREFIX_0FBD */
3100   {
3101     { "bsrS",   { Gv, Ev } },
3102     { "lzcntS", { Gv, Ev } },
3103     { "bsrS",   { Gv, Ev } },
3104   },
3105
3106   /* PREFIX_0FC2 */
3107   {
3108     { "cmpps",  { XM, EXx, CMP } },
3109     { "cmpss",  { XM, EXd, CMP } },
3110     { "cmppd",  { XM, EXx, CMP } },
3111     { "cmpsd",  { XM, EXq, CMP } },
3112   },
3113
3114   /* PREFIX_0FC3 */
3115   {
3116     { "movntiS", { Ma, Gv } },
3117   },
3118
3119   /* PREFIX_0FC7_REG_6 */
3120   {
3121     { "vmptrld",{ Mq } },
3122     { "vmxon",  { Mq } },
3123     { "vmclear",{ Mq } },
3124   },
3125
3126   /* PREFIX_0FD0 */
3127   {
3128     { Bad_Opcode },
3129     { Bad_Opcode },
3130     { "addsubpd", { XM, EXx } },
3131     { "addsubps", { XM, EXx } },
3132   },
3133
3134   /* PREFIX_0FD6 */
3135   {
3136     { Bad_Opcode },
3137     { "movq2dq",{ XM, MS } },
3138     { "movq",   { EXqS, XM } },
3139     { "movdq2q",{ MX, XS } },
3140   },
3141
3142   /* PREFIX_0FE6 */
3143   {
3144     { Bad_Opcode },
3145     { "cvtdq2pd", { XM, EXq } },
3146     { "cvttpd2dq", { XM, EXx } },
3147     { "cvtpd2dq", { XM, EXx } },
3148   },
3149
3150   /* PREFIX_0FE7 */
3151   {
3152     { "movntq", { Mq, MX } },
3153     { Bad_Opcode },
3154     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3155   },
3156
3157   /* PREFIX_0FF0 */
3158   {
3159     { Bad_Opcode },
3160     { Bad_Opcode },
3161     { Bad_Opcode },
3162     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3163   },
3164
3165   /* PREFIX_0FF7 */
3166   {
3167     { "maskmovq", { MX, MS } },
3168     { Bad_Opcode },
3169     { "maskmovdqu", { XM, XS } },
3170   },
3171
3172   /* PREFIX_0F3810 */
3173   {
3174     { Bad_Opcode },
3175     { Bad_Opcode },
3176     { "pblendvb", { XM, EXx, XMM0 } },
3177   },
3178
3179   /* PREFIX_0F3814 */
3180   {
3181     { Bad_Opcode },
3182     { Bad_Opcode },
3183     { "blendvps", { XM, EXx, XMM0 } },
3184   },
3185
3186   /* PREFIX_0F3815 */
3187   {
3188     { Bad_Opcode },
3189     { Bad_Opcode },
3190     { "blendvpd", { XM, EXx, XMM0 } },
3191   },
3192
3193   /* PREFIX_0F3817 */
3194   {
3195     { Bad_Opcode },
3196     { Bad_Opcode },
3197     { "ptest",  { XM, EXx } },
3198   },
3199
3200   /* PREFIX_0F3820 */
3201   {
3202     { Bad_Opcode },
3203     { Bad_Opcode },
3204     { "pmovsxbw", { XM, EXq } },
3205   },
3206
3207   /* PREFIX_0F3821 */
3208   {
3209     { Bad_Opcode },
3210     { Bad_Opcode },
3211     { "pmovsxbd", { XM, EXd } },
3212   },
3213
3214   /* PREFIX_0F3822 */
3215   {
3216     { Bad_Opcode },
3217     { Bad_Opcode },
3218     { "pmovsxbq", { XM, EXw } },
3219   },
3220
3221   /* PREFIX_0F3823 */
3222   {
3223     { Bad_Opcode },
3224     { Bad_Opcode },
3225     { "pmovsxwd", { XM, EXq } },
3226   },
3227
3228   /* PREFIX_0F3824 */
3229   {
3230     { Bad_Opcode },
3231     { Bad_Opcode },
3232     { "pmovsxwq", { XM, EXd } },
3233   },
3234
3235   /* PREFIX_0F3825 */
3236   {
3237     { Bad_Opcode },
3238     { Bad_Opcode },
3239     { "pmovsxdq", { XM, EXq } },
3240   },
3241
3242   /* PREFIX_0F3828 */
3243   {
3244     { Bad_Opcode },
3245     { Bad_Opcode },
3246     { "pmuldq", { XM, EXx } },
3247   },
3248
3249   /* PREFIX_0F3829 */
3250   {
3251     { Bad_Opcode },
3252     { Bad_Opcode },
3253     { "pcmpeqq", { XM, EXx } },
3254   },
3255
3256   /* PREFIX_0F382A */
3257   {
3258     { Bad_Opcode },
3259     { Bad_Opcode },
3260     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3261   },
3262
3263   /* PREFIX_0F382B */
3264   {
3265     { Bad_Opcode },
3266     { Bad_Opcode },
3267     { "packusdw", { XM, EXx } },
3268   },
3269
3270   /* PREFIX_0F3830 */
3271   {
3272     { Bad_Opcode },
3273     { Bad_Opcode },
3274     { "pmovzxbw", { XM, EXq } },
3275   },
3276
3277   /* PREFIX_0F3831 */
3278   {
3279     { Bad_Opcode },
3280     { Bad_Opcode },
3281     { "pmovzxbd", { XM, EXd } },
3282   },
3283
3284   /* PREFIX_0F3832 */
3285   {
3286     { Bad_Opcode },
3287     { Bad_Opcode },
3288     { "pmovzxbq", { XM, EXw } },
3289   },
3290
3291   /* PREFIX_0F3833 */
3292   {
3293     { Bad_Opcode },
3294     { Bad_Opcode },
3295     { "pmovzxwd", { XM, EXq } },
3296   },
3297
3298   /* PREFIX_0F3834 */
3299   {
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { "pmovzxwq", { XM, EXd } },
3303   },
3304
3305   /* PREFIX_0F3835 */
3306   {
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { "pmovzxdq", { XM, EXq } },
3310   },
3311
3312   /* PREFIX_0F3837 */
3313   {
3314     { Bad_Opcode },
3315     { Bad_Opcode },
3316     { "pcmpgtq", { XM, EXx } },
3317   },
3318
3319   /* PREFIX_0F3838 */
3320   {
3321     { Bad_Opcode },
3322     { Bad_Opcode },
3323     { "pminsb", { XM, EXx } },
3324   },
3325
3326   /* PREFIX_0F3839 */
3327   {
3328     { Bad_Opcode },
3329     { Bad_Opcode },
3330     { "pminsd", { XM, EXx } },
3331   },
3332
3333   /* PREFIX_0F383A */
3334   {
3335     { Bad_Opcode },
3336     { Bad_Opcode },
3337     { "pminuw", { XM, EXx } },
3338   },
3339
3340   /* PREFIX_0F383B */
3341   {
3342     { Bad_Opcode },
3343     { Bad_Opcode },
3344     { "pminud", { XM, EXx } },
3345   },
3346
3347   /* PREFIX_0F383C */
3348   {
3349     { Bad_Opcode },
3350     { Bad_Opcode },
3351     { "pmaxsb", { XM, EXx } },
3352   },
3353
3354   /* PREFIX_0F383D */
3355   {
3356     { Bad_Opcode },
3357     { Bad_Opcode },
3358     { "pmaxsd", { XM, EXx } },
3359   },
3360
3361   /* PREFIX_0F383E */
3362   {
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { "pmaxuw", { XM, EXx } },
3366   },
3367
3368   /* PREFIX_0F383F */
3369   {
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { "pmaxud", { XM, EXx } },
3373   },
3374
3375   /* PREFIX_0F3840 */
3376   {
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { "pmulld", { XM, EXx } },
3380   },
3381
3382   /* PREFIX_0F3841 */
3383   {
3384     { Bad_Opcode },
3385     { Bad_Opcode },
3386     { "phminposuw", { XM, EXx } },
3387   },
3388
3389   /* PREFIX_0F3880 */
3390   {
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393     { "invept", { Gm, Mo } },
3394   },
3395
3396   /* PREFIX_0F3881 */
3397   {
3398     { Bad_Opcode },
3399     { Bad_Opcode },
3400     { "invvpid", { Gm, Mo } },
3401   },
3402
3403   /* PREFIX_0F38DB */
3404   {
3405     { Bad_Opcode },
3406     { Bad_Opcode },
3407     { "aesimc", { XM, EXx } },
3408   },
3409
3410   /* PREFIX_0F38DC */
3411   {
3412     { Bad_Opcode },
3413     { Bad_Opcode },
3414     { "aesenc", { XM, EXx } },
3415   },
3416
3417   /* PREFIX_0F38DD */
3418   {
3419     { Bad_Opcode },
3420     { Bad_Opcode },
3421     { "aesenclast", { XM, EXx } },
3422   },
3423
3424   /* PREFIX_0F38DE */
3425   {
3426     { Bad_Opcode },
3427     { Bad_Opcode },
3428     { "aesdec", { XM, EXx } },
3429   },
3430
3431   /* PREFIX_0F38DF */
3432   {
3433     { Bad_Opcode },
3434     { Bad_Opcode },
3435     { "aesdeclast", { XM, EXx } },
3436   },
3437
3438   /* PREFIX_0F38F0 */
3439   {
3440     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3441     { Bad_Opcode },
3442     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3443     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3444   },
3445
3446   /* PREFIX_0F38F1 */
3447   {
3448     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3449     { Bad_Opcode },
3450     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3451     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3452   },
3453
3454   /* PREFIX_0F3A08 */
3455   {
3456     { Bad_Opcode },
3457     { Bad_Opcode },
3458     { "roundps", { XM, EXx, Ib } },
3459   },
3460
3461   /* PREFIX_0F3A09 */
3462   {
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { "roundpd", { XM, EXx, Ib } },
3466   },
3467
3468   /* PREFIX_0F3A0A */
3469   {
3470     { Bad_Opcode },
3471     { Bad_Opcode },
3472     { "roundss", { XM, EXd, Ib } },
3473   },
3474
3475   /* PREFIX_0F3A0B */
3476   {
3477     { Bad_Opcode },
3478     { Bad_Opcode },
3479     { "roundsd", { XM, EXq, Ib } },
3480   },
3481
3482   /* PREFIX_0F3A0C */
3483   {
3484     { Bad_Opcode },
3485     { Bad_Opcode },
3486     { "blendps", { XM, EXx, Ib } },
3487   },
3488
3489   /* PREFIX_0F3A0D */
3490   {
3491     { Bad_Opcode },
3492     { Bad_Opcode },
3493     { "blendpd", { XM, EXx, Ib } },
3494   },
3495
3496   /* PREFIX_0F3A0E */
3497   {
3498     { Bad_Opcode },
3499     { Bad_Opcode },
3500     { "pblendw", { XM, EXx, Ib } },
3501   },
3502
3503   /* PREFIX_0F3A14 */
3504   {
3505     { Bad_Opcode },
3506     { Bad_Opcode },
3507     { "pextrb", { Edqb, XM, Ib } },
3508   },
3509
3510   /* PREFIX_0F3A15 */
3511   {
3512     { Bad_Opcode },
3513     { Bad_Opcode },
3514     { "pextrw", { Edqw, XM, Ib } },
3515   },
3516
3517   /* PREFIX_0F3A16 */
3518   {
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { "pextrK", { Edq, XM, Ib } },
3522   },
3523
3524   /* PREFIX_0F3A17 */
3525   {
3526     { Bad_Opcode },
3527     { Bad_Opcode },
3528     { "extractps", { Edqd, XM, Ib } },
3529   },
3530
3531   /* PREFIX_0F3A20 */
3532   {
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { "pinsrb", { XM, Edqb, Ib } },
3536   },
3537
3538   /* PREFIX_0F3A21 */
3539   {
3540     { Bad_Opcode },
3541     { Bad_Opcode },
3542     { "insertps", { XM, EXd, Ib } },
3543   },
3544
3545   /* PREFIX_0F3A22 */
3546   {
3547     { Bad_Opcode },
3548     { Bad_Opcode },
3549     { "pinsrK", { XM, Edq, Ib } },
3550   },
3551
3552   /* PREFIX_0F3A40 */
3553   {
3554     { Bad_Opcode },
3555     { Bad_Opcode },
3556     { "dpps",   { XM, EXx, Ib } },
3557   },
3558
3559   /* PREFIX_0F3A41 */
3560   {
3561     { Bad_Opcode },
3562     { Bad_Opcode },
3563     { "dppd",   { XM, EXx, Ib } },
3564   },
3565
3566   /* PREFIX_0F3A42 */
3567   {
3568     { Bad_Opcode },
3569     { Bad_Opcode },
3570     { "mpsadbw", { XM, EXx, Ib } },
3571   },
3572
3573   /* PREFIX_0F3A44 */
3574   {
3575     { Bad_Opcode },
3576     { Bad_Opcode },
3577     { "pclmulqdq", { XM, EXx, PCLMUL } },
3578   },
3579
3580   /* PREFIX_0F3A60 */
3581   {
3582     { Bad_Opcode },
3583     { Bad_Opcode },
3584     { "pcmpestrm", { XM, EXx, Ib } },
3585   },
3586
3587   /* PREFIX_0F3A61 */
3588   {
3589     { Bad_Opcode },
3590     { Bad_Opcode },
3591     { "pcmpestri", { XM, EXx, Ib } },
3592   },
3593
3594   /* PREFIX_0F3A62 */
3595   {
3596     { Bad_Opcode },
3597     { Bad_Opcode },
3598     { "pcmpistrm", { XM, EXx, Ib } },
3599   },
3600
3601   /* PREFIX_0F3A63 */
3602   {
3603     { Bad_Opcode },
3604     { Bad_Opcode },
3605     { "pcmpistri", { XM, EXx, Ib } },
3606   },
3607
3608   /* PREFIX_0F3ADF */
3609   {
3610     { Bad_Opcode },
3611     { Bad_Opcode },
3612     { "aeskeygenassist", { XM, EXx, Ib } },
3613   },
3614
3615   /* PREFIX_VEX_0F10 */
3616   {
3617     { VEX_W_TABLE (VEX_W_0F10_P_0) },
3618     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3619     { VEX_W_TABLE (VEX_W_0F10_P_2) },
3620     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3621   },
3622
3623   /* PREFIX_VEX_0F11 */
3624   {
3625     { VEX_W_TABLE (VEX_W_0F11_P_0) },
3626     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3627     { VEX_W_TABLE (VEX_W_0F11_P_2) },
3628     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3629   },
3630
3631   /* PREFIX_VEX_0F12 */
3632   {
3633     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3634     { VEX_W_TABLE (VEX_W_0F12_P_1) },
3635     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3636     { VEX_W_TABLE (VEX_W_0F12_P_3) },
3637   },
3638
3639   /* PREFIX_VEX_0F16 */
3640   {
3641     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3642     { VEX_W_TABLE (VEX_W_0F16_P_1) },
3643     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3644   },
3645
3646   /* PREFIX_VEX_0F2A */
3647   {
3648     { Bad_Opcode },
3649     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3650     { Bad_Opcode },
3651     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3652   },
3653
3654   /* PREFIX_VEX_0F2C */
3655   {
3656     { Bad_Opcode },
3657     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3658     { Bad_Opcode },
3659     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3660   },
3661
3662   /* PREFIX_VEX_0F2D */
3663   {
3664     { Bad_Opcode },
3665     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3666     { Bad_Opcode },
3667     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3668   },
3669
3670   /* PREFIX_VEX_0F2E */
3671   {
3672     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3673     { Bad_Opcode },
3674     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3675   },
3676
3677   /* PREFIX_VEX_0F2F */
3678   {
3679     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3680     { Bad_Opcode },
3681     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3682   },
3683
3684   /* PREFIX_VEX_0F51 */
3685   {
3686     { VEX_W_TABLE (VEX_W_0F51_P_0) },
3687     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3688     { VEX_W_TABLE (VEX_W_0F51_P_2) },
3689     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3690   },
3691
3692   /* PREFIX_VEX_0F52 */
3693   {
3694     { VEX_W_TABLE (VEX_W_0F52_P_0) },
3695     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3696   },
3697
3698   /* PREFIX_VEX_0F53 */
3699   {
3700     { VEX_W_TABLE (VEX_W_0F53_P_0) },
3701     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3702   },
3703
3704   /* PREFIX_VEX_0F58 */
3705   {
3706     { VEX_W_TABLE (VEX_W_0F58_P_0) },
3707     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3708     { VEX_W_TABLE (VEX_W_0F58_P_2) },
3709     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3710   },
3711
3712   /* PREFIX_VEX_0F59 */
3713   {
3714     { VEX_W_TABLE (VEX_W_0F59_P_0) },
3715     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3716     { VEX_W_TABLE (VEX_W_0F59_P_2) },
3717     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3718   },
3719
3720   /* PREFIX_VEX_0F5A */
3721   {
3722     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3723     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3724     { "vcvtpd2ps%XY", { XMM, EXx } },
3725     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3726   },
3727
3728   /* PREFIX_VEX_0F5B */
3729   {
3730     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3731     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3732     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3733   },
3734
3735   /* PREFIX_VEX_0F5C */
3736   {
3737     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3738     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3739     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3740     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3741   },
3742
3743   /* PREFIX_VEX_0F5D */
3744   {
3745     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3746     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3747     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3748     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3749   },
3750
3751   /* PREFIX_VEX_0F5E */
3752   {
3753     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3754     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3755     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3756     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3757   },
3758
3759   /* PREFIX_VEX_0F5F */
3760   {
3761     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3762     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3763     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3764     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3765   },
3766
3767   /* PREFIX_VEX_0F60 */
3768   {
3769     { Bad_Opcode },
3770     { Bad_Opcode },
3771     { VEX_LEN_TABLE (VEX_LEN_0F60_P_2) },
3772   },
3773
3774   /* PREFIX_VEX_0F61 */
3775   {
3776     { Bad_Opcode },
3777     { Bad_Opcode },
3778     { VEX_LEN_TABLE (VEX_LEN_0F61_P_2) },
3779   },
3780
3781   /* PREFIX_VEX_0F62 */
3782   {
3783     { Bad_Opcode },
3784     { Bad_Opcode },
3785     { VEX_LEN_TABLE (VEX_LEN_0F62_P_2) },
3786   },
3787
3788   /* PREFIX_VEX_0F63 */
3789   {
3790     { Bad_Opcode },
3791     { Bad_Opcode },
3792     { VEX_LEN_TABLE (VEX_LEN_0F63_P_2) },
3793   },
3794
3795   /* PREFIX_VEX_0F64 */
3796   {
3797     { Bad_Opcode },
3798     { Bad_Opcode },
3799     { VEX_LEN_TABLE (VEX_LEN_0F64_P_2) },
3800   },
3801
3802   /* PREFIX_VEX_0F65 */
3803   {
3804     { Bad_Opcode },
3805     { Bad_Opcode },
3806     { VEX_LEN_TABLE (VEX_LEN_0F65_P_2) },
3807   },
3808
3809   /* PREFIX_VEX_0F66 */
3810   {
3811     { Bad_Opcode },
3812     { Bad_Opcode },
3813     { VEX_LEN_TABLE (VEX_LEN_0F66_P_2) },
3814   },
3815
3816   /* PREFIX_VEX_0F67 */
3817   {
3818     { Bad_Opcode },
3819     { Bad_Opcode },
3820     { VEX_LEN_TABLE (VEX_LEN_0F67_P_2) },
3821   },
3822
3823   /* PREFIX_VEX_0F68 */
3824   {
3825     { Bad_Opcode },
3826     { Bad_Opcode },
3827     { VEX_LEN_TABLE (VEX_LEN_0F68_P_2) },
3828   },
3829
3830   /* PREFIX_VEX_0F69 */
3831   {
3832     { Bad_Opcode },
3833     { Bad_Opcode },
3834     { VEX_LEN_TABLE (VEX_LEN_0F69_P_2) },
3835   },
3836
3837   /* PREFIX_VEX_0F6A */
3838   {
3839     { Bad_Opcode },
3840     { Bad_Opcode },
3841     { VEX_LEN_TABLE (VEX_LEN_0F6A_P_2) },
3842   },
3843
3844   /* PREFIX_VEX_0F6B */
3845   {
3846     { Bad_Opcode },
3847     { Bad_Opcode },
3848     { VEX_LEN_TABLE (VEX_LEN_0F6B_P_2) },
3849   },
3850
3851   /* PREFIX_VEX_0F6C */
3852   {
3853     { Bad_Opcode },
3854     { Bad_Opcode },
3855     { VEX_LEN_TABLE (VEX_LEN_0F6C_P_2) },
3856   },
3857
3858   /* PREFIX_VEX_0F6D */
3859   {
3860     { Bad_Opcode },
3861     { Bad_Opcode },
3862     { VEX_LEN_TABLE (VEX_LEN_0F6D_P_2) },
3863   },
3864
3865   /* PREFIX_VEX_0F6E */
3866   {
3867     { Bad_Opcode },
3868     { Bad_Opcode },
3869     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3870   },
3871
3872   /* PREFIX_VEX_0F6F */
3873   {
3874     { Bad_Opcode },
3875     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3876     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3877   },
3878
3879   /* PREFIX_VEX_0F70 */
3880   {
3881     { Bad_Opcode },
3882     { VEX_LEN_TABLE (VEX_LEN_0F70_P_1) },
3883     { VEX_LEN_TABLE (VEX_LEN_0F70_P_2) },
3884     { VEX_LEN_TABLE (VEX_LEN_0F70_P_3) },
3885   },
3886
3887   /* PREFIX_VEX_0F71_REG_2 */
3888   {
3889     { Bad_Opcode },
3890     { Bad_Opcode },
3891     { VEX_LEN_TABLE (VEX_LEN_0F71_R_2_P_2) },
3892   },
3893
3894   /* PREFIX_VEX_0F71_REG_4 */
3895   {
3896     { Bad_Opcode },
3897     { Bad_Opcode },
3898     { VEX_LEN_TABLE (VEX_LEN_0F71_R_4_P_2) },
3899   },
3900
3901   /* PREFIX_VEX_0F71_REG_6 */
3902   {
3903     { Bad_Opcode },
3904     { Bad_Opcode },
3905     { VEX_LEN_TABLE (VEX_LEN_0F71_R_6_P_2) },
3906   },
3907
3908   /* PREFIX_VEX_0F72_REG_2 */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { VEX_LEN_TABLE (VEX_LEN_0F72_R_2_P_2) },
3913   },
3914
3915   /* PREFIX_VEX_0F72_REG_4 */
3916   {
3917     { Bad_Opcode },
3918     { Bad_Opcode },
3919     { VEX_LEN_TABLE (VEX_LEN_0F72_R_4_P_2) },
3920   },
3921
3922   /* PREFIX_VEX_0F72_REG_6 */
3923   {
3924     { Bad_Opcode },
3925     { Bad_Opcode },
3926     { VEX_LEN_TABLE (VEX_LEN_0F72_R_6_P_2) },
3927   },
3928
3929   /* PREFIX_VEX_0F73_REG_2 */
3930   {
3931     { Bad_Opcode },
3932     { Bad_Opcode },
3933     { VEX_LEN_TABLE (VEX_LEN_0F73_R_2_P_2) },
3934   },
3935
3936   /* PREFIX_VEX_0F73_REG_3 */
3937   {
3938     { Bad_Opcode },
3939     { Bad_Opcode },
3940     { VEX_LEN_TABLE (VEX_LEN_0F73_R_3_P_2) },
3941   },
3942
3943   /* PREFIX_VEX_0F73_REG_6 */
3944   {
3945     { Bad_Opcode },
3946     { Bad_Opcode },
3947     { VEX_LEN_TABLE (VEX_LEN_0F73_R_6_P_2) },
3948   },
3949
3950   /* PREFIX_VEX_0F73_REG_7 */
3951   {
3952     { Bad_Opcode },
3953     { Bad_Opcode },
3954     { VEX_LEN_TABLE (VEX_LEN_0F73_R_7_P_2) },
3955   },
3956
3957   /* PREFIX_VEX_0F74 */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { VEX_LEN_TABLE (VEX_LEN_0F74_P_2) },
3962   },
3963
3964   /* PREFIX_VEX_0F75 */
3965   {
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { VEX_LEN_TABLE (VEX_LEN_0F75_P_2) },
3969   },
3970
3971   /* PREFIX_VEX_0F76 */
3972   {
3973     { Bad_Opcode },
3974     { Bad_Opcode },
3975     { VEX_LEN_TABLE (VEX_LEN_0F76_P_2) },
3976   },
3977
3978   /* PREFIX_VEX_0F77 */
3979   {
3980     { VEX_W_TABLE (VEX_W_0F77_P_0) },
3981   },
3982
3983   /* PREFIX_VEX_0F7C */
3984   {
3985     { Bad_Opcode },
3986     { Bad_Opcode },
3987     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
3988     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
3989   },
3990
3991   /* PREFIX_VEX_0F7D */
3992   {
3993     { Bad_Opcode },
3994     { Bad_Opcode },
3995     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
3996     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
3997   },
3998
3999   /* PREFIX_VEX_0F7E */
4000   {
4001     { Bad_Opcode },
4002     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4003     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4004   },
4005
4006   /* PREFIX_VEX_0F7F */
4007   {
4008     { Bad_Opcode },
4009     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4010     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4011   },
4012
4013   /* PREFIX_VEX_0FC2 */
4014   {
4015     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4016     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4017     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4018     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4019   },
4020
4021   /* PREFIX_VEX_0FC4 */
4022   {
4023     { Bad_Opcode },
4024     { Bad_Opcode },
4025     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4026   },
4027
4028   /* PREFIX_VEX_0FC5 */
4029   {
4030     { Bad_Opcode },
4031     { Bad_Opcode },
4032     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4033   },
4034
4035   /* PREFIX_VEX_0FD0 */
4036   {
4037     { Bad_Opcode },
4038     { Bad_Opcode },
4039     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4040     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4041   },
4042
4043   /* PREFIX_VEX_0FD1 */
4044   {
4045     { Bad_Opcode },
4046     { Bad_Opcode },
4047     { VEX_LEN_TABLE (VEX_LEN_0FD1_P_2) },
4048   },
4049
4050   /* PREFIX_VEX_0FD2 */
4051   {
4052     { Bad_Opcode },
4053     { Bad_Opcode },
4054     { VEX_LEN_TABLE (VEX_LEN_0FD2_P_2) },
4055   },
4056
4057   /* PREFIX_VEX_0FD3 */
4058   {
4059     { Bad_Opcode },
4060     { Bad_Opcode },
4061     { VEX_LEN_TABLE (VEX_LEN_0FD3_P_2) },
4062   },
4063
4064   /* PREFIX_VEX_0FD4 */
4065   {
4066     { Bad_Opcode },
4067     { Bad_Opcode },
4068     { VEX_LEN_TABLE (VEX_LEN_0FD4_P_2) },
4069   },
4070
4071   /* PREFIX_VEX_0FD5 */
4072   {
4073     { Bad_Opcode },
4074     { Bad_Opcode },
4075     { VEX_LEN_TABLE (VEX_LEN_0FD5_P_2) },
4076   },
4077
4078   /* PREFIX_VEX_0FD6 */
4079   {
4080     { Bad_Opcode },
4081     { Bad_Opcode },
4082     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4083   },
4084
4085   /* PREFIX_VEX_0FD7 */
4086   {
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4090   },
4091
4092   /* PREFIX_VEX_0FD8 */
4093   {
4094     { Bad_Opcode },
4095     { Bad_Opcode },
4096     { VEX_LEN_TABLE (VEX_LEN_0FD8_P_2) },
4097   },
4098
4099   /* PREFIX_VEX_0FD9 */
4100   {
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { VEX_LEN_TABLE (VEX_LEN_0FD9_P_2) },
4104   },
4105
4106   /* PREFIX_VEX_0FDA */
4107   {
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { VEX_LEN_TABLE (VEX_LEN_0FDA_P_2) },
4111   },
4112
4113   /* PREFIX_VEX_0FDB */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { VEX_LEN_TABLE (VEX_LEN_0FDB_P_2) },
4118   },
4119
4120   /* PREFIX_VEX_0FDC */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { VEX_LEN_TABLE (VEX_LEN_0FDC_P_2) },
4125   },
4126
4127   /* PREFIX_VEX_0FDD */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { VEX_LEN_TABLE (VEX_LEN_0FDD_P_2) },
4132   },
4133
4134   /* PREFIX_VEX_0FDE */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { VEX_LEN_TABLE (VEX_LEN_0FDE_P_2) },
4139   },
4140
4141   /* PREFIX_VEX_0FDF */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { VEX_LEN_TABLE (VEX_LEN_0FDF_P_2) },
4146   },
4147
4148   /* PREFIX_VEX_0FE0 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { VEX_LEN_TABLE (VEX_LEN_0FE0_P_2) },
4153   },
4154
4155   /* PREFIX_VEX_0FE1 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { VEX_LEN_TABLE (VEX_LEN_0FE1_P_2) },
4160   },
4161
4162   /* PREFIX_VEX_0FE2 */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { VEX_LEN_TABLE (VEX_LEN_0FE2_P_2) },
4167   },
4168
4169   /* PREFIX_VEX_0FE3 */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { VEX_LEN_TABLE (VEX_LEN_0FE3_P_2) },
4174   },
4175
4176   /* PREFIX_VEX_0FE4 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { VEX_LEN_TABLE (VEX_LEN_0FE4_P_2) },
4181   },
4182
4183   /* PREFIX_VEX_0FE5 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { VEX_LEN_TABLE (VEX_LEN_0FE5_P_2) },
4188   },
4189
4190   /* PREFIX_VEX_0FE6 */
4191   {
4192     { Bad_Opcode },
4193     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4194     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4195     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4196   },
4197
4198   /* PREFIX_VEX_0FE7 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4203   },
4204
4205   /* PREFIX_VEX_0FE8 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { VEX_LEN_TABLE (VEX_LEN_0FE8_P_2) },
4210   },
4211
4212   /* PREFIX_VEX_0FE9 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { VEX_LEN_TABLE (VEX_LEN_0FE9_P_2) },
4217   },
4218
4219   /* PREFIX_VEX_0FEA */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { VEX_LEN_TABLE (VEX_LEN_0FEA_P_2) },
4224   },
4225
4226   /* PREFIX_VEX_0FEB */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { VEX_LEN_TABLE (VEX_LEN_0FEB_P_2) },
4231   },
4232
4233   /* PREFIX_VEX_0FEC */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { VEX_LEN_TABLE (VEX_LEN_0FEC_P_2) },
4238   },
4239
4240   /* PREFIX_VEX_0FED */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { VEX_LEN_TABLE (VEX_LEN_0FED_P_2) },
4245   },
4246
4247   /* PREFIX_VEX_0FEE */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { VEX_LEN_TABLE (VEX_LEN_0FEE_P_2) },
4252   },
4253
4254   /* PREFIX_VEX_0FEF */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { VEX_LEN_TABLE (VEX_LEN_0FEF_P_2) },
4259   },
4260
4261   /* PREFIX_VEX_0FF0 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4267   },
4268
4269   /* PREFIX_VEX_0FF1 */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { VEX_LEN_TABLE (VEX_LEN_0FF1_P_2) },
4274   },
4275
4276   /* PREFIX_VEX_0FF2 */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { VEX_LEN_TABLE (VEX_LEN_0FF2_P_2) },
4281   },
4282
4283   /* PREFIX_VEX_0FF3 */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { VEX_LEN_TABLE (VEX_LEN_0FF3_P_2) },
4288   },
4289
4290   /* PREFIX_VEX_0FF4 */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { VEX_LEN_TABLE (VEX_LEN_0FF4_P_2) },
4295   },
4296
4297   /* PREFIX_VEX_0FF5 */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { VEX_LEN_TABLE (VEX_LEN_0FF5_P_2) },
4302   },
4303
4304   /* PREFIX_VEX_0FF6 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { VEX_LEN_TABLE (VEX_LEN_0FF6_P_2) },
4309   },
4310
4311   /* PREFIX_VEX_0FF7 */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4316   },
4317
4318   /* PREFIX_VEX_0FF8 */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { VEX_LEN_TABLE (VEX_LEN_0FF8_P_2) },
4323   },
4324
4325   /* PREFIX_VEX_0FF9 */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { VEX_LEN_TABLE (VEX_LEN_0FF9_P_2) },
4330   },
4331
4332   /* PREFIX_VEX_0FFA */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { VEX_LEN_TABLE (VEX_LEN_0FFA_P_2) },
4337   },
4338
4339   /* PREFIX_VEX_0FFB */
4340   {
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { VEX_LEN_TABLE (VEX_LEN_0FFB_P_2) },
4344   },
4345
4346   /* PREFIX_VEX_0FFC */
4347   {
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { VEX_LEN_TABLE (VEX_LEN_0FFC_P_2) },
4351   },
4352
4353   /* PREFIX_VEX_0FFD */
4354   {
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { VEX_LEN_TABLE (VEX_LEN_0FFD_P_2) },
4358   },
4359
4360   /* PREFIX_VEX_0FFE */
4361   {
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { VEX_LEN_TABLE (VEX_LEN_0FFE_P_2) },
4365   },
4366
4367   /* PREFIX_VEX_0F3800 */
4368   {
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { VEX_LEN_TABLE (VEX_LEN_0F3800_P_2) },
4372   },
4373
4374   /* PREFIX_VEX_0F3801 */
4375   {
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     { VEX_LEN_TABLE (VEX_LEN_0F3801_P_2) },
4379   },
4380
4381   /* PREFIX_VEX_0F3802 */
4382   {
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { VEX_LEN_TABLE (VEX_LEN_0F3802_P_2) },
4386   },
4387
4388   /* PREFIX_VEX_0F3803 */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { VEX_LEN_TABLE (VEX_LEN_0F3803_P_2) },
4393   },
4394
4395   /* PREFIX_VEX_0F3804 */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { VEX_LEN_TABLE (VEX_LEN_0F3804_P_2) },
4400   },
4401
4402   /* PREFIX_VEX_0F3805 */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { VEX_LEN_TABLE (VEX_LEN_0F3805_P_2) },
4407   },
4408
4409   /* PREFIX_VEX_0F3806 */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { VEX_LEN_TABLE (VEX_LEN_0F3806_P_2) },
4414   },
4415
4416   /* PREFIX_VEX_0F3807 */
4417   {
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { VEX_LEN_TABLE (VEX_LEN_0F3807_P_2) },
4421   },
4422
4423   /* PREFIX_VEX_0F3808 */
4424   {
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { VEX_LEN_TABLE (VEX_LEN_0F3808_P_2) },
4428   },
4429
4430   /* PREFIX_VEX_0F3809 */
4431   {
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { VEX_LEN_TABLE (VEX_LEN_0F3809_P_2) },
4435   },
4436
4437   /* PREFIX_VEX_0F380A */
4438   {
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { VEX_LEN_TABLE (VEX_LEN_0F380A_P_2) },
4442   },
4443
4444   /* PREFIX_VEX_0F380B */
4445   {
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { VEX_LEN_TABLE (VEX_LEN_0F380B_P_2) },
4449   },
4450
4451   /* PREFIX_VEX_0F380C */
4452   {
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4456   },
4457
4458   /* PREFIX_VEX_0F380D */
4459   {
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4463   },
4464
4465   /* PREFIX_VEX_0F380E */
4466   {
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4470   },
4471
4472   /* PREFIX_VEX_0F380F */
4473   {
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4477   },
4478
4479   /* PREFIX_VEX_0F3813 */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { "vcvtph2ps", { XM, EXxmmq } },
4484   },
4485
4486   /* PREFIX_VEX_0F3817 */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4491   },
4492
4493   /* PREFIX_VEX_0F3818 */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { MOD_TABLE (MOD_VEX_0F3818_PREFIX_2) },
4498   },
4499
4500   /* PREFIX_VEX_0F3819 */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { MOD_TABLE (MOD_VEX_0F3819_PREFIX_2) },
4505   },
4506
4507   /* PREFIX_VEX_0F381A */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4512   },
4513
4514   /* PREFIX_VEX_0F381C */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { VEX_LEN_TABLE (VEX_LEN_0F381C_P_2) },
4519   },
4520
4521   /* PREFIX_VEX_0F381D */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { VEX_LEN_TABLE (VEX_LEN_0F381D_P_2) },
4526   },
4527
4528   /* PREFIX_VEX_0F381E */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { VEX_LEN_TABLE (VEX_LEN_0F381E_P_2) },
4533   },
4534
4535   /* PREFIX_VEX_0F3820 */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { VEX_LEN_TABLE (VEX_LEN_0F3820_P_2) },
4540   },
4541
4542   /* PREFIX_VEX_0F3821 */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { VEX_LEN_TABLE (VEX_LEN_0F3821_P_2) },
4547   },
4548
4549   /* PREFIX_VEX_0F3822 */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { VEX_LEN_TABLE (VEX_LEN_0F3822_P_2) },
4554   },
4555
4556   /* PREFIX_VEX_0F3823 */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { VEX_LEN_TABLE (VEX_LEN_0F3823_P_2) },
4561   },
4562
4563   /* PREFIX_VEX_0F3824 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { VEX_LEN_TABLE (VEX_LEN_0F3824_P_2) },
4568   },
4569
4570   /* PREFIX_VEX_0F3825 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { VEX_LEN_TABLE (VEX_LEN_0F3825_P_2) },
4575   },
4576
4577   /* PREFIX_VEX_0F3828 */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { VEX_LEN_TABLE (VEX_LEN_0F3828_P_2) },
4582   },
4583
4584   /* PREFIX_VEX_0F3829 */
4585   {
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { VEX_LEN_TABLE (VEX_LEN_0F3829_P_2) },
4589   },
4590
4591   /* PREFIX_VEX_0F382A */
4592   {
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4596   },
4597
4598   /* PREFIX_VEX_0F382B */
4599   {
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { VEX_LEN_TABLE (VEX_LEN_0F382B_P_2) },
4603   },
4604
4605   /* PREFIX_VEX_0F382C */
4606   {
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4610   },
4611
4612   /* PREFIX_VEX_0F382D */
4613   {
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4617   },
4618
4619   /* PREFIX_VEX_0F382E */
4620   {
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4624   },
4625
4626   /* PREFIX_VEX_0F382F */
4627   {
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4631   },
4632
4633   /* PREFIX_VEX_0F3830 */
4634   {
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { VEX_LEN_TABLE (VEX_LEN_0F3830_P_2) },
4638   },
4639
4640   /* PREFIX_VEX_0F3831 */
4641   {
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     { VEX_LEN_TABLE (VEX_LEN_0F3831_P_2) },
4645   },
4646
4647   /* PREFIX_VEX_0F3832 */
4648   {
4649     { Bad_Opcode },
4650     { Bad_Opcode },
4651     { VEX_LEN_TABLE (VEX_LEN_0F3832_P_2) },
4652   },
4653
4654   /* PREFIX_VEX_0F3833 */
4655   {
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { VEX_LEN_TABLE (VEX_LEN_0F3833_P_2) },
4659   },
4660
4661   /* PREFIX_VEX_0F3834 */
4662   {
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { VEX_LEN_TABLE (VEX_LEN_0F3834_P_2) },
4666   },
4667
4668   /* PREFIX_VEX_0F3835 */
4669   {
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { VEX_LEN_TABLE (VEX_LEN_0F3835_P_2) },
4673   },
4674
4675   /* PREFIX_VEX_0F3837 */
4676   {
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     { VEX_LEN_TABLE (VEX_LEN_0F3837_P_2) },
4680   },
4681
4682   /* PREFIX_VEX_0F3838 */
4683   {
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { VEX_LEN_TABLE (VEX_LEN_0F3838_P_2) },
4687   },
4688
4689   /* PREFIX_VEX_0F3839 */
4690   {
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { VEX_LEN_TABLE (VEX_LEN_0F3839_P_2) },
4694   },
4695
4696   /* PREFIX_VEX_0F383A */
4697   {
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { VEX_LEN_TABLE (VEX_LEN_0F383A_P_2) },
4701   },
4702
4703   /* PREFIX_VEX_0F383B */
4704   {
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { VEX_LEN_TABLE (VEX_LEN_0F383B_P_2) },
4708   },
4709
4710   /* PREFIX_VEX_0F383C */
4711   {
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { VEX_LEN_TABLE (VEX_LEN_0F383C_P_2) },
4715   },
4716
4717   /* PREFIX_VEX_0F383D */
4718   {
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { VEX_LEN_TABLE (VEX_LEN_0F383D_P_2) },
4722   },
4723
4724   /* PREFIX_VEX_0F383E */
4725   {
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { VEX_LEN_TABLE (VEX_LEN_0F383E_P_2) },
4729   },
4730
4731   /* PREFIX_VEX_0F383F */
4732   {
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { VEX_LEN_TABLE (VEX_LEN_0F383F_P_2) },
4736   },
4737
4738   /* PREFIX_VEX_0F3840 */
4739   {
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { VEX_LEN_TABLE (VEX_LEN_0F3840_P_2) },
4743   },
4744
4745   /* PREFIX_VEX_0F3841 */
4746   {
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4750   },
4751
4752   /* PREFIX_VEX_0F3896 */
4753   {
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4757   },
4758
4759   /* PREFIX_VEX_0F3897 */
4760   {
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4764   },
4765
4766   /* PREFIX_VEX_0F3898 */
4767   {
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { "vfmadd132p%XW", { XM, Vex, EXx } },
4771   },
4772
4773   /* PREFIX_VEX_0F3899 */
4774   {
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4778   },
4779
4780   /* PREFIX_VEX_0F389A */
4781   {
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { "vfmsub132p%XW", { XM, Vex, EXx } },
4785   },
4786
4787   /* PREFIX_VEX_0F389B */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4792   },
4793
4794   /* PREFIX_VEX_0F389C */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4799   },
4800
4801   /* PREFIX_VEX_0F389D */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4806   },
4807
4808   /* PREFIX_VEX_0F389E */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4813   },
4814
4815   /* PREFIX_VEX_0F389F */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4820   },
4821
4822   /* PREFIX_VEX_0F38A6 */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4827     { Bad_Opcode },
4828   },
4829
4830   /* PREFIX_VEX_0F38A7 */
4831   {
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4835   },
4836
4837   /* PREFIX_VEX_0F38A8 */
4838   {
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { "vfmadd213p%XW", { XM, Vex, EXx } },
4842   },
4843
4844   /* PREFIX_VEX_0F38A9 */
4845   {
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4849   },
4850
4851   /* PREFIX_VEX_0F38AA */
4852   {
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { "vfmsub213p%XW", { XM, Vex, EXx } },
4856   },
4857
4858   /* PREFIX_VEX_0F38AB */
4859   {
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4863   },
4864
4865   /* PREFIX_VEX_0F38AC */
4866   {
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4870   },
4871
4872   /* PREFIX_VEX_0F38AD */
4873   {
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4877   },
4878
4879   /* PREFIX_VEX_0F38AE */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4884   },
4885
4886   /* PREFIX_VEX_0F38AF */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4891   },
4892
4893   /* PREFIX_VEX_0F38B6 */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4898   },
4899
4900   /* PREFIX_VEX_0F38B7 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4905   },
4906
4907   /* PREFIX_VEX_0F38B8 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { "vfmadd231p%XW", { XM, Vex, EXx } },
4912   },
4913
4914   /* PREFIX_VEX_0F38B9 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4919   },
4920
4921   /* PREFIX_VEX_0F38BA */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { "vfmsub231p%XW", { XM, Vex, EXx } },
4926   },
4927
4928   /* PREFIX_VEX_0F38BB */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4933   },
4934
4935   /* PREFIX_VEX_0F38BC */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4940   },
4941
4942   /* PREFIX_VEX_0F38BD */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4947   },
4948
4949   /* PREFIX_VEX_0F38BE */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4954   },
4955
4956   /* PREFIX_VEX_0F38BF */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4961   },
4962
4963   /* PREFIX_VEX_0F38DB */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
4968   },
4969
4970   /* PREFIX_VEX_0F38DC */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
4975   },
4976
4977   /* PREFIX_VEX_0F38DD */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
4982   },
4983
4984   /* PREFIX_VEX_0F38DE */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
4989   },
4990
4991   /* PREFIX_VEX_0F38DF */
4992   {
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
4996   },
4997
4998   /* PREFIX_VEX_0F38F2 */
4999   {
5000     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5001   },
5002
5003   /* PREFIX_VEX_0F38F3_REG_1 */
5004   {
5005     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5006   },
5007
5008   /* PREFIX_VEX_0F38F3_REG_2 */
5009   {
5010     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5011   },
5012
5013   /* PREFIX_VEX_0F38F3_REG_3 */
5014   {
5015     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5016   },
5017
5018   /* PREFIX_VEX_0F38F7 */
5019   {
5020     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5021   },
5022
5023   /* PREFIX_VEX_0F3A04 */
5024   {
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5028   },
5029
5030   /* PREFIX_VEX_0F3A05 */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5035   },
5036
5037   /* PREFIX_VEX_0F3A06 */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5042   },
5043
5044   /* PREFIX_VEX_0F3A08 */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5049   },
5050
5051   /* PREFIX_VEX_0F3A09 */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5056   },
5057
5058   /* PREFIX_VEX_0F3A0A */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5063   },
5064
5065   /* PREFIX_VEX_0F3A0B */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5070   },
5071
5072   /* PREFIX_VEX_0F3A0C */
5073   {
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5077   },
5078
5079   /* PREFIX_VEX_0F3A0D */
5080   {
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0F3A0E */
5087   {
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { VEX_LEN_TABLE (VEX_LEN_0F3A0E_P_2) },
5091   },
5092
5093   /* PREFIX_VEX_0F3A0F */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { VEX_LEN_TABLE (VEX_LEN_0F3A0F_P_2) },
5098   },
5099
5100   /* PREFIX_VEX_0F3A14 */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0F3A15 */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5112   },
5113
5114   /* PREFIX_VEX_0F3A16 */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5119   },
5120
5121   /* PREFIX_VEX_0F3A17 */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5126   },
5127
5128   /* PREFIX_VEX_0F3A18 */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0F3A19 */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5140   },
5141
5142   /* PREFIX_VEX_0F3A1D */
5143   {
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { "vcvtps2ph", { EXxmmq, XM, Ib } },
5147   },
5148
5149   /* PREFIX_VEX_0F3A20 */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5154   },
5155
5156   /* PREFIX_VEX_0F3A21 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5161   },
5162
5163   /* PREFIX_VEX_0F3A22 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5168   },
5169
5170   /* PREFIX_VEX_0F3A40 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5175   },
5176
5177   /* PREFIX_VEX_0F3A41 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5182   },
5183
5184   /* PREFIX_VEX_0F3A42 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_LEN_TABLE (VEX_LEN_0F3A42_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0F3A44 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5196   },
5197
5198   /* PREFIX_VEX_0F3A48 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0F3A49 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0F3A4A */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0F3A4B */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0F3A4C */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_LEN_TABLE (VEX_LEN_0F3A4C_P_2) },
5231   },
5232
5233   /* PREFIX_VEX_0F3A5C */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5238   },
5239
5240   /* PREFIX_VEX_0F3A5D */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5245   },
5246
5247   /* PREFIX_VEX_0F3A5E */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5252   },
5253
5254   /* PREFIX_VEX_0F3A5F */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5259   },
5260
5261   /* PREFIX_VEX_0F3A60 */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5266     { Bad_Opcode },
5267   },
5268
5269   /* PREFIX_VEX_0F3A61 */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5274   },
5275
5276   /* PREFIX_VEX_0F3A62 */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5281   },
5282
5283   /* PREFIX_VEX_0F3A63 */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5288   },
5289
5290   /* PREFIX_VEX_0F3A68 */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5295   },
5296
5297   /* PREFIX_VEX_0F3A69 */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5302   },
5303
5304   /* PREFIX_VEX_0F3A6A */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5309   },
5310
5311   /* PREFIX_VEX_0F3A6B */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5316   },
5317
5318   /* PREFIX_VEX_0F3A6C */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5323   },
5324
5325   /* PREFIX_VEX_0F3A6D */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5330   },
5331
5332   /* PREFIX_VEX_0F3A6E */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5337   },
5338
5339   /* PREFIX_VEX_0F3A6F */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5344   },
5345
5346   /* PREFIX_VEX_0F3A78 */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5351   },
5352
5353   /* PREFIX_VEX_0F3A79 */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5358   },
5359
5360   /* PREFIX_VEX_0F3A7A */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5365   },
5366
5367   /* PREFIX_VEX_0F3A7B */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5372   },
5373
5374   /* PREFIX_VEX_0F3A7C */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5379     { Bad_Opcode },
5380   },
5381
5382   /* PREFIX_VEX_0F3A7D */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5387   },
5388
5389   /* PREFIX_VEX_0F3A7E */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5394   },
5395
5396   /* PREFIX_VEX_0F3A7F */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5401   },
5402
5403   /* PREFIX_VEX_0F3ADF */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5408   },
5409 };
5410
5411 static const struct dis386 x86_64_table[][2] = {
5412   /* X86_64_06 */
5413   {
5414     { "pushP", { es } },
5415   },
5416
5417   /* X86_64_07 */
5418   {
5419     { "popP", { es } },
5420   },
5421
5422   /* X86_64_0D */
5423   {
5424     { "pushP", { cs } },
5425   },
5426
5427   /* X86_64_16 */
5428   {
5429     { "pushP", { ss } },
5430   },
5431
5432   /* X86_64_17 */
5433   {
5434     { "popP", { ss } },
5435   },
5436
5437   /* X86_64_1E */
5438   {
5439     { "pushP", { ds } },
5440   },
5441
5442   /* X86_64_1F */
5443   {
5444     { "popP", { ds } },
5445   },
5446
5447   /* X86_64_27 */
5448   {
5449     { "daa", { XX } },
5450   },
5451
5452   /* X86_64_2F */
5453   {
5454     { "das", { XX } },
5455   },
5456
5457   /* X86_64_37 */
5458   {
5459     { "aaa", { XX } },
5460   },
5461
5462   /* X86_64_3F */
5463   {
5464     { "aas", { XX } },
5465   },
5466
5467   /* X86_64_60 */
5468   {
5469     { "pushaP", { XX } },
5470   },
5471
5472   /* X86_64_61 */
5473   {
5474     { "popaP", { XX } },
5475   },
5476
5477   /* X86_64_62 */
5478   {
5479     { MOD_TABLE (MOD_62_32BIT) },
5480   },
5481
5482   /* X86_64_63 */
5483   {
5484     { "arpl", { Ew, Gw } },
5485     { "movs{lq|xd}", { Gv, Ed } },
5486   },
5487
5488   /* X86_64_6D */
5489   {
5490     { "ins{R|}", { Yzr, indirDX } },
5491     { "ins{G|}", { Yzr, indirDX } },
5492   },
5493
5494   /* X86_64_6F */
5495   {
5496     { "outs{R|}", { indirDXr, Xz } },
5497     { "outs{G|}", { indirDXr, Xz } },
5498   },
5499
5500   /* X86_64_9A */
5501   {
5502     { "Jcall{T|}", { Ap } },
5503   },
5504
5505   /* X86_64_C4 */
5506   {
5507     { MOD_TABLE (MOD_C4_32BIT) },
5508     { VEX_C4_TABLE (VEX_0F) },
5509   },
5510
5511   /* X86_64_C5 */
5512   {
5513     { MOD_TABLE (MOD_C5_32BIT) },
5514     { VEX_C5_TABLE (VEX_0F) },
5515   },
5516
5517   /* X86_64_CE */
5518   {
5519     { "into", { XX } },
5520   },
5521
5522   /* X86_64_D4 */
5523   {
5524     { "aam", { sIb } },
5525   },
5526
5527   /* X86_64_D5 */
5528   {
5529     { "aad", { sIb } },
5530   },
5531
5532   /* X86_64_EA */
5533   {
5534     { "Jjmp{T|}", { Ap } },
5535   },
5536
5537   /* X86_64_0F01_REG_0 */
5538   {
5539     { "sgdt{Q|IQ}", { M } },
5540     { "sgdt", { M } },
5541   },
5542
5543   /* X86_64_0F01_REG_1 */
5544   {
5545     { "sidt{Q|IQ}", { M } },
5546     { "sidt", { M } },
5547   },
5548
5549   /* X86_64_0F01_REG_2 */
5550   {
5551     { "lgdt{Q|Q}", { M } },
5552     { "lgdt", { M } },
5553   },
5554
5555   /* X86_64_0F01_REG_3 */
5556   {
5557     { "lidt{Q|Q}", { M } },
5558     { "lidt", { M } },
5559   },
5560 };
5561
5562 static const struct dis386 three_byte_table[][256] = {
5563
5564   /* THREE_BYTE_0F38 */
5565   {
5566     /* 00 */
5567     { "pshufb",         { MX, EM } },
5568     { "phaddw",         { MX, EM } },
5569     { "phaddd",         { MX, EM } },
5570     { "phaddsw",        { MX, EM } },
5571     { "pmaddubsw",      { MX, EM } },
5572     { "phsubw",         { MX, EM } },
5573     { "phsubd",         { MX, EM } },
5574     { "phsubsw",        { MX, EM } },
5575     /* 08 */
5576     { "psignb",         { MX, EM } },
5577     { "psignw",         { MX, EM } },
5578     { "psignd",         { MX, EM } },
5579     { "pmulhrsw",       { MX, EM } },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     /* 10 */
5585     { PREFIX_TABLE (PREFIX_0F3810) },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { PREFIX_TABLE (PREFIX_0F3814) },
5590     { PREFIX_TABLE (PREFIX_0F3815) },
5591     { Bad_Opcode },
5592     { PREFIX_TABLE (PREFIX_0F3817) },
5593     /* 18 */
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { "pabsb",          { MX, EM } },
5599     { "pabsw",          { MX, EM } },
5600     { "pabsd",          { MX, EM } },
5601     { Bad_Opcode },
5602     /* 20 */
5603     { PREFIX_TABLE (PREFIX_0F3820) },
5604     { PREFIX_TABLE (PREFIX_0F3821) },
5605     { PREFIX_TABLE (PREFIX_0F3822) },
5606     { PREFIX_TABLE (PREFIX_0F3823) },
5607     { PREFIX_TABLE (PREFIX_0F3824) },
5608     { PREFIX_TABLE (PREFIX_0F3825) },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     /* 28 */
5612     { PREFIX_TABLE (PREFIX_0F3828) },
5613     { PREFIX_TABLE (PREFIX_0F3829) },
5614     { PREFIX_TABLE (PREFIX_0F382A) },
5615     { PREFIX_TABLE (PREFIX_0F382B) },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     /* 30 */
5621     { PREFIX_TABLE (PREFIX_0F3830) },
5622     { PREFIX_TABLE (PREFIX_0F3831) },
5623     { PREFIX_TABLE (PREFIX_0F3832) },
5624     { PREFIX_TABLE (PREFIX_0F3833) },
5625     { PREFIX_TABLE (PREFIX_0F3834) },
5626     { PREFIX_TABLE (PREFIX_0F3835) },
5627     { Bad_Opcode },
5628     { PREFIX_TABLE (PREFIX_0F3837) },
5629     /* 38 */
5630     { PREFIX_TABLE (PREFIX_0F3838) },
5631     { PREFIX_TABLE (PREFIX_0F3839) },
5632     { PREFIX_TABLE (PREFIX_0F383A) },
5633     { PREFIX_TABLE (PREFIX_0F383B) },
5634     { PREFIX_TABLE (PREFIX_0F383C) },
5635     { PREFIX_TABLE (PREFIX_0F383D) },
5636     { PREFIX_TABLE (PREFIX_0F383E) },
5637     { PREFIX_TABLE (PREFIX_0F383F) },
5638     /* 40 */
5639     { PREFIX_TABLE (PREFIX_0F3840) },
5640     { PREFIX_TABLE (PREFIX_0F3841) },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     /* 48 */
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     /* 50 */
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     /* 58 */
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     /* 60 */
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     /* 68 */
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     /* 70 */
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     /* 78 */
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     /* 80 */
5711     { PREFIX_TABLE (PREFIX_0F3880) },
5712     { PREFIX_TABLE (PREFIX_0F3881) },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     /* 88 */
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     /* 90 */
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     /* 98 */
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     /* a0 */
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     /* a8 */
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     /* b0 */
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     /* b8 */
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     /* c0 */
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     /* c8 */
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     /* d0 */
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     /* d8 */
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { PREFIX_TABLE (PREFIX_0F38DB) },
5814     { PREFIX_TABLE (PREFIX_0F38DC) },
5815     { PREFIX_TABLE (PREFIX_0F38DD) },
5816     { PREFIX_TABLE (PREFIX_0F38DE) },
5817     { PREFIX_TABLE (PREFIX_0F38DF) },
5818     /* e0 */
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     /* e8 */
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     /* f0 */
5837     { PREFIX_TABLE (PREFIX_0F38F0) },
5838     { PREFIX_TABLE (PREFIX_0F38F1) },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     /* f8 */
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854   },
5855   /* THREE_BYTE_0F3A */
5856   {
5857     /* 00 */
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     /* 08 */
5867     { PREFIX_TABLE (PREFIX_0F3A08) },
5868     { PREFIX_TABLE (PREFIX_0F3A09) },
5869     { PREFIX_TABLE (PREFIX_0F3A0A) },
5870     { PREFIX_TABLE (PREFIX_0F3A0B) },
5871     { PREFIX_TABLE (PREFIX_0F3A0C) },
5872     { PREFIX_TABLE (PREFIX_0F3A0D) },
5873     { PREFIX_TABLE (PREFIX_0F3A0E) },
5874     { "palignr",        { MX, EM, Ib } },
5875     /* 10 */
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { PREFIX_TABLE (PREFIX_0F3A14) },
5881     { PREFIX_TABLE (PREFIX_0F3A15) },
5882     { PREFIX_TABLE (PREFIX_0F3A16) },
5883     { PREFIX_TABLE (PREFIX_0F3A17) },
5884     /* 18 */
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     /* 20 */
5894     { PREFIX_TABLE (PREFIX_0F3A20) },
5895     { PREFIX_TABLE (PREFIX_0F3A21) },
5896     { PREFIX_TABLE (PREFIX_0F3A22) },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     /* 28 */
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     /* 30 */
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     /* 38 */
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     /* 40 */
5930     { PREFIX_TABLE (PREFIX_0F3A40) },
5931     { PREFIX_TABLE (PREFIX_0F3A41) },
5932     { PREFIX_TABLE (PREFIX_0F3A42) },
5933     { Bad_Opcode },
5934     { PREFIX_TABLE (PREFIX_0F3A44) },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     /* 48 */
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     /* 50 */
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     /* 58 */
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     /* 60 */
5966     { PREFIX_TABLE (PREFIX_0F3A60) },
5967     { PREFIX_TABLE (PREFIX_0F3A61) },
5968     { PREFIX_TABLE (PREFIX_0F3A62) },
5969     { PREFIX_TABLE (PREFIX_0F3A63) },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     /* 68 */
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     /* 70 */
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     /* 78 */
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     /* 80 */
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     /* 88 */
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     /* 90 */
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     /* 98 */
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     /* a0 */
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     /* a8 */
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     /* b0 */
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     /* b8 */
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     /* c0 */
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     /* c8 */
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     /* d0 */
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     /* d8 */
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { PREFIX_TABLE (PREFIX_0F3ADF) },
6109     /* e0 */
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     /* e8 */
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     /* f0 */
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     /* f8 */
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145   },
6146
6147   /* THREE_BYTE_0F7A */
6148   {
6149     /* 00 */
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     /* 08 */
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     /* 10 */
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     /* 18 */
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     /* 20 */
6186     { "ptest",          { XX } },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     /* 28 */
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     /* 30 */
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     /* 38 */
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     /* 40 */
6222     { Bad_Opcode },
6223     { "phaddbw",        { XM, EXq } },
6224     { "phaddbd",        { XM, EXq } },
6225     { "phaddbq",        { XM, EXq } },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "phaddwd",        { XM, EXq } },
6229     { "phaddwq",        { XM, EXq } },
6230     /* 48 */
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "phadddq",        { XM, EXq } },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     /* 50 */
6240     { Bad_Opcode },
6241     { "phaddubw",       { XM, EXq } },
6242     { "phaddubd",       { XM, EXq } },
6243     { "phaddubq",       { XM, EXq } },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { "phadduwd",       { XM, EXq } },
6247     { "phadduwq",       { XM, EXq } },
6248     /* 58 */
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { "phaddudq",       { XM, EXq } },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     /* 60 */
6258     { Bad_Opcode },
6259     { "phsubbw",        { XM, EXq } },
6260     { "phsubbd",        { XM, EXq } },
6261     { "phsubbq",        { XM, EXq } },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     /* 68 */
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     /* 70 */
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     /* 78 */
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     /* 80 */
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     /* 88 */
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     /* 90 */
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     /* 98 */
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     /* a0 */
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     /* a8 */
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     /* b0 */
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     /* b8 */
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     /* c0 */
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     /* c8 */
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     /* d0 */
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     /* d8 */
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     /* e0 */
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     /* e8 */
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     /* f0 */
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     /* f8 */
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437   },
6438 };
6439
6440 static const struct dis386 xop_table[][256] = {
6441   /* XOP_08 */
6442   {
6443     /* 00 */
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     /* 08 */
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     /* 10 */
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     /* 18 */
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     /* 20 */
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     /* 28 */
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     /* 30 */
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     /* 38 */
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     /* 40 */
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     /* 48 */
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     /* 50 */
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     /* 58 */
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     /* 60 */
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     /* 68 */
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     /* 70 */
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     /* 78 */
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     /* 80 */
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6594     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6595     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6596     /* 88 */
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6604     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6605     /* 90 */
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6612     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6613     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6614     /* 98 */
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6622     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6623     /* a0 */
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6627     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6631     { Bad_Opcode },
6632     /* a8 */
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     /* b0 */
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6649     { Bad_Opcode },
6650     /* b8 */
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     /* c0 */
6660     { "vprotb",         { XM, Vex_2src_1, Ib } },
6661     { "vprotw",         { XM, Vex_2src_1, Ib } },
6662     { "vprotd",         { XM, Vex_2src_1, Ib } },
6663     { "vprotq",         { XM, Vex_2src_1, Ib } },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     /* c8 */
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6674     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6675     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6676     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6677     /* d0 */
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     /* d8 */
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     /* e0 */
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     /* e8 */
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6710     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6711     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6712     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6713     /* f0 */
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     /* f8 */
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731   },
6732   /* XOP_09 */
6733   {
6734     /* 00 */
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     /* 08 */
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     /* 10 */
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { REG_TABLE (REG_XOP_LWPCB) },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     /* 18 */
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     /* 20 */
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     /* 28 */
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     /* 30 */
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     /* 38 */
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     /* 40 */
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     /* 48 */
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     /* 50 */
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     /* 58 */
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     /* 60 */
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     /* 68 */
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     /* 70 */
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     /* 78 */
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     /* 80 */
6879     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
6880     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
6881     { "vfrczss",        { XM, EXd } },
6882     { "vfrczsd",        { XM, EXq } },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     /* 88 */
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     /* 90 */
6897     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6898     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6899     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6900     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6901     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6902     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6903     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6904     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6905     /* 98 */
6906     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6907     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6908     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6909     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     /* a0 */
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     /* a8 */
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     /* b0 */
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     /* b8 */
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     /* c0 */
6951     { Bad_Opcode },
6952     { "vphaddbw",       { XM, EXxmm } },
6953     { "vphaddbd",       { XM, EXxmm } },
6954     { "vphaddbq",       { XM, EXxmm } },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { "vphaddwd",       { XM, EXxmm } },
6958     { "vphaddwq",       { XM, EXxmm } },
6959     /* c8 */
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { "vphadddq",       { XM, EXxmm } },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     /* d0 */
6969     { Bad_Opcode },
6970     { "vphaddubw",      { XM, EXxmm } },
6971     { "vphaddubd",      { XM, EXxmm } },
6972     { "vphaddubq",      { XM, EXxmm } },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { "vphadduwd",      { XM, EXxmm } },
6976     { "vphadduwq",      { XM, EXxmm } },
6977     /* d8 */
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { "vphaddudq",      { XM, EXxmm } },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     /* e0 */
6987     { Bad_Opcode },
6988     { "vphsubbw",       { XM, EXxmm } },
6989     { "vphsubwd",       { XM, EXxmm } },
6990     { "vphsubdq",       { XM, EXxmm } },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     /* e8 */
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     /* f0 */
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     /* f8 */
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022   },
7023   /* XOP_0A */
7024   {
7025     /* 00 */
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* 08 */
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* 10 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { REG_TABLE (REG_XOP_LWP) },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* 18 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* 20 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* 28 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* 30 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* 38 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* 40 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* 48 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* 50 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* 58 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* 60 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     /* 68 */
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     /* 70 */
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     /* 78 */
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     /* 80 */
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     /* 88 */
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     /* 90 */
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     /* 98 */
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     /* a0 */
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     /* a8 */
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     /* b0 */
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     /* b8 */
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* c0 */
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     /* c8 */
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     /* d0 */
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     /* d8 */
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     /* e0 */
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     /* e8 */
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     /* f0 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* f8 */
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313   },
7314 };
7315
7316 static const struct dis386 vex_table[][256] = {
7317   /* VEX_0F */
7318   {
7319     /* 00 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* 08 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* 10 */
7338     { PREFIX_TABLE (PREFIX_VEX_0F10) },
7339     { PREFIX_TABLE (PREFIX_VEX_0F11) },
7340     { PREFIX_TABLE (PREFIX_VEX_0F12) },
7341     { MOD_TABLE (MOD_VEX_0F13) },
7342     { VEX_W_TABLE (VEX_W_0F14) },
7343     { VEX_W_TABLE (VEX_W_0F15) },
7344     { PREFIX_TABLE (PREFIX_VEX_0F16) },
7345     { MOD_TABLE (MOD_VEX_0F17) },
7346     /* 18 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* 20 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* 28 */
7365     { VEX_W_TABLE (VEX_W_0F28) },
7366     { VEX_W_TABLE (VEX_W_0F29) },
7367     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7368     { MOD_TABLE (MOD_VEX_0F2B) },
7369     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7370     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7371     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7372     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7373     /* 30 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* 38 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* 40 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* 48 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* 50 */
7410     { MOD_TABLE (MOD_VEX_0F50) },
7411     { PREFIX_TABLE (PREFIX_VEX_0F51) },
7412     { PREFIX_TABLE (PREFIX_VEX_0F52) },
7413     { PREFIX_TABLE (PREFIX_VEX_0F53) },
7414     { "vandpX",         { XM, Vex, EXx } },
7415     { "vandnpX",        { XM, Vex, EXx } },
7416     { "vorpX",          { XM, Vex, EXx } },
7417     { "vxorpX",         { XM, Vex, EXx } },
7418     /* 58 */
7419     { PREFIX_TABLE (PREFIX_VEX_0F58) },
7420     { PREFIX_TABLE (PREFIX_VEX_0F59) },
7421     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7422     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7423     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7424     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7425     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7426     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7427     /* 60 */
7428     { PREFIX_TABLE (PREFIX_VEX_0F60) },
7429     { PREFIX_TABLE (PREFIX_VEX_0F61) },
7430     { PREFIX_TABLE (PREFIX_VEX_0F62) },
7431     { PREFIX_TABLE (PREFIX_VEX_0F63) },
7432     { PREFIX_TABLE (PREFIX_VEX_0F64) },
7433     { PREFIX_TABLE (PREFIX_VEX_0F65) },
7434     { PREFIX_TABLE (PREFIX_VEX_0F66) },
7435     { PREFIX_TABLE (PREFIX_VEX_0F67) },
7436     /* 68 */
7437     { PREFIX_TABLE (PREFIX_VEX_0F68) },
7438     { PREFIX_TABLE (PREFIX_VEX_0F69) },
7439     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7440     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7441     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7442     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7443     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7444     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7445     /* 70 */
7446     { PREFIX_TABLE (PREFIX_VEX_0F70) },
7447     { REG_TABLE (REG_VEX_0F71) },
7448     { REG_TABLE (REG_VEX_0F72) },
7449     { REG_TABLE (REG_VEX_0F73) },
7450     { PREFIX_TABLE (PREFIX_VEX_0F74) },
7451     { PREFIX_TABLE (PREFIX_VEX_0F75) },
7452     { PREFIX_TABLE (PREFIX_VEX_0F76) },
7453     { PREFIX_TABLE (PREFIX_VEX_0F77) },
7454     /* 78 */
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7460     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7461     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7462     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7463     /* 80 */
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     /* 88 */
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     /* 90 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* 98 */
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     /* a0 */
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     /* a8 */
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { REG_TABLE (REG_VEX_0FAE) },
7516     { Bad_Opcode },
7517     /* b0 */
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     /* b8 */
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     /* c0 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7539     { Bad_Opcode },
7540     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7541     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7542     { "vshufpX",        { XM, Vex, EXx, Ib } },
7543     { Bad_Opcode },
7544     /* c8 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* d0 */
7554     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7555     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7556     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7557     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7558     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7559     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7560     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7561     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7562     /* d8 */
7563     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7564     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7565     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7566     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7567     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7568     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7569     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7570     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7571     /* e0 */
7572     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7573     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7574     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7575     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7576     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7577     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7578     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7579     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7580     /* e8 */
7581     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7582     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7583     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7584     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7585     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7586     { PREFIX_TABLE (PREFIX_VEX_0FED) },
7587     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7588     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7589     /* f0 */
7590     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7591     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7592     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7593     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7594     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7595     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7596     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7597     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7598     /* f8 */
7599     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7600     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7601     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7602     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7603     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7604     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7605     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7606     { Bad_Opcode },
7607   },
7608   /* VEX_0F38 */
7609   {
7610     /* 00 */
7611     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7612     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7613     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7614     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7615     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7616     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7617     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7618     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7619     /* 08 */
7620     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7621     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7622     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7623     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7624     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7625     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7626     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7627     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7628     /* 10 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7637     /* 18 */
7638     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7639     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7640     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7641     { Bad_Opcode },
7642     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7643     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7644     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7645     { Bad_Opcode },
7646     /* 20 */
7647     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7648     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7649     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7650     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7651     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7652     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     /* 28 */
7656     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7657     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7658     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7659     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7660     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7661     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7662     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7663     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7664     /* 30 */
7665     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7666     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7667     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7668     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7669     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7670     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7671     { Bad_Opcode },
7672     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7673     /* 38 */
7674     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7675     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7676     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7677     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7678     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7679     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7680     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7681     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7682     /* 40 */
7683     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7684     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* 48 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* 50 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     /* 58 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     /* 60 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     /* 68 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     /* 70 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     /* 78 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* 80 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     /* 88 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     /* 90 */
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
7780     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
7781     /* 98 */
7782     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
7783     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
7784     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
7785     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
7786     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
7787     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
7788     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
7789     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
7790     /* a0 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
7798     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
7799     /* a8 */
7800     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
7801     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
7802     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
7803     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
7804     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
7805     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
7806     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
7807     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
7808     /* b0 */
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
7816     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
7817     /* b8 */
7818     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
7819     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
7820     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
7821     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
7822     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
7823     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
7824     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
7825     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
7826     /* c0 */
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     /* c8 */
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     /* d0 */
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     /* d8 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
7858     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
7859     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
7860     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
7861     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
7862     /* e0 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     /* e8 */
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     /* f0 */
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
7884     { REG_TABLE (REG_VEX_0F38F3) },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
7889     /* f8 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898   },
7899   /* VEX_0F3A */
7900   {
7901     /* 00 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
7907     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
7908     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
7909     { Bad_Opcode },
7910     /* 08 */
7911     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
7912     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
7913     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
7914     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
7915     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
7916     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
7917     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
7918     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
7919     /* 10 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
7925     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
7926     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
7927     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
7928     /* 18 */
7929     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
7930     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     /* 20 */
7938     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
7939     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
7940     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* 28 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* 30 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* 38 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* 40 */
7974     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
7975     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
7976     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
7977     { Bad_Opcode },
7978     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* 48 */
7983     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
7984     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
7985     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
7986     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
7987     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* 50 */
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* 58 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8006     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8007     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8008     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8009     /* 60 */
8010     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8011     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8012     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8013     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     /* 68 */
8019     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8020     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8021     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8022     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8023     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8024     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8025     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8026     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8027     /* 70 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     /* 78 */
8037     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8038     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8039     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8040     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8041     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8042     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8043     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8044     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8045     /* 80 */
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     /* 88 */
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     /* 90 */
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     /* 98 */
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     /* a0 */
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     /* a8 */
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     /* b0 */
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     /* b8 */
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     /* c0 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* c8 */
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     /* d0 */
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     /* d8 */
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8153     /* e0 */
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     /* e8 */
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     /* f0 */
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     /* f8 */
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189   },
8190 };
8191
8192 static const struct dis386 vex_len_table[][2] = {
8193   /* VEX_LEN_0F10_P_1 */
8194   {
8195     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8196     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8197   },
8198
8199   /* VEX_LEN_0F10_P_3 */
8200   {
8201     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8202     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8203   },
8204
8205   /* VEX_LEN_0F11_P_1 */
8206   {
8207     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8208     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8209   },
8210
8211   /* VEX_LEN_0F11_P_3 */
8212   {
8213     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8214     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8215   },
8216
8217   /* VEX_LEN_0F12_P_0_M_0 */
8218   {
8219     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8220   },
8221
8222   /* VEX_LEN_0F12_P_0_M_1 */
8223   {
8224     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8225   },
8226
8227   /* VEX_LEN_0F12_P_2 */
8228   {
8229     { VEX_W_TABLE (VEX_W_0F12_P_2) },
8230   },
8231
8232   /* VEX_LEN_0F13_M_0 */
8233   {
8234     { VEX_W_TABLE (VEX_W_0F13_M_0) },
8235   },
8236
8237   /* VEX_LEN_0F16_P_0_M_0 */
8238   {
8239     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8240   },
8241
8242   /* VEX_LEN_0F16_P_0_M_1 */
8243   {
8244     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8245   },
8246
8247   /* VEX_LEN_0F16_P_2 */
8248   {
8249     { VEX_W_TABLE (VEX_W_0F16_P_2) },
8250   },
8251
8252   /* VEX_LEN_0F17_M_0 */
8253   {
8254     { VEX_W_TABLE (VEX_W_0F17_M_0) },
8255   },
8256
8257   /* VEX_LEN_0F2A_P_1 */
8258   {
8259     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8260     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8261   },
8262
8263   /* VEX_LEN_0F2A_P_3 */
8264   {
8265     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8266     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8267   },
8268
8269   /* VEX_LEN_0F2C_P_1 */
8270   {
8271     { "vcvttss2siY",    { Gv, EXdScalar } },
8272     { "vcvttss2siY",    { Gv, EXdScalar } },
8273   },
8274
8275   /* VEX_LEN_0F2C_P_3 */
8276   {
8277     { "vcvttsd2siY",    { Gv, EXqScalar } },
8278     { "vcvttsd2siY",    { Gv, EXqScalar } },
8279   },
8280
8281   /* VEX_LEN_0F2D_P_1 */
8282   {
8283     { "vcvtss2siY",     { Gv, EXdScalar } },
8284     { "vcvtss2siY",     { Gv, EXdScalar } },
8285   },
8286
8287   /* VEX_LEN_0F2D_P_3 */
8288   {
8289     { "vcvtsd2siY",     { Gv, EXqScalar } },
8290     { "vcvtsd2siY",     { Gv, EXqScalar } },
8291   },
8292
8293   /* VEX_LEN_0F2E_P_0 */
8294   {
8295     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8296     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8297   },
8298
8299   /* VEX_LEN_0F2E_P_2 */
8300   {
8301     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8302     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8303   },
8304
8305   /* VEX_LEN_0F2F_P_0 */
8306   {
8307     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8308     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8309   },
8310
8311   /* VEX_LEN_0F2F_P_2 */
8312   {
8313     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8314     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8315   },
8316
8317   /* VEX_LEN_0F51_P_1 */
8318   {
8319     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8320     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8321   },
8322
8323   /* VEX_LEN_0F51_P_3 */
8324   {
8325     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8326     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8327   },
8328
8329   /* VEX_LEN_0F52_P_1 */
8330   {
8331     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8332     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8333   },
8334
8335   /* VEX_LEN_0F53_P_1 */
8336   {
8337     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8338     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8339   },
8340
8341   /* VEX_LEN_0F58_P_1 */
8342   {
8343     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8344     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8345   },
8346
8347   /* VEX_LEN_0F58_P_3 */
8348   {
8349     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8350     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8351   },
8352
8353   /* VEX_LEN_0F59_P_1 */
8354   {
8355     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8356     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8357   },
8358
8359   /* VEX_LEN_0F59_P_3 */
8360   {
8361     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8362     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8363   },
8364
8365   /* VEX_LEN_0F5A_P_1 */
8366   {
8367     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8368     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8369   },
8370
8371   /* VEX_LEN_0F5A_P_3 */
8372   {
8373     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8374     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8375   },
8376
8377   /* VEX_LEN_0F5C_P_1 */
8378   {
8379     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8380     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8381   },
8382
8383   /* VEX_LEN_0F5C_P_3 */
8384   {
8385     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8386     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8387   },
8388
8389   /* VEX_LEN_0F5D_P_1 */
8390   {
8391     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8392     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8393   },
8394
8395   /* VEX_LEN_0F5D_P_3 */
8396   {
8397     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8398     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8399   },
8400
8401   /* VEX_LEN_0F5E_P_1 */
8402   {
8403     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8404     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8405   },
8406
8407   /* VEX_LEN_0F5E_P_3 */
8408   {
8409     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8410     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8411   },
8412
8413   /* VEX_LEN_0F5F_P_1 */
8414   {
8415     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8416     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8417   },
8418
8419   /* VEX_LEN_0F5F_P_3 */
8420   {
8421     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8422     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8423   },
8424
8425   /* VEX_LEN_0F60_P_2 */
8426   {
8427     { VEX_W_TABLE (VEX_W_0F60_P_2) },
8428   },
8429
8430   /* VEX_LEN_0F61_P_2 */
8431   {
8432     { VEX_W_TABLE (VEX_W_0F61_P_2) },
8433   },
8434
8435   /* VEX_LEN_0F62_P_2 */
8436   {
8437     { VEX_W_TABLE (VEX_W_0F62_P_2) },
8438   },
8439
8440   /* VEX_LEN_0F63_P_2 */
8441   {
8442     { VEX_W_TABLE (VEX_W_0F63_P_2) },
8443   },
8444
8445   /* VEX_LEN_0F64_P_2 */
8446   {
8447     { VEX_W_TABLE (VEX_W_0F64_P_2) },
8448   },
8449
8450   /* VEX_LEN_0F65_P_2 */
8451   {
8452     { VEX_W_TABLE (VEX_W_0F65_P_2) },
8453   },
8454
8455   /* VEX_LEN_0F66_P_2 */
8456   {
8457     { VEX_W_TABLE (VEX_W_0F66_P_2) },
8458   },
8459
8460   /* VEX_LEN_0F67_P_2 */
8461   {
8462     { VEX_W_TABLE (VEX_W_0F67_P_2) },
8463   },
8464
8465   /* VEX_LEN_0F68_P_2 */
8466   {
8467     { VEX_W_TABLE (VEX_W_0F68_P_2) },
8468   },
8469
8470   /* VEX_LEN_0F69_P_2 */
8471   {
8472     { VEX_W_TABLE (VEX_W_0F69_P_2) },
8473   },
8474
8475   /* VEX_LEN_0F6A_P_2 */
8476   {
8477     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
8478   },
8479
8480   /* VEX_LEN_0F6B_P_2 */
8481   {
8482     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
8483   },
8484
8485   /* VEX_LEN_0F6C_P_2 */
8486   {
8487     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
8488   },
8489
8490   /* VEX_LEN_0F6D_P_2 */
8491   {
8492     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
8493   },
8494
8495   /* VEX_LEN_0F6E_P_2 */
8496   {
8497     { "vmovK",          { XMScalar, Edq } },
8498     { "vmovK",          { XMScalar, Edq } },
8499   },
8500
8501   /* VEX_LEN_0F70_P_1 */
8502   {
8503     { VEX_W_TABLE (VEX_W_0F70_P_1) },
8504   },
8505
8506   /* VEX_LEN_0F70_P_2 */
8507   {
8508     { VEX_W_TABLE (VEX_W_0F70_P_2) },
8509   },
8510
8511   /* VEX_LEN_0F70_P_3 */
8512   {
8513     { VEX_W_TABLE (VEX_W_0F70_P_3) },
8514   },
8515
8516   /* VEX_LEN_0F71_R_2_P_2 */
8517   {
8518     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
8519   },
8520
8521   /* VEX_LEN_0F71_R_4_P_2 */
8522   {
8523     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
8524   },
8525
8526   /* VEX_LEN_0F71_R_6_P_2 */
8527   {
8528     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
8529   },
8530
8531   /* VEX_LEN_0F72_R_2_P_2 */
8532   {
8533     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
8534   },
8535
8536   /* VEX_LEN_0F72_R_4_P_2 */
8537   {
8538     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
8539   },
8540
8541   /* VEX_LEN_0F72_R_6_P_2 */
8542   {
8543     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
8544   },
8545
8546   /* VEX_LEN_0F73_R_2_P_2 */
8547   {
8548     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
8549   },
8550
8551   /* VEX_LEN_0F73_R_3_P_2 */
8552   {
8553     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
8554   },
8555
8556   /* VEX_LEN_0F73_R_6_P_2 */
8557   {
8558     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
8559   },
8560
8561   /* VEX_LEN_0F73_R_7_P_2 */
8562   {
8563     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
8564   },
8565
8566   /* VEX_LEN_0F74_P_2 */
8567   {
8568     { VEX_W_TABLE (VEX_W_0F74_P_2) },
8569   },
8570
8571   /* VEX_LEN_0F75_P_2 */
8572   {
8573     { VEX_W_TABLE (VEX_W_0F75_P_2) },
8574   },
8575
8576   /* VEX_LEN_0F76_P_2 */
8577   {
8578     { VEX_W_TABLE (VEX_W_0F76_P_2) },
8579   },
8580
8581   /* VEX_LEN_0F7E_P_1 */
8582   {
8583     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8584     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8585   },
8586
8587   /* VEX_LEN_0F7E_P_2 */
8588   {
8589     { "vmovK",          { Edq, XMScalar } },
8590     { "vmovK",          { Edq, XMScalar } },
8591   },
8592
8593   /* VEX_LEN_0FAE_R_2_M_0 */
8594   {
8595     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8596   },
8597
8598   /* VEX_LEN_0FAE_R_3_M_0 */
8599   {
8600     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8601   },
8602
8603   /* VEX_LEN_0FC2_P_1 */
8604   {
8605     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8606     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8607   },
8608
8609   /* VEX_LEN_0FC2_P_3 */
8610   {
8611     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8612     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8613   },
8614
8615   /* VEX_LEN_0FC4_P_2 */
8616   {
8617     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8618   },
8619
8620   /* VEX_LEN_0FC5_P_2 */
8621   {
8622     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8623   },
8624
8625   /* VEX_LEN_0FD1_P_2 */
8626   {
8627     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
8628   },
8629
8630   /* VEX_LEN_0FD2_P_2 */
8631   {
8632     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
8633   },
8634
8635   /* VEX_LEN_0FD3_P_2 */
8636   {
8637     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
8638   },
8639
8640   /* VEX_LEN_0FD4_P_2 */
8641   {
8642     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
8643   },
8644
8645   /* VEX_LEN_0FD5_P_2 */
8646   {
8647     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
8648   },
8649
8650   /* VEX_LEN_0FD6_P_2 */
8651   {
8652     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8653     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8654   },
8655
8656   /* VEX_LEN_0FD7_P_2_M_1 */
8657   {
8658     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
8659   },
8660
8661   /* VEX_LEN_0FD8_P_2 */
8662   {
8663     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
8664   },
8665
8666   /* VEX_LEN_0FD9_P_2 */
8667   {
8668     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
8669   },
8670
8671   /* VEX_LEN_0FDA_P_2 */
8672   {
8673     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
8674   },
8675
8676   /* VEX_LEN_0FDB_P_2 */
8677   {
8678     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
8679   },
8680
8681   /* VEX_LEN_0FDC_P_2 */
8682   {
8683     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
8684   },
8685
8686   /* VEX_LEN_0FDD_P_2 */
8687   {
8688     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
8689   },
8690
8691   /* VEX_LEN_0FDE_P_2 */
8692   {
8693     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
8694   },
8695
8696   /* VEX_LEN_0FDF_P_2 */
8697   {
8698     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
8699   },
8700
8701   /* VEX_LEN_0FE0_P_2 */
8702   {
8703     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
8704   },
8705
8706   /* VEX_LEN_0FE1_P_2 */
8707   {
8708     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
8709   },
8710
8711   /* VEX_LEN_0FE2_P_2 */
8712   {
8713     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
8714   },
8715
8716   /* VEX_LEN_0FE3_P_2 */
8717   {
8718     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
8719   },
8720
8721   /* VEX_LEN_0FE4_P_2 */
8722   {
8723     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
8724   },
8725
8726   /* VEX_LEN_0FE5_P_2 */
8727   {
8728     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
8729   },
8730
8731   /* VEX_LEN_0FE8_P_2 */
8732   {
8733     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
8734   },
8735
8736   /* VEX_LEN_0FE9_P_2 */
8737   {
8738     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
8739   },
8740
8741   /* VEX_LEN_0FEA_P_2 */
8742   {
8743     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
8744   },
8745
8746   /* VEX_LEN_0FEB_P_2 */
8747   {
8748     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
8749   },
8750
8751   /* VEX_LEN_0FEC_P_2 */
8752   {
8753     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
8754   },
8755
8756   /* VEX_LEN_0FED_P_2 */
8757   {
8758     { VEX_W_TABLE (VEX_W_0FED_P_2) },
8759   },
8760
8761   /* VEX_LEN_0FEE_P_2 */
8762   {
8763     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
8764   },
8765
8766   /* VEX_LEN_0FEF_P_2 */
8767   {
8768     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
8769   },
8770
8771   /* VEX_LEN_0FF1_P_2 */
8772   {
8773     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
8774   },
8775
8776   /* VEX_LEN_0FF2_P_2 */
8777   {
8778     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
8779   },
8780
8781   /* VEX_LEN_0FF3_P_2 */
8782   {
8783     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
8784   },
8785
8786   /* VEX_LEN_0FF4_P_2 */
8787   {
8788     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
8789   },
8790
8791   /* VEX_LEN_0FF5_P_2 */
8792   {
8793     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
8794   },
8795
8796   /* VEX_LEN_0FF6_P_2 */
8797   {
8798     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
8799   },
8800
8801   /* VEX_LEN_0FF7_P_2 */
8802   {
8803     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8804   },
8805
8806   /* VEX_LEN_0FF8_P_2 */
8807   {
8808     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
8809   },
8810
8811   /* VEX_LEN_0FF9_P_2 */
8812   {
8813     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
8814   },
8815
8816   /* VEX_LEN_0FFA_P_2 */
8817   {
8818     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
8819   },
8820
8821   /* VEX_LEN_0FFB_P_2 */
8822   {
8823     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
8824   },
8825
8826   /* VEX_LEN_0FFC_P_2 */
8827   {
8828     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
8829   },
8830
8831   /* VEX_LEN_0FFD_P_2 */
8832   {
8833     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
8834   },
8835
8836   /* VEX_LEN_0FFE_P_2 */
8837   {
8838     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
8839   },
8840
8841   /* VEX_LEN_0F3800_P_2 */
8842   {
8843     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
8844   },
8845
8846   /* VEX_LEN_0F3801_P_2 */
8847   {
8848     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
8849   },
8850
8851   /* VEX_LEN_0F3802_P_2 */
8852   {
8853     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
8854   },
8855
8856   /* VEX_LEN_0F3803_P_2 */
8857   {
8858     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
8859   },
8860
8861   /* VEX_LEN_0F3804_P_2 */
8862   {
8863     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
8864   },
8865
8866   /* VEX_LEN_0F3805_P_2 */
8867   {
8868     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
8869   },
8870
8871   /* VEX_LEN_0F3806_P_2 */
8872   {
8873     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
8874   },
8875
8876   /* VEX_LEN_0F3807_P_2 */
8877   {
8878     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
8879   },
8880
8881   /* VEX_LEN_0F3808_P_2 */
8882   {
8883     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
8884   },
8885
8886   /* VEX_LEN_0F3809_P_2 */
8887   {
8888     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
8889   },
8890
8891   /* VEX_LEN_0F380A_P_2 */
8892   {
8893     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
8894   },
8895
8896   /* VEX_LEN_0F380B_P_2 */
8897   {
8898     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
8899   },
8900
8901   /* VEX_LEN_0F3819_P_2_M_0 */
8902   {
8903     { Bad_Opcode },
8904     { VEX_W_TABLE (VEX_W_0F3819_P_2_M_0) },
8905   },
8906
8907   /* VEX_LEN_0F381A_P_2_M_0 */
8908   {
8909     { Bad_Opcode },
8910     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8911   },
8912
8913   /* VEX_LEN_0F381C_P_2 */
8914   {
8915     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
8916   },
8917
8918   /* VEX_LEN_0F381D_P_2 */
8919   {
8920     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
8921   },
8922
8923   /* VEX_LEN_0F381E_P_2 */
8924   {
8925     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
8926   },
8927
8928   /* VEX_LEN_0F3820_P_2 */
8929   {
8930     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
8931   },
8932
8933   /* VEX_LEN_0F3821_P_2 */
8934   {
8935     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
8936   },
8937
8938   /* VEX_LEN_0F3822_P_2 */
8939   {
8940     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
8941   },
8942
8943   /* VEX_LEN_0F3823_P_2 */
8944   {
8945     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
8946   },
8947
8948   /* VEX_LEN_0F3824_P_2 */
8949   {
8950     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
8951   },
8952
8953   /* VEX_LEN_0F3825_P_2 */
8954   {
8955     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
8956   },
8957
8958   /* VEX_LEN_0F3828_P_2 */
8959   {
8960     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
8961   },
8962
8963   /* VEX_LEN_0F3829_P_2 */
8964   {
8965     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
8966   },
8967
8968   /* VEX_LEN_0F382A_P_2_M_0 */
8969   {
8970     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
8971   },
8972
8973   /* VEX_LEN_0F382B_P_2 */
8974   {
8975     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
8976   },
8977
8978   /* VEX_LEN_0F3830_P_2 */
8979   {
8980     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
8981   },
8982
8983   /* VEX_LEN_0F3831_P_2 */
8984   {
8985     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
8986   },
8987
8988   /* VEX_LEN_0F3832_P_2 */
8989   {
8990     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
8991   },
8992
8993   /* VEX_LEN_0F3833_P_2 */
8994   {
8995     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
8996   },
8997
8998   /* VEX_LEN_0F3834_P_2 */
8999   {
9000     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
9001   },
9002
9003   /* VEX_LEN_0F3835_P_2 */
9004   {
9005     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
9006   },
9007
9008   /* VEX_LEN_0F3837_P_2 */
9009   {
9010     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
9011   },
9012
9013   /* VEX_LEN_0F3838_P_2 */
9014   {
9015     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
9016   },
9017
9018   /* VEX_LEN_0F3839_P_2 */
9019   {
9020     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
9021   },
9022
9023   /* VEX_LEN_0F383A_P_2 */
9024   {
9025     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
9026   },
9027
9028   /* VEX_LEN_0F383B_P_2 */
9029   {
9030     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
9031   },
9032
9033   /* VEX_LEN_0F383C_P_2 */
9034   {
9035     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
9036   },
9037
9038   /* VEX_LEN_0F383D_P_2 */
9039   {
9040     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
9041   },
9042
9043   /* VEX_LEN_0F383E_P_2 */
9044   {
9045     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
9046   },
9047
9048   /* VEX_LEN_0F383F_P_2 */
9049   {
9050     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
9051   },
9052
9053   /* VEX_LEN_0F3840_P_2 */
9054   {
9055     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
9056   },
9057
9058   /* VEX_LEN_0F3841_P_2 */
9059   {
9060     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9061   },
9062
9063   /* VEX_LEN_0F38DB_P_2 */
9064   {
9065     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9066   },
9067
9068   /* VEX_LEN_0F38DC_P_2 */
9069   {
9070     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9071   },
9072
9073   /* VEX_LEN_0F38DD_P_2 */
9074   {
9075     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9076   },
9077
9078   /* VEX_LEN_0F38DE_P_2 */
9079   {
9080     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9081   },
9082
9083   /* VEX_LEN_0F38DF_P_2 */
9084   {
9085     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9086   },
9087
9088   /* VEX_LEN_0F38F2_P_0 */
9089   {
9090     { "andnS",          { Gdq, VexGdq, Edq } },
9091   },
9092
9093   /* VEX_LEN_0F38F3_R_1_P_0 */
9094   {
9095     { "blsrS",          { VexGdq, Edq } },
9096   },
9097
9098   /* VEX_LEN_0F38F3_R_2_P_0 */
9099   {
9100     { "blsmskS",        { VexGdq, Edq } },
9101   },
9102
9103   /* VEX_LEN_0F38F3_R_3_P_0 */
9104   {
9105     { "blsiS",          { VexGdq, Edq } },
9106   },
9107
9108   /* VEX_LEN_0F38F7_P_0 */
9109   {
9110     { "bextrS",         { Gdq, Edq, VexGdq } },
9111   },
9112
9113   /* VEX_LEN_0F3A06_P_2 */
9114   {
9115     { Bad_Opcode },
9116     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9117   },
9118
9119   /* VEX_LEN_0F3A0A_P_2 */
9120   {
9121     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9122     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9123   },
9124
9125   /* VEX_LEN_0F3A0B_P_2 */
9126   {
9127     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9128     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9129   },
9130
9131   /* VEX_LEN_0F3A0E_P_2 */
9132   {
9133     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
9134   },
9135
9136   /* VEX_LEN_0F3A0F_P_2 */
9137   {
9138     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
9139   },
9140
9141   /* VEX_LEN_0F3A14_P_2 */
9142   {
9143     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9144   },
9145
9146   /* VEX_LEN_0F3A15_P_2 */
9147   {
9148     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9149   },
9150
9151   /* VEX_LEN_0F3A16_P_2  */
9152   {
9153     { "vpextrK",        { Edq, XM, Ib } },
9154   },
9155
9156   /* VEX_LEN_0F3A17_P_2 */
9157   {
9158     { "vextractps",     { Edqd, XM, Ib } },
9159   },
9160
9161   /* VEX_LEN_0F3A18_P_2 */
9162   {
9163     { Bad_Opcode },
9164     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9165   },
9166
9167   /* VEX_LEN_0F3A19_P_2 */
9168   {
9169     { Bad_Opcode },
9170     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9171   },
9172
9173   /* VEX_LEN_0F3A20_P_2 */
9174   {
9175     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9176   },
9177
9178   /* VEX_LEN_0F3A21_P_2 */
9179   {
9180     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9181   },
9182
9183   /* VEX_LEN_0F3A22_P_2 */
9184   {
9185     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9186   },
9187
9188   /* VEX_LEN_0F3A41_P_2 */
9189   {
9190     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9191   },
9192
9193   /* VEX_LEN_0F3A42_P_2 */
9194   {
9195     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
9196   },
9197
9198   /* VEX_LEN_0F3A44_P_2 */
9199   {
9200     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9201   },
9202
9203   /* VEX_LEN_0F3A4C_P_2 */
9204   {
9205     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
9206   },
9207
9208   /* VEX_LEN_0F3A60_P_2 */
9209   {
9210     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9211   },
9212
9213   /* VEX_LEN_0F3A61_P_2 */
9214   {
9215     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9216   },
9217
9218   /* VEX_LEN_0F3A62_P_2 */
9219   {
9220     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9221   },
9222
9223   /* VEX_LEN_0F3A63_P_2 */
9224   {
9225     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9226   },
9227
9228   /* VEX_LEN_0F3A6A_P_2 */
9229   {
9230     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9231   },
9232
9233   /* VEX_LEN_0F3A6B_P_2 */
9234   {
9235     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9236   },
9237
9238   /* VEX_LEN_0F3A6E_P_2 */
9239   {
9240     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9241   },
9242
9243   /* VEX_LEN_0F3A6F_P_2 */
9244   {
9245     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9246   },
9247
9248   /* VEX_LEN_0F3A7A_P_2 */
9249   {
9250     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9251   },
9252
9253   /* VEX_LEN_0F3A7B_P_2 */
9254   {
9255     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9256   },
9257
9258   /* VEX_LEN_0F3A7E_P_2 */
9259   {
9260     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9261   },
9262
9263   /* VEX_LEN_0F3A7F_P_2 */
9264   {
9265     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9266   },
9267
9268   /* VEX_LEN_0F3ADF_P_2 */
9269   {
9270     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9271   },
9272
9273   /* VEX_LEN_0FXOP_09_80 */
9274   {
9275     { "vfrczps",        { XM, EXxmm } },
9276     { "vfrczps",        { XM, EXymmq } },
9277   },
9278
9279   /* VEX_LEN_0FXOP_09_81 */
9280   {
9281     { "vfrczpd",        { XM, EXxmm } },
9282     { "vfrczpd",        { XM, EXymmq } },
9283   },
9284 };
9285
9286 static const struct dis386 vex_w_table[][2] = {
9287   {
9288     /* VEX_W_0F10_P_0 */
9289     { "vmovups",        { XM, EXx } },
9290   },
9291   {
9292     /* VEX_W_0F10_P_1 */
9293     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9294   },
9295   {
9296     /* VEX_W_0F10_P_2 */
9297     { "vmovupd",        { XM, EXx } },
9298   },
9299   {
9300     /* VEX_W_0F10_P_3 */
9301     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9302   },
9303   {
9304     /* VEX_W_0F11_P_0 */
9305     { "vmovups",        { EXxS, XM } },
9306   },
9307   {
9308     /* VEX_W_0F11_P_1 */
9309     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9310   },
9311   {
9312     /* VEX_W_0F11_P_2 */
9313     { "vmovupd",        { EXxS, XM } },
9314   },
9315   {
9316     /* VEX_W_0F11_P_3 */
9317     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9318   },
9319   {
9320     /* VEX_W_0F12_P_0_M_0 */
9321     { "vmovlps",        { XM, Vex128, EXq } },
9322   },
9323   {
9324     /* VEX_W_0F12_P_0_M_1 */
9325     { "vmovhlps",       { XM, Vex128, EXq } },
9326   },
9327   {
9328     /* VEX_W_0F12_P_1 */
9329     { "vmovsldup",      { XM, EXx } },
9330   },
9331   {
9332     /* VEX_W_0F12_P_2 */
9333     { "vmovlpd",        { XM, Vex128, EXq } },
9334   },
9335   {
9336     /* VEX_W_0F12_P_3 */
9337     { "vmovddup",       { XM, EXymmq } },
9338   },
9339   {
9340     /* VEX_W_0F13_M_0 */
9341     { "vmovlpX",        { EXq, XM } },
9342   },
9343   {
9344     /* VEX_W_0F14 */
9345     { "vunpcklpX",      { XM, Vex, EXx } },
9346   },
9347   {
9348     /* VEX_W_0F15 */
9349     { "vunpckhpX",      { XM, Vex, EXx } },
9350   },
9351   {
9352     /* VEX_W_0F16_P_0_M_0 */
9353     { "vmovhps",        { XM, Vex128, EXq } },
9354   },
9355   {
9356     /* VEX_W_0F16_P_0_M_1 */
9357     { "vmovlhps",       { XM, Vex128, EXq } },
9358   },
9359   {
9360     /* VEX_W_0F16_P_1 */
9361     { "vmovshdup",      { XM, EXx } },
9362   },
9363   {
9364     /* VEX_W_0F16_P_2 */
9365     { "vmovhpd",        { XM, Vex128, EXq } },
9366   },
9367   {
9368     /* VEX_W_0F17_M_0 */
9369     { "vmovhpX",        { EXq, XM } },
9370   },
9371   {
9372     /* VEX_W_0F28 */
9373     { "vmovapX",        { XM, EXx } },
9374   },
9375   {
9376     /* VEX_W_0F29 */
9377     { "vmovapX",        { EXxS, XM } },
9378   },
9379   {
9380     /* VEX_W_0F2B_M_0 */
9381     { "vmovntpX",       { Mx, XM } },
9382   },
9383   {
9384     /* VEX_W_0F2E_P_0 */
9385     { "vucomiss",       { XMScalar, EXdScalar } },
9386   },
9387   {
9388     /* VEX_W_0F2E_P_2 */
9389     { "vucomisd",       { XMScalar, EXqScalar } },
9390   },
9391   {
9392     /* VEX_W_0F2F_P_0 */
9393     { "vcomiss",        { XMScalar, EXdScalar } },
9394   },
9395   {
9396     /* VEX_W_0F2F_P_2 */
9397     { "vcomisd",        { XMScalar, EXqScalar } },
9398   },
9399   {
9400     /* VEX_W_0F50_M_0 */
9401     { "vmovmskpX",      { Gdq, XS } },
9402   },
9403   {
9404     /* VEX_W_0F51_P_0 */
9405     { "vsqrtps",        { XM, EXx } },
9406   },
9407   {
9408     /* VEX_W_0F51_P_1 */
9409     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9410   },
9411   {
9412     /* VEX_W_0F51_P_2  */
9413     { "vsqrtpd",        { XM, EXx } },
9414   },
9415   {
9416     /* VEX_W_0F51_P_3 */
9417     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9418   },
9419   {
9420     /* VEX_W_0F52_P_0 */
9421     { "vrsqrtps",       { XM, EXx } },
9422   },
9423   {
9424     /* VEX_W_0F52_P_1 */
9425     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9426   },
9427   {
9428     /* VEX_W_0F53_P_0  */
9429     { "vrcpps",         { XM, EXx } },
9430   },
9431   {
9432     /* VEX_W_0F53_P_1  */
9433     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9434   },
9435   {
9436     /* VEX_W_0F58_P_0  */
9437     { "vaddps",         { XM, Vex, EXx } },
9438   },
9439   {
9440     /* VEX_W_0F58_P_1  */
9441     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9442   },
9443   {
9444     /* VEX_W_0F58_P_2  */
9445     { "vaddpd",         { XM, Vex, EXx } },
9446   },
9447   {
9448     /* VEX_W_0F58_P_3  */
9449     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9450   },
9451   {
9452     /* VEX_W_0F59_P_0  */
9453     { "vmulps",         { XM, Vex, EXx } },
9454   },
9455   {
9456     /* VEX_W_0F59_P_1  */
9457     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9458   },
9459   {
9460     /* VEX_W_0F59_P_2  */
9461     { "vmulpd",         { XM, Vex, EXx } },
9462   },
9463   {
9464     /* VEX_W_0F59_P_3  */
9465     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9466   },
9467   {
9468     /* VEX_W_0F5A_P_0  */
9469     { "vcvtps2pd",      { XM, EXxmmq } },
9470   },
9471   {
9472     /* VEX_W_0F5A_P_1  */
9473     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9474   },
9475   {
9476     /* VEX_W_0F5A_P_3  */
9477     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9478   },
9479   {
9480     /* VEX_W_0F5B_P_0  */
9481     { "vcvtdq2ps",      { XM, EXx } },
9482   },
9483   {
9484     /* VEX_W_0F5B_P_1  */
9485     { "vcvttps2dq",     { XM, EXx } },
9486   },
9487   {
9488     /* VEX_W_0F5B_P_2  */
9489     { "vcvtps2dq",      { XM, EXx } },
9490   },
9491   {
9492     /* VEX_W_0F5C_P_0  */
9493     { "vsubps",         { XM, Vex, EXx } },
9494   },
9495   {
9496     /* VEX_W_0F5C_P_1  */
9497     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9498   },
9499   {
9500     /* VEX_W_0F5C_P_2  */
9501     { "vsubpd",         { XM, Vex, EXx } },
9502   },
9503   {
9504     /* VEX_W_0F5C_P_3  */
9505     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9506   },
9507   {
9508     /* VEX_W_0F5D_P_0  */
9509     { "vminps",         { XM, Vex, EXx } },
9510   },
9511   {
9512     /* VEX_W_0F5D_P_1  */
9513     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9514   },
9515   {
9516     /* VEX_W_0F5D_P_2  */
9517     { "vminpd",         { XM, Vex, EXx } },
9518   },
9519   {
9520     /* VEX_W_0F5D_P_3  */
9521     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9522   },
9523   {
9524     /* VEX_W_0F5E_P_0  */
9525     { "vdivps",         { XM, Vex, EXx } },
9526   },
9527   {
9528     /* VEX_W_0F5E_P_1  */
9529     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9530   },
9531   {
9532     /* VEX_W_0F5E_P_2  */
9533     { "vdivpd",         { XM, Vex, EXx } },
9534   },
9535   {
9536     /* VEX_W_0F5E_P_3  */
9537     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9538   },
9539   {
9540     /* VEX_W_0F5F_P_0  */
9541     { "vmaxps",         { XM, Vex, EXx } },
9542   },
9543   {
9544     /* VEX_W_0F5F_P_1  */
9545     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9546   },
9547   {
9548     /* VEX_W_0F5F_P_2  */
9549     { "vmaxpd",         { XM, Vex, EXx } },
9550   },
9551   {
9552     /* VEX_W_0F5F_P_3  */
9553     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9554   },
9555   {
9556     /* VEX_W_0F60_P_2  */
9557     { "vpunpcklbw",     { XM, Vex128, EXx } },
9558   },
9559   {
9560     /* VEX_W_0F61_P_2  */
9561     { "vpunpcklwd",     { XM, Vex128, EXx } },
9562   },
9563   {
9564     /* VEX_W_0F62_P_2  */
9565     { "vpunpckldq",     { XM, Vex128, EXx } },
9566   },
9567   {
9568     /* VEX_W_0F63_P_2  */
9569     { "vpacksswb",      { XM, Vex128, EXx } },
9570   },
9571   {
9572     /* VEX_W_0F64_P_2  */
9573     { "vpcmpgtb",       { XM, Vex128, EXx } },
9574   },
9575   {
9576     /* VEX_W_0F65_P_2  */
9577     { "vpcmpgtw",       { XM, Vex128, EXx } },
9578   },
9579   {
9580     /* VEX_W_0F66_P_2  */
9581     { "vpcmpgtd",       { XM, Vex128, EXx } },
9582   },
9583   {
9584     /* VEX_W_0F67_P_2  */
9585     { "vpackuswb",      { XM, Vex128, EXx } },
9586   },
9587   {
9588     /* VEX_W_0F68_P_2  */
9589     { "vpunpckhbw",     { XM, Vex128, EXx } },
9590   },
9591   {
9592     /* VEX_W_0F69_P_2  */
9593     { "vpunpckhwd",     { XM, Vex128, EXx } },
9594   },
9595   {
9596     /* VEX_W_0F6A_P_2  */
9597     { "vpunpckhdq",     { XM, Vex128, EXx } },
9598   },
9599   {
9600     /* VEX_W_0F6B_P_2  */
9601     { "vpackssdw",      { XM, Vex128, EXx } },
9602   },
9603   {
9604     /* VEX_W_0F6C_P_2  */
9605     { "vpunpcklqdq",    { XM, Vex128, EXx } },
9606   },
9607   {
9608     /* VEX_W_0F6D_P_2  */
9609     { "vpunpckhqdq",    { XM, Vex128, EXx } },
9610   },
9611   {
9612     /* VEX_W_0F6F_P_1  */
9613     { "vmovdqu",        { XM, EXx } },
9614   },
9615   {
9616     /* VEX_W_0F6F_P_2  */
9617     { "vmovdqa",        { XM, EXx } },
9618   },
9619   {
9620     /* VEX_W_0F70_P_1 */
9621     { "vpshufhw",       { XM, EXx, Ib } },
9622   },
9623   {
9624     /* VEX_W_0F70_P_2 */
9625     { "vpshufd",        { XM, EXx, Ib } },
9626   },
9627   {
9628     /* VEX_W_0F70_P_3 */
9629     { "vpshuflw",       { XM, EXx, Ib } },
9630   },
9631   {
9632     /* VEX_W_0F71_R_2_P_2  */
9633     { "vpsrlw",         { Vex128, XS, Ib } },
9634   },
9635   {
9636     /* VEX_W_0F71_R_4_P_2  */
9637     { "vpsraw",         { Vex128, XS, Ib } },
9638   },
9639   {
9640     /* VEX_W_0F71_R_6_P_2  */
9641     { "vpsllw",         { Vex128, XS, Ib } },
9642   },
9643   {
9644     /* VEX_W_0F72_R_2_P_2  */
9645     { "vpsrld",         { Vex128, XS, Ib } },
9646   },
9647   {
9648     /* VEX_W_0F72_R_4_P_2  */
9649     { "vpsrad",         { Vex128, XS, Ib } },
9650   },
9651   {
9652     /* VEX_W_0F72_R_6_P_2  */
9653     { "vpslld",         { Vex128, XS, Ib } },
9654   },
9655   {
9656     /* VEX_W_0F73_R_2_P_2  */
9657     { "vpsrlq",         { Vex128, XS, Ib } },
9658   },
9659   {
9660     /* VEX_W_0F73_R_3_P_2  */
9661     { "vpsrldq",        { Vex128, XS, Ib } },
9662   },
9663   {
9664     /* VEX_W_0F73_R_6_P_2  */
9665     { "vpsllq",         { Vex128, XS, Ib } },
9666   },
9667   {
9668     /* VEX_W_0F73_R_7_P_2  */
9669     { "vpslldq",        { Vex128, XS, Ib } },
9670   },
9671   {
9672     /* VEX_W_0F74_P_2 */
9673     { "vpcmpeqb",       { XM, Vex128, EXx } },
9674   },
9675   {
9676     /* VEX_W_0F75_P_2 */
9677     { "vpcmpeqw",       { XM, Vex128, EXx } },
9678   },
9679   {
9680     /* VEX_W_0F76_P_2 */
9681     { "vpcmpeqd",       { XM, Vex128, EXx } },
9682   },
9683   {
9684     /* VEX_W_0F77_P_0 */
9685     { "",               { VZERO } },
9686   },
9687   {
9688     /* VEX_W_0F7C_P_2 */
9689     { "vhaddpd",        { XM, Vex, EXx } },
9690   },
9691   {
9692     /* VEX_W_0F7C_P_3 */
9693     { "vhaddps",        { XM, Vex, EXx } },
9694   },
9695   {
9696     /* VEX_W_0F7D_P_2 */
9697     { "vhsubpd",        { XM, Vex, EXx } },
9698   },
9699   {
9700     /* VEX_W_0F7D_P_3 */
9701     { "vhsubps",        { XM, Vex, EXx } },
9702   },
9703   {
9704     /* VEX_W_0F7E_P_1 */
9705     { "vmovq",          { XMScalar, EXqScalar } },
9706   },
9707   {
9708     /* VEX_W_0F7F_P_1 */
9709     { "vmovdqu",        { EXxS, XM } },
9710   },
9711   {
9712     /* VEX_W_0F7F_P_2 */
9713     { "vmovdqa",        { EXxS, XM } },
9714   },
9715   {
9716     /* VEX_W_0FAE_R_2_M_0 */
9717     { "vldmxcsr",       { Md } },
9718   },
9719   {
9720     /* VEX_W_0FAE_R_3_M_0 */
9721     { "vstmxcsr",       { Md } },
9722   },
9723   {
9724     /* VEX_W_0FC2_P_0 */
9725     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9726   },
9727   {
9728     /* VEX_W_0FC2_P_1 */
9729     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9730   },
9731   {
9732     /* VEX_W_0FC2_P_2 */
9733     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9734   },
9735   {
9736     /* VEX_W_0FC2_P_3 */
9737     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9738   },
9739   {
9740     /* VEX_W_0FC4_P_2 */
9741     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9742   },
9743   {
9744     /* VEX_W_0FC5_P_2 */
9745     { "vpextrw",        { Gdq, XS, Ib } },
9746   },
9747   {
9748     /* VEX_W_0FD0_P_2 */
9749     { "vaddsubpd",      { XM, Vex, EXx } },
9750   },
9751   {
9752     /* VEX_W_0FD0_P_3 */
9753     { "vaddsubps",      { XM, Vex, EXx } },
9754   },
9755   {
9756     /* VEX_W_0FD1_P_2 */
9757     { "vpsrlw",         { XM, Vex128, EXx } },
9758   },
9759   {
9760     /* VEX_W_0FD2_P_2 */
9761     { "vpsrld",         { XM, Vex128, EXx } },
9762   },
9763   {
9764     /* VEX_W_0FD3_P_2 */
9765     { "vpsrlq",         { XM, Vex128, EXx } },
9766   },
9767   {
9768     /* VEX_W_0FD4_P_2 */
9769     { "vpaddq",         { XM, Vex128, EXx } },
9770   },
9771   {
9772     /* VEX_W_0FD5_P_2 */
9773     { "vpmullw",        { XM, Vex128, EXx } },
9774   },
9775   {
9776     /* VEX_W_0FD6_P_2 */
9777     { "vmovq",          { EXqScalarS, XMScalar } },
9778   },
9779   {
9780     /* VEX_W_0FD7_P_2_M_1 */
9781     { "vpmovmskb",      { Gdq, XS } },
9782   },
9783   {
9784     /* VEX_W_0FD8_P_2 */
9785     { "vpsubusb",       { XM, Vex128, EXx } },
9786   },
9787   {
9788     /* VEX_W_0FD9_P_2 */
9789     { "vpsubusw",       { XM, Vex128, EXx } },
9790   },
9791   {
9792     /* VEX_W_0FDA_P_2 */
9793     { "vpminub",        { XM, Vex128, EXx } },
9794   },
9795   {
9796     /* VEX_W_0FDB_P_2 */
9797     { "vpand",          { XM, Vex128, EXx } },
9798   },
9799   {
9800     /* VEX_W_0FDC_P_2 */
9801     { "vpaddusb",       { XM, Vex128, EXx } },
9802   },
9803   {
9804     /* VEX_W_0FDD_P_2 */
9805     { "vpaddusw",       { XM, Vex128, EXx } },
9806   },
9807   {
9808     /* VEX_W_0FDE_P_2 */
9809     { "vpmaxub",        { XM, Vex128, EXx } },
9810   },
9811   {
9812     /* VEX_W_0FDF_P_2 */
9813     { "vpandn",         { XM, Vex128, EXx } },
9814   },
9815   {
9816     /* VEX_W_0FE0_P_2  */
9817     { "vpavgb",         { XM, Vex128, EXx } },
9818   },
9819   {
9820     /* VEX_W_0FE1_P_2  */
9821     { "vpsraw",         { XM, Vex128, EXx } },
9822   },
9823   {
9824     /* VEX_W_0FE2_P_2  */
9825     { "vpsrad",         { XM, Vex128, EXx } },
9826   },
9827   {
9828     /* VEX_W_0FE3_P_2  */
9829     { "vpavgw",         { XM, Vex128, EXx } },
9830   },
9831   {
9832     /* VEX_W_0FE4_P_2  */
9833     { "vpmulhuw",       { XM, Vex128, EXx } },
9834   },
9835   {
9836     /* VEX_W_0FE5_P_2  */
9837     { "vpmulhw",        { XM, Vex128, EXx } },
9838   },
9839   {
9840     /* VEX_W_0FE6_P_1  */
9841     { "vcvtdq2pd",      { XM, EXxmmq } },
9842   },
9843   {
9844     /* VEX_W_0FE6_P_2  */
9845     { "vcvttpd2dq%XY",  { XMM, EXx } },
9846   },
9847   {
9848     /* VEX_W_0FE6_P_3  */
9849     { "vcvtpd2dq%XY",   { XMM, EXx } },
9850   },
9851   {
9852     /* VEX_W_0FE7_P_2_M_0 */
9853     { "vmovntdq",       { Mx, XM } },
9854   },
9855   {
9856     /* VEX_W_0FE8_P_2  */
9857     { "vpsubsb",        { XM, Vex128, EXx } },
9858   },
9859   {
9860     /* VEX_W_0FE9_P_2  */
9861     { "vpsubsw",        { XM, Vex128, EXx } },
9862   },
9863   {
9864     /* VEX_W_0FEA_P_2  */
9865     { "vpminsw",        { XM, Vex128, EXx } },
9866   },
9867   {
9868     /* VEX_W_0FEB_P_2  */
9869     { "vpor",           { XM, Vex128, EXx } },
9870   },
9871   {
9872     /* VEX_W_0FEC_P_2  */
9873     { "vpaddsb",        { XM, Vex128, EXx } },
9874   },
9875   {
9876     /* VEX_W_0FED_P_2  */
9877     { "vpaddsw",        { XM, Vex128, EXx } },
9878   },
9879   {
9880     /* VEX_W_0FEE_P_2  */
9881     { "vpmaxsw",        { XM, Vex128, EXx } },
9882   },
9883   {
9884     /* VEX_W_0FEF_P_2  */
9885     { "vpxor",          { XM, Vex128, EXx } },
9886   },
9887   {
9888     /* VEX_W_0FF0_P_3_M_0 */
9889     { "vlddqu",         { XM, M } },
9890   },
9891   {
9892     /* VEX_W_0FF1_P_2 */
9893     { "vpsllw",         { XM, Vex128, EXx } },
9894   },
9895   {
9896     /* VEX_W_0FF2_P_2 */
9897     { "vpslld",         { XM, Vex128, EXx } },
9898   },
9899   {
9900     /* VEX_W_0FF3_P_2 */
9901     { "vpsllq",         { XM, Vex128, EXx } },
9902   },
9903   {
9904     /* VEX_W_0FF4_P_2 */
9905     { "vpmuludq",       { XM, Vex128, EXx } },
9906   },
9907   {
9908     /* VEX_W_0FF5_P_2 */
9909     { "vpmaddwd",       { XM, Vex128, EXx } },
9910   },
9911   {
9912     /* VEX_W_0FF6_P_2 */
9913     { "vpsadbw",        { XM, Vex128, EXx } },
9914   },
9915   {
9916     /* VEX_W_0FF7_P_2 */
9917     { "vmaskmovdqu",    { XM, XS } },
9918   },
9919   {
9920     /* VEX_W_0FF8_P_2 */
9921     { "vpsubb",         { XM, Vex128, EXx } },
9922   },
9923   {
9924     /* VEX_W_0FF9_P_2 */
9925     { "vpsubw",         { XM, Vex128, EXx } },
9926   },
9927   {
9928     /* VEX_W_0FFA_P_2 */
9929     { "vpsubd",         { XM, Vex128, EXx } },
9930   },
9931   {
9932     /* VEX_W_0FFB_P_2 */
9933     { "vpsubq",         { XM, Vex128, EXx } },
9934   },
9935   {
9936     /* VEX_W_0FFC_P_2 */
9937     { "vpaddb",         { XM, Vex128, EXx } },
9938   },
9939   {
9940     /* VEX_W_0FFD_P_2 */
9941     { "vpaddw",         { XM, Vex128, EXx } },
9942   },
9943   {
9944     /* VEX_W_0FFE_P_2 */
9945     { "vpaddd",         { XM, Vex128, EXx } },
9946   },
9947   {
9948     /* VEX_W_0F3800_P_2  */
9949     { "vpshufb",        { XM, Vex128, EXx } },
9950   },
9951   {
9952     /* VEX_W_0F3801_P_2  */
9953     { "vphaddw",        { XM, Vex128, EXx } },
9954   },
9955   {
9956     /* VEX_W_0F3802_P_2  */
9957     { "vphaddd",        { XM, Vex128, EXx } },
9958   },
9959   {
9960     /* VEX_W_0F3803_P_2  */
9961     { "vphaddsw",       { XM, Vex128, EXx } },
9962   },
9963   {
9964     /* VEX_W_0F3804_P_2  */
9965     { "vpmaddubsw",     { XM, Vex128, EXx } },
9966   },
9967   {
9968     /* VEX_W_0F3805_P_2  */
9969     { "vphsubw",        { XM, Vex128, EXx } },
9970   },
9971   {
9972     /* VEX_W_0F3806_P_2  */
9973     { "vphsubd",        { XM, Vex128, EXx } },
9974   },
9975   {
9976     /* VEX_W_0F3807_P_2  */
9977     { "vphsubsw",       { XM, Vex128, EXx } },
9978   },
9979   {
9980     /* VEX_W_0F3808_P_2  */
9981     { "vpsignb",        { XM, Vex128, EXx } },
9982   },
9983   {
9984     /* VEX_W_0F3809_P_2  */
9985     { "vpsignw",        { XM, Vex128, EXx } },
9986   },
9987   {
9988     /* VEX_W_0F380A_P_2  */
9989     { "vpsignd",        { XM, Vex128, EXx } },
9990   },
9991   {
9992     /* VEX_W_0F380B_P_2  */
9993     { "vpmulhrsw",      { XM, Vex128, EXx } },
9994   },
9995   {
9996     /* VEX_W_0F380C_P_2  */
9997     { "vpermilps",      { XM, Vex, EXx } },
9998   },
9999   {
10000     /* VEX_W_0F380D_P_2  */
10001     { "vpermilpd",      { XM, Vex, EXx } },
10002   },
10003   {
10004     /* VEX_W_0F380E_P_2  */
10005     { "vtestps",        { XM, EXx } },
10006   },
10007   {
10008     /* VEX_W_0F380F_P_2  */
10009     { "vtestpd",        { XM, EXx } },
10010   },
10011   {
10012     /* VEX_W_0F3817_P_2 */
10013     { "vptest",         { XM, EXx } },
10014   },
10015   {
10016     /* VEX_W_0F3818_P_2_M_0 */
10017     { "vbroadcastss",   { XM, Md } },
10018   },
10019   {
10020     /* VEX_W_0F3819_P_2_M_0 */
10021     { "vbroadcastsd",   { XM, Mq } },
10022   },
10023   {
10024     /* VEX_W_0F381A_P_2_M_0 */
10025     { "vbroadcastf128", { XM, Mxmm } },
10026   },
10027   {
10028     /* VEX_W_0F381C_P_2 */
10029     { "vpabsb",         { XM, EXx } },
10030   },
10031   {
10032     /* VEX_W_0F381D_P_2 */
10033     { "vpabsw",         { XM, EXx } },
10034   },
10035   {
10036     /* VEX_W_0F381E_P_2 */
10037     { "vpabsd",         { XM, EXx } },
10038   },
10039   {
10040     /* VEX_W_0F3820_P_2 */
10041     { "vpmovsxbw",      { XM, EXq } },
10042   },
10043   {
10044     /* VEX_W_0F3821_P_2 */
10045     { "vpmovsxbd",      { XM, EXd } },
10046   },
10047   {
10048     /* VEX_W_0F3822_P_2 */
10049     { "vpmovsxbq",      { XM, EXw } },
10050   },
10051   {
10052     /* VEX_W_0F3823_P_2 */
10053     { "vpmovsxwd",      { XM, EXq } },
10054   },
10055   {
10056     /* VEX_W_0F3824_P_2 */
10057     { "vpmovsxwq",      { XM, EXd } },
10058   },
10059   {
10060     /* VEX_W_0F3825_P_2 */
10061     { "vpmovsxdq",      { XM, EXq } },
10062   },
10063   {
10064     /* VEX_W_0F3828_P_2 */
10065     { "vpmuldq",        { XM, Vex128, EXx } },
10066   },
10067   {
10068     /* VEX_W_0F3829_P_2 */
10069     { "vpcmpeqq",       { XM, Vex128, EXx } },
10070   },
10071   {
10072     /* VEX_W_0F382A_P_2_M_0 */
10073     { "vmovntdqa",      { XM, Mx } },
10074   },
10075   {
10076     /* VEX_W_0F382B_P_2 */
10077     { "vpackusdw",      { XM, Vex128, EXx } },
10078   },
10079   {
10080     /* VEX_W_0F382C_P_2_M_0 */
10081     { "vmaskmovps",     { XM, Vex, Mx } },
10082   },
10083   {
10084     /* VEX_W_0F382D_P_2_M_0 */
10085     { "vmaskmovpd",     { XM, Vex, Mx } },
10086   },
10087   {
10088     /* VEX_W_0F382E_P_2_M_0 */
10089     { "vmaskmovps",     { Mx, Vex, XM } },
10090   },
10091   {
10092     /* VEX_W_0F382F_P_2_M_0 */
10093     { "vmaskmovpd",     { Mx, Vex, XM } },
10094   },
10095   {
10096     /* VEX_W_0F3830_P_2 */
10097     { "vpmovzxbw",      { XM, EXq } },
10098   },
10099   {
10100     /* VEX_W_0F3831_P_2 */
10101     { "vpmovzxbd",      { XM, EXd } },
10102   },
10103   {
10104     /* VEX_W_0F3832_P_2 */
10105     { "vpmovzxbq",      { XM, EXw } },
10106   },
10107   {
10108     /* VEX_W_0F3833_P_2 */
10109     { "vpmovzxwd",      { XM, EXq } },
10110   },
10111   {
10112     /* VEX_W_0F3834_P_2 */
10113     { "vpmovzxwq",      { XM, EXd } },
10114   },
10115   {
10116     /* VEX_W_0F3835_P_2 */
10117     { "vpmovzxdq",      { XM, EXq } },
10118   },
10119   {
10120     /* VEX_W_0F3837_P_2 */
10121     { "vpcmpgtq",       { XM, Vex128, EXx } },
10122   },
10123   {
10124     /* VEX_W_0F3838_P_2 */
10125     { "vpminsb",        { XM, Vex128, EXx } },
10126   },
10127   {
10128     /* VEX_W_0F3839_P_2 */
10129     { "vpminsd",        { XM, Vex128, EXx } },
10130   },
10131   {
10132     /* VEX_W_0F383A_P_2 */
10133     { "vpminuw",        { XM, Vex128, EXx } },
10134   },
10135   {
10136     /* VEX_W_0F383B_P_2 */
10137     { "vpminud",        { XM, Vex128, EXx } },
10138   },
10139   {
10140     /* VEX_W_0F383C_P_2 */
10141     { "vpmaxsb",        { XM, Vex128, EXx } },
10142   },
10143   {
10144     /* VEX_W_0F383D_P_2 */
10145     { "vpmaxsd",        { XM, Vex128, EXx } },
10146   },
10147   {
10148     /* VEX_W_0F383E_P_2 */
10149     { "vpmaxuw",        { XM, Vex128, EXx } },
10150   },
10151   {
10152     /* VEX_W_0F383F_P_2 */
10153     { "vpmaxud",        { XM, Vex128, EXx } },
10154   },
10155   {
10156     /* VEX_W_0F3840_P_2 */
10157     { "vpmulld",        { XM, Vex128, EXx } },
10158   },
10159   {
10160     /* VEX_W_0F3841_P_2 */
10161     { "vphminposuw",    { XM, EXx } },
10162   },
10163   {
10164     /* VEX_W_0F38DB_P_2 */
10165     { "vaesimc",        { XM, EXx } },
10166   },
10167   {
10168     /* VEX_W_0F38DC_P_2 */
10169     { "vaesenc",        { XM, Vex128, EXx } },
10170   },
10171   {
10172     /* VEX_W_0F38DD_P_2 */
10173     { "vaesenclast",    { XM, Vex128, EXx } },
10174   },
10175   {
10176     /* VEX_W_0F38DE_P_2 */
10177     { "vaesdec",        { XM, Vex128, EXx } },
10178   },
10179   {
10180     /* VEX_W_0F38DF_P_2 */
10181     { "vaesdeclast",    { XM, Vex128, EXx } },
10182   },
10183   {
10184     /* VEX_W_0F3A04_P_2 */
10185     { "vpermilps",      { XM, EXx, Ib } },
10186   },
10187   {
10188     /* VEX_W_0F3A05_P_2 */
10189     { "vpermilpd",      { XM, EXx, Ib } },
10190   },
10191   {
10192     /* VEX_W_0F3A06_P_2 */
10193     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10194   },
10195   {
10196     /* VEX_W_0F3A08_P_2 */
10197     { "vroundps",       { XM, EXx, Ib } },
10198   },
10199   {
10200     /* VEX_W_0F3A09_P_2 */
10201     { "vroundpd",       { XM, EXx, Ib } },
10202   },
10203   {
10204     /* VEX_W_0F3A0A_P_2 */
10205     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10206   },
10207   {
10208     /* VEX_W_0F3A0B_P_2 */
10209     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10210   },
10211   {
10212     /* VEX_W_0F3A0C_P_2 */
10213     { "vblendps",       { XM, Vex, EXx, Ib } },
10214   },
10215   {
10216     /* VEX_W_0F3A0D_P_2 */
10217     { "vblendpd",       { XM, Vex, EXx, Ib } },
10218   },
10219   {
10220     /* VEX_W_0F3A0E_P_2 */
10221     { "vpblendw",       { XM, Vex128, EXx, Ib } },
10222   },
10223   {
10224     /* VEX_W_0F3A0F_P_2 */
10225     { "vpalignr",       { XM, Vex128, EXx, Ib } },
10226   },
10227   {
10228     /* VEX_W_0F3A14_P_2 */
10229     { "vpextrb",        { Edqb, XM, Ib } },
10230   },
10231   {
10232     /* VEX_W_0F3A15_P_2 */
10233     { "vpextrw",        { Edqw, XM, Ib } },
10234   },
10235   {
10236     /* VEX_W_0F3A18_P_2 */
10237     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10238   },
10239   {
10240     /* VEX_W_0F3A19_P_2 */
10241     { "vextractf128",   { EXxmm, XM, Ib } },
10242   },
10243   {
10244     /* VEX_W_0F3A20_P_2 */
10245     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10246   },
10247   {
10248     /* VEX_W_0F3A21_P_2 */
10249     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10250   },
10251   {
10252     /* VEX_W_0F3A40_P_2 */
10253     { "vdpps",          { XM, Vex, EXx, Ib } },
10254   },
10255   {
10256     /* VEX_W_0F3A41_P_2 */
10257     { "vdppd",          { XM, Vex128, EXx, Ib } },
10258   },
10259   {
10260     /* VEX_W_0F3A42_P_2 */
10261     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
10262   },
10263   {
10264     /* VEX_W_0F3A44_P_2 */
10265     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10266   },
10267   {
10268     /* VEX_W_0F3A48_P_2 */
10269     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10270     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10271   },
10272   {
10273     /* VEX_W_0F3A49_P_2 */
10274     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10275     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10276   },
10277   {
10278     /* VEX_W_0F3A4A_P_2 */
10279     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10280   },
10281   {
10282     /* VEX_W_0F3A4B_P_2 */
10283     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10284   },
10285   {
10286     /* VEX_W_0F3A4C_P_2 */
10287     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
10288   },
10289   {
10290     /* VEX_W_0F3A60_P_2 */
10291     { "vpcmpestrm",     { XM, EXx, Ib } },
10292   },
10293   {
10294     /* VEX_W_0F3A61_P_2 */
10295     { "vpcmpestri",     { XM, EXx, Ib } },
10296   },
10297   {
10298     /* VEX_W_0F3A62_P_2 */
10299     { "vpcmpistrm",     { XM, EXx, Ib } },
10300   },
10301   {
10302     /* VEX_W_0F3A63_P_2 */
10303     { "vpcmpistri",     { XM, EXx, Ib } },
10304   },
10305   {
10306     /* VEX_W_0F3ADF_P_2 */
10307     { "vaeskeygenassist", { XM, EXx, Ib } },
10308   },
10309 };
10310
10311 static const struct dis386 mod_table[][2] = {
10312   {
10313     /* MOD_8D */
10314     { "leaS",           { Gv, M } },
10315   },
10316   {
10317     /* MOD_0F01_REG_0 */
10318     { X86_64_TABLE (X86_64_0F01_REG_0) },
10319     { RM_TABLE (RM_0F01_REG_0) },
10320   },
10321   {
10322     /* MOD_0F01_REG_1 */
10323     { X86_64_TABLE (X86_64_0F01_REG_1) },
10324     { RM_TABLE (RM_0F01_REG_1) },
10325   },
10326   {
10327     /* MOD_0F01_REG_2 */
10328     { X86_64_TABLE (X86_64_0F01_REG_2) },
10329     { RM_TABLE (RM_0F01_REG_2) },
10330   },
10331   {
10332     /* MOD_0F01_REG_3 */
10333     { X86_64_TABLE (X86_64_0F01_REG_3) },
10334     { RM_TABLE (RM_0F01_REG_3) },
10335   },
10336   {
10337     /* MOD_0F01_REG_7 */
10338     { "invlpg",         { Mb } },
10339     { RM_TABLE (RM_0F01_REG_7) },
10340   },
10341   {
10342     /* MOD_0F12_PREFIX_0 */
10343     { "movlps",         { XM, EXq } },
10344     { "movhlps",        { XM, EXq } },
10345   },
10346   {
10347     /* MOD_0F13 */
10348     { "movlpX",         { EXq, XM } },
10349   },
10350   {
10351     /* MOD_0F16_PREFIX_0 */
10352     { "movhps",         { XM, EXq } },
10353     { "movlhps",        { XM, EXq } },
10354   },
10355   {
10356     /* MOD_0F17 */
10357     { "movhpX",         { EXq, XM } },
10358   },
10359   {
10360     /* MOD_0F18_REG_0 */
10361     { "prefetchnta",    { Mb } },
10362   },
10363   {
10364     /* MOD_0F18_REG_1 */
10365     { "prefetcht0",     { Mb } },
10366   },
10367   {
10368     /* MOD_0F18_REG_2 */
10369     { "prefetcht1",     { Mb } },
10370   },
10371   {
10372     /* MOD_0F18_REG_3 */
10373     { "prefetcht2",     { Mb } },
10374   },
10375   {
10376     /* MOD_0F20 */
10377     { Bad_Opcode },
10378     { "movZ",           { Rm, Cm } },
10379   },
10380   {
10381     /* MOD_0F21 */
10382     { Bad_Opcode },
10383     { "movZ",           { Rm, Dm } },
10384   },
10385   {
10386     /* MOD_0F22 */
10387     { Bad_Opcode },
10388     { "movZ",           { Cm, Rm } },
10389   },
10390   {
10391     /* MOD_0F23 */
10392     { Bad_Opcode },
10393     { "movZ",           { Dm, Rm } },
10394   },
10395   {
10396     /* MOD_0F24 */
10397     { Bad_Opcode },
10398     { "movL",           { Rd, Td } },
10399   },
10400   {
10401     /* MOD_0F26 */
10402     { Bad_Opcode },
10403     { "movL",           { Td, Rd } },
10404   },
10405   {
10406     /* MOD_0F2B_PREFIX_0 */
10407     {"movntps",         { Mx, XM } },
10408   },
10409   {
10410     /* MOD_0F2B_PREFIX_1 */
10411     {"movntss",         { Md, XM } },
10412   },
10413   {
10414     /* MOD_0F2B_PREFIX_2 */
10415     {"movntpd",         { Mx, XM } },
10416   },
10417   {
10418     /* MOD_0F2B_PREFIX_3 */
10419     {"movntsd",         { Mq, XM } },
10420   },
10421   {
10422     /* MOD_0F51 */
10423     { Bad_Opcode },
10424     { "movmskpX",       { Gdq, XS } },
10425   },
10426   {
10427     /* MOD_0F71_REG_2 */
10428     { Bad_Opcode },
10429     { "psrlw",          { MS, Ib } },
10430   },
10431   {
10432     /* MOD_0F71_REG_4 */
10433     { Bad_Opcode },
10434     { "psraw",          { MS, Ib } },
10435   },
10436   {
10437     /* MOD_0F71_REG_6 */
10438     { Bad_Opcode },
10439     { "psllw",          { MS, Ib } },
10440   },
10441   {
10442     /* MOD_0F72_REG_2 */
10443     { Bad_Opcode },
10444     { "psrld",          { MS, Ib } },
10445   },
10446   {
10447     /* MOD_0F72_REG_4 */
10448     { Bad_Opcode },
10449     { "psrad",          { MS, Ib } },
10450   },
10451   {
10452     /* MOD_0F72_REG_6 */
10453     { Bad_Opcode },
10454     { "pslld",          { MS, Ib } },
10455   },
10456   {
10457     /* MOD_0F73_REG_2 */
10458     { Bad_Opcode },
10459     { "psrlq",          { MS, Ib } },
10460   },
10461   {
10462     /* MOD_0F73_REG_3 */
10463     { Bad_Opcode },
10464     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10465   },
10466   {
10467     /* MOD_0F73_REG_6 */
10468     { Bad_Opcode },
10469     { "psllq",          { MS, Ib } },
10470   },
10471   {
10472     /* MOD_0F73_REG_7 */
10473     { Bad_Opcode },
10474     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10475   },
10476   {
10477     /* MOD_0FAE_REG_0 */
10478     { "fxsave",         { FXSAVE } },
10479     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10480   },
10481   {
10482     /* MOD_0FAE_REG_1 */
10483     { "fxrstor",        { FXSAVE } },
10484     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10485   },
10486   {
10487     /* MOD_0FAE_REG_2 */
10488     { "ldmxcsr",        { Md } },
10489     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10490   },
10491   {
10492     /* MOD_0FAE_REG_3 */
10493     { "stmxcsr",        { Md } },
10494     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10495   },
10496   {
10497     /* MOD_0FAE_REG_4 */
10498     { "xsave",          { FXSAVE } },
10499   },
10500   {
10501     /* MOD_0FAE_REG_5 */
10502     { "xrstor",         { FXSAVE } },
10503     { RM_TABLE (RM_0FAE_REG_5) },
10504   },
10505   {
10506     /* MOD_0FAE_REG_6 */
10507     { "xsaveopt",       { FXSAVE } },
10508     { RM_TABLE (RM_0FAE_REG_6) },
10509   },
10510   {
10511     /* MOD_0FAE_REG_7 */
10512     { "clflush",        { Mb } },
10513     { RM_TABLE (RM_0FAE_REG_7) },
10514   },
10515   {
10516     /* MOD_0FB2 */
10517     { "lssS",           { Gv, Mp } },
10518   },
10519   {
10520     /* MOD_0FB4 */
10521     { "lfsS",           { Gv, Mp } },
10522   },
10523   {
10524     /* MOD_0FB5 */
10525     { "lgsS",           { Gv, Mp } },
10526   },
10527   {
10528     /* MOD_0FC7_REG_6 */
10529     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10530     { "rdrand",         { Ev } },
10531   },
10532   {
10533     /* MOD_0FC7_REG_7 */
10534     { "vmptrst",        { Mq } },
10535   },
10536   {
10537     /* MOD_0FD7 */
10538     { Bad_Opcode },
10539     { "pmovmskb",       { Gdq, MS } },
10540   },
10541   {
10542     /* MOD_0FE7_PREFIX_2 */
10543     { "movntdq",        { Mx, XM } },
10544   },
10545   {
10546     /* MOD_0FF0_PREFIX_3 */
10547     { "lddqu",          { XM, M } },
10548   },
10549   {
10550     /* MOD_0F382A_PREFIX_2 */
10551     { "movntdqa",       { XM, Mx } },
10552   },
10553   {
10554     /* MOD_62_32BIT */
10555     { "bound{S|}",      { Gv, Ma } },
10556   },
10557   {
10558     /* MOD_C4_32BIT */
10559     { "lesS",           { Gv, Mp } },
10560     { VEX_C4_TABLE (VEX_0F) },
10561   },
10562   {
10563     /* MOD_C5_32BIT */
10564     { "ldsS",           { Gv, Mp } },
10565     { VEX_C5_TABLE (VEX_0F) },
10566   },
10567   {
10568     /* MOD_VEX_0F12_PREFIX_0 */
10569     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10570     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10571   },
10572   {
10573     /* MOD_VEX_0F13 */
10574     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10575   },
10576   {
10577     /* MOD_VEX_0F16_PREFIX_0 */
10578     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10579     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10580   },
10581   {
10582     /* MOD_VEX_0F17 */
10583     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10584   },
10585   {
10586     /* MOD_VEX_0F2B */
10587     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10588   },
10589   {
10590     /* MOD_VEX_0F50 */
10591     { Bad_Opcode },
10592     { VEX_W_TABLE (VEX_W_0F50_M_0) },
10593   },
10594   {
10595     /* MOD_VEX_0F71_REG_2 */
10596     { Bad_Opcode },
10597     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10598   },
10599   {
10600     /* MOD_VEX_0F71_REG_4 */
10601     { Bad_Opcode },
10602     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10603   },
10604   {
10605     /* MOD_VEX_0F71_REG_6 */
10606     { Bad_Opcode },
10607     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10608   },
10609   {
10610     /* MOD_VEX_0F72_REG_2 */
10611     { Bad_Opcode },
10612     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10613   },
10614   {
10615     /* MOD_VEX_0F72_REG_4 */
10616     { Bad_Opcode },
10617     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10618   },
10619   {
10620     /* MOD_VEX_0F72_REG_6 */
10621     { Bad_Opcode },
10622     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10623   },
10624   {
10625     /* MOD_VEX_0F73_REG_2 */
10626     { Bad_Opcode },
10627     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10628   },
10629   {
10630     /* MOD_VEX_0F73_REG_3 */
10631     { Bad_Opcode },
10632     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10633   },
10634   {
10635     /* MOD_VEX_0F73_REG_6 */
10636     { Bad_Opcode },
10637     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10638   },
10639   {
10640     /* MOD_VEX_0F73_REG_7 */
10641     { Bad_Opcode },
10642     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10643   },
10644   {
10645     /* MOD_VEX_0FAE_REG_2 */
10646     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10647   },
10648   {
10649     /* MOD_VEX_0FAE_REG_3 */
10650     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10651   },
10652   {
10653     /* MOD_VEX_0FD7_PREFIX_2 */
10654     { Bad_Opcode },
10655     { VEX_LEN_TABLE (VEX_LEN_0FD7_P_2_M_1) },
10656   },
10657   {
10658     /* MOD_VEX_0FE7_PREFIX_2 */
10659     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10660   },
10661   {
10662     /* MOD_VEX_0FF0_PREFIX_3 */
10663     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10664   },
10665   {
10666     /* MOD_VEX_0F3818_PREFIX_2 */
10667     { VEX_W_TABLE (VEX_W_0F3818_P_2_M_0) },
10668   },
10669   {
10670     /* MOD_VEX_0F3819_PREFIX_2 */
10671     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2_M_0) },
10672   },
10673   {
10674     /* MOD_VEX_0F381A_PREFIX_2 */
10675     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10676   },
10677   {
10678     /* MOD_VEX_0F382A_PREFIX_2 */
10679     { VEX_LEN_TABLE (VEX_LEN_0F382A_P_2_M_0) },
10680   },
10681   {
10682     /* MOD_VEX_0F382C_PREFIX_2 */
10683     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10684   },
10685   {
10686     /* MOD_VEX_0F382D_PREFIX_2 */
10687     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10688   },
10689   {
10690     /* MOD_VEX_0F382E_PREFIX_2 */
10691     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10692   },
10693   {
10694     /* MOD_VEX_0F382F_PREFIX_2 */
10695     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10696   },
10697 };
10698
10699 static const struct dis386 rm_table[][8] = {
10700   {
10701     /* RM_0F01_REG_0 */
10702     { Bad_Opcode },
10703     { "vmcall",         { Skip_MODRM } },
10704     { "vmlaunch",       { Skip_MODRM } },
10705     { "vmresume",       { Skip_MODRM } },
10706     { "vmxoff",         { Skip_MODRM } },
10707   },
10708   {
10709     /* RM_0F01_REG_1 */
10710     { "monitor",        { { OP_Monitor, 0 } } },
10711     { "mwait",          { { OP_Mwait, 0 } } },
10712   },
10713   {
10714     /* RM_0F01_REG_2 */
10715     { "xgetbv",         { Skip_MODRM } },
10716     { "xsetbv",         { Skip_MODRM } },
10717   },
10718   {
10719     /* RM_0F01_REG_3 */
10720     { "vmrun",          { Skip_MODRM } },
10721     { "vmmcall",        { Skip_MODRM } },
10722     { "vmload",         { Skip_MODRM } },
10723     { "vmsave",         { Skip_MODRM } },
10724     { "stgi",           { Skip_MODRM } },
10725     { "clgi",           { Skip_MODRM } },
10726     { "skinit",         { Skip_MODRM } },
10727     { "invlpga",        { Skip_MODRM } },
10728   },
10729   {
10730     /* RM_0F01_REG_7 */
10731     { "swapgs",         { Skip_MODRM } },
10732     { "rdtscp",         { Skip_MODRM } },
10733   },
10734   {
10735     /* RM_0FAE_REG_5 */
10736     { "lfence",         { Skip_MODRM } },
10737   },
10738   {
10739     /* RM_0FAE_REG_6 */
10740     { "mfence",         { Skip_MODRM } },
10741   },
10742   {
10743     /* RM_0FAE_REG_7 */
10744     { "sfence",         { Skip_MODRM } },
10745   },
10746 };
10747
10748 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10749
10750 /* We use the high bit to indicate different name for the same
10751    prefix.  */
10752 #define ADDR16_PREFIX   (0x67 | 0x100)
10753 #define ADDR32_PREFIX   (0x67 | 0x200)
10754 #define DATA16_PREFIX   (0x66 | 0x100)
10755 #define DATA32_PREFIX   (0x66 | 0x200)
10756 #define REP_PREFIX      (0xf3 | 0x100)
10757
10758 static int
10759 ckprefix (void)
10760 {
10761   int newrex, i, length;
10762   rex = 0;
10763   rex_ignored = 0;
10764   prefixes = 0;
10765   used_prefixes = 0;
10766   rex_used = 0;
10767   last_lock_prefix = -1;
10768   last_repz_prefix = -1;
10769   last_repnz_prefix = -1;
10770   last_data_prefix = -1;
10771   last_addr_prefix = -1;
10772   last_rex_prefix = -1;
10773   last_seg_prefix = -1;
10774   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10775     all_prefixes[i] = 0;
10776   i = 0;
10777   length = 0;
10778   /* The maximum instruction length is 15bytes.  */
10779   while (length < MAX_CODE_LENGTH - 1)
10780     {
10781       FETCH_DATA (the_info, codep + 1);
10782       newrex = 0;
10783       switch (*codep)
10784         {
10785         /* REX prefixes family.  */
10786         case 0x40:
10787         case 0x41:
10788         case 0x42:
10789         case 0x43:
10790         case 0x44:
10791         case 0x45:
10792         case 0x46:
10793         case 0x47:
10794         case 0x48:
10795         case 0x49:
10796         case 0x4a:
10797         case 0x4b:
10798         case 0x4c:
10799         case 0x4d:
10800         case 0x4e:
10801         case 0x4f:
10802           if (address_mode == mode_64bit)
10803             newrex = *codep;
10804           else
10805             return 1;
10806           last_rex_prefix = i;
10807           break;
10808         case 0xf3:
10809           prefixes |= PREFIX_REPZ;
10810           last_repz_prefix = i;
10811           break;
10812         case 0xf2:
10813           prefixes |= PREFIX_REPNZ;
10814           last_repnz_prefix = i;
10815           break;
10816         case 0xf0:
10817           prefixes |= PREFIX_LOCK;
10818           last_lock_prefix = i;
10819           break;
10820         case 0x2e:
10821           prefixes |= PREFIX_CS;
10822           last_seg_prefix = i;
10823           break;
10824         case 0x36:
10825           prefixes |= PREFIX_SS;
10826           last_seg_prefix = i;
10827           break;
10828         case 0x3e:
10829           prefixes |= PREFIX_DS;
10830           last_seg_prefix = i;
10831           break;
10832         case 0x26:
10833           prefixes |= PREFIX_ES;
10834           last_seg_prefix = i;
10835           break;
10836         case 0x64:
10837           prefixes |= PREFIX_FS;
10838           last_seg_prefix = i;
10839           break;
10840         case 0x65:
10841           prefixes |= PREFIX_GS;
10842           last_seg_prefix = i;
10843           break;
10844         case 0x66:
10845           prefixes |= PREFIX_DATA;
10846           last_data_prefix = i;
10847           break;
10848         case 0x67:
10849           prefixes |= PREFIX_ADDR;
10850           last_addr_prefix = i;
10851           break;
10852         case FWAIT_OPCODE:
10853           /* fwait is really an instruction.  If there are prefixes
10854              before the fwait, they belong to the fwait, *not* to the
10855              following instruction.  */
10856           if (prefixes || rex)
10857             {
10858               prefixes |= PREFIX_FWAIT;
10859               codep++;
10860               return 1;
10861             }
10862           prefixes = PREFIX_FWAIT;
10863           break;
10864         default:
10865           return 1;
10866         }
10867       /* Rex is ignored when followed by another prefix.  */
10868       if (rex)
10869         {
10870           rex_used = rex;
10871           return 1;
10872         }
10873       if (*codep != FWAIT_OPCODE)
10874         all_prefixes[i++] = *codep;
10875       rex = newrex;
10876       codep++;
10877       length++;
10878     }
10879   return 0;
10880 }
10881
10882 static int
10883 seg_prefix (int pref)
10884 {
10885   switch (pref)
10886     {
10887     case 0x2e:
10888       return PREFIX_CS;
10889     case 0x36:
10890       return PREFIX_SS;
10891     case 0x3e:
10892       return PREFIX_DS;
10893     case 0x26:
10894       return PREFIX_ES;
10895     case 0x64:
10896       return PREFIX_FS;
10897     case 0x65:
10898       return PREFIX_GS;
10899     default:
10900       return 0;
10901     }
10902 }
10903
10904 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10905    prefix byte.  */
10906
10907 static const char *
10908 prefix_name (int pref, int sizeflag)
10909 {
10910   static const char *rexes [16] =
10911     {
10912       "rex",            /* 0x40 */
10913       "rex.B",          /* 0x41 */
10914       "rex.X",          /* 0x42 */
10915       "rex.XB",         /* 0x43 */
10916       "rex.R",          /* 0x44 */
10917       "rex.RB",         /* 0x45 */
10918       "rex.RX",         /* 0x46 */
10919       "rex.RXB",        /* 0x47 */
10920       "rex.W",          /* 0x48 */
10921       "rex.WB",         /* 0x49 */
10922       "rex.WX",         /* 0x4a */
10923       "rex.WXB",        /* 0x4b */
10924       "rex.WR",         /* 0x4c */
10925       "rex.WRB",        /* 0x4d */
10926       "rex.WRX",        /* 0x4e */
10927       "rex.WRXB",       /* 0x4f */
10928     };
10929
10930   switch (pref)
10931     {
10932     /* REX prefixes family.  */
10933     case 0x40:
10934     case 0x41:
10935     case 0x42:
10936     case 0x43:
10937     case 0x44:
10938     case 0x45:
10939     case 0x46:
10940     case 0x47:
10941     case 0x48:
10942     case 0x49:
10943     case 0x4a:
10944     case 0x4b:
10945     case 0x4c:
10946     case 0x4d:
10947     case 0x4e:
10948     case 0x4f:
10949       return rexes [pref - 0x40];
10950     case 0xf3:
10951       return "repz";
10952     case 0xf2:
10953       return "repnz";
10954     case 0xf0:
10955       return "lock";
10956     case 0x2e:
10957       return "cs";
10958     case 0x36:
10959       return "ss";
10960     case 0x3e:
10961       return "ds";
10962     case 0x26:
10963       return "es";
10964     case 0x64:
10965       return "fs";
10966     case 0x65:
10967       return "gs";
10968     case 0x66:
10969       return (sizeflag & DFLAG) ? "data16" : "data32";
10970     case 0x67:
10971       if (address_mode == mode_64bit)
10972         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10973       else
10974         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10975     case FWAIT_OPCODE:
10976       return "fwait";
10977     case ADDR16_PREFIX:
10978       return "addr16";
10979     case ADDR32_PREFIX:
10980       return "addr32";
10981     case DATA16_PREFIX:
10982       return "data16";
10983     case DATA32_PREFIX:
10984       return "data32";
10985     case REP_PREFIX:
10986       return "rep";
10987     default:
10988       return NULL;
10989     }
10990 }
10991
10992 static char op_out[MAX_OPERANDS][100];
10993 static int op_ad, op_index[MAX_OPERANDS];
10994 static int two_source_ops;
10995 static bfd_vma op_address[MAX_OPERANDS];
10996 static bfd_vma op_riprel[MAX_OPERANDS];
10997 static bfd_vma start_pc;
10998
10999 /*
11000  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11001  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11002  *   section of the "Virtual 8086 Mode" chapter.)
11003  * 'pc' should be the address of this instruction, it will
11004  *   be used to print the target address if this is a relative jump or call
11005  * The function returns the length of this instruction in bytes.
11006  */
11007
11008 static char intel_syntax;
11009 static char intel_mnemonic = !SYSV386_COMPAT;
11010 static char open_char;
11011 static char close_char;
11012 static char separator_char;
11013 static char scale_char;
11014
11015 /* Here for backwards compatibility.  When gdb stops using
11016    print_insn_i386_att and print_insn_i386_intel these functions can
11017    disappear, and print_insn_i386 be merged into print_insn.  */
11018 int
11019 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11020 {
11021   intel_syntax = 0;
11022
11023   return print_insn (pc, info);
11024 }
11025
11026 int
11027 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11028 {
11029   intel_syntax = 1;
11030
11031   return print_insn (pc, info);
11032 }
11033
11034 int
11035 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11036 {
11037   intel_syntax = -1;
11038
11039   return print_insn (pc, info);
11040 }
11041
11042 void
11043 print_i386_disassembler_options (FILE *stream)
11044 {
11045   fprintf (stream, _("\n\
11046 The following i386/x86-64 specific disassembler options are supported for use\n\
11047 with the -M switch (multiple options should be separated by commas):\n"));
11048
11049   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11050   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11051   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11052   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11053   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11054   fprintf (stream, _("  att-mnemonic\n"
11055                      "              Display instruction in AT&T mnemonic\n"));
11056   fprintf (stream, _("  intel-mnemonic\n"
11057                      "              Display instruction in Intel mnemonic\n"));
11058   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11059   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11060   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11061   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11062   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11063   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11064 }
11065
11066 /* Bad opcode.  */
11067 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11068
11069 /* Get a pointer to struct dis386 with a valid name.  */
11070
11071 static const struct dis386 *
11072 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11073 {
11074   int vindex, vex_table_index;
11075
11076   if (dp->name != NULL)
11077     return dp;
11078
11079   switch (dp->op[0].bytemode)
11080     {
11081     case USE_REG_TABLE:
11082       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11083       break;
11084
11085     case USE_MOD_TABLE:
11086       vindex = modrm.mod == 0x3 ? 1 : 0;
11087       dp = &mod_table[dp->op[1].bytemode][vindex];
11088       break;
11089
11090     case USE_RM_TABLE:
11091       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11092       break;
11093
11094     case USE_PREFIX_TABLE:
11095       if (need_vex)
11096         {
11097           /* The prefix in VEX is implicit.  */
11098           switch (vex.prefix)
11099             {
11100             case 0:
11101               vindex = 0;
11102               break;
11103             case REPE_PREFIX_OPCODE:
11104               vindex = 1;
11105               break;
11106             case DATA_PREFIX_OPCODE:
11107               vindex = 2;
11108               break;
11109             case REPNE_PREFIX_OPCODE:
11110               vindex = 3;
11111               break;
11112             default:
11113               abort ();
11114               break;
11115             }
11116         }
11117       else
11118         {
11119           vindex = 0;
11120           used_prefixes |= (prefixes & PREFIX_REPZ);
11121           if (prefixes & PREFIX_REPZ)
11122             {
11123               vindex = 1;
11124               all_prefixes[last_repz_prefix] = 0;
11125             }
11126           else
11127             {
11128               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11129                  PREFIX_DATA.  */
11130               used_prefixes |= (prefixes & PREFIX_REPNZ);
11131               if (prefixes & PREFIX_REPNZ)
11132                 {
11133                   vindex = 3;
11134                   all_prefixes[last_repnz_prefix] = 0;
11135                 }
11136               else
11137                 {
11138                   used_prefixes |= (prefixes & PREFIX_DATA);
11139                   if (prefixes & PREFIX_DATA)
11140                     {
11141                       vindex = 2;
11142                       all_prefixes[last_data_prefix] = 0;
11143                     }
11144                 }
11145             }
11146         }
11147       dp = &prefix_table[dp->op[1].bytemode][vindex];
11148       break;
11149
11150     case USE_X86_64_TABLE:
11151       vindex = address_mode == mode_64bit ? 1 : 0;
11152       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11153       break;
11154
11155     case USE_3BYTE_TABLE:
11156       FETCH_DATA (info, codep + 2);
11157       vindex = *codep++;
11158       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11159       modrm.mod = (*codep >> 6) & 3;
11160       modrm.reg = (*codep >> 3) & 7;
11161       modrm.rm = *codep & 7;
11162       break;
11163
11164     case USE_VEX_LEN_TABLE:
11165       if (!need_vex)
11166         abort ();
11167
11168       switch (vex.length)
11169         {
11170         case 128:
11171           vindex = 0;
11172           break;
11173         case 256:
11174           vindex = 1;
11175           break;
11176         default:
11177           abort ();
11178           break;
11179         }
11180
11181       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11182       break;
11183
11184     case USE_XOP_8F_TABLE:
11185       FETCH_DATA (info, codep + 3);
11186       /* All bits in the REX prefix are ignored.  */
11187       rex_ignored = rex;
11188       rex = ~(*codep >> 5) & 0x7;
11189
11190       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11191       switch ((*codep & 0x1f))
11192         {
11193         default:
11194           dp = &bad_opcode;
11195           return dp;
11196         case 0x8:
11197           vex_table_index = XOP_08;
11198           break;
11199         case 0x9:
11200           vex_table_index = XOP_09;
11201           break;
11202         case 0xa:
11203           vex_table_index = XOP_0A;
11204           break;
11205         }
11206       codep++;
11207       vex.w = *codep & 0x80;
11208       if (vex.w && address_mode == mode_64bit)
11209         rex |= REX_W;
11210
11211       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11212       if (address_mode != mode_64bit
11213           && vex.register_specifier > 0x7)
11214         {
11215           dp = &bad_opcode;
11216           return dp;
11217         }
11218
11219       vex.length = (*codep & 0x4) ? 256 : 128;
11220       switch ((*codep & 0x3))
11221         {
11222         case 0:
11223           vex.prefix = 0;
11224           break;
11225         case 1:
11226           vex.prefix = DATA_PREFIX_OPCODE;
11227           break;
11228         case 2:
11229           vex.prefix = REPE_PREFIX_OPCODE;
11230           break;
11231         case 3:
11232           vex.prefix = REPNE_PREFIX_OPCODE;
11233           break;
11234         }
11235       need_vex = 1;
11236       need_vex_reg = 1;
11237       codep++;
11238       vindex = *codep++;
11239       dp = &xop_table[vex_table_index][vindex];
11240
11241       FETCH_DATA (info, codep + 1);
11242       modrm.mod = (*codep >> 6) & 3;
11243       modrm.reg = (*codep >> 3) & 7;
11244       modrm.rm = *codep & 7;
11245       break;
11246
11247     case USE_VEX_C4_TABLE:
11248       FETCH_DATA (info, codep + 3);
11249       /* All bits in the REX prefix are ignored.  */
11250       rex_ignored = rex;
11251       rex = ~(*codep >> 5) & 0x7;
11252       switch ((*codep & 0x1f))
11253         {
11254         default:
11255           dp = &bad_opcode;
11256           return dp;
11257         case 0x1:
11258           vex_table_index = VEX_0F;
11259           break;
11260         case 0x2:
11261           vex_table_index = VEX_0F38;
11262           break;
11263         case 0x3:
11264           vex_table_index = VEX_0F3A;
11265           break;
11266         }
11267       codep++;
11268       vex.w = *codep & 0x80;
11269       if (vex.w && address_mode == mode_64bit)
11270         rex |= REX_W;
11271
11272       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11273       if (address_mode != mode_64bit
11274           && vex.register_specifier > 0x7)
11275         {
11276           dp = &bad_opcode;
11277           return dp;
11278         }
11279
11280       vex.length = (*codep & 0x4) ? 256 : 128;
11281       switch ((*codep & 0x3))
11282         {
11283         case 0:
11284           vex.prefix = 0;
11285           break;
11286         case 1:
11287           vex.prefix = DATA_PREFIX_OPCODE;
11288           break;
11289         case 2:
11290           vex.prefix = REPE_PREFIX_OPCODE;
11291           break;
11292         case 3:
11293           vex.prefix = REPNE_PREFIX_OPCODE;
11294           break;
11295         }
11296       need_vex = 1;
11297       need_vex_reg = 1;
11298       codep++;
11299       vindex = *codep++;
11300       dp = &vex_table[vex_table_index][vindex];
11301       /* There is no MODRM byte for VEX [82|77].  */
11302       if (vindex != 0x77 && vindex != 0x82)
11303         {
11304           FETCH_DATA (info, codep + 1);
11305           modrm.mod = (*codep >> 6) & 3;
11306           modrm.reg = (*codep >> 3) & 7;
11307           modrm.rm = *codep & 7;
11308         }
11309       break;
11310
11311     case USE_VEX_C5_TABLE:
11312       FETCH_DATA (info, codep + 2);
11313       /* All bits in the REX prefix are ignored.  */
11314       rex_ignored = rex;
11315       rex = (*codep & 0x80) ? 0 : REX_R;
11316
11317       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11318       if (address_mode != mode_64bit
11319           && vex.register_specifier > 0x7)
11320         {
11321           dp = &bad_opcode;
11322           return dp;
11323         }
11324
11325       vex.w = 0;
11326
11327       vex.length = (*codep & 0x4) ? 256 : 128;
11328       switch ((*codep & 0x3))
11329         {
11330         case 0:
11331           vex.prefix = 0;
11332           break;
11333         case 1:
11334           vex.prefix = DATA_PREFIX_OPCODE;
11335           break;
11336         case 2:
11337           vex.prefix = REPE_PREFIX_OPCODE;
11338           break;
11339         case 3:
11340           vex.prefix = REPNE_PREFIX_OPCODE;
11341           break;
11342         }
11343       need_vex = 1;
11344       need_vex_reg = 1;
11345       codep++;
11346       vindex = *codep++;
11347       dp = &vex_table[dp->op[1].bytemode][vindex];
11348       /* There is no MODRM byte for VEX [82|77].  */
11349       if (vindex != 0x77 && vindex != 0x82)
11350         {
11351           FETCH_DATA (info, codep + 1);
11352           modrm.mod = (*codep >> 6) & 3;
11353           modrm.reg = (*codep >> 3) & 7;
11354           modrm.rm = *codep & 7;
11355         }
11356       break;
11357
11358     case USE_VEX_W_TABLE:
11359       if (!need_vex)
11360         abort ();
11361
11362       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11363       break;
11364
11365     case 0:
11366       dp = &bad_opcode;
11367       break;
11368
11369     default:
11370       abort ();
11371     }
11372
11373   if (dp->name != NULL)
11374     return dp;
11375   else
11376     return get_valid_dis386 (dp, info);
11377 }
11378
11379 static void
11380 get_sib (disassemble_info *info)
11381 {
11382   /* If modrm.mod == 3, operand must be register.  */
11383   if (need_modrm
11384       && address_mode != mode_16bit
11385       && modrm.mod != 3
11386       && modrm.rm == 4)
11387     {
11388       FETCH_DATA (info, codep + 2);
11389       sib.index = (codep [1] >> 3) & 7;
11390       sib.scale = (codep [1] >> 6) & 3;
11391       sib.base = codep [1] & 7;
11392     }
11393 }
11394
11395 static int
11396 print_insn (bfd_vma pc, disassemble_info *info)
11397 {
11398   const struct dis386 *dp;
11399   int i;
11400   char *op_txt[MAX_OPERANDS];
11401   int needcomma;
11402   int sizeflag;
11403   const char *p;
11404   struct dis_private priv;
11405   int prefix_length;
11406   int default_prefixes;
11407
11408   if (info->mach == bfd_mach_x86_64_intel_syntax
11409       || info->mach == bfd_mach_x86_64
11410       || info->mach == bfd_mach_x64_32_intel_syntax
11411       || info->mach == bfd_mach_x64_32
11412       || info->mach == bfd_mach_l1om
11413       || info->mach == bfd_mach_l1om_intel_syntax)
11414     address_mode = mode_64bit;
11415   else
11416     address_mode = mode_32bit;
11417
11418   if (intel_syntax == (char) -1)
11419     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11420                     || info->mach == bfd_mach_x86_64_intel_syntax
11421                     || info->mach == bfd_mach_x64_32_intel_syntax
11422                     || info->mach == bfd_mach_l1om_intel_syntax);
11423
11424   if (info->mach == bfd_mach_i386_i386
11425       || info->mach == bfd_mach_x86_64
11426       || info->mach == bfd_mach_x64_32
11427       || info->mach == bfd_mach_l1om
11428       || info->mach == bfd_mach_i386_i386_intel_syntax
11429       || info->mach == bfd_mach_x86_64_intel_syntax
11430       || info->mach == bfd_mach_x64_32_intel_syntax
11431       || info->mach == bfd_mach_l1om_intel_syntax)
11432     priv.orig_sizeflag = AFLAG | DFLAG;
11433   else if (info->mach == bfd_mach_i386_i8086)
11434     priv.orig_sizeflag = 0;
11435   else
11436     abort ();
11437
11438   for (p = info->disassembler_options; p != NULL; )
11439     {
11440       if (CONST_STRNEQ (p, "x86-64"))
11441         {
11442           address_mode = mode_64bit;
11443           priv.orig_sizeflag = AFLAG | DFLAG;
11444         }
11445       else if (CONST_STRNEQ (p, "i386"))
11446         {
11447           address_mode = mode_32bit;
11448           priv.orig_sizeflag = AFLAG | DFLAG;
11449         }
11450       else if (CONST_STRNEQ (p, "i8086"))
11451         {
11452           address_mode = mode_16bit;
11453           priv.orig_sizeflag = 0;
11454         }
11455       else if (CONST_STRNEQ (p, "intel"))
11456         {
11457           intel_syntax = 1;
11458           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11459             intel_mnemonic = 1;
11460         }
11461       else if (CONST_STRNEQ (p, "att"))
11462         {
11463           intel_syntax = 0;
11464           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11465             intel_mnemonic = 0;
11466         }
11467       else if (CONST_STRNEQ (p, "addr"))
11468         {
11469           if (address_mode == mode_64bit)
11470             {
11471               if (p[4] == '3' && p[5] == '2')
11472                 priv.orig_sizeflag &= ~AFLAG;
11473               else if (p[4] == '6' && p[5] == '4')
11474                 priv.orig_sizeflag |= AFLAG;
11475             }
11476           else
11477             {
11478               if (p[4] == '1' && p[5] == '6')
11479                 priv.orig_sizeflag &= ~AFLAG;
11480               else if (p[4] == '3' && p[5] == '2')
11481                 priv.orig_sizeflag |= AFLAG;
11482             }
11483         }
11484       else if (CONST_STRNEQ (p, "data"))
11485         {
11486           if (p[4] == '1' && p[5] == '6')
11487             priv.orig_sizeflag &= ~DFLAG;
11488           else if (p[4] == '3' && p[5] == '2')
11489             priv.orig_sizeflag |= DFLAG;
11490         }
11491       else if (CONST_STRNEQ (p, "suffix"))
11492         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11493
11494       p = strchr (p, ',');
11495       if (p != NULL)
11496         p++;
11497     }
11498
11499   if (intel_syntax)
11500     {
11501       names64 = intel_names64;
11502       names32 = intel_names32;
11503       names16 = intel_names16;
11504       names8 = intel_names8;
11505       names8rex = intel_names8rex;
11506       names_seg = intel_names_seg;
11507       names_mm = intel_names_mm;
11508       names_xmm = intel_names_xmm;
11509       names_ymm = intel_names_ymm;
11510       index64 = intel_index64;
11511       index32 = intel_index32;
11512       index16 = intel_index16;
11513       open_char = '[';
11514       close_char = ']';
11515       separator_char = '+';
11516       scale_char = '*';
11517     }
11518   else
11519     {
11520       names64 = att_names64;
11521       names32 = att_names32;
11522       names16 = att_names16;
11523       names8 = att_names8;
11524       names8rex = att_names8rex;
11525       names_seg = att_names_seg;
11526       names_mm = att_names_mm;
11527       names_xmm = att_names_xmm;
11528       names_ymm = att_names_ymm;
11529       index64 = att_index64;
11530       index32 = att_index32;
11531       index16 = att_index16;
11532       open_char = '(';
11533       close_char =  ')';
11534       separator_char = ',';
11535       scale_char = ',';
11536     }
11537
11538   /* The output looks better if we put 7 bytes on a line, since that
11539      puts most long word instructions on a single line.  Use 8 bytes
11540      for Intel L1OM.  */
11541   if (info->mach == bfd_mach_l1om
11542       || info->mach == bfd_mach_l1om_intel_syntax)
11543     info->bytes_per_line = 8;
11544   else
11545     info->bytes_per_line = 7;
11546
11547   info->private_data = &priv;
11548   priv.max_fetched = priv.the_buffer;
11549   priv.insn_start = pc;
11550
11551   obuf[0] = 0;
11552   for (i = 0; i < MAX_OPERANDS; ++i)
11553     {
11554       op_out[i][0] = 0;
11555       op_index[i] = -1;
11556     }
11557
11558   the_info = info;
11559   start_pc = pc;
11560   start_codep = priv.the_buffer;
11561   codep = priv.the_buffer;
11562
11563   if (setjmp (priv.bailout) != 0)
11564     {
11565       const char *name;
11566
11567       /* Getting here means we tried for data but didn't get it.  That
11568          means we have an incomplete instruction of some sort.  Just
11569          print the first byte as a prefix or a .byte pseudo-op.  */
11570       if (codep > priv.the_buffer)
11571         {
11572           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11573           if (name != NULL)
11574             (*info->fprintf_func) (info->stream, "%s", name);
11575           else
11576             {
11577               /* Just print the first byte as a .byte instruction.  */
11578               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11579                                      (unsigned int) priv.the_buffer[0]);
11580             }
11581
11582           return 1;
11583         }
11584
11585       return -1;
11586     }
11587
11588   obufp = obuf;
11589   sizeflag = priv.orig_sizeflag;
11590
11591   if (!ckprefix () || rex_used)
11592     {
11593       /* Too many prefixes or unused REX prefixes.  */
11594       for (i = 0;
11595            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11596            i++)
11597         (*info->fprintf_func) (info->stream, "%s",
11598                                prefix_name (all_prefixes[i], sizeflag));
11599       return 1;
11600     }
11601
11602   insn_codep = codep;
11603
11604   FETCH_DATA (info, codep + 1);
11605   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11606
11607   if (((prefixes & PREFIX_FWAIT)
11608        && ((*codep < 0xd8) || (*codep > 0xdf))))
11609     {
11610       (*info->fprintf_func) (info->stream, "fwait");
11611       return 1;
11612     }
11613
11614   if (*codep == 0x0f)
11615     {
11616       unsigned char threebyte;
11617       FETCH_DATA (info, codep + 2);
11618       threebyte = *++codep;
11619       dp = &dis386_twobyte[threebyte];
11620       need_modrm = twobyte_has_modrm[*codep];
11621       codep++;
11622     }
11623   else
11624     {
11625       dp = &dis386[*codep];
11626       need_modrm = onebyte_has_modrm[*codep];
11627       codep++;
11628     }
11629
11630   if ((prefixes & PREFIX_REPZ))
11631     used_prefixes |= PREFIX_REPZ;
11632   if ((prefixes & PREFIX_REPNZ))
11633     used_prefixes |= PREFIX_REPNZ;
11634   if ((prefixes & PREFIX_LOCK))
11635     used_prefixes |= PREFIX_LOCK;
11636
11637   default_prefixes = 0;
11638   if (prefixes & PREFIX_ADDR)
11639     {
11640       sizeflag ^= AFLAG;
11641       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11642         {
11643           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11644             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11645           else
11646             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11647           default_prefixes |= PREFIX_ADDR;
11648         }
11649     }
11650
11651   if ((prefixes & PREFIX_DATA))
11652     {
11653       sizeflag ^= DFLAG;
11654       if (dp->op[2].bytemode == cond_jump_mode
11655           && dp->op[0].bytemode == v_mode
11656           && !intel_syntax)
11657         {
11658           if (sizeflag & DFLAG)
11659             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11660           else
11661             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11662           default_prefixes |= PREFIX_DATA;
11663         }
11664       else if (rex & REX_W)
11665         {
11666           /* REX_W will override PREFIX_DATA.  */
11667           default_prefixes |= PREFIX_DATA;
11668         }
11669     }
11670
11671   if (need_modrm)
11672     {
11673       FETCH_DATA (info, codep + 1);
11674       modrm.mod = (*codep >> 6) & 3;
11675       modrm.reg = (*codep >> 3) & 7;
11676       modrm.rm = *codep & 7;
11677     }
11678
11679    need_vex = 0;
11680    need_vex_reg = 0;
11681    vex_w_done = 0;
11682
11683   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11684     {
11685       get_sib (info);
11686       dofloat (sizeflag);
11687     }
11688   else
11689     {
11690       dp = get_valid_dis386 (dp, info);
11691       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11692         {
11693           get_sib (info);
11694           for (i = 0; i < MAX_OPERANDS; ++i)
11695             {
11696               obufp = op_out[i];
11697               op_ad = MAX_OPERANDS - 1 - i;
11698               if (dp->op[i].rtn)
11699                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11700             }
11701         }
11702     }
11703
11704   /* See if any prefixes were not used.  If so, print the first one
11705      separately.  If we don't do this, we'll wind up printing an
11706      instruction stream which does not precisely correspond to the
11707      bytes we are disassembling.  */
11708   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11709     {
11710       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11711         if (all_prefixes[i])
11712           {
11713             const char *name;
11714             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11715             if (name == NULL)
11716               name = INTERNAL_DISASSEMBLER_ERROR;
11717             (*info->fprintf_func) (info->stream, "%s", name);
11718             return 1;
11719           }
11720     }
11721
11722   /* Check if the REX prefix is used.  */
11723   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11724     all_prefixes[last_rex_prefix] = 0;
11725
11726   /* Check if the SEG prefix is used.  */
11727   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11728                    | PREFIX_FS | PREFIX_GS)) != 0
11729       && (used_prefixes
11730           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11731     all_prefixes[last_seg_prefix] = 0;
11732
11733   /* Check if the ADDR prefix is used.  */
11734   if ((prefixes & PREFIX_ADDR) != 0
11735       && (used_prefixes & PREFIX_ADDR) != 0)
11736     all_prefixes[last_addr_prefix] = 0;
11737
11738   /* Check if the DATA prefix is used.  */
11739   if ((prefixes & PREFIX_DATA) != 0
11740       && (used_prefixes & PREFIX_DATA) != 0)
11741     all_prefixes[last_data_prefix] = 0;
11742
11743   prefix_length = 0;
11744   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11745     if (all_prefixes[i])
11746       {
11747         const char *name;
11748         name = prefix_name (all_prefixes[i], sizeflag);
11749         if (name == NULL)
11750           abort ();
11751         prefix_length += strlen (name) + 1;
11752         (*info->fprintf_func) (info->stream, "%s ", name);
11753       }
11754
11755   /* Check maximum code length.  */
11756   if ((codep - start_codep) > MAX_CODE_LENGTH)
11757     {
11758       (*info->fprintf_func) (info->stream, "(bad)");
11759       return MAX_CODE_LENGTH;
11760     }
11761
11762   obufp = mnemonicendp;
11763   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11764     oappend (" ");
11765   oappend (" ");
11766   (*info->fprintf_func) (info->stream, "%s", obuf);
11767
11768   /* The enter and bound instructions are printed with operands in the same
11769      order as the intel book; everything else is printed in reverse order.  */
11770   if (intel_syntax || two_source_ops)
11771     {
11772       bfd_vma riprel;
11773
11774       for (i = 0; i < MAX_OPERANDS; ++i)
11775         op_txt[i] = op_out[i];
11776
11777       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11778         {
11779           op_ad = op_index[i];
11780           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11781           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11782           riprel = op_riprel[i];
11783           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11784           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11785         }
11786     }
11787   else
11788     {
11789       for (i = 0; i < MAX_OPERANDS; ++i)
11790         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11791     }
11792
11793   needcomma = 0;
11794   for (i = 0; i < MAX_OPERANDS; ++i)
11795     if (*op_txt[i])
11796       {
11797         if (needcomma)
11798           (*info->fprintf_func) (info->stream, ",");
11799         if (op_index[i] != -1 && !op_riprel[i])
11800           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11801         else
11802           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11803         needcomma = 1;
11804       }
11805
11806   for (i = 0; i < MAX_OPERANDS; i++)
11807     if (op_index[i] != -1 && op_riprel[i])
11808       {
11809         (*info->fprintf_func) (info->stream, "        # ");
11810         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11811                                                 + op_address[op_index[i]]), info);
11812         break;
11813       }
11814   return codep - priv.the_buffer;
11815 }
11816
11817 static const char *float_mem[] = {
11818   /* d8 */
11819   "fadd{s|}",
11820   "fmul{s|}",
11821   "fcom{s|}",
11822   "fcomp{s|}",
11823   "fsub{s|}",
11824   "fsubr{s|}",
11825   "fdiv{s|}",
11826   "fdivr{s|}",
11827   /* d9 */
11828   "fld{s|}",
11829   "(bad)",
11830   "fst{s|}",
11831   "fstp{s|}",
11832   "fldenvIC",
11833   "fldcw",
11834   "fNstenvIC",
11835   "fNstcw",
11836   /* da */
11837   "fiadd{l|}",
11838   "fimul{l|}",
11839   "ficom{l|}",
11840   "ficomp{l|}",
11841   "fisub{l|}",
11842   "fisubr{l|}",
11843   "fidiv{l|}",
11844   "fidivr{l|}",
11845   /* db */
11846   "fild{l|}",
11847   "fisttp{l|}",
11848   "fist{l|}",
11849   "fistp{l|}",
11850   "(bad)",
11851   "fld{t||t|}",
11852   "(bad)",
11853   "fstp{t||t|}",
11854   /* dc */
11855   "fadd{l|}",
11856   "fmul{l|}",
11857   "fcom{l|}",
11858   "fcomp{l|}",
11859   "fsub{l|}",
11860   "fsubr{l|}",
11861   "fdiv{l|}",
11862   "fdivr{l|}",
11863   /* dd */
11864   "fld{l|}",
11865   "fisttp{ll|}",
11866   "fst{l||}",
11867   "fstp{l|}",
11868   "frstorIC",
11869   "(bad)",
11870   "fNsaveIC",
11871   "fNstsw",
11872   /* de */
11873   "fiadd",
11874   "fimul",
11875   "ficom",
11876   "ficomp",
11877   "fisub",
11878   "fisubr",
11879   "fidiv",
11880   "fidivr",
11881   /* df */
11882   "fild",
11883   "fisttp",
11884   "fist",
11885   "fistp",
11886   "fbld",
11887   "fild{ll|}",
11888   "fbstp",
11889   "fistp{ll|}",
11890 };
11891
11892 static const unsigned char float_mem_mode[] = {
11893   /* d8 */
11894   d_mode,
11895   d_mode,
11896   d_mode,
11897   d_mode,
11898   d_mode,
11899   d_mode,
11900   d_mode,
11901   d_mode,
11902   /* d9 */
11903   d_mode,
11904   0,
11905   d_mode,
11906   d_mode,
11907   0,
11908   w_mode,
11909   0,
11910   w_mode,
11911   /* da */
11912   d_mode,
11913   d_mode,
11914   d_mode,
11915   d_mode,
11916   d_mode,
11917   d_mode,
11918   d_mode,
11919   d_mode,
11920   /* db */
11921   d_mode,
11922   d_mode,
11923   d_mode,
11924   d_mode,
11925   0,
11926   t_mode,
11927   0,
11928   t_mode,
11929   /* dc */
11930   q_mode,
11931   q_mode,
11932   q_mode,
11933   q_mode,
11934   q_mode,
11935   q_mode,
11936   q_mode,
11937   q_mode,
11938   /* dd */
11939   q_mode,
11940   q_mode,
11941   q_mode,
11942   q_mode,
11943   0,
11944   0,
11945   0,
11946   w_mode,
11947   /* de */
11948   w_mode,
11949   w_mode,
11950   w_mode,
11951   w_mode,
11952   w_mode,
11953   w_mode,
11954   w_mode,
11955   w_mode,
11956   /* df */
11957   w_mode,
11958   w_mode,
11959   w_mode,
11960   w_mode,
11961   t_mode,
11962   q_mode,
11963   t_mode,
11964   q_mode
11965 };
11966
11967 #define ST { OP_ST, 0 }
11968 #define STi { OP_STi, 0 }
11969
11970 #define FGRPd9_2 NULL, { { NULL, 0 } }
11971 #define FGRPd9_4 NULL, { { NULL, 1 } }
11972 #define FGRPd9_5 NULL, { { NULL, 2 } }
11973 #define FGRPd9_6 NULL, { { NULL, 3 } }
11974 #define FGRPd9_7 NULL, { { NULL, 4 } }
11975 #define FGRPda_5 NULL, { { NULL, 5 } }
11976 #define FGRPdb_4 NULL, { { NULL, 6 } }
11977 #define FGRPde_3 NULL, { { NULL, 7 } }
11978 #define FGRPdf_4 NULL, { { NULL, 8 } }
11979
11980 static const struct dis386 float_reg[][8] = {
11981   /* d8 */
11982   {
11983     { "fadd",   { ST, STi } },
11984     { "fmul",   { ST, STi } },
11985     { "fcom",   { STi } },
11986     { "fcomp",  { STi } },
11987     { "fsub",   { ST, STi } },
11988     { "fsubr",  { ST, STi } },
11989     { "fdiv",   { ST, STi } },
11990     { "fdivr",  { ST, STi } },
11991   },
11992   /* d9 */
11993   {
11994     { "fld",    { STi } },
11995     { "fxch",   { STi } },
11996     { FGRPd9_2 },
11997     { Bad_Opcode },
11998     { FGRPd9_4 },
11999     { FGRPd9_5 },
12000     { FGRPd9_6 },
12001     { FGRPd9_7 },
12002   },
12003   /* da */
12004   {
12005     { "fcmovb", { ST, STi } },
12006     { "fcmove", { ST, STi } },
12007     { "fcmovbe",{ ST, STi } },
12008     { "fcmovu", { ST, STi } },
12009     { Bad_Opcode },
12010     { FGRPda_5 },
12011     { Bad_Opcode },
12012     { Bad_Opcode },
12013   },
12014   /* db */
12015   {
12016     { "fcmovnb",{ ST, STi } },
12017     { "fcmovne",{ ST, STi } },
12018     { "fcmovnbe",{ ST, STi } },
12019     { "fcmovnu",{ ST, STi } },
12020     { FGRPdb_4 },
12021     { "fucomi", { ST, STi } },
12022     { "fcomi",  { ST, STi } },
12023     { Bad_Opcode },
12024   },
12025   /* dc */
12026   {
12027     { "fadd",   { STi, ST } },
12028     { "fmul",   { STi, ST } },
12029     { Bad_Opcode },
12030     { Bad_Opcode },
12031     { "fsub!M", { STi, ST } },
12032     { "fsubM",  { STi, ST } },
12033     { "fdiv!M", { STi, ST } },
12034     { "fdivM",  { STi, ST } },
12035   },
12036   /* dd */
12037   {
12038     { "ffree",  { STi } },
12039     { Bad_Opcode },
12040     { "fst",    { STi } },
12041     { "fstp",   { STi } },
12042     { "fucom",  { STi } },
12043     { "fucomp", { STi } },
12044     { Bad_Opcode },
12045     { Bad_Opcode },
12046   },
12047   /* de */
12048   {
12049     { "faddp",  { STi, ST } },
12050     { "fmulp",  { STi, ST } },
12051     { Bad_Opcode },
12052     { FGRPde_3 },
12053     { "fsub!Mp", { STi, ST } },
12054     { "fsubMp", { STi, ST } },
12055     { "fdiv!Mp", { STi, ST } },
12056     { "fdivMp", { STi, ST } },
12057   },
12058   /* df */
12059   {
12060     { "ffreep", { STi } },
12061     { Bad_Opcode },
12062     { Bad_Opcode },
12063     { Bad_Opcode },
12064     { FGRPdf_4 },
12065     { "fucomip", { ST, STi } },
12066     { "fcomip", { ST, STi } },
12067     { Bad_Opcode },
12068   },
12069 };
12070
12071 static char *fgrps[][8] = {
12072   /* d9_2  0 */
12073   {
12074     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12075   },
12076
12077   /* d9_4  1 */
12078   {
12079     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12080   },
12081
12082   /* d9_5  2 */
12083   {
12084     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12085   },
12086
12087   /* d9_6  3 */
12088   {
12089     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12090   },
12091
12092   /* d9_7  4 */
12093   {
12094     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12095   },
12096
12097   /* da_5  5 */
12098   {
12099     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12100   },
12101
12102   /* db_4  6 */
12103   {
12104     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12105     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12106   },
12107
12108   /* de_3  7 */
12109   {
12110     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12111   },
12112
12113   /* df_4  8 */
12114   {
12115     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12116   },
12117 };
12118
12119 static void
12120 swap_operand (void)
12121 {
12122   mnemonicendp[0] = '.';
12123   mnemonicendp[1] = 's';
12124   mnemonicendp += 2;
12125 }
12126
12127 static void
12128 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12129                int sizeflag ATTRIBUTE_UNUSED)
12130 {
12131   /* Skip mod/rm byte.  */
12132   MODRM_CHECK;
12133   codep++;
12134 }
12135
12136 static void
12137 dofloat (int sizeflag)
12138 {
12139   const struct dis386 *dp;
12140   unsigned char floatop;
12141
12142   floatop = codep[-1];
12143
12144   if (modrm.mod != 3)
12145     {
12146       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12147
12148       putop (float_mem[fp_indx], sizeflag);
12149       obufp = op_out[0];
12150       op_ad = 2;
12151       OP_E (float_mem_mode[fp_indx], sizeflag);
12152       return;
12153     }
12154   /* Skip mod/rm byte.  */
12155   MODRM_CHECK;
12156   codep++;
12157
12158   dp = &float_reg[floatop - 0xd8][modrm.reg];
12159   if (dp->name == NULL)
12160     {
12161       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12162
12163       /* Instruction fnstsw is only one with strange arg.  */
12164       if (floatop == 0xdf && codep[-1] == 0xe0)
12165         strcpy (op_out[0], names16[0]);
12166     }
12167   else
12168     {
12169       putop (dp->name, sizeflag);
12170
12171       obufp = op_out[0];
12172       op_ad = 2;
12173       if (dp->op[0].rtn)
12174         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12175
12176       obufp = op_out[1];
12177       op_ad = 1;
12178       if (dp->op[1].rtn)
12179         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12180     }
12181 }
12182
12183 static void
12184 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12185 {
12186   oappend ("%st" + intel_syntax);
12187 }
12188
12189 static void
12190 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12191 {
12192   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12193   oappend (scratchbuf + intel_syntax);
12194 }
12195
12196 /* Capital letters in template are macros.  */
12197 static int
12198 putop (const char *in_template, int sizeflag)
12199 {
12200   const char *p;
12201   int alt = 0;
12202   int cond = 1;
12203   unsigned int l = 0, len = 1;
12204   char last[4];
12205
12206 #define SAVE_LAST(c)                    \
12207   if (l < len && l < sizeof (last))     \
12208     last[l++] = c;                      \
12209   else                                  \
12210     abort ();
12211
12212   for (p = in_template; *p; p++)
12213     {
12214       switch (*p)
12215         {
12216         default:
12217           *obufp++ = *p;
12218           break;
12219         case '%':
12220           len++;
12221           break;
12222         case '!':
12223           cond = 0;
12224           break;
12225         case '{':
12226           alt = 0;
12227           if (intel_syntax)
12228             {
12229               while (*++p != '|')
12230                 if (*p == '}' || *p == '\0')
12231                   abort ();
12232             }
12233           /* Fall through.  */
12234         case 'I':
12235           alt = 1;
12236           continue;
12237         case '|':
12238           while (*++p != '}')
12239             {
12240               if (*p == '\0')
12241                 abort ();
12242             }
12243           break;
12244         case '}':
12245           break;
12246         case 'A':
12247           if (intel_syntax)
12248             break;
12249           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12250             *obufp++ = 'b';
12251           break;
12252         case 'B':
12253           if (l == 0 && len == 1)
12254             {
12255 case_B:
12256               if (intel_syntax)
12257                 break;
12258               if (sizeflag & SUFFIX_ALWAYS)
12259                 *obufp++ = 'b';
12260             }
12261           else
12262             {
12263               if (l != 1
12264                   || len != 2
12265                   || last[0] != 'L')
12266                 {
12267                   SAVE_LAST (*p);
12268                   break;
12269                 }
12270
12271               if (address_mode == mode_64bit
12272                   && !(prefixes & PREFIX_ADDR))
12273                 {
12274                   *obufp++ = 'a';
12275                   *obufp++ = 'b';
12276                   *obufp++ = 's';
12277                 }
12278
12279               goto case_B;
12280             }
12281           break;
12282         case 'C':
12283           if (intel_syntax && !alt)
12284             break;
12285           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12286             {
12287               if (sizeflag & DFLAG)
12288                 *obufp++ = intel_syntax ? 'd' : 'l';
12289               else
12290                 *obufp++ = intel_syntax ? 'w' : 's';
12291               used_prefixes |= (prefixes & PREFIX_DATA);
12292             }
12293           break;
12294         case 'D':
12295           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12296             break;
12297           USED_REX (REX_W);
12298           if (modrm.mod == 3)
12299             {
12300               if (rex & REX_W)
12301                 *obufp++ = 'q';
12302               else
12303                 {
12304                   if (sizeflag & DFLAG)
12305                     *obufp++ = intel_syntax ? 'd' : 'l';
12306                   else
12307                     *obufp++ = 'w';
12308                   used_prefixes |= (prefixes & PREFIX_DATA);
12309                 }
12310             }
12311           else
12312             *obufp++ = 'w';
12313           break;
12314         case 'E':               /* For jcxz/jecxz */
12315           if (address_mode == mode_64bit)
12316             {
12317               if (sizeflag & AFLAG)
12318                 *obufp++ = 'r';
12319               else
12320                 *obufp++ = 'e';
12321             }
12322           else
12323             if (sizeflag & AFLAG)
12324               *obufp++ = 'e';
12325           used_prefixes |= (prefixes & PREFIX_ADDR);
12326           break;
12327         case 'F':
12328           if (intel_syntax)
12329             break;
12330           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12331             {
12332               if (sizeflag & AFLAG)
12333                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12334               else
12335                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12336               used_prefixes |= (prefixes & PREFIX_ADDR);
12337             }
12338           break;
12339         case 'G':
12340           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12341             break;
12342           if ((rex & REX_W) || (sizeflag & DFLAG))
12343             *obufp++ = 'l';
12344           else
12345             *obufp++ = 'w';
12346           if (!(rex & REX_W))
12347             used_prefixes |= (prefixes & PREFIX_DATA);
12348           break;
12349         case 'H':
12350           if (intel_syntax)
12351             break;
12352           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12353               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12354             {
12355               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12356               *obufp++ = ',';
12357               *obufp++ = 'p';
12358               if (prefixes & PREFIX_DS)
12359                 *obufp++ = 't';
12360               else
12361                 *obufp++ = 'n';
12362             }
12363           break;
12364         case 'J':
12365           if (intel_syntax)
12366             break;
12367           *obufp++ = 'l';
12368           break;
12369         case 'K':
12370           USED_REX (REX_W);
12371           if (rex & REX_W)
12372             *obufp++ = 'q';
12373           else
12374             *obufp++ = 'd';
12375           break;
12376         case 'Z':
12377           if (intel_syntax)
12378             break;
12379           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12380             {
12381               *obufp++ = 'q';
12382               break;
12383             }
12384           /* Fall through.  */
12385           goto case_L;
12386         case 'L':
12387           if (l != 0 || len != 1)
12388             {
12389               SAVE_LAST (*p);
12390               break;
12391             }
12392 case_L:
12393           if (intel_syntax)
12394             break;
12395           if (sizeflag & SUFFIX_ALWAYS)
12396             *obufp++ = 'l';
12397           break;
12398         case 'M':
12399           if (intel_mnemonic != cond)
12400             *obufp++ = 'r';
12401           break;
12402         case 'N':
12403           if ((prefixes & PREFIX_FWAIT) == 0)
12404             *obufp++ = 'n';
12405           else
12406             used_prefixes |= PREFIX_FWAIT;
12407           break;
12408         case 'O':
12409           USED_REX (REX_W);
12410           if (rex & REX_W)
12411             *obufp++ = 'o';
12412           else if (intel_syntax && (sizeflag & DFLAG))
12413             *obufp++ = 'q';
12414           else
12415             *obufp++ = 'd';
12416           if (!(rex & REX_W))
12417             used_prefixes |= (prefixes & PREFIX_DATA);
12418           break;
12419         case 'T':
12420           if (!intel_syntax
12421               && address_mode == mode_64bit
12422               && (sizeflag & DFLAG))
12423             {
12424               *obufp++ = 'q';
12425               break;
12426             }
12427           /* Fall through.  */
12428         case 'P':
12429           if (intel_syntax)
12430             {
12431               if ((rex & REX_W) == 0
12432                   && (prefixes & PREFIX_DATA))
12433                 {
12434                   if ((sizeflag & DFLAG) == 0)
12435                     *obufp++ = 'w';
12436                    used_prefixes |= (prefixes & PREFIX_DATA);
12437                 }
12438               break;
12439             }
12440           if ((prefixes & PREFIX_DATA)
12441               || (rex & REX_W)
12442               || (sizeflag & SUFFIX_ALWAYS))
12443             {
12444               USED_REX (REX_W);
12445               if (rex & REX_W)
12446                 *obufp++ = 'q';
12447               else
12448                 {
12449                    if (sizeflag & DFLAG)
12450                       *obufp++ = 'l';
12451                    else
12452                      *obufp++ = 'w';
12453                    used_prefixes |= (prefixes & PREFIX_DATA);
12454                 }
12455             }
12456           break;
12457         case 'U':
12458           if (intel_syntax)
12459             break;
12460           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12461             {
12462               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12463                 *obufp++ = 'q';
12464               break;
12465             }
12466           /* Fall through.  */
12467           goto case_Q;
12468         case 'Q':
12469           if (l == 0 && len == 1)
12470             {
12471 case_Q:
12472               if (intel_syntax && !alt)
12473                 break;
12474               USED_REX (REX_W);
12475               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12476                 {
12477                   if (rex & REX_W)
12478                     *obufp++ = 'q';
12479                   else
12480                     {
12481                       if (sizeflag & DFLAG)
12482                         *obufp++ = intel_syntax ? 'd' : 'l';
12483                       else
12484                         *obufp++ = 'w';
12485                       used_prefixes |= (prefixes & PREFIX_DATA);
12486                     }
12487                 }
12488             }
12489           else
12490             {
12491               if (l != 1 || len != 2 || last[0] != 'L')
12492                 {
12493                   SAVE_LAST (*p);
12494                   break;
12495                 }
12496               if (intel_syntax
12497                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12498                 break;
12499               if ((rex & REX_W))
12500                 {
12501                   USED_REX (REX_W);
12502                   *obufp++ = 'q';
12503                 }
12504               else
12505                 *obufp++ = 'l';
12506             }
12507           break;
12508         case 'R':
12509           USED_REX (REX_W);
12510           if (rex & REX_W)
12511             *obufp++ = 'q';
12512           else if (sizeflag & DFLAG)
12513             {
12514               if (intel_syntax)
12515                   *obufp++ = 'd';
12516               else
12517                   *obufp++ = 'l';
12518             }
12519           else
12520             *obufp++ = 'w';
12521           if (intel_syntax && !p[1]
12522               && ((rex & REX_W) || (sizeflag & DFLAG)))
12523             *obufp++ = 'e';
12524           if (!(rex & REX_W))
12525             used_prefixes |= (prefixes & PREFIX_DATA);
12526           break;
12527         case 'V':
12528           if (l == 0 && len == 1)
12529             {
12530               if (intel_syntax)
12531                 break;
12532               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12533                 {
12534                   if (sizeflag & SUFFIX_ALWAYS)
12535                     *obufp++ = 'q';
12536                   break;
12537                 }
12538             }
12539           else
12540             {
12541               if (l != 1
12542                   || len != 2
12543                   || last[0] != 'L')
12544                 {
12545                   SAVE_LAST (*p);
12546                   break;
12547                 }
12548
12549               if (rex & REX_W)
12550                 {
12551                   *obufp++ = 'a';
12552                   *obufp++ = 'b';
12553                   *obufp++ = 's';
12554                 }
12555             }
12556           /* Fall through.  */
12557           goto case_S;
12558         case 'S':
12559           if (l == 0 && len == 1)
12560             {
12561 case_S:
12562               if (intel_syntax)
12563                 break;
12564               if (sizeflag & SUFFIX_ALWAYS)
12565                 {
12566                   if (rex & REX_W)
12567                     *obufp++ = 'q';
12568                   else
12569                     {
12570                       if (sizeflag & DFLAG)
12571                         *obufp++ = 'l';
12572                       else
12573                         *obufp++ = 'w';
12574                       used_prefixes |= (prefixes & PREFIX_DATA);
12575                     }
12576                 }
12577             }
12578           else
12579             {
12580               if (l != 1
12581                   || len != 2
12582                   || last[0] != 'L')
12583                 {
12584                   SAVE_LAST (*p);
12585                   break;
12586                 }
12587
12588               if (address_mode == mode_64bit
12589                   && !(prefixes & PREFIX_ADDR))
12590                 {
12591                   *obufp++ = 'a';
12592                   *obufp++ = 'b';
12593                   *obufp++ = 's';
12594                 }
12595
12596               goto case_S;
12597             }
12598           break;
12599         case 'X':
12600           if (l != 0 || len != 1)
12601             {
12602               SAVE_LAST (*p);
12603               break;
12604             }
12605           if (need_vex && vex.prefix)
12606             {
12607               if (vex.prefix == DATA_PREFIX_OPCODE)
12608                 *obufp++ = 'd';
12609               else
12610                 *obufp++ = 's';
12611             }
12612           else
12613             {
12614               if (prefixes & PREFIX_DATA)
12615                 *obufp++ = 'd';
12616               else
12617                 *obufp++ = 's';
12618               used_prefixes |= (prefixes & PREFIX_DATA);
12619             }
12620           break;
12621         case 'Y':
12622           if (l == 0 && len == 1)
12623             {
12624               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12625                 break;
12626               if (rex & REX_W)
12627                 {
12628                   USED_REX (REX_W);
12629                   *obufp++ = 'q';
12630                 }
12631               break;
12632             }
12633           else
12634             {
12635               if (l != 1 || len != 2 || last[0] != 'X')
12636                 {
12637                   SAVE_LAST (*p);
12638                   break;
12639                 }
12640               if (!need_vex)
12641                 abort ();
12642               if (intel_syntax
12643                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12644                 break;
12645               switch (vex.length)
12646                 {
12647                 case 128:
12648                   *obufp++ = 'x';
12649                   break;
12650                 case 256:
12651                   *obufp++ = 'y';
12652                   break;
12653                 default:
12654                   abort ();
12655                 }
12656             }
12657           break;
12658         case 'W':
12659           if (l == 0 && len == 1)
12660             {
12661               /* operand size flag for cwtl, cbtw */
12662               USED_REX (REX_W);
12663               if (rex & REX_W)
12664                 {
12665                   if (intel_syntax)
12666                     *obufp++ = 'd';
12667                   else
12668                     *obufp++ = 'l';
12669                 }
12670               else if (sizeflag & DFLAG)
12671                 *obufp++ = 'w';
12672               else
12673                 *obufp++ = 'b';
12674               if (!(rex & REX_W))
12675                 used_prefixes |= (prefixes & PREFIX_DATA);
12676             }
12677           else
12678             {
12679               if (l != 1 || len != 2 || last[0] != 'X')
12680                 {
12681                   SAVE_LAST (*p);
12682                   break;
12683                 }
12684               if (!need_vex)
12685                 abort ();
12686               *obufp++ = vex.w ? 'd': 's';
12687             }
12688           break;
12689         }
12690       alt = 0;
12691     }
12692   *obufp = 0;
12693   mnemonicendp = obufp;
12694   return 0;
12695 }
12696
12697 static void
12698 oappend (const char *s)
12699 {
12700   obufp = stpcpy (obufp, s);
12701 }
12702
12703 static void
12704 append_seg (void)
12705 {
12706   if (prefixes & PREFIX_CS)
12707     {
12708       used_prefixes |= PREFIX_CS;
12709       oappend ("%cs:" + intel_syntax);
12710     }
12711   if (prefixes & PREFIX_DS)
12712     {
12713       used_prefixes |= PREFIX_DS;
12714       oappend ("%ds:" + intel_syntax);
12715     }
12716   if (prefixes & PREFIX_SS)
12717     {
12718       used_prefixes |= PREFIX_SS;
12719       oappend ("%ss:" + intel_syntax);
12720     }
12721   if (prefixes & PREFIX_ES)
12722     {
12723       used_prefixes |= PREFIX_ES;
12724       oappend ("%es:" + intel_syntax);
12725     }
12726   if (prefixes & PREFIX_FS)
12727     {
12728       used_prefixes |= PREFIX_FS;
12729       oappend ("%fs:" + intel_syntax);
12730     }
12731   if (prefixes & PREFIX_GS)
12732     {
12733       used_prefixes |= PREFIX_GS;
12734       oappend ("%gs:" + intel_syntax);
12735     }
12736 }
12737
12738 static void
12739 OP_indirE (int bytemode, int sizeflag)
12740 {
12741   if (!intel_syntax)
12742     oappend ("*");
12743   OP_E (bytemode, sizeflag);
12744 }
12745
12746 static void
12747 print_operand_value (char *buf, int hex, bfd_vma disp)
12748 {
12749   if (address_mode == mode_64bit)
12750     {
12751       if (hex)
12752         {
12753           char tmp[30];
12754           int i;
12755           buf[0] = '0';
12756           buf[1] = 'x';
12757           sprintf_vma (tmp, disp);
12758           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12759           strcpy (buf + 2, tmp + i);
12760         }
12761       else
12762         {
12763           bfd_signed_vma v = disp;
12764           char tmp[30];
12765           int i;
12766           if (v < 0)
12767             {
12768               *(buf++) = '-';
12769               v = -disp;
12770               /* Check for possible overflow on 0x8000000000000000.  */
12771               if (v < 0)
12772                 {
12773                   strcpy (buf, "9223372036854775808");
12774                   return;
12775                 }
12776             }
12777           if (!v)
12778             {
12779               strcpy (buf, "0");
12780               return;
12781             }
12782
12783           i = 0;
12784           tmp[29] = 0;
12785           while (v)
12786             {
12787               tmp[28 - i] = (v % 10) + '0';
12788               v /= 10;
12789               i++;
12790             }
12791           strcpy (buf, tmp + 29 - i);
12792         }
12793     }
12794   else
12795     {
12796       if (hex)
12797         sprintf (buf, "0x%x", (unsigned int) disp);
12798       else
12799         sprintf (buf, "%d", (int) disp);
12800     }
12801 }
12802
12803 /* Put DISP in BUF as signed hex number.  */
12804
12805 static void
12806 print_displacement (char *buf, bfd_vma disp)
12807 {
12808   bfd_signed_vma val = disp;
12809   char tmp[30];
12810   int i, j = 0;
12811
12812   if (val < 0)
12813     {
12814       buf[j++] = '-';
12815       val = -disp;
12816
12817       /* Check for possible overflow.  */
12818       if (val < 0)
12819         {
12820           switch (address_mode)
12821             {
12822             case mode_64bit:
12823               strcpy (buf + j, "0x8000000000000000");
12824               break;
12825             case mode_32bit:
12826               strcpy (buf + j, "0x80000000");
12827               break;
12828             case mode_16bit:
12829               strcpy (buf + j, "0x8000");
12830               break;
12831             }
12832           return;
12833         }
12834     }
12835
12836   buf[j++] = '0';
12837   buf[j++] = 'x';
12838
12839   sprintf_vma (tmp, (bfd_vma) val);
12840   for (i = 0; tmp[i] == '0'; i++)
12841     continue;
12842   if (tmp[i] == '\0')
12843     i--;
12844   strcpy (buf + j, tmp + i);
12845 }
12846
12847 static void
12848 intel_operand_size (int bytemode, int sizeflag)
12849 {
12850   switch (bytemode)
12851     {
12852     case b_mode:
12853     case b_swap_mode:
12854     case dqb_mode:
12855       oappend ("BYTE PTR ");
12856       break;
12857     case w_mode:
12858     case dqw_mode:
12859       oappend ("WORD PTR ");
12860       break;
12861     case stack_v_mode:
12862       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12863         {
12864           oappend ("QWORD PTR ");
12865           break;
12866         }
12867       /* FALLTHRU */
12868     case v_mode:
12869     case v_swap_mode:
12870     case dq_mode:
12871       USED_REX (REX_W);
12872       if (rex & REX_W)
12873         oappend ("QWORD PTR ");
12874       else
12875         {
12876           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12877             oappend ("DWORD PTR ");
12878           else
12879             oappend ("WORD PTR ");
12880           used_prefixes |= (prefixes & PREFIX_DATA);
12881         }
12882       break;
12883     case z_mode:
12884       if ((rex & REX_W) || (sizeflag & DFLAG))
12885         *obufp++ = 'D';
12886       oappend ("WORD PTR ");
12887       if (!(rex & REX_W))
12888         used_prefixes |= (prefixes & PREFIX_DATA);
12889       break;
12890     case a_mode:
12891       if (sizeflag & DFLAG)
12892         oappend ("QWORD PTR ");
12893       else
12894         oappend ("DWORD PTR ");
12895       used_prefixes |= (prefixes & PREFIX_DATA);
12896       break;
12897     case d_mode:
12898     case d_scalar_mode:
12899     case d_scalar_swap_mode:
12900     case d_swap_mode:
12901     case dqd_mode:
12902       oappend ("DWORD PTR ");
12903       break;
12904     case q_mode:
12905     case q_scalar_mode:
12906     case q_scalar_swap_mode:
12907     case q_swap_mode:
12908       oappend ("QWORD PTR ");
12909       break;
12910     case m_mode:
12911       if (address_mode == mode_64bit)
12912         oappend ("QWORD PTR ");
12913       else
12914         oappend ("DWORD PTR ");
12915       break;
12916     case f_mode:
12917       if (sizeflag & DFLAG)
12918         oappend ("FWORD PTR ");
12919       else
12920         oappend ("DWORD PTR ");
12921       used_prefixes |= (prefixes & PREFIX_DATA);
12922       break;
12923     case t_mode:
12924       oappend ("TBYTE PTR ");
12925       break;
12926     case x_mode:
12927     case x_swap_mode:
12928       if (need_vex)
12929         {
12930           switch (vex.length)
12931             {
12932             case 128:
12933               oappend ("XMMWORD PTR ");
12934               break;
12935             case 256:
12936               oappend ("YMMWORD PTR ");
12937               break;
12938             default:
12939               abort ();
12940             }
12941         }
12942       else
12943         oappend ("XMMWORD PTR ");
12944       break;
12945     case xmm_mode:
12946       oappend ("XMMWORD PTR ");
12947       break;
12948     case xmmq_mode:
12949       if (!need_vex)
12950         abort ();
12951
12952       switch (vex.length)
12953         {
12954         case 128:
12955           oappend ("QWORD PTR ");
12956           break;
12957         case 256:
12958           oappend ("XMMWORD PTR ");
12959           break;
12960         default:
12961           abort ();
12962         }
12963       break;
12964     case ymmq_mode:
12965       if (!need_vex)
12966         abort ();
12967
12968       switch (vex.length)
12969         {
12970         case 128:
12971           oappend ("QWORD PTR ");
12972           break;
12973         case 256:
12974           oappend ("YMMWORD PTR ");
12975           break;
12976         default:
12977           abort ();
12978         }
12979       break;
12980     case o_mode:
12981       oappend ("OWORD PTR ");
12982       break;
12983     case vex_w_dq_mode:
12984     case vex_scalar_w_dq_mode:
12985       if (!need_vex)
12986         abort ();
12987
12988       if (vex.w)
12989         oappend ("QWORD PTR ");
12990       else
12991         oappend ("DWORD PTR ");
12992       break;
12993     default:
12994       break;
12995     }
12996 }
12997
12998 static void
12999 OP_E_register (int bytemode, int sizeflag)
13000 {
13001   int reg = modrm.rm;
13002   const char **names;
13003
13004   USED_REX (REX_B);
13005   if ((rex & REX_B))
13006     reg += 8;
13007
13008   if ((sizeflag & SUFFIX_ALWAYS)
13009       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
13010     swap_operand ();
13011
13012   switch (bytemode)
13013     {
13014     case b_mode:
13015     case b_swap_mode:
13016       USED_REX (0);
13017       if (rex)
13018         names = names8rex;
13019       else
13020         names = names8;
13021       break;
13022     case w_mode:
13023       names = names16;
13024       break;
13025     case d_mode:
13026       names = names32;
13027       break;
13028     case q_mode:
13029       names = names64;
13030       break;
13031     case m_mode:
13032       names = address_mode == mode_64bit ? names64 : names32;
13033       break;
13034     case stack_v_mode:
13035       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13036         {
13037           names = names64;
13038           break;
13039         }
13040       bytemode = v_mode;
13041       /* FALLTHRU */
13042     case v_mode:
13043     case v_swap_mode:
13044     case dq_mode:
13045     case dqb_mode:
13046     case dqd_mode:
13047     case dqw_mode:
13048       USED_REX (REX_W);
13049       if (rex & REX_W)
13050         names = names64;
13051       else
13052         {
13053           if ((sizeflag & DFLAG)
13054               || (bytemode != v_mode
13055                   && bytemode != v_swap_mode))
13056             names = names32;
13057           else
13058             names = names16;
13059           used_prefixes |= (prefixes & PREFIX_DATA);
13060         }
13061       break;
13062     case 0:
13063       return;
13064     default:
13065       oappend (INTERNAL_DISASSEMBLER_ERROR);
13066       return;
13067     }
13068   oappend (names[reg]);
13069 }
13070
13071 static void
13072 OP_E_memory (int bytemode, int sizeflag)
13073 {
13074   bfd_vma disp = 0;
13075   int add = (rex & REX_B) ? 8 : 0;
13076   int riprel = 0;
13077
13078   USED_REX (REX_B);
13079   if (intel_syntax)
13080     intel_operand_size (bytemode, sizeflag);
13081   append_seg ();
13082
13083   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13084     {
13085       /* 32/64 bit address mode */
13086       int havedisp;
13087       int havesib;
13088       int havebase;
13089       int haveindex;
13090       int needindex;
13091       int base, rbase;
13092       int vindex = 0;
13093       int scale = 0;
13094
13095       havesib = 0;
13096       havebase = 1;
13097       haveindex = 0;
13098       base = modrm.rm;
13099
13100       if (base == 4)
13101         {
13102           havesib = 1;
13103           vindex = sib.index;
13104           scale = sib.scale;
13105           base = sib.base;
13106           USED_REX (REX_X);
13107           if (rex & REX_X)
13108             vindex += 8;
13109           haveindex = vindex != 4;
13110           codep++;
13111         }
13112       rbase = base + add;
13113
13114       switch (modrm.mod)
13115         {
13116         case 0:
13117           if (base == 5)
13118             {
13119               havebase = 0;
13120               if (address_mode == mode_64bit && !havesib)
13121                 riprel = 1;
13122               disp = get32s ();
13123             }
13124           break;
13125         case 1:
13126           FETCH_DATA (the_info, codep + 1);
13127           disp = *codep++;
13128           if ((disp & 0x80) != 0)
13129             disp -= 0x100;
13130           break;
13131         case 2:
13132           disp = get32s ();
13133           break;
13134         }
13135
13136       /* In 32bit mode, we need index register to tell [offset] from
13137          [eiz*1 + offset].  */
13138       needindex = (havesib
13139                    && !havebase
13140                    && !haveindex
13141                    && address_mode == mode_32bit);
13142       havedisp = (havebase
13143                   || needindex
13144                   || (havesib && (haveindex || scale != 0)));
13145
13146       if (!intel_syntax)
13147         if (modrm.mod != 0 || base == 5)
13148           {
13149             if (havedisp || riprel)
13150               print_displacement (scratchbuf, disp);
13151             else
13152               print_operand_value (scratchbuf, 1, disp);
13153             oappend (scratchbuf);
13154             if (riprel)
13155               {
13156                 set_op (disp, 1);
13157                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13158               }
13159           }
13160
13161       if (havebase || haveindex || riprel)
13162         used_prefixes |= PREFIX_ADDR;
13163
13164       if (havedisp || (intel_syntax && riprel))
13165         {
13166           *obufp++ = open_char;
13167           if (intel_syntax && riprel)
13168             {
13169               set_op (disp, 1);
13170               oappend (sizeflag & AFLAG ? "rip" : "eip");
13171             }
13172           *obufp = '\0';
13173           if (havebase)
13174             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13175                      ? names64[rbase] : names32[rbase]);
13176           if (havesib)
13177             {
13178               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13179                  print index to tell base + index from base.  */
13180               if (scale != 0
13181                   || needindex
13182                   || haveindex
13183                   || (havebase && base != ESP_REG_NUM))
13184                 {
13185                   if (!intel_syntax || havebase)
13186                     {
13187                       *obufp++ = separator_char;
13188                       *obufp = '\0';
13189                     }
13190                   if (haveindex)
13191                     oappend (address_mode == mode_64bit
13192                              && (sizeflag & AFLAG)
13193                              ? names64[vindex] : names32[vindex]);
13194                   else
13195                     oappend (address_mode == mode_64bit
13196                              && (sizeflag & AFLAG)
13197                              ? index64 : index32);
13198
13199                   *obufp++ = scale_char;
13200                   *obufp = '\0';
13201                   sprintf (scratchbuf, "%d", 1 << scale);
13202                   oappend (scratchbuf);
13203                 }
13204             }
13205           if (intel_syntax
13206               && (disp || modrm.mod != 0 || base == 5))
13207             {
13208               if (!havedisp || (bfd_signed_vma) disp >= 0)
13209                 {
13210                   *obufp++ = '+';
13211                   *obufp = '\0';
13212                 }
13213               else if (modrm.mod != 1 && disp != -disp)
13214                 {
13215                   *obufp++ = '-';
13216                   *obufp = '\0';
13217                   disp = - (bfd_signed_vma) disp;
13218                 }
13219
13220               if (havedisp)
13221                 print_displacement (scratchbuf, disp);
13222               else
13223                 print_operand_value (scratchbuf, 1, disp);
13224               oappend (scratchbuf);
13225             }
13226
13227           *obufp++ = close_char;
13228           *obufp = '\0';
13229         }
13230       else if (intel_syntax)
13231         {
13232           if (modrm.mod != 0 || base == 5)
13233             {
13234               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13235                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13236                 ;
13237               else
13238                 {
13239                   oappend (names_seg[ds_reg - es_reg]);
13240                   oappend (":");
13241                 }
13242               print_operand_value (scratchbuf, 1, disp);
13243               oappend (scratchbuf);
13244             }
13245         }
13246     }
13247   else
13248     {
13249       /* 16 bit address mode */
13250       used_prefixes |= prefixes & PREFIX_ADDR;
13251       switch (modrm.mod)
13252         {
13253         case 0:
13254           if (modrm.rm == 6)
13255             {
13256               disp = get16 ();
13257               if ((disp & 0x8000) != 0)
13258                 disp -= 0x10000;
13259             }
13260           break;
13261         case 1:
13262           FETCH_DATA (the_info, codep + 1);
13263           disp = *codep++;
13264           if ((disp & 0x80) != 0)
13265             disp -= 0x100;
13266           break;
13267         case 2:
13268           disp = get16 ();
13269           if ((disp & 0x8000) != 0)
13270             disp -= 0x10000;
13271           break;
13272         }
13273
13274       if (!intel_syntax)
13275         if (modrm.mod != 0 || modrm.rm == 6)
13276           {
13277             print_displacement (scratchbuf, disp);
13278             oappend (scratchbuf);
13279           }
13280
13281       if (modrm.mod != 0 || modrm.rm != 6)
13282         {
13283           *obufp++ = open_char;
13284           *obufp = '\0';
13285           oappend (index16[modrm.rm]);
13286           if (intel_syntax
13287               && (disp || modrm.mod != 0 || modrm.rm == 6))
13288             {
13289               if ((bfd_signed_vma) disp >= 0)
13290                 {
13291                   *obufp++ = '+';
13292                   *obufp = '\0';
13293                 }
13294               else if (modrm.mod != 1)
13295                 {
13296                   *obufp++ = '-';
13297                   *obufp = '\0';
13298                   disp = - (bfd_signed_vma) disp;
13299                 }
13300
13301               print_displacement (scratchbuf, disp);
13302               oappend (scratchbuf);
13303             }
13304
13305           *obufp++ = close_char;
13306           *obufp = '\0';
13307         }
13308       else if (intel_syntax)
13309         {
13310           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13311                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13312             ;
13313           else
13314             {
13315               oappend (names_seg[ds_reg - es_reg]);
13316               oappend (":");
13317             }
13318           print_operand_value (scratchbuf, 1, disp & 0xffff);
13319           oappend (scratchbuf);
13320         }
13321     }
13322 }
13323
13324 static void
13325 OP_E (int bytemode, int sizeflag)
13326 {
13327   /* Skip mod/rm byte.  */
13328   MODRM_CHECK;
13329   codep++;
13330
13331   if (modrm.mod == 3)
13332     OP_E_register (bytemode, sizeflag);
13333   else
13334     OP_E_memory (bytemode, sizeflag);
13335 }
13336
13337 static void
13338 OP_G (int bytemode, int sizeflag)
13339 {
13340   int add = 0;
13341   USED_REX (REX_R);
13342   if (rex & REX_R)
13343     add += 8;
13344   switch (bytemode)
13345     {
13346     case b_mode:
13347       USED_REX (0);
13348       if (rex)
13349         oappend (names8rex[modrm.reg + add]);
13350       else
13351         oappend (names8[modrm.reg + add]);
13352       break;
13353     case w_mode:
13354       oappend (names16[modrm.reg + add]);
13355       break;
13356     case d_mode:
13357       oappend (names32[modrm.reg + add]);
13358       break;
13359     case q_mode:
13360       oappend (names64[modrm.reg + add]);
13361       break;
13362     case v_mode:
13363     case dq_mode:
13364     case dqb_mode:
13365     case dqd_mode:
13366     case dqw_mode:
13367       USED_REX (REX_W);
13368       if (rex & REX_W)
13369         oappend (names64[modrm.reg + add]);
13370       else
13371         {
13372           if ((sizeflag & DFLAG) || bytemode != v_mode)
13373             oappend (names32[modrm.reg + add]);
13374           else
13375             oappend (names16[modrm.reg + add]);
13376           used_prefixes |= (prefixes & PREFIX_DATA);
13377         }
13378       break;
13379     case m_mode:
13380       if (address_mode == mode_64bit)
13381         oappend (names64[modrm.reg + add]);
13382       else
13383         oappend (names32[modrm.reg + add]);
13384       break;
13385     default:
13386       oappend (INTERNAL_DISASSEMBLER_ERROR);
13387       break;
13388     }
13389 }
13390
13391 static bfd_vma
13392 get64 (void)
13393 {
13394   bfd_vma x;
13395 #ifdef BFD64
13396   unsigned int a;
13397   unsigned int b;
13398
13399   FETCH_DATA (the_info, codep + 8);
13400   a = *codep++ & 0xff;
13401   a |= (*codep++ & 0xff) << 8;
13402   a |= (*codep++ & 0xff) << 16;
13403   a |= (*codep++ & 0xff) << 24;
13404   b = *codep++ & 0xff;
13405   b |= (*codep++ & 0xff) << 8;
13406   b |= (*codep++ & 0xff) << 16;
13407   b |= (*codep++ & 0xff) << 24;
13408   x = a + ((bfd_vma) b << 32);
13409 #else
13410   abort ();
13411   x = 0;
13412 #endif
13413   return x;
13414 }
13415
13416 static bfd_signed_vma
13417 get32 (void)
13418 {
13419   bfd_signed_vma x = 0;
13420
13421   FETCH_DATA (the_info, codep + 4);
13422   x = *codep++ & (bfd_signed_vma) 0xff;
13423   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13424   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13425   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13426   return x;
13427 }
13428
13429 static bfd_signed_vma
13430 get32s (void)
13431 {
13432   bfd_signed_vma x = 0;
13433
13434   FETCH_DATA (the_info, codep + 4);
13435   x = *codep++ & (bfd_signed_vma) 0xff;
13436   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13437   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13438   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13439
13440   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13441
13442   return x;
13443 }
13444
13445 static int
13446 get16 (void)
13447 {
13448   int x = 0;
13449
13450   FETCH_DATA (the_info, codep + 2);
13451   x = *codep++ & 0xff;
13452   x |= (*codep++ & 0xff) << 8;
13453   return x;
13454 }
13455
13456 static void
13457 set_op (bfd_vma op, int riprel)
13458 {
13459   op_index[op_ad] = op_ad;
13460   if (address_mode == mode_64bit)
13461     {
13462       op_address[op_ad] = op;
13463       op_riprel[op_ad] = riprel;
13464     }
13465   else
13466     {
13467       /* Mask to get a 32-bit address.  */
13468       op_address[op_ad] = op & 0xffffffff;
13469       op_riprel[op_ad] = riprel & 0xffffffff;
13470     }
13471 }
13472
13473 static void
13474 OP_REG (int code, int sizeflag)
13475 {
13476   const char *s;
13477   int add;
13478   USED_REX (REX_B);
13479   if (rex & REX_B)
13480     add = 8;
13481   else
13482     add = 0;
13483
13484   switch (code)
13485     {
13486     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13487     case sp_reg: case bp_reg: case si_reg: case di_reg:
13488       s = names16[code - ax_reg + add];
13489       break;
13490     case es_reg: case ss_reg: case cs_reg:
13491     case ds_reg: case fs_reg: case gs_reg:
13492       s = names_seg[code - es_reg + add];
13493       break;
13494     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13495     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13496       USED_REX (0);
13497       if (rex)
13498         s = names8rex[code - al_reg + add];
13499       else
13500         s = names8[code - al_reg];
13501       break;
13502     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13503     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13504       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13505         {
13506           s = names64[code - rAX_reg + add];
13507           break;
13508         }
13509       code += eAX_reg - rAX_reg;
13510       /* Fall through.  */
13511     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13512     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13513       USED_REX (REX_W);
13514       if (rex & REX_W)
13515         s = names64[code - eAX_reg + add];
13516       else
13517         {
13518           if (sizeflag & DFLAG)
13519             s = names32[code - eAX_reg + add];
13520           else
13521             s = names16[code - eAX_reg + add];
13522           used_prefixes |= (prefixes & PREFIX_DATA);
13523         }
13524       break;
13525     default:
13526       s = INTERNAL_DISASSEMBLER_ERROR;
13527       break;
13528     }
13529   oappend (s);
13530 }
13531
13532 static void
13533 OP_IMREG (int code, int sizeflag)
13534 {
13535   const char *s;
13536
13537   switch (code)
13538     {
13539     case indir_dx_reg:
13540       if (intel_syntax)
13541         s = "dx";
13542       else
13543         s = "(%dx)";
13544       break;
13545     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13546     case sp_reg: case bp_reg: case si_reg: case di_reg:
13547       s = names16[code - ax_reg];
13548       break;
13549     case es_reg: case ss_reg: case cs_reg:
13550     case ds_reg: case fs_reg: case gs_reg:
13551       s = names_seg[code - es_reg];
13552       break;
13553     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13554     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13555       USED_REX (0);
13556       if (rex)
13557         s = names8rex[code - al_reg];
13558       else
13559         s = names8[code - al_reg];
13560       break;
13561     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13562     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13563       USED_REX (REX_W);
13564       if (rex & REX_W)
13565         s = names64[code - eAX_reg];
13566       else
13567         {
13568           if (sizeflag & DFLAG)
13569             s = names32[code - eAX_reg];
13570           else
13571             s = names16[code - eAX_reg];
13572           used_prefixes |= (prefixes & PREFIX_DATA);
13573         }
13574       break;
13575     case z_mode_ax_reg:
13576       if ((rex & REX_W) || (sizeflag & DFLAG))
13577         s = *names32;
13578       else
13579         s = *names16;
13580       if (!(rex & REX_W))
13581         used_prefixes |= (prefixes & PREFIX_DATA);
13582       break;
13583     default:
13584       s = INTERNAL_DISASSEMBLER_ERROR;
13585       break;
13586     }
13587   oappend (s);
13588 }
13589
13590 static void
13591 OP_I (int bytemode, int sizeflag)
13592 {
13593   bfd_signed_vma op;
13594   bfd_signed_vma mask = -1;
13595
13596   switch (bytemode)
13597     {
13598     case b_mode:
13599       FETCH_DATA (the_info, codep + 1);
13600       op = *codep++;
13601       mask = 0xff;
13602       break;
13603     case q_mode:
13604       if (address_mode == mode_64bit)
13605         {
13606           op = get32s ();
13607           break;
13608         }
13609       /* Fall through.  */
13610     case v_mode:
13611       USED_REX (REX_W);
13612       if (rex & REX_W)
13613         op = get32s ();
13614       else
13615         {
13616           if (sizeflag & DFLAG)
13617             {
13618               op = get32 ();
13619               mask = 0xffffffff;
13620             }
13621           else
13622             {
13623               op = get16 ();
13624               mask = 0xfffff;
13625             }
13626           used_prefixes |= (prefixes & PREFIX_DATA);
13627         }
13628       break;
13629     case w_mode:
13630       mask = 0xfffff;
13631       op = get16 ();
13632       break;
13633     case const_1_mode:
13634       if (intel_syntax)
13635         oappend ("1");
13636       return;
13637     default:
13638       oappend (INTERNAL_DISASSEMBLER_ERROR);
13639       return;
13640     }
13641
13642   op &= mask;
13643   scratchbuf[0] = '$';
13644   print_operand_value (scratchbuf + 1, 1, op);
13645   oappend (scratchbuf + intel_syntax);
13646   scratchbuf[0] = '\0';
13647 }
13648
13649 static void
13650 OP_I64 (int bytemode, int sizeflag)
13651 {
13652   bfd_signed_vma op;
13653   bfd_signed_vma mask = -1;
13654
13655   if (address_mode != mode_64bit)
13656     {
13657       OP_I (bytemode, sizeflag);
13658       return;
13659     }
13660
13661   switch (bytemode)
13662     {
13663     case b_mode:
13664       FETCH_DATA (the_info, codep + 1);
13665       op = *codep++;
13666       mask = 0xff;
13667       break;
13668     case v_mode:
13669       USED_REX (REX_W);
13670       if (rex & REX_W)
13671         op = get64 ();
13672       else
13673         {
13674           if (sizeflag & DFLAG)
13675             {
13676               op = get32 ();
13677               mask = 0xffffffff;
13678             }
13679           else
13680             {
13681               op = get16 ();
13682               mask = 0xfffff;
13683             }
13684           used_prefixes |= (prefixes & PREFIX_DATA);
13685         }
13686       break;
13687     case w_mode:
13688       mask = 0xfffff;
13689       op = get16 ();
13690       break;
13691     default:
13692       oappend (INTERNAL_DISASSEMBLER_ERROR);
13693       return;
13694     }
13695
13696   op &= mask;
13697   scratchbuf[0] = '$';
13698   print_operand_value (scratchbuf + 1, 1, op);
13699   oappend (scratchbuf + intel_syntax);
13700   scratchbuf[0] = '\0';
13701 }
13702
13703 static void
13704 OP_sI (int bytemode, int sizeflag)
13705 {
13706   bfd_signed_vma op;
13707
13708   switch (bytemode)
13709     {
13710     case b_mode:
13711       FETCH_DATA (the_info, codep + 1);
13712       op = *codep++;
13713       if ((op & 0x80) != 0)
13714         op -= 0x100;
13715       break;
13716     case v_mode:
13717       if (sizeflag & DFLAG)
13718         op = get32s ();
13719       else
13720         op = get16 ();
13721       break;
13722     default:
13723       oappend (INTERNAL_DISASSEMBLER_ERROR);
13724       return;
13725     }
13726
13727   scratchbuf[0] = '$';
13728   print_operand_value (scratchbuf + 1, 1, op);
13729   oappend (scratchbuf + intel_syntax);
13730 }
13731
13732 static void
13733 OP_J (int bytemode, int sizeflag)
13734 {
13735   bfd_vma disp;
13736   bfd_vma mask = -1;
13737   bfd_vma segment = 0;
13738
13739   switch (bytemode)
13740     {
13741     case b_mode:
13742       FETCH_DATA (the_info, codep + 1);
13743       disp = *codep++;
13744       if ((disp & 0x80) != 0)
13745         disp -= 0x100;
13746       break;
13747     case v_mode:
13748       USED_REX (REX_W);
13749       if ((sizeflag & DFLAG) || (rex & REX_W))
13750         disp = get32s ();
13751       else
13752         {
13753           disp = get16 ();
13754           if ((disp & 0x8000) != 0)
13755             disp -= 0x10000;
13756           /* In 16bit mode, address is wrapped around at 64k within
13757              the same segment.  Otherwise, a data16 prefix on a jump
13758              instruction means that the pc is masked to 16 bits after
13759              the displacement is added!  */
13760           mask = 0xffff;
13761           if ((prefixes & PREFIX_DATA) == 0)
13762             segment = ((start_pc + codep - start_codep)
13763                        & ~((bfd_vma) 0xffff));
13764         }
13765       if (!(rex & REX_W))
13766         used_prefixes |= (prefixes & PREFIX_DATA);
13767       break;
13768     default:
13769       oappend (INTERNAL_DISASSEMBLER_ERROR);
13770       return;
13771     }
13772   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13773   set_op (disp, 0);
13774   print_operand_value (scratchbuf, 1, disp);
13775   oappend (scratchbuf);
13776 }
13777
13778 static void
13779 OP_SEG (int bytemode, int sizeflag)
13780 {
13781   if (bytemode == w_mode)
13782     oappend (names_seg[modrm.reg]);
13783   else
13784     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13785 }
13786
13787 static void
13788 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13789 {
13790   int seg, offset;
13791
13792   if (sizeflag & DFLAG)
13793     {
13794       offset = get32 ();
13795       seg = get16 ();
13796     }
13797   else
13798     {
13799       offset = get16 ();
13800       seg = get16 ();
13801     }
13802   used_prefixes |= (prefixes & PREFIX_DATA);
13803   if (intel_syntax)
13804     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13805   else
13806     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13807   oappend (scratchbuf);
13808 }
13809
13810 static void
13811 OP_OFF (int bytemode, int sizeflag)
13812 {
13813   bfd_vma off;
13814
13815   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13816     intel_operand_size (bytemode, sizeflag);
13817   append_seg ();
13818
13819   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13820     off = get32 ();
13821   else
13822     off = get16 ();
13823
13824   if (intel_syntax)
13825     {
13826       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13827                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13828         {
13829           oappend (names_seg[ds_reg - es_reg]);
13830           oappend (":");
13831         }
13832     }
13833   print_operand_value (scratchbuf, 1, off);
13834   oappend (scratchbuf);
13835 }
13836
13837 static void
13838 OP_OFF64 (int bytemode, int sizeflag)
13839 {
13840   bfd_vma off;
13841
13842   if (address_mode != mode_64bit
13843       || (prefixes & PREFIX_ADDR))
13844     {
13845       OP_OFF (bytemode, sizeflag);
13846       return;
13847     }
13848
13849   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13850     intel_operand_size (bytemode, sizeflag);
13851   append_seg ();
13852
13853   off = get64 ();
13854
13855   if (intel_syntax)
13856     {
13857       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13858                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13859         {
13860           oappend (names_seg[ds_reg - es_reg]);
13861           oappend (":");
13862         }
13863     }
13864   print_operand_value (scratchbuf, 1, off);
13865   oappend (scratchbuf);
13866 }
13867
13868 static void
13869 ptr_reg (int code, int sizeflag)
13870 {
13871   const char *s;
13872
13873   *obufp++ = open_char;
13874   used_prefixes |= (prefixes & PREFIX_ADDR);
13875   if (address_mode == mode_64bit)
13876     {
13877       if (!(sizeflag & AFLAG))
13878         s = names32[code - eAX_reg];
13879       else
13880         s = names64[code - eAX_reg];
13881     }
13882   else if (sizeflag & AFLAG)
13883     s = names32[code - eAX_reg];
13884   else
13885     s = names16[code - eAX_reg];
13886   oappend (s);
13887   *obufp++ = close_char;
13888   *obufp = 0;
13889 }
13890
13891 static void
13892 OP_ESreg (int code, int sizeflag)
13893 {
13894   if (intel_syntax)
13895     {
13896       switch (codep[-1])
13897         {
13898         case 0x6d:      /* insw/insl */
13899           intel_operand_size (z_mode, sizeflag);
13900           break;
13901         case 0xa5:      /* movsw/movsl/movsq */
13902         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13903         case 0xab:      /* stosw/stosl */
13904         case 0xaf:      /* scasw/scasl */
13905           intel_operand_size (v_mode, sizeflag);
13906           break;
13907         default:
13908           intel_operand_size (b_mode, sizeflag);
13909         }
13910     }
13911   oappend ("%es:" + intel_syntax);
13912   ptr_reg (code, sizeflag);
13913 }
13914
13915 static void
13916 OP_DSreg (int code, int sizeflag)
13917 {
13918   if (intel_syntax)
13919     {
13920       switch (codep[-1])
13921         {
13922         case 0x6f:      /* outsw/outsl */
13923           intel_operand_size (z_mode, sizeflag);
13924           break;
13925         case 0xa5:      /* movsw/movsl/movsq */
13926         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13927         case 0xad:      /* lodsw/lodsl/lodsq */
13928           intel_operand_size (v_mode, sizeflag);
13929           break;
13930         default:
13931           intel_operand_size (b_mode, sizeflag);
13932         }
13933     }
13934   if ((prefixes
13935        & (PREFIX_CS
13936           | PREFIX_DS
13937           | PREFIX_SS
13938           | PREFIX_ES
13939           | PREFIX_FS
13940           | PREFIX_GS)) == 0)
13941     prefixes |= PREFIX_DS;
13942   append_seg ();
13943   ptr_reg (code, sizeflag);
13944 }
13945
13946 static void
13947 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13948 {
13949   int add;
13950   if (rex & REX_R)
13951     {
13952       USED_REX (REX_R);
13953       add = 8;
13954     }
13955   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13956     {
13957       all_prefixes[last_lock_prefix] = 0;
13958       used_prefixes |= PREFIX_LOCK;
13959       add = 8;
13960     }
13961   else
13962     add = 0;
13963   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13964   oappend (scratchbuf + intel_syntax);
13965 }
13966
13967 static void
13968 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13969 {
13970   int add;
13971   USED_REX (REX_R);
13972   if (rex & REX_R)
13973     add = 8;
13974   else
13975     add = 0;
13976   if (intel_syntax)
13977     sprintf (scratchbuf, "db%d", modrm.reg + add);
13978   else
13979     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13980   oappend (scratchbuf);
13981 }
13982
13983 static void
13984 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13985 {
13986   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13987   oappend (scratchbuf + intel_syntax);
13988 }
13989
13990 static void
13991 OP_R (int bytemode, int sizeflag)
13992 {
13993   if (modrm.mod == 3)
13994     OP_E (bytemode, sizeflag);
13995   else
13996     BadOp ();
13997 }
13998
13999 static void
14000 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14001 {
14002   int reg = modrm.reg;
14003   const char **names;
14004
14005   used_prefixes |= (prefixes & PREFIX_DATA);
14006   if (prefixes & PREFIX_DATA)
14007     {
14008       names = names_xmm;
14009       USED_REX (REX_R);
14010       if (rex & REX_R)
14011         reg += 8;
14012     }
14013   else
14014     names = names_mm;
14015   oappend (names[reg]);
14016 }
14017
14018 static void
14019 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14020 {
14021   int reg = modrm.reg;
14022   const char **names;
14023
14024   USED_REX (REX_R);
14025   if (rex & REX_R)
14026     reg += 8;
14027   if (need_vex
14028       && bytemode != xmm_mode
14029       && bytemode != scalar_mode)
14030     {
14031       switch (vex.length)
14032         {
14033         case 128:
14034           names = names_xmm;
14035           break;
14036         case 256:
14037           names = names_ymm;
14038           break;
14039         default:
14040           abort ();
14041         }
14042     }
14043   else
14044     names = names_xmm;
14045   oappend (names[reg]);
14046 }
14047
14048 static void
14049 OP_EM (int bytemode, int sizeflag)
14050 {
14051   int reg;
14052   const char **names;
14053
14054   if (modrm.mod != 3)
14055     {
14056       if (intel_syntax
14057           && (bytemode == v_mode || bytemode == v_swap_mode))
14058         {
14059           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14060           used_prefixes |= (prefixes & PREFIX_DATA);
14061         }
14062       OP_E (bytemode, sizeflag);
14063       return;
14064     }
14065
14066   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14067     swap_operand ();
14068
14069   /* Skip mod/rm byte.  */
14070   MODRM_CHECK;
14071   codep++;
14072   used_prefixes |= (prefixes & PREFIX_DATA);
14073   reg = modrm.rm;
14074   if (prefixes & PREFIX_DATA)
14075     {
14076       names = names_xmm;
14077       USED_REX (REX_B);
14078       if (rex & REX_B)
14079         reg += 8;
14080     }
14081   else
14082     names = names_mm;
14083   oappend (names[reg]);
14084 }
14085
14086 /* cvt* are the only instructions in sse2 which have
14087    both SSE and MMX operands and also have 0x66 prefix
14088    in their opcode. 0x66 was originally used to differentiate
14089    between SSE and MMX instruction(operands). So we have to handle the
14090    cvt* separately using OP_EMC and OP_MXC */
14091 static void
14092 OP_EMC (int bytemode, int sizeflag)
14093 {
14094   if (modrm.mod != 3)
14095     {
14096       if (intel_syntax && bytemode == v_mode)
14097         {
14098           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14099           used_prefixes |= (prefixes & PREFIX_DATA);
14100         }
14101       OP_E (bytemode, sizeflag);
14102       return;
14103     }
14104
14105   /* Skip mod/rm byte.  */
14106   MODRM_CHECK;
14107   codep++;
14108   used_prefixes |= (prefixes & PREFIX_DATA);
14109   oappend (names_mm[modrm.rm]);
14110 }
14111
14112 static void
14113 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14114 {
14115   used_prefixes |= (prefixes & PREFIX_DATA);
14116   oappend (names_mm[modrm.reg]);
14117 }
14118
14119 static void
14120 OP_EX (int bytemode, int sizeflag)
14121 {
14122   int reg;
14123   const char **names;
14124
14125   /* Skip mod/rm byte.  */
14126   MODRM_CHECK;
14127   codep++;
14128
14129   if (modrm.mod != 3)
14130     {
14131       OP_E_memory (bytemode, sizeflag);
14132       return;
14133     }
14134
14135   reg = modrm.rm;
14136   USED_REX (REX_B);
14137   if (rex & REX_B)
14138     reg += 8;
14139
14140   if ((sizeflag & SUFFIX_ALWAYS)
14141       && (bytemode == x_swap_mode
14142           || bytemode == d_swap_mode
14143           || bytemode == d_scalar_swap_mode
14144           || bytemode == q_swap_mode
14145           || bytemode == q_scalar_swap_mode))
14146     swap_operand ();
14147
14148   if (need_vex
14149       && bytemode != xmm_mode
14150       && bytemode != xmmq_mode
14151       && bytemode != d_scalar_mode
14152       && bytemode != d_scalar_swap_mode
14153       && bytemode != q_scalar_mode
14154       && bytemode != q_scalar_swap_mode
14155       && bytemode != vex_scalar_w_dq_mode)
14156     {
14157       switch (vex.length)
14158         {
14159         case 128:
14160           names = names_xmm;
14161           break;
14162         case 256:
14163           names = names_ymm;
14164           break;
14165         default:
14166           abort ();
14167         }
14168     }
14169   else
14170     names = names_xmm;
14171   oappend (names[reg]);
14172 }
14173
14174 static void
14175 OP_MS (int bytemode, int sizeflag)
14176 {
14177   if (modrm.mod == 3)
14178     OP_EM (bytemode, sizeflag);
14179   else
14180     BadOp ();
14181 }
14182
14183 static void
14184 OP_XS (int bytemode, int sizeflag)
14185 {
14186   if (modrm.mod == 3)
14187     OP_EX (bytemode, sizeflag);
14188   else
14189     BadOp ();
14190 }
14191
14192 static void
14193 OP_M (int bytemode, int sizeflag)
14194 {
14195   if (modrm.mod == 3)
14196     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14197     BadOp ();
14198   else
14199     OP_E (bytemode, sizeflag);
14200 }
14201
14202 static void
14203 OP_0f07 (int bytemode, int sizeflag)
14204 {
14205   if (modrm.mod != 3 || modrm.rm != 0)
14206     BadOp ();
14207   else
14208     OP_E (bytemode, sizeflag);
14209 }
14210
14211 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14212    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14213
14214 static void
14215 NOP_Fixup1 (int bytemode, int sizeflag)
14216 {
14217   if ((prefixes & PREFIX_DATA) != 0
14218       || (rex != 0
14219           && rex != 0x48
14220           && address_mode == mode_64bit))
14221     OP_REG (bytemode, sizeflag);
14222   else
14223     strcpy (obuf, "nop");
14224 }
14225
14226 static void
14227 NOP_Fixup2 (int bytemode, int sizeflag)
14228 {
14229   if ((prefixes & PREFIX_DATA) != 0
14230       || (rex != 0
14231           && rex != 0x48
14232           && address_mode == mode_64bit))
14233     OP_IMREG (bytemode, sizeflag);
14234 }
14235
14236 static const char *const Suffix3DNow[] = {
14237 /* 00 */        NULL,           NULL,           NULL,           NULL,
14238 /* 04 */        NULL,           NULL,           NULL,           NULL,
14239 /* 08 */        NULL,           NULL,           NULL,           NULL,
14240 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14241 /* 10 */        NULL,           NULL,           NULL,           NULL,
14242 /* 14 */        NULL,           NULL,           NULL,           NULL,
14243 /* 18 */        NULL,           NULL,           NULL,           NULL,
14244 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14245 /* 20 */        NULL,           NULL,           NULL,           NULL,
14246 /* 24 */        NULL,           NULL,           NULL,           NULL,
14247 /* 28 */        NULL,           NULL,           NULL,           NULL,
14248 /* 2C */        NULL,           NULL,           NULL,           NULL,
14249 /* 30 */        NULL,           NULL,           NULL,           NULL,
14250 /* 34 */        NULL,           NULL,           NULL,           NULL,
14251 /* 38 */        NULL,           NULL,           NULL,           NULL,
14252 /* 3C */        NULL,           NULL,           NULL,           NULL,
14253 /* 40 */        NULL,           NULL,           NULL,           NULL,
14254 /* 44 */        NULL,           NULL,           NULL,           NULL,
14255 /* 48 */        NULL,           NULL,           NULL,           NULL,
14256 /* 4C */        NULL,           NULL,           NULL,           NULL,
14257 /* 50 */        NULL,           NULL,           NULL,           NULL,
14258 /* 54 */        NULL,           NULL,           NULL,           NULL,
14259 /* 58 */        NULL,           NULL,           NULL,           NULL,
14260 /* 5C */        NULL,           NULL,           NULL,           NULL,
14261 /* 60 */        NULL,           NULL,           NULL,           NULL,
14262 /* 64 */        NULL,           NULL,           NULL,           NULL,
14263 /* 68 */        NULL,           NULL,           NULL,           NULL,
14264 /* 6C */        NULL,           NULL,           NULL,           NULL,
14265 /* 70 */        NULL,           NULL,           NULL,           NULL,
14266 /* 74 */        NULL,           NULL,           NULL,           NULL,
14267 /* 78 */        NULL,           NULL,           NULL,           NULL,
14268 /* 7C */        NULL,           NULL,           NULL,           NULL,
14269 /* 80 */        NULL,           NULL,           NULL,           NULL,
14270 /* 84 */        NULL,           NULL,           NULL,           NULL,
14271 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14272 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14273 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14274 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14275 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14276 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14277 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14278 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14279 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14280 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14281 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14282 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14283 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14284 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14285 /* C0 */        NULL,           NULL,           NULL,           NULL,
14286 /* C4 */        NULL,           NULL,           NULL,           NULL,
14287 /* C8 */        NULL,           NULL,           NULL,           NULL,
14288 /* CC */        NULL,           NULL,           NULL,           NULL,
14289 /* D0 */        NULL,           NULL,           NULL,           NULL,
14290 /* D4 */        NULL,           NULL,           NULL,           NULL,
14291 /* D8 */        NULL,           NULL,           NULL,           NULL,
14292 /* DC */        NULL,           NULL,           NULL,           NULL,
14293 /* E0 */        NULL,           NULL,           NULL,           NULL,
14294 /* E4 */        NULL,           NULL,           NULL,           NULL,
14295 /* E8 */        NULL,           NULL,           NULL,           NULL,
14296 /* EC */        NULL,           NULL,           NULL,           NULL,
14297 /* F0 */        NULL,           NULL,           NULL,           NULL,
14298 /* F4 */        NULL,           NULL,           NULL,           NULL,
14299 /* F8 */        NULL,           NULL,           NULL,           NULL,
14300 /* FC */        NULL,           NULL,           NULL,           NULL,
14301 };
14302
14303 static void
14304 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14305 {
14306   const char *mnemonic;
14307
14308   FETCH_DATA (the_info, codep + 1);
14309   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14310      place where an 8-bit immediate would normally go.  ie. the last
14311      byte of the instruction.  */
14312   obufp = mnemonicendp;
14313   mnemonic = Suffix3DNow[*codep++ & 0xff];
14314   if (mnemonic)
14315     oappend (mnemonic);
14316   else
14317     {
14318       /* Since a variable sized modrm/sib chunk is between the start
14319          of the opcode (0x0f0f) and the opcode suffix, we need to do
14320          all the modrm processing first, and don't know until now that
14321          we have a bad opcode.  This necessitates some cleaning up.  */
14322       op_out[0][0] = '\0';
14323       op_out[1][0] = '\0';
14324       BadOp ();
14325     }
14326   mnemonicendp = obufp;
14327 }
14328
14329 static struct op simd_cmp_op[] =
14330 {
14331   { STRING_COMMA_LEN ("eq") },
14332   { STRING_COMMA_LEN ("lt") },
14333   { STRING_COMMA_LEN ("le") },
14334   { STRING_COMMA_LEN ("unord") },
14335   { STRING_COMMA_LEN ("neq") },
14336   { STRING_COMMA_LEN ("nlt") },
14337   { STRING_COMMA_LEN ("nle") },
14338   { STRING_COMMA_LEN ("ord") }
14339 };
14340
14341 static void
14342 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14343 {
14344   unsigned int cmp_type;
14345
14346   FETCH_DATA (the_info, codep + 1);
14347   cmp_type = *codep++ & 0xff;
14348   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14349     {
14350       char suffix [3];
14351       char *p = mnemonicendp - 2;
14352       suffix[0] = p[0];
14353       suffix[1] = p[1];
14354       suffix[2] = '\0';
14355       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14356       mnemonicendp += simd_cmp_op[cmp_type].len;
14357     }
14358   else
14359     {
14360       /* We have a reserved extension byte.  Output it directly.  */
14361       scratchbuf[0] = '$';
14362       print_operand_value (scratchbuf + 1, 1, cmp_type);
14363       oappend (scratchbuf + intel_syntax);
14364       scratchbuf[0] = '\0';
14365     }
14366 }
14367
14368 static void
14369 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14370           int sizeflag ATTRIBUTE_UNUSED)
14371 {
14372   /* mwait %eax,%ecx  */
14373   if (!intel_syntax)
14374     {
14375       const char **names = (address_mode == mode_64bit
14376                             ? names64 : names32);
14377       strcpy (op_out[0], names[0]);
14378       strcpy (op_out[1], names[1]);
14379       two_source_ops = 1;
14380     }
14381   /* Skip mod/rm byte.  */
14382   MODRM_CHECK;
14383   codep++;
14384 }
14385
14386 static void
14387 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14388             int sizeflag ATTRIBUTE_UNUSED)
14389 {
14390   /* monitor %eax,%ecx,%edx"  */
14391   if (!intel_syntax)
14392     {
14393       const char **op1_names;
14394       const char **names = (address_mode == mode_64bit
14395                             ? names64 : names32);
14396
14397       if (!(prefixes & PREFIX_ADDR))
14398         op1_names = (address_mode == mode_16bit
14399                      ? names16 : names);
14400       else
14401         {
14402           /* Remove "addr16/addr32".  */
14403           all_prefixes[last_addr_prefix] = 0;
14404           op1_names = (address_mode != mode_32bit
14405                        ? names32 : names16);
14406           used_prefixes |= PREFIX_ADDR;
14407         }
14408       strcpy (op_out[0], op1_names[0]);
14409       strcpy (op_out[1], names[1]);
14410       strcpy (op_out[2], names[2]);
14411       two_source_ops = 1;
14412     }
14413   /* Skip mod/rm byte.  */
14414   MODRM_CHECK;
14415   codep++;
14416 }
14417
14418 static void
14419 BadOp (void)
14420 {
14421   /* Throw away prefixes and 1st. opcode byte.  */
14422   codep = insn_codep + 1;
14423   oappend ("(bad)");
14424 }
14425
14426 static void
14427 REP_Fixup (int bytemode, int sizeflag)
14428 {
14429   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14430      lods and stos.  */
14431   if (prefixes & PREFIX_REPZ)
14432     all_prefixes[last_repz_prefix] = REP_PREFIX;
14433
14434   switch (bytemode)
14435     {
14436     case al_reg:
14437     case eAX_reg:
14438     case indir_dx_reg:
14439       OP_IMREG (bytemode, sizeflag);
14440       break;
14441     case eDI_reg:
14442       OP_ESreg (bytemode, sizeflag);
14443       break;
14444     case eSI_reg:
14445       OP_DSreg (bytemode, sizeflag);
14446       break;
14447     default:
14448       abort ();
14449       break;
14450     }
14451 }
14452
14453 static void
14454 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14455 {
14456   USED_REX (REX_W);
14457   if (rex & REX_W)
14458     {
14459       /* Change cmpxchg8b to cmpxchg16b.  */
14460       char *p = mnemonicendp - 2;
14461       mnemonicendp = stpcpy (p, "16b");
14462       bytemode = o_mode;
14463     }
14464   OP_M (bytemode, sizeflag);
14465 }
14466
14467 static void
14468 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14469 {
14470   const char **names;
14471
14472   if (need_vex)
14473     {
14474       switch (vex.length)
14475         {
14476         case 128:
14477           names = names_xmm;
14478           break;
14479         case 256:
14480           names = names_ymm;
14481           break;
14482         default:
14483           abort ();
14484         }
14485     }
14486   else
14487     names = names_xmm;
14488   oappend (names[reg]);
14489 }
14490
14491 static void
14492 CRC32_Fixup (int bytemode, int sizeflag)
14493 {
14494   /* Add proper suffix to "crc32".  */
14495   char *p = mnemonicendp;
14496
14497   switch (bytemode)
14498     {
14499     case b_mode:
14500       if (intel_syntax)
14501         goto skip;
14502
14503       *p++ = 'b';
14504       break;
14505     case v_mode:
14506       if (intel_syntax)
14507         goto skip;
14508
14509       USED_REX (REX_W);
14510       if (rex & REX_W)
14511         *p++ = 'q';
14512       else
14513         {
14514           if (sizeflag & DFLAG)
14515             *p++ = 'l';
14516           else
14517             *p++ = 'w';
14518           used_prefixes |= (prefixes & PREFIX_DATA);
14519         }
14520       break;
14521     default:
14522       oappend (INTERNAL_DISASSEMBLER_ERROR);
14523       break;
14524     }
14525   mnemonicendp = p;
14526   *p = '\0';
14527
14528 skip:
14529   if (modrm.mod == 3)
14530     {
14531       int add;
14532
14533       /* Skip mod/rm byte.  */
14534       MODRM_CHECK;
14535       codep++;
14536
14537       USED_REX (REX_B);
14538       add = (rex & REX_B) ? 8 : 0;
14539       if (bytemode == b_mode)
14540         {
14541           USED_REX (0);
14542           if (rex)
14543             oappend (names8rex[modrm.rm + add]);
14544           else
14545             oappend (names8[modrm.rm + add]);
14546         }
14547       else
14548         {
14549           USED_REX (REX_W);
14550           if (rex & REX_W)
14551             oappend (names64[modrm.rm + add]);
14552           else if ((prefixes & PREFIX_DATA))
14553             oappend (names16[modrm.rm + add]);
14554           else
14555             oappend (names32[modrm.rm + add]);
14556         }
14557     }
14558   else
14559     OP_E (bytemode, sizeflag);
14560 }
14561
14562 static void
14563 FXSAVE_Fixup (int bytemode, int sizeflag)
14564 {
14565   /* Add proper suffix to "fxsave" and "fxrstor".  */
14566   USED_REX (REX_W);
14567   if (rex & REX_W)
14568     {
14569       char *p = mnemonicendp;
14570       *p++ = '6';
14571       *p++ = '4';
14572       *p = '\0';
14573       mnemonicendp = p;
14574     }
14575   OP_M (bytemode, sizeflag);
14576 }
14577
14578 /* Display the destination register operand for instructions with
14579    VEX. */
14580
14581 static void
14582 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14583 {
14584   int reg;
14585   const char **names;
14586
14587   if (!need_vex)
14588     abort ();
14589
14590   if (!need_vex_reg)
14591     return;
14592
14593   reg = vex.register_specifier;
14594   if (bytemode == vex_scalar_mode)
14595     {
14596       oappend (names_xmm[reg]);
14597       return;
14598     }
14599
14600   switch (vex.length)
14601     {
14602     case 128:
14603       switch (bytemode)
14604         {
14605         case vex_mode:
14606         case vex128_mode:
14607           names = names_xmm;
14608           break;
14609         case dq_mode:
14610           if (vex.w)
14611             names = names64;
14612           else
14613             names = names32;
14614           break;
14615         default:
14616           abort ();
14617           return;
14618         }
14619       break;
14620     case 256:
14621       switch (bytemode)
14622         {
14623         case vex_mode:
14624         case vex256_mode:
14625           break;
14626         default:
14627           abort ();
14628           return;
14629         }
14630
14631       names = names_ymm;
14632       break;
14633     default:
14634       abort ();
14635       break;
14636     }
14637   oappend (names[reg]);
14638 }
14639
14640 /* Get the VEX immediate byte without moving codep.  */
14641
14642 static unsigned char
14643 get_vex_imm8 (int sizeflag, int opnum)
14644 {
14645   int bytes_before_imm = 0;
14646
14647   if (modrm.mod != 3)
14648     {
14649       /* There are SIB/displacement bytes.  */
14650       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14651         {
14652           /* 32/64 bit address mode */
14653           int base = modrm.rm;
14654
14655           /* Check SIB byte.  */
14656           if (base == 4)
14657             {
14658               FETCH_DATA (the_info, codep + 1);
14659               base = *codep & 7;
14660               /* When decoding the third source, don't increase
14661                  bytes_before_imm as this has already been incremented
14662                  by one in OP_E_memory while decoding the second
14663                  source operand.  */
14664               if (opnum == 0)
14665                 bytes_before_imm++;
14666             }
14667
14668           /* Don't increase bytes_before_imm when decoding the third source,
14669              it has already been incremented by OP_E_memory while decoding
14670              the second source operand.  */
14671           if (opnum == 0)
14672             {
14673               switch (modrm.mod)
14674                 {
14675                   case 0:
14676                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14677                        SIB == 5, there is a 4 byte displacement.  */
14678                     if (base != 5)
14679                       /* No displacement. */
14680                       break;
14681                   case 2:
14682                     /* 4 byte displacement.  */
14683                     bytes_before_imm += 4;
14684                     break;
14685                   case 1:
14686                     /* 1 byte displacement.  */
14687                     bytes_before_imm++;
14688                     break;
14689                 }
14690             }
14691         }
14692       else
14693         {
14694           /* 16 bit address mode */
14695           /* Don't increase bytes_before_imm when decoding the third source,
14696              it has already been incremented by OP_E_memory while decoding
14697              the second source operand.  */
14698           if (opnum == 0)
14699             {
14700               switch (modrm.mod)
14701                 {
14702                 case 0:
14703                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14704                   if (modrm.rm != 6)
14705                     /* No displacement. */
14706                     break;
14707                 case 2:
14708                   /* 2 byte displacement.  */
14709                   bytes_before_imm += 2;
14710                   break;
14711                 case 1:
14712                   /* 1 byte displacement: when decoding the third source,
14713                      don't increase bytes_before_imm as this has already
14714                      been incremented by one in OP_E_memory while decoding
14715                      the second source operand.  */
14716                   if (opnum == 0)
14717                     bytes_before_imm++;
14718
14719                   break;
14720                 }
14721             }
14722         }
14723     }
14724
14725   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14726   return codep [bytes_before_imm];
14727 }
14728
14729 static void
14730 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14731 {
14732   const char **names;
14733
14734   if (reg == -1 && modrm.mod != 3)
14735     {
14736       OP_E_memory (bytemode, sizeflag);
14737       return;
14738     }
14739   else
14740     {
14741       if (reg == -1)
14742         {
14743           reg = modrm.rm;
14744           USED_REX (REX_B);
14745           if (rex & REX_B)
14746             reg += 8;
14747         }
14748       else if (reg > 7 && address_mode != mode_64bit)
14749         BadOp ();
14750     }
14751
14752   switch (vex.length)
14753     {
14754     case 128:
14755       names = names_xmm;
14756       break;
14757     case 256:
14758       names = names_ymm;
14759       break;
14760     default:
14761       abort ();
14762     }
14763   oappend (names[reg]);
14764 }
14765
14766 static void
14767 OP_EX_VexImmW (int bytemode, int sizeflag)
14768 {
14769   int reg = -1;
14770   static unsigned char vex_imm8;
14771
14772   if (vex_w_done == 0)
14773     {
14774       vex_w_done = 1;
14775
14776       /* Skip mod/rm byte.  */
14777       MODRM_CHECK;
14778       codep++;
14779
14780       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14781
14782       if (vex.w)
14783           reg = vex_imm8 >> 4;
14784
14785       OP_EX_VexReg (bytemode, sizeflag, reg);
14786     }
14787   else if (vex_w_done == 1)
14788     {
14789       vex_w_done = 2;
14790
14791       if (!vex.w)
14792           reg = vex_imm8 >> 4;
14793
14794       OP_EX_VexReg (bytemode, sizeflag, reg);
14795     }
14796   else
14797     {
14798       /* Output the imm8 directly.  */
14799       scratchbuf[0] = '$';
14800       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14801       oappend (scratchbuf + intel_syntax);
14802       scratchbuf[0] = '\0';
14803       codep++;
14804     }
14805 }
14806
14807 static void
14808 OP_Vex_2src (int bytemode, int sizeflag)
14809 {
14810   if (modrm.mod == 3)
14811     {
14812       int reg = modrm.rm;
14813       USED_REX (REX_B);
14814       if (rex & REX_B)
14815         reg += 8;
14816       oappend (names_xmm[reg]);
14817     }
14818   else
14819     {
14820       if (intel_syntax
14821           && (bytemode == v_mode || bytemode == v_swap_mode))
14822         {
14823           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14824           used_prefixes |= (prefixes & PREFIX_DATA);
14825         }
14826       OP_E (bytemode, sizeflag);
14827     }
14828 }
14829
14830 static void
14831 OP_Vex_2src_1 (int bytemode, int sizeflag)
14832 {
14833   if (modrm.mod == 3)
14834     {
14835       /* Skip mod/rm byte.   */
14836       MODRM_CHECK;
14837       codep++;
14838     }
14839
14840   if (vex.w)
14841     oappend (names_xmm[vex.register_specifier]);
14842   else
14843     OP_Vex_2src (bytemode, sizeflag);
14844 }
14845
14846 static void
14847 OP_Vex_2src_2 (int bytemode, int sizeflag)
14848 {
14849   if (vex.w)
14850     OP_Vex_2src (bytemode, sizeflag);
14851   else
14852     oappend (names_xmm[vex.register_specifier]);
14853 }
14854
14855 static void
14856 OP_EX_VexW (int bytemode, int sizeflag)
14857 {
14858   int reg = -1;
14859
14860   if (!vex_w_done)
14861     {
14862       vex_w_done = 1;
14863
14864       /* Skip mod/rm byte.  */
14865       MODRM_CHECK;
14866       codep++;
14867
14868       if (vex.w)
14869         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14870     }
14871   else
14872     {
14873       if (!vex.w)
14874         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14875     }
14876
14877   OP_EX_VexReg (bytemode, sizeflag, reg);
14878 }
14879
14880 static void
14881 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14882              int sizeflag ATTRIBUTE_UNUSED)
14883 {
14884   /* Skip the immediate byte and check for invalid bits.  */
14885   FETCH_DATA (the_info, codep + 1);
14886   if (*codep++ & 0xf)
14887     BadOp ();
14888 }
14889
14890 static void
14891 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14892 {
14893   int reg;
14894   const char **names;
14895
14896   FETCH_DATA (the_info, codep + 1);
14897   reg = *codep++;
14898
14899   if (bytemode != x_mode)
14900     abort ();
14901
14902   if (reg & 0xf)
14903       BadOp ();
14904
14905   reg >>= 4;
14906   if (reg > 7 && address_mode != mode_64bit)
14907     BadOp ();
14908
14909   switch (vex.length)
14910     {
14911     case 128:
14912       names = names_xmm;
14913       break;
14914     case 256:
14915       names = names_ymm;
14916       break;
14917     default:
14918       abort ();
14919     }
14920   oappend (names[reg]);
14921 }
14922
14923 static void
14924 OP_XMM_VexW (int bytemode, int sizeflag)
14925 {
14926   /* Turn off the REX.W bit since it is used for swapping operands
14927      now.  */
14928   rex &= ~REX_W;
14929   OP_XMM (bytemode, sizeflag);
14930 }
14931
14932 static void
14933 OP_EX_Vex (int bytemode, int sizeflag)
14934 {
14935   if (modrm.mod != 3)
14936     {
14937       if (vex.register_specifier != 0)
14938         BadOp ();
14939       need_vex_reg = 0;
14940     }
14941   OP_EX (bytemode, sizeflag);
14942 }
14943
14944 static void
14945 OP_XMM_Vex (int bytemode, int sizeflag)
14946 {
14947   if (modrm.mod != 3)
14948     {
14949       if (vex.register_specifier != 0)
14950         BadOp ();
14951       need_vex_reg = 0;
14952     }
14953   OP_XMM (bytemode, sizeflag);
14954 }
14955
14956 static void
14957 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14958 {
14959   switch (vex.length)
14960     {
14961     case 128:
14962       mnemonicendp = stpcpy (obuf, "vzeroupper");
14963       break;
14964     case 256:
14965       mnemonicendp = stpcpy (obuf, "vzeroall");
14966       break;
14967     default:
14968       abort ();
14969     }
14970 }
14971
14972 static struct op vex_cmp_op[] =
14973 {
14974   { STRING_COMMA_LEN ("eq") },
14975   { STRING_COMMA_LEN ("lt") },
14976   { STRING_COMMA_LEN ("le") },
14977   { STRING_COMMA_LEN ("unord") },
14978   { STRING_COMMA_LEN ("neq") },
14979   { STRING_COMMA_LEN ("nlt") },
14980   { STRING_COMMA_LEN ("nle") },
14981   { STRING_COMMA_LEN ("ord") },
14982   { STRING_COMMA_LEN ("eq_uq") },
14983   { STRING_COMMA_LEN ("nge") },
14984   { STRING_COMMA_LEN ("ngt") },
14985   { STRING_COMMA_LEN ("false") },
14986   { STRING_COMMA_LEN ("neq_oq") },
14987   { STRING_COMMA_LEN ("ge") },
14988   { STRING_COMMA_LEN ("gt") },
14989   { STRING_COMMA_LEN ("true") },
14990   { STRING_COMMA_LEN ("eq_os") },
14991   { STRING_COMMA_LEN ("lt_oq") },
14992   { STRING_COMMA_LEN ("le_oq") },
14993   { STRING_COMMA_LEN ("unord_s") },
14994   { STRING_COMMA_LEN ("neq_us") },
14995   { STRING_COMMA_LEN ("nlt_uq") },
14996   { STRING_COMMA_LEN ("nle_uq") },
14997   { STRING_COMMA_LEN ("ord_s") },
14998   { STRING_COMMA_LEN ("eq_us") },
14999   { STRING_COMMA_LEN ("nge_uq") },
15000   { STRING_COMMA_LEN ("ngt_uq") },
15001   { STRING_COMMA_LEN ("false_os") },
15002   { STRING_COMMA_LEN ("neq_os") },
15003   { STRING_COMMA_LEN ("ge_oq") },
15004   { STRING_COMMA_LEN ("gt_oq") },
15005   { STRING_COMMA_LEN ("true_us") },
15006 };
15007
15008 static void
15009 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15010 {
15011   unsigned int cmp_type;
15012
15013   FETCH_DATA (the_info, codep + 1);
15014   cmp_type = *codep++ & 0xff;
15015   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15016     {
15017       char suffix [3];
15018       char *p = mnemonicendp - 2;
15019       suffix[0] = p[0];
15020       suffix[1] = p[1];
15021       suffix[2] = '\0';
15022       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15023       mnemonicendp += vex_cmp_op[cmp_type].len;
15024     }
15025   else
15026     {
15027       /* We have a reserved extension byte.  Output it directly.  */
15028       scratchbuf[0] = '$';
15029       print_operand_value (scratchbuf + 1, 1, cmp_type);
15030       oappend (scratchbuf + intel_syntax);
15031       scratchbuf[0] = '\0';
15032     }
15033 }
15034
15035 static const struct op pclmul_op[] =
15036 {
15037   { STRING_COMMA_LEN ("lql") },
15038   { STRING_COMMA_LEN ("hql") },
15039   { STRING_COMMA_LEN ("lqh") },
15040   { STRING_COMMA_LEN ("hqh") }
15041 };
15042
15043 static void
15044 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15045               int sizeflag ATTRIBUTE_UNUSED)
15046 {
15047   unsigned int pclmul_type;
15048
15049   FETCH_DATA (the_info, codep + 1);
15050   pclmul_type = *codep++ & 0xff;
15051   switch (pclmul_type)
15052     {
15053     case 0x10:
15054       pclmul_type = 2;
15055       break;
15056     case 0x11:
15057       pclmul_type = 3;
15058       break;
15059     default:
15060       break;
15061     }
15062   if (pclmul_type < ARRAY_SIZE (pclmul_op))
15063     {
15064       char suffix [4];
15065       char *p = mnemonicendp - 3;
15066       suffix[0] = p[0];
15067       suffix[1] = p[1];
15068       suffix[2] = p[2];
15069       suffix[3] = '\0';
15070       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15071       mnemonicendp += pclmul_op[pclmul_type].len;
15072     }
15073   else
15074     {
15075       /* We have a reserved extension byte.  Output it directly.  */
15076       scratchbuf[0] = '$';
15077       print_operand_value (scratchbuf + 1, 1, pclmul_type);
15078       oappend (scratchbuf + intel_syntax);
15079       scratchbuf[0] = '\0';
15080     }
15081 }
15082
15083 static void
15084 MOVBE_Fixup (int bytemode, int sizeflag)
15085 {
15086   /* Add proper suffix to "movbe".  */
15087   char *p = mnemonicendp;
15088
15089   switch (bytemode)
15090     {
15091     case v_mode:
15092       if (intel_syntax)
15093         goto skip;
15094
15095       USED_REX (REX_W);
15096       if (sizeflag & SUFFIX_ALWAYS)
15097         {
15098           if (rex & REX_W)
15099             *p++ = 'q';
15100           else
15101             {
15102               if (sizeflag & DFLAG)
15103                 *p++ = 'l';
15104               else
15105                 *p++ = 'w';
15106               used_prefixes |= (prefixes & PREFIX_DATA);
15107             }
15108         }
15109       break;
15110     default:
15111       oappend (INTERNAL_DISASSEMBLER_ERROR);
15112       break;
15113     }
15114   mnemonicendp = p;
15115   *p = '\0';
15116
15117 skip:
15118   OP_M (bytemode, sizeflag);
15119 }
15120
15121 static void
15122 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15123 {
15124   int reg;
15125   const char **names;
15126
15127   /* Skip mod/rm byte.  */
15128   MODRM_CHECK;
15129   codep++;
15130
15131   if (vex.w)
15132     names = names64;
15133   else
15134     names = names32;
15135
15136   reg = modrm.rm;
15137   USED_REX (REX_B);
15138   if (rex & REX_B)
15139     reg += 8;
15140
15141   oappend (names[reg]);
15142 }
15143
15144 static void
15145 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15146 {
15147   const char **names;
15148
15149   if (vex.w)
15150     names = names64;
15151   else
15152     names = names32;
15153
15154   oappend (names[vex.register_specifier]);
15155 }
15156