opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2022 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43 typedef struct instr_info instr_info;
  44
  45 static int print_insn (bfd_vma, instr_info *);
  46 static void dofloat (instr_info *, int);
  47 static void OP_ST (instr_info *, int, int);
  48 static void OP_STi (instr_info *, int, int);
  49 static int putop (instr_info *, const char *, int);
  50 static void oappend (instr_info *, const char *);
  51 static void append_seg (instr_info *);
  52 static void OP_indirE (instr_info *, int, int);
  53 static void print_operand_value (instr_info *, char *, int, bfd_vma);
  54 static void OP_E_memory (instr_info *, int, int);
  55 static void print_displacement (instr_info *, char *, bfd_vma);
  56 static void OP_E (instr_info *, int, int);
  57 static void OP_G (instr_info *, int, int);
  58 static bfd_vma get64 (instr_info *);
  59 static bfd_signed_vma get32 (instr_info *);
  60 static bfd_signed_vma get32s (instr_info *);
  61 static int get16 (instr_info *);
  62 static void set_op (instr_info *, bfd_vma, int);
  63 static void OP_Skip_MODRM (instr_info *, int, int);
  64 static void OP_REG (instr_info *, int, int);
  65 static void OP_IMREG (instr_info *, int, int);
  66 static void OP_I (instr_info *, int, int);
  67 static void OP_I64 (instr_info *, int, int);
  68 static void OP_sI (instr_info *, int, int);
  69 static void OP_J (instr_info *, int, int);
  70 static void OP_SEG (instr_info *, int, int);
  71 static void OP_DIR (instr_info *, int, int);
  72 static void OP_OFF (instr_info *, int, int);
  73 static void OP_OFF64 (instr_info *, int, int);
  74 static void ptr_reg (instr_info *, int, int);
  75 static void OP_ESreg (instr_info *, int, int);
  76 static void OP_DSreg (instr_info *, int, int);
  77 static void OP_C (instr_info *, int, int);
  78 static void OP_D (instr_info *, int, int);
  79 static void OP_T (instr_info *, int, int);
  80 static void OP_MMX (instr_info *, int, int);
  81 static void OP_XMM (instr_info *, int, int);
  82 static void OP_EM (instr_info *, int, int);
  83 static void OP_EX (instr_info *, int, int);
  84 static void OP_EMC (instr_info *, int,int);
  85 static void OP_MXC (instr_info *, int,int);
  86 static void OP_MS (instr_info *, int, int);
  87 static void OP_XS (instr_info *, int, int);
  88 static void OP_M (instr_info *, int, int);
  89 static void OP_VEX (instr_info *, int, int);
  90 static void OP_VexR (instr_info *, int, int);
  91 static void OP_VexW (instr_info *, int, int);
  92 static void OP_Rounding (instr_info *, int, int);
  93 static void OP_REG_VexI4 (instr_info *, int, int);
  94 static void OP_VexI4 (instr_info *, int, int);
  95 static void PCLMUL_Fixup (instr_info *, int, int);
  96 static void VPCMP_Fixup (instr_info *, int, int);
  97 static void VPCOM_Fixup (instr_info *, int, int);
  98 static void OP_0f07 (instr_info *, int, int);
  99 static void OP_Monitor (instr_info *, int, int);
 100 static void OP_Mwait (instr_info *, int, int);
 101 static void NOP_Fixup1 (instr_info *, int, int);
 102 static void NOP_Fixup2 (instr_info *, int, int);
 103 static void OP_3DNowSuffix (instr_info *, int, int);
 104 static void CMP_Fixup (instr_info *, int, int);
 105 static void BadOp (instr_info *);
 106 static void REP_Fixup (instr_info *, int, int);
 107 static void SEP_Fixup (instr_info *, int, int);
 108 static void BND_Fixup (instr_info *, int, int);
 109 static void NOTRACK_Fixup (instr_info *, int, int);
 110 static void HLE_Fixup1 (instr_info *, int, int);
 111 static void HLE_Fixup2 (instr_info *, int, int);
 112 static void HLE_Fixup3 (instr_info *, int, int);
 113 static void CMPXCHG8B_Fixup (instr_info *, int, int);
 114 static void XMM_Fixup (instr_info *, int, int);
 115 static void FXSAVE_Fixup (instr_info *, int, int);
 116
 117 static void MOVSXD_Fixup (instr_info *, int, int);
 118 static void DistinctDest_Fixup (instr_info *, int, int);
 119
 120 struct dis_private {
 121   /* Points to first byte not fetched.  */
 122   bfd_byte *max_fetched;
 123   bfd_byte the_buffer[MAX_MNEM_SIZE];
 124   bfd_vma insn_start;
 125   int orig_sizeflag;
 126   OPCODES_SIGJMP_BUF bailout;
 127 };
 128
 129 enum address_mode
 130 {
 131   mode_16bit,
 132   mode_32bit,
 133   mode_64bit
 134 };
 135
 136 enum x86_64_isa
 137 {
 138   amd64 = 1,
 139   intel64
 140 };
 141
 142 struct instr_info
 143 {
 144   enum address_mode address_mode;
 145
 146   /* Flags for the prefixes for the current instruction.  See below.  */
 147   int prefixes;
 148
 149   /* REX prefix the current instruction.  See below.  */
 150   int rex;
 151   /* Bits of REX we've already used.  */
 152   int rex_used;
 153
 154   /* Flags for ins->prefixes which we somehow handled when printing the
 155      current instruction.  */
 156   int used_prefixes;
 157
 158   /* Flags for EVEX bits which we somehow handled when printing the
 159      current instruction.  */
 160   int evex_used;
 161
 162   char obuf[100];
 163   char *obufp;
 164   char *mnemonicendp;
 165   char scratchbuf[100];
 166   unsigned char *start_codep;
 167   unsigned char *insn_codep;
 168   unsigned char *codep;
 169   unsigned char *end_codep;
 170   int last_lock_prefix;
 171   int last_repz_prefix;
 172   int last_repnz_prefix;
 173   int last_data_prefix;
 174   int last_addr_prefix;
 175   int last_rex_prefix;
 176   int last_seg_prefix;
 177   int fwait_prefix;
 178   /* The active segment register prefix.  */
 179   int active_seg_prefix;
 180
 181 #define MAX_CODE_LENGTH 15
 182   /* We can up to 14 ins->prefixes since the maximum instruction length is
 183      15bytes.  */
 184   int all_prefixes[MAX_CODE_LENGTH - 1];
 185   disassemble_info *info;
 186
 187   struct
 188   {
 189     int mod;
 190     int reg;
 191     int rm;
 192   }
 193   modrm;
 194   unsigned char need_modrm;
 195
 196   struct
 197   {
 198     int scale;
 199     int index;
 200     int base;
 201   }
 202   sib;
 203
 204   struct
 205   {
 206     int register_specifier;
 207     int length;
 208     int prefix;
 209     int w;
 210     int evex;
 211     int r;
 212     int v;
 213     int mask_register_specifier;
 214     int zeroing;
 215     int ll;
 216     int b;
 217     int no_broadcast;
 218   }
 219   vex;
 220   unsigned char need_vex;
 221
 222   const char **names64;
 223   const char **names32;
 224   const char **names16;
 225   const char **names8;
 226   const char **names8rex;
 227   const char **names_seg;
 228   const char *index64;
 229   const char *index32;
 230   const char **index16;
 231   const char **names_bnd;
 232   const char **names_mm;
 233   const char **names_xmm;
 234   const char **names_ymm;
 235   const char **names_zmm;
 236   const char **names_tmm;
 237   const char **names_mask;
 238
 239   /* Remember if the current op is a jump instruction.  */
 240   bool op_is_jump;
 241
 242   char op_out[MAX_OPERANDS][100];
 243   int op_ad, op_index[MAX_OPERANDS];
 244   int two_source_ops;
 245   bfd_vma op_address[MAX_OPERANDS];
 246   bfd_vma op_riprel[MAX_OPERANDS];
 247   bfd_vma start_pc;
 248
 249   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 250    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 251    *   section of the "Virtual 8086 Mode" chapter.)
 252    * 'pc' should be the address of this instruction, it will
 253    *   be used to print the target address if this is a relative jump or call
 254    * The function returns the length of this instruction in bytes.
 255    */
 256   char intel_syntax;
 257   char intel_mnemonic;
 258   char open_char;
 259   char close_char;
 260   char separator_char;
 261   char scale_char;
 262
 263   enum x86_64_isa isa64;
 264
 265 };
 266
 267 /* Mark parts used in the REX prefix.  When we are testing for
 268    empty prefix (for 8bit register REX extension), just mask it
 269    out.  Otherwise test for REX bit is excuse for existence of REX
 270    only in case value is nonzero.  */
 271 #define USED_REX(value)                                 \
 272   {                                                     \
 273     if (value)                                          \
 274       {                                                 \
 275         if ((ins->rex & value))                         \
 276           ins->rex_used |= (value) | REX_OPCODE;        \
 277       }                                                 \
 278     else                                                \
 279       ins->rex_used |= REX_OPCODE;                      \
 280   }
 281
 282
 283 #define EVEX_b_used 1
 284
 285 /* Flags stored in PREFIXES.  */
 286 #define PREFIX_REPZ 1
 287 #define PREFIX_REPNZ 2
 288 #define PREFIX_LOCK 4
 289 #define PREFIX_CS 8
 290 #define PREFIX_SS 0x10
 291 #define PREFIX_DS 0x20
 292 #define PREFIX_ES 0x40
 293 #define PREFIX_FS 0x80
 294 #define PREFIX_GS 0x100
 295 #define PREFIX_DATA 0x200
 296 #define PREFIX_ADDR 0x400
 297 #define PREFIX_FWAIT 0x800
 298
 299 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 300    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 301    on error.  */
 302 #define FETCH_DATA(info, addr) \
 303   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 304    ? 1 : fetch_data ((info), (addr)))
 305
 306 static int
 307 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 308 {
 309   int status;
 310   struct dis_private *priv = (struct dis_private *) info->private_data;
 311   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 312
 313   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 314     status = (*info->read_memory_func) (start,
 315                                         priv->max_fetched,
 316                                         addr - priv->max_fetched,
 317                                         info);
 318   else
 319     status = -1;
 320   if (status != 0)
 321     {
 322       /* If we did manage to read at least one byte, then
 323          print_insn_i386 will do something sensible.  Otherwise, print
 324          an error.  We do that here because this is where we know
 325          STATUS.  */
 326       if (priv->max_fetched == priv->the_buffer)
 327         (*info->memory_error_func) (status, start, info);
 328       OPCODES_SIGLONGJMP (priv->bailout, 1);
 329     }
 330   else
 331     priv->max_fetched = addr;
 332   return 1;
 333 }
 334
 335 /* Possible values for prefix requirement.  */
 336 #define PREFIX_IGNORED_SHIFT    16
 337 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 338 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 339 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 340 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 341 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 342
 343 /* Opcode prefixes.  */
 344 #define PREFIX_OPCODE           (PREFIX_REPZ \
 345                                  | PREFIX_REPNZ \
 346                                  | PREFIX_DATA)
 347
 348 /* Prefixes ignored.  */
 349 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 350                                  | PREFIX_IGNORED_REPNZ \
 351                                  | PREFIX_IGNORED_DATA)
 352
 353 #define XX { NULL, 0 }
 354 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 355
 356 #define Eb { OP_E, b_mode }
 357 #define Ebnd { OP_E, bnd_mode }
 358 #define EbS { OP_E, b_swap_mode }
 359 #define EbndS { OP_E, bnd_swap_mode }
 360 #define Ev { OP_E, v_mode }
 361 #define Eva { OP_E, va_mode }
 362 #define Ev_bnd { OP_E, v_bnd_mode }
 363 #define EvS { OP_E, v_swap_mode }
 364 #define Ed { OP_E, d_mode }
 365 #define Edq { OP_E, dq_mode }
 366 #define Edb { OP_E, db_mode }
 367 #define Edw { OP_E, dw_mode }
 368 #define Eq { OP_E, q_mode }
 369 #define indirEv { OP_indirE, indir_v_mode }
 370 #define indirEp { OP_indirE, f_mode }
 371 #define stackEv { OP_E, stack_v_mode }
 372 #define Em { OP_E, m_mode }
 373 #define Ew { OP_E, w_mode }
 374 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 375 #define Ma { OP_M, a_mode }
 376 #define Mb { OP_M, b_mode }
 377 #define Md { OP_M, d_mode }
 378 #define Mo { OP_M, o_mode }
 379 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 380 #define Mq { OP_M, q_mode }
 381 #define Mv { OP_M, v_mode }
 382 #define Mv_bnd { OP_M, v_bndmk_mode }
 383 #define Mx { OP_M, x_mode }
 384 #define Mxmm { OP_M, xmm_mode }
 385 #define Gb { OP_G, b_mode }
 386 #define Gbnd { OP_G, bnd_mode }
 387 #define Gv { OP_G, v_mode }
 388 #define Gd { OP_G, d_mode }
 389 #define Gdq { OP_G, dq_mode }
 390 #define Gm { OP_G, m_mode }
 391 #define Gva { OP_G, va_mode }
 392 #define Gw { OP_G, w_mode }
 393 #define Ib { OP_I, b_mode }
 394 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 395 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 396 #define Iv { OP_I, v_mode }
 397 #define sIv { OP_sI, v_mode }
 398 #define Iv64 { OP_I64, v_mode }
 399 #define Id { OP_I, d_mode }
 400 #define Iw { OP_I, w_mode }
 401 #define I1 { OP_I, const_1_mode }
 402 #define Jb { OP_J, b_mode }
 403 #define Jv { OP_J, v_mode }
 404 #define Jdqw { OP_J, dqw_mode }
 405 #define Cm { OP_C, m_mode }
 406 #define Dm { OP_D, m_mode }
 407 #define Td { OP_T, d_mode }
 408 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 409
 410 #define RMeAX { OP_REG, eAX_reg }
 411 #define RMeBX { OP_REG, eBX_reg }
 412 #define RMeCX { OP_REG, eCX_reg }
 413 #define RMeDX { OP_REG, eDX_reg }
 414 #define RMeSP { OP_REG, eSP_reg }
 415 #define RMeBP { OP_REG, eBP_reg }
 416 #define RMeSI { OP_REG, eSI_reg }
 417 #define RMeDI { OP_REG, eDI_reg }
 418 #define RMrAX { OP_REG, rAX_reg }
 419 #define RMrBX { OP_REG, rBX_reg }
 420 #define RMrCX { OP_REG, rCX_reg }
 421 #define RMrDX { OP_REG, rDX_reg }
 422 #define RMrSP { OP_REG, rSP_reg }
 423 #define RMrBP { OP_REG, rBP_reg }
 424 #define RMrSI { OP_REG, rSI_reg }
 425 #define RMrDI { OP_REG, rDI_reg }
 426 #define RMAL { OP_REG, al_reg }
 427 #define RMCL { OP_REG, cl_reg }
 428 #define RMDL { OP_REG, dl_reg }
 429 #define RMBL { OP_REG, bl_reg }
 430 #define RMAH { OP_REG, ah_reg }
 431 #define RMCH { OP_REG, ch_reg }
 432 #define RMDH { OP_REG, dh_reg }
 433 #define RMBH { OP_REG, bh_reg }
 434 #define RMAX { OP_REG, ax_reg }
 435 #define RMDX { OP_REG, dx_reg }
 436
 437 #define eAX { OP_IMREG, eAX_reg }
 438 #define AL { OP_IMREG, al_reg }
 439 #define CL { OP_IMREG, cl_reg }
 440 #define zAX { OP_IMREG, z_mode_ax_reg }
 441 #define indirDX { OP_IMREG, indir_dx_reg }
 442
 443 #define Sw { OP_SEG, w_mode }
 444 #define Sv { OP_SEG, v_mode }
 445 #define Ap { OP_DIR, 0 }
 446 #define Ob { OP_OFF64, b_mode }
 447 #define Ov { OP_OFF64, v_mode }
 448 #define Xb { OP_DSreg, eSI_reg }
 449 #define Xv { OP_DSreg, eSI_reg }
 450 #define Xz { OP_DSreg, eSI_reg }
 451 #define Yb { OP_ESreg, eDI_reg }
 452 #define Yv { OP_ESreg, eDI_reg }
 453 #define DSBX { OP_DSreg, eBX_reg }
 454
 455 #define es { OP_REG, es_reg }
 456 #define ss { OP_REG, ss_reg }
 457 #define cs { OP_REG, cs_reg }
 458 #define ds { OP_REG, ds_reg }
 459 #define fs { OP_REG, fs_reg }
 460 #define gs { OP_REG, gs_reg }
 461
 462 #define MX { OP_MMX, 0 }
 463 #define XM { OP_XMM, 0 }
 464 #define XMScalar { OP_XMM, scalar_mode }
 465 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 466 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 467 #define XMM { OP_XMM, xmm_mode }
 468 #define TMM { OP_XMM, tmm_mode }
 469 #define XMxmmq { OP_XMM, xmmq_mode }
 470 #define EM { OP_EM, v_mode }
 471 #define EMS { OP_EM, v_swap_mode }
 472 #define EMd { OP_EM, d_mode }
 473 #define EMx { OP_EM, x_mode }
 474 #define EXbwUnit { OP_EX, bw_unit_mode }
 475 #define EXb { OP_EX, b_mode }
 476 #define EXw { OP_EX, w_mode }
 477 #define EXd { OP_EX, d_mode }
 478 #define EXdS { OP_EX, d_swap_mode }
 479 #define EXwS { OP_EX, w_swap_mode }
 480 #define EXq { OP_EX, q_mode }
 481 #define EXqS { OP_EX, q_swap_mode }
 482 #define EXdq { OP_EX, dq_mode }
 483 #define EXx { OP_EX, x_mode }
 484 #define EXxh { OP_EX, xh_mode }
 485 #define EXxS { OP_EX, x_swap_mode }
 486 #define EXxmm { OP_EX, xmm_mode }
 487 #define EXymm { OP_EX, ymm_mode }
 488 #define EXtmm { OP_EX, tmm_mode }
 489 #define EXxmmq { OP_EX, xmmq_mode }
 490 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 491 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 492 #define EXxmmdw { OP_EX, xmmdw_mode }
 493 #define EXxmmqd { OP_EX, xmmqd_mode }
 494 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 495 #define EXymmq { OP_EX, ymmq_mode }
 496 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 497 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 498 #define MS { OP_MS, v_mode }
 499 #define XS { OP_XS, v_mode }
 500 #define EMCq { OP_EMC, q_mode }
 501 #define MXC { OP_MXC, 0 }
 502 #define OPSUF { OP_3DNowSuffix, 0 }
 503 #define SEP { SEP_Fixup, 0 }
 504 #define CMP { CMP_Fixup, 0 }
 505 #define XMM0 { XMM_Fixup, 0 }
 506 #define FXSAVE { FXSAVE_Fixup, 0 }
 507
 508 #define Vex { OP_VEX, x_mode }
 509 #define VexW { OP_VexW, x_mode }
 510 #define VexScalar { OP_VEX, scalar_mode }
 511 #define VexScalarR { OP_VexR, scalar_mode }
 512 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 513 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 514 #define VexGdq { OP_VEX, dq_mode }
 515 #define VexTmm { OP_VEX, tmm_mode }
 516 #define XMVexI4 { OP_REG_VexI4, x_mode }
 517 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 518 #define VexI4 { OP_VexI4, 0 }
 519 #define PCLMUL { PCLMUL_Fixup, 0 }
 520 #define VPCMP { VPCMP_Fixup, 0 }
 521 #define VPCOM { VPCOM_Fixup, 0 }
 522
 523 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 524 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 525 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 526
 527 #define MaskG { OP_G, mask_mode }
 528 #define MaskE { OP_E, mask_mode }
 529 #define MaskBDE { OP_E, mask_bd_mode }
 530 #define MaskVex { OP_VEX, mask_mode }
 531
 532 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 533 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 534
 535 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 536
 537 /* Used handle "rep" prefix for string instructions.  */
 538 #define Xbr { REP_Fixup, eSI_reg }
 539 #define Xvr { REP_Fixup, eSI_reg }
 540 #define Ybr { REP_Fixup, eDI_reg }
 541 #define Yvr { REP_Fixup, eDI_reg }
 542 #define Yzr { REP_Fixup, eDI_reg }
 543 #define indirDXr { REP_Fixup, indir_dx_reg }
 544 #define ALr { REP_Fixup, al_reg }
 545 #define eAXr { REP_Fixup, eAX_reg }
 546
 547 /* Used handle HLE prefix for lockable instructions.  */
 548 #define Ebh1 { HLE_Fixup1, b_mode }
 549 #define Evh1 { HLE_Fixup1, v_mode }
 550 #define Ebh2 { HLE_Fixup2, b_mode }
 551 #define Evh2 { HLE_Fixup2, v_mode }
 552 #define Ebh3 { HLE_Fixup3, b_mode }
 553 #define Evh3 { HLE_Fixup3, v_mode }
 554
 555 #define BND { BND_Fixup, 0 }
 556 #define NOTRACK { NOTRACK_Fixup, 0 }
 557
 558 #define cond_jump_flag { NULL, cond_jump_mode }
 559 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 560
 561 /* bits in sizeflag */
 562 #define SUFFIX_ALWAYS 4
 563 #define AFLAG 2
 564 #define DFLAG 1
 565
 566 enum
 567 {
 568   /* byte operand */
 569   b_mode = 1,
 570   /* byte operand with operand swapped */
 571   b_swap_mode,
 572   /* byte operand, sign extend like 'T' suffix */
 573   b_T_mode,
 574   /* operand size depends on prefixes */
 575   v_mode,
 576   /* operand size depends on prefixes with operand swapped */
 577   v_swap_mode,
 578   /* operand size depends on address prefix */
 579   va_mode,
 580   /* word operand */
 581   w_mode,
 582   /* double word operand  */
 583   d_mode,
 584   /* word operand with operand swapped  */
 585   w_swap_mode,
 586   /* double word operand with operand swapped */
 587   d_swap_mode,
 588   /* quad word operand */
 589   q_mode,
 590   /* quad word operand with operand swapped */
 591   q_swap_mode,
 592   /* ten-byte operand */
 593   t_mode,
 594   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 595      broadcast enabled.  */
 596   x_mode,
 597   /* Similar to x_mode, but with different EVEX mem shifts.  */
 598   evex_x_gscat_mode,
 599   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 600   bw_unit_mode,
 601   /* Similar to x_mode, but with disabled broadcast.  */
 602   evex_x_nobcst_mode,
 603   /* Similar to x_mode, but with operands swapped and disabled broadcast
 604      in EVEX.  */
 605   x_swap_mode,
 606   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 607      broadcast of 16bit enabled.  */
 608   xh_mode,
 609   /* 16-byte XMM operand */
 610   xmm_mode,
 611   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 612      memory operand (depending on vector length).  Broadcast isn't
 613      allowed.  */
 614   xmmq_mode,
 615   /* Same as xmmq_mode, but broadcast is allowed.  */
 616   evex_half_bcst_xmmq_mode,
 617   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 618      memory operand (depending on vector length).  16bit broadcast.  */
 619   evex_half_bcst_xmmqh_mode,
 620   /* 16-byte XMM, word, double word or quad word operand.  */
 621   xmmdw_mode,
 622   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 623   xmmqd_mode,
 624   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 625      16bit broadcast.  */
 626   evex_half_bcst_xmmqdh_mode,
 627   /* 32-byte YMM operand */
 628   ymm_mode,
 629   /* quad word, ymmword or zmmword memory operand.  */
 630   ymmq_mode,
 631   /* TMM operand */
 632   tmm_mode,
 633   /* d_mode in 32bit, q_mode in 64bit mode.  */
 634   m_mode,
 635   /* pair of v_mode operands */
 636   a_mode,
 637   cond_jump_mode,
 638   loop_jcxz_mode,
 639   movsxd_mode,
 640   v_bnd_mode,
 641   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 642   v_bndmk_mode,
 643   /* operand size depends on REX.W / VEX.W.  */
 644   dq_mode,
 645   /* Displacements like v_mode without considering Intel64 ISA.  */
 646   dqw_mode,
 647   /* bounds operand */
 648   bnd_mode,
 649   /* bounds operand with operand swapped */
 650   bnd_swap_mode,
 651   /* 4- or 6-byte pointer operand */
 652   f_mode,
 653   const_1_mode,
 654   /* v_mode for indirect branch opcodes.  */
 655   indir_v_mode,
 656   /* v_mode for stack-related opcodes.  */
 657   stack_v_mode,
 658   /* non-quad operand size depends on prefixes */
 659   z_mode,
 660   /* 16-byte operand */
 661   o_mode,
 662   /* registers like d_mode, memory like b_mode.  */
 663   db_mode,
 664   /* registers like d_mode, memory like w_mode.  */
 665   dw_mode,
 666
 667   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 668   vex_vsib_d_w_dq_mode,
 669   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 670   vex_vsib_q_w_dq_mode,
 671   /* mandatory non-vector SIB.  */
 672   vex_sibmem_mode,
 673
 674   /* scalar, ignore vector length.  */
 675   scalar_mode,
 676
 677   /* Static rounding.  */
 678   evex_rounding_mode,
 679   /* Static rounding, 64-bit mode only.  */
 680   evex_rounding_64_mode,
 681   /* Supress all exceptions.  */
 682   evex_sae_mode,
 683
 684   /* Mask register operand.  */
 685   mask_mode,
 686   /* Mask register operand.  */
 687   mask_bd_mode,
 688
 689   es_reg,
 690   cs_reg,
 691   ss_reg,
 692   ds_reg,
 693   fs_reg,
 694   gs_reg,
 695
 696   eAX_reg,
 697   eCX_reg,
 698   eDX_reg,
 699   eBX_reg,
 700   eSP_reg,
 701   eBP_reg,
 702   eSI_reg,
 703   eDI_reg,
 704
 705   al_reg,
 706   cl_reg,
 707   dl_reg,
 708   bl_reg,
 709   ah_reg,
 710   ch_reg,
 711   dh_reg,
 712   bh_reg,
 713
 714   ax_reg,
 715   cx_reg,
 716   dx_reg,
 717   bx_reg,
 718   sp_reg,
 719   bp_reg,
 720   si_reg,
 721   di_reg,
 722
 723   rAX_reg,
 724   rCX_reg,
 725   rDX_reg,
 726   rBX_reg,
 727   rSP_reg,
 728   rBP_reg,
 729   rSI_reg,
 730   rDI_reg,
 731
 732   z_mode_ax_reg,
 733   indir_dx_reg
 734 };
 735
 736 enum
 737 {
 738   FLOATCODE = 1,
 739   USE_REG_TABLE,
 740   USE_MOD_TABLE,
 741   USE_RM_TABLE,
 742   USE_PREFIX_TABLE,
 743   USE_X86_64_TABLE,
 744   USE_3BYTE_TABLE,
 745   USE_XOP_8F_TABLE,
 746   USE_VEX_C4_TABLE,
 747   USE_VEX_C5_TABLE,
 748   USE_VEX_LEN_TABLE,
 749   USE_VEX_W_TABLE,
 750   USE_EVEX_TABLE,
 751   USE_EVEX_LEN_TABLE
 752 };
 753
 754 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 755
 756 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 757 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 758 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 759 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 760 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 761 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 762 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 763 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 764 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 765 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 766 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 767 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 768 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 769 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 770 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 771 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 772
 773 enum
 774 {
 775   REG_80 = 0,
 776   REG_81,
 777   REG_83,
 778   REG_8F,
 779   REG_C0,
 780   REG_C1,
 781   REG_C6,
 782   REG_C7,
 783   REG_D0,
 784   REG_D1,
 785   REG_D2,
 786   REG_D3,
 787   REG_F6,
 788   REG_F7,
 789   REG_FE,
 790   REG_FF,
 791   REG_0F00,
 792   REG_0F01,
 793   REG_0F0D,
 794   REG_0F18,
 795   REG_0F1C_P_0_MOD_0,
 796   REG_0F1E_P_1_MOD_3,
 797   REG_0F38D8_PREFIX_1,
 798   REG_0F3A0F_PREFIX_1_MOD_3,
 799   REG_0F71_MOD_0,
 800   REG_0F72_MOD_0,
 801   REG_0F73_MOD_0,
 802   REG_0FA6,
 803   REG_0FA7,
 804   REG_0FAE,
 805   REG_0FBA,
 806   REG_0FC7,
 807   REG_VEX_0F71_M_0,
 808   REG_VEX_0F72_M_0,
 809   REG_VEX_0F73_M_0,
 810   REG_VEX_0FAE,
 811   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 812   REG_VEX_0F38F3_L_0,
 813
 814   REG_XOP_09_01_L_0,
 815   REG_XOP_09_02_L_0,
 816   REG_XOP_09_12_M_1_L_0,
 817   REG_XOP_0A_12_L_0,
 818
 819   REG_EVEX_0F71,
 820   REG_EVEX_0F72,
 821   REG_EVEX_0F73,
 822   REG_EVEX_0F38C6_M_0_L_2,
 823   REG_EVEX_0F38C7_M_0_L_2
 824 };
 825
 826 enum
 827 {
 828   MOD_62_32BIT = 0,
 829   MOD_8D,
 830   MOD_C4_32BIT,
 831   MOD_C5_32BIT,
 832   MOD_C6_REG_7,
 833   MOD_C7_REG_7,
 834   MOD_FF_REG_3,
 835   MOD_FF_REG_5,
 836   MOD_0F01_REG_0,
 837   MOD_0F01_REG_1,
 838   MOD_0F01_REG_2,
 839   MOD_0F01_REG_3,
 840   MOD_0F01_REG_5,
 841   MOD_0F01_REG_7,
 842   MOD_0F12_PREFIX_0,
 843   MOD_0F12_PREFIX_2,
 844   MOD_0F13,
 845   MOD_0F16_PREFIX_0,
 846   MOD_0F16_PREFIX_2,
 847   MOD_0F17,
 848   MOD_0F18_REG_0,
 849   MOD_0F18_REG_1,
 850   MOD_0F18_REG_2,
 851   MOD_0F18_REG_3,
 852   MOD_0F1A_PREFIX_0,
 853   MOD_0F1B_PREFIX_0,
 854   MOD_0F1B_PREFIX_1,
 855   MOD_0F1C_PREFIX_0,
 856   MOD_0F1E_PREFIX_1,
 857   MOD_0F2B_PREFIX_0,
 858   MOD_0F2B_PREFIX_1,
 859   MOD_0F2B_PREFIX_2,
 860   MOD_0F2B_PREFIX_3,
 861   MOD_0F50,
 862   MOD_0F71,
 863   MOD_0F72,
 864   MOD_0F73,
 865   MOD_0FAE_REG_0,
 866   MOD_0FAE_REG_1,
 867   MOD_0FAE_REG_2,
 868   MOD_0FAE_REG_3,
 869   MOD_0FAE_REG_4,
 870   MOD_0FAE_REG_5,
 871   MOD_0FAE_REG_6,
 872   MOD_0FAE_REG_7,
 873   MOD_0FB2,
 874   MOD_0FB4,
 875   MOD_0FB5,
 876   MOD_0FC3,
 877   MOD_0FC7_REG_3,
 878   MOD_0FC7_REG_4,
 879   MOD_0FC7_REG_5,
 880   MOD_0FC7_REG_6,
 881   MOD_0FC7_REG_7,
 882   MOD_0FD7,
 883   MOD_0FE7_PREFIX_2,
 884   MOD_0FF0_PREFIX_3,
 885   MOD_0F382A,
 886   MOD_0F38DC_PREFIX_1,
 887   MOD_0F38DD_PREFIX_1,
 888   MOD_0F38DE_PREFIX_1,
 889   MOD_0F38DF_PREFIX_1,
 890   MOD_0F38F5,
 891   MOD_0F38F6_PREFIX_0,
 892   MOD_0F38F8_PREFIX_1,
 893   MOD_0F38F8_PREFIX_2,
 894   MOD_0F38F8_PREFIX_3,
 895   MOD_0F38F9,
 896   MOD_0F38FA_PREFIX_1,
 897   MOD_0F38FB_PREFIX_1,
 898   MOD_0F3A0F_PREFIX_1,
 899
 900   MOD_VEX_0F12_PREFIX_0,
 901   MOD_VEX_0F12_PREFIX_2,
 902   MOD_VEX_0F13,
 903   MOD_VEX_0F16_PREFIX_0,
 904   MOD_VEX_0F16_PREFIX_2,
 905   MOD_VEX_0F17,
 906   MOD_VEX_0F2B,
 907   MOD_VEX_0F41_L_1,
 908   MOD_VEX_0F42_L_1,
 909   MOD_VEX_0F44_L_0,
 910   MOD_VEX_0F45_L_1,
 911   MOD_VEX_0F46_L_1,
 912   MOD_VEX_0F47_L_1,
 913   MOD_VEX_0F4A_L_1,
 914   MOD_VEX_0F4B_L_1,
 915   MOD_VEX_0F50,
 916   MOD_VEX_0F71,
 917   MOD_VEX_0F72,
 918   MOD_VEX_0F73,
 919   MOD_VEX_0F91_L_0,
 920   MOD_VEX_0F92_L_0,
 921   MOD_VEX_0F93_L_0,
 922   MOD_VEX_0F98_L_0,
 923   MOD_VEX_0F99_L_0,
 924   MOD_VEX_0FAE_REG_2,
 925   MOD_VEX_0FAE_REG_3,
 926   MOD_VEX_0FD7,
 927   MOD_VEX_0FE7,
 928   MOD_VEX_0FF0_PREFIX_3,
 929   MOD_VEX_0F381A,
 930   MOD_VEX_0F382A,
 931   MOD_VEX_0F382C,
 932   MOD_VEX_0F382D,
 933   MOD_VEX_0F382E,
 934   MOD_VEX_0F382F,
 935   MOD_VEX_0F3849_X86_64_P_0_W_0,
 936   MOD_VEX_0F3849_X86_64_P_2_W_0,
 937   MOD_VEX_0F3849_X86_64_P_3_W_0,
 938   MOD_VEX_0F384B_X86_64_P_1_W_0,
 939   MOD_VEX_0F384B_X86_64_P_2_W_0,
 940   MOD_VEX_0F384B_X86_64_P_3_W_0,
 941   MOD_VEX_0F385A,
 942   MOD_VEX_0F385C_X86_64_P_1_W_0,
 943   MOD_VEX_0F385E_X86_64_P_0_W_0,
 944   MOD_VEX_0F385E_X86_64_P_1_W_0,
 945   MOD_VEX_0F385E_X86_64_P_2_W_0,
 946   MOD_VEX_0F385E_X86_64_P_3_W_0,
 947   MOD_VEX_0F388C,
 948   MOD_VEX_0F388E,
 949   MOD_VEX_0F3A30_L_0,
 950   MOD_VEX_0F3A31_L_0,
 951   MOD_VEX_0F3A32_L_0,
 952   MOD_VEX_0F3A33_L_0,
 953
 954   MOD_XOP_09_12,
 955
 956   MOD_EVEX_0F381A,
 957   MOD_EVEX_0F381B,
 958   MOD_EVEX_0F3828_P_1,
 959   MOD_EVEX_0F382A_P_1_W_1,
 960   MOD_EVEX_0F3838_P_1,
 961   MOD_EVEX_0F383A_P_1_W_0,
 962   MOD_EVEX_0F385A,
 963   MOD_EVEX_0F385B,
 964   MOD_EVEX_0F387A_W_0,
 965   MOD_EVEX_0F387B_W_0,
 966   MOD_EVEX_0F387C,
 967   MOD_EVEX_0F38C6,
 968   MOD_EVEX_0F38C7,
 969 };
 970
 971 enum
 972 {
 973   RM_C6_REG_7 = 0,
 974   RM_C7_REG_7,
 975   RM_0F01_REG_0,
 976   RM_0F01_REG_1,
 977   RM_0F01_REG_2,
 978   RM_0F01_REG_3,
 979   RM_0F01_REG_5_MOD_3,
 980   RM_0F01_REG_7_MOD_3,
 981   RM_0F1E_P_1_MOD_3_REG_7,
 982   RM_0FAE_REG_6_MOD_3_P_0,
 983   RM_0FAE_REG_7_MOD_3,
 984   RM_0F3A0F_P_1_MOD_3_REG_0,
 985
 986   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 987 };
 988
 989 enum
 990 {
 991   PREFIX_90 = 0,
 992   PREFIX_0F01_REG_1_RM_4,
 993   PREFIX_0F01_REG_1_RM_5,
 994   PREFIX_0F01_REG_1_RM_6,
 995   PREFIX_0F01_REG_1_RM_7,
 996   PREFIX_0F01_REG_3_RM_1,
 997   PREFIX_0F01_REG_5_MOD_0,
 998   PREFIX_0F01_REG_5_MOD_3_RM_0,
 999   PREFIX_0F01_REG_5_MOD_3_RM_1,
1000   PREFIX_0F01_REG_5_MOD_3_RM_2,
1001   PREFIX_0F01_REG_5_MOD_3_RM_4,
1002   PREFIX_0F01_REG_5_MOD_3_RM_5,
1003   PREFIX_0F01_REG_5_MOD_3_RM_6,
1004   PREFIX_0F01_REG_5_MOD_3_RM_7,
1005   PREFIX_0F01_REG_7_MOD_3_RM_2,
1006   PREFIX_0F01_REG_7_MOD_3_RM_6,
1007   PREFIX_0F01_REG_7_MOD_3_RM_7,
1008   PREFIX_0F09,
1009   PREFIX_0F10,
1010   PREFIX_0F11,
1011   PREFIX_0F12,
1012   PREFIX_0F16,
1013   PREFIX_0F1A,
1014   PREFIX_0F1B,
1015   PREFIX_0F1C,
1016   PREFIX_0F1E,
1017   PREFIX_0F2A,
1018   PREFIX_0F2B,
1019   PREFIX_0F2C,
1020   PREFIX_0F2D,
1021   PREFIX_0F2E,
1022   PREFIX_0F2F,
1023   PREFIX_0F51,
1024   PREFIX_0F52,
1025   PREFIX_0F53,
1026   PREFIX_0F58,
1027   PREFIX_0F59,
1028   PREFIX_0F5A,
1029   PREFIX_0F5B,
1030   PREFIX_0F5C,
1031   PREFIX_0F5D,
1032   PREFIX_0F5E,
1033   PREFIX_0F5F,
1034   PREFIX_0F60,
1035   PREFIX_0F61,
1036   PREFIX_0F62,
1037   PREFIX_0F6F,
1038   PREFIX_0F70,
1039   PREFIX_0F78,
1040   PREFIX_0F79,
1041   PREFIX_0F7C,
1042   PREFIX_0F7D,
1043   PREFIX_0F7E,
1044   PREFIX_0F7F,
1045   PREFIX_0FAE_REG_0_MOD_3,
1046   PREFIX_0FAE_REG_1_MOD_3,
1047   PREFIX_0FAE_REG_2_MOD_3,
1048   PREFIX_0FAE_REG_3_MOD_3,
1049   PREFIX_0FAE_REG_4_MOD_0,
1050   PREFIX_0FAE_REG_4_MOD_3,
1051   PREFIX_0FAE_REG_5_MOD_3,
1052   PREFIX_0FAE_REG_6_MOD_0,
1053   PREFIX_0FAE_REG_6_MOD_3,
1054   PREFIX_0FAE_REG_7_MOD_0,
1055   PREFIX_0FB8,
1056   PREFIX_0FBC,
1057   PREFIX_0FBD,
1058   PREFIX_0FC2,
1059   PREFIX_0FC7_REG_6_MOD_0,
1060   PREFIX_0FC7_REG_6_MOD_3,
1061   PREFIX_0FC7_REG_7_MOD_3,
1062   PREFIX_0FD0,
1063   PREFIX_0FD6,
1064   PREFIX_0FE6,
1065   PREFIX_0FE7,
1066   PREFIX_0FF0,
1067   PREFIX_0FF7,
1068   PREFIX_0F38D8,
1069   PREFIX_0F38DC,
1070   PREFIX_0F38DD,
1071   PREFIX_0F38DE,
1072   PREFIX_0F38DF,
1073   PREFIX_0F38F0,
1074   PREFIX_0F38F1,
1075   PREFIX_0F38F6,
1076   PREFIX_0F38F8,
1077   PREFIX_0F38FA,
1078   PREFIX_0F38FB,
1079   PREFIX_0F3A0F,
1080   PREFIX_VEX_0F10,
1081   PREFIX_VEX_0F11,
1082   PREFIX_VEX_0F12,
1083   PREFIX_VEX_0F16,
1084   PREFIX_VEX_0F2A,
1085   PREFIX_VEX_0F2C,
1086   PREFIX_VEX_0F2D,
1087   PREFIX_VEX_0F2E,
1088   PREFIX_VEX_0F2F,
1089   PREFIX_VEX_0F41_L_1_M_1_W_0,
1090   PREFIX_VEX_0F41_L_1_M_1_W_1,
1091   PREFIX_VEX_0F42_L_1_M_1_W_0,
1092   PREFIX_VEX_0F42_L_1_M_1_W_1,
1093   PREFIX_VEX_0F44_L_0_M_1_W_0,
1094   PREFIX_VEX_0F44_L_0_M_1_W_1,
1095   PREFIX_VEX_0F45_L_1_M_1_W_0,
1096   PREFIX_VEX_0F45_L_1_M_1_W_1,
1097   PREFIX_VEX_0F46_L_1_M_1_W_0,
1098   PREFIX_VEX_0F46_L_1_M_1_W_1,
1099   PREFIX_VEX_0F47_L_1_M_1_W_0,
1100   PREFIX_VEX_0F47_L_1_M_1_W_1,
1101   PREFIX_VEX_0F4A_L_1_M_1_W_0,
1102   PREFIX_VEX_0F4A_L_1_M_1_W_1,
1103   PREFIX_VEX_0F4B_L_1_M_1_W_0,
1104   PREFIX_VEX_0F4B_L_1_M_1_W_1,
1105   PREFIX_VEX_0F51,
1106   PREFIX_VEX_0F52,
1107   PREFIX_VEX_0F53,
1108   PREFIX_VEX_0F58,
1109   PREFIX_VEX_0F59,
1110   PREFIX_VEX_0F5A,
1111   PREFIX_VEX_0F5B,
1112   PREFIX_VEX_0F5C,
1113   PREFIX_VEX_0F5D,
1114   PREFIX_VEX_0F5E,
1115   PREFIX_VEX_0F5F,
1116   PREFIX_VEX_0F6F,
1117   PREFIX_VEX_0F70,
1118   PREFIX_VEX_0F7C,
1119   PREFIX_VEX_0F7D,
1120   PREFIX_VEX_0F7E,
1121   PREFIX_VEX_0F7F,
1122   PREFIX_VEX_0F90_L_0_W_0,
1123   PREFIX_VEX_0F90_L_0_W_1,
1124   PREFIX_VEX_0F91_L_0_M_0_W_0,
1125   PREFIX_VEX_0F91_L_0_M_0_W_1,
1126   PREFIX_VEX_0F92_L_0_M_1_W_0,
1127   PREFIX_VEX_0F92_L_0_M_1_W_1,
1128   PREFIX_VEX_0F93_L_0_M_1_W_0,
1129   PREFIX_VEX_0F93_L_0_M_1_W_1,
1130   PREFIX_VEX_0F98_L_0_M_1_W_0,
1131   PREFIX_VEX_0F98_L_0_M_1_W_1,
1132   PREFIX_VEX_0F99_L_0_M_1_W_0,
1133   PREFIX_VEX_0F99_L_0_M_1_W_1,
1134   PREFIX_VEX_0FC2,
1135   PREFIX_VEX_0FD0,
1136   PREFIX_VEX_0FE6,
1137   PREFIX_VEX_0FF0,
1138   PREFIX_VEX_0F3849_X86_64,
1139   PREFIX_VEX_0F384B_X86_64,
1140   PREFIX_VEX_0F385C_X86_64,
1141   PREFIX_VEX_0F385E_X86_64,
1142   PREFIX_VEX_0F38F5_L_0,
1143   PREFIX_VEX_0F38F6_L_0,
1144   PREFIX_VEX_0F38F7_L_0,
1145   PREFIX_VEX_0F3AF0_L_0,
1146
1147   PREFIX_EVEX_0F5B,
1148   PREFIX_EVEX_0F6F,
1149   PREFIX_EVEX_0F70,
1150   PREFIX_EVEX_0F78,
1151   PREFIX_EVEX_0F79,
1152   PREFIX_EVEX_0F7A,
1153   PREFIX_EVEX_0F7B,
1154   PREFIX_EVEX_0F7E,
1155   PREFIX_EVEX_0F7F,
1156   PREFIX_EVEX_0FC2,
1157   PREFIX_EVEX_0FE6,
1158   PREFIX_EVEX_0F3810,
1159   PREFIX_EVEX_0F3811,
1160   PREFIX_EVEX_0F3812,
1161   PREFIX_EVEX_0F3813,
1162   PREFIX_EVEX_0F3814,
1163   PREFIX_EVEX_0F3815,
1164   PREFIX_EVEX_0F3820,
1165   PREFIX_EVEX_0F3821,
1166   PREFIX_EVEX_0F3822,
1167   PREFIX_EVEX_0F3823,
1168   PREFIX_EVEX_0F3824,
1169   PREFIX_EVEX_0F3825,
1170   PREFIX_EVEX_0F3826,
1171   PREFIX_EVEX_0F3827,
1172   PREFIX_EVEX_0F3828,
1173   PREFIX_EVEX_0F3829,
1174   PREFIX_EVEX_0F382A,
1175   PREFIX_EVEX_0F3830,
1176   PREFIX_EVEX_0F3831,
1177   PREFIX_EVEX_0F3832,
1178   PREFIX_EVEX_0F3833,
1179   PREFIX_EVEX_0F3834,
1180   PREFIX_EVEX_0F3835,
1181   PREFIX_EVEX_0F3838,
1182   PREFIX_EVEX_0F3839,
1183   PREFIX_EVEX_0F383A,
1184   PREFIX_EVEX_0F3852,
1185   PREFIX_EVEX_0F3853,
1186   PREFIX_EVEX_0F3868,
1187   PREFIX_EVEX_0F3872,
1188   PREFIX_EVEX_0F389A,
1189   PREFIX_EVEX_0F389B,
1190   PREFIX_EVEX_0F38AA,
1191   PREFIX_EVEX_0F38AB,
1192
1193   PREFIX_EVEX_0F3A08,
1194   PREFIX_EVEX_0F3A0A,
1195   PREFIX_EVEX_0F3A26,
1196   PREFIX_EVEX_0F3A27,
1197   PREFIX_EVEX_0F3A56,
1198   PREFIX_EVEX_0F3A57,
1199   PREFIX_EVEX_0F3A66,
1200   PREFIX_EVEX_0F3A67,
1201   PREFIX_EVEX_0F3AC2,
1202
1203   PREFIX_EVEX_MAP5_10,
1204   PREFIX_EVEX_MAP5_11,
1205   PREFIX_EVEX_MAP5_1D,
1206   PREFIX_EVEX_MAP5_2A,
1207   PREFIX_EVEX_MAP5_2C,
1208   PREFIX_EVEX_MAP5_2D,
1209   PREFIX_EVEX_MAP5_2E,
1210   PREFIX_EVEX_MAP5_2F,
1211   PREFIX_EVEX_MAP5_51,
1212   PREFIX_EVEX_MAP5_58,
1213   PREFIX_EVEX_MAP5_59,
1214   PREFIX_EVEX_MAP5_5A,
1215   PREFIX_EVEX_MAP5_5B,
1216   PREFIX_EVEX_MAP5_5C,
1217   PREFIX_EVEX_MAP5_5D,
1218   PREFIX_EVEX_MAP5_5E,
1219   PREFIX_EVEX_MAP5_5F,
1220   PREFIX_EVEX_MAP5_78,
1221   PREFIX_EVEX_MAP5_79,
1222   PREFIX_EVEX_MAP5_7A,
1223   PREFIX_EVEX_MAP5_7B,
1224   PREFIX_EVEX_MAP5_7C,
1225   PREFIX_EVEX_MAP5_7D,
1226
1227   PREFIX_EVEX_MAP6_13,
1228   PREFIX_EVEX_MAP6_56,
1229   PREFIX_EVEX_MAP6_57,
1230   PREFIX_EVEX_MAP6_D6,
1231   PREFIX_EVEX_MAP6_D7,
1232 };
1233
1234 enum
1235 {
1236   X86_64_06 = 0,
1237   X86_64_07,
1238   X86_64_0E,
1239   X86_64_16,
1240   X86_64_17,
1241   X86_64_1E,
1242   X86_64_1F,
1243   X86_64_27,
1244   X86_64_2F,
1245   X86_64_37,
1246   X86_64_3F,
1247   X86_64_60,
1248   X86_64_61,
1249   X86_64_62,
1250   X86_64_63,
1251   X86_64_6D,
1252   X86_64_6F,
1253   X86_64_82,
1254   X86_64_9A,
1255   X86_64_C2,
1256   X86_64_C3,
1257   X86_64_C4,
1258   X86_64_C5,
1259   X86_64_CE,
1260   X86_64_D4,
1261   X86_64_D5,
1262   X86_64_E8,
1263   X86_64_E9,
1264   X86_64_EA,
1265   X86_64_0F01_REG_0,
1266   X86_64_0F01_REG_1,
1267   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1268   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1269   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1270   X86_64_0F01_REG_2,
1271   X86_64_0F01_REG_3,
1272   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1273   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1274   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1275   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1276   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1277   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1278   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1279   X86_64_0F24,
1280   X86_64_0F26,
1281   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1282
1283   X86_64_VEX_0F3849,
1284   X86_64_VEX_0F384B,
1285   X86_64_VEX_0F385C,
1286   X86_64_VEX_0F385E
1287 };
1288
1289 enum
1290 {
1291   THREE_BYTE_0F38 = 0,
1292   THREE_BYTE_0F3A
1293 };
1294
1295 enum
1296 {
1297   XOP_08 = 0,
1298   XOP_09,
1299   XOP_0A
1300 };
1301
1302 enum
1303 {
1304   VEX_0F = 0,
1305   VEX_0F38,
1306   VEX_0F3A
1307 };
1308
1309 enum
1310 {
1311   EVEX_0F = 0,
1312   EVEX_0F38,
1313   EVEX_0F3A,
1314   EVEX_MAP5,
1315   EVEX_MAP6,
1316 };
1317
1318 enum
1319 {
1320   VEX_LEN_0F12_P_0_M_0 = 0,
1321   VEX_LEN_0F12_P_0_M_1,
1322 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1323   VEX_LEN_0F13_M_0,
1324   VEX_LEN_0F16_P_0_M_0,
1325   VEX_LEN_0F16_P_0_M_1,
1326 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1327   VEX_LEN_0F17_M_0,
1328   VEX_LEN_0F41,
1329   VEX_LEN_0F42,
1330   VEX_LEN_0F44,
1331   VEX_LEN_0F45,
1332   VEX_LEN_0F46,
1333   VEX_LEN_0F47,
1334   VEX_LEN_0F4A,
1335   VEX_LEN_0F4B,
1336   VEX_LEN_0F6E,
1337   VEX_LEN_0F77,
1338   VEX_LEN_0F7E_P_1,
1339   VEX_LEN_0F7E_P_2,
1340   VEX_LEN_0F90,
1341   VEX_LEN_0F91,
1342   VEX_LEN_0F92,
1343   VEX_LEN_0F93,
1344   VEX_LEN_0F98,
1345   VEX_LEN_0F99,
1346   VEX_LEN_0FAE_R_2_M_0,
1347   VEX_LEN_0FAE_R_3_M_0,
1348   VEX_LEN_0FC4,
1349   VEX_LEN_0FC5,
1350   VEX_LEN_0FD6,
1351   VEX_LEN_0FF7,
1352   VEX_LEN_0F3816,
1353   VEX_LEN_0F3819,
1354   VEX_LEN_0F381A_M_0,
1355   VEX_LEN_0F3836,
1356   VEX_LEN_0F3841,
1357   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1358   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1359   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1360   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1361   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1362   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1363   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1364   VEX_LEN_0F385A_M_0,
1365   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1366   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1367   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1368   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1369   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1370   VEX_LEN_0F38DB,
1371   VEX_LEN_0F38F2,
1372   VEX_LEN_0F38F3,
1373   VEX_LEN_0F38F5,
1374   VEX_LEN_0F38F6,
1375   VEX_LEN_0F38F7,
1376   VEX_LEN_0F3A00,
1377   VEX_LEN_0F3A01,
1378   VEX_LEN_0F3A06,
1379   VEX_LEN_0F3A14,
1380   VEX_LEN_0F3A15,
1381   VEX_LEN_0F3A16,
1382   VEX_LEN_0F3A17,
1383   VEX_LEN_0F3A18,
1384   VEX_LEN_0F3A19,
1385   VEX_LEN_0F3A20,
1386   VEX_LEN_0F3A21,
1387   VEX_LEN_0F3A22,
1388   VEX_LEN_0F3A30,
1389   VEX_LEN_0F3A31,
1390   VEX_LEN_0F3A32,
1391   VEX_LEN_0F3A33,
1392   VEX_LEN_0F3A38,
1393   VEX_LEN_0F3A39,
1394   VEX_LEN_0F3A41,
1395   VEX_LEN_0F3A46,
1396   VEX_LEN_0F3A60,
1397   VEX_LEN_0F3A61,
1398   VEX_LEN_0F3A62,
1399   VEX_LEN_0F3A63,
1400   VEX_LEN_0F3ADF,
1401   VEX_LEN_0F3AF0,
1402   VEX_LEN_0FXOP_08_85,
1403   VEX_LEN_0FXOP_08_86,
1404   VEX_LEN_0FXOP_08_87,
1405   VEX_LEN_0FXOP_08_8E,
1406   VEX_LEN_0FXOP_08_8F,
1407   VEX_LEN_0FXOP_08_95,
1408   VEX_LEN_0FXOP_08_96,
1409   VEX_LEN_0FXOP_08_97,
1410   VEX_LEN_0FXOP_08_9E,
1411   VEX_LEN_0FXOP_08_9F,
1412   VEX_LEN_0FXOP_08_A3,
1413   VEX_LEN_0FXOP_08_A6,
1414   VEX_LEN_0FXOP_08_B6,
1415   VEX_LEN_0FXOP_08_C0,
1416   VEX_LEN_0FXOP_08_C1,
1417   VEX_LEN_0FXOP_08_C2,
1418   VEX_LEN_0FXOP_08_C3,
1419   VEX_LEN_0FXOP_08_CC,
1420   VEX_LEN_0FXOP_08_CD,
1421   VEX_LEN_0FXOP_08_CE,
1422   VEX_LEN_0FXOP_08_CF,
1423   VEX_LEN_0FXOP_08_EC,
1424   VEX_LEN_0FXOP_08_ED,
1425   VEX_LEN_0FXOP_08_EE,
1426   VEX_LEN_0FXOP_08_EF,
1427   VEX_LEN_0FXOP_09_01,
1428   VEX_LEN_0FXOP_09_02,
1429   VEX_LEN_0FXOP_09_12_M_1,
1430   VEX_LEN_0FXOP_09_82_W_0,
1431   VEX_LEN_0FXOP_09_83_W_0,
1432   VEX_LEN_0FXOP_09_90,
1433   VEX_LEN_0FXOP_09_91,
1434   VEX_LEN_0FXOP_09_92,
1435   VEX_LEN_0FXOP_09_93,
1436   VEX_LEN_0FXOP_09_94,
1437   VEX_LEN_0FXOP_09_95,
1438   VEX_LEN_0FXOP_09_96,
1439   VEX_LEN_0FXOP_09_97,
1440   VEX_LEN_0FXOP_09_98,
1441   VEX_LEN_0FXOP_09_99,
1442   VEX_LEN_0FXOP_09_9A,
1443   VEX_LEN_0FXOP_09_9B,
1444   VEX_LEN_0FXOP_09_C1,
1445   VEX_LEN_0FXOP_09_C2,
1446   VEX_LEN_0FXOP_09_C3,
1447   VEX_LEN_0FXOP_09_C6,
1448   VEX_LEN_0FXOP_09_C7,
1449   VEX_LEN_0FXOP_09_CB,
1450   VEX_LEN_0FXOP_09_D1,
1451   VEX_LEN_0FXOP_09_D2,
1452   VEX_LEN_0FXOP_09_D3,
1453   VEX_LEN_0FXOP_09_D6,
1454   VEX_LEN_0FXOP_09_D7,
1455   VEX_LEN_0FXOP_09_DB,
1456   VEX_LEN_0FXOP_09_E1,
1457   VEX_LEN_0FXOP_09_E2,
1458   VEX_LEN_0FXOP_09_E3,
1459   VEX_LEN_0FXOP_0A_12,
1460 };
1461
1462 enum
1463 {
1464   EVEX_LEN_0F3816 = 0,
1465   EVEX_LEN_0F3819,
1466   EVEX_LEN_0F381A_M_0,
1467   EVEX_LEN_0F381B_M_0,
1468   EVEX_LEN_0F3836,
1469   EVEX_LEN_0F385A_M_0,
1470   EVEX_LEN_0F385B_M_0,
1471   EVEX_LEN_0F38C6_M_0,
1472   EVEX_LEN_0F38C7_M_0,
1473   EVEX_LEN_0F3A00,
1474   EVEX_LEN_0F3A01,
1475   EVEX_LEN_0F3A18,
1476   EVEX_LEN_0F3A19,
1477   EVEX_LEN_0F3A1A,
1478   EVEX_LEN_0F3A1B,
1479   EVEX_LEN_0F3A23,
1480   EVEX_LEN_0F3A38,
1481   EVEX_LEN_0F3A39,
1482   EVEX_LEN_0F3A3A,
1483   EVEX_LEN_0F3A3B,
1484   EVEX_LEN_0F3A43
1485 };
1486
1487 enum
1488 {
1489   VEX_W_0F41_L_1_M_1 = 0,
1490   VEX_W_0F42_L_1_M_1,
1491   VEX_W_0F44_L_0_M_1,
1492   VEX_W_0F45_L_1_M_1,
1493   VEX_W_0F46_L_1_M_1,
1494   VEX_W_0F47_L_1_M_1,
1495   VEX_W_0F4A_L_1_M_1,
1496   VEX_W_0F4B_L_1_M_1,
1497   VEX_W_0F90_L_0,
1498   VEX_W_0F91_L_0_M_0,
1499   VEX_W_0F92_L_0_M_1,
1500   VEX_W_0F93_L_0_M_1,
1501   VEX_W_0F98_L_0_M_1,
1502   VEX_W_0F99_L_0_M_1,
1503   VEX_W_0F380C,
1504   VEX_W_0F380D,
1505   VEX_W_0F380E,
1506   VEX_W_0F380F,
1507   VEX_W_0F3813,
1508   VEX_W_0F3816_L_1,
1509   VEX_W_0F3818,
1510   VEX_W_0F3819_L_1,
1511   VEX_W_0F381A_M_0_L_1,
1512   VEX_W_0F382C_M_0,
1513   VEX_W_0F382D_M_0,
1514   VEX_W_0F382E_M_0,
1515   VEX_W_0F382F_M_0,
1516   VEX_W_0F3836,
1517   VEX_W_0F3846,
1518   VEX_W_0F3849_X86_64_P_0,
1519   VEX_W_0F3849_X86_64_P_2,
1520   VEX_W_0F3849_X86_64_P_3,
1521   VEX_W_0F384B_X86_64_P_1,
1522   VEX_W_0F384B_X86_64_P_2,
1523   VEX_W_0F384B_X86_64_P_3,
1524   VEX_W_0F3850,
1525   VEX_W_0F3851,
1526   VEX_W_0F3852,
1527   VEX_W_0F3853,
1528   VEX_W_0F3858,
1529   VEX_W_0F3859,
1530   VEX_W_0F385A_M_0_L_0,
1531   VEX_W_0F385C_X86_64_P_1,
1532   VEX_W_0F385E_X86_64_P_0,
1533   VEX_W_0F385E_X86_64_P_1,
1534   VEX_W_0F385E_X86_64_P_2,
1535   VEX_W_0F385E_X86_64_P_3,
1536   VEX_W_0F3878,
1537   VEX_W_0F3879,
1538   VEX_W_0F38CF,
1539   VEX_W_0F3A00_L_1,
1540   VEX_W_0F3A01_L_1,
1541   VEX_W_0F3A02,
1542   VEX_W_0F3A04,
1543   VEX_W_0F3A05,
1544   VEX_W_0F3A06_L_1,
1545   VEX_W_0F3A18_L_1,
1546   VEX_W_0F3A19_L_1,
1547   VEX_W_0F3A1D,
1548   VEX_W_0F3A38_L_1,
1549   VEX_W_0F3A39_L_1,
1550   VEX_W_0F3A46_L_1,
1551   VEX_W_0F3A4A,
1552   VEX_W_0F3A4B,
1553   VEX_W_0F3A4C,
1554   VEX_W_0F3ACE,
1555   VEX_W_0F3ACF,
1556
1557   VEX_W_0FXOP_08_85_L_0,
1558   VEX_W_0FXOP_08_86_L_0,
1559   VEX_W_0FXOP_08_87_L_0,
1560   VEX_W_0FXOP_08_8E_L_0,
1561   VEX_W_0FXOP_08_8F_L_0,
1562   VEX_W_0FXOP_08_95_L_0,
1563   VEX_W_0FXOP_08_96_L_0,
1564   VEX_W_0FXOP_08_97_L_0,
1565   VEX_W_0FXOP_08_9E_L_0,
1566   VEX_W_0FXOP_08_9F_L_0,
1567   VEX_W_0FXOP_08_A6_L_0,
1568   VEX_W_0FXOP_08_B6_L_0,
1569   VEX_W_0FXOP_08_C0_L_0,
1570   VEX_W_0FXOP_08_C1_L_0,
1571   VEX_W_0FXOP_08_C2_L_0,
1572   VEX_W_0FXOP_08_C3_L_0,
1573   VEX_W_0FXOP_08_CC_L_0,
1574   VEX_W_0FXOP_08_CD_L_0,
1575   VEX_W_0FXOP_08_CE_L_0,
1576   VEX_W_0FXOP_08_CF_L_0,
1577   VEX_W_0FXOP_08_EC_L_0,
1578   VEX_W_0FXOP_08_ED_L_0,
1579   VEX_W_0FXOP_08_EE_L_0,
1580   VEX_W_0FXOP_08_EF_L_0,
1581
1582   VEX_W_0FXOP_09_80,
1583   VEX_W_0FXOP_09_81,
1584   VEX_W_0FXOP_09_82,
1585   VEX_W_0FXOP_09_83,
1586   VEX_W_0FXOP_09_C1_L_0,
1587   VEX_W_0FXOP_09_C2_L_0,
1588   VEX_W_0FXOP_09_C3_L_0,
1589   VEX_W_0FXOP_09_C6_L_0,
1590   VEX_W_0FXOP_09_C7_L_0,
1591   VEX_W_0FXOP_09_CB_L_0,
1592   VEX_W_0FXOP_09_D1_L_0,
1593   VEX_W_0FXOP_09_D2_L_0,
1594   VEX_W_0FXOP_09_D3_L_0,
1595   VEX_W_0FXOP_09_D6_L_0,
1596   VEX_W_0FXOP_09_D7_L_0,
1597   VEX_W_0FXOP_09_DB_L_0,
1598   VEX_W_0FXOP_09_E1_L_0,
1599   VEX_W_0FXOP_09_E2_L_0,
1600   VEX_W_0FXOP_09_E3_L_0,
1601
1602   EVEX_W_0F5B_P_0,
1603   EVEX_W_0F62,
1604   EVEX_W_0F66,
1605   EVEX_W_0F6A,
1606   EVEX_W_0F6B,
1607   EVEX_W_0F6C,
1608   EVEX_W_0F6D,
1609   EVEX_W_0F6F_P_1,
1610   EVEX_W_0F6F_P_2,
1611   EVEX_W_0F6F_P_3,
1612   EVEX_W_0F70_P_2,
1613   EVEX_W_0F72_R_2,
1614   EVEX_W_0F72_R_6,
1615   EVEX_W_0F73_R_2,
1616   EVEX_W_0F73_R_6,
1617   EVEX_W_0F76,
1618   EVEX_W_0F78_P_0,
1619   EVEX_W_0F78_P_2,
1620   EVEX_W_0F79_P_0,
1621   EVEX_W_0F79_P_2,
1622   EVEX_W_0F7A_P_1,
1623   EVEX_W_0F7A_P_2,
1624   EVEX_W_0F7A_P_3,
1625   EVEX_W_0F7B_P_2,
1626   EVEX_W_0F7E_P_1,
1627   EVEX_W_0F7F_P_1,
1628   EVEX_W_0F7F_P_2,
1629   EVEX_W_0F7F_P_3,
1630   EVEX_W_0FD2,
1631   EVEX_W_0FD3,
1632   EVEX_W_0FD4,
1633   EVEX_W_0FD6,
1634   EVEX_W_0FE6_P_1,
1635   EVEX_W_0FE7,
1636   EVEX_W_0FF2,
1637   EVEX_W_0FF3,
1638   EVEX_W_0FF4,
1639   EVEX_W_0FFA,
1640   EVEX_W_0FFB,
1641   EVEX_W_0FFE,
1642
1643   EVEX_W_0F3810_P_1,
1644   EVEX_W_0F3810_P_2,
1645   EVEX_W_0F3811_P_1,
1646   EVEX_W_0F3811_P_2,
1647   EVEX_W_0F3812_P_1,
1648   EVEX_W_0F3812_P_2,
1649   EVEX_W_0F3813_P_1,
1650   EVEX_W_0F3814_P_1,
1651   EVEX_W_0F3815_P_1,
1652   EVEX_W_0F3819_L_n,
1653   EVEX_W_0F381A_M_0_L_n,
1654   EVEX_W_0F381B_M_0_L_2,
1655   EVEX_W_0F381E,
1656   EVEX_W_0F381F,
1657   EVEX_W_0F3820_P_1,
1658   EVEX_W_0F3821_P_1,
1659   EVEX_W_0F3822_P_1,
1660   EVEX_W_0F3823_P_1,
1661   EVEX_W_0F3824_P_1,
1662   EVEX_W_0F3825_P_1,
1663   EVEX_W_0F3825_P_2,
1664   EVEX_W_0F3828_P_2,
1665   EVEX_W_0F3829_P_2,
1666   EVEX_W_0F382A_P_1,
1667   EVEX_W_0F382A_P_2,
1668   EVEX_W_0F382B,
1669   EVEX_W_0F3830_P_1,
1670   EVEX_W_0F3831_P_1,
1671   EVEX_W_0F3832_P_1,
1672   EVEX_W_0F3833_P_1,
1673   EVEX_W_0F3834_P_1,
1674   EVEX_W_0F3835_P_1,
1675   EVEX_W_0F3835_P_2,
1676   EVEX_W_0F3837,
1677   EVEX_W_0F383A_P_1,
1678   EVEX_W_0F3859,
1679   EVEX_W_0F385A_M_0_L_n,
1680   EVEX_W_0F385B_M_0_L_2,
1681   EVEX_W_0F3870,
1682   EVEX_W_0F3872_P_2,
1683   EVEX_W_0F387A,
1684   EVEX_W_0F387B,
1685   EVEX_W_0F3883,
1686
1687   EVEX_W_0F3A18_L_n,
1688   EVEX_W_0F3A19_L_n,
1689   EVEX_W_0F3A1A_L_2,
1690   EVEX_W_0F3A1B_L_2,
1691   EVEX_W_0F3A21,
1692   EVEX_W_0F3A23_L_n,
1693   EVEX_W_0F3A38_L_n,
1694   EVEX_W_0F3A39_L_n,
1695   EVEX_W_0F3A3A_L_2,
1696   EVEX_W_0F3A3B_L_2,
1697   EVEX_W_0F3A42,
1698   EVEX_W_0F3A43_L_n,
1699   EVEX_W_0F3A70,
1700   EVEX_W_0F3A72,
1701
1702   EVEX_W_MAP5_5B_P_0,
1703   EVEX_W_MAP5_7A_P_3,
1704 };
1705
1706 typedef void (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1707
1708 struct dis386 {
1709   const char *name;
1710   struct
1711     {
1712       op_rtn rtn;
1713       int bytemode;
1714     } op[MAX_OPERANDS];
1715   unsigned int prefix_requirement;
1716 };
1717
1718 /* Upper case letters in the instruction names here are macros.
1719    'A' => print 'b' if no register operands or suffix_always is true
1720    'B' => print 'b' if suffix_always is true
1721    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1722           size prefix
1723    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1724           suffix_always is true
1725    'E' => print 'e' if 32-bit form of jcxz
1726    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1727    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1728    'H' => print ",pt" or ",pn" branch hint
1729    'I' unused.
1730    'J' unused.
1731    'K' => print 'd' or 'q' if rex prefix is present.
1732    'L' unused.
1733    'M' => print 'r' if intel_mnemonic is false.
1734    'N' => print 'n' if instruction has no wait "prefix"
1735    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1736    'P' => behave as 'T' except with register operand outside of suffix_always
1737           mode
1738    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1739           is true
1740    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1741    'S' => print 'w', 'l' or 'q' if suffix_always is true
1742    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1743           prefix or if suffix_always is true.
1744    'U' unused.
1745    'V' unused.
1746    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1747    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1748    'Y' unused.
1749    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1750    '!' => change condition from true to false or from false to true.
1751    '%' => add 1 upper case letter to the macro.
1752    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1753           prefix or suffix_always is true (lcall/ljmp).
1754    '@' => in 64bit mode for Intel64 ISA or if instruction
1755           has no operand sizing prefix, print 'q' if suffix_always is true or
1756           nothing otherwise; behave as 'P' in all other cases
1757
1758    2 upper case letter macros:
1759    "XY" => print 'x' or 'y' if suffix_always is true or no register
1760            operands and no broadcast.
1761    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1762            register operands and no broadcast.
1763    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1764    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1765    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1766    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1767    "XV" => print "{vex3}" pseudo prefix
1768    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1769            being false, or no operand at all in 64bit mode, or if suffix_always
1770            is true.
1771    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1772    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1773    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1774    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1775    "BW" => print 'b' or 'w' depending on the VEX.W bit
1776    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1777            an operand size prefix, or suffix_always is true.  print
1778            'q' if rex prefix is present.
1779
1780    Many of the above letters print nothing in Intel mode.  See "putop"
1781    for the details.
1782
1783    Braces '{' and '}', and vertical bars '|', indicate alternative
1784    mnemonic strings for AT&T and Intel.  */
1785
1786 static const struct dis386 dis386[] = {
1787   /* 00 */
1788   { "addB",             { Ebh1, Gb }, 0 },
1789   { "addS",             { Evh1, Gv }, 0 },
1790   { "addB",             { Gb, EbS }, 0 },
1791   { "addS",             { Gv, EvS }, 0 },
1792   { "addB",             { AL, Ib }, 0 },
1793   { "addS",             { eAX, Iv }, 0 },
1794   { X86_64_TABLE (X86_64_06) },
1795   { X86_64_TABLE (X86_64_07) },
1796   /* 08 */
1797   { "orB",              { Ebh1, Gb }, 0 },
1798   { "orS",              { Evh1, Gv }, 0 },
1799   { "orB",              { Gb, EbS }, 0 },
1800   { "orS",              { Gv, EvS }, 0 },
1801   { "orB",              { AL, Ib }, 0 },
1802   { "orS",              { eAX, Iv }, 0 },
1803   { X86_64_TABLE (X86_64_0E) },
1804   { Bad_Opcode },       /* 0x0f extended opcode escape */
1805   /* 10 */
1806   { "adcB",             { Ebh1, Gb }, 0 },
1807   { "adcS",             { Evh1, Gv }, 0 },
1808   { "adcB",             { Gb, EbS }, 0 },
1809   { "adcS",             { Gv, EvS }, 0 },
1810   { "adcB",             { AL, Ib }, 0 },
1811   { "adcS",             { eAX, Iv }, 0 },
1812   { X86_64_TABLE (X86_64_16) },
1813   { X86_64_TABLE (X86_64_17) },
1814   /* 18 */
1815   { "sbbB",             { Ebh1, Gb }, 0 },
1816   { "sbbS",             { Evh1, Gv }, 0 },
1817   { "sbbB",             { Gb, EbS }, 0 },
1818   { "sbbS",             { Gv, EvS }, 0 },
1819   { "sbbB",             { AL, Ib }, 0 },
1820   { "sbbS",             { eAX, Iv }, 0 },
1821   { X86_64_TABLE (X86_64_1E) },
1822   { X86_64_TABLE (X86_64_1F) },
1823   /* 20 */
1824   { "andB",             { Ebh1, Gb }, 0 },
1825   { "andS",             { Evh1, Gv }, 0 },
1826   { "andB",             { Gb, EbS }, 0 },
1827   { "andS",             { Gv, EvS }, 0 },
1828   { "andB",             { AL, Ib }, 0 },
1829   { "andS",             { eAX, Iv }, 0 },
1830   { Bad_Opcode },       /* SEG ES prefix */
1831   { X86_64_TABLE (X86_64_27) },
1832   /* 28 */
1833   { "subB",             { Ebh1, Gb }, 0 },
1834   { "subS",             { Evh1, Gv }, 0 },
1835   { "subB",             { Gb, EbS }, 0 },
1836   { "subS",             { Gv, EvS }, 0 },
1837   { "subB",             { AL, Ib }, 0 },
1838   { "subS",             { eAX, Iv }, 0 },
1839   { Bad_Opcode },       /* SEG CS prefix */
1840   { X86_64_TABLE (X86_64_2F) },
1841   /* 30 */
1842   { "xorB",             { Ebh1, Gb }, 0 },
1843   { "xorS",             { Evh1, Gv }, 0 },
1844   { "xorB",             { Gb, EbS }, 0 },
1845   { "xorS",             { Gv, EvS }, 0 },
1846   { "xorB",             { AL, Ib }, 0 },
1847   { "xorS",             { eAX, Iv }, 0 },
1848   { Bad_Opcode },       /* SEG SS prefix */
1849   { X86_64_TABLE (X86_64_37) },
1850   /* 38 */
1851   { "cmpB",             { Eb, Gb }, 0 },
1852   { "cmpS",             { Ev, Gv }, 0 },
1853   { "cmpB",             { Gb, EbS }, 0 },
1854   { "cmpS",             { Gv, EvS }, 0 },
1855   { "cmpB",             { AL, Ib }, 0 },
1856   { "cmpS",             { eAX, Iv }, 0 },
1857   { Bad_Opcode },       /* SEG DS prefix */
1858   { X86_64_TABLE (X86_64_3F) },
1859   /* 40 */
1860   { "inc{S|}",          { RMeAX }, 0 },
1861   { "inc{S|}",          { RMeCX }, 0 },
1862   { "inc{S|}",          { RMeDX }, 0 },
1863   { "inc{S|}",          { RMeBX }, 0 },
1864   { "inc{S|}",          { RMeSP }, 0 },
1865   { "inc{S|}",          { RMeBP }, 0 },
1866   { "inc{S|}",          { RMeSI }, 0 },
1867   { "inc{S|}",          { RMeDI }, 0 },
1868   /* 48 */
1869   { "dec{S|}",          { RMeAX }, 0 },
1870   { "dec{S|}",          { RMeCX }, 0 },
1871   { "dec{S|}",          { RMeDX }, 0 },
1872   { "dec{S|}",          { RMeBX }, 0 },
1873   { "dec{S|}",          { RMeSP }, 0 },
1874   { "dec{S|}",          { RMeBP }, 0 },
1875   { "dec{S|}",          { RMeSI }, 0 },
1876   { "dec{S|}",          { RMeDI }, 0 },
1877   /* 50 */
1878   { "push{!P|}",                { RMrAX }, 0 },
1879   { "push{!P|}",                { RMrCX }, 0 },
1880   { "push{!P|}",                { RMrDX }, 0 },
1881   { "push{!P|}",                { RMrBX }, 0 },
1882   { "push{!P|}",                { RMrSP }, 0 },
1883   { "push{!P|}",                { RMrBP }, 0 },
1884   { "push{!P|}",                { RMrSI }, 0 },
1885   { "push{!P|}",                { RMrDI }, 0 },
1886   /* 58 */
1887   { "pop{!P|}",         { RMrAX }, 0 },
1888   { "pop{!P|}",         { RMrCX }, 0 },
1889   { "pop{!P|}",         { RMrDX }, 0 },
1890   { "pop{!P|}",         { RMrBX }, 0 },
1891   { "pop{!P|}",         { RMrSP }, 0 },
1892   { "pop{!P|}",         { RMrBP }, 0 },
1893   { "pop{!P|}",         { RMrSI }, 0 },
1894   { "pop{!P|}",         { RMrDI }, 0 },
1895   /* 60 */
1896   { X86_64_TABLE (X86_64_60) },
1897   { X86_64_TABLE (X86_64_61) },
1898   { X86_64_TABLE (X86_64_62) },
1899   { X86_64_TABLE (X86_64_63) },
1900   { Bad_Opcode },       /* seg fs */
1901   { Bad_Opcode },       /* seg gs */
1902   { Bad_Opcode },       /* op size prefix */
1903   { Bad_Opcode },       /* adr size prefix */
1904   /* 68 */
1905   { "pushP",            { sIv }, 0 },
1906   { "imulS",            { Gv, Ev, Iv }, 0 },
1907   { "pushP",            { sIbT }, 0 },
1908   { "imulS",            { Gv, Ev, sIb }, 0 },
1909   { "ins{b|}",          { Ybr, indirDX }, 0 },
1910   { X86_64_TABLE (X86_64_6D) },
1911   { "outs{b|}",         { indirDXr, Xb }, 0 },
1912   { X86_64_TABLE (X86_64_6F) },
1913   /* 70 */
1914   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1915   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1916   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1917   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1918   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1919   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1920   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1921   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1922   /* 78 */
1923   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1924   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1925   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1926   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1927   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1928   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1929   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1930   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1931   /* 80 */
1932   { REG_TABLE (REG_80) },
1933   { REG_TABLE (REG_81) },
1934   { X86_64_TABLE (X86_64_82) },
1935   { REG_TABLE (REG_83) },
1936   { "testB",            { Eb, Gb }, 0 },
1937   { "testS",            { Ev, Gv }, 0 },
1938   { "xchgB",            { Ebh2, Gb }, 0 },
1939   { "xchgS",            { Evh2, Gv }, 0 },
1940   /* 88 */
1941   { "movB",             { Ebh3, Gb }, 0 },
1942   { "movS",             { Evh3, Gv }, 0 },
1943   { "movB",             { Gb, EbS }, 0 },
1944   { "movS",             { Gv, EvS }, 0 },
1945   { "movD",             { Sv, Sw }, 0 },
1946   { MOD_TABLE (MOD_8D) },
1947   { "movD",             { Sw, Sv }, 0 },
1948   { REG_TABLE (REG_8F) },
1949   /* 90 */
1950   { PREFIX_TABLE (PREFIX_90) },
1951   { "xchgS",            { RMeCX, eAX }, 0 },
1952   { "xchgS",            { RMeDX, eAX }, 0 },
1953   { "xchgS",            { RMeBX, eAX }, 0 },
1954   { "xchgS",            { RMeSP, eAX }, 0 },
1955   { "xchgS",            { RMeBP, eAX }, 0 },
1956   { "xchgS",            { RMeSI, eAX }, 0 },
1957   { "xchgS",            { RMeDI, eAX }, 0 },
1958   /* 98 */
1959   { "cW{t|}R",          { XX }, 0 },
1960   { "cR{t|}O",          { XX }, 0 },
1961   { X86_64_TABLE (X86_64_9A) },
1962   { Bad_Opcode },       /* fwait */
1963   { "pushfP",           { XX }, 0 },
1964   { "popfP",            { XX }, 0 },
1965   { "sahf",             { XX }, 0 },
1966   { "lahf",             { XX }, 0 },
1967   /* a0 */
1968   { "mov%LB",           { AL, Ob }, 0 },
1969   { "mov%LS",           { eAX, Ov }, 0 },
1970   { "mov%LB",           { Ob, AL }, 0 },
1971   { "mov%LS",           { Ov, eAX }, 0 },
1972   { "movs{b|}",         { Ybr, Xb }, 0 },
1973   { "movs{R|}",         { Yvr, Xv }, 0 },
1974   { "cmps{b|}",         { Xb, Yb }, 0 },
1975   { "cmps{R|}",         { Xv, Yv }, 0 },
1976   /* a8 */
1977   { "testB",            { AL, Ib }, 0 },
1978   { "testS",            { eAX, Iv }, 0 },
1979   { "stosB",            { Ybr, AL }, 0 },
1980   { "stosS",            { Yvr, eAX }, 0 },
1981   { "lodsB",            { ALr, Xb }, 0 },
1982   { "lodsS",            { eAXr, Xv }, 0 },
1983   { "scasB",            { AL, Yb }, 0 },
1984   { "scasS",            { eAX, Yv }, 0 },
1985   /* b0 */
1986   { "movB",             { RMAL, Ib }, 0 },
1987   { "movB",             { RMCL, Ib }, 0 },
1988   { "movB",             { RMDL, Ib }, 0 },
1989   { "movB",             { RMBL, Ib }, 0 },
1990   { "movB",             { RMAH, Ib }, 0 },
1991   { "movB",             { RMCH, Ib }, 0 },
1992   { "movB",             { RMDH, Ib }, 0 },
1993   { "movB",             { RMBH, Ib }, 0 },
1994   /* b8 */
1995   { "mov%LV",           { RMeAX, Iv64 }, 0 },
1996   { "mov%LV",           { RMeCX, Iv64 }, 0 },
1997   { "mov%LV",           { RMeDX, Iv64 }, 0 },
1998   { "mov%LV",           { RMeBX, Iv64 }, 0 },
1999   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2000   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2001   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2002   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2003   /* c0 */
2004   { REG_TABLE (REG_C0) },
2005   { REG_TABLE (REG_C1) },
2006   { X86_64_TABLE (X86_64_C2) },
2007   { X86_64_TABLE (X86_64_C3) },
2008   { X86_64_TABLE (X86_64_C4) },
2009   { X86_64_TABLE (X86_64_C5) },
2010   { REG_TABLE (REG_C6) },
2011   { REG_TABLE (REG_C7) },
2012   /* c8 */
2013   { "enterP",           { Iw, Ib }, 0 },
2014   { "leaveP",           { XX }, 0 },
2015   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2016   { "{l|}ret{|f}%LP",   { XX }, 0 },
2017   { "int3",             { XX }, 0 },
2018   { "int",              { Ib }, 0 },
2019   { X86_64_TABLE (X86_64_CE) },
2020   { "iret%LP",          { XX }, 0 },
2021   /* d0 */
2022   { REG_TABLE (REG_D0) },
2023   { REG_TABLE (REG_D1) },
2024   { REG_TABLE (REG_D2) },
2025   { REG_TABLE (REG_D3) },
2026   { X86_64_TABLE (X86_64_D4) },
2027   { X86_64_TABLE (X86_64_D5) },
2028   { Bad_Opcode },
2029   { "xlat",             { DSBX }, 0 },
2030   /* d8 */
2031   { FLOAT },
2032   { FLOAT },
2033   { FLOAT },
2034   { FLOAT },
2035   { FLOAT },
2036   { FLOAT },
2037   { FLOAT },
2038   { FLOAT },
2039   /* e0 */
2040   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2041   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2042   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2043   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2044   { "inB",              { AL, Ib }, 0 },
2045   { "inG",              { zAX, Ib }, 0 },
2046   { "outB",             { Ib, AL }, 0 },
2047   { "outG",             { Ib, zAX }, 0 },
2048   /* e8 */
2049   { X86_64_TABLE (X86_64_E8) },
2050   { X86_64_TABLE (X86_64_E9) },
2051   { X86_64_TABLE (X86_64_EA) },
2052   { "jmp",              { Jb, BND }, 0 },
2053   { "inB",              { AL, indirDX }, 0 },
2054   { "inG",              { zAX, indirDX }, 0 },
2055   { "outB",             { indirDX, AL }, 0 },
2056   { "outG",             { indirDX, zAX }, 0 },
2057   /* f0 */
2058   { Bad_Opcode },       /* lock prefix */
2059   { "int1",             { XX }, 0 },
2060   { Bad_Opcode },       /* repne */
2061   { Bad_Opcode },       /* repz */
2062   { "hlt",              { XX }, 0 },
2063   { "cmc",              { XX }, 0 },
2064   { REG_TABLE (REG_F6) },
2065   { REG_TABLE (REG_F7) },
2066   /* f8 */
2067   { "clc",              { XX }, 0 },
2068   { "stc",              { XX }, 0 },
2069   { "cli",              { XX }, 0 },
2070   { "sti",              { XX }, 0 },
2071   { "cld",              { XX }, 0 },
2072   { "std",              { XX }, 0 },
2073   { REG_TABLE (REG_FE) },
2074   { REG_TABLE (REG_FF) },
2075 };
2076
2077 static const struct dis386 dis386_twobyte[] = {
2078   /* 00 */
2079   { REG_TABLE (REG_0F00 ) },
2080   { REG_TABLE (REG_0F01 ) },
2081   { "larS",             { Gv, Ew }, 0 },
2082   { "lslS",             { Gv, Ew }, 0 },
2083   { Bad_Opcode },
2084   { "syscall",          { XX }, 0 },
2085   { "clts",             { XX }, 0 },
2086   { "sysret%LQ",                { XX }, 0 },
2087   /* 08 */
2088   { "invd",             { XX }, 0 },
2089   { PREFIX_TABLE (PREFIX_0F09) },
2090   { Bad_Opcode },
2091   { "ud2",              { XX }, 0 },
2092   { Bad_Opcode },
2093   { REG_TABLE (REG_0F0D) },
2094   { "femms",            { XX }, 0 },
2095   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2096   /* 10 */
2097   { PREFIX_TABLE (PREFIX_0F10) },
2098   { PREFIX_TABLE (PREFIX_0F11) },
2099   { PREFIX_TABLE (PREFIX_0F12) },
2100   { MOD_TABLE (MOD_0F13) },
2101   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2102   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2103   { PREFIX_TABLE (PREFIX_0F16) },
2104   { MOD_TABLE (MOD_0F17) },
2105   /* 18 */
2106   { REG_TABLE (REG_0F18) },
2107   { "nopQ",             { Ev }, 0 },
2108   { PREFIX_TABLE (PREFIX_0F1A) },
2109   { PREFIX_TABLE (PREFIX_0F1B) },
2110   { PREFIX_TABLE (PREFIX_0F1C) },
2111   { "nopQ",             { Ev }, 0 },
2112   { PREFIX_TABLE (PREFIX_0F1E) },
2113   { "nopQ",             { Ev }, 0 },
2114   /* 20 */
2115   { "movZ",             { Em, Cm }, 0 },
2116   { "movZ",             { Em, Dm }, 0 },
2117   { "movZ",             { Cm, Em }, 0 },
2118   { "movZ",             { Dm, Em }, 0 },
2119   { X86_64_TABLE (X86_64_0F24) },
2120   { Bad_Opcode },
2121   { X86_64_TABLE (X86_64_0F26) },
2122   { Bad_Opcode },
2123   /* 28 */
2124   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2125   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2126   { PREFIX_TABLE (PREFIX_0F2A) },
2127   { PREFIX_TABLE (PREFIX_0F2B) },
2128   { PREFIX_TABLE (PREFIX_0F2C) },
2129   { PREFIX_TABLE (PREFIX_0F2D) },
2130   { PREFIX_TABLE (PREFIX_0F2E) },
2131   { PREFIX_TABLE (PREFIX_0F2F) },
2132   /* 30 */
2133   { "wrmsr",            { XX }, 0 },
2134   { "rdtsc",            { XX }, 0 },
2135   { "rdmsr",            { XX }, 0 },
2136   { "rdpmc",            { XX }, 0 },
2137   { "sysenter",         { SEP }, 0 },
2138   { "sysexit%LQ",       { SEP }, 0 },
2139   { Bad_Opcode },
2140   { "getsec",           { XX }, 0 },
2141   /* 38 */
2142   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2143   { Bad_Opcode },
2144   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2145   { Bad_Opcode },
2146   { Bad_Opcode },
2147   { Bad_Opcode },
2148   { Bad_Opcode },
2149   { Bad_Opcode },
2150   /* 40 */
2151   { "cmovoS",           { Gv, Ev }, 0 },
2152   { "cmovnoS",          { Gv, Ev }, 0 },
2153   { "cmovbS",           { Gv, Ev }, 0 },
2154   { "cmovaeS",          { Gv, Ev }, 0 },
2155   { "cmoveS",           { Gv, Ev }, 0 },
2156   { "cmovneS",          { Gv, Ev }, 0 },
2157   { "cmovbeS",          { Gv, Ev }, 0 },
2158   { "cmovaS",           { Gv, Ev }, 0 },
2159   /* 48 */
2160   { "cmovsS",           { Gv, Ev }, 0 },
2161   { "cmovnsS",          { Gv, Ev }, 0 },
2162   { "cmovpS",           { Gv, Ev }, 0 },
2163   { "cmovnpS",          { Gv, Ev }, 0 },
2164   { "cmovlS",           { Gv, Ev }, 0 },
2165   { "cmovgeS",          { Gv, Ev }, 0 },
2166   { "cmovleS",          { Gv, Ev }, 0 },
2167   { "cmovgS",           { Gv, Ev }, 0 },
2168   /* 50 */
2169   { MOD_TABLE (MOD_0F50) },
2170   { PREFIX_TABLE (PREFIX_0F51) },
2171   { PREFIX_TABLE (PREFIX_0F52) },
2172   { PREFIX_TABLE (PREFIX_0F53) },
2173   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2174   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2175   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2176   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2177   /* 58 */
2178   { PREFIX_TABLE (PREFIX_0F58) },
2179   { PREFIX_TABLE (PREFIX_0F59) },
2180   { PREFIX_TABLE (PREFIX_0F5A) },
2181   { PREFIX_TABLE (PREFIX_0F5B) },
2182   { PREFIX_TABLE (PREFIX_0F5C) },
2183   { PREFIX_TABLE (PREFIX_0F5D) },
2184   { PREFIX_TABLE (PREFIX_0F5E) },
2185   { PREFIX_TABLE (PREFIX_0F5F) },
2186   /* 60 */
2187   { PREFIX_TABLE (PREFIX_0F60) },
2188   { PREFIX_TABLE (PREFIX_0F61) },
2189   { PREFIX_TABLE (PREFIX_0F62) },
2190   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2191   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2192   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2193   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2194   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2195   /* 68 */
2196   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2197   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2198   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2199   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2200   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2201   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2202   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2203   { PREFIX_TABLE (PREFIX_0F6F) },
2204   /* 70 */
2205   { PREFIX_TABLE (PREFIX_0F70) },
2206   { MOD_TABLE (MOD_0F71) },
2207   { MOD_TABLE (MOD_0F72) },
2208   { MOD_TABLE (MOD_0F73) },
2209   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2210   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2211   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2212   { "emms",             { XX }, PREFIX_OPCODE },
2213   /* 78 */
2214   { PREFIX_TABLE (PREFIX_0F78) },
2215   { PREFIX_TABLE (PREFIX_0F79) },
2216   { Bad_Opcode },
2217   { Bad_Opcode },
2218   { PREFIX_TABLE (PREFIX_0F7C) },
2219   { PREFIX_TABLE (PREFIX_0F7D) },
2220   { PREFIX_TABLE (PREFIX_0F7E) },
2221   { PREFIX_TABLE (PREFIX_0F7F) },
2222   /* 80 */
2223   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2224   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2225   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2226   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2227   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2228   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2229   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2230   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2231   /* 88 */
2232   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2233   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2234   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2235   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2236   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2237   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2238   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2239   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2240   /* 90 */
2241   { "seto",             { Eb }, 0 },
2242   { "setno",            { Eb }, 0 },
2243   { "setb",             { Eb }, 0 },
2244   { "setae",            { Eb }, 0 },
2245   { "sete",             { Eb }, 0 },
2246   { "setne",            { Eb }, 0 },
2247   { "setbe",            { Eb }, 0 },
2248   { "seta",             { Eb }, 0 },
2249   /* 98 */
2250   { "sets",             { Eb }, 0 },
2251   { "setns",            { Eb }, 0 },
2252   { "setp",             { Eb }, 0 },
2253   { "setnp",            { Eb }, 0 },
2254   { "setl",             { Eb }, 0 },
2255   { "setge",            { Eb }, 0 },
2256   { "setle",            { Eb }, 0 },
2257   { "setg",             { Eb }, 0 },
2258   /* a0 */
2259   { "pushP",            { fs }, 0 },
2260   { "popP",             { fs }, 0 },
2261   { "cpuid",            { XX }, 0 },
2262   { "btS",              { Ev, Gv }, 0 },
2263   { "shldS",            { Ev, Gv, Ib }, 0 },
2264   { "shldS",            { Ev, Gv, CL }, 0 },
2265   { REG_TABLE (REG_0FA6) },
2266   { REG_TABLE (REG_0FA7) },
2267   /* a8 */
2268   { "pushP",            { gs }, 0 },
2269   { "popP",             { gs }, 0 },
2270   { "rsm",              { XX }, 0 },
2271   { "btsS",             { Evh1, Gv }, 0 },
2272   { "shrdS",            { Ev, Gv, Ib }, 0 },
2273   { "shrdS",            { Ev, Gv, CL }, 0 },
2274   { REG_TABLE (REG_0FAE) },
2275   { "imulS",            { Gv, Ev }, 0 },
2276   /* b0 */
2277   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2278   { "cmpxchgS",         { Evh1, Gv }, 0 },
2279   { MOD_TABLE (MOD_0FB2) },
2280   { "btrS",             { Evh1, Gv }, 0 },
2281   { MOD_TABLE (MOD_0FB4) },
2282   { MOD_TABLE (MOD_0FB5) },
2283   { "movz{bR|x}",       { Gv, Eb }, 0 },
2284   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2285   /* b8 */
2286   { PREFIX_TABLE (PREFIX_0FB8) },
2287   { "ud1S",             { Gv, Ev }, 0 },
2288   { REG_TABLE (REG_0FBA) },
2289   { "btcS",             { Evh1, Gv }, 0 },
2290   { PREFIX_TABLE (PREFIX_0FBC) },
2291   { PREFIX_TABLE (PREFIX_0FBD) },
2292   { "movs{bR|x}",       { Gv, Eb }, 0 },
2293   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2294   /* c0 */
2295   { "xaddB",            { Ebh1, Gb }, 0 },
2296   { "xaddS",            { Evh1, Gv }, 0 },
2297   { PREFIX_TABLE (PREFIX_0FC2) },
2298   { MOD_TABLE (MOD_0FC3) },
2299   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2300   { "pextrw",           { Gd, MS, Ib }, PREFIX_OPCODE },
2301   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2302   { REG_TABLE (REG_0FC7) },
2303   /* c8 */
2304   { "bswap",            { RMeAX }, 0 },
2305   { "bswap",            { RMeCX }, 0 },
2306   { "bswap",            { RMeDX }, 0 },
2307   { "bswap",            { RMeBX }, 0 },
2308   { "bswap",            { RMeSP }, 0 },
2309   { "bswap",            { RMeBP }, 0 },
2310   { "bswap",            { RMeSI }, 0 },
2311   { "bswap",            { RMeDI }, 0 },
2312   /* d0 */
2313   { PREFIX_TABLE (PREFIX_0FD0) },
2314   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2315   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2316   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2317   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2318   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2319   { PREFIX_TABLE (PREFIX_0FD6) },
2320   { MOD_TABLE (MOD_0FD7) },
2321   /* d8 */
2322   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2323   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2324   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2325   { "pand",             { MX, EM }, PREFIX_OPCODE },
2326   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2327   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2328   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2329   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2330   /* e0 */
2331   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2332   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2333   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2334   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2335   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2336   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2337   { PREFIX_TABLE (PREFIX_0FE6) },
2338   { PREFIX_TABLE (PREFIX_0FE7) },
2339   /* e8 */
2340   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2341   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2342   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2343   { "por",              { MX, EM }, PREFIX_OPCODE },
2344   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2345   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2346   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2347   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2348   /* f0 */
2349   { PREFIX_TABLE (PREFIX_0FF0) },
2350   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2351   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2352   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2353   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2354   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2355   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2356   { PREFIX_TABLE (PREFIX_0FF7) },
2357   /* f8 */
2358   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2359   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2360   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2361   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2362   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2363   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2364   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2365   { "ud0S",             { Gv, Ev }, 0 },
2366 };
2367
2368 static const unsigned char onebyte_has_modrm[256] = {
2369   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2370   /*       -------------------------------        */
2371   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2372   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2373   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2374   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2375   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2376   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2377   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2378   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2379   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2380   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2381   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2382   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2383   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2384   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2385   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2386   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2387   /*       -------------------------------        */
2388   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2389 };
2390
2391 static const unsigned char twobyte_has_modrm[256] = {
2392   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2393   /*       -------------------------------        */
2394   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2395   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2396   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2397   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2398   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2399   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2400   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2401   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2402   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2403   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2404   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2405   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2406   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2407   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2408   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2409   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2410   /*       -------------------------------        */
2411   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2412 };
2413
2414
2415 struct op
2416   {
2417     const char *name;
2418     unsigned int len;
2419   };
2420
2421 /* If we are accessing mod/rm/reg without need_modrm set, then the
2422    values are stale.  Hitting this abort likely indicates that you
2423    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2424 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2425
2426 static const char *intel_names64[] = {
2427   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2428   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2429 };
2430 static const char *intel_names32[] = {
2431   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2432   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2433 };
2434 static const char *intel_names16[] = {
2435   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2436   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2437 };
2438 static const char *intel_names8[] = {
2439   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2440 };
2441 static const char *intel_names8rex[] = {
2442   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2443   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2444 };
2445 static const char *intel_names_seg[] = {
2446   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2447 };
2448 static const char *intel_index64 = "riz";
2449 static const char *intel_index32 = "eiz";
2450 static const char *intel_index16[] = {
2451   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2452 };
2453
2454 static const char *att_names64[] = {
2455   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2456   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2457 };
2458 static const char *att_names32[] = {
2459   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2460   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2461 };
2462 static const char *att_names16[] = {
2463   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2464   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2465 };
2466 static const char *att_names8[] = {
2467   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2468 };
2469 static const char *att_names8rex[] = {
2470   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2471   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2472 };
2473 static const char *att_names_seg[] = {
2474   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2475 };
2476 static const char *att_index64 = "%riz";
2477 static const char *att_index32 = "%eiz";
2478 static const char *att_index16[] = {
2479   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2480 };
2481
2482 static const char *intel_names_mm[] = {
2483   "mm0", "mm1", "mm2", "mm3",
2484   "mm4", "mm5", "mm6", "mm7"
2485 };
2486 static const char *att_names_mm[] = {
2487   "%mm0", "%mm1", "%mm2", "%mm3",
2488   "%mm4", "%mm5", "%mm6", "%mm7"
2489 };
2490
2491 static const char *intel_names_bnd[] = {
2492   "bnd0", "bnd1", "bnd2", "bnd3"
2493 };
2494
2495 static const char *att_names_bnd[] = {
2496   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2497 };
2498
2499 static const char *intel_names_xmm[] = {
2500   "xmm0", "xmm1", "xmm2", "xmm3",
2501   "xmm4", "xmm5", "xmm6", "xmm7",
2502   "xmm8", "xmm9", "xmm10", "xmm11",
2503   "xmm12", "xmm13", "xmm14", "xmm15",
2504   "xmm16", "xmm17", "xmm18", "xmm19",
2505   "xmm20", "xmm21", "xmm22", "xmm23",
2506   "xmm24", "xmm25", "xmm26", "xmm27",
2507   "xmm28", "xmm29", "xmm30", "xmm31"
2508 };
2509 static const char *att_names_xmm[] = {
2510   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2511   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2512   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2513   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2514   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2515   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2516   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2517   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2518 };
2519
2520 static const char *intel_names_ymm[] = {
2521   "ymm0", "ymm1", "ymm2", "ymm3",
2522   "ymm4", "ymm5", "ymm6", "ymm7",
2523   "ymm8", "ymm9", "ymm10", "ymm11",
2524   "ymm12", "ymm13", "ymm14", "ymm15",
2525   "ymm16", "ymm17", "ymm18", "ymm19",
2526   "ymm20", "ymm21", "ymm22", "ymm23",
2527   "ymm24", "ymm25", "ymm26", "ymm27",
2528   "ymm28", "ymm29", "ymm30", "ymm31"
2529 };
2530 static const char *att_names_ymm[] = {
2531   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2532   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2533   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2534   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2535   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2536   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2537   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2538   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2539 };
2540
2541 static const char *intel_names_zmm[] = {
2542   "zmm0", "zmm1", "zmm2", "zmm3",
2543   "zmm4", "zmm5", "zmm6", "zmm7",
2544   "zmm8", "zmm9", "zmm10", "zmm11",
2545   "zmm12", "zmm13", "zmm14", "zmm15",
2546   "zmm16", "zmm17", "zmm18", "zmm19",
2547   "zmm20", "zmm21", "zmm22", "zmm23",
2548   "zmm24", "zmm25", "zmm26", "zmm27",
2549   "zmm28", "zmm29", "zmm30", "zmm31"
2550 };
2551 static const char *att_names_zmm[] = {
2552   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2553   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2554   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2555   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2556   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2557   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2558   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2559   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2560 };
2561
2562 static const char *intel_names_tmm[] = {
2563   "tmm0", "tmm1", "tmm2", "tmm3",
2564   "tmm4", "tmm5", "tmm6", "tmm7"
2565 };
2566 static const char *att_names_tmm[] = {
2567   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2568   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2569 };
2570
2571 static const char *intel_names_mask[] = {
2572   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2573 };
2574 static const char *att_names_mask[] = {
2575   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2576 };
2577
2578 static const char *const names_rounding[] =
2579 {
2580   "{rn-",
2581   "{rd-",
2582   "{ru-",
2583   "{rz-"
2584 };
2585
2586 static const struct dis386 reg_table[][8] = {
2587   /* REG_80 */
2588   {
2589     { "addA",   { Ebh1, Ib }, 0 },
2590     { "orA",    { Ebh1, Ib }, 0 },
2591     { "adcA",   { Ebh1, Ib }, 0 },
2592     { "sbbA",   { Ebh1, Ib }, 0 },
2593     { "andA",   { Ebh1, Ib }, 0 },
2594     { "subA",   { Ebh1, Ib }, 0 },
2595     { "xorA",   { Ebh1, Ib }, 0 },
2596     { "cmpA",   { Eb, Ib }, 0 },
2597   },
2598   /* REG_81 */
2599   {
2600     { "addQ",   { Evh1, Iv }, 0 },
2601     { "orQ",    { Evh1, Iv }, 0 },
2602     { "adcQ",   { Evh1, Iv }, 0 },
2603     { "sbbQ",   { Evh1, Iv }, 0 },
2604     { "andQ",   { Evh1, Iv }, 0 },
2605     { "subQ",   { Evh1, Iv }, 0 },
2606     { "xorQ",   { Evh1, Iv }, 0 },
2607     { "cmpQ",   { Ev, Iv }, 0 },
2608   },
2609   /* REG_83 */
2610   {
2611     { "addQ",   { Evh1, sIb }, 0 },
2612     { "orQ",    { Evh1, sIb }, 0 },
2613     { "adcQ",   { Evh1, sIb }, 0 },
2614     { "sbbQ",   { Evh1, sIb }, 0 },
2615     { "andQ",   { Evh1, sIb }, 0 },
2616     { "subQ",   { Evh1, sIb }, 0 },
2617     { "xorQ",   { Evh1, sIb }, 0 },
2618     { "cmpQ",   { Ev, sIb }, 0 },
2619   },
2620   /* REG_8F */
2621   {
2622     { "pop{P|}", { stackEv }, 0 },
2623     { XOP_8F_TABLE (XOP_09) },
2624     { Bad_Opcode },
2625     { Bad_Opcode },
2626     { Bad_Opcode },
2627     { XOP_8F_TABLE (XOP_09) },
2628   },
2629   /* REG_C0 */
2630   {
2631     { "rolA",   { Eb, Ib }, 0 },
2632     { "rorA",   { Eb, Ib }, 0 },
2633     { "rclA",   { Eb, Ib }, 0 },
2634     { "rcrA",   { Eb, Ib }, 0 },
2635     { "shlA",   { Eb, Ib }, 0 },
2636     { "shrA",   { Eb, Ib }, 0 },
2637     { "shlA",   { Eb, Ib }, 0 },
2638     { "sarA",   { Eb, Ib }, 0 },
2639   },
2640   /* REG_C1 */
2641   {
2642     { "rolQ",   { Ev, Ib }, 0 },
2643     { "rorQ",   { Ev, Ib }, 0 },
2644     { "rclQ",   { Ev, Ib }, 0 },
2645     { "rcrQ",   { Ev, Ib }, 0 },
2646     { "shlQ",   { Ev, Ib }, 0 },
2647     { "shrQ",   { Ev, Ib }, 0 },
2648     { "shlQ",   { Ev, Ib }, 0 },
2649     { "sarQ",   { Ev, Ib }, 0 },
2650   },
2651   /* REG_C6 */
2652   {
2653     { "movA",   { Ebh3, Ib }, 0 },
2654     { Bad_Opcode },
2655     { Bad_Opcode },
2656     { Bad_Opcode },
2657     { Bad_Opcode },
2658     { Bad_Opcode },
2659     { Bad_Opcode },
2660     { MOD_TABLE (MOD_C6_REG_7) },
2661   },
2662   /* REG_C7 */
2663   {
2664     { "movQ",   { Evh3, Iv }, 0 },
2665     { Bad_Opcode },
2666     { Bad_Opcode },
2667     { Bad_Opcode },
2668     { Bad_Opcode },
2669     { Bad_Opcode },
2670     { Bad_Opcode },
2671     { MOD_TABLE (MOD_C7_REG_7) },
2672   },
2673   /* REG_D0 */
2674   {
2675     { "rolA",   { Eb, I1 }, 0 },
2676     { "rorA",   { Eb, I1 }, 0 },
2677     { "rclA",   { Eb, I1 }, 0 },
2678     { "rcrA",   { Eb, I1 }, 0 },
2679     { "shlA",   { Eb, I1 }, 0 },
2680     { "shrA",   { Eb, I1 }, 0 },
2681     { "shlA",   { Eb, I1 }, 0 },
2682     { "sarA",   { Eb, I1 }, 0 },
2683   },
2684   /* REG_D1 */
2685   {
2686     { "rolQ",   { Ev, I1 }, 0 },
2687     { "rorQ",   { Ev, I1 }, 0 },
2688     { "rclQ",   { Ev, I1 }, 0 },
2689     { "rcrQ",   { Ev, I1 }, 0 },
2690     { "shlQ",   { Ev, I1 }, 0 },
2691     { "shrQ",   { Ev, I1 }, 0 },
2692     { "shlQ",   { Ev, I1 }, 0 },
2693     { "sarQ",   { Ev, I1 }, 0 },
2694   },
2695   /* REG_D2 */
2696   {
2697     { "rolA",   { Eb, CL }, 0 },
2698     { "rorA",   { Eb, CL }, 0 },
2699     { "rclA",   { Eb, CL }, 0 },
2700     { "rcrA",   { Eb, CL }, 0 },
2701     { "shlA",   { Eb, CL }, 0 },
2702     { "shrA",   { Eb, CL }, 0 },
2703     { "shlA",   { Eb, CL }, 0 },
2704     { "sarA",   { Eb, CL }, 0 },
2705   },
2706   /* REG_D3 */
2707   {
2708     { "rolQ",   { Ev, CL }, 0 },
2709     { "rorQ",   { Ev, CL }, 0 },
2710     { "rclQ",   { Ev, CL }, 0 },
2711     { "rcrQ",   { Ev, CL }, 0 },
2712     { "shlQ",   { Ev, CL }, 0 },
2713     { "shrQ",   { Ev, CL }, 0 },
2714     { "shlQ",   { Ev, CL }, 0 },
2715     { "sarQ",   { Ev, CL }, 0 },
2716   },
2717   /* REG_F6 */
2718   {
2719     { "testA",  { Eb, Ib }, 0 },
2720     { "testA",  { Eb, Ib }, 0 },
2721     { "notA",   { Ebh1 }, 0 },
2722     { "negA",   { Ebh1 }, 0 },
2723     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2724     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2725     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2726     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2727   },
2728   /* REG_F7 */
2729   {
2730     { "testQ",  { Ev, Iv }, 0 },
2731     { "testQ",  { Ev, Iv }, 0 },
2732     { "notQ",   { Evh1 }, 0 },
2733     { "negQ",   { Evh1 }, 0 },
2734     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2735     { "imulQ",  { Ev }, 0 },
2736     { "divQ",   { Ev }, 0 },
2737     { "idivQ",  { Ev }, 0 },
2738   },
2739   /* REG_FE */
2740   {
2741     { "incA",   { Ebh1 }, 0 },
2742     { "decA",   { Ebh1 }, 0 },
2743   },
2744   /* REG_FF */
2745   {
2746     { "incQ",   { Evh1 }, 0 },
2747     { "decQ",   { Evh1 }, 0 },
2748     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2749     { MOD_TABLE (MOD_FF_REG_3) },
2750     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2751     { MOD_TABLE (MOD_FF_REG_5) },
2752     { "push{P|}", { stackEv }, 0 },
2753     { Bad_Opcode },
2754   },
2755   /* REG_0F00 */
2756   {
2757     { "sldtD",  { Sv }, 0 },
2758     { "strD",   { Sv }, 0 },
2759     { "lldt",   { Ew }, 0 },
2760     { "ltr",    { Ew }, 0 },
2761     { "verr",   { Ew }, 0 },
2762     { "verw",   { Ew }, 0 },
2763     { Bad_Opcode },
2764     { Bad_Opcode },
2765   },
2766   /* REG_0F01 */
2767   {
2768     { MOD_TABLE (MOD_0F01_REG_0) },
2769     { MOD_TABLE (MOD_0F01_REG_1) },
2770     { MOD_TABLE (MOD_0F01_REG_2) },
2771     { MOD_TABLE (MOD_0F01_REG_3) },
2772     { "smswD",  { Sv }, 0 },
2773     { MOD_TABLE (MOD_0F01_REG_5) },
2774     { "lmsw",   { Ew }, 0 },
2775     { MOD_TABLE (MOD_0F01_REG_7) },
2776   },
2777   /* REG_0F0D */
2778   {
2779     { "prefetch",       { Mb }, 0 },
2780     { "prefetchw",      { Mb }, 0 },
2781     { "prefetchwt1",    { Mb }, 0 },
2782     { "prefetch",       { Mb }, 0 },
2783     { "prefetch",       { Mb }, 0 },
2784     { "prefetch",       { Mb }, 0 },
2785     { "prefetch",       { Mb }, 0 },
2786     { "prefetch",       { Mb }, 0 },
2787   },
2788   /* REG_0F18 */
2789   {
2790     { MOD_TABLE (MOD_0F18_REG_0) },
2791     { MOD_TABLE (MOD_0F18_REG_1) },
2792     { MOD_TABLE (MOD_0F18_REG_2) },
2793     { MOD_TABLE (MOD_0F18_REG_3) },
2794     { "nopQ",           { Ev }, 0 },
2795     { "nopQ",           { Ev }, 0 },
2796     { "nopQ",           { Ev }, 0 },
2797     { "nopQ",           { Ev }, 0 },
2798   },
2799   /* REG_0F1C_P_0_MOD_0 */
2800   {
2801     { "cldemote",       { Mb }, 0 },
2802     { "nopQ",           { Ev }, 0 },
2803     { "nopQ",           { Ev }, 0 },
2804     { "nopQ",           { Ev }, 0 },
2805     { "nopQ",           { Ev }, 0 },
2806     { "nopQ",           { Ev }, 0 },
2807     { "nopQ",           { Ev }, 0 },
2808     { "nopQ",           { Ev }, 0 },
2809   },
2810   /* REG_0F1E_P_1_MOD_3 */
2811   {
2812     { "nopQ",           { Ev }, PREFIX_IGNORED },
2813     { "rdsspK",         { Edq }, 0 },
2814     { "nopQ",           { Ev }, PREFIX_IGNORED },
2815     { "nopQ",           { Ev }, PREFIX_IGNORED },
2816     { "nopQ",           { Ev }, PREFIX_IGNORED },
2817     { "nopQ",           { Ev }, PREFIX_IGNORED },
2818     { "nopQ",           { Ev }, PREFIX_IGNORED },
2819     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2820   },
2821   /* REG_0F38D8_PREFIX_1 */
2822   {
2823     { "aesencwide128kl",        { M }, 0 },
2824     { "aesdecwide128kl",        { M }, 0 },
2825     { "aesencwide256kl",        { M }, 0 },
2826     { "aesdecwide256kl",        { M }, 0 },
2827   },
2828   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2829   {
2830     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2831   },
2832   /* REG_0F71_MOD_0 */
2833   {
2834     { Bad_Opcode },
2835     { Bad_Opcode },
2836     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
2837     { Bad_Opcode },
2838     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
2839     { Bad_Opcode },
2840     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
2841   },
2842   /* REG_0F72_MOD_0 */
2843   {
2844     { Bad_Opcode },
2845     { Bad_Opcode },
2846     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
2847     { Bad_Opcode },
2848     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
2849     { Bad_Opcode },
2850     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
2851   },
2852   /* REG_0F73_MOD_0 */
2853   {
2854     { Bad_Opcode },
2855     { Bad_Opcode },
2856     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
2857     { "psrldq",         { XS, Ib }, PREFIX_DATA },
2858     { Bad_Opcode },
2859     { Bad_Opcode },
2860     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
2861     { "pslldq",         { XS, Ib }, PREFIX_DATA },
2862   },
2863   /* REG_0FA6 */
2864   {
2865     { "montmul",        { { OP_0f07, 0 } }, 0 },
2866     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2867     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2868   },
2869   /* REG_0FA7 */
2870   {
2871     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2872     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2873     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2874     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2875     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2876     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2877   },
2878   /* REG_0FAE */
2879   {
2880     { MOD_TABLE (MOD_0FAE_REG_0) },
2881     { MOD_TABLE (MOD_0FAE_REG_1) },
2882     { MOD_TABLE (MOD_0FAE_REG_2) },
2883     { MOD_TABLE (MOD_0FAE_REG_3) },
2884     { MOD_TABLE (MOD_0FAE_REG_4) },
2885     { MOD_TABLE (MOD_0FAE_REG_5) },
2886     { MOD_TABLE (MOD_0FAE_REG_6) },
2887     { MOD_TABLE (MOD_0FAE_REG_7) },
2888   },
2889   /* REG_0FBA */
2890   {
2891     { Bad_Opcode },
2892     { Bad_Opcode },
2893     { Bad_Opcode },
2894     { Bad_Opcode },
2895     { "btQ",    { Ev, Ib }, 0 },
2896     { "btsQ",   { Evh1, Ib }, 0 },
2897     { "btrQ",   { Evh1, Ib }, 0 },
2898     { "btcQ",   { Evh1, Ib }, 0 },
2899   },
2900   /* REG_0FC7 */
2901   {
2902     { Bad_Opcode },
2903     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2904     { Bad_Opcode },
2905     { MOD_TABLE (MOD_0FC7_REG_3) },
2906     { MOD_TABLE (MOD_0FC7_REG_4) },
2907     { MOD_TABLE (MOD_0FC7_REG_5) },
2908     { MOD_TABLE (MOD_0FC7_REG_6) },
2909     { MOD_TABLE (MOD_0FC7_REG_7) },
2910   },
2911   /* REG_VEX_0F71_M_0 */
2912   {
2913     { Bad_Opcode },
2914     { Bad_Opcode },
2915     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
2916     { Bad_Opcode },
2917     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
2918     { Bad_Opcode },
2919     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
2920   },
2921   /* REG_VEX_0F72_M_0 */
2922   {
2923     { Bad_Opcode },
2924     { Bad_Opcode },
2925     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
2926     { Bad_Opcode },
2927     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
2928     { Bad_Opcode },
2929     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
2930   },
2931   /* REG_VEX_0F73_M_0 */
2932   {
2933     { Bad_Opcode },
2934     { Bad_Opcode },
2935     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
2936     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
2937     { Bad_Opcode },
2938     { Bad_Opcode },
2939     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
2940     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
2941   },
2942   /* REG_VEX_0FAE */
2943   {
2944     { Bad_Opcode },
2945     { Bad_Opcode },
2946     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2947     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2948   },
2949   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2950   {
2951     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2952   },
2953   /* REG_VEX_0F38F3_L_0 */
2954   {
2955     { Bad_Opcode },
2956     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
2957     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
2958     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
2959   },
2960   /* REG_XOP_09_01_L_0 */
2961   {
2962     { Bad_Opcode },
2963     { "blcfill",        { VexGdq, Edq }, 0 },
2964     { "blsfill",        { VexGdq, Edq }, 0 },
2965     { "blcs",   { VexGdq, Edq }, 0 },
2966     { "tzmsk",  { VexGdq, Edq }, 0 },
2967     { "blcic",  { VexGdq, Edq }, 0 },
2968     { "blsic",  { VexGdq, Edq }, 0 },
2969     { "t1mskc", { VexGdq, Edq }, 0 },
2970   },
2971   /* REG_XOP_09_02_L_0 */
2972   {
2973     { Bad_Opcode },
2974     { "blcmsk", { VexGdq, Edq }, 0 },
2975     { Bad_Opcode },
2976     { Bad_Opcode },
2977     { Bad_Opcode },
2978     { Bad_Opcode },
2979     { "blci",   { VexGdq, Edq }, 0 },
2980   },
2981   /* REG_XOP_09_12_M_1_L_0 */
2982   {
2983     { "llwpcb", { Edq }, 0 },
2984     { "slwpcb", { Edq }, 0 },
2985   },
2986   /* REG_XOP_0A_12_L_0 */
2987   {
2988     { "lwpins", { VexGdq, Ed, Id }, 0 },
2989     { "lwpval", { VexGdq, Ed, Id }, 0 },
2990   },
2991
2992 #include "i386-dis-evex-reg.h"
2993 };
2994
2995 static const struct dis386 prefix_table[][4] = {
2996   /* PREFIX_90 */
2997   {
2998     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
2999     { "pause", { XX }, 0 },
3000     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3001     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3002   },
3003
3004   /* PREFIX_0F01_REG_1_RM_4 */
3005   {
3006     { Bad_Opcode },
3007     { Bad_Opcode },
3008     { "tdcall",         { Skip_MODRM }, 0 },
3009     { Bad_Opcode },
3010   },
3011
3012   /* PREFIX_0F01_REG_1_RM_5 */
3013   {
3014     { Bad_Opcode },
3015     { Bad_Opcode },
3016     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3017     { Bad_Opcode },
3018   },
3019
3020   /* PREFIX_0F01_REG_1_RM_6 */
3021   {
3022     { Bad_Opcode },
3023     { Bad_Opcode },
3024     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3025     { Bad_Opcode },
3026   },
3027
3028   /* PREFIX_0F01_REG_1_RM_7 */
3029   {
3030     { "encls",          { Skip_MODRM }, 0 },
3031     { Bad_Opcode },
3032     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3033     { Bad_Opcode },
3034   },
3035
3036   /* PREFIX_0F01_REG_3_RM_1 */
3037   {
3038     { "vmmcall",        { Skip_MODRM }, 0 },
3039     { "vmgexit",        { Skip_MODRM }, 0 },
3040     { Bad_Opcode },
3041     { "vmgexit",        { Skip_MODRM }, 0 },
3042   },
3043
3044   /* PREFIX_0F01_REG_5_MOD_0 */
3045   {
3046     { Bad_Opcode },
3047     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3048   },
3049
3050   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3051   {
3052     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3053     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3054     { Bad_Opcode },
3055     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3056   },
3057
3058   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3059   {
3060     { Bad_Opcode },
3061     { Bad_Opcode },
3062     { Bad_Opcode },
3063     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3064   },
3065
3066   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3067   {
3068     { Bad_Opcode },
3069     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3070   },
3071
3072   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3073   {
3074     { Bad_Opcode },
3075     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3076   },
3077
3078   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3079   {
3080     { Bad_Opcode },
3081     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3082   },
3083
3084   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3085   {
3086     { "rdpkru", { Skip_MODRM }, 0 },
3087     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3088   },
3089
3090   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3091   {
3092     { "wrpkru", { Skip_MODRM }, 0 },
3093     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3094   },
3095
3096   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3097   {
3098     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3099     { "mcommit",        { Skip_MODRM }, 0 },
3100   },
3101
3102   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3103   {
3104     { "invlpgb",        { Skip_MODRM }, 0 },
3105     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3106     { Bad_Opcode },
3107     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3108   },
3109
3110   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3111   {
3112     { "tlbsync",        { Skip_MODRM }, 0 },
3113     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3114     { Bad_Opcode },
3115     { "pvalidate",      { Skip_MODRM }, 0 },
3116   },
3117
3118   /* PREFIX_0F09 */
3119   {
3120     { "wbinvd",   { XX }, 0 },
3121     { "wbnoinvd", { XX }, 0 },
3122   },
3123
3124   /* PREFIX_0F10 */
3125   {
3126     { "movups", { XM, EXx }, PREFIX_OPCODE },
3127     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3128     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3129     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3130   },
3131
3132   /* PREFIX_0F11 */
3133   {
3134     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3135     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3136     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3137     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3138   },
3139
3140   /* PREFIX_0F12 */
3141   {
3142     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3143     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3144     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3145     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3146   },
3147
3148   /* PREFIX_0F16 */
3149   {
3150     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3151     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3152     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3153   },
3154
3155   /* PREFIX_0F1A */
3156   {
3157     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3158     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3159     { "bndmov", { Gbnd, Ebnd }, 0 },
3160     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3161   },
3162
3163   /* PREFIX_0F1B */
3164   {
3165     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3166     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3167     { "bndmov", { EbndS, Gbnd }, 0 },
3168     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3169   },
3170
3171   /* PREFIX_0F1C */
3172   {
3173     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3174     { "nopQ",   { Ev }, PREFIX_IGNORED },
3175     { "nopQ",   { Ev }, 0 },
3176     { "nopQ",   { Ev }, PREFIX_IGNORED },
3177   },
3178
3179   /* PREFIX_0F1E */
3180   {
3181     { "nopQ",   { Ev }, 0 },
3182     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3183     { "nopQ",   { Ev }, 0 },
3184     { NULL,     { XX }, PREFIX_IGNORED },
3185   },
3186
3187   /* PREFIX_0F2A */
3188   {
3189     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3190     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3191     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3192     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3193   },
3194
3195   /* PREFIX_0F2B */
3196   {
3197     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3198     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3199     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3200     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3201   },
3202
3203   /* PREFIX_0F2C */
3204   {
3205     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3206     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3207     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3208     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3209   },
3210
3211   /* PREFIX_0F2D */
3212   {
3213     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3214     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3215     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3216     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3217   },
3218
3219   /* PREFIX_0F2E */
3220   {
3221     { "ucomiss",{ XM, EXd }, 0 },
3222     { Bad_Opcode },
3223     { "ucomisd",{ XM, EXq }, 0 },
3224   },
3225
3226   /* PREFIX_0F2F */
3227   {
3228     { "comiss", { XM, EXd }, 0 },
3229     { Bad_Opcode },
3230     { "comisd", { XM, EXq }, 0 },
3231   },
3232
3233   /* PREFIX_0F51 */
3234   {
3235     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3236     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3237     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3238     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3239   },
3240
3241   /* PREFIX_0F52 */
3242   {
3243     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3244     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3245   },
3246
3247   /* PREFIX_0F53 */
3248   {
3249     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3250     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3251   },
3252
3253   /* PREFIX_0F58 */
3254   {
3255     { "addps", { XM, EXx }, PREFIX_OPCODE },
3256     { "addss", { XM, EXd }, PREFIX_OPCODE },
3257     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3258     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3259   },
3260
3261   /* PREFIX_0F59 */
3262   {
3263     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3264     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3265     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3266     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3267   },
3268
3269   /* PREFIX_0F5A */
3270   {
3271     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3272     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3273     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3274     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3275   },
3276
3277   /* PREFIX_0F5B */
3278   {
3279     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3280     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3281     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3282   },
3283
3284   /* PREFIX_0F5C */
3285   {
3286     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3287     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3288     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3289     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3290   },
3291
3292   /* PREFIX_0F5D */
3293   {
3294     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3295     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3296     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3297     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3298   },
3299
3300   /* PREFIX_0F5E */
3301   {
3302     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3303     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3304     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3305     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3306   },
3307
3308   /* PREFIX_0F5F */
3309   {
3310     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3311     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3312     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3313     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3314   },
3315
3316   /* PREFIX_0F60 */
3317   {
3318     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3319     { Bad_Opcode },
3320     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3321   },
3322
3323   /* PREFIX_0F61 */
3324   {
3325     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3326     { Bad_Opcode },
3327     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3328   },
3329
3330   /* PREFIX_0F62 */
3331   {
3332     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3333     { Bad_Opcode },
3334     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3335   },
3336
3337   /* PREFIX_0F6F */
3338   {
3339     { "movq",   { MX, EM }, PREFIX_OPCODE },
3340     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3341     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3342   },
3343
3344   /* PREFIX_0F70 */
3345   {
3346     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3347     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3348     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3349     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3350   },
3351
3352   /* PREFIX_0F78 */
3353   {
3354     {"vmread",  { Em, Gm }, 0 },
3355     { Bad_Opcode },
3356     {"extrq",   { XS, Ib, Ib }, 0 },
3357     {"insertq", { XM, XS, Ib, Ib }, 0 },
3358   },
3359
3360   /* PREFIX_0F79 */
3361   {
3362     {"vmwrite", { Gm, Em }, 0 },
3363     { Bad_Opcode },
3364     {"extrq",   { XM, XS }, 0 },
3365     {"insertq", { XM, XS }, 0 },
3366   },
3367
3368   /* PREFIX_0F7C */
3369   {
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3373     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3374   },
3375
3376   /* PREFIX_0F7D */
3377   {
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3381     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3382   },
3383
3384   /* PREFIX_0F7E */
3385   {
3386     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3387     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3388     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3389   },
3390
3391   /* PREFIX_0F7F */
3392   {
3393     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3394     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3395     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3396   },
3397
3398   /* PREFIX_0FAE_REG_0_MOD_3 */
3399   {
3400     { Bad_Opcode },
3401     { "rdfsbase", { Ev }, 0 },
3402   },
3403
3404   /* PREFIX_0FAE_REG_1_MOD_3 */
3405   {
3406     { Bad_Opcode },
3407     { "rdgsbase", { Ev }, 0 },
3408   },
3409
3410   /* PREFIX_0FAE_REG_2_MOD_3 */
3411   {
3412     { Bad_Opcode },
3413     { "wrfsbase", { Ev }, 0 },
3414   },
3415
3416   /* PREFIX_0FAE_REG_3_MOD_3 */
3417   {
3418     { Bad_Opcode },
3419     { "wrgsbase", { Ev }, 0 },
3420   },
3421
3422   /* PREFIX_0FAE_REG_4_MOD_0 */
3423   {
3424     { "xsave",  { FXSAVE }, 0 },
3425     { "ptwrite{%LQ|}", { Edq }, 0 },
3426   },
3427
3428   /* PREFIX_0FAE_REG_4_MOD_3 */
3429   {
3430     { Bad_Opcode },
3431     { "ptwrite{%LQ|}", { Edq }, 0 },
3432   },
3433
3434   /* PREFIX_0FAE_REG_5_MOD_3 */
3435   {
3436     { "lfence",         { Skip_MODRM }, 0 },
3437     { "incsspK",        { Edq }, PREFIX_OPCODE },
3438   },
3439
3440   /* PREFIX_0FAE_REG_6_MOD_0 */
3441   {
3442     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3443     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3444     { "clwb",   { Mb }, PREFIX_OPCODE },
3445   },
3446
3447   /* PREFIX_0FAE_REG_6_MOD_3 */
3448   {
3449     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3450     { "umonitor",       { Eva }, PREFIX_OPCODE },
3451     { "tpause", { Edq }, PREFIX_OPCODE },
3452     { "umwait", { Edq }, PREFIX_OPCODE },
3453   },
3454
3455   /* PREFIX_0FAE_REG_7_MOD_0 */
3456   {
3457     { "clflush",        { Mb }, 0 },
3458     { Bad_Opcode },
3459     { "clflushopt",     { Mb }, 0 },
3460   },
3461
3462   /* PREFIX_0FB8 */
3463   {
3464     { Bad_Opcode },
3465     { "popcntS", { Gv, Ev }, 0 },
3466   },
3467
3468   /* PREFIX_0FBC */
3469   {
3470     { "bsfS",   { Gv, Ev }, 0 },
3471     { "tzcntS", { Gv, Ev }, 0 },
3472     { "bsfS",   { Gv, Ev }, 0 },
3473   },
3474
3475   /* PREFIX_0FBD */
3476   {
3477     { "bsrS",   { Gv, Ev }, 0 },
3478     { "lzcntS", { Gv, Ev }, 0 },
3479     { "bsrS",   { Gv, Ev }, 0 },
3480   },
3481
3482   /* PREFIX_0FC2 */
3483   {
3484     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3485     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3486     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3487     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3488   },
3489
3490   /* PREFIX_0FC7_REG_6_MOD_0 */
3491   {
3492     { "vmptrld",{ Mq }, 0 },
3493     { "vmxon",  { Mq }, 0 },
3494     { "vmclear",{ Mq }, 0 },
3495   },
3496
3497   /* PREFIX_0FC7_REG_6_MOD_3 */
3498   {
3499     { "rdrand", { Ev }, 0 },
3500     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3501     { "rdrand", { Ev }, 0 }
3502   },
3503
3504   /* PREFIX_0FC7_REG_7_MOD_3 */
3505   {
3506     { "rdseed", { Ev }, 0 },
3507     { "rdpid",  { Em }, 0 },
3508     { "rdseed", { Ev }, 0 },
3509   },
3510
3511   /* PREFIX_0FD0 */
3512   {
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { "addsubpd", { XM, EXx }, 0 },
3516     { "addsubps", { XM, EXx }, 0 },
3517   },
3518
3519   /* PREFIX_0FD6 */
3520   {
3521     { Bad_Opcode },
3522     { "movq2dq",{ XM, MS }, 0 },
3523     { "movq",   { EXqS, XM }, 0 },
3524     { "movdq2q",{ MX, XS }, 0 },
3525   },
3526
3527   /* PREFIX_0FE6 */
3528   {
3529     { Bad_Opcode },
3530     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3531     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3532     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3533   },
3534
3535   /* PREFIX_0FE7 */
3536   {
3537     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3538     { Bad_Opcode },
3539     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3540   },
3541
3542   /* PREFIX_0FF0 */
3543   {
3544     { Bad_Opcode },
3545     { Bad_Opcode },
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3548   },
3549
3550   /* PREFIX_0FF7 */
3551   {
3552     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3553     { Bad_Opcode },
3554     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3555   },
3556
3557   /* PREFIX_0F38D8 */
3558   {
3559     { Bad_Opcode },
3560     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3561   },
3562
3563   /* PREFIX_0F38DC */
3564   {
3565     { Bad_Opcode },
3566     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3567     { "aesenc", { XM, EXx }, 0 },
3568   },
3569
3570   /* PREFIX_0F38DD */
3571   {
3572     { Bad_Opcode },
3573     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3574     { "aesenclast", { XM, EXx }, 0 },
3575   },
3576
3577   /* PREFIX_0F38DE */
3578   {
3579     { Bad_Opcode },
3580     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3581     { "aesdec", { XM, EXx }, 0 },
3582   },
3583
3584   /* PREFIX_0F38DF */
3585   {
3586     { Bad_Opcode },
3587     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3588     { "aesdeclast", { XM, EXx }, 0 },
3589   },
3590
3591   /* PREFIX_0F38F0 */
3592   {
3593     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3594     { Bad_Opcode },
3595     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3596     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3597   },
3598
3599   /* PREFIX_0F38F1 */
3600   {
3601     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3602     { Bad_Opcode },
3603     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3604     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3605   },
3606
3607   /* PREFIX_0F38F6 */
3608   {
3609     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3610     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3611     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3612     { Bad_Opcode },
3613   },
3614
3615   /* PREFIX_0F38F8 */
3616   {
3617     { Bad_Opcode },
3618     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3619     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3620     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3621   },
3622   /* PREFIX_0F38FA */
3623   {
3624     { Bad_Opcode },
3625     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3626   },
3627
3628   /* PREFIX_0F38FB */
3629   {
3630     { Bad_Opcode },
3631     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3632   },
3633
3634   /* PREFIX_0F3A0F */
3635   {
3636     { Bad_Opcode },
3637     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3638   },
3639
3640   /* PREFIX_VEX_0F10 */
3641   {
3642     { "vmovupX",        { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3643     { "vmovs%XS",       { XMScalar, VexScalarR, EXd }, 0 },
3644     { "vmovupX",        { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3645     { "vmovs%XD",       { XMScalar, VexScalarR, EXq }, 0 },
3646   },
3647
3648   /* PREFIX_VEX_0F11 */
3649   {
3650     { "vmovupX",        { EXxS, XM }, PREFIX_OPCODE },
3651     { "vmovs%XS",       { EXdS, VexScalarR, XMScalar }, 0 },
3652     { "vmovupX",        { EXxS, XM }, PREFIX_OPCODE },
3653     { "vmovs%XD",       { EXqS, VexScalarR, XMScalar }, 0 },
3654   },
3655
3656   /* PREFIX_VEX_0F12 */
3657   {
3658     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3659     { "vmov%XSldup",    { XM, EXEvexXNoBcst }, 0 },
3660     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3661     { "vmov%XDdup",     { XM, EXymmq }, 0 },
3662   },
3663
3664   /* PREFIX_VEX_0F16 */
3665   {
3666     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3667     { "vmov%XShdup",    { XM, EXEvexXNoBcst }, 0 },
3668     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3669   },
3670
3671   /* PREFIX_VEX_0F2A */
3672   {
3673     { Bad_Opcode },
3674     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3675     { Bad_Opcode },
3676     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3677   },
3678
3679   /* PREFIX_VEX_0F2C */
3680   {
3681     { Bad_Opcode },
3682     { "vcvttss2si",     { Gdq, EXd, EXxEVexS }, 0 },
3683     { Bad_Opcode },
3684     { "vcvttsd2si",     { Gdq, EXq, EXxEVexS }, 0 },
3685   },
3686
3687   /* PREFIX_VEX_0F2D */
3688   {
3689     { Bad_Opcode },
3690     { "vcvtss2si",      { Gdq, EXd, EXxEVexR }, 0 },
3691     { Bad_Opcode },
3692     { "vcvtsd2si",      { Gdq, EXq, EXxEVexR }, 0 },
3693   },
3694
3695   /* PREFIX_VEX_0F2E */
3696   {
3697     { "vucomisX",       { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3698     { Bad_Opcode },
3699     { "vucomisX",       { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3700   },
3701
3702   /* PREFIX_VEX_0F2F */
3703   {
3704     { "vcomisX",        { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3705     { Bad_Opcode },
3706     { "vcomisX",        { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3707   },
3708
3709   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3710   {
3711     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3712     { Bad_Opcode },
3713     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3714   },
3715
3716   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3717   {
3718     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3719     { Bad_Opcode },
3720     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3721   },
3722
3723   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3724   {
3725     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3726     { Bad_Opcode },
3727     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3728   },
3729
3730   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3731   {
3732     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3733     { Bad_Opcode },
3734     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3735   },
3736
3737   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3738   {
3739     { "knotw",          { MaskG, MaskE }, 0 },
3740     { Bad_Opcode },
3741     { "knotb",          { MaskG, MaskE }, 0 },
3742   },
3743
3744   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3745   {
3746     { "knotq",          { MaskG, MaskE }, 0 },
3747     { Bad_Opcode },
3748     { "knotd",          { MaskG, MaskE }, 0 },
3749   },
3750
3751   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3752   {
3753     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3754     { Bad_Opcode },
3755     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3756   },
3757
3758   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3759   {
3760     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3761     { Bad_Opcode },
3762     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3763   },
3764
3765   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3766   {
3767     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3768     { Bad_Opcode },
3769     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3770   },
3771
3772   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3773   {
3774     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3775     { Bad_Opcode },
3776     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3777   },
3778
3779   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3780   {
3781     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3782     { Bad_Opcode },
3783     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3784   },
3785
3786   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3787   {
3788     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3789     { Bad_Opcode },
3790     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3791   },
3792
3793   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3794   {
3795     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3796     { Bad_Opcode },
3797     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3798   },
3799
3800   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3801   {
3802     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3803     { Bad_Opcode },
3804     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3805   },
3806
3807   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3808   {
3809     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3810     { Bad_Opcode },
3811     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3812   },
3813
3814   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3815   {
3816     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3817   },
3818
3819   /* PREFIX_VEX_0F51 */
3820   {
3821     { "vsqrtpX",        { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3822     { "vsqrts%XS",      { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3823     { "vsqrtpX",        { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3824     { "vsqrts%XD",      { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3825   },
3826
3827   /* PREFIX_VEX_0F52 */
3828   {
3829     { "vrsqrtps",       { XM, EXx }, 0 },
3830     { "vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3831   },
3832
3833   /* PREFIX_VEX_0F53 */
3834   {
3835     { "vrcpps",         { XM, EXx }, 0 },
3836     { "vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3837   },
3838
3839   /* PREFIX_VEX_0F58 */
3840   {
3841     { "vaddpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3842     { "vadds%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3843     { "vaddpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3844     { "vadds%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3845   },
3846
3847   /* PREFIX_VEX_0F59 */
3848   {
3849     { "vmulpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3850     { "vmuls%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3851     { "vmulpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3852     { "vmuls%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3853   },
3854
3855   /* PREFIX_VEX_0F5A */
3856   {
3857     { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3858     { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3859     { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3860     { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3861   },
3862
3863   /* PREFIX_VEX_0F5B */
3864   {
3865     { "vcvtdq2ps",      { XM, EXx }, 0 },
3866     { "vcvttps2dq",     { XM, EXx }, 0 },
3867     { "vcvtps2dq",      { XM, EXx }, 0 },
3868   },
3869
3870   /* PREFIX_VEX_0F5C */
3871   {
3872     { "vsubpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3873     { "vsubs%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3874     { "vsubpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3875     { "vsubs%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3876   },
3877
3878   /* PREFIX_VEX_0F5D */
3879   {
3880     { "vminpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3881     { "vmins%XS",       { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3882     { "vminpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3883     { "vmins%XD",       { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3884   },
3885
3886   /* PREFIX_VEX_0F5E */
3887   {
3888     { "vdivpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3889     { "vdivs%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3890     { "vdivpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3891     { "vdivs%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3892   },
3893
3894   /* PREFIX_VEX_0F5F */
3895   {
3896     { "vmaxpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3897     { "vmaxs%XS",       { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3898     { "vmaxpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3899     { "vmaxs%XD",       { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3900   },
3901
3902   /* PREFIX_VEX_0F6F */
3903   {
3904     { Bad_Opcode },
3905     { "vmovdqu",        { XM, EXx }, 0 },
3906     { "vmovdqa",        { XM, EXx }, 0 },
3907   },
3908
3909   /* PREFIX_VEX_0F70 */
3910   {
3911     { Bad_Opcode },
3912     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3913     { "vpshufd",        { XM, EXx, Ib }, 0 },
3914     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3915   },
3916
3917   /* PREFIX_VEX_0F7C */
3918   {
3919     { Bad_Opcode },
3920     { Bad_Opcode },
3921     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3922     { "vhaddps",        { XM, Vex, EXx }, 0 },
3923   },
3924
3925   /* PREFIX_VEX_0F7D */
3926   {
3927     { Bad_Opcode },
3928     { Bad_Opcode },
3929     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3930     { "vhsubps",        { XM, Vex, EXx }, 0 },
3931   },
3932
3933   /* PREFIX_VEX_0F7E */
3934   {
3935     { Bad_Opcode },
3936     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3937     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3938   },
3939
3940   /* PREFIX_VEX_0F7F */
3941   {
3942     { Bad_Opcode },
3943     { "vmovdqu",        { EXxS, XM }, 0 },
3944     { "vmovdqa",        { EXxS, XM }, 0 },
3945   },
3946
3947   /* PREFIX_VEX_0F90_L_0_W_0 */
3948   {
3949     { "kmovw",          { MaskG, MaskE }, 0 },
3950     { Bad_Opcode },
3951     { "kmovb",          { MaskG, MaskBDE }, 0 },
3952   },
3953
3954   /* PREFIX_VEX_0F90_L_0_W_1 */
3955   {
3956     { "kmovq",          { MaskG, MaskE }, 0 },
3957     { Bad_Opcode },
3958     { "kmovd",          { MaskG, MaskBDE }, 0 },
3959   },
3960
3961   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3962   {
3963     { "kmovw",          { Ew, MaskG }, 0 },
3964     { Bad_Opcode },
3965     { "kmovb",          { Eb, MaskG }, 0 },
3966   },
3967
3968   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3969   {
3970     { "kmovq",          { Eq, MaskG }, 0 },
3971     { Bad_Opcode },
3972     { "kmovd",          { Ed, MaskG }, 0 },
3973   },
3974
3975   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3976   {
3977     { "kmovw",          { MaskG, Edq }, 0 },
3978     { Bad_Opcode },
3979     { "kmovb",          { MaskG, Edq }, 0 },
3980     { "kmovd",          { MaskG, Edq }, 0 },
3981   },
3982
3983   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3984   {
3985     { Bad_Opcode },
3986     { Bad_Opcode },
3987     { Bad_Opcode },
3988     { "kmovK",          { MaskG, Edq }, 0 },
3989   },
3990
3991   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3992   {
3993     { "kmovw",          { Gdq, MaskE }, 0 },
3994     { Bad_Opcode },
3995     { "kmovb",          { Gdq, MaskE }, 0 },
3996     { "kmovd",          { Gdq, MaskE }, 0 },
3997   },
3998
3999   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
4000   {
4001     { Bad_Opcode },
4002     { Bad_Opcode },
4003     { Bad_Opcode },
4004     { "kmovK",          { Gdq, MaskE }, 0 },
4005   },
4006
4007   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
4008   {
4009     { "kortestw", { MaskG, MaskE }, 0 },
4010     { Bad_Opcode },
4011     { "kortestb", { MaskG, MaskE }, 0 },
4012   },
4013
4014   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4015   {
4016     { "kortestq", { MaskG, MaskE }, 0 },
4017     { Bad_Opcode },
4018     { "kortestd", { MaskG, MaskE }, 0 },
4019   },
4020
4021   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4022   {
4023     { "ktestw", { MaskG, MaskE }, 0 },
4024     { Bad_Opcode },
4025     { "ktestb", { MaskG, MaskE }, 0 },
4026   },
4027
4028   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4029   {
4030     { "ktestq", { MaskG, MaskE }, 0 },
4031     { Bad_Opcode },
4032     { "ktestd", { MaskG, MaskE }, 0 },
4033   },
4034
4035   /* PREFIX_VEX_0FC2 */
4036   {
4037     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
4038     { "vcmpss",         { XMScalar, VexScalar, EXd, CMP }, 0 },
4039     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
4040     { "vcmpsd",         { XMScalar, VexScalar, EXq, CMP }, 0 },
4041   },
4042
4043   /* PREFIX_VEX_0FD0 */
4044   {
4045     { Bad_Opcode },
4046     { Bad_Opcode },
4047     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
4048     { "vaddsubps",      { XM, Vex, EXx }, 0 },
4049   },
4050
4051   /* PREFIX_VEX_0FE6 */
4052   {
4053     { Bad_Opcode },
4054     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
4055     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
4056     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
4057   },
4058
4059   /* PREFIX_VEX_0FF0 */
4060   {
4061     { Bad_Opcode },
4062     { Bad_Opcode },
4063     { Bad_Opcode },
4064     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4065   },
4066
4067   /* PREFIX_VEX_0F3849_X86_64 */
4068   {
4069     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4070     { Bad_Opcode },
4071     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4072     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4073   },
4074
4075   /* PREFIX_VEX_0F384B_X86_64 */
4076   {
4077     { Bad_Opcode },
4078     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4079     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4080     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4081   },
4082
4083   /* PREFIX_VEX_0F385C_X86_64 */
4084   {
4085     { Bad_Opcode },
4086     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4087     { Bad_Opcode },
4088   },
4089
4090   /* PREFIX_VEX_0F385E_X86_64 */
4091   {
4092     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4093     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4094     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4095     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4096   },
4097
4098   /* PREFIX_VEX_0F38F5_L_0 */
4099   {
4100     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4101     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4102     { Bad_Opcode },
4103     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4104   },
4105
4106   /* PREFIX_VEX_0F38F6_L_0 */
4107   {
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4112   },
4113
4114   /* PREFIX_VEX_0F38F7_L_0 */
4115   {
4116     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4117     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4118     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4119     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4120   },
4121
4122   /* PREFIX_VEX_0F3AF0_L_0 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4128   },
4129
4130 #include "i386-dis-evex-prefix.h"
4131 };
4132
4133 static const struct dis386 x86_64_table[][2] = {
4134   /* X86_64_06 */
4135   {
4136     { "pushP", { es }, 0 },
4137   },
4138
4139   /* X86_64_07 */
4140   {
4141     { "popP", { es }, 0 },
4142   },
4143
4144   /* X86_64_0E */
4145   {
4146     { "pushP", { cs }, 0 },
4147   },
4148
4149   /* X86_64_16 */
4150   {
4151     { "pushP", { ss }, 0 },
4152   },
4153
4154   /* X86_64_17 */
4155   {
4156     { "popP", { ss }, 0 },
4157   },
4158
4159   /* X86_64_1E */
4160   {
4161     { "pushP", { ds }, 0 },
4162   },
4163
4164   /* X86_64_1F */
4165   {
4166     { "popP", { ds }, 0 },
4167   },
4168
4169   /* X86_64_27 */
4170   {
4171     { "daa", { XX }, 0 },
4172   },
4173
4174   /* X86_64_2F */
4175   {
4176     { "das", { XX }, 0 },
4177   },
4178
4179   /* X86_64_37 */
4180   {
4181     { "aaa", { XX }, 0 },
4182   },
4183
4184   /* X86_64_3F */
4185   {
4186     { "aas", { XX }, 0 },
4187   },
4188
4189   /* X86_64_60 */
4190   {
4191     { "pushaP", { XX }, 0 },
4192   },
4193
4194   /* X86_64_61 */
4195   {
4196     { "popaP", { XX }, 0 },
4197   },
4198
4199   /* X86_64_62 */
4200   {
4201     { MOD_TABLE (MOD_62_32BIT) },
4202     { EVEX_TABLE (EVEX_0F) },
4203   },
4204
4205   /* X86_64_63 */
4206   {
4207     { "arpl", { Ew, Gw }, 0 },
4208     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4209   },
4210
4211   /* X86_64_6D */
4212   {
4213     { "ins{R|}", { Yzr, indirDX }, 0 },
4214     { "ins{G|}", { Yzr, indirDX }, 0 },
4215   },
4216
4217   /* X86_64_6F */
4218   {
4219     { "outs{R|}", { indirDXr, Xz }, 0 },
4220     { "outs{G|}", { indirDXr, Xz }, 0 },
4221   },
4222
4223   /* X86_64_82 */
4224   {
4225     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4226     { REG_TABLE (REG_80) },
4227   },
4228
4229   /* X86_64_9A */
4230   {
4231     { "{l|}call{P|}", { Ap }, 0 },
4232   },
4233
4234   /* X86_64_C2 */
4235   {
4236     { "retP",           { Iw, BND }, 0 },
4237     { "ret@",           { Iw, BND }, 0 },
4238   },
4239
4240   /* X86_64_C3 */
4241   {
4242     { "retP",           { BND }, 0 },
4243     { "ret@",           { BND }, 0 },
4244   },
4245
4246   /* X86_64_C4 */
4247   {
4248     { MOD_TABLE (MOD_C4_32BIT) },
4249     { VEX_C4_TABLE (VEX_0F) },
4250   },
4251
4252   /* X86_64_C5 */
4253   {
4254     { MOD_TABLE (MOD_C5_32BIT) },
4255     { VEX_C5_TABLE (VEX_0F) },
4256   },
4257
4258   /* X86_64_CE */
4259   {
4260     { "into", { XX }, 0 },
4261   },
4262
4263   /* X86_64_D4 */
4264   {
4265     { "aam", { Ib }, 0 },
4266   },
4267
4268   /* X86_64_D5 */
4269   {
4270     { "aad", { Ib }, 0 },
4271   },
4272
4273   /* X86_64_E8 */
4274   {
4275     { "callP",          { Jv, BND }, 0 },
4276     { "call@",          { Jv, BND }, 0 }
4277   },
4278
4279   /* X86_64_E9 */
4280   {
4281     { "jmpP",           { Jv, BND }, 0 },
4282     { "jmp@",           { Jv, BND }, 0 }
4283   },
4284
4285   /* X86_64_EA */
4286   {
4287     { "{l|}jmp{P|}", { Ap }, 0 },
4288   },
4289
4290   /* X86_64_0F01_REG_0 */
4291   {
4292     { "sgdt{Q|Q}", { M }, 0 },
4293     { "sgdt", { M }, 0 },
4294   },
4295
4296   /* X86_64_0F01_REG_1 */
4297   {
4298     { "sidt{Q|Q}", { M }, 0 },
4299     { "sidt", { M }, 0 },
4300   },
4301
4302   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4303   {
4304     { Bad_Opcode },
4305     { "seamret",        { Skip_MODRM }, 0 },
4306   },
4307
4308   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4309   {
4310     { Bad_Opcode },
4311     { "seamops",        { Skip_MODRM }, 0 },
4312   },
4313
4314   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4315   {
4316     { Bad_Opcode },
4317     { "seamcall",       { Skip_MODRM }, 0 },
4318   },
4319
4320   /* X86_64_0F01_REG_2 */
4321   {
4322     { "lgdt{Q|Q}", { M }, 0 },
4323     { "lgdt", { M }, 0 },
4324   },
4325
4326   /* X86_64_0F01_REG_3 */
4327   {
4328     { "lidt{Q|Q}", { M }, 0 },
4329     { "lidt", { M }, 0 },
4330   },
4331
4332   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4333   {
4334     { Bad_Opcode },
4335     { "uiret",  { Skip_MODRM }, 0 },
4336   },
4337
4338   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4339   {
4340     { Bad_Opcode },
4341     { "testui", { Skip_MODRM }, 0 },
4342   },
4343
4344   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4345   {
4346     { Bad_Opcode },
4347     { "clui",   { Skip_MODRM }, 0 },
4348   },
4349
4350   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4351   {
4352     { Bad_Opcode },
4353     { "stui",   { Skip_MODRM }, 0 },
4354   },
4355
4356   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4357   {
4358     { Bad_Opcode },
4359     { "rmpadjust",      { Skip_MODRM }, 0 },
4360   },
4361
4362   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4363   {
4364     { Bad_Opcode },
4365     { "rmpupdate",      { Skip_MODRM }, 0 },
4366   },
4367
4368   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4369   {
4370     { Bad_Opcode },
4371     { "psmash", { Skip_MODRM }, 0 },
4372   },
4373
4374   {
4375     /* X86_64_0F24 */
4376     { "movZ",           { Em, Td }, 0 },
4377   },
4378
4379   {
4380     /* X86_64_0F26 */
4381     { "movZ",           { Td, Em }, 0 },
4382   },
4383
4384   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4385   {
4386     { Bad_Opcode },
4387     { "senduipi",       { Eq }, 0 },
4388   },
4389
4390   /* X86_64_VEX_0F3849 */
4391   {
4392     { Bad_Opcode },
4393     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4394   },
4395
4396   /* X86_64_VEX_0F384B */
4397   {
4398     { Bad_Opcode },
4399     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4400   },
4401
4402   /* X86_64_VEX_0F385C */
4403   {
4404     { Bad_Opcode },
4405     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4406   },
4407
4408   /* X86_64_VEX_0F385E */
4409   {
4410     { Bad_Opcode },
4411     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4412   },
4413 };
4414
4415 static const struct dis386 three_byte_table[][256] = {
4416
4417   /* THREE_BYTE_0F38 */
4418   {
4419     /* 00 */
4420     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4421     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4422     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4423     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4424     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4425     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4426     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4427     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4428     /* 08 */
4429     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4430     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4431     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4432     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     /* 10 */
4438     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4443     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4444     { Bad_Opcode },
4445     { "ptest",  { XM, EXx }, PREFIX_DATA },
4446     /* 18 */
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4452     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4453     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4454     { Bad_Opcode },
4455     /* 20 */
4456     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4457     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4458     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4459     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4460     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4461     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     /* 28 */
4465     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4466     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4467     { MOD_TABLE (MOD_0F382A) },
4468     { "packusdw", { XM, EXx }, PREFIX_DATA },
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     /* 30 */
4474     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4475     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4476     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4477     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4478     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4479     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4480     { Bad_Opcode },
4481     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4482     /* 38 */
4483     { "pminsb", { XM, EXx }, PREFIX_DATA },
4484     { "pminsd", { XM, EXx }, PREFIX_DATA },
4485     { "pminuw", { XM, EXx }, PREFIX_DATA },
4486     { "pminud", { XM, EXx }, PREFIX_DATA },
4487     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4488     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4489     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4490     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4491     /* 40 */
4492     { "pmulld", { XM, EXx }, PREFIX_DATA },
4493     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     /* 48 */
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     /* 50 */
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     /* 58 */
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     /* 60 */
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     /* 68 */
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     /* 70 */
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     /* 78 */
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     /* 80 */
4564     { "invept", { Gm, Mo }, PREFIX_DATA },
4565     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4566     { "invpcid", { Gm, M }, PREFIX_DATA },
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     /* 88 */
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     /* 90 */
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     /* 98 */
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     /* a0 */
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     /* a8 */
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     /* b0 */
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     /* b8 */
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     /* c0 */
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     /* c8 */
4645     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4646     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4647     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4648     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4649     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4650     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4651     { Bad_Opcode },
4652     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4653     /* d0 */
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     /* d8 */
4663     { PREFIX_TABLE (PREFIX_0F38D8) },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { "aesimc", { XM, EXx }, PREFIX_DATA },
4667     { PREFIX_TABLE (PREFIX_0F38DC) },
4668     { PREFIX_TABLE (PREFIX_0F38DD) },
4669     { PREFIX_TABLE (PREFIX_0F38DE) },
4670     { PREFIX_TABLE (PREFIX_0F38DF) },
4671     /* e0 */
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     /* e8 */
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     /* f0 */
4690     { PREFIX_TABLE (PREFIX_0F38F0) },
4691     { PREFIX_TABLE (PREFIX_0F38F1) },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { MOD_TABLE (MOD_0F38F5) },
4696     { PREFIX_TABLE (PREFIX_0F38F6) },
4697     { Bad_Opcode },
4698     /* f8 */
4699     { PREFIX_TABLE (PREFIX_0F38F8) },
4700     { MOD_TABLE (MOD_0F38F9) },
4701     { PREFIX_TABLE (PREFIX_0F38FA) },
4702     { PREFIX_TABLE (PREFIX_0F38FB) },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707   },
4708   /* THREE_BYTE_0F3A */
4709   {
4710     /* 00 */
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     /* 08 */
4720     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4721     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4722     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4723     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4724     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4725     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4726     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4727     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4728     /* 10 */
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4734     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4735     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4736     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4737     /* 18 */
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     /* 20 */
4747     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4748     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4749     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     /* 28 */
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     /* 30 */
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     /* 38 */
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     /* 40 */
4783     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4784     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4785     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4786     { Bad_Opcode },
4787     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     /* 48 */
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     /* 50 */
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     /* 58 */
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     /* 60 */
4819     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4820     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4821     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4822     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     /* 68 */
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     /* 70 */
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     /* 78 */
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     /* 80 */
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     /* 88 */
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     /* 90 */
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     /* 98 */
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     /* a0 */
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     /* a8 */
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     /* b0 */
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     /* b8 */
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     /* c0 */
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     /* c8 */
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4941     { Bad_Opcode },
4942     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4943     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4944     /* d0 */
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     /* d8 */
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4962     /* e0 */
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     /* e8 */
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     /* f0 */
4981     { PREFIX_TABLE (PREFIX_0F3A0F) },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     /* f8 */
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998   },
4999 };
5000
5001 static const struct dis386 xop_table[][256] = {
5002   /* XOP_08 */
5003   {
5004     /* 00 */
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     /* 08 */
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     /* 10 */
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     /* 18 */
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     /* 20 */
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     /* 28 */
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     /* 30 */
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     /* 38 */
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     /* 40 */
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     /* 48 */
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     /* 50 */
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     /* 58 */
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     /* 60 */
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     /* 68 */
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     /* 70 */
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     /* 78 */
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     /* 80 */
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5155     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5156     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5157     /* 88 */
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5165     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5166     /* 90 */
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5173     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5174     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5175     /* 98 */
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5183     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5184     /* a0 */
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5188     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5192     { Bad_Opcode },
5193     /* a8 */
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     /* b0 */
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5210     { Bad_Opcode },
5211     /* b8 */
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     /* c0 */
5221     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5222     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5223     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5224     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     /* c8 */
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5235     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5236     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5237     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5238     /* d0 */
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     /* d8 */
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     /* e0 */
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     /* e8 */
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5271     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5272     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5273     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5274     /* f0 */
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     /* f8 */
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292   },
5293   /* XOP_09 */
5294   {
5295     /* 00 */
5296     { Bad_Opcode },
5297     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5298     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     /* 08 */
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     /* 10 */
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { MOD_TABLE (MOD_XOP_09_12) },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     /* 18 */
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     /* 20 */
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     /* 28 */
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     /* 30 */
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     /* 38 */
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     /* 40 */
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     /* 48 */
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     /* 50 */
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     /* 58 */
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     /* 60 */
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     /* 68 */
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     /* 70 */
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     /* 78 */
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     /* 80 */
5440     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5441     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5442     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5443     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     /* 88 */
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     /* 90 */
5458     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5459     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5460     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5461     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5462     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5463     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5464     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5465     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5466     /* 98 */
5467     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5468     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5469     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5470     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     /* a0 */
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     /* a8 */
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     /* b0 */
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     /* b8 */
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     /* c0 */
5512     { Bad_Opcode },
5513     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5514     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5515     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5519     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5520     /* c8 */
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     /* d0 */
5530     { Bad_Opcode },
5531     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5532     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5533     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5537     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5538     /* d8 */
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     /* e0 */
5548     { Bad_Opcode },
5549     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5550     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5551     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     /* e8 */
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     /* f0 */
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     /* f8 */
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583   },
5584   /* XOP_0A */
5585   {
5586     /* 00 */
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     /* 08 */
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     /* 10 */
5605     { "bextrS", { Gdq, Edq, Id }, 0 },
5606     { Bad_Opcode },
5607     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     /* 18 */
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     /* 20 */
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     /* 28 */
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     /* 30 */
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     /* 38 */
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     /* 40 */
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     /* 48 */
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     /* 50 */
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     /* 58 */
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     /* 60 */
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     /* 68 */
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     /* 70 */
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     /* 78 */
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     /* 80 */
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     /* 88 */
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     /* 90 */
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     /* 98 */
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     /* a0 */
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     /* a8 */
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     /* b0 */
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     /* b8 */
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     /* c0 */
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     /* c8 */
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     /* d0 */
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     /* d8 */
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     /* e0 */
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     /* e8 */
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     /* f0 */
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     /* f8 */
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874   },
5875 };
5876
5877 static const struct dis386 vex_table[][256] = {
5878   /* VEX_0F */
5879   {
5880     /* 00 */
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     /* 08 */
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     /* 10 */
5899     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5900     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5901     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5902     { MOD_TABLE (MOD_VEX_0F13) },
5903     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5904     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5905     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5906     { MOD_TABLE (MOD_VEX_0F17) },
5907     /* 18 */
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     /* 20 */
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     /* 28 */
5926     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5927     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5928     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5929     { MOD_TABLE (MOD_VEX_0F2B) },
5930     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5931     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5932     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5933     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5934     /* 30 */
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     /* 38 */
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     /* 40 */
5953     { Bad_Opcode },
5954     { VEX_LEN_TABLE (VEX_LEN_0F41) },
5955     { VEX_LEN_TABLE (VEX_LEN_0F42) },
5956     { Bad_Opcode },
5957     { VEX_LEN_TABLE (VEX_LEN_0F44) },
5958     { VEX_LEN_TABLE (VEX_LEN_0F45) },
5959     { VEX_LEN_TABLE (VEX_LEN_0F46) },
5960     { VEX_LEN_TABLE (VEX_LEN_0F47) },
5961     /* 48 */
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5965     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     /* 50 */
5971     { MOD_TABLE (MOD_VEX_0F50) },
5972     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5973     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5974     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5975     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5976     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5977     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5978     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5979     /* 58 */
5980     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5981     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5982     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5983     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5984     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5985     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5986     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5987     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5988     /* 60 */
5989     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5990     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5991     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5992     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5993     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5994     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5995     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5996     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5997     /* 68 */
5998     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5999     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
6000     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
6001     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
6002     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6003     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6004     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6005     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6006     /* 70 */
6007     { PREFIX_TABLE (PREFIX_VEX_0F70) },
6008     { MOD_TABLE (MOD_VEX_0F71) },
6009     { MOD_TABLE (MOD_VEX_0F72) },
6010     { MOD_TABLE (MOD_VEX_0F73) },
6011     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
6012     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
6013     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
6014     { VEX_LEN_TABLE (VEX_LEN_0F77) },
6015     /* 78 */
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6021     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6022     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6023     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6024     /* 80 */
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     /* 88 */
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     /* 90 */
6043     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6044     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6045     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6046     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     /* 98 */
6052     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6053     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     /* a0 */
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     /* a8 */
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { REG_TABLE (REG_VEX_0FAE) },
6077     { Bad_Opcode },
6078     /* b0 */
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     /* b8 */
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     /* c0 */
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6100     { Bad_Opcode },
6101     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6102     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6103     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6104     { Bad_Opcode },
6105     /* c8 */
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     /* d0 */
6115     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6116     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6117     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6118     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6119     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6120     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6121     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6122     { MOD_TABLE (MOD_VEX_0FD7) },
6123     /* d8 */
6124     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6125     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6126     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6127     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6128     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6129     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6130     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6131     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6132     /* e0 */
6133     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6134     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6135     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6136     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6137     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6138     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6139     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6140     { MOD_TABLE (MOD_VEX_0FE7) },
6141     /* e8 */
6142     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6143     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6144     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6145     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6146     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6147     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6148     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6149     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6150     /* f0 */
6151     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6152     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6153     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6154     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6155     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6156     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6157     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6158     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6159     /* f8 */
6160     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6161     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6162     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6163     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6164     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6165     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6166     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6167     { Bad_Opcode },
6168   },
6169   /* VEX_0F38 */
6170   {
6171     /* 00 */
6172     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6173     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6174     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6175     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6176     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6177     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6178     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6179     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6180     /* 08 */
6181     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6182     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6183     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6184     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6185     { VEX_W_TABLE (VEX_W_0F380C) },
6186     { VEX_W_TABLE (VEX_W_0F380D) },
6187     { VEX_W_TABLE (VEX_W_0F380E) },
6188     { VEX_W_TABLE (VEX_W_0F380F) },
6189     /* 10 */
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { VEX_W_TABLE (VEX_W_0F3813) },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6197     { "vptest",         { XM, EXx }, PREFIX_DATA },
6198     /* 18 */
6199     { VEX_W_TABLE (VEX_W_0F3818) },
6200     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6201     { MOD_TABLE (MOD_VEX_0F381A) },
6202     { Bad_Opcode },
6203     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6204     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6205     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6206     { Bad_Opcode },
6207     /* 20 */
6208     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6209     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6210     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6211     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6212     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6213     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     /* 28 */
6217     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6218     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6219     { MOD_TABLE (MOD_VEX_0F382A) },
6220     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6221     { MOD_TABLE (MOD_VEX_0F382C) },
6222     { MOD_TABLE (MOD_VEX_0F382D) },
6223     { MOD_TABLE (MOD_VEX_0F382E) },
6224     { MOD_TABLE (MOD_VEX_0F382F) },
6225     /* 30 */
6226     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6227     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6228     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6229     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6230     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6231     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6232     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6233     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6234     /* 38 */
6235     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6236     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6237     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6238     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6239     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6240     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6241     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6242     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6243     /* 40 */
6244     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6245     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6250     { VEX_W_TABLE (VEX_W_0F3846) },
6251     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6252     /* 48 */
6253     { Bad_Opcode },
6254     { X86_64_TABLE (X86_64_VEX_0F3849) },
6255     { Bad_Opcode },
6256     { X86_64_TABLE (X86_64_VEX_0F384B) },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     /* 50 */
6262     { VEX_W_TABLE (VEX_W_0F3850) },
6263     { VEX_W_TABLE (VEX_W_0F3851) },
6264     { VEX_W_TABLE (VEX_W_0F3852) },
6265     { VEX_W_TABLE (VEX_W_0F3853) },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     /* 58 */
6271     { VEX_W_TABLE (VEX_W_0F3858) },
6272     { VEX_W_TABLE (VEX_W_0F3859) },
6273     { MOD_TABLE (MOD_VEX_0F385A) },
6274     { Bad_Opcode },
6275     { X86_64_TABLE (X86_64_VEX_0F385C) },
6276     { Bad_Opcode },
6277     { X86_64_TABLE (X86_64_VEX_0F385E) },
6278     { Bad_Opcode },
6279     /* 60 */
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     /* 68 */
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     /* 70 */
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     /* 78 */
6307     { VEX_W_TABLE (VEX_W_0F3878) },
6308     { VEX_W_TABLE (VEX_W_0F3879) },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     /* 80 */
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     /* 88 */
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { MOD_TABLE (MOD_VEX_0F388C) },
6330     { Bad_Opcode },
6331     { MOD_TABLE (MOD_VEX_0F388E) },
6332     { Bad_Opcode },
6333     /* 90 */
6334     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6335     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6336     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6337     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6341     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6342     /* 98 */
6343     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6344     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6345     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6346     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6347     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6348     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6349     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6350     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6351     /* a0 */
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6359     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6360     /* a8 */
6361     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6362     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6363     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6364     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6365     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6366     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6367     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6368     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6369     /* b0 */
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6377     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6378     /* b8 */
6379     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6380     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6381     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6382     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6383     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6384     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6385     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6386     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6387     /* c0 */
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     /* c8 */
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_W_TABLE (VEX_W_0F38CF) },
6405     /* d0 */
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     /* d8 */
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6419     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6420     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6421     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6422     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6423     /* e0 */
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     /* e8 */
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     /* f0 */
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6445     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6448     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6449     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6450     /* f8 */
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459   },
6460   /* VEX_0F3A */
6461   {
6462     /* 00 */
6463     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6464     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6465     { VEX_W_TABLE (VEX_W_0F3A02) },
6466     { Bad_Opcode },
6467     { VEX_W_TABLE (VEX_W_0F3A04) },
6468     { VEX_W_TABLE (VEX_W_0F3A05) },
6469     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6470     { Bad_Opcode },
6471     /* 08 */
6472     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6473     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6474     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6475     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6476     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6477     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6478     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6479     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6480     /* 10 */
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6486     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6489     /* 18 */
6490     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_W_TABLE (VEX_W_0F3A1D) },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     /* 20 */
6499     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     /* 28 */
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     /* 30 */
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6518     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6519     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6520     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     /* 38 */
6526     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6527     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     /* 40 */
6535     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6537     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6538     { Bad_Opcode },
6539     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6540     { Bad_Opcode },
6541     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6542     { Bad_Opcode },
6543     /* 48 */
6544     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6545     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6546     { VEX_W_TABLE (VEX_W_0F3A4A) },
6547     { VEX_W_TABLE (VEX_W_0F3A4B) },
6548     { VEX_W_TABLE (VEX_W_0F3A4C) },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     /* 50 */
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     /* 58 */
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6567     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6568     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6569     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6570     /* 60 */
6571     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6572     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6573     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6574     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     /* 68 */
6580     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6581     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6582     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6583     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6584     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6585     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6586     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6587     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6588     /* 70 */
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     /* 78 */
6598     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6599     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6600     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6601     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6602     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6603     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6604     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6605     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6606     /* 80 */
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     /* 88 */
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     /* 90 */
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     /* 98 */
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     /* a0 */
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     /* a8 */
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     /* b0 */
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     /* b8 */
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     /* c0 */
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     /* c8 */
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { VEX_W_TABLE (VEX_W_0F3ACE) },
6695     { VEX_W_TABLE (VEX_W_0F3ACF) },
6696     /* d0 */
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     /* d8 */
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6714     /* e0 */
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     /* e8 */
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     /* f0 */
6733     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     /* f8 */
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750   },
6751 };
6752
6753 #include "i386-dis-evex.h"
6754
6755 static const struct dis386 vex_len_table[][2] = {
6756   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6757   {
6758     { "vmovlpX",        { XM, Vex, EXq }, PREFIX_OPCODE },
6759   },
6760
6761   /* VEX_LEN_0F12_P_0_M_1 */
6762   {
6763     { "vmovhlp%XS",     { XM, Vex, EXq }, 0 },
6764   },
6765
6766   /* VEX_LEN_0F13_M_0 */
6767   {
6768     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6769   },
6770
6771   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6772   {
6773     { "vmovhpX",        { XM, Vex, EXq }, PREFIX_OPCODE },
6774   },
6775
6776   /* VEX_LEN_0F16_P_0_M_1 */
6777   {
6778     { "vmovlhp%XS",     { XM, Vex, EXq }, 0 },
6779   },
6780
6781   /* VEX_LEN_0F17_M_0 */
6782   {
6783     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6784   },
6785
6786   /* VEX_LEN_0F41 */
6787   {
6788     { Bad_Opcode },
6789     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6790   },
6791
6792   /* VEX_LEN_0F42 */
6793   {
6794     { Bad_Opcode },
6795     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6796   },
6797
6798   /* VEX_LEN_0F44 */
6799   {
6800     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6801   },
6802
6803   /* VEX_LEN_0F45 */
6804   {
6805     { Bad_Opcode },
6806     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6807   },
6808
6809   /* VEX_LEN_0F46 */
6810   {
6811     { Bad_Opcode },
6812     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6813   },
6814
6815   /* VEX_LEN_0F47 */
6816   {
6817     { Bad_Opcode },
6818     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6819   },
6820
6821   /* VEX_LEN_0F4A */
6822   {
6823     { Bad_Opcode },
6824     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6825   },
6826
6827   /* VEX_LEN_0F4B */
6828   {
6829     { Bad_Opcode },
6830     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6831   },
6832
6833   /* VEX_LEN_0F6E */
6834   {
6835     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6836   },
6837
6838   /* VEX_LEN_0F77 */
6839   {
6840     { "vzeroupper",     { XX }, 0 },
6841     { "vzeroall",       { XX }, 0 },
6842   },
6843
6844   /* VEX_LEN_0F7E_P_1 */
6845   {
6846     { "vmovq",          { XMScalar, EXq }, 0 },
6847   },
6848
6849   /* VEX_LEN_0F7E_P_2 */
6850   {
6851     { "vmovK",          { Edq, XMScalar }, 0 },
6852   },
6853
6854   /* VEX_LEN_0F90 */
6855   {
6856     { VEX_W_TABLE (VEX_W_0F90_L_0) },
6857   },
6858
6859   /* VEX_LEN_0F91 */
6860   {
6861     { MOD_TABLE (MOD_VEX_0F91_L_0) },
6862   },
6863
6864   /* VEX_LEN_0F92 */
6865   {
6866     { MOD_TABLE (MOD_VEX_0F92_L_0) },
6867   },
6868
6869   /* VEX_LEN_0F93 */
6870   {
6871     { MOD_TABLE (MOD_VEX_0F93_L_0) },
6872   },
6873
6874   /* VEX_LEN_0F98 */
6875   {
6876     { MOD_TABLE (MOD_VEX_0F98_L_0) },
6877   },
6878
6879   /* VEX_LEN_0F99 */
6880   {
6881     { MOD_TABLE (MOD_VEX_0F99_L_0) },
6882   },
6883
6884   /* VEX_LEN_0FAE_R_2_M_0 */
6885   {
6886     { "vldmxcsr",       { Md }, 0 },
6887   },
6888
6889   /* VEX_LEN_0FAE_R_3_M_0 */
6890   {
6891     { "vstmxcsr",       { Md }, 0 },
6892   },
6893
6894   /* VEX_LEN_0FC4 */
6895   {
6896     { "vpinsrw",        { XM, Vex, Edw, Ib }, PREFIX_DATA },
6897   },
6898
6899   /* VEX_LEN_0FC5 */
6900   {
6901     { "vpextrw",        { Gd, XS, Ib }, PREFIX_DATA },
6902   },
6903
6904   /* VEX_LEN_0FD6 */
6905   {
6906     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6907   },
6908
6909   /* VEX_LEN_0FF7 */
6910   {
6911     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6912   },
6913
6914   /* VEX_LEN_0F3816 */
6915   {
6916     { Bad_Opcode },
6917     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6918   },
6919
6920   /* VEX_LEN_0F3819 */
6921   {
6922     { Bad_Opcode },
6923     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6924   },
6925
6926   /* VEX_LEN_0F381A_M_0 */
6927   {
6928     { Bad_Opcode },
6929     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6930   },
6931
6932   /* VEX_LEN_0F3836 */
6933   {
6934     { Bad_Opcode },
6935     { VEX_W_TABLE (VEX_W_0F3836) },
6936   },
6937
6938   /* VEX_LEN_0F3841 */
6939   {
6940     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6941   },
6942
6943    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6944   {
6945     { "ldtilecfg", { M }, 0 },
6946   },
6947
6948   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6949   {
6950     { "tilerelease", { Skip_MODRM }, 0 },
6951   },
6952
6953   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6954   {
6955     { "sttilecfg", { M }, 0 },
6956   },
6957
6958   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6959   {
6960     { "tilezero", { TMM, Skip_MODRM }, 0 },
6961   },
6962
6963   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6964   {
6965     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6966   },
6967   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6968   {
6969     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6970   },
6971
6972   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6973   {
6974     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6975   },
6976
6977   /* VEX_LEN_0F385A_M_0 */
6978   {
6979     { Bad_Opcode },
6980     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6981   },
6982
6983   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6984   {
6985     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6986   },
6987
6988   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6989   {
6990     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6991   },
6992
6993   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6994   {
6995     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6996   },
6997
6998   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6999   {
7000     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7001   },
7002
7003   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7004   {
7005     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7006   },
7007
7008   /* VEX_LEN_0F38DB */
7009   {
7010     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7011   },
7012
7013   /* VEX_LEN_0F38F2 */
7014   {
7015     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7016   },
7017
7018   /* VEX_LEN_0F38F3 */
7019   {
7020     { REG_TABLE(REG_VEX_0F38F3_L_0) },
7021   },
7022
7023   /* VEX_LEN_0F38F5 */
7024   {
7025     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7026   },
7027
7028   /* VEX_LEN_0F38F6 */
7029   {
7030     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7031   },
7032
7033   /* VEX_LEN_0F38F7 */
7034   {
7035     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7036   },
7037
7038   /* VEX_LEN_0F3A00 */
7039   {
7040     { Bad_Opcode },
7041     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7042   },
7043
7044   /* VEX_LEN_0F3A01 */
7045   {
7046     { Bad_Opcode },
7047     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7048   },
7049
7050   /* VEX_LEN_0F3A06 */
7051   {
7052     { Bad_Opcode },
7053     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7054   },
7055
7056   /* VEX_LEN_0F3A14 */
7057   {
7058     { "vpextrb",        { Edb, XM, Ib }, PREFIX_DATA },
7059   },
7060
7061   /* VEX_LEN_0F3A15 */
7062   {
7063     { "vpextrw",        { Edw, XM, Ib }, PREFIX_DATA },
7064   },
7065
7066   /* VEX_LEN_0F3A16  */
7067   {
7068     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
7069   },
7070
7071   /* VEX_LEN_0F3A17 */
7072   {
7073     { "vextractps",     { Ed, XM, Ib }, PREFIX_DATA },
7074   },
7075
7076   /* VEX_LEN_0F3A18 */
7077   {
7078     { Bad_Opcode },
7079     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7080   },
7081
7082   /* VEX_LEN_0F3A19 */
7083   {
7084     { Bad_Opcode },
7085     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7086   },
7087
7088   /* VEX_LEN_0F3A20 */
7089   {
7090     { "vpinsrb",        { XM, Vex, Edb, Ib }, PREFIX_DATA },
7091   },
7092
7093   /* VEX_LEN_0F3A21 */
7094   {
7095     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
7096   },
7097
7098   /* VEX_LEN_0F3A22 */
7099   {
7100     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
7101   },
7102
7103   /* VEX_LEN_0F3A30 */
7104   {
7105     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7106   },
7107
7108   /* VEX_LEN_0F3A31 */
7109   {
7110     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7111   },
7112
7113   /* VEX_LEN_0F3A32 */
7114   {
7115     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7116   },
7117
7118   /* VEX_LEN_0F3A33 */
7119   {
7120     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7121   },
7122
7123   /* VEX_LEN_0F3A38 */
7124   {
7125     { Bad_Opcode },
7126     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7127   },
7128
7129   /* VEX_LEN_0F3A39 */
7130   {
7131     { Bad_Opcode },
7132     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7133   },
7134
7135   /* VEX_LEN_0F3A41 */
7136   {
7137     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7138   },
7139
7140   /* VEX_LEN_0F3A46 */
7141   {
7142     { Bad_Opcode },
7143     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7144   },
7145
7146   /* VEX_LEN_0F3A60 */
7147   {
7148     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7149   },
7150
7151   /* VEX_LEN_0F3A61 */
7152   {
7153     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7154   },
7155
7156   /* VEX_LEN_0F3A62 */
7157   {
7158     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7159   },
7160
7161   /* VEX_LEN_0F3A63 */
7162   {
7163     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7164   },
7165
7166   /* VEX_LEN_0F3ADF */
7167   {
7168     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7169   },
7170
7171   /* VEX_LEN_0F3AF0 */
7172   {
7173     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7174   },
7175
7176   /* VEX_LEN_0FXOP_08_85 */
7177   {
7178     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7179   },
7180
7181   /* VEX_LEN_0FXOP_08_86 */
7182   {
7183     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7184   },
7185
7186   /* VEX_LEN_0FXOP_08_87 */
7187   {
7188     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7189   },
7190
7191   /* VEX_LEN_0FXOP_08_8E */
7192   {
7193     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7194   },
7195
7196   /* VEX_LEN_0FXOP_08_8F */
7197   {
7198     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7199   },
7200
7201   /* VEX_LEN_0FXOP_08_95 */
7202   {
7203     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7204   },
7205
7206   /* VEX_LEN_0FXOP_08_96 */
7207   {
7208     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7209   },
7210
7211   /* VEX_LEN_0FXOP_08_97 */
7212   {
7213     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7214   },
7215
7216   /* VEX_LEN_0FXOP_08_9E */
7217   {
7218     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7219   },
7220
7221   /* VEX_LEN_0FXOP_08_9F */
7222   {
7223     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7224   },
7225
7226   /* VEX_LEN_0FXOP_08_A3 */
7227   {
7228     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7229   },
7230
7231   /* VEX_LEN_0FXOP_08_A6 */
7232   {
7233     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7234   },
7235
7236   /* VEX_LEN_0FXOP_08_B6 */
7237   {
7238     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7239   },
7240
7241   /* VEX_LEN_0FXOP_08_C0 */
7242   {
7243     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7244   },
7245
7246   /* VEX_LEN_0FXOP_08_C1 */
7247   {
7248     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7249   },
7250
7251   /* VEX_LEN_0FXOP_08_C2 */
7252   {
7253     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7254   },
7255
7256   /* VEX_LEN_0FXOP_08_C3 */
7257   {
7258     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7259   },
7260
7261   /* VEX_LEN_0FXOP_08_CC */
7262   {
7263     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7264   },
7265
7266   /* VEX_LEN_0FXOP_08_CD */
7267   {
7268     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7269   },
7270
7271   /* VEX_LEN_0FXOP_08_CE */
7272   {
7273     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7274   },
7275
7276   /* VEX_LEN_0FXOP_08_CF */
7277   {
7278     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7279   },
7280
7281   /* VEX_LEN_0FXOP_08_EC */
7282   {
7283     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7284   },
7285
7286   /* VEX_LEN_0FXOP_08_ED */
7287   {
7288     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7289   },
7290
7291   /* VEX_LEN_0FXOP_08_EE */
7292   {
7293     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7294   },
7295
7296   /* VEX_LEN_0FXOP_08_EF */
7297   {
7298     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7299   },
7300
7301   /* VEX_LEN_0FXOP_09_01 */
7302   {
7303     { REG_TABLE (REG_XOP_09_01_L_0) },
7304   },
7305
7306   /* VEX_LEN_0FXOP_09_02 */
7307   {
7308     { REG_TABLE (REG_XOP_09_02_L_0) },
7309   },
7310
7311   /* VEX_LEN_0FXOP_09_12_M_1 */
7312   {
7313     { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7314   },
7315
7316   /* VEX_LEN_0FXOP_09_82_W_0 */
7317   {
7318     { "vfrczss",        { XM, EXd }, 0 },
7319   },
7320
7321   /* VEX_LEN_0FXOP_09_83_W_0 */
7322   {
7323     { "vfrczsd",        { XM, EXq }, 0 },
7324   },
7325
7326   /* VEX_LEN_0FXOP_09_90 */
7327   {
7328     { "vprotb",         { XM, EXx, VexW }, 0 },
7329   },
7330
7331   /* VEX_LEN_0FXOP_09_91 */
7332   {
7333     { "vprotw",         { XM, EXx, VexW }, 0 },
7334   },
7335
7336   /* VEX_LEN_0FXOP_09_92 */
7337   {
7338     { "vprotd",         { XM, EXx, VexW }, 0 },
7339   },
7340
7341   /* VEX_LEN_0FXOP_09_93 */
7342   {
7343     { "vprotq",         { XM, EXx, VexW }, 0 },
7344   },
7345
7346   /* VEX_LEN_0FXOP_09_94 */
7347   {
7348     { "vpshlb",         { XM, EXx, VexW }, 0 },
7349   },
7350
7351   /* VEX_LEN_0FXOP_09_95 */
7352   {
7353     { "vpshlw",         { XM, EXx, VexW }, 0 },
7354   },
7355
7356   /* VEX_LEN_0FXOP_09_96 */
7357   {
7358     { "vpshld",         { XM, EXx, VexW }, 0 },
7359   },
7360
7361   /* VEX_LEN_0FXOP_09_97 */
7362   {
7363     { "vpshlq",         { XM, EXx, VexW }, 0 },
7364   },
7365
7366   /* VEX_LEN_0FXOP_09_98 */
7367   {
7368     { "vpshab",         { XM, EXx, VexW }, 0 },
7369   },
7370
7371   /* VEX_LEN_0FXOP_09_99 */
7372   {
7373     { "vpshaw",         { XM, EXx, VexW }, 0 },
7374   },
7375
7376   /* VEX_LEN_0FXOP_09_9A */
7377   {
7378     { "vpshad",         { XM, EXx, VexW }, 0 },
7379   },
7380
7381   /* VEX_LEN_0FXOP_09_9B */
7382   {
7383     { "vpshaq",         { XM, EXx, VexW }, 0 },
7384   },
7385
7386   /* VEX_LEN_0FXOP_09_C1 */
7387   {
7388     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7389   },
7390
7391   /* VEX_LEN_0FXOP_09_C2 */
7392   {
7393     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7394   },
7395
7396   /* VEX_LEN_0FXOP_09_C3 */
7397   {
7398     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7399   },
7400
7401   /* VEX_LEN_0FXOP_09_C6 */
7402   {
7403     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7404   },
7405
7406   /* VEX_LEN_0FXOP_09_C7 */
7407   {
7408     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7409   },
7410
7411   /* VEX_LEN_0FXOP_09_CB */
7412   {
7413     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7414   },
7415
7416   /* VEX_LEN_0FXOP_09_D1 */
7417   {
7418     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7419   },
7420
7421   /* VEX_LEN_0FXOP_09_D2 */
7422   {
7423     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7424   },
7425
7426   /* VEX_LEN_0FXOP_09_D3 */
7427   {
7428     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7429   },
7430
7431   /* VEX_LEN_0FXOP_09_D6 */
7432   {
7433     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7434   },
7435
7436   /* VEX_LEN_0FXOP_09_D7 */
7437   {
7438     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7439   },
7440
7441   /* VEX_LEN_0FXOP_09_DB */
7442   {
7443     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7444   },
7445
7446   /* VEX_LEN_0FXOP_09_E1 */
7447   {
7448     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7449   },
7450
7451   /* VEX_LEN_0FXOP_09_E2 */
7452   {
7453     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7454   },
7455
7456   /* VEX_LEN_0FXOP_09_E3 */
7457   {
7458     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7459   },
7460
7461   /* VEX_LEN_0FXOP_0A_12 */
7462   {
7463     { REG_TABLE (REG_XOP_0A_12_L_0) },
7464   },
7465 };
7466
7467 #include "i386-dis-evex-len.h"
7468
7469 static const struct dis386 vex_w_table[][2] = {
7470   {
7471     /* VEX_W_0F41_L_1_M_1 */
7472     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7473     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7474   },
7475   {
7476     /* VEX_W_0F42_L_1_M_1 */
7477     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7478     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7479   },
7480   {
7481     /* VEX_W_0F44_L_0_M_1 */
7482     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7483     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7484   },
7485   {
7486     /* VEX_W_0F45_L_1_M_1 */
7487     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7488     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7489   },
7490   {
7491     /* VEX_W_0F46_L_1_M_1 */
7492     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7493     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7494   },
7495   {
7496     /* VEX_W_0F47_L_1_M_1 */
7497     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7498     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7499   },
7500   {
7501     /* VEX_W_0F4A_L_1_M_1 */
7502     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7503     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7504   },
7505   {
7506     /* VEX_W_0F4B_L_1_M_1 */
7507     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7508     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7509   },
7510   {
7511     /* VEX_W_0F90_L_0 */
7512     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7513     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7514   },
7515   {
7516     /* VEX_W_0F91_L_0_M_0 */
7517     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7518     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7519   },
7520   {
7521     /* VEX_W_0F92_L_0_M_1 */
7522     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7523     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7524   },
7525   {
7526     /* VEX_W_0F93_L_0_M_1 */
7527     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7528     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7529   },
7530   {
7531     /* VEX_W_0F98_L_0_M_1 */
7532     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7533     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7534   },
7535   {
7536     /* VEX_W_0F99_L_0_M_1 */
7537     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7538     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7539   },
7540   {
7541     /* VEX_W_0F380C  */
7542     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7543   },
7544   {
7545     /* VEX_W_0F380D  */
7546     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7547   },
7548   {
7549     /* VEX_W_0F380E  */
7550     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7551   },
7552   {
7553     /* VEX_W_0F380F  */
7554     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7555   },
7556   {
7557     /* VEX_W_0F3813 */
7558     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7559   },
7560   {
7561     /* VEX_W_0F3816_L_1  */
7562     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7563   },
7564   {
7565     /* VEX_W_0F3818 */
7566     { "vbroadcastss",   { XM, EXd }, PREFIX_DATA },
7567   },
7568   {
7569     /* VEX_W_0F3819_L_1 */
7570     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7571   },
7572   {
7573     /* VEX_W_0F381A_M_0_L_1 */
7574     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7575   },
7576   {
7577     /* VEX_W_0F382C_M_0 */
7578     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7579   },
7580   {
7581     /* VEX_W_0F382D_M_0 */
7582     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7583   },
7584   {
7585     /* VEX_W_0F382E_M_0 */
7586     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7587   },
7588   {
7589     /* VEX_W_0F382F_M_0 */
7590     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7591   },
7592   {
7593     /* VEX_W_0F3836  */
7594     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7595   },
7596   {
7597     /* VEX_W_0F3846 */
7598     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7599   },
7600   {
7601     /* VEX_W_0F3849_X86_64_P_0 */
7602     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7603   },
7604   {
7605     /* VEX_W_0F3849_X86_64_P_2 */
7606     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7607   },
7608   {
7609     /* VEX_W_0F3849_X86_64_P_3 */
7610     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7611   },
7612   {
7613     /* VEX_W_0F384B_X86_64_P_1 */
7614     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7615   },
7616   {
7617     /* VEX_W_0F384B_X86_64_P_2 */
7618     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7619   },
7620   {
7621     /* VEX_W_0F384B_X86_64_P_3 */
7622     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7623   },
7624   {
7625     /* VEX_W_0F3850 */
7626     { "%XV vpdpbusd",   { XM, Vex, EXx }, 0 },
7627   },
7628   {
7629     /* VEX_W_0F3851 */
7630     { "%XV vpdpbusds",  { XM, Vex, EXx }, 0 },
7631   },
7632   {
7633     /* VEX_W_0F3852 */
7634     { "%XV vpdpwssd",   { XM, Vex, EXx }, 0 },
7635   },
7636   {
7637     /* VEX_W_0F3853 */
7638     { "%XV vpdpwssds",  { XM, Vex, EXx }, 0 },
7639   },
7640   {
7641     /* VEX_W_0F3858 */
7642     { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
7643   },
7644   {
7645     /* VEX_W_0F3859 */
7646     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7647   },
7648   {
7649     /* VEX_W_0F385A_M_0_L_0 */
7650     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7651   },
7652   {
7653     /* VEX_W_0F385C_X86_64_P_1 */
7654     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7655   },
7656   {
7657     /* VEX_W_0F385E_X86_64_P_0 */
7658     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7659   },
7660   {
7661     /* VEX_W_0F385E_X86_64_P_1 */
7662     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7663   },
7664   {
7665     /* VEX_W_0F385E_X86_64_P_2 */
7666     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7667   },
7668   {
7669     /* VEX_W_0F385E_X86_64_P_3 */
7670     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7671   },
7672   {
7673     /* VEX_W_0F3878 */
7674     { "vpbroadcastb",   { XM, EXb }, PREFIX_DATA },
7675   },
7676   {
7677     /* VEX_W_0F3879 */
7678     { "vpbroadcastw",   { XM, EXw }, PREFIX_DATA },
7679   },
7680   {
7681     /* VEX_W_0F38CF */
7682     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7683   },
7684   {
7685     /* VEX_W_0F3A00_L_1 */
7686     { Bad_Opcode },
7687     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7688   },
7689   {
7690     /* VEX_W_0F3A01_L_1 */
7691     { Bad_Opcode },
7692     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7693   },
7694   {
7695     /* VEX_W_0F3A02 */
7696     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7697   },
7698   {
7699     /* VEX_W_0F3A04 */
7700     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7701   },
7702   {
7703     /* VEX_W_0F3A05 */
7704     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7705   },
7706   {
7707     /* VEX_W_0F3A06_L_1 */
7708     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7709   },
7710   {
7711     /* VEX_W_0F3A18_L_1 */
7712     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7713   },
7714   {
7715     /* VEX_W_0F3A19_L_1 */
7716     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7717   },
7718   {
7719     /* VEX_W_0F3A1D */
7720     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7721   },
7722   {
7723     /* VEX_W_0F3A38_L_1 */
7724     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7725   },
7726   {
7727     /* VEX_W_0F3A39_L_1 */
7728     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7729   },
7730   {
7731     /* VEX_W_0F3A46_L_1 */
7732     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7733   },
7734   {
7735     /* VEX_W_0F3A4A */
7736     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7737   },
7738   {
7739     /* VEX_W_0F3A4B */
7740     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7741   },
7742   {
7743     /* VEX_W_0F3A4C */
7744     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7745   },
7746   {
7747     /* VEX_W_0F3ACE */
7748     { Bad_Opcode },
7749     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7750   },
7751   {
7752     /* VEX_W_0F3ACF */
7753     { Bad_Opcode },
7754     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7755   },
7756   /* VEX_W_0FXOP_08_85_L_0 */
7757   {
7758     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7759   },
7760   /* VEX_W_0FXOP_08_86_L_0 */
7761   {
7762     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7763   },
7764   /* VEX_W_0FXOP_08_87_L_0 */
7765   {
7766     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7767   },
7768   /* VEX_W_0FXOP_08_8E_L_0 */
7769   {
7770     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7771   },
7772   /* VEX_W_0FXOP_08_8F_L_0 */
7773   {
7774     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7775   },
7776   /* VEX_W_0FXOP_08_95_L_0 */
7777   {
7778     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7779   },
7780   /* VEX_W_0FXOP_08_96_L_0 */
7781   {
7782     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7783   },
7784   /* VEX_W_0FXOP_08_97_L_0 */
7785   {
7786     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7787   },
7788   /* VEX_W_0FXOP_08_9E_L_0 */
7789   {
7790     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7791   },
7792   /* VEX_W_0FXOP_08_9F_L_0 */
7793   {
7794     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7795   },
7796   /* VEX_W_0FXOP_08_A6_L_0 */
7797   {
7798     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7799   },
7800   /* VEX_W_0FXOP_08_B6_L_0 */
7801   {
7802     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7803   },
7804   /* VEX_W_0FXOP_08_C0_L_0 */
7805   {
7806     { "vprotb",         { XM, EXx, Ib }, 0 },
7807   },
7808   /* VEX_W_0FXOP_08_C1_L_0 */
7809   {
7810     { "vprotw",         { XM, EXx, Ib }, 0 },
7811   },
7812   /* VEX_W_0FXOP_08_C2_L_0 */
7813   {
7814     { "vprotd",         { XM, EXx, Ib }, 0 },
7815   },
7816   /* VEX_W_0FXOP_08_C3_L_0 */
7817   {
7818     { "vprotq",         { XM, EXx, Ib }, 0 },
7819   },
7820   /* VEX_W_0FXOP_08_CC_L_0 */
7821   {
7822      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7823   },
7824   /* VEX_W_0FXOP_08_CD_L_0 */
7825   {
7826      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7827   },
7828   /* VEX_W_0FXOP_08_CE_L_0 */
7829   {
7830      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7831   },
7832   /* VEX_W_0FXOP_08_CF_L_0 */
7833   {
7834      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7835   },
7836   /* VEX_W_0FXOP_08_EC_L_0 */
7837   {
7838      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7839   },
7840   /* VEX_W_0FXOP_08_ED_L_0 */
7841   {
7842      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7843   },
7844   /* VEX_W_0FXOP_08_EE_L_0 */
7845   {
7846      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7847   },
7848   /* VEX_W_0FXOP_08_EF_L_0 */
7849   {
7850      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7851   },
7852   /* VEX_W_0FXOP_09_80 */
7853   {
7854     { "vfrczps",        { XM, EXx }, 0 },
7855   },
7856   /* VEX_W_0FXOP_09_81 */
7857   {
7858     { "vfrczpd",        { XM, EXx }, 0 },
7859   },
7860   /* VEX_W_0FXOP_09_82 */
7861   {
7862     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7863   },
7864   /* VEX_W_0FXOP_09_83 */
7865   {
7866     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7867   },
7868   /* VEX_W_0FXOP_09_C1_L_0 */
7869   {
7870     { "vphaddbw",       { XM, EXxmm }, 0 },
7871   },
7872   /* VEX_W_0FXOP_09_C2_L_0 */
7873   {
7874     { "vphaddbd",       { XM, EXxmm }, 0 },
7875   },
7876   /* VEX_W_0FXOP_09_C3_L_0 */
7877   {
7878     { "vphaddbq",       { XM, EXxmm }, 0 },
7879   },
7880   /* VEX_W_0FXOP_09_C6_L_0 */
7881   {
7882     { "vphaddwd",       { XM, EXxmm }, 0 },
7883   },
7884   /* VEX_W_0FXOP_09_C7_L_0 */
7885   {
7886     { "vphaddwq",       { XM, EXxmm }, 0 },
7887   },
7888   /* VEX_W_0FXOP_09_CB_L_0 */
7889   {
7890     { "vphadddq",       { XM, EXxmm }, 0 },
7891   },
7892   /* VEX_W_0FXOP_09_D1_L_0 */
7893   {
7894     { "vphaddubw",      { XM, EXxmm }, 0 },
7895   },
7896   /* VEX_W_0FXOP_09_D2_L_0 */
7897   {
7898     { "vphaddubd",      { XM, EXxmm }, 0 },
7899   },
7900   /* VEX_W_0FXOP_09_D3_L_0 */
7901   {
7902     { "vphaddubq",      { XM, EXxmm }, 0 },
7903   },
7904   /* VEX_W_0FXOP_09_D6_L_0 */
7905   {
7906     { "vphadduwd",      { XM, EXxmm }, 0 },
7907   },
7908   /* VEX_W_0FXOP_09_D7_L_0 */
7909   {
7910     { "vphadduwq",      { XM, EXxmm }, 0 },
7911   },
7912   /* VEX_W_0FXOP_09_DB_L_0 */
7913   {
7914     { "vphaddudq",      { XM, EXxmm }, 0 },
7915   },
7916   /* VEX_W_0FXOP_09_E1_L_0 */
7917   {
7918     { "vphsubbw",       { XM, EXxmm }, 0 },
7919   },
7920   /* VEX_W_0FXOP_09_E2_L_0 */
7921   {
7922     { "vphsubwd",       { XM, EXxmm }, 0 },
7923   },
7924   /* VEX_W_0FXOP_09_E3_L_0 */
7925   {
7926     { "vphsubdq",       { XM, EXxmm }, 0 },
7927   },
7928
7929 #include "i386-dis-evex-w.h"
7930 };
7931
7932 static const struct dis386 mod_table[][2] = {
7933   {
7934     /* MOD_62_32BIT */
7935     { "bound{S|}",      { Gv, Ma }, 0 },
7936     { EVEX_TABLE (EVEX_0F) },
7937   },
7938   {
7939     /* MOD_8D */
7940     { "leaS",           { Gv, M }, 0 },
7941   },
7942   {
7943     /* MOD_C4_32BIT */
7944     { "lesS",           { Gv, Mp }, 0 },
7945     { VEX_C4_TABLE (VEX_0F) },
7946   },
7947   {
7948     /* MOD_C5_32BIT */
7949     { "ldsS",           { Gv, Mp }, 0 },
7950     { VEX_C5_TABLE (VEX_0F) },
7951   },
7952   {
7953     /* MOD_C6_REG_7 */
7954     { Bad_Opcode },
7955     { RM_TABLE (RM_C6_REG_7) },
7956   },
7957   {
7958     /* MOD_C7_REG_7 */
7959     { Bad_Opcode },
7960     { RM_TABLE (RM_C7_REG_7) },
7961   },
7962   {
7963     /* MOD_FF_REG_3 */
7964     { "{l|}call^", { indirEp }, 0 },
7965   },
7966   {
7967     /* MOD_FF_REG_5 */
7968     { "{l|}jmp^", { indirEp }, 0 },
7969   },
7970   {
7971     /* MOD_0F01_REG_0 */
7972     { X86_64_TABLE (X86_64_0F01_REG_0) },
7973     { RM_TABLE (RM_0F01_REG_0) },
7974   },
7975   {
7976     /* MOD_0F01_REG_1 */
7977     { X86_64_TABLE (X86_64_0F01_REG_1) },
7978     { RM_TABLE (RM_0F01_REG_1) },
7979   },
7980   {
7981     /* MOD_0F01_REG_2 */
7982     { X86_64_TABLE (X86_64_0F01_REG_2) },
7983     { RM_TABLE (RM_0F01_REG_2) },
7984   },
7985   {
7986     /* MOD_0F01_REG_3 */
7987     { X86_64_TABLE (X86_64_0F01_REG_3) },
7988     { RM_TABLE (RM_0F01_REG_3) },
7989   },
7990   {
7991     /* MOD_0F01_REG_5 */
7992     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7993     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7994   },
7995   {
7996     /* MOD_0F01_REG_7 */
7997     { "invlpg",         { Mb }, 0 },
7998     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7999   },
8000   {
8001     /* MOD_0F12_PREFIX_0 */
8002     { "movlpX",         { XM, EXq }, 0 },
8003     { "movhlps",        { XM, EXq }, 0 },
8004   },
8005   {
8006     /* MOD_0F12_PREFIX_2 */
8007     { "movlpX", { XM, EXq }, 0 },
8008   },
8009   {
8010     /* MOD_0F13 */
8011     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
8012   },
8013   {
8014     /* MOD_0F16_PREFIX_0 */
8015     { "movhpX",         { XM, EXq }, 0 },
8016     { "movlhps",        { XM, EXq }, 0 },
8017   },
8018   {
8019     /* MOD_0F16_PREFIX_2 */
8020     { "movhpX", { XM, EXq }, 0 },
8021   },
8022   {
8023     /* MOD_0F17 */
8024     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8025   },
8026   {
8027     /* MOD_0F18_REG_0 */
8028     { "prefetchnta",    { Mb }, 0 },
8029     { "nopQ",           { Ev }, 0 },
8030   },
8031   {
8032     /* MOD_0F18_REG_1 */
8033     { "prefetcht0",     { Mb }, 0 },
8034     { "nopQ",           { Ev }, 0 },
8035   },
8036   {
8037     /* MOD_0F18_REG_2 */
8038     { "prefetcht1",     { Mb }, 0 },
8039     { "nopQ",           { Ev }, 0 },
8040   },
8041   {
8042     /* MOD_0F18_REG_3 */
8043     { "prefetcht2",     { Mb }, 0 },
8044     { "nopQ",           { Ev }, 0 },
8045   },
8046   {
8047     /* MOD_0F1A_PREFIX_0 */
8048     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8049     { "nopQ",           { Ev }, 0 },
8050   },
8051   {
8052     /* MOD_0F1B_PREFIX_0 */
8053     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8054     { "nopQ",           { Ev }, 0 },
8055   },
8056   {
8057     /* MOD_0F1B_PREFIX_1 */
8058     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8059     { "nopQ",           { Ev }, PREFIX_IGNORED },
8060   },
8061   {
8062     /* MOD_0F1C_PREFIX_0 */
8063     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8064     { "nopQ",           { Ev }, 0 },
8065   },
8066   {
8067     /* MOD_0F1E_PREFIX_1 */
8068     { "nopQ",           { Ev }, PREFIX_IGNORED },
8069     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8070   },
8071   {
8072     /* MOD_0F2B_PREFIX_0 */
8073     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8074   },
8075   {
8076     /* MOD_0F2B_PREFIX_1 */
8077     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8078   },
8079   {
8080     /* MOD_0F2B_PREFIX_2 */
8081     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8082   },
8083   {
8084     /* MOD_0F2B_PREFIX_3 */
8085     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8086   },
8087   {
8088     /* MOD_0F50 */
8089     { Bad_Opcode },
8090     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8091   },
8092   {
8093     /* MOD_0F71 */
8094     { Bad_Opcode },
8095     { REG_TABLE (REG_0F71_MOD_0) },
8096   },
8097   {
8098     /* MOD_0F72 */
8099     { Bad_Opcode },
8100     { REG_TABLE (REG_0F72_MOD_0) },
8101   },
8102   {
8103     /* MOD_0F73 */
8104     { Bad_Opcode },
8105     { REG_TABLE (REG_0F73_MOD_0) },
8106   },
8107   {
8108     /* MOD_0FAE_REG_0 */
8109     { "fxsave",         { FXSAVE }, 0 },
8110     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8111   },
8112   {
8113     /* MOD_0FAE_REG_1 */
8114     { "fxrstor",        { FXSAVE }, 0 },
8115     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8116   },
8117   {
8118     /* MOD_0FAE_REG_2 */
8119     { "ldmxcsr",        { Md }, 0 },
8120     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8121   },
8122   {
8123     /* MOD_0FAE_REG_3 */
8124     { "stmxcsr",        { Md }, 0 },
8125     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8126   },
8127   {
8128     /* MOD_0FAE_REG_4 */
8129     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8130     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8131   },
8132   {
8133     /* MOD_0FAE_REG_5 */
8134     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8135     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8136   },
8137   {
8138     /* MOD_0FAE_REG_6 */
8139     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8140     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8141   },
8142   {
8143     /* MOD_0FAE_REG_7 */
8144     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8145     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8146   },
8147   {
8148     /* MOD_0FB2 */
8149     { "lssS",           { Gv, Mp }, 0 },
8150   },
8151   {
8152     /* MOD_0FB4 */
8153     { "lfsS",           { Gv, Mp }, 0 },
8154   },
8155   {
8156     /* MOD_0FB5 */
8157     { "lgsS",           { Gv, Mp }, 0 },
8158   },
8159   {
8160     /* MOD_0FC3 */
8161     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8162   },
8163   {
8164     /* MOD_0FC7_REG_3 */
8165     { "xrstors",        { FXSAVE }, 0 },
8166   },
8167   {
8168     /* MOD_0FC7_REG_4 */
8169     { "xsavec",         { FXSAVE }, 0 },
8170   },
8171   {
8172     /* MOD_0FC7_REG_5 */
8173     { "xsaves",         { FXSAVE }, 0 },
8174   },
8175   {
8176     /* MOD_0FC7_REG_6 */
8177     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8178     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8179   },
8180   {
8181     /* MOD_0FC7_REG_7 */
8182     { "vmptrst",        { Mq }, 0 },
8183     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8184   },
8185   {
8186     /* MOD_0FD7 */
8187     { Bad_Opcode },
8188     { "pmovmskb",       { Gdq, MS }, 0 },
8189   },
8190   {
8191     /* MOD_0FE7_PREFIX_2 */
8192     { "movntdq",        { Mx, XM }, 0 },
8193   },
8194   {
8195     /* MOD_0FF0_PREFIX_3 */
8196     { "lddqu",          { XM, M }, 0 },
8197   },
8198   {
8199     /* MOD_0F382A */
8200     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8201   },
8202   {
8203     /* MOD_0F38DC_PREFIX_1 */
8204     { "aesenc128kl",    { XM, M }, 0 },
8205     { "loadiwkey",      { XM, EXx }, 0 },
8206   },
8207   {
8208     /* MOD_0F38DD_PREFIX_1 */
8209     { "aesdec128kl",    { XM, M }, 0 },
8210   },
8211   {
8212     /* MOD_0F38DE_PREFIX_1 */
8213     { "aesenc256kl",    { XM, M }, 0 },
8214   },
8215   {
8216     /* MOD_0F38DF_PREFIX_1 */
8217     { "aesdec256kl",    { XM, M }, 0 },
8218   },
8219   {
8220     /* MOD_0F38F5 */
8221     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8222   },
8223   {
8224     /* MOD_0F38F6_PREFIX_0 */
8225     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8226   },
8227   {
8228     /* MOD_0F38F8_PREFIX_1 */
8229     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8230   },
8231   {
8232     /* MOD_0F38F8_PREFIX_2 */
8233     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8234   },
8235   {
8236     /* MOD_0F38F8_PREFIX_3 */
8237     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8238   },
8239   {
8240     /* MOD_0F38F9 */
8241     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8242   },
8243   {
8244     /* MOD_0F38FA_PREFIX_1 */
8245     { Bad_Opcode },
8246     { "encodekey128", { Gd, Ed }, 0 },
8247   },
8248   {
8249     /* MOD_0F38FB_PREFIX_1 */
8250     { Bad_Opcode },
8251     { "encodekey256", { Gd, Ed }, 0 },
8252   },
8253   {
8254     /* MOD_0F3A0F_PREFIX_1 */
8255     { Bad_Opcode },
8256     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8257   },
8258   {
8259     /* MOD_VEX_0F12_PREFIX_0 */
8260     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8261     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8262   },
8263   {
8264     /* MOD_VEX_0F12_PREFIX_2 */
8265     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8266   },
8267   {
8268     /* MOD_VEX_0F13 */
8269     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8270   },
8271   {
8272     /* MOD_VEX_0F16_PREFIX_0 */
8273     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8274     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8275   },
8276   {
8277     /* MOD_VEX_0F16_PREFIX_2 */
8278     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8279   },
8280   {
8281     /* MOD_VEX_0F17 */
8282     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8283   },
8284   {
8285     /* MOD_VEX_0F2B */
8286     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8287   },
8288   {
8289     /* MOD_VEX_0F41_L_1 */
8290     { Bad_Opcode },
8291     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8292   },
8293   {
8294     /* MOD_VEX_0F42_L_1 */
8295     { Bad_Opcode },
8296     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8297   },
8298   {
8299     /* MOD_VEX_0F44_L_0 */
8300     { Bad_Opcode },
8301     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8302   },
8303   {
8304     /* MOD_VEX_0F45_L_1 */
8305     { Bad_Opcode },
8306     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8307   },
8308   {
8309     /* MOD_VEX_0F46_L_1 */
8310     { Bad_Opcode },
8311     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8312   },
8313   {
8314     /* MOD_VEX_0F47_L_1 */
8315     { Bad_Opcode },
8316     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8317   },
8318   {
8319     /* MOD_VEX_0F4A_L_1 */
8320     { Bad_Opcode },
8321     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8322   },
8323   {
8324     /* MOD_VEX_0F4B_L_1 */
8325     { Bad_Opcode },
8326     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8327   },
8328   {
8329     /* MOD_VEX_0F50 */
8330     { Bad_Opcode },
8331     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8332   },
8333   {
8334     /* MOD_VEX_0F71 */
8335     { Bad_Opcode },
8336     { REG_TABLE (REG_VEX_0F71_M_0) },
8337   },
8338   {
8339     /* MOD_VEX_0F72 */
8340     { Bad_Opcode },
8341     { REG_TABLE (REG_VEX_0F72_M_0) },
8342   },
8343   {
8344     /* MOD_VEX_0F73 */
8345     { Bad_Opcode },
8346     { REG_TABLE (REG_VEX_0F73_M_0) },
8347   },
8348   {
8349     /* MOD_VEX_0F91_L_0 */
8350     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8351   },
8352   {
8353     /* MOD_VEX_0F92_L_0 */
8354     { Bad_Opcode },
8355     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8356   },
8357   {
8358     /* MOD_VEX_0F93_L_0 */
8359     { Bad_Opcode },
8360     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8361   },
8362   {
8363     /* MOD_VEX_0F98_L_0 */
8364     { Bad_Opcode },
8365     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8366   },
8367   {
8368     /* MOD_VEX_0F99_L_0 */
8369     { Bad_Opcode },
8370     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8371   },
8372   {
8373     /* MOD_VEX_0FAE_REG_2 */
8374     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8375   },
8376   {
8377     /* MOD_VEX_0FAE_REG_3 */
8378     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8379   },
8380   {
8381     /* MOD_VEX_0FD7 */
8382     { Bad_Opcode },
8383     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8384   },
8385   {
8386     /* MOD_VEX_0FE7 */
8387     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8388   },
8389   {
8390     /* MOD_VEX_0FF0_PREFIX_3 */
8391     { "vlddqu",         { XM, M }, 0 },
8392   },
8393   {
8394     /* MOD_VEX_0F381A */
8395     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8396   },
8397   {
8398     /* MOD_VEX_0F382A */
8399     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8400   },
8401   {
8402     /* MOD_VEX_0F382C */
8403     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8404   },
8405   {
8406     /* MOD_VEX_0F382D */
8407     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8408   },
8409   {
8410     /* MOD_VEX_0F382E */
8411     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8412   },
8413   {
8414     /* MOD_VEX_0F382F */
8415     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8416   },
8417   {
8418     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8419     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8420     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8421   },
8422   {
8423     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8424     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8425   },
8426   {
8427     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8428     { Bad_Opcode },
8429     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8430   },
8431   {
8432     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8433     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8434   },
8435   {
8436     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8437     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8438   },
8439   {
8440     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8441     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8442   },
8443   {
8444     /* MOD_VEX_0F385A */
8445     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8446   },
8447   {
8448     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8449     { Bad_Opcode },
8450     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8451   },
8452   {
8453     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8454     { Bad_Opcode },
8455     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8456   },
8457   {
8458     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8459     { Bad_Opcode },
8460     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8461   },
8462   {
8463     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8464     { Bad_Opcode },
8465     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8466   },
8467   {
8468     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8469     { Bad_Opcode },
8470     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8471   },
8472   {
8473     /* MOD_VEX_0F388C */
8474     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8475   },
8476   {
8477     /* MOD_VEX_0F388E */
8478     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8479   },
8480   {
8481     /* MOD_VEX_0F3A30_L_0 */
8482     { Bad_Opcode },
8483     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8484   },
8485   {
8486     /* MOD_VEX_0F3A31_L_0 */
8487     { Bad_Opcode },
8488     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8489   },
8490   {
8491     /* MOD_VEX_0F3A32_L_0 */
8492     { Bad_Opcode },
8493     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8494   },
8495   {
8496     /* MOD_VEX_0F3A33_L_0 */
8497     { Bad_Opcode },
8498     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8499   },
8500   {
8501     /* MOD_XOP_09_12 */
8502     { Bad_Opcode },
8503     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8504   },
8505
8506 #include "i386-dis-evex-mod.h"
8507 };
8508
8509 static const struct dis386 rm_table[][8] = {
8510   {
8511     /* RM_C6_REG_7 */
8512     { "xabort",         { Skip_MODRM, Ib }, 0 },
8513   },
8514   {
8515     /* RM_C7_REG_7 */
8516     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8517   },
8518   {
8519     /* RM_0F01_REG_0 */
8520     { "enclv",          { Skip_MODRM }, 0 },
8521     { "vmcall",         { Skip_MODRM }, 0 },
8522     { "vmlaunch",       { Skip_MODRM }, 0 },
8523     { "vmresume",       { Skip_MODRM }, 0 },
8524     { "vmxoff",         { Skip_MODRM }, 0 },
8525     { "pconfig",        { Skip_MODRM }, 0 },
8526   },
8527   {
8528     /* RM_0F01_REG_1 */
8529     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8530     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8531     { "clac",           { Skip_MODRM }, 0 },
8532     { "stac",           { Skip_MODRM }, 0 },
8533     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8534     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8535     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8536     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8537   },
8538   {
8539     /* RM_0F01_REG_2 */
8540     { "xgetbv",         { Skip_MODRM }, 0 },
8541     { "xsetbv",         { Skip_MODRM }, 0 },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { "vmfunc",         { Skip_MODRM }, 0 },
8545     { "xend",           { Skip_MODRM }, 0 },
8546     { "xtest",          { Skip_MODRM }, 0 },
8547     { "enclu",          { Skip_MODRM }, 0 },
8548   },
8549   {
8550     /* RM_0F01_REG_3 */
8551     { "vmrun",          { Skip_MODRM }, 0 },
8552     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8553     { "vmload",         { Skip_MODRM }, 0 },
8554     { "vmsave",         { Skip_MODRM }, 0 },
8555     { "stgi",           { Skip_MODRM }, 0 },
8556     { "clgi",           { Skip_MODRM }, 0 },
8557     { "skinit",         { Skip_MODRM }, 0 },
8558     { "invlpga",        { Skip_MODRM }, 0 },
8559   },
8560   {
8561     /* RM_0F01_REG_5_MOD_3 */
8562     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8563     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8564     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8565     { Bad_Opcode },
8566     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8567     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8568     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8569     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8570   },
8571   {
8572     /* RM_0F01_REG_7_MOD_3 */
8573     { "swapgs",         { Skip_MODRM }, 0  },
8574     { "rdtscp",         { Skip_MODRM }, 0  },
8575     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8576     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8577     { "clzero",         { Skip_MODRM }, 0  },
8578     { "rdpru",          { Skip_MODRM }, 0  },
8579     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8580     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8581   },
8582   {
8583     /* RM_0F1E_P_1_MOD_3_REG_7 */
8584     { "nopQ",           { Ev }, PREFIX_IGNORED },
8585     { "nopQ",           { Ev }, PREFIX_IGNORED },
8586     { "endbr64",        { Skip_MODRM }, 0 },
8587     { "endbr32",        { Skip_MODRM }, 0 },
8588     { "nopQ",           { Ev }, PREFIX_IGNORED },
8589     { "nopQ",           { Ev }, PREFIX_IGNORED },
8590     { "nopQ",           { Ev }, PREFIX_IGNORED },
8591     { "nopQ",           { Ev }, PREFIX_IGNORED },
8592   },
8593   {
8594     /* RM_0FAE_REG_6_MOD_3 */
8595     { "mfence",         { Skip_MODRM }, 0 },
8596   },
8597   {
8598     /* RM_0FAE_REG_7_MOD_3 */
8599     { "sfence",         { Skip_MODRM }, 0 },
8600   },
8601   {
8602     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8603     { "hreset",         { Skip_MODRM, Ib }, 0 },
8604   },
8605   {
8606     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8607     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8608   },
8609 };
8610
8611 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8612
8613 /* We use the high bit to indicate different name for the same
8614    prefix.  */
8615 #define REP_PREFIX      (0xf3 | 0x100)
8616 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8617 #define XRELEASE_PREFIX (0xf3 | 0x400)
8618 #define BND_PREFIX      (0xf2 | 0x400)
8619 #define NOTRACK_PREFIX  (0x3e | 0x100)
8620
8621 static int
8622 ckprefix (instr_info *ins)
8623 {
8624   int newrex, i, length;
8625   ins->rex = 0;
8626   ins->prefixes = 0;
8627   ins->used_prefixes = 0;
8628   ins->rex_used = 0;
8629   ins->evex_used = 0;
8630   ins->last_lock_prefix = -1;
8631   ins->last_repz_prefix = -1;
8632   ins->last_repnz_prefix = -1;
8633   ins->last_data_prefix = -1;
8634   ins->last_addr_prefix = -1;
8635   ins->last_rex_prefix = -1;
8636   ins->last_seg_prefix = -1;
8637   ins->fwait_prefix = -1;
8638   ins->active_seg_prefix = 0;
8639   for (i = 0; i < (int) ARRAY_SIZE (ins->all_prefixes); i++)
8640     ins->all_prefixes[i] = 0;
8641   i = 0;
8642   length = 0;
8643   /* The maximum instruction length is 15bytes.  */
8644   while (length < MAX_CODE_LENGTH - 1)
8645     {
8646       FETCH_DATA (ins->info, ins->codep + 1);
8647       newrex = 0;
8648       switch (*ins->codep)
8649         {
8650         /* REX prefixes family.  */
8651         case 0x40:
8652         case 0x41:
8653         case 0x42:
8654         case 0x43:
8655         case 0x44:
8656         case 0x45:
8657         case 0x46:
8658         case 0x47:
8659         case 0x48:
8660         case 0x49:
8661         case 0x4a:
8662         case 0x4b:
8663         case 0x4c:
8664         case 0x4d:
8665         case 0x4e:
8666         case 0x4f:
8667           if (ins->address_mode == mode_64bit)
8668             newrex = *ins->codep;
8669           else
8670             return 1;
8671           ins->last_rex_prefix = i;
8672           break;
8673         case 0xf3:
8674           ins->prefixes |= PREFIX_REPZ;
8675           ins->last_repz_prefix = i;
8676           break;
8677         case 0xf2:
8678           ins->prefixes |= PREFIX_REPNZ;
8679           ins->last_repnz_prefix = i;
8680           break;
8681         case 0xf0:
8682           ins->prefixes |= PREFIX_LOCK;
8683           ins->last_lock_prefix = i;
8684           break;
8685         case 0x2e:
8686           ins->prefixes |= PREFIX_CS;
8687           ins->last_seg_prefix = i;
8688           if (ins->address_mode != mode_64bit)
8689             ins->active_seg_prefix = PREFIX_CS;
8690           break;
8691         case 0x36:
8692           ins->prefixes |= PREFIX_SS;
8693           ins->last_seg_prefix = i;
8694           if (ins->address_mode != mode_64bit)
8695             ins->active_seg_prefix = PREFIX_SS;
8696           break;
8697         case 0x3e:
8698           ins->prefixes |= PREFIX_DS;
8699           ins->last_seg_prefix = i;
8700           if (ins->address_mode != mode_64bit)
8701             ins->active_seg_prefix = PREFIX_DS;
8702           break;
8703         case 0x26:
8704           ins->prefixes |= PREFIX_ES;
8705           ins->last_seg_prefix = i;
8706           if (ins->address_mode != mode_64bit)
8707             ins->active_seg_prefix = PREFIX_ES;
8708           break;
8709         case 0x64:
8710           ins->prefixes |= PREFIX_FS;
8711           ins->last_seg_prefix = i;
8712           ins->active_seg_prefix = PREFIX_FS;
8713           break;
8714         case 0x65:
8715           ins->prefixes |= PREFIX_GS;
8716           ins->last_seg_prefix = i;
8717           ins->active_seg_prefix = PREFIX_GS;
8718           break;
8719         case 0x66:
8720           ins->prefixes |= PREFIX_DATA;
8721           ins->last_data_prefix = i;
8722           break;
8723         case 0x67:
8724           ins->prefixes |= PREFIX_ADDR;
8725           ins->last_addr_prefix = i;
8726           break;
8727         case FWAIT_OPCODE:
8728           /* fwait is really an instruction.  If there are prefixes
8729              before the fwait, they belong to the fwait, *not* to the
8730              following instruction.  */
8731           ins->fwait_prefix = i;
8732           if (ins->prefixes || ins->rex)
8733             {
8734               ins->prefixes |= PREFIX_FWAIT;
8735               ins->codep++;
8736               /* This ensures that the previous REX prefixes are noticed
8737                  as unused prefixes, as in the return case below.  */
8738               ins->rex_used = ins->rex;
8739               return 1;
8740             }
8741           ins->prefixes = PREFIX_FWAIT;
8742           break;
8743         default:
8744           return 1;
8745         }
8746       /* Rex is ignored when followed by another prefix.  */
8747       if (ins->rex)
8748         {
8749           ins->rex_used = ins->rex;
8750           return 1;
8751         }
8752       if (*ins->codep != FWAIT_OPCODE)
8753         ins->all_prefixes[i++] = *ins->codep;
8754       ins->rex = newrex;
8755       ins->codep++;
8756       length++;
8757     }
8758   return 0;
8759 }
8760
8761 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8762    prefix byte.  */
8763
8764 static const char *
8765 prefix_name (instr_info *ins, int pref, int sizeflag)
8766 {
8767   static const char *rexes [16] =
8768     {
8769       "rex",            /* 0x40 */
8770       "rex.B",          /* 0x41 */
8771       "rex.X",          /* 0x42 */
8772       "rex.XB",         /* 0x43 */
8773       "rex.R",          /* 0x44 */
8774       "rex.RB",         /* 0x45 */
8775       "rex.RX",         /* 0x46 */
8776       "rex.RXB",        /* 0x47 */
8777       "rex.W",          /* 0x48 */
8778       "rex.WB",         /* 0x49 */
8779       "rex.WX",         /* 0x4a */
8780       "rex.WXB",        /* 0x4b */
8781       "rex.WR",         /* 0x4c */
8782       "rex.WRB",        /* 0x4d */
8783       "rex.WRX",        /* 0x4e */
8784       "rex.WRXB",       /* 0x4f */
8785     };
8786
8787   switch (pref)
8788     {
8789     /* REX prefixes family.  */
8790     case 0x40:
8791     case 0x41:
8792     case 0x42:
8793     case 0x43:
8794     case 0x44:
8795     case 0x45:
8796     case 0x46:
8797     case 0x47:
8798     case 0x48:
8799     case 0x49:
8800     case 0x4a:
8801     case 0x4b:
8802     case 0x4c:
8803     case 0x4d:
8804     case 0x4e:
8805     case 0x4f:
8806       return rexes [pref - 0x40];
8807     case 0xf3:
8808       return "repz";
8809     case 0xf2:
8810       return "repnz";
8811     case 0xf0:
8812       return "lock";
8813     case 0x2e:
8814       return "cs";
8815     case 0x36:
8816       return "ss";
8817     case 0x3e:
8818       return "ds";
8819     case 0x26:
8820       return "es";
8821     case 0x64:
8822       return "fs";
8823     case 0x65:
8824       return "gs";
8825     case 0x66:
8826       return (sizeflag & DFLAG) ? "data16" : "data32";
8827     case 0x67:
8828       if (ins->address_mode == mode_64bit)
8829         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8830       else
8831         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8832     case FWAIT_OPCODE:
8833       return "fwait";
8834     case REP_PREFIX:
8835       return "rep";
8836     case XACQUIRE_PREFIX:
8837       return "xacquire";
8838     case XRELEASE_PREFIX:
8839       return "xrelease";
8840     case BND_PREFIX:
8841       return "bnd";
8842     case NOTRACK_PREFIX:
8843       return "notrack";
8844     default:
8845       return NULL;
8846     }
8847 }
8848
8849 /* Here for backwards compatibility.  When gdb stops using
8850    print_insn_i386_att and print_insn_i386_intel these functions can
8851    disappear, and print_insn_i386 be merged into print_insn.  */
8852 int
8853 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
8854 {
8855   instr_info ins;
8856   ins.info = info;
8857   ins.intel_syntax = 0;
8858
8859   return print_insn (pc, &ins);
8860 }
8861
8862 int
8863 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
8864 {
8865   instr_info ins;
8866   ins.info = info;
8867   ins.intel_syntax = 1;
8868
8869   return print_insn (pc, &ins);
8870 }
8871
8872 int
8873 print_insn_i386 (bfd_vma pc, disassemble_info *info)
8874 {
8875   instr_info ins;
8876   ins.info = info;
8877   ins.intel_syntax = -1;
8878
8879   return print_insn (pc, &ins);
8880 }
8881
8882 void
8883 print_i386_disassembler_options (FILE *stream)
8884 {
8885   fprintf (stream, _("\n\
8886 The following i386/x86-64 specific disassembler options are supported for use\n\
8887 with the -M switch (multiple options should be separated by commas):\n"));
8888
8889   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8890   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8891   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8892   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8893   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8894   fprintf (stream, _("  att-mnemonic\n"
8895                      "              Display instruction in AT&T mnemonic\n"));
8896   fprintf (stream, _("  intel-mnemonic\n"
8897                      "              Display instruction in Intel mnemonic\n"));
8898   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8899   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8900   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8901   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8902   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8903   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8904   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8905   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8906 }
8907
8908 /* Bad opcode.  */
8909 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8910
8911 /* Get a pointer to struct dis386 with a valid name.  */
8912
8913 static const struct dis386 *
8914 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8915 {
8916   int vindex, vex_table_index;
8917
8918   if (dp->name != NULL)
8919     return dp;
8920
8921   switch (dp->op[0].bytemode)
8922     {
8923     case USE_REG_TABLE:
8924       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8925       break;
8926
8927     case USE_MOD_TABLE:
8928       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8929       dp = &mod_table[dp->op[1].bytemode][vindex];
8930       break;
8931
8932     case USE_RM_TABLE:
8933       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8934       break;
8935
8936     case USE_PREFIX_TABLE:
8937       if (ins->need_vex)
8938         {
8939           /* The prefix in VEX is implicit.  */
8940           switch (ins->vex.prefix)
8941             {
8942             case 0:
8943               vindex = 0;
8944               break;
8945             case REPE_PREFIX_OPCODE:
8946               vindex = 1;
8947               break;
8948             case DATA_PREFIX_OPCODE:
8949               vindex = 2;
8950               break;
8951             case REPNE_PREFIX_OPCODE:
8952               vindex = 3;
8953               break;
8954             default:
8955               abort ();
8956               break;
8957             }
8958         }
8959       else
8960         {
8961           int last_prefix = -1;
8962           int prefix = 0;
8963           vindex = 0;
8964           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8965              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8966              last one wins.  */
8967           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8968             {
8969               if (ins->last_repz_prefix > ins->last_repnz_prefix)
8970                 {
8971                   vindex = 1;
8972                   prefix = PREFIX_REPZ;
8973                   last_prefix = ins->last_repz_prefix;
8974                 }
8975               else
8976                 {
8977                   vindex = 3;
8978                   prefix = PREFIX_REPNZ;
8979                   last_prefix = ins->last_repnz_prefix;
8980                 }
8981
8982               /* Check if prefix should be ignored.  */
8983               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8984                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8985                    & prefix) != 0
8986                   && !prefix_table[dp->op[1].bytemode][vindex].name)
8987                 vindex = 0;
8988             }
8989
8990           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8991             {
8992               vindex = 2;
8993               prefix = PREFIX_DATA;
8994               last_prefix = ins->last_data_prefix;
8995             }
8996
8997           if (vindex != 0)
8998             {
8999               ins->used_prefixes |= prefix;
9000               ins->all_prefixes[last_prefix] = 0;
9001             }
9002         }
9003       dp = &prefix_table[dp->op[1].bytemode][vindex];
9004       break;
9005
9006     case USE_X86_64_TABLE:
9007       vindex = ins->address_mode == mode_64bit ? 1 : 0;
9008       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9009       break;
9010
9011     case USE_3BYTE_TABLE:
9012       FETCH_DATA (ins->info, ins->codep + 2);
9013       vindex = *ins->codep++;
9014       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9015       ins->end_codep = ins->codep;
9016       ins->modrm.mod = (*ins->codep >> 6) & 3;
9017       ins->modrm.reg = (*ins->codep >> 3) & 7;
9018       ins->modrm.rm = *ins->codep & 7;
9019       break;
9020
9021     case USE_VEX_LEN_TABLE:
9022       if (!ins->need_vex)
9023         abort ();
9024
9025       switch (ins->vex.length)
9026         {
9027         case 128:
9028           vindex = 0;
9029           break;
9030         case 512:
9031           /* This allows re-using in particular table entries where only
9032              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
9033           if (ins->vex.evex)
9034             {
9035         case 256:
9036               vindex = 1;
9037               break;
9038             }
9039         /* Fall through.  */
9040         default:
9041           abort ();
9042           break;
9043         }
9044
9045       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9046       break;
9047
9048     case USE_EVEX_LEN_TABLE:
9049       if (!ins->vex.evex)
9050         abort ();
9051
9052       switch (ins->vex.length)
9053         {
9054         case 128:
9055           vindex = 0;
9056           break;
9057         case 256:
9058           vindex = 1;
9059           break;
9060         case 512:
9061           vindex = 2;
9062           break;
9063         default:
9064           abort ();
9065           break;
9066         }
9067
9068       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9069       break;
9070
9071     case USE_XOP_8F_TABLE:
9072       FETCH_DATA (ins->info, ins->codep + 3);
9073       ins->rex = ~(*ins->codep >> 5) & 0x7;
9074
9075       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9076       switch ((*ins->codep & 0x1f))
9077         {
9078         default:
9079           dp = &bad_opcode;
9080           return dp;
9081         case 0x8:
9082           vex_table_index = XOP_08;
9083           break;
9084         case 0x9:
9085           vex_table_index = XOP_09;
9086           break;
9087         case 0xa:
9088           vex_table_index = XOP_0A;
9089           break;
9090         }
9091       ins->codep++;
9092       ins->vex.w = *ins->codep & 0x80;
9093       if (ins->vex.w && ins->address_mode == mode_64bit)
9094         ins->rex |= REX_W;
9095
9096       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9097       if (ins->address_mode != mode_64bit)
9098         {
9099           /* In 16/32-bit mode REX_B is silently ignored.  */
9100           ins->rex &= ~REX_B;
9101         }
9102
9103       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9104       switch ((*ins->codep & 0x3))
9105         {
9106         case 0:
9107           break;
9108         case 1:
9109           ins->vex.prefix = DATA_PREFIX_OPCODE;
9110           break;
9111         case 2:
9112           ins->vex.prefix = REPE_PREFIX_OPCODE;
9113           break;
9114         case 3:
9115           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9116           break;
9117         }
9118       ins->need_vex = 1;
9119       ins->codep++;
9120       vindex = *ins->codep++;
9121       dp = &xop_table[vex_table_index][vindex];
9122
9123       ins->end_codep = ins->codep;
9124       FETCH_DATA (ins->info, ins->codep + 1);
9125       ins->modrm.mod = (*ins->codep >> 6) & 3;
9126       ins->modrm.reg = (*ins->codep >> 3) & 7;
9127       ins->modrm.rm = *ins->codep & 7;
9128
9129       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9130          having to decode the bits for every otherwise valid encoding.  */
9131       if (ins->vex.prefix)
9132         return &bad_opcode;
9133       break;
9134
9135     case USE_VEX_C4_TABLE:
9136       /* VEX prefix.  */
9137       FETCH_DATA (ins->info, ins->codep + 3);
9138       ins->rex = ~(*ins->codep >> 5) & 0x7;
9139       switch ((*ins->codep & 0x1f))
9140         {
9141         default:
9142           dp = &bad_opcode;
9143           return dp;
9144         case 0x1:
9145           vex_table_index = VEX_0F;
9146           break;
9147         case 0x2:
9148           vex_table_index = VEX_0F38;
9149           break;
9150         case 0x3:
9151           vex_table_index = VEX_0F3A;
9152           break;
9153         }
9154       ins->codep++;
9155       ins->vex.w = *ins->codep & 0x80;
9156       if (ins->address_mode == mode_64bit)
9157         {
9158           if (ins->vex.w)
9159             ins->rex |= REX_W;
9160         }
9161       else
9162         {
9163           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9164              is ignored, other REX bits are 0 and the highest bit in
9165              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9166           ins->rex = 0;
9167         }
9168       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9169       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9170       switch ((*ins->codep & 0x3))
9171         {
9172         case 0:
9173           break;
9174         case 1:
9175           ins->vex.prefix = DATA_PREFIX_OPCODE;
9176           break;
9177         case 2:
9178           ins->vex.prefix = REPE_PREFIX_OPCODE;
9179           break;
9180         case 3:
9181           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9182           break;
9183         }
9184       ins->need_vex = 1;
9185       ins->codep++;
9186       vindex = *ins->codep++;
9187       dp = &vex_table[vex_table_index][vindex];
9188       ins->end_codep = ins->codep;
9189       /* There is no MODRM byte for VEX0F 77.  */
9190       if (vex_table_index != VEX_0F || vindex != 0x77)
9191         {
9192           FETCH_DATA (ins->info, ins->codep + 1);
9193           ins->modrm.mod = (*ins->codep >> 6) & 3;
9194           ins->modrm.reg = (*ins->codep >> 3) & 7;
9195           ins->modrm.rm = *ins->codep & 7;
9196         }
9197       break;
9198
9199     case USE_VEX_C5_TABLE:
9200       /* VEX prefix.  */
9201       FETCH_DATA (ins->info, ins->codep + 2);
9202       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9203
9204       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9205          VEX.vvvv is 1.  */
9206       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9207       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9208       switch ((*ins->codep & 0x3))
9209         {
9210         case 0:
9211           break;
9212         case 1:
9213           ins->vex.prefix = DATA_PREFIX_OPCODE;
9214           break;
9215         case 2:
9216           ins->vex.prefix = REPE_PREFIX_OPCODE;
9217           break;
9218         case 3:
9219           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9220           break;
9221         }
9222       ins->need_vex = 1;
9223       ins->codep++;
9224       vindex = *ins->codep++;
9225       dp = &vex_table[dp->op[1].bytemode][vindex];
9226       ins->end_codep = ins->codep;
9227       /* There is no MODRM byte for VEX 77.  */
9228       if (vindex != 0x77)
9229         {
9230           FETCH_DATA (ins->info, ins->codep + 1);
9231           ins->modrm.mod = (*ins->codep >> 6) & 3;
9232           ins->modrm.reg = (*ins->codep >> 3) & 7;
9233           ins->modrm.rm = *ins->codep & 7;
9234         }
9235       break;
9236
9237     case USE_VEX_W_TABLE:
9238       if (!ins->need_vex)
9239         abort ();
9240
9241       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w ? 1 : 0];
9242       break;
9243
9244     case USE_EVEX_TABLE:
9245       ins->two_source_ops = 0;
9246       /* EVEX prefix.  */
9247       ins->vex.evex = 1;
9248       FETCH_DATA (ins->info, ins->codep + 4);
9249       /* The first byte after 0x62.  */
9250       ins->rex = ~(*ins->codep >> 5) & 0x7;
9251       ins->vex.r = *ins->codep & 0x10;
9252       switch ((*ins->codep & 0xf))
9253         {
9254         default:
9255           return &bad_opcode;
9256         case 0x1:
9257           vex_table_index = EVEX_0F;
9258           break;
9259         case 0x2:
9260           vex_table_index = EVEX_0F38;
9261           break;
9262         case 0x3:
9263           vex_table_index = EVEX_0F3A;
9264           break;
9265         case 0x5:
9266           vex_table_index = EVEX_MAP5;
9267           break;
9268         case 0x6:
9269           vex_table_index = EVEX_MAP6;
9270           break;
9271         }
9272
9273       /* The second byte after 0x62.  */
9274       ins->codep++;
9275       ins->vex.w = *ins->codep & 0x80;
9276       if (ins->vex.w && ins->address_mode == mode_64bit)
9277         ins->rex |= REX_W;
9278
9279       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9280
9281       /* The U bit.  */
9282       if (!(*ins->codep & 0x4))
9283         return &bad_opcode;
9284
9285       switch ((*ins->codep & 0x3))
9286         {
9287         case 0:
9288           break;
9289         case 1:
9290           ins->vex.prefix = DATA_PREFIX_OPCODE;
9291           break;
9292         case 2:
9293           ins->vex.prefix = REPE_PREFIX_OPCODE;
9294           break;
9295         case 3:
9296           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9297           break;
9298         }
9299
9300       /* The third byte after 0x62.  */
9301       ins->codep++;
9302
9303       /* Remember the static rounding bits.  */
9304       ins->vex.ll = (*ins->codep >> 5) & 3;
9305       ins->vex.b = (*ins->codep & 0x10) != 0;
9306
9307       ins->vex.v = *ins->codep & 0x8;
9308       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9309       ins->vex.zeroing = *ins->codep & 0x80;
9310
9311       if (ins->address_mode != mode_64bit)
9312         {
9313           /* In 16/32-bit mode silently ignore following bits.  */
9314           ins->rex &= ~REX_B;
9315           ins->vex.r = 1;
9316         }
9317
9318       ins->need_vex = 1;
9319       ins->codep++;
9320       vindex = *ins->codep++;
9321       dp = &evex_table[vex_table_index][vindex];
9322       ins->end_codep = ins->codep;
9323       FETCH_DATA (ins->info, ins->codep + 1);
9324       ins->modrm.mod = (*ins->codep >> 6) & 3;
9325       ins->modrm.reg = (*ins->codep >> 3) & 7;
9326       ins->modrm.rm = *ins->codep & 7;
9327
9328       /* Set vector length.  */
9329       if (ins->modrm.mod == 3 && ins->vex.b)
9330         ins->vex.length = 512;
9331       else
9332         {
9333           switch (ins->vex.ll)
9334             {
9335             case 0x0:
9336               ins->vex.length = 128;
9337               break;
9338             case 0x1:
9339               ins->vex.length = 256;
9340               break;
9341             case 0x2:
9342               ins->vex.length = 512;
9343               break;
9344             default:
9345               return &bad_opcode;
9346             }
9347         }
9348       break;
9349
9350     case 0:
9351       dp = &bad_opcode;
9352       break;
9353
9354     default:
9355       abort ();
9356     }
9357
9358   if (dp->name != NULL)
9359     return dp;
9360   else
9361     return get_valid_dis386 (dp, ins);
9362 }
9363
9364 static void
9365 get_sib (instr_info *ins, int sizeflag)
9366 {
9367   /* If modrm.mod == 3, operand must be register.  */
9368   if (ins->need_modrm
9369       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9370       && ins->modrm.mod != 3
9371       && ins->modrm.rm == 4)
9372     {
9373       FETCH_DATA (ins->info, ins->codep + 2);
9374       ins->sib.index = (ins->codep[1] >> 3) & 7;
9375       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9376       ins->sib.base = ins->codep[1] & 7;
9377     }
9378 }
9379
9380 static int
9381 print_insn (bfd_vma pc, instr_info *ins)
9382 {
9383   const struct dis386 *dp;
9384   int i;
9385   char *op_txt[MAX_OPERANDS];
9386   int needcomma;
9387   int sizeflag, orig_sizeflag;
9388   const char *p;
9389   struct dis_private priv;
9390   int prefix_length;
9391
9392   ins->isa64 = 0;
9393   ins->intel_mnemonic = !SYSV386_COMPAT;
9394   ins->op_is_jump = false;
9395   priv.orig_sizeflag = AFLAG | DFLAG;
9396   if ((ins->info->mach & bfd_mach_i386_i386) != 0)
9397     ins->address_mode = mode_32bit;
9398   else if (ins->info->mach == bfd_mach_i386_i8086)
9399     {
9400       ins->address_mode = mode_16bit;
9401       priv.orig_sizeflag = 0;
9402     }
9403   else
9404     ins->address_mode = mode_64bit;
9405
9406   if (ins->intel_syntax == (char) -1)
9407     ins->intel_syntax = (ins->info->mach & bfd_mach_i386_intel_syntax) != 0;
9408
9409   for (p = ins->info->disassembler_options; p != NULL;)
9410     {
9411       if (startswith (p, "amd64"))
9412         ins->isa64 = amd64;
9413       else if (startswith (p, "intel64"))
9414         ins->isa64 = intel64;
9415       else if (startswith (p, "x86-64"))
9416         {
9417           ins->address_mode = mode_64bit;
9418           priv.orig_sizeflag |= AFLAG | DFLAG;
9419         }
9420       else if (startswith (p, "i386"))
9421         {
9422           ins->address_mode = mode_32bit;
9423           priv.orig_sizeflag |= AFLAG | DFLAG;
9424         }
9425       else if (startswith (p, "i8086"))
9426         {
9427           ins->address_mode = mode_16bit;
9428           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9429         }
9430       else if (startswith (p, "intel"))
9431         {
9432           ins->intel_syntax = 1;
9433           if (startswith (p + 5, "-mnemonic"))
9434             ins->intel_mnemonic = 1;
9435         }
9436       else if (startswith (p, "att"))
9437         {
9438           ins->intel_syntax = 0;
9439           if (startswith (p + 3, "-mnemonic"))
9440             ins->intel_mnemonic = 0;
9441         }
9442       else if (startswith (p, "addr"))
9443         {
9444           if (ins->address_mode == mode_64bit)
9445             {
9446               if (p[4] == '3' && p[5] == '2')
9447                 priv.orig_sizeflag &= ~AFLAG;
9448               else if (p[4] == '6' && p[5] == '4')
9449                 priv.orig_sizeflag |= AFLAG;
9450             }
9451           else
9452             {
9453               if (p[4] == '1' && p[5] == '6')
9454                 priv.orig_sizeflag &= ~AFLAG;
9455               else if (p[4] == '3' && p[5] == '2')
9456                 priv.orig_sizeflag |= AFLAG;
9457             }
9458         }
9459       else if (startswith (p, "data"))
9460         {
9461           if (p[4] == '1' && p[5] == '6')
9462             priv.orig_sizeflag &= ~DFLAG;
9463           else if (p[4] == '3' && p[5] == '2')
9464             priv.orig_sizeflag |= DFLAG;
9465         }
9466       else if (startswith (p, "suffix"))
9467         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9468
9469       p = strchr (p, ',');
9470       if (p != NULL)
9471         p++;
9472     }
9473
9474   if (ins->address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9475     {
9476       (*ins->info->fprintf_func) (ins->info->stream,
9477                              _("64-bit address is disabled"));
9478       return -1;
9479     }
9480
9481   if (ins->intel_syntax)
9482     {
9483       ins->names64 = intel_names64;
9484       ins->names32 = intel_names32;
9485       ins->names16 = intel_names16;
9486       ins->names8 = intel_names8;
9487       ins->names8rex = intel_names8rex;
9488       ins->names_seg = intel_names_seg;
9489       ins->names_mm = intel_names_mm;
9490       ins->names_bnd = intel_names_bnd;
9491       ins->names_xmm = intel_names_xmm;
9492       ins->names_ymm = intel_names_ymm;
9493       ins->names_zmm = intel_names_zmm;
9494       ins->names_tmm = intel_names_tmm;
9495       ins->index64 = intel_index64;
9496       ins->index32 = intel_index32;
9497       ins->names_mask = intel_names_mask;
9498       ins->index16 = intel_index16;
9499       ins->open_char = '[';
9500       ins->close_char = ']';
9501       ins->separator_char = '+';
9502       ins->scale_char = '*';
9503     }
9504   else
9505     {
9506       ins->names64 = att_names64;
9507       ins->names32 = att_names32;
9508       ins->names16 = att_names16;
9509       ins->names8 = att_names8;
9510       ins->names8rex = att_names8rex;
9511       ins->names_seg = att_names_seg;
9512       ins->names_mm = att_names_mm;
9513       ins->names_bnd = att_names_bnd;
9514       ins->names_xmm = att_names_xmm;
9515       ins->names_ymm = att_names_ymm;
9516       ins->names_zmm = att_names_zmm;
9517       ins->names_tmm = att_names_tmm;
9518       ins->index64 = att_index64;
9519       ins->index32 = att_index32;
9520       ins->names_mask = att_names_mask;
9521       ins->index16 = att_index16;
9522       ins->open_char = '(';
9523       ins->close_char =  ')';
9524       ins->separator_char = ',';
9525       ins->scale_char = ',';
9526     }
9527
9528   /* The output looks better if we put 7 bytes on a line, since that
9529      puts most long word instructions on a single line.  Use 8 bytes
9530      for Intel L1OM.  */
9531   if ((ins->info->mach & bfd_mach_l1om) != 0)
9532     ins->info->bytes_per_line = 8;
9533   else
9534     ins->info->bytes_per_line = 7;
9535
9536   ins->info->private_data = &priv;
9537   priv.max_fetched = priv.the_buffer;
9538   priv.insn_start = pc;
9539
9540   ins->obuf[0] = 0;
9541   for (i = 0; i < MAX_OPERANDS; ++i)
9542     {
9543       ins->op_out[i][0] = 0;
9544       ins->op_index[i] = -1;
9545     }
9546
9547   ins->start_pc = pc;
9548   ins->start_codep = priv.the_buffer;
9549   ins->codep = priv.the_buffer;
9550
9551   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9552     {
9553       const char *name;
9554
9555       /* Getting here means we tried for data but didn't get it.  That
9556          means we have an incomplete instruction of some sort.  Just
9557          print the first byte as a prefix or a .byte pseudo-op.  */
9558       if (ins->codep > priv.the_buffer)
9559         {
9560           name = prefix_name (ins, priv.the_buffer[0], priv.orig_sizeflag);
9561           if (name != NULL)
9562             (*ins->info->fprintf_func) (ins->info->stream, "%s", name);
9563           else
9564             {
9565               /* Just print the first byte as a .byte instruction.  */
9566               (*ins->info->fprintf_func) (ins->info->stream, ".byte 0x%x",
9567                                      (unsigned int) priv.the_buffer[0]);
9568             }
9569
9570           return 1;
9571         }
9572
9573       return -1;
9574     }
9575
9576   ins->obufp = ins->obuf;
9577   sizeflag = priv.orig_sizeflag;
9578
9579   if (!ckprefix (ins) || ins->rex_used)
9580     {
9581       /* Too many ins->prefixes or unused REX ins->prefixes.  */
9582       for (i = 0;
9583            i < (int) ARRAY_SIZE (ins->all_prefixes) && ins->all_prefixes[i];
9584            i++)
9585         (*ins->info->fprintf_func) (ins->info->stream, "%s%s",
9586                                i == 0 ? "" : " ",
9587                                prefix_name (ins, ins->all_prefixes[i],
9588                                             sizeflag));
9589       return i;
9590     }
9591
9592   ins->insn_codep = ins->codep;
9593
9594   FETCH_DATA (ins->info, ins->codep + 1);
9595   ins->two_source_ops = (*ins->codep == 0x62) || (*ins->codep == 0xc8);
9596
9597   if (((ins->prefixes & PREFIX_FWAIT)
9598        && ((*ins->codep < 0xd8) || (*ins->codep > 0xdf))))
9599     {
9600       /* Handle ins->prefixes before fwait.  */
9601       for (i = 0; i < ins->fwait_prefix && ins->all_prefixes[i];
9602            i++)
9603         (*ins->info->fprintf_func) (ins->info->stream, "%s ",
9604                                     prefix_name (ins, ins->all_prefixes[i],
9605                                                  sizeflag));
9606       (*ins->info->fprintf_func) (ins->info->stream, "fwait");
9607       return i + 1;
9608     }
9609
9610   if (*ins->codep == 0x0f)
9611     {
9612       unsigned char threebyte;
9613
9614       ins->codep++;
9615       FETCH_DATA (ins->info, ins->codep + 1);
9616       threebyte = *ins->codep;
9617       dp = &dis386_twobyte[threebyte];
9618       ins->need_modrm = twobyte_has_modrm[threebyte];
9619       ins->codep++;
9620     }
9621   else
9622     {
9623       dp = &dis386[*ins->codep];
9624       ins->need_modrm = onebyte_has_modrm[*ins->codep];
9625       ins->codep++;
9626     }
9627
9628   /* Save sizeflag for printing the extra ins->prefixes later before updating
9629      it for mnemonic and operand processing.  The prefix names depend
9630      only on the address mode.  */
9631   orig_sizeflag = sizeflag;
9632   if (ins->prefixes & PREFIX_ADDR)
9633     sizeflag ^= AFLAG;
9634   if ((ins->prefixes & PREFIX_DATA))
9635     sizeflag ^= DFLAG;
9636
9637   ins->end_codep = ins->codep;
9638   if (ins->need_modrm)
9639     {
9640       FETCH_DATA (ins->info, ins->codep + 1);
9641       ins->modrm.mod = (*ins->codep >> 6) & 3;
9642       ins->modrm.reg = (*ins->codep >> 3) & 7;
9643       ins->modrm.rm = *ins->codep & 7;
9644     }
9645   else
9646     memset (&ins->modrm, 0, sizeof (ins->modrm));
9647
9648   ins->need_vex = 0;
9649   memset (&ins->vex, 0, sizeof (ins->vex));
9650
9651   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9652     {
9653       get_sib (ins, sizeflag);
9654       dofloat (ins, sizeflag);
9655     }
9656   else
9657     {
9658       dp = get_valid_dis386 (dp, ins);
9659       if (dp != NULL && putop (ins, dp->name, sizeflag) == 0)
9660         {
9661           get_sib (ins, sizeflag);
9662           for (i = 0; i < MAX_OPERANDS; ++i)
9663             {
9664               ins->obufp = ins->op_out[i];
9665               ins->op_ad = MAX_OPERANDS - 1 - i;
9666               if (dp->op[i].rtn)
9667                 (*dp->op[i].rtn) (ins, dp->op[i].bytemode, sizeflag);
9668               /* For EVEX instruction after the last operand masking
9669                  should be printed.  */
9670               if (i == 0 && ins->vex.evex)
9671                 {
9672                   /* Don't print {%k0}.  */
9673                   if (ins->vex.mask_register_specifier)
9674                     {
9675                       oappend (ins, "{");
9676                       oappend (ins,
9677                              ins->names_mask[ins->vex.mask_register_specifier]);
9678                       oappend (ins, "}");
9679                     }
9680                   if (ins->vex.zeroing)
9681                     oappend (ins, "{z}");
9682
9683                   /* S/G insns require a mask and don't allow
9684                      zeroing-masking.  */
9685                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9686                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9687                       && (ins->vex.mask_register_specifier == 0
9688                           || ins->vex.zeroing))
9689                     oappend (ins, "/(bad)");
9690                 }
9691             }
9692
9693           /* Check whether rounding control was enabled for an insn not
9694              supporting it.  */
9695           if (ins->modrm.mod == 3 && ins->vex.b
9696               && !(ins->evex_used & EVEX_b_used))
9697             {
9698               for (i = 0; i < MAX_OPERANDS; ++i)
9699                 {
9700                   ins->obufp = ins->op_out[i];
9701                   if (*ins->obufp)
9702                     continue;
9703                   oappend (ins, names_rounding[ins->vex.ll]);
9704                   oappend (ins, "bad}");
9705                   break;
9706                 }
9707             }
9708         }
9709     }
9710
9711   /* Clear instruction information.  */
9712   ins->info->insn_info_valid = 0;
9713   ins->info->branch_delay_insns = 0;
9714   ins->info->data_size = 0;
9715   ins->info->insn_type = dis_noninsn;
9716   ins->info->target = 0;
9717   ins->info->target2 = 0;
9718
9719   /* Reset jump operation indicator.  */
9720   ins->op_is_jump = false;
9721   {
9722     int jump_detection = 0;
9723
9724     /* Extract flags.  */
9725     for (i = 0; i < MAX_OPERANDS; ++i)
9726       {
9727         if ((dp->op[i].rtn == OP_J)
9728             || (dp->op[i].rtn == OP_indirE))
9729           jump_detection |= 1;
9730         else if ((dp->op[i].rtn == BND_Fixup)
9731                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9732           jump_detection |= 2;
9733         else if ((dp->op[i].bytemode == cond_jump_mode)
9734                  || (dp->op[i].bytemode == loop_jcxz_mode))
9735           jump_detection |= 4;
9736       }
9737
9738     /* Determine if this is a jump or branch.  */
9739     if ((jump_detection & 0x3) == 0x3)
9740       {
9741         ins->op_is_jump = true;
9742         if (jump_detection & 0x4)
9743           ins->info->insn_type = dis_condbranch;
9744         else
9745           ins->info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9746             ? dis_jsr : dis_branch;
9747       }
9748   }
9749
9750   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9751      are all 0s in inverted form.  */
9752   if (ins->need_vex && ins->vex.register_specifier != 0)
9753     {
9754       (*ins->info->fprintf_func) (ins->info->stream, "(bad)");
9755       return ins->end_codep - priv.the_buffer;
9756     }
9757
9758   /* If EVEX.z is set, there must be an actual mask register in use.  */
9759   if (ins->vex.zeroing && ins->vex.mask_register_specifier == 0)
9760     {
9761       (*ins->info->fprintf_func) (ins->info->stream, "(bad)");
9762       return ins->end_codep - priv.the_buffer;
9763     }
9764
9765   switch (dp->prefix_requirement)
9766     {
9767     case PREFIX_DATA:
9768       /* If only the data prefix is marked as mandatory, its absence renders
9769          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9770       if (ins->need_vex ? !ins->vex.prefix : !(ins->prefixes & PREFIX_DATA))
9771         {
9772           (*ins->info->fprintf_func) (ins->info->stream, "(bad)");
9773           return ins->end_codep - priv.the_buffer;
9774         }
9775       ins->used_prefixes |= PREFIX_DATA;
9776       /* Fall through.  */
9777     case PREFIX_OPCODE:
9778       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9779          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9780          used by putop and MMX/SSE operand and may be overridden by the
9781          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9782          separately.  */
9783       if (((ins->need_vex
9784             ? ins->vex.prefix == REPE_PREFIX_OPCODE
9785               || ins->vex.prefix == REPNE_PREFIX_OPCODE
9786             : (ins->prefixes
9787                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9788            && (ins->used_prefixes
9789                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9790           || (((ins->need_vex
9791                 ? ins->vex.prefix == DATA_PREFIX_OPCODE
9792                 : ((ins->prefixes
9793                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9794                    == PREFIX_DATA))
9795                && (ins->used_prefixes & PREFIX_DATA) == 0))
9796           || (ins->vex.evex && dp->prefix_requirement != PREFIX_DATA
9797               && !ins->vex.w != !(ins->used_prefixes & PREFIX_DATA)))
9798         {
9799           (*ins->info->fprintf_func) (ins->info->stream, "(bad)");
9800           return ins->end_codep - priv.the_buffer;
9801         }
9802       break;
9803
9804     case PREFIX_IGNORED:
9805       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9806          origins in all_prefixes.  */
9807       ins->used_prefixes &= ~PREFIX_OPCODE;
9808       if (ins->last_data_prefix >= 0)
9809         ins->all_prefixes[ins->last_data_prefix] = 0x66;
9810       if (ins->last_repz_prefix >= 0)
9811         ins->all_prefixes[ins->last_repz_prefix] = 0xf3;
9812       if (ins->last_repnz_prefix >= 0)
9813         ins->all_prefixes[ins->last_repnz_prefix] = 0xf2;
9814       break;
9815     }
9816
9817   /* Check if the REX prefix is used.  */
9818   if ((ins->rex ^ ins->rex_used) == 0
9819       && !ins->need_vex && ins->last_rex_prefix >= 0)
9820     ins->all_prefixes[ins->last_rex_prefix] = 0;
9821
9822   /* Check if the SEG prefix is used.  */
9823   if ((ins->prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9824                    | PREFIX_FS | PREFIX_GS)) != 0
9825       && (ins->used_prefixes & ins->active_seg_prefix) != 0)
9826     ins->all_prefixes[ins->last_seg_prefix] = 0;
9827
9828   /* Check if the ADDR prefix is used.  */
9829   if ((ins->prefixes & PREFIX_ADDR) != 0
9830       && (ins->used_prefixes & PREFIX_ADDR) != 0)
9831     ins->all_prefixes[ins->last_addr_prefix] = 0;
9832
9833   /* Check if the DATA prefix is used.  */
9834   if ((ins->prefixes & PREFIX_DATA) != 0
9835       && (ins->used_prefixes & PREFIX_DATA) != 0
9836       && !ins->need_vex)
9837     ins->all_prefixes[ins->last_data_prefix] = 0;
9838
9839   /* Print the extra ins->prefixes.  */
9840   prefix_length = 0;
9841   for (i = 0; i < (int) ARRAY_SIZE (ins->all_prefixes); i++)
9842     if (ins->all_prefixes[i])
9843       {
9844         const char *name;
9845         name = prefix_name (ins, ins->all_prefixes[i], orig_sizeflag);
9846         if (name == NULL)
9847           abort ();
9848         prefix_length += strlen (name) + 1;
9849         (*ins->info->fprintf_func) (ins->info->stream, "%s ", name);
9850       }
9851
9852   /* Check maximum code length.  */
9853   if ((ins->codep - ins->start_codep) > MAX_CODE_LENGTH)
9854     {
9855       (*ins->info->fprintf_func) (ins->info->stream, "(bad)");
9856       return MAX_CODE_LENGTH;
9857     }
9858
9859   ins->obufp = ins->mnemonicendp;
9860   for (i = strlen (ins->obuf) + prefix_length; i < 6; i++)
9861     oappend (ins, " ");
9862   oappend (ins, " ");
9863   (*ins->info->fprintf_func) (ins->info->stream, "%s", ins->obuf);
9864
9865   /* The enter and bound instructions are printed with operands in the same
9866      order as the intel book; everything else is printed in reverse order.  */
9867   if (ins->intel_syntax || ins->two_source_ops)
9868     {
9869       bfd_vma riprel;
9870
9871       for (i = 0; i < MAX_OPERANDS; ++i)
9872         op_txt[i] = ins->op_out[i];
9873
9874       if (ins->intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9875           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9876         {
9877           op_txt[2] = ins->op_out[3];
9878           op_txt[3] = ins->op_out[2];
9879         }
9880
9881       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9882         {
9883           ins->op_ad = ins->op_index[i];
9884           ins->op_index[i] = ins->op_index[MAX_OPERANDS - 1 - i];
9885           ins->op_index[MAX_OPERANDS - 1 - i] = ins->op_ad;
9886           riprel = ins->op_riprel[i];
9887           ins->op_riprel[i] = ins->op_riprel[MAX_OPERANDS - 1 - i];
9888           ins->op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9889         }
9890     }
9891   else
9892     {
9893       for (i = 0; i < MAX_OPERANDS; ++i)
9894         op_txt[MAX_OPERANDS - 1 - i] = ins->op_out[i];
9895     }
9896
9897   needcomma = 0;
9898   for (i = 0; i < MAX_OPERANDS; ++i)
9899     if (*op_txt[i])
9900       {
9901         if (needcomma)
9902           (*ins->info->fprintf_func) (ins->info->stream, ",");
9903         if (ins->op_index[i] != -1 && !ins->op_riprel[i])
9904           {
9905             bfd_vma target = (bfd_vma) ins->op_address[ins->op_index[i]];
9906
9907             if (ins->op_is_jump)
9908               {
9909                 ins->info->insn_info_valid = 1;
9910                 ins->info->branch_delay_insns = 0;
9911                 ins->info->data_size = 0;
9912                 ins->info->target = target;
9913                 ins->info->target2 = 0;
9914               }
9915             (*ins->info->print_address_func) (target, ins->info);
9916           }
9917         else
9918           (*ins->info->fprintf_func) (ins->info->stream, "%s", op_txt[i]);
9919         needcomma = 1;
9920       }
9921
9922   for (i = 0; i < MAX_OPERANDS; i++)
9923     if (ins->op_index[i] != -1 && ins->op_riprel[i])
9924       {
9925         (*ins->info->fprintf_func) (ins->info->stream, "        # ");
9926         (*ins->info->print_address_func) ((bfd_vma)
9927                         (ins->start_pc + (ins->codep - ins->start_codep)
9928                          + ins->op_address[ins->op_index[i]]), ins->info);
9929         break;
9930       }
9931   return ins->codep - priv.the_buffer;
9932 }
9933
9934 static const char *float_mem[] = {
9935   /* d8 */
9936   "fadd{s|}",
9937   "fmul{s|}",
9938   "fcom{s|}",
9939   "fcomp{s|}",
9940   "fsub{s|}",
9941   "fsubr{s|}",
9942   "fdiv{s|}",
9943   "fdivr{s|}",
9944   /* d9 */
9945   "fld{s|}",
9946   "(bad)",
9947   "fst{s|}",
9948   "fstp{s|}",
9949   "fldenv{C|C}",
9950   "fldcw",
9951   "fNstenv{C|C}",
9952   "fNstcw",
9953   /* da */
9954   "fiadd{l|}",
9955   "fimul{l|}",
9956   "ficom{l|}",
9957   "ficomp{l|}",
9958   "fisub{l|}",
9959   "fisubr{l|}",
9960   "fidiv{l|}",
9961   "fidivr{l|}",
9962   /* db */
9963   "fild{l|}",
9964   "fisttp{l|}",
9965   "fist{l|}",
9966   "fistp{l|}",
9967   "(bad)",
9968   "fld{t|}",
9969   "(bad)",
9970   "fstp{t|}",
9971   /* dc */
9972   "fadd{l|}",
9973   "fmul{l|}",
9974   "fcom{l|}",
9975   "fcomp{l|}",
9976   "fsub{l|}",
9977   "fsubr{l|}",
9978   "fdiv{l|}",
9979   "fdivr{l|}",
9980   /* dd */
9981   "fld{l|}",
9982   "fisttp{ll|}",
9983   "fst{l||}",
9984   "fstp{l|}",
9985   "frstor{C|C}",
9986   "(bad)",
9987   "fNsave{C|C}",
9988   "fNstsw",
9989   /* de */
9990   "fiadd{s|}",
9991   "fimul{s|}",
9992   "ficom{s|}",
9993   "ficomp{s|}",
9994   "fisub{s|}",
9995   "fisubr{s|}",
9996   "fidiv{s|}",
9997   "fidivr{s|}",
9998   /* df */
9999   "fild{s|}",
10000   "fisttp{s|}",
10001   "fist{s|}",
10002   "fistp{s|}",
10003   "fbld",
10004   "fild{ll|}",
10005   "fbstp",
10006   "fistp{ll|}",
10007 };
10008
10009 static const unsigned char float_mem_mode[] = {
10010   /* d8 */
10011   d_mode,
10012   d_mode,
10013   d_mode,
10014   d_mode,
10015   d_mode,
10016   d_mode,
10017   d_mode,
10018   d_mode,
10019   /* d9 */
10020   d_mode,
10021   0,
10022   d_mode,
10023   d_mode,
10024   0,
10025   w_mode,
10026   0,
10027   w_mode,
10028   /* da */
10029   d_mode,
10030   d_mode,
10031   d_mode,
10032   d_mode,
10033   d_mode,
10034   d_mode,
10035   d_mode,
10036   d_mode,
10037   /* db */
10038   d_mode,
10039   d_mode,
10040   d_mode,
10041   d_mode,
10042   0,
10043   t_mode,
10044   0,
10045   t_mode,
10046   /* dc */
10047   q_mode,
10048   q_mode,
10049   q_mode,
10050   q_mode,
10051   q_mode,
10052   q_mode,
10053   q_mode,
10054   q_mode,
10055   /* dd */
10056   q_mode,
10057   q_mode,
10058   q_mode,
10059   q_mode,
10060   0,
10061   0,
10062   0,
10063   w_mode,
10064   /* de */
10065   w_mode,
10066   w_mode,
10067   w_mode,
10068   w_mode,
10069   w_mode,
10070   w_mode,
10071   w_mode,
10072   w_mode,
10073   /* df */
10074   w_mode,
10075   w_mode,
10076   w_mode,
10077   w_mode,
10078   t_mode,
10079   q_mode,
10080   t_mode,
10081   q_mode
10082 };
10083
10084 #define ST { OP_ST, 0 }
10085 #define STi { OP_STi, 0 }
10086
10087 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10088 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10089 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10090 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10091 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10092 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10093 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10094 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10095 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10096
10097 static const struct dis386 float_reg[][8] = {
10098   /* d8 */
10099   {
10100     { "fadd",   { ST, STi }, 0 },
10101     { "fmul",   { ST, STi }, 0 },
10102     { "fcom",   { STi }, 0 },
10103     { "fcomp",  { STi }, 0 },
10104     { "fsub",   { ST, STi }, 0 },
10105     { "fsubr",  { ST, STi }, 0 },
10106     { "fdiv",   { ST, STi }, 0 },
10107     { "fdivr",  { ST, STi }, 0 },
10108   },
10109   /* d9 */
10110   {
10111     { "fld",    { STi }, 0 },
10112     { "fxch",   { STi }, 0 },
10113     { FGRPd9_2 },
10114     { Bad_Opcode },
10115     { FGRPd9_4 },
10116     { FGRPd9_5 },
10117     { FGRPd9_6 },
10118     { FGRPd9_7 },
10119   },
10120   /* da */
10121   {
10122     { "fcmovb", { ST, STi }, 0 },
10123     { "fcmove", { ST, STi }, 0 },
10124     { "fcmovbe",{ ST, STi }, 0 },
10125     { "fcmovu", { ST, STi }, 0 },
10126     { Bad_Opcode },
10127     { FGRPda_5 },
10128     { Bad_Opcode },
10129     { Bad_Opcode },
10130   },
10131   /* db */
10132   {
10133     { "fcmovnb",{ ST, STi }, 0 },
10134     { "fcmovne",{ ST, STi }, 0 },
10135     { "fcmovnbe",{ ST, STi }, 0 },
10136     { "fcmovnu",{ ST, STi }, 0 },
10137     { FGRPdb_4 },
10138     { "fucomi", { ST, STi }, 0 },
10139     { "fcomi",  { ST, STi }, 0 },
10140     { Bad_Opcode },
10141   },
10142   /* dc */
10143   {
10144     { "fadd",   { STi, ST }, 0 },
10145     { "fmul",   { STi, ST }, 0 },
10146     { Bad_Opcode },
10147     { Bad_Opcode },
10148     { "fsub{!M|r}",     { STi, ST }, 0 },
10149     { "fsub{M|}",       { STi, ST }, 0 },
10150     { "fdiv{!M|r}",     { STi, ST }, 0 },
10151     { "fdiv{M|}",       { STi, ST }, 0 },
10152   },
10153   /* dd */
10154   {
10155     { "ffree",  { STi }, 0 },
10156     { Bad_Opcode },
10157     { "fst",    { STi }, 0 },
10158     { "fstp",   { STi }, 0 },
10159     { "fucom",  { STi }, 0 },
10160     { "fucomp", { STi }, 0 },
10161     { Bad_Opcode },
10162     { Bad_Opcode },
10163   },
10164   /* de */
10165   {
10166     { "faddp",  { STi, ST }, 0 },
10167     { "fmulp",  { STi, ST }, 0 },
10168     { Bad_Opcode },
10169     { FGRPde_3 },
10170     { "fsub{!M|r}p",    { STi, ST }, 0 },
10171     { "fsub{M|}p",      { STi, ST }, 0 },
10172     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10173     { "fdiv{M|}p",      { STi, ST }, 0 },
10174   },
10175   /* df */
10176   {
10177     { "ffreep", { STi }, 0 },
10178     { Bad_Opcode },
10179     { Bad_Opcode },
10180     { Bad_Opcode },
10181     { FGRPdf_4 },
10182     { "fucomip", { ST, STi }, 0 },
10183     { "fcomip", { ST, STi }, 0 },
10184     { Bad_Opcode },
10185   },
10186 };
10187
10188 static char *fgrps[][8] = {
10189   /* Bad opcode 0 */
10190   {
10191     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10192   },
10193
10194   /* d9_2  1 */
10195   {
10196     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10197   },
10198
10199   /* d9_4  2 */
10200   {
10201     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10202   },
10203
10204   /* d9_5  3 */
10205   {
10206     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10207   },
10208
10209   /* d9_6  4 */
10210   {
10211     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10212   },
10213
10214   /* d9_7  5 */
10215   {
10216     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10217   },
10218
10219   /* da_5  6 */
10220   {
10221     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10222   },
10223
10224   /* db_4  7 */
10225   {
10226     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10227     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10228   },
10229
10230   /* de_3  8 */
10231   {
10232     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10233   },
10234
10235   /* df_4  9 */
10236   {
10237     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10238   },
10239 };
10240
10241 static void
10242 swap_operand (instr_info *ins)
10243 {
10244   ins->mnemonicendp[0] = '.';
10245   ins->mnemonicendp[1] = 's';
10246   ins->mnemonicendp[2] = '\0';
10247   ins->mnemonicendp += 2;
10248 }
10249
10250 static void
10251 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10252                int sizeflag ATTRIBUTE_UNUSED)
10253 {
10254   /* Skip mod/rm byte.  */
10255   MODRM_CHECK;
10256   ins->codep++;
10257 }
10258
10259 static void
10260 dofloat (instr_info *ins, int sizeflag)
10261 {
10262   const struct dis386 *dp;
10263   unsigned char floatop;
10264
10265   floatop = ins->codep[-1];
10266
10267   if (ins->modrm.mod != 3)
10268     {
10269       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10270
10271       putop (ins, float_mem[fp_indx], sizeflag);
10272       ins->obufp = ins->op_out[0];
10273       ins->op_ad = 2;
10274       OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10275       return;
10276     }
10277   /* Skip mod/rm byte.  */
10278   MODRM_CHECK;
10279   ins->codep++;
10280
10281   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10282   if (dp->name == NULL)
10283     {
10284       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10285
10286       /* Instruction fnstsw is only one with strange arg.  */
10287       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10288         strcpy (ins->op_out[0], ins->names16[0]);
10289     }
10290   else
10291     {
10292       putop (ins, dp->name, sizeflag);
10293
10294       ins->obufp = ins->op_out[0];
10295       ins->op_ad = 2;
10296       if (dp->op[0].rtn)
10297         (*dp->op[0].rtn) (ins, dp->op[0].bytemode, sizeflag);
10298
10299       ins->obufp = ins->op_out[1];
10300       ins->op_ad = 1;
10301       if (dp->op[1].rtn)
10302         (*dp->op[1].rtn) (ins, dp->op[1].bytemode, sizeflag);
10303     }
10304 }
10305
10306 /* Like oappend (below), but S is a string starting with '%'.
10307    In Intel syntax, the '%' is elided.  */
10308 static void
10309 oappend_maybe_intel (instr_info *ins, const char *s)
10310 {
10311   oappend (ins, s + ins->intel_syntax);
10312 }
10313
10314 static void
10315 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10316        int sizeflag ATTRIBUTE_UNUSED)
10317 {
10318   oappend_maybe_intel (ins, "%st");
10319 }
10320
10321 static void
10322 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10323         int sizeflag ATTRIBUTE_UNUSED)
10324 {
10325   sprintf (ins->scratchbuf, "%%st(%d)", ins->modrm.rm);
10326   oappend_maybe_intel (ins, ins->scratchbuf);
10327 }
10328
10329 /* Capital letters in template are macros.  */
10330 static int
10331 putop (instr_info *ins, const char *in_template, int sizeflag)
10332 {
10333   const char *p;
10334   int alt = 0;
10335   int cond = 1;
10336   unsigned int l = 0, len = 0;
10337   char last[4];
10338
10339   for (p = in_template; *p; p++)
10340     {
10341       if (len > l)
10342         {
10343           if (l >= sizeof (last) || !ISUPPER (*p))
10344             abort ();
10345           last[l++] = *p;
10346           continue;
10347         }
10348       switch (*p)
10349         {
10350         default:
10351           *ins->obufp++ = *p;
10352           break;
10353         case '%':
10354           len++;
10355           break;
10356         case '!':
10357           cond = 0;
10358           break;
10359         case '{':
10360           if (ins->intel_syntax)
10361             {
10362               while (*++p != '|')
10363                 if (*p == '}' || *p == '\0')
10364                   abort ();
10365               alt = 1;
10366             }
10367           break;
10368         case '|':
10369           while (*++p != '}')
10370             {
10371               if (*p == '\0')
10372                 abort ();
10373             }
10374           break;
10375         case '}':
10376           alt = 0;
10377           break;
10378         case 'A':
10379           if (ins->intel_syntax)
10380             break;
10381           if ((ins->need_modrm && ins->modrm.mod != 3)
10382               || (sizeflag & SUFFIX_ALWAYS))
10383             *ins->obufp++ = 'b';
10384           break;
10385         case 'B':
10386           if (l == 0)
10387             {
10388             case_B:
10389               if (ins->intel_syntax)
10390                 break;
10391               if (sizeflag & SUFFIX_ALWAYS)
10392                 *ins->obufp++ = 'b';
10393             }
10394           else if (l == 1 && last[0] == 'L')
10395             {
10396               if (ins->address_mode == mode_64bit
10397                   && !(ins->prefixes & PREFIX_ADDR))
10398                 {
10399                   *ins->obufp++ = 'a';
10400                   *ins->obufp++ = 'b';
10401                   *ins->obufp++ = 's';
10402                 }
10403
10404               goto case_B;
10405             }
10406           else
10407             abort ();
10408           break;
10409         case 'C':
10410           if (ins->intel_syntax && !alt)
10411             break;
10412           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10413             {
10414               if (sizeflag & DFLAG)
10415                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10416               else
10417                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10418               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10419             }
10420           break;
10421         case 'D':
10422           if (l == 1)
10423             {
10424               switch (last[0])
10425               {
10426               case 'X':
10427                 if (!ins->vex.evex || ins->vex.w)
10428                   *ins->obufp++ = 'd';
10429                 else
10430                   oappend (ins, "{bad}");
10431                 break;
10432               default:
10433                 abort ();
10434               }
10435               break;
10436             }
10437           if (l)
10438             abort ();
10439           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10440             break;
10441           USED_REX (REX_W);
10442           if (ins->modrm.mod == 3)
10443             {
10444               if (ins->rex & REX_W)
10445                 *ins->obufp++ = 'q';
10446               else
10447                 {
10448                   if (sizeflag & DFLAG)
10449                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10450                   else
10451                     *ins->obufp++ = 'w';
10452                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10453                 }
10454             }
10455           else
10456             *ins->obufp++ = 'w';
10457           break;
10458         case 'E':               /* For jcxz/jecxz */
10459           if (ins->address_mode == mode_64bit)
10460             {
10461               if (sizeflag & AFLAG)
10462                 *ins->obufp++ = 'r';
10463               else
10464                 *ins->obufp++ = 'e';
10465             }
10466           else
10467             if (sizeflag & AFLAG)
10468               *ins->obufp++ = 'e';
10469           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10470           break;
10471         case 'F':
10472           if (ins->intel_syntax)
10473             break;
10474           if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10475             {
10476               if (sizeflag & AFLAG)
10477                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10478               else
10479                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10480               ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10481             }
10482           break;
10483         case 'G':
10484           if (ins->intel_syntax || (ins->obufp[-1] != 's'
10485                                     && !(sizeflag & SUFFIX_ALWAYS)))
10486             break;
10487           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10488             *ins->obufp++ = 'l';
10489           else
10490             *ins->obufp++ = 'w';
10491           if (!(ins->rex & REX_W))
10492             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10493           break;
10494         case 'H':
10495           if (l == 0)
10496             {
10497               if (ins->intel_syntax)
10498                 break;
10499               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10500                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10501                 {
10502                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10503                   *ins->obufp++ = ',';
10504                   *ins->obufp++ = 'p';
10505
10506                   /* Set active_seg_prefix even if not set in 64-bit mode
10507                      because here it is a valid branch hint. */
10508                   if (ins->prefixes & PREFIX_DS)
10509                     {
10510                       ins->active_seg_prefix = PREFIX_DS;
10511                       *ins->obufp++ = 't';
10512                     }
10513                   else
10514                     {
10515                       ins->active_seg_prefix = PREFIX_CS;
10516                       *ins->obufp++ = 'n';
10517                     }
10518                 }
10519             }
10520           else if (l == 1 && last[0] == 'X')
10521             {
10522               if (ins->vex.w == 0)
10523                 *ins->obufp++ = 'h';
10524               else
10525                 oappend (ins, "{bad}");
10526             }
10527           else
10528             abort ();
10529           break;
10530         case 'K':
10531           USED_REX (REX_W);
10532           if (ins->rex & REX_W)
10533             *ins->obufp++ = 'q';
10534           else
10535             *ins->obufp++ = 'd';
10536           break;
10537         case 'L':
10538           abort ();
10539         case 'M':
10540           if (ins->intel_mnemonic != cond)
10541             *ins->obufp++ = 'r';
10542           break;
10543         case 'N':
10544           if ((ins->prefixes & PREFIX_FWAIT) == 0)
10545             *ins->obufp++ = 'n';
10546           else
10547             ins->used_prefixes |= PREFIX_FWAIT;
10548           break;
10549         case 'O':
10550           USED_REX (REX_W);
10551           if (ins->rex & REX_W)
10552             *ins->obufp++ = 'o';
10553           else if (ins->intel_syntax && (sizeflag & DFLAG))
10554             *ins->obufp++ = 'q';
10555           else
10556             *ins->obufp++ = 'd';
10557           if (!(ins->rex & REX_W))
10558             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10559           break;
10560         case '@':
10561           if (ins->address_mode == mode_64bit
10562               && (ins->isa64 == intel64 || (ins->rex & REX_W)
10563                   || !(ins->prefixes & PREFIX_DATA)))
10564             {
10565               if (sizeflag & SUFFIX_ALWAYS)
10566                 *ins->obufp++ = 'q';
10567               break;
10568             }
10569           /* Fall through.  */
10570         case 'P':
10571           if (l == 0)
10572             {
10573               if ((ins->modrm.mod == 3 || !cond)
10574                   && !(sizeflag & SUFFIX_ALWAYS))
10575                 break;
10576           /* Fall through.  */
10577         case 'T':
10578               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10579                   || ((sizeflag & SUFFIX_ALWAYS)
10580                       && ins->address_mode != mode_64bit))
10581                 {
10582                   *ins->obufp++ = (sizeflag & DFLAG)
10583                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
10584                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10585                 }
10586               else if (sizeflag & SUFFIX_ALWAYS)
10587                 *ins->obufp++ = 'q';
10588             }
10589           else if (l == 1 && last[0] == 'L')
10590             {
10591               if ((ins->prefixes & PREFIX_DATA)
10592                   || (ins->rex & REX_W)
10593                   || (sizeflag & SUFFIX_ALWAYS))
10594                 {
10595                   USED_REX (REX_W);
10596                   if (ins->rex & REX_W)
10597                     *ins->obufp++ = 'q';
10598                   else
10599                     {
10600                       if (sizeflag & DFLAG)
10601                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10602                       else
10603                         *ins->obufp++ = 'w';
10604                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10605                     }
10606                 }
10607             }
10608           else
10609             abort ();
10610           break;
10611         case 'Q':
10612           if (l == 0)
10613             {
10614               if (ins->intel_syntax && !alt)
10615                 break;
10616               USED_REX (REX_W);
10617               if ((ins->need_modrm && ins->modrm.mod != 3)
10618                   || (sizeflag & SUFFIX_ALWAYS))
10619                 {
10620                   if (ins->rex & REX_W)
10621                     *ins->obufp++ = 'q';
10622                   else
10623                     {
10624                       if (sizeflag & DFLAG)
10625                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10626                       else
10627                         *ins->obufp++ = 'w';
10628                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10629                     }
10630                 }
10631             }
10632           else if (l == 1 && last[0] == 'D')
10633             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10634           else if (l == 1 && last[0] == 'L')
10635             {
10636               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10637                        : ins->address_mode != mode_64bit)
10638                 break;
10639               if ((ins->rex & REX_W))
10640                 {
10641                   USED_REX (REX_W);
10642                   *ins->obufp++ = 'q';
10643                 }
10644               else if ((ins->address_mode == mode_64bit && cond)
10645                       || (sizeflag & SUFFIX_ALWAYS))
10646                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10647             }
10648           else
10649             abort ();
10650           break;
10651         case 'R':
10652           USED_REX (REX_W);
10653           if (ins->rex & REX_W)
10654             *ins->obufp++ = 'q';
10655           else if (sizeflag & DFLAG)
10656             {
10657               if (ins->intel_syntax)
10658                   *ins->obufp++ = 'd';
10659               else
10660                   *ins->obufp++ = 'l';
10661             }
10662           else
10663             *ins->obufp++ = 'w';
10664           if (ins->intel_syntax && !p[1]
10665               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10666             *ins->obufp++ = 'e';
10667           if (!(ins->rex & REX_W))
10668             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10669           break;
10670         case 'S':
10671           if (l == 0)
10672             {
10673             case_S:
10674               if (ins->intel_syntax)
10675                 break;
10676               if (sizeflag & SUFFIX_ALWAYS)
10677                 {
10678                   if (ins->rex & REX_W)
10679                     *ins->obufp++ = 'q';
10680                   else
10681                     {
10682                       if (sizeflag & DFLAG)
10683                         *ins->obufp++ = 'l';
10684                       else
10685                         *ins->obufp++ = 'w';
10686                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10687                     }
10688                 }
10689               break;
10690             }
10691           if (l != 1)
10692             abort ();
10693           switch (last[0])
10694             {
10695             case 'L':
10696               if (ins->address_mode == mode_64bit
10697                   && !(ins->prefixes & PREFIX_ADDR))
10698                 {
10699                   *ins->obufp++ = 'a';
10700                   *ins->obufp++ = 'b';
10701                   *ins->obufp++ = 's';
10702                 }
10703
10704               goto case_S;
10705             case 'X':
10706               if (!ins->vex.evex || !ins->vex.w)
10707                 *ins->obufp++ = 's';
10708               else
10709                 oappend (ins, "{bad}");
10710               break;
10711             default:
10712               abort ();
10713             }
10714           break;
10715         case 'V':
10716           if (l == 0)
10717             abort ();
10718           else if (l == 1
10719                    && (last[0] == 'L' || last[0] == 'X'))
10720             {
10721               if (last[0] == 'X')
10722                 {
10723                   *ins->obufp++ = '{';
10724                   *ins->obufp++ = 'v';
10725                   *ins->obufp++ = 'e';
10726                   *ins->obufp++ = 'x';
10727                   *ins->obufp++ = '}';
10728                 }
10729               else if (ins->rex & REX_W)
10730                 {
10731                   *ins->obufp++ = 'a';
10732                   *ins->obufp++ = 'b';
10733                   *ins->obufp++ = 's';
10734                 }
10735             }
10736           else
10737             abort ();
10738           goto case_S;
10739         case 'W':
10740           if (l == 0)
10741             {
10742               /* operand size flag for cwtl, cbtw */
10743               USED_REX (REX_W);
10744               if (ins->rex & REX_W)
10745                 {
10746                   if (ins->intel_syntax)
10747                     *ins->obufp++ = 'd';
10748                   else
10749                     *ins->obufp++ = 'l';
10750                 }
10751               else if (sizeflag & DFLAG)
10752                 *ins->obufp++ = 'w';
10753               else
10754                 *ins->obufp++ = 'b';
10755               if (!(ins->rex & REX_W))
10756                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10757             }
10758           else if (l == 1)
10759             {
10760               if (!ins->need_vex)
10761                 abort ();
10762               if (last[0] == 'X')
10763                 *ins->obufp++ = ins->vex.w ? 'd': 's';
10764               else if (last[0] == 'B')
10765                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10766               else
10767                 abort ();
10768             }
10769           else
10770             abort ();
10771           break;
10772         case 'X':
10773           if (l != 0)
10774             abort ();
10775           if (ins->need_vex
10776               ? ins->vex.prefix == DATA_PREFIX_OPCODE
10777               : ins->prefixes & PREFIX_DATA)
10778             {
10779               *ins->obufp++ = 'd';
10780               ins->used_prefixes |= PREFIX_DATA;
10781             }
10782           else
10783             *ins->obufp++ = 's';
10784           break;
10785         case 'Y':
10786           if (l == 1 && last[0] == 'X')
10787             {
10788               if (!ins->need_vex)
10789                 abort ();
10790               if (ins->intel_syntax
10791                   || ((ins->modrm.mod == 3 || ins->vex.b)
10792                       && !(sizeflag & SUFFIX_ALWAYS)))
10793                 break;
10794               switch (ins->vex.length)
10795                 {
10796                 case 128:
10797                   *ins->obufp++ = 'x';
10798                   break;
10799                 case 256:
10800                   *ins->obufp++ = 'y';
10801                   break;
10802                 case 512:
10803                   if (!ins->vex.evex)
10804                 default:
10805                     abort ();
10806                 }
10807             }
10808           else
10809             abort ();
10810           break;
10811         case 'Z':
10812           if (l == 0)
10813             {
10814               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10815               ins->modrm.mod = 3;
10816               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10817                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10818             }
10819           else if (l == 1 && last[0] == 'X')
10820             {
10821               if (!ins->vex.evex)
10822                 abort ();
10823               if (ins->intel_syntax
10824                   || ((ins->modrm.mod == 3 || ins->vex.b)
10825                       && !(sizeflag & SUFFIX_ALWAYS)))
10826                 break;
10827               switch (ins->vex.length)
10828                 {
10829                 case 128:
10830                   *ins->obufp++ = 'x';
10831                   break;
10832                 case 256:
10833                   *ins->obufp++ = 'y';
10834                   break;
10835                 case 512:
10836                   *ins->obufp++ = 'z';
10837                   break;
10838                 default:
10839                   abort ();
10840                 }
10841             }
10842           else
10843             abort ();
10844           break;
10845         case '^':
10846           if (ins->intel_syntax)
10847             break;
10848           if (ins->isa64 == intel64 && (ins->rex & REX_W))
10849             {
10850               USED_REX (REX_W);
10851               *ins->obufp++ = 'q';
10852               break;
10853             }
10854           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10855             {
10856               if (sizeflag & DFLAG)
10857                 *ins->obufp++ = 'l';
10858               else
10859                 *ins->obufp++ = 'w';
10860               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10861             }
10862           break;
10863         }
10864
10865       if (len == l)
10866         len = l = 0;
10867     }
10868   *ins->obufp = 0;
10869   ins->mnemonicendp = ins->obufp;
10870   return 0;
10871 }
10872
10873 static void
10874 oappend (instr_info *ins, const char *s)
10875 {
10876   ins->obufp = stpcpy (ins->obufp, s);
10877 }
10878
10879 static void
10880 append_seg (instr_info *ins)
10881 {
10882   /* Only print the active segment register.  */
10883   if (!ins->active_seg_prefix)
10884     return;
10885
10886   ins->used_prefixes |= ins->active_seg_prefix;
10887   switch (ins->active_seg_prefix)
10888     {
10889     case PREFIX_CS:
10890       oappend_maybe_intel (ins, "%cs:");
10891       break;
10892     case PREFIX_DS:
10893       oappend_maybe_intel (ins, "%ds:");
10894       break;
10895     case PREFIX_SS:
10896       oappend_maybe_intel (ins, "%ss:");
10897       break;
10898     case PREFIX_ES:
10899       oappend_maybe_intel (ins, "%es:");
10900       break;
10901     case PREFIX_FS:
10902       oappend_maybe_intel (ins, "%fs:");
10903       break;
10904     case PREFIX_GS:
10905       oappend_maybe_intel (ins, "%gs:");
10906       break;
10907     default:
10908       break;
10909     }
10910 }
10911
10912 static void
10913 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
10914 {
10915   if (!ins->intel_syntax)
10916     oappend (ins, "*");
10917   OP_E (ins, bytemode, sizeflag);
10918 }
10919
10920 static void
10921 print_operand_value (instr_info *ins, char *buf, int hex, bfd_vma disp)
10922 {
10923   if (ins->address_mode == mode_64bit)
10924     {
10925       if (hex)
10926         {
10927           char tmp[30];
10928           int i;
10929           buf[0] = '0';
10930           buf[1] = 'x';
10931           sprintf_vma (tmp, disp);
10932           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10933           strcpy (buf + 2, tmp + i);
10934         }
10935       else
10936         {
10937           bfd_signed_vma v = disp;
10938           char tmp[30];
10939           int i;
10940           if (v < 0)
10941             {
10942               *(buf++) = '-';
10943               v = -disp;
10944               /* Check for possible overflow on 0x8000000000000000.  */
10945               if (v < 0)
10946                 {
10947                   strcpy (buf, "9223372036854775808");
10948                   return;
10949                 }
10950             }
10951           if (!v)
10952             {
10953               strcpy (buf, "0");
10954               return;
10955             }
10956
10957           i = 0;
10958           tmp[29] = 0;
10959           while (v)
10960             {
10961               tmp[28 - i] = (v % 10) + '0';
10962               v /= 10;
10963               i++;
10964             }
10965           strcpy (buf, tmp + 29 - i);
10966         }
10967     }
10968   else
10969     {
10970       if (hex)
10971         sprintf (buf, "0x%x", (unsigned int) disp);
10972       else
10973         sprintf (buf, "%d", (int) disp);
10974     }
10975 }
10976
10977 /* Put DISP in BUF as signed hex number.  */
10978
10979 static void
10980 print_displacement (instr_info *ins, char *buf, bfd_vma disp)
10981 {
10982   bfd_signed_vma val = disp;
10983   char tmp[30];
10984   int i, j = 0;
10985
10986   if (val < 0)
10987     {
10988       buf[j++] = '-';
10989       val = -disp;
10990
10991       /* Check for possible overflow.  */
10992       if (val < 0)
10993         {
10994           switch (ins->address_mode)
10995             {
10996             case mode_64bit:
10997               strcpy (buf + j, "0x8000000000000000");
10998               break;
10999             case mode_32bit:
11000               strcpy (buf + j, "0x80000000");
11001               break;
11002             case mode_16bit:
11003               strcpy (buf + j, "0x8000");
11004               break;
11005             }
11006           return;
11007         }
11008     }
11009
11010   buf[j++] = '0';
11011   buf[j++] = 'x';
11012
11013   sprintf_vma (tmp, (bfd_vma) val);
11014   for (i = 0; tmp[i] == '0'; i++)
11015     continue;
11016   if (tmp[i] == '\0')
11017     i--;
11018   strcpy (buf + j, tmp + i);
11019 }
11020
11021 static void
11022 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11023 {
11024   if (ins->vex.b)
11025     {
11026       if (!ins->vex.no_broadcast)
11027         switch (bytemode)
11028           {
11029           case x_mode:
11030           case evex_half_bcst_xmmq_mode:
11031             if (ins->vex.w)
11032               oappend (ins, "QWORD PTR ");
11033             else
11034               oappend (ins, "DWORD PTR ");
11035             break;
11036           case xh_mode:
11037           case evex_half_bcst_xmmqh_mode:
11038           case evex_half_bcst_xmmqdh_mode:
11039             oappend (ins, "WORD PTR ");
11040             break;
11041           default:
11042             ins->vex.no_broadcast = 1;
11043             break;
11044           }
11045       return;
11046     }
11047   switch (bytemode)
11048     {
11049     case b_mode:
11050     case b_swap_mode:
11051     case db_mode:
11052       oappend (ins, "BYTE PTR ");
11053       break;
11054     case w_mode:
11055     case w_swap_mode:
11056     case dw_mode:
11057       oappend (ins, "WORD PTR ");
11058       break;
11059     case indir_v_mode:
11060       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11061         {
11062           oappend (ins, "QWORD PTR ");
11063           break;
11064         }
11065       /* Fall through.  */
11066     case stack_v_mode:
11067       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11068                                               || (ins->rex & REX_W)))
11069         {
11070           oappend (ins, "QWORD PTR ");
11071           break;
11072         }
11073       /* Fall through.  */
11074     case v_mode:
11075     case v_swap_mode:
11076     case dq_mode:
11077       USED_REX (REX_W);
11078       if (ins->rex & REX_W)
11079         oappend (ins, "QWORD PTR ");
11080       else if (bytemode == dq_mode)
11081         oappend (ins, "DWORD PTR ");
11082       else
11083         {
11084           if (sizeflag & DFLAG)
11085             oappend (ins, "DWORD PTR ");
11086           else
11087             oappend (ins, "WORD PTR ");
11088           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11089         }
11090       break;
11091     case z_mode:
11092       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11093         *ins->obufp++ = 'D';
11094       oappend (ins, "WORD PTR ");
11095       if (!(ins->rex & REX_W))
11096         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11097       break;
11098     case a_mode:
11099       if (sizeflag & DFLAG)
11100         oappend (ins, "QWORD PTR ");
11101       else
11102         oappend (ins, "DWORD PTR ");
11103       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11104       break;
11105     case movsxd_mode:
11106       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11107         oappend (ins, "WORD PTR ");
11108       else
11109         oappend (ins, "DWORD PTR ");
11110       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11111       break;
11112     case d_mode:
11113     case d_swap_mode:
11114       oappend (ins, "DWORD PTR ");
11115       break;
11116     case q_mode:
11117     case q_swap_mode:
11118       oappend (ins, "QWORD PTR ");
11119       break;
11120     case m_mode:
11121       if (ins->address_mode == mode_64bit)
11122         oappend (ins, "QWORD PTR ");
11123       else
11124         oappend (ins, "DWORD PTR ");
11125       break;
11126     case f_mode:
11127       if (sizeflag & DFLAG)
11128         oappend (ins, "FWORD PTR ");
11129       else
11130         oappend (ins, "DWORD PTR ");
11131       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11132       break;
11133     case t_mode:
11134       oappend (ins, "TBYTE PTR ");
11135       break;
11136     case x_mode:
11137     case xh_mode:
11138     case x_swap_mode:
11139     case evex_x_gscat_mode:
11140     case evex_x_nobcst_mode:
11141     case bw_unit_mode:
11142       if (ins->need_vex)
11143         {
11144           switch (ins->vex.length)
11145             {
11146             case 128:
11147               oappend (ins, "XMMWORD PTR ");
11148               break;
11149             case 256:
11150               oappend (ins, "YMMWORD PTR ");
11151               break;
11152             case 512:
11153               oappend (ins, "ZMMWORD PTR ");
11154               break;
11155             default:
11156               abort ();
11157             }
11158         }
11159       else
11160         oappend (ins, "XMMWORD PTR ");
11161       break;
11162     case xmm_mode:
11163       oappend (ins, "XMMWORD PTR ");
11164       break;
11165     case ymm_mode:
11166       oappend (ins, "YMMWORD PTR ");
11167       break;
11168     case xmmq_mode:
11169     case evex_half_bcst_xmmqh_mode:
11170     case evex_half_bcst_xmmq_mode:
11171       if (!ins->need_vex)
11172         abort ();
11173
11174       switch (ins->vex.length)
11175         {
11176         case 128:
11177           oappend (ins, "QWORD PTR ");
11178           break;
11179         case 256:
11180           oappend (ins, "XMMWORD PTR ");
11181           break;
11182         case 512:
11183           oappend (ins, "YMMWORD PTR ");
11184           break;
11185         default:
11186           abort ();
11187         }
11188       break;
11189     case xmmdw_mode:
11190       if (!ins->need_vex)
11191         abort ();
11192
11193       switch (ins->vex.length)
11194         {
11195         case 128:
11196           oappend (ins, "WORD PTR ");
11197           break;
11198         case 256:
11199           oappend (ins, "DWORD PTR ");
11200           break;
11201         case 512:
11202           oappend (ins, "QWORD PTR ");
11203           break;
11204         default:
11205           abort ();
11206         }
11207       break;
11208     case xmmqd_mode:
11209     case evex_half_bcst_xmmqdh_mode:
11210       if (!ins->need_vex)
11211         abort ();
11212
11213       switch (ins->vex.length)
11214         {
11215         case 128:
11216           oappend (ins, "DWORD PTR ");
11217           break;
11218         case 256:
11219           oappend (ins, "QWORD PTR ");
11220           break;
11221         case 512:
11222           oappend (ins, "XMMWORD PTR ");
11223           break;
11224         default:
11225           abort ();
11226         }
11227       break;
11228     case ymmq_mode:
11229       if (!ins->need_vex)
11230         abort ();
11231
11232       switch (ins->vex.length)
11233         {
11234         case 128:
11235           oappend (ins, "QWORD PTR ");
11236           break;
11237         case 256:
11238           oappend (ins, "YMMWORD PTR ");
11239           break;
11240         case 512:
11241           oappend (ins, "ZMMWORD PTR ");
11242           break;
11243         default:
11244           abort ();
11245         }
11246       break;
11247     case o_mode:
11248       oappend (ins, "OWORD PTR ");
11249       break;
11250     case vex_vsib_d_w_dq_mode:
11251     case vex_vsib_q_w_dq_mode:
11252       if (!ins->need_vex)
11253         abort ();
11254       if (ins->vex.w)
11255         oappend (ins, "QWORD PTR ");
11256       else
11257         oappend (ins, "DWORD PTR ");
11258       break;
11259     case mask_bd_mode:
11260       if (!ins->need_vex || ins->vex.length != 128)
11261         abort ();
11262       if (ins->vex.w)
11263         oappend (ins, "DWORD PTR ");
11264       else
11265         oappend (ins, "BYTE PTR ");
11266       break;
11267     case mask_mode:
11268       if (!ins->need_vex)
11269         abort ();
11270       if (ins->vex.w)
11271         oappend (ins, "QWORD PTR ");
11272       else
11273         oappend (ins, "WORD PTR ");
11274       break;
11275     case v_bnd_mode:
11276     case v_bndmk_mode:
11277     default:
11278       break;
11279     }
11280 }
11281
11282 static void
11283 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11284                 int bytemode, int sizeflag)
11285 {
11286   const char **names;
11287
11288   USED_REX (rexmask);
11289   if (ins->rex & rexmask)
11290     reg += 8;
11291
11292   switch (bytemode)
11293     {
11294     case b_mode:
11295     case b_swap_mode:
11296       if (reg & 4)
11297         USED_REX (0);
11298       if (ins->rex)
11299         names = ins->names8rex;
11300       else
11301         names = ins->names8;
11302       break;
11303     case w_mode:
11304       names = ins->names16;
11305       break;
11306     case d_mode:
11307     case dw_mode:
11308     case db_mode:
11309       names = ins->names32;
11310       break;
11311     case q_mode:
11312       names = ins->names64;
11313       break;
11314     case m_mode:
11315     case v_bnd_mode:
11316       names = ins->address_mode == mode_64bit ? ins->names64 : ins->names32;
11317       break;
11318     case bnd_mode:
11319     case bnd_swap_mode:
11320       if (reg > 0x3)
11321         {
11322           oappend (ins, "(bad)");
11323           return;
11324         }
11325       names = ins->names_bnd;
11326       break;
11327     case indir_v_mode:
11328       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11329         {
11330           names = ins->names64;
11331           break;
11332         }
11333       /* Fall through.  */
11334     case stack_v_mode:
11335       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11336                                               || (ins->rex & REX_W)))
11337         {
11338           names = ins->names64;
11339           break;
11340         }
11341       bytemode = v_mode;
11342       /* Fall through.  */
11343     case v_mode:
11344     case v_swap_mode:
11345     case dq_mode:
11346       USED_REX (REX_W);
11347       if (ins->rex & REX_W)
11348         names = ins->names64;
11349       else if (bytemode != v_mode && bytemode != v_swap_mode)
11350         names = ins->names32;
11351       else
11352         {
11353           if (sizeflag & DFLAG)
11354             names = ins->names32;
11355           else
11356             names = ins->names16;
11357           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11358         }
11359       break;
11360     case movsxd_mode:
11361       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11362         names = ins->names16;
11363       else
11364         names = ins->names32;
11365       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11366       break;
11367     case va_mode:
11368       names = (ins->address_mode == mode_64bit
11369                ? ins->names64 : ins->names32);
11370       if (!(ins->prefixes & PREFIX_ADDR))
11371         names = (ins->address_mode == mode_16bit
11372                      ? ins->names16 : names);
11373       else
11374         {
11375           /* Remove "addr16/addr32".  */
11376           ins->all_prefixes[ins->last_addr_prefix] = 0;
11377           names = (ins->address_mode != mode_32bit
11378                        ? ins->names32 : ins->names16);
11379           ins->used_prefixes |= PREFIX_ADDR;
11380         }
11381       break;
11382     case mask_bd_mode:
11383     case mask_mode:
11384       if (reg > 0x7)
11385         {
11386           oappend (ins, "(bad)");
11387           return;
11388         }
11389       names = ins->names_mask;
11390       break;
11391     case 0:
11392       return;
11393     default:
11394       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11395       return;
11396     }
11397   oappend (ins, names[reg]);
11398 }
11399
11400 static void
11401 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11402 {
11403   bfd_vma disp = 0;
11404   int add = (ins->rex & REX_B) ? 8 : 0;
11405   int riprel = 0;
11406   int shift;
11407
11408   if (ins->vex.evex)
11409     {
11410       switch (bytemode)
11411         {
11412         case dw_mode:
11413         case w_mode:
11414         case w_swap_mode:
11415           shift = 1;
11416           break;
11417         case db_mode:
11418         case b_mode:
11419           shift = 0;
11420           break;
11421         case dq_mode:
11422           if (ins->address_mode != mode_64bit)
11423             {
11424         case d_mode:
11425         case d_swap_mode:
11426               shift = 2;
11427               break;
11428             }
11429             /* fall through */
11430         case vex_vsib_d_w_dq_mode:
11431         case vex_vsib_q_w_dq_mode:
11432         case evex_x_gscat_mode:
11433           shift = ins->vex.w ? 3 : 2;
11434           break;
11435         case xh_mode:
11436         case evex_half_bcst_xmmqh_mode:
11437         case evex_half_bcst_xmmqdh_mode:
11438           if (ins->vex.b)
11439             {
11440               shift = ins->vex.w ? 2 : 1;
11441               break;
11442             }
11443           /* Fall through.  */
11444         case x_mode:
11445         case evex_half_bcst_xmmq_mode:
11446           if (ins->vex.b)
11447             {
11448               shift = ins->vex.w ? 3 : 2;
11449               break;
11450             }
11451           /* Fall through.  */
11452         case xmmqd_mode:
11453         case xmmdw_mode:
11454         case xmmq_mode:
11455         case ymmq_mode:
11456         case evex_x_nobcst_mode:
11457         case x_swap_mode:
11458           switch (ins->vex.length)
11459             {
11460             case 128:
11461               shift = 4;
11462               break;
11463             case 256:
11464               shift = 5;
11465               break;
11466             case 512:
11467               shift = 6;
11468               break;
11469             default:
11470               abort ();
11471             }
11472           /* Make necessary corrections to shift for modes that need it.  */
11473           if (bytemode == xmmq_mode
11474               || bytemode == evex_half_bcst_xmmqh_mode
11475               || bytemode == evex_half_bcst_xmmq_mode
11476               || (bytemode == ymmq_mode && ins->vex.length == 128))
11477             shift -= 1;
11478           else if (bytemode == xmmqd_mode
11479                    || bytemode == evex_half_bcst_xmmqdh_mode)
11480             shift -= 2;
11481           else if (bytemode == xmmdw_mode)
11482             shift -= 3;
11483           break;
11484         case ymm_mode:
11485           shift = 5;
11486           break;
11487         case xmm_mode:
11488           shift = 4;
11489           break;
11490         case q_mode:
11491         case q_swap_mode:
11492           shift = 3;
11493           break;
11494         case bw_unit_mode:
11495           shift = ins->vex.w ? 1 : 0;
11496           break;
11497         default:
11498           abort ();
11499         }
11500     }
11501   else
11502     shift = 0;
11503
11504   USED_REX (REX_B);
11505   if (ins->intel_syntax)
11506     intel_operand_size (ins, bytemode, sizeflag);
11507   append_seg (ins);
11508
11509   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11510     {
11511       /* 32/64 bit address mode */
11512       int havedisp;
11513       int havesib;
11514       int havebase;
11515       int haveindex;
11516       int needindex;
11517       int needaddr32;
11518       int base, rbase;
11519       int vindex = 0;
11520       int scale = 0;
11521       int addr32flag = !((sizeflag & AFLAG)
11522                          || bytemode == v_bnd_mode
11523                          || bytemode == v_bndmk_mode
11524                          || bytemode == bnd_mode
11525                          || bytemode == bnd_swap_mode);
11526       bool check_gather = false;
11527       const char **indexes64 = ins->names64;
11528       const char **indexes32 = ins->names32;
11529
11530       havesib = 0;
11531       havebase = 1;
11532       haveindex = 0;
11533       base = ins->modrm.rm;
11534
11535       if (base == 4)
11536         {
11537           havesib = 1;
11538           vindex = ins->sib.index;
11539           USED_REX (REX_X);
11540           if (ins->rex & REX_X)
11541             vindex += 8;
11542           switch (bytemode)
11543             {
11544             case vex_vsib_d_w_dq_mode:
11545             case vex_vsib_q_w_dq_mode:
11546               if (!ins->need_vex)
11547                 abort ();
11548               if (ins->vex.evex)
11549                 {
11550                   if (!ins->vex.v)
11551                     vindex += 16;
11552                   check_gather = ins->obufp == ins->op_out[1];
11553                 }
11554
11555               haveindex = 1;
11556               switch (ins->vex.length)
11557                 {
11558                 case 128:
11559                   indexes64 = indexes32 = ins->names_xmm;
11560                   break;
11561                 case 256:
11562                   if (!ins->vex.w
11563                       || bytemode == vex_vsib_q_w_dq_mode)
11564                     indexes64 = indexes32 = ins->names_ymm;
11565                   else
11566                     indexes64 = indexes32 = ins->names_xmm;
11567                   break;
11568                 case 512:
11569                   if (!ins->vex.w
11570                       || bytemode == vex_vsib_q_w_dq_mode)
11571                     indexes64 = indexes32 = ins->names_zmm;
11572                   else
11573                     indexes64 = indexes32 = ins->names_ymm;
11574                   break;
11575                 default:
11576                   abort ();
11577                 }
11578               break;
11579             default:
11580               haveindex = vindex != 4;
11581               break;
11582             }
11583           scale = ins->sib.scale;
11584           base = ins->sib.base;
11585           ins->codep++;
11586         }
11587       else
11588         {
11589           /* Check for mandatory SIB.  */
11590           if (bytemode == vex_vsib_d_w_dq_mode
11591               || bytemode == vex_vsib_q_w_dq_mode
11592               || bytemode == vex_sibmem_mode)
11593             {
11594               oappend (ins, "(bad)");
11595               return;
11596             }
11597         }
11598       rbase = base + add;
11599
11600       switch (ins->modrm.mod)
11601         {
11602         case 0:
11603           if (base == 5)
11604             {
11605               havebase = 0;
11606               if (ins->address_mode == mode_64bit && !havesib)
11607                 riprel = 1;
11608               disp = get32s (ins);
11609               if (riprel && bytemode == v_bndmk_mode)
11610                 {
11611                   oappend (ins, "(bad)");
11612                   return;
11613                 }
11614             }
11615           break;
11616         case 1:
11617           FETCH_DATA (ins->info, ins->codep + 1);
11618           disp = *ins->codep++;
11619           if ((disp & 0x80) != 0)
11620             disp -= 0x100;
11621           if (ins->vex.evex && shift > 0)
11622             disp <<= shift;
11623           break;
11624         case 2:
11625           disp = get32s (ins);
11626           break;
11627         }
11628
11629       needindex = 0;
11630       needaddr32 = 0;
11631       if (havesib
11632           && !havebase
11633           && !haveindex
11634           && ins->address_mode != mode_16bit)
11635         {
11636           if (ins->address_mode == mode_64bit)
11637             {
11638               if (addr32flag)
11639                 {
11640                   /* Without base nor index registers, zero-extend the
11641                      lower 32-bit displacement to 64 bits.  */
11642                   disp = (unsigned int) disp;
11643                   needindex = 1;
11644                 }
11645               needaddr32 = 1;
11646             }
11647           else
11648             {
11649               /* In 32-bit mode, we need index register to tell [offset]
11650                  from [eiz*1 + offset].  */
11651               needindex = 1;
11652             }
11653         }
11654
11655       havedisp = (havebase
11656                   || needindex
11657                   || (havesib && (haveindex || scale != 0)));
11658
11659       if (!ins->intel_syntax)
11660         if (ins->modrm.mod != 0 || base == 5)
11661           {
11662             if (havedisp || riprel)
11663               print_displacement (ins, ins->scratchbuf, disp);
11664             else
11665               print_operand_value (ins, ins->scratchbuf, 1, disp);
11666             oappend (ins, ins->scratchbuf);
11667             if (riprel)
11668               {
11669                 set_op (ins, disp, 1);
11670                 oappend (ins, !addr32flag ? "(%rip)" : "(%eip)");
11671               }
11672           }
11673
11674       if ((havebase || haveindex || needindex || needaddr32 || riprel)
11675           && (ins->address_mode != mode_64bit
11676               || ((bytemode != v_bnd_mode)
11677                   && (bytemode != v_bndmk_mode)
11678                   && (bytemode != bnd_mode)
11679                   && (bytemode != bnd_swap_mode))))
11680         ins->used_prefixes |= PREFIX_ADDR;
11681
11682       if (havedisp || (ins->intel_syntax && riprel))
11683         {
11684           *ins->obufp++ = ins->open_char;
11685           if (ins->intel_syntax && riprel)
11686             {
11687               set_op (ins, disp, 1);
11688               oappend (ins, !addr32flag ? "rip" : "eip");
11689             }
11690           *ins->obufp = '\0';
11691           if (havebase)
11692             oappend (ins, ins->address_mode == mode_64bit && !addr32flag
11693                      ? ins->names64[rbase] : ins->names32[rbase]);
11694           if (havesib)
11695             {
11696               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11697                  print index to tell base + index from base.  */
11698               if (scale != 0
11699                   || needindex
11700                   || haveindex
11701                   || (havebase && base != ESP_REG_NUM))
11702                 {
11703                   if (!ins->intel_syntax || havebase)
11704                     {
11705                       *ins->obufp++ = ins->separator_char;
11706                       *ins->obufp = '\0';
11707                     }
11708                   if (haveindex)
11709                     {
11710                       if (ins->address_mode == mode_64bit || vindex < 16)
11711                         oappend (ins, ins->address_mode == mode_64bit
11712                                  && !addr32flag
11713                                  ? indexes64[vindex] : indexes32[vindex]);
11714                       else
11715                         oappend (ins, "(bad)");
11716                     }
11717                   else
11718                     oappend (ins, ins->address_mode == mode_64bit && !addr32flag
11719                              ? ins->index64 : ins->index32);
11720
11721                   *ins->obufp++ = ins->scale_char;
11722                   *ins->obufp = '\0';
11723                   sprintf (ins->scratchbuf, "%d", 1 << scale);
11724                   oappend (ins, ins->scratchbuf);
11725                 }
11726             }
11727           if (ins->intel_syntax
11728               && (disp || ins->modrm.mod != 0 || base == 5))
11729             {
11730               if (!havedisp || (bfd_signed_vma) disp >= 0)
11731                 {
11732                   *ins->obufp++ = '+';
11733                   *ins->obufp = '\0';
11734                 }
11735               else if (ins->modrm.mod != 1 && disp != -disp)
11736                 {
11737                   *ins->obufp++ = '-';
11738                   *ins->obufp = '\0';
11739                   disp = - (bfd_signed_vma) disp;
11740                 }
11741
11742               if (havedisp)
11743                 print_displacement (ins, ins->scratchbuf, disp);
11744               else
11745                 print_operand_value (ins, ins->scratchbuf, 1, disp);
11746               oappend (ins, ins->scratchbuf);
11747             }
11748
11749           *ins->obufp++ = ins->close_char;
11750           *ins->obufp = '\0';
11751
11752           if (check_gather)
11753             {
11754               /* Both XMM/YMM/ZMM registers must be distinct.  */
11755               int modrm_reg = ins->modrm.reg;
11756
11757               if (ins->rex & REX_R)
11758                 modrm_reg += 8;
11759               if (!ins->vex.r)
11760                 modrm_reg += 16;
11761               if (vindex == modrm_reg)
11762                 oappend (ins, "/(bad)");
11763             }
11764         }
11765       else if (ins->intel_syntax)
11766         {
11767           if (ins->modrm.mod != 0 || base == 5)
11768             {
11769               if (!ins->active_seg_prefix)
11770                 {
11771                   oappend (ins, ins->names_seg[ds_reg - es_reg]);
11772                   oappend (ins, ":");
11773                 }
11774               print_operand_value (ins, ins->scratchbuf, 1, disp);
11775               oappend (ins, ins->scratchbuf);
11776             }
11777         }
11778     }
11779   else if (bytemode == v_bnd_mode
11780            || bytemode == v_bndmk_mode
11781            || bytemode == bnd_mode
11782            || bytemode == bnd_swap_mode
11783            || bytemode == vex_vsib_d_w_dq_mode
11784            || bytemode == vex_vsib_q_w_dq_mode)
11785     {
11786       oappend (ins, "(bad)");
11787       return;
11788     }
11789   else
11790     {
11791       /* 16 bit address mode */
11792       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
11793       switch (ins->modrm.mod)
11794         {
11795         case 0:
11796           if (ins->modrm.rm == 6)
11797             {
11798               disp = get16 (ins);
11799               if ((disp & 0x8000) != 0)
11800                 disp -= 0x10000;
11801             }
11802           break;
11803         case 1:
11804           FETCH_DATA (ins->info, ins->codep + 1);
11805           disp = *ins->codep++;
11806           if ((disp & 0x80) != 0)
11807             disp -= 0x100;
11808           if (ins->vex.evex && shift > 0)
11809             disp <<= shift;
11810           break;
11811         case 2:
11812           disp = get16 (ins);
11813           if ((disp & 0x8000) != 0)
11814             disp -= 0x10000;
11815           break;
11816         }
11817
11818       if (!ins->intel_syntax)
11819         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
11820           {
11821             print_displacement (ins, ins->scratchbuf, disp);
11822             oappend (ins, ins->scratchbuf);
11823           }
11824
11825       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
11826         {
11827           *ins->obufp++ = ins->open_char;
11828           *ins->obufp = '\0';
11829           oappend (ins, ins->index16[ins->modrm.rm]);
11830           if (ins->intel_syntax
11831               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
11832             {
11833               if ((bfd_signed_vma) disp >= 0)
11834                 {
11835                   *ins->obufp++ = '+';
11836                   *ins->obufp = '\0';
11837                 }
11838               else if (ins->modrm.mod != 1)
11839                 {
11840                   *ins->obufp++ = '-';
11841                   *ins->obufp = '\0';
11842                   disp = - (bfd_signed_vma) disp;
11843                 }
11844
11845               print_displacement (ins, ins->scratchbuf, disp);
11846               oappend (ins, ins->scratchbuf);
11847             }
11848
11849           *ins->obufp++ = ins->close_char;
11850           *ins->obufp = '\0';
11851         }
11852       else if (ins->intel_syntax)
11853         {
11854           if (!ins->active_seg_prefix)
11855             {
11856               oappend (ins, ins->names_seg[ds_reg - es_reg]);
11857               oappend (ins, ":");
11858             }
11859           print_operand_value (ins, ins->scratchbuf, 1, disp & 0xffff);
11860           oappend (ins, ins->scratchbuf);
11861         }
11862     }
11863   if (ins->vex.b)
11864     {
11865       ins->evex_used |= EVEX_b_used;
11866
11867       /* Broadcast can only ever be valid for memory sources.  */
11868       if (ins->obufp == ins->op_out[0])
11869         ins->vex.no_broadcast = 1;
11870
11871       if (!ins->vex.no_broadcast)
11872         {
11873           if (bytemode == xh_mode)
11874             {
11875               if (ins->vex.w)
11876                 oappend (ins, "{bad}");
11877               else
11878                 {
11879                   switch (ins->vex.length)
11880                     {
11881                     case 128:
11882                       oappend (ins, "{1to8}");
11883                       break;
11884                     case 256:
11885                       oappend (ins, "{1to16}");
11886                       break;
11887                     case 512:
11888                       oappend (ins, "{1to32}");
11889                       break;
11890                     default:
11891                       abort ();
11892                     }
11893                 }
11894             }
11895           else if (bytemode == q_mode
11896                    || bytemode == ymmq_mode)
11897             ins->vex.no_broadcast = 1;
11898           else if (ins->vex.w
11899                    || bytemode == evex_half_bcst_xmmqdh_mode
11900                    || bytemode == evex_half_bcst_xmmq_mode)
11901             {
11902               switch (ins->vex.length)
11903                 {
11904                 case 128:
11905                   oappend (ins, "{1to2}");
11906                   break;
11907                 case 256:
11908                   oappend (ins, "{1to4}");
11909                   break;
11910                 case 512:
11911                   oappend (ins, "{1to8}");
11912                   break;
11913                 default:
11914                   abort ();
11915                 }
11916             }
11917           else if (bytemode == x_mode
11918                    || bytemode == evex_half_bcst_xmmqh_mode)
11919             {
11920               switch (ins->vex.length)
11921                 {
11922                 case 128:
11923                   oappend (ins, "{1to4}");
11924                   break;
11925                 case 256:
11926                   oappend (ins, "{1to8}");
11927                   break;
11928                 case 512:
11929                   oappend (ins, "{1to16}");
11930                   break;
11931                 default:
11932                   abort ();
11933                 }
11934             }
11935           else
11936             ins->vex.no_broadcast = 1;
11937         }
11938       if (ins->vex.no_broadcast)
11939         oappend (ins, "{bad}");
11940     }
11941 }
11942
11943 static void
11944 OP_E (instr_info *ins, int bytemode, int sizeflag)
11945 {
11946   /* Skip mod/rm byte.  */
11947   MODRM_CHECK;
11948   ins->codep++;
11949
11950   if (ins->modrm.mod == 3)
11951     {
11952       if ((sizeflag & SUFFIX_ALWAYS)
11953           && (bytemode == b_swap_mode
11954               || bytemode == bnd_swap_mode
11955               || bytemode == v_swap_mode))
11956         swap_operand (ins);
11957
11958       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
11959     }
11960   else
11961     OP_E_memory (ins, bytemode, sizeflag);
11962 }
11963
11964 static void
11965 OP_G (instr_info *ins, int bytemode, int sizeflag)
11966 {
11967   if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
11968     {
11969       oappend (ins, "(bad)");
11970       return;
11971     }
11972
11973   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
11974 }
11975
11976 #ifdef BFD64
11977 static bfd_vma
11978 get64 (instr_info *ins)
11979 {
11980   bfd_vma x;
11981   unsigned int a;
11982   unsigned int b;
11983
11984   FETCH_DATA (ins->info, ins->codep + 8);
11985   a = *ins->codep++ & 0xff;
11986   a |= (*ins->codep++ & 0xff) << 8;
11987   a |= (*ins->codep++ & 0xff) << 16;
11988   a |= (*ins->codep++ & 0xffu) << 24;
11989   b = *ins->codep++ & 0xff;
11990   b |= (*ins->codep++ & 0xff) << 8;
11991   b |= (*ins->codep++ & 0xff) << 16;
11992   b |= (*ins->codep++ & 0xffu) << 24;
11993   x = a + ((bfd_vma) b << 32);
11994   return x;
11995 }
11996 #else
11997 static bfd_vma
11998 get64 (instr_info *ins ATTRIBUTE_UNUSED)
11999 {
12000   abort ();
12001   return 0;
12002 }
12003 #endif
12004
12005 static bfd_signed_vma
12006 get32 (instr_info *ins)
12007 {
12008   bfd_signed_vma x = 0;
12009
12010   FETCH_DATA (ins->info, ins->codep + 4);
12011   x = *ins->codep++ & (bfd_signed_vma) 0xff;
12012   x |= (*ins->codep++ & (bfd_signed_vma) 0xff) << 8;
12013   x |= (*ins->codep++ & (bfd_signed_vma) 0xff) << 16;
12014   x |= (*ins->codep++ & (bfd_signed_vma) 0xff) << 24;
12015   return x;
12016 }
12017
12018 static bfd_signed_vma
12019 get32s (instr_info *ins)
12020 {
12021   bfd_signed_vma x = 0;
12022
12023   FETCH_DATA (ins->info, ins->codep + 4);
12024   x = *ins->codep++ & (bfd_signed_vma) 0xff;
12025   x |= (*ins->codep++ & (bfd_signed_vma) 0xff) << 8;
12026   x |= (*ins->codep++ & (bfd_signed_vma) 0xff) << 16;
12027   x |= (*ins->codep++ & (bfd_signed_vma) 0xff) << 24;
12028
12029   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12030
12031   return x;
12032 }
12033
12034 static int
12035 get16 (instr_info *ins)
12036 {
12037   int x = 0;
12038
12039   FETCH_DATA (ins->info, ins->codep + 2);
12040   x = *ins->codep++ & 0xff;
12041   x |= (*ins->codep++ & 0xff) << 8;
12042   return x;
12043 }
12044
12045 static void
12046 set_op (instr_info *ins, bfd_vma op, int riprel)
12047 {
12048   ins->op_index[ins->op_ad] = ins->op_ad;
12049   if (ins->address_mode == mode_64bit)
12050     {
12051       ins->op_address[ins->op_ad] = op;
12052       ins->op_riprel[ins->op_ad] = riprel;
12053     }
12054   else
12055     {
12056       /* Mask to get a 32-bit address.  */
12057       ins->op_address[ins->op_ad] = op & 0xffffffff;
12058       ins->op_riprel[ins->op_ad] = riprel & 0xffffffff;
12059     }
12060 }
12061
12062 static void
12063 OP_REG (instr_info *ins, int code, int sizeflag)
12064 {
12065   const char *s;
12066   int add;
12067
12068   switch (code)
12069     {
12070     case es_reg: case ss_reg: case cs_reg:
12071     case ds_reg: case fs_reg: case gs_reg:
12072       oappend (ins, ins->names_seg[code - es_reg]);
12073       return;
12074     }
12075
12076   USED_REX (REX_B);
12077   if (ins->rex & REX_B)
12078     add = 8;
12079   else
12080     add = 0;
12081
12082   switch (code)
12083     {
12084     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12085     case sp_reg: case bp_reg: case si_reg: case di_reg:
12086       s = ins->names16[code - ax_reg + add];
12087       break;
12088     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12089       USED_REX (0);
12090       /* Fall through.  */
12091     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12092       if (ins->rex)
12093         s = ins->names8rex[code - al_reg + add];
12094       else
12095         s = ins->names8[code - al_reg];
12096       break;
12097     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12098     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12099       if (ins->address_mode == mode_64bit
12100           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12101         {
12102           s = ins->names64[code - rAX_reg + add];
12103           break;
12104         }
12105       code += eAX_reg - rAX_reg;
12106       /* Fall through.  */
12107     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12108     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12109       USED_REX (REX_W);
12110       if (ins->rex & REX_W)
12111         s = ins->names64[code - eAX_reg + add];
12112       else
12113         {
12114           if (sizeflag & DFLAG)
12115             s = ins->names32[code - eAX_reg + add];
12116           else
12117             s = ins->names16[code - eAX_reg + add];
12118           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12119         }
12120       break;
12121     default:
12122       s = INTERNAL_DISASSEMBLER_ERROR;
12123       break;
12124     }
12125   oappend (ins, s);
12126 }
12127
12128 static void
12129 OP_IMREG (instr_info *ins, int code, int sizeflag)
12130 {
12131   const char *s;
12132
12133   switch (code)
12134     {
12135     case indir_dx_reg:
12136       if (ins->intel_syntax)
12137         s = "dx";
12138       else
12139         s = "(%dx)";
12140       break;
12141     case al_reg: case cl_reg:
12142       s = ins->names8[code - al_reg];
12143       break;
12144     case eAX_reg:
12145       USED_REX (REX_W);
12146       if (ins->rex & REX_W)
12147         {
12148           s = *ins->names64;
12149           break;
12150         }
12151       /* Fall through.  */
12152     case z_mode_ax_reg:
12153       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12154         s = *ins->names32;
12155       else
12156         s = *ins->names16;
12157       if (!(ins->rex & REX_W))
12158         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12159       break;
12160     default:
12161       s = INTERNAL_DISASSEMBLER_ERROR;
12162       break;
12163     }
12164   oappend (ins, s);
12165 }
12166
12167 static void
12168 OP_I (instr_info *ins, int bytemode, int sizeflag)
12169 {
12170   bfd_signed_vma op;
12171   bfd_signed_vma mask = -1;
12172
12173   switch (bytemode)
12174     {
12175     case b_mode:
12176       FETCH_DATA (ins->info, ins->codep + 1);
12177       op = *ins->codep++;
12178       mask = 0xff;
12179       break;
12180     case v_mode:
12181       USED_REX (REX_W);
12182       if (ins->rex & REX_W)
12183         op = get32s (ins);
12184       else
12185         {
12186           if (sizeflag & DFLAG)
12187             {
12188               op = get32 (ins);
12189               mask = 0xffffffff;
12190             }
12191           else
12192             {
12193               op = get16 (ins);
12194               mask = 0xfffff;
12195             }
12196           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12197         }
12198       break;
12199     case d_mode:
12200       mask = 0xffffffff;
12201       op = get32 (ins);
12202       break;
12203     case w_mode:
12204       mask = 0xfffff;
12205       op = get16 (ins);
12206       break;
12207     case const_1_mode:
12208       if (ins->intel_syntax)
12209         oappend (ins, "1");
12210       return;
12211     default:
12212       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12213       return;
12214     }
12215
12216   op &= mask;
12217   ins->scratchbuf[0] = '$';
12218   print_operand_value (ins, ins->scratchbuf + 1, 1, op);
12219   oappend_maybe_intel (ins, ins->scratchbuf);
12220   ins->scratchbuf[0] = '\0';
12221 }
12222
12223 static void
12224 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12225 {
12226   if (bytemode != v_mode || ins->address_mode != mode_64bit
12227       || !(ins->rex & REX_W))
12228     {
12229       OP_I (ins, bytemode, sizeflag);
12230       return;
12231     }
12232
12233   USED_REX (REX_W);
12234
12235   ins->scratchbuf[0] = '$';
12236   print_operand_value (ins, ins->scratchbuf + 1, 1, get64 (ins));
12237   oappend_maybe_intel (ins, ins->scratchbuf);
12238   ins->scratchbuf[0] = '\0';
12239 }
12240
12241 static void
12242 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12243 {
12244   bfd_signed_vma op;
12245
12246   switch (bytemode)
12247     {
12248     case b_mode:
12249     case b_T_mode:
12250       FETCH_DATA (ins->info, ins->codep + 1);
12251       op = *ins->codep++;
12252       if ((op & 0x80) != 0)
12253         op -= 0x100;
12254       if (bytemode == b_T_mode)
12255         {
12256           if (ins->address_mode != mode_64bit
12257               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12258             {
12259               /* The operand-size prefix is overridden by a REX prefix.  */
12260               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12261                 op &= 0xffffffff;
12262               else
12263                 op &= 0xffff;
12264           }
12265         }
12266       else
12267         {
12268           if (!(ins->rex & REX_W))
12269             {
12270               if (sizeflag & DFLAG)
12271                 op &= 0xffffffff;
12272               else
12273                 op &= 0xffff;
12274             }
12275         }
12276       break;
12277     case v_mode:
12278       /* The operand-size prefix is overridden by a REX prefix.  */
12279       if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12280         op = get32s (ins);
12281       else
12282         op = get16 (ins);
12283       break;
12284     default:
12285       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12286       return;
12287     }
12288
12289   ins->scratchbuf[0] = '$';
12290   print_operand_value (ins, ins->scratchbuf + 1, 1, op);
12291   oappend_maybe_intel (ins, ins->scratchbuf);
12292 }
12293
12294 static void
12295 OP_J (instr_info *ins, int bytemode, int sizeflag)
12296 {
12297   bfd_vma disp;
12298   bfd_vma mask = -1;
12299   bfd_vma segment = 0;
12300
12301   switch (bytemode)
12302     {
12303     case b_mode:
12304       FETCH_DATA (ins->info, ins->codep + 1);
12305       disp = *ins->codep++;
12306       if ((disp & 0x80) != 0)
12307         disp -= 0x100;
12308       break;
12309     case v_mode:
12310     case dqw_mode:
12311       if ((sizeflag & DFLAG)
12312           || (ins->address_mode == mode_64bit
12313               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12314                   || (ins->rex & REX_W))))
12315         disp = get32s (ins);
12316       else
12317         {
12318           disp = get16 (ins);
12319           if ((disp & 0x8000) != 0)
12320             disp -= 0x10000;
12321           /* In 16bit mode, address is wrapped around at 64k within
12322              the same segment.  Otherwise, a data16 prefix on a jump
12323              instruction means that the pc is masked to 16 bits after
12324              the displacement is added!  */
12325           mask = 0xffff;
12326           if ((ins->prefixes & PREFIX_DATA) == 0)
12327             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12328                        & ~((bfd_vma) 0xffff));
12329         }
12330       if (ins->address_mode != mode_64bit
12331           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12332         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12333       break;
12334     default:
12335       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12336       return;
12337     }
12338   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12339          | segment;
12340   set_op (ins, disp, 0);
12341   print_operand_value (ins, ins->scratchbuf, 1, disp);
12342   oappend (ins, ins->scratchbuf);
12343 }
12344
12345 static void
12346 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12347 {
12348   if (bytemode == w_mode)
12349     oappend (ins, ins->names_seg[ins->modrm.reg]);
12350   else
12351     OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12352 }
12353
12354 static void
12355 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12356 {
12357   int seg, offset;
12358
12359   if (sizeflag & DFLAG)
12360     {
12361       offset = get32 (ins);
12362       seg = get16 (ins);
12363     }
12364   else
12365     {
12366       offset = get16 (ins);
12367       seg = get16 (ins);
12368     }
12369   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12370   if (ins->intel_syntax)
12371     sprintf (ins->scratchbuf, "0x%x:0x%x", seg, offset);
12372   else
12373     sprintf (ins->scratchbuf, "$0x%x,$0x%x", seg, offset);
12374   oappend (ins, ins->scratchbuf);
12375 }
12376
12377 static void
12378 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12379 {
12380   bfd_vma off;
12381
12382   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12383     intel_operand_size (ins, bytemode, sizeflag);
12384   append_seg (ins);
12385
12386   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12387     off = get32 (ins);
12388   else
12389     off = get16 (ins);
12390
12391   if (ins->intel_syntax)
12392     {
12393       if (!ins->active_seg_prefix)
12394         {
12395           oappend (ins, ins->names_seg[ds_reg - es_reg]);
12396           oappend (ins, ":");
12397         }
12398     }
12399   print_operand_value (ins, ins->scratchbuf, 1, off);
12400   oappend (ins, ins->scratchbuf);
12401 }
12402
12403 static void
12404 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12405 {
12406   bfd_vma off;
12407
12408   if (ins->address_mode != mode_64bit
12409       || (ins->prefixes & PREFIX_ADDR))
12410     {
12411       OP_OFF (ins, bytemode, sizeflag);
12412       return;
12413     }
12414
12415   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12416     intel_operand_size (ins, bytemode, sizeflag);
12417   append_seg (ins);
12418
12419   off = get64 (ins);
12420
12421   if (ins->intel_syntax)
12422     {
12423       if (!ins->active_seg_prefix)
12424         {
12425           oappend (ins, ins->names_seg[ds_reg - es_reg]);
12426           oappend (ins, ":");
12427         }
12428     }
12429   print_operand_value (ins, ins->scratchbuf, 1, off);
12430   oappend (ins, ins->scratchbuf);
12431 }
12432
12433 static void
12434 ptr_reg (instr_info *ins, int code, int sizeflag)
12435 {
12436   const char *s;
12437
12438   *ins->obufp++ = ins->open_char;
12439   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12440   if (ins->address_mode == mode_64bit)
12441     {
12442       if (!(sizeflag & AFLAG))
12443         s = ins->names32[code - eAX_reg];
12444       else
12445         s = ins->names64[code - eAX_reg];
12446     }
12447   else if (sizeflag & AFLAG)
12448     s = ins->names32[code - eAX_reg];
12449   else
12450     s = ins->names16[code - eAX_reg];
12451   oappend (ins, s);
12452   *ins->obufp++ = ins->close_char;
12453   *ins->obufp = 0;
12454 }
12455
12456 static void
12457 OP_ESreg (instr_info *ins, int code, int sizeflag)
12458 {
12459   if (ins->intel_syntax)
12460     {
12461       switch (ins->codep[-1])
12462         {
12463         case 0x6d:      /* insw/insl */
12464           intel_operand_size (ins, z_mode, sizeflag);
12465           break;
12466         case 0xa5:      /* movsw/movsl/movsq */
12467         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12468         case 0xab:      /* stosw/stosl */
12469         case 0xaf:      /* scasw/scasl */
12470           intel_operand_size (ins, v_mode, sizeflag);
12471           break;
12472         default:
12473           intel_operand_size (ins, b_mode, sizeflag);
12474         }
12475     }
12476   oappend_maybe_intel (ins, "%es:");
12477   ptr_reg (ins, code, sizeflag);
12478 }
12479
12480 static void
12481 OP_DSreg (instr_info *ins, int code, int sizeflag)
12482 {
12483   if (ins->intel_syntax)
12484     {
12485       switch (ins->codep[-1])
12486         {
12487         case 0x6f:      /* outsw/outsl */
12488           intel_operand_size (ins, z_mode, sizeflag);
12489           break;
12490         case 0xa5:      /* movsw/movsl/movsq */
12491         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12492         case 0xad:      /* lodsw/lodsl/lodsq */
12493           intel_operand_size (ins, v_mode, sizeflag);
12494           break;
12495         default:
12496           intel_operand_size (ins, b_mode, sizeflag);
12497         }
12498     }
12499   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12500      default segment register DS is printed.  */
12501   if (!ins->active_seg_prefix)
12502     ins->active_seg_prefix = PREFIX_DS;
12503   append_seg (ins);
12504   ptr_reg (ins, code, sizeflag);
12505 }
12506
12507 static void
12508 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12509       int sizeflag ATTRIBUTE_UNUSED)
12510 {
12511   int add;
12512   if (ins->rex & REX_R)
12513     {
12514       USED_REX (REX_R);
12515       add = 8;
12516     }
12517   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12518     {
12519       ins->all_prefixes[ins->last_lock_prefix] = 0;
12520       ins->used_prefixes |= PREFIX_LOCK;
12521       add = 8;
12522     }
12523   else
12524     add = 0;
12525   sprintf (ins->scratchbuf, "%%cr%d", ins->modrm.reg + add);
12526   oappend_maybe_intel (ins, ins->scratchbuf);
12527 }
12528
12529 static void
12530 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12531       int sizeflag ATTRIBUTE_UNUSED)
12532 {
12533   int add;
12534   USED_REX (REX_R);
12535   if (ins->rex & REX_R)
12536     add = 8;
12537   else
12538     add = 0;
12539   if (ins->intel_syntax)
12540     sprintf (ins->scratchbuf, "dr%d", ins->modrm.reg + add);
12541   else
12542     sprintf (ins->scratchbuf, "%%db%d", ins->modrm.reg + add);
12543   oappend (ins, ins->scratchbuf);
12544 }
12545
12546 static void
12547 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12548       int sizeflag ATTRIBUTE_UNUSED)
12549 {
12550   sprintf (ins->scratchbuf, "%%tr%d", ins->modrm.reg);
12551   oappend_maybe_intel (ins, ins->scratchbuf);
12552 }
12553
12554 static void
12555 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12556         int sizeflag ATTRIBUTE_UNUSED)
12557 {
12558   int reg = ins->modrm.reg;
12559   const char **names;
12560
12561   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12562   if (ins->prefixes & PREFIX_DATA)
12563     {
12564       names = ins->names_xmm;
12565       USED_REX (REX_R);
12566       if (ins->rex & REX_R)
12567         reg += 8;
12568     }
12569   else
12570     names = ins->names_mm;
12571   oappend (ins, names[reg]);
12572 }
12573
12574 static void
12575 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12576 {
12577   const char **names;
12578
12579   if (bytemode == xmmq_mode
12580       || bytemode == evex_half_bcst_xmmqh_mode
12581       || bytemode == evex_half_bcst_xmmq_mode)
12582     {
12583       switch (ins->vex.length)
12584         {
12585         case 128:
12586         case 256:
12587           names = ins->names_xmm;
12588           break;
12589         case 512:
12590           names = ins->names_ymm;
12591           break;
12592         default:
12593           abort ();
12594         }
12595     }
12596   else if (bytemode == ymm_mode)
12597     names = ins->names_ymm;
12598   else if (bytemode == tmm_mode)
12599     {
12600       if (reg >= 8)
12601         {
12602           oappend (ins, "(bad)");
12603           return;
12604         }
12605       names = ins->names_tmm;
12606     }
12607   else if (ins->need_vex
12608            && bytemode != xmm_mode
12609            && bytemode != scalar_mode
12610            && bytemode != xmmdw_mode
12611            && bytemode != xmmqd_mode
12612            && bytemode != evex_half_bcst_xmmqdh_mode
12613            && bytemode != w_swap_mode
12614            && bytemode != b_mode
12615            && bytemode != w_mode
12616            && bytemode != d_mode
12617            && bytemode != q_mode)
12618     {
12619       switch (ins->vex.length)
12620         {
12621         case 128:
12622           names = ins->names_xmm;
12623           break;
12624         case 256:
12625           if (ins->vex.w
12626               || bytemode != vex_vsib_q_w_dq_mode)
12627             names = ins->names_ymm;
12628           else
12629             names = ins->names_xmm;
12630           break;
12631         case 512:
12632           if (ins->vex.w
12633               || bytemode != vex_vsib_q_w_dq_mode)
12634             names = ins->names_zmm;
12635           else
12636             names = ins->names_ymm;
12637           break;
12638         default:
12639           abort ();
12640         }
12641     }
12642   else
12643     names = ins->names_xmm;
12644   oappend (ins, names[reg]);
12645 }
12646
12647 static void
12648 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12649 {
12650   unsigned int reg = ins->modrm.reg;
12651
12652   USED_REX (REX_R);
12653   if (ins->rex & REX_R)
12654     reg += 8;
12655   if (ins->vex.evex)
12656     {
12657       if (!ins->vex.r)
12658         reg += 16;
12659     }
12660
12661   if (bytemode == tmm_mode)
12662     ins->modrm.reg = reg;
12663   else if (bytemode == scalar_mode)
12664     ins->vex.no_broadcast = 1;
12665
12666   print_vector_reg (ins, reg, bytemode);
12667 }
12668
12669 static void
12670 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12671 {
12672   int reg;
12673   const char **names;
12674
12675   if (ins->modrm.mod != 3)
12676     {
12677       if (ins->intel_syntax
12678           && (bytemode == v_mode || bytemode == v_swap_mode))
12679         {
12680           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12681           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12682         }
12683       OP_E (ins, bytemode, sizeflag);
12684       return;
12685     }
12686
12687   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12688     swap_operand (ins);
12689
12690   /* Skip mod/rm byte.  */
12691   MODRM_CHECK;
12692   ins->codep++;
12693   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12694   reg = ins->modrm.rm;
12695   if (ins->prefixes & PREFIX_DATA)
12696     {
12697       names = ins->names_xmm;
12698       USED_REX (REX_B);
12699       if (ins->rex & REX_B)
12700         reg += 8;
12701     }
12702   else
12703     names = ins->names_mm;
12704   oappend (ins, names[reg]);
12705 }
12706
12707 /* cvt* are the only instructions in sse2 which have
12708    both SSE and MMX operands and also have 0x66 prefix
12709    in their opcode. 0x66 was originally used to differentiate
12710    between SSE and MMX instruction(operands). So we have to handle the
12711    cvt* separately using OP_EMC and OP_MXC */
12712 static void
12713 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12714 {
12715   if (ins->modrm.mod != 3)
12716     {
12717       if (ins->intel_syntax && bytemode == v_mode)
12718         {
12719           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12720           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12721         }
12722       OP_E (ins, bytemode, sizeflag);
12723       return;
12724     }
12725
12726   /* Skip mod/rm byte.  */
12727   MODRM_CHECK;
12728   ins->codep++;
12729   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12730   oappend (ins, ins->names_mm[ins->modrm.rm]);
12731 }
12732
12733 static void
12734 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12735         int sizeflag ATTRIBUTE_UNUSED)
12736 {
12737   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12738   oappend (ins, ins->names_mm[ins->modrm.reg]);
12739 }
12740
12741 static void
12742 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12743 {
12744   int reg;
12745
12746   /* Skip mod/rm byte.  */
12747   MODRM_CHECK;
12748   ins->codep++;
12749
12750   if (bytemode == dq_mode)
12751     bytemode = ins->vex.w ? q_mode : d_mode;
12752
12753   if (ins->modrm.mod != 3)
12754     {
12755       OP_E_memory (ins, bytemode, sizeflag);
12756       return;
12757     }
12758
12759   reg = ins->modrm.rm;
12760   USED_REX (REX_B);
12761   if (ins->rex & REX_B)
12762     reg += 8;
12763   if (ins->vex.evex)
12764     {
12765       USED_REX (REX_X);
12766       if ((ins->rex & REX_X))
12767         reg += 16;
12768     }
12769
12770   if ((sizeflag & SUFFIX_ALWAYS)
12771       && (bytemode == x_swap_mode
12772           || bytemode == w_swap_mode
12773           || bytemode == d_swap_mode
12774           || bytemode == q_swap_mode))
12775     swap_operand (ins);
12776
12777   if (bytemode == tmm_mode)
12778     ins->modrm.rm = reg;
12779
12780   print_vector_reg (ins, reg, bytemode);
12781 }
12782
12783 static void
12784 OP_MS (instr_info *ins, int bytemode, int sizeflag)
12785 {
12786   if (ins->modrm.mod == 3)
12787     OP_EM (ins, bytemode, sizeflag);
12788   else
12789     BadOp (ins);
12790 }
12791
12792 static void
12793 OP_XS (instr_info *ins, int bytemode, int sizeflag)
12794 {
12795   if (ins->modrm.mod == 3)
12796     OP_EX (ins, bytemode, sizeflag);
12797   else
12798     BadOp (ins);
12799 }
12800
12801 static void
12802 OP_M (instr_info *ins, int bytemode, int sizeflag)
12803 {
12804   if (ins->modrm.mod == 3)
12805     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12806     BadOp (ins);
12807   else
12808     OP_E (ins, bytemode, sizeflag);
12809 }
12810
12811 static void
12812 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
12813 {
12814   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
12815     BadOp (ins);
12816   else
12817     OP_E (ins, bytemode, sizeflag);
12818 }
12819
12820 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12821    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12822
12823 static void
12824 NOP_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
12825 {
12826   if ((ins->prefixes & PREFIX_DATA) != 0
12827       || (ins->rex != 0
12828           && ins->rex != 0x48
12829           && ins->address_mode == mode_64bit))
12830     OP_REG (ins, bytemode, sizeflag);
12831   else
12832     strcpy (ins->obuf, "nop");
12833 }
12834
12835 static void
12836 NOP_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
12837 {
12838   if ((ins->prefixes & PREFIX_DATA) != 0
12839       || (ins->rex != 0
12840           && ins->rex != 0x48
12841           && ins->address_mode == mode_64bit))
12842     OP_IMREG (ins, bytemode, sizeflag);
12843 }
12844
12845 static const char *const Suffix3DNow[] = {
12846 /* 00 */        NULL,           NULL,           NULL,           NULL,
12847 /* 04 */        NULL,           NULL,           NULL,           NULL,
12848 /* 08 */        NULL,           NULL,           NULL,           NULL,
12849 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12850 /* 10 */        NULL,           NULL,           NULL,           NULL,
12851 /* 14 */        NULL,           NULL,           NULL,           NULL,
12852 /* 18 */        NULL,           NULL,           NULL,           NULL,
12853 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12854 /* 20 */        NULL,           NULL,           NULL,           NULL,
12855 /* 24 */        NULL,           NULL,           NULL,           NULL,
12856 /* 28 */        NULL,           NULL,           NULL,           NULL,
12857 /* 2C */        NULL,           NULL,           NULL,           NULL,
12858 /* 30 */        NULL,           NULL,           NULL,           NULL,
12859 /* 34 */        NULL,           NULL,           NULL,           NULL,
12860 /* 38 */        NULL,           NULL,           NULL,           NULL,
12861 /* 3C */        NULL,           NULL,           NULL,           NULL,
12862 /* 40 */        NULL,           NULL,           NULL,           NULL,
12863 /* 44 */        NULL,           NULL,           NULL,           NULL,
12864 /* 48 */        NULL,           NULL,           NULL,           NULL,
12865 /* 4C */        NULL,           NULL,           NULL,           NULL,
12866 /* 50 */        NULL,           NULL,           NULL,           NULL,
12867 /* 54 */        NULL,           NULL,           NULL,           NULL,
12868 /* 58 */        NULL,           NULL,           NULL,           NULL,
12869 /* 5C */        NULL,           NULL,           NULL,           NULL,
12870 /* 60 */        NULL,           NULL,           NULL,           NULL,
12871 /* 64 */        NULL,           NULL,           NULL,           NULL,
12872 /* 68 */        NULL,           NULL,           NULL,           NULL,
12873 /* 6C */        NULL,           NULL,           NULL,           NULL,
12874 /* 70 */        NULL,           NULL,           NULL,           NULL,
12875 /* 74 */        NULL,           NULL,           NULL,           NULL,
12876 /* 78 */        NULL,           NULL,           NULL,           NULL,
12877 /* 7C */        NULL,           NULL,           NULL,           NULL,
12878 /* 80 */        NULL,           NULL,           NULL,           NULL,
12879 /* 84 */        NULL,           NULL,           NULL,           NULL,
12880 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12881 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12882 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12883 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12884 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12885 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12886 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12887 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12888 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12889 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12890 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12891 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12892 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12893 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12894 /* C0 */        NULL,           NULL,           NULL,           NULL,
12895 /* C4 */        NULL,           NULL,           NULL,           NULL,
12896 /* C8 */        NULL,           NULL,           NULL,           NULL,
12897 /* CC */        NULL,           NULL,           NULL,           NULL,
12898 /* D0 */        NULL,           NULL,           NULL,           NULL,
12899 /* D4 */        NULL,           NULL,           NULL,           NULL,
12900 /* D8 */        NULL,           NULL,           NULL,           NULL,
12901 /* DC */        NULL,           NULL,           NULL,           NULL,
12902 /* E0 */        NULL,           NULL,           NULL,           NULL,
12903 /* E4 */        NULL,           NULL,           NULL,           NULL,
12904 /* E8 */        NULL,           NULL,           NULL,           NULL,
12905 /* EC */        NULL,           NULL,           NULL,           NULL,
12906 /* F0 */        NULL,           NULL,           NULL,           NULL,
12907 /* F4 */        NULL,           NULL,           NULL,           NULL,
12908 /* F8 */        NULL,           NULL,           NULL,           NULL,
12909 /* FC */        NULL,           NULL,           NULL,           NULL,
12910 };
12911
12912 static void
12913 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12914                 int sizeflag ATTRIBUTE_UNUSED)
12915 {
12916   const char *mnemonic;
12917
12918   FETCH_DATA (ins->info, ins->codep + 1);
12919   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12920      place where an 8-bit immediate would normally go.  ie. the last
12921      byte of the instruction.  */
12922   ins->obufp = ins->mnemonicendp;
12923   mnemonic = Suffix3DNow[*ins->codep++ & 0xff];
12924   if (mnemonic)
12925     oappend (ins, mnemonic);
12926   else
12927     {
12928       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
12929          of the opcode (0x0f0f) and the opcode suffix, we need to do
12930          all the ins->modrm processing first, and don't know until now that
12931          we have a bad opcode.  This necessitates some cleaning up.  */
12932       ins->op_out[0][0] = '\0';
12933       ins->op_out[1][0] = '\0';
12934       BadOp (ins);
12935     }
12936   ins->mnemonicendp = ins->obufp;
12937 }
12938
12939 static const struct op simd_cmp_op[] =
12940 {
12941   { STRING_COMMA_LEN ("eq") },
12942   { STRING_COMMA_LEN ("lt") },
12943   { STRING_COMMA_LEN ("le") },
12944   { STRING_COMMA_LEN ("unord") },
12945   { STRING_COMMA_LEN ("neq") },
12946   { STRING_COMMA_LEN ("nlt") },
12947   { STRING_COMMA_LEN ("nle") },
12948   { STRING_COMMA_LEN ("ord") }
12949 };
12950
12951 static const struct op vex_cmp_op[] =
12952 {
12953   { STRING_COMMA_LEN ("eq_uq") },
12954   { STRING_COMMA_LEN ("nge") },
12955   { STRING_COMMA_LEN ("ngt") },
12956   { STRING_COMMA_LEN ("false") },
12957   { STRING_COMMA_LEN ("neq_oq") },
12958   { STRING_COMMA_LEN ("ge") },
12959   { STRING_COMMA_LEN ("gt") },
12960   { STRING_COMMA_LEN ("true") },
12961   { STRING_COMMA_LEN ("eq_os") },
12962   { STRING_COMMA_LEN ("lt_oq") },
12963   { STRING_COMMA_LEN ("le_oq") },
12964   { STRING_COMMA_LEN ("unord_s") },
12965   { STRING_COMMA_LEN ("neq_us") },
12966   { STRING_COMMA_LEN ("nlt_uq") },
12967   { STRING_COMMA_LEN ("nle_uq") },
12968   { STRING_COMMA_LEN ("ord_s") },
12969   { STRING_COMMA_LEN ("eq_us") },
12970   { STRING_COMMA_LEN ("nge_uq") },
12971   { STRING_COMMA_LEN ("ngt_uq") },
12972   { STRING_COMMA_LEN ("false_os") },
12973   { STRING_COMMA_LEN ("neq_os") },
12974   { STRING_COMMA_LEN ("ge_oq") },
12975   { STRING_COMMA_LEN ("gt_oq") },
12976   { STRING_COMMA_LEN ("true_us") },
12977 };
12978
12979 static void
12980 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12981            int sizeflag ATTRIBUTE_UNUSED)
12982 {
12983   unsigned int cmp_type;
12984
12985   FETCH_DATA (ins->info, ins->codep + 1);
12986   cmp_type = *ins->codep++ & 0xff;
12987   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12988     {
12989       char suffix[3];
12990       char *p = ins->mnemonicendp - 2;
12991       suffix[0] = p[0];
12992       suffix[1] = p[1];
12993       suffix[2] = '\0';
12994       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12995       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
12996     }
12997   else if (ins->need_vex
12998            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
12999     {
13000       char suffix[3];
13001       char *p = ins->mnemonicendp - 2;
13002       suffix[0] = p[0];
13003       suffix[1] = p[1];
13004       suffix[2] = '\0';
13005       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13006       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13007       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13008     }
13009   else
13010     {
13011       /* We have a reserved extension byte.  Output it directly.  */
13012       ins->scratchbuf[0] = '$';
13013       print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
13014       oappend_maybe_intel (ins, ins->scratchbuf);
13015       ins->scratchbuf[0] = '\0';
13016     }
13017 }
13018
13019 static void
13020 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13021 {
13022   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13023   if (!ins->intel_syntax)
13024     {
13025       strcpy (ins->op_out[0], ins->names32[0]);
13026       strcpy (ins->op_out[1], ins->names32[1]);
13027       if (bytemode == eBX_reg)
13028         strcpy (ins->op_out[2], ins->names32[3]);
13029       ins->two_source_ops = 1;
13030     }
13031   /* Skip mod/rm byte.  */
13032   MODRM_CHECK;
13033   ins->codep++;
13034 }
13035
13036 static void
13037 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13038             int sizeflag ATTRIBUTE_UNUSED)
13039 {
13040   /* monitor %{e,r,}ax,%ecx,%edx"  */
13041   if (!ins->intel_syntax)
13042     {
13043       const char **names = (ins->address_mode == mode_64bit
13044                             ? ins->names64 : ins->names32);
13045
13046       if (ins->prefixes & PREFIX_ADDR)
13047         {
13048           /* Remove "addr16/addr32".  */
13049           ins->all_prefixes[ins->last_addr_prefix] = 0;
13050           names = (ins->address_mode != mode_32bit
13051                    ? ins->names32 : ins->names16);
13052           ins->used_prefixes |= PREFIX_ADDR;
13053         }
13054       else if (ins->address_mode == mode_16bit)
13055         names = ins->names16;
13056       strcpy (ins->op_out[0], names[0]);
13057       strcpy (ins->op_out[1], ins->names32[1]);
13058       strcpy (ins->op_out[2], ins->names32[2]);
13059       ins->two_source_ops = 1;
13060     }
13061   /* Skip mod/rm byte.  */
13062   MODRM_CHECK;
13063   ins->codep++;
13064 }
13065
13066 static void
13067 BadOp (instr_info *ins)
13068 {
13069   /* Throw away prefixes and 1st. opcode byte.  */
13070   ins->codep = ins->insn_codep + 1;
13071   oappend (ins, "(bad)");
13072 }
13073
13074 static void
13075 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13076 {
13077   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13078      lods and stos.  */
13079   if (ins->prefixes & PREFIX_REPZ)
13080     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13081
13082   switch (bytemode)
13083     {
13084     case al_reg:
13085     case eAX_reg:
13086     case indir_dx_reg:
13087       OP_IMREG (ins, bytemode, sizeflag);
13088       break;
13089     case eDI_reg:
13090       OP_ESreg (ins, bytemode, sizeflag);
13091       break;
13092     case eSI_reg:
13093       OP_DSreg (ins, bytemode, sizeflag);
13094       break;
13095     default:
13096       abort ();
13097       break;
13098     }
13099 }
13100
13101 static void
13102 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13103            int sizeflag ATTRIBUTE_UNUSED)
13104 {
13105   if (ins->isa64 != amd64)
13106     return;
13107
13108   ins->obufp = ins->obuf;
13109   BadOp (ins);
13110   ins->mnemonicendp = ins->obufp;
13111   ++ins->codep;
13112 }
13113
13114 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13115    "bnd".  */
13116
13117 static void
13118 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13119            int sizeflag ATTRIBUTE_UNUSED)
13120 {
13121   if (ins->prefixes & PREFIX_REPNZ)
13122     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13123 }
13124
13125 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13126    "notrack".  */
13127
13128 static void
13129 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13130                int sizeflag ATTRIBUTE_UNUSED)
13131 {
13132   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13133      we've seen a PREFIX_DS.  */
13134   if ((ins->prefixes & PREFIX_DS) != 0
13135       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13136     {
13137       /* NOTRACK prefix is only valid on indirect branch instructions.
13138          NB: DATA prefix is unsupported for Intel64.  */
13139       ins->active_seg_prefix = 0;
13140       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13141     }
13142 }
13143
13144 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13145    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13146  */
13147
13148 static void
13149 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13150 {
13151   if (ins->modrm.mod != 3
13152       && (ins->prefixes & PREFIX_LOCK) != 0)
13153     {
13154       if (ins->prefixes & PREFIX_REPZ)
13155         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13156       if (ins->prefixes & PREFIX_REPNZ)
13157         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13158     }
13159
13160   OP_E (ins, bytemode, sizeflag);
13161 }
13162
13163 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13164    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13165  */
13166
13167 static void
13168 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13169 {
13170   if (ins->modrm.mod != 3)
13171     {
13172       if (ins->prefixes & PREFIX_REPZ)
13173         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13174       if (ins->prefixes & PREFIX_REPNZ)
13175         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13176     }
13177
13178   OP_E (ins, bytemode, sizeflag);
13179 }
13180
13181 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13182    "xrelease" for memory operand.  No check for LOCK prefix.   */
13183
13184 static void
13185 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13186 {
13187   if (ins->modrm.mod != 3
13188       && ins->last_repz_prefix > ins->last_repnz_prefix
13189       && (ins->prefixes & PREFIX_REPZ) != 0)
13190     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13191
13192   OP_E (ins, bytemode, sizeflag);
13193 }
13194
13195 static void
13196 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13197 {
13198   USED_REX (REX_W);
13199   if (ins->rex & REX_W)
13200     {
13201       /* Change cmpxchg8b to cmpxchg16b.  */
13202       char *p = ins->mnemonicendp - 2;
13203       ins->mnemonicendp = stpcpy (p, "16b");
13204       bytemode = o_mode;
13205     }
13206   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13207     {
13208       if (ins->prefixes & PREFIX_REPZ)
13209         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13210       if (ins->prefixes & PREFIX_REPNZ)
13211         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13212     }
13213
13214   OP_M (ins, bytemode, sizeflag);
13215 }
13216
13217 static void
13218 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13219 {
13220   const char **names;
13221
13222   if (ins->need_vex)
13223     {
13224       switch (ins->vex.length)
13225         {
13226         case 128:
13227           names = ins->names_xmm;
13228           break;
13229         case 256:
13230           names = ins->names_ymm;
13231           break;
13232         default:
13233           abort ();
13234         }
13235     }
13236   else
13237     names = ins->names_xmm;
13238   oappend (ins, names[reg]);
13239 }
13240
13241 static void
13242 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13243 {
13244   /* Add proper suffix to "fxsave" and "fxrstor".  */
13245   USED_REX (REX_W);
13246   if (ins->rex & REX_W)
13247     {
13248       char *p = ins->mnemonicendp;
13249       *p++ = '6';
13250       *p++ = '4';
13251       *p = '\0';
13252       ins->mnemonicendp = p;
13253     }
13254   OP_M (ins, bytemode, sizeflag);
13255 }
13256
13257 /* Display the destination register operand for instructions with
13258    VEX. */
13259
13260 static void
13261 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13262 {
13263   int reg, modrm_reg, sib_index = -1;
13264   const char **names;
13265
13266   if (!ins->need_vex)
13267     abort ();
13268
13269   reg = ins->vex.register_specifier;
13270   ins->vex.register_specifier = 0;
13271   if (ins->address_mode != mode_64bit)
13272     {
13273       if (ins->vex.evex && !ins->vex.v)
13274         {
13275           oappend (ins, "(bad)");
13276           return;
13277         }
13278
13279       reg &= 7;
13280     }
13281   else if (ins->vex.evex && !ins->vex.v)
13282     reg += 16;
13283
13284   switch (bytemode)
13285     {
13286     case scalar_mode:
13287       oappend (ins, ins->names_xmm[reg]);
13288       return;
13289
13290     case vex_vsib_d_w_dq_mode:
13291     case vex_vsib_q_w_dq_mode:
13292       /* This must be the 3rd operand.  */
13293       if (ins->obufp != ins->op_out[2])
13294         abort ();
13295       if (ins->vex.length == 128
13296           || (bytemode != vex_vsib_d_w_dq_mode
13297               && !ins->vex.w))
13298         oappend (ins, ins->names_xmm[reg]);
13299       else
13300         oappend (ins, ins->names_ymm[reg]);
13301
13302       /* All 3 XMM/YMM registers must be distinct.  */
13303       modrm_reg = ins->modrm.reg;
13304       if (ins->rex & REX_R)
13305         modrm_reg += 8;
13306
13307       if (ins->modrm.rm == 4)
13308         {
13309           sib_index = ins->sib.index;
13310           if (ins->rex & REX_X)
13311             sib_index += 8;
13312         }
13313
13314       if (reg == modrm_reg || reg == sib_index)
13315         strcpy (ins->obufp, "/(bad)");
13316       if (modrm_reg == sib_index || modrm_reg == reg)
13317         strcat (ins->op_out[0], "/(bad)");
13318       if (sib_index == modrm_reg || sib_index == reg)
13319         strcat (ins->op_out[1], "/(bad)");
13320
13321       return;
13322
13323     case tmm_mode:
13324       /* All 3 TMM registers must be distinct.  */
13325       if (reg >= 8)
13326         oappend (ins, "(bad)");
13327       else
13328         {
13329           /* This must be the 3rd operand.  */
13330           if (ins->obufp != ins->op_out[2])
13331             abort ();
13332           oappend (ins, ins->names_tmm[reg]);
13333           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13334             strcpy (ins->obufp, "/(bad)");
13335         }
13336
13337       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13338           || ins->modrm.rm == reg)
13339         {
13340           if (ins->modrm.reg <= 8
13341               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13342             strcat (ins->op_out[0], "/(bad)");
13343           if (ins->modrm.rm <= 8
13344               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13345             strcat (ins->op_out[1], "/(bad)");
13346         }
13347
13348       return;
13349     }
13350
13351   switch (ins->vex.length)
13352     {
13353     case 128:
13354       switch (bytemode)
13355         {
13356         case x_mode:
13357           names = ins->names_xmm;
13358           break;
13359         case dq_mode:
13360           if (ins->rex & REX_W)
13361             names = ins->names64;
13362           else
13363             names = ins->names32;
13364           break;
13365         case mask_bd_mode:
13366         case mask_mode:
13367           if (reg > 0x7)
13368             {
13369               oappend (ins, "(bad)");
13370               return;
13371             }
13372           names = ins->names_mask;
13373           break;
13374         default:
13375           abort ();
13376           return;
13377         }
13378       break;
13379     case 256:
13380       switch (bytemode)
13381         {
13382         case x_mode:
13383           names = ins->names_ymm;
13384           break;
13385         case mask_bd_mode:
13386         case mask_mode:
13387           if (reg > 0x7)
13388             {
13389               oappend (ins, "(bad)");
13390               return;
13391             }
13392           names = ins->names_mask;
13393           break;
13394         default:
13395           /* See PR binutils/20893 for a reproducer.  */
13396           oappend (ins, "(bad)");
13397           return;
13398         }
13399       break;
13400     case 512:
13401       names = ins->names_zmm;
13402       break;
13403     default:
13404       abort ();
13405       break;
13406     }
13407   oappend (ins, names[reg]);
13408 }
13409
13410 static void
13411 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13412 {
13413   if (ins->modrm.mod == 3)
13414     OP_VEX (ins, bytemode, sizeflag);
13415 }
13416
13417 static void
13418 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13419 {
13420   OP_VEX (ins, bytemode, sizeflag);
13421
13422   if (ins->vex.w)
13423     {
13424       /* Swap 2nd and 3rd operands.  */
13425       strcpy (ins->scratchbuf, ins->op_out[2]);
13426       strcpy (ins->op_out[2], ins->op_out[1]);
13427       strcpy (ins->op_out[1], ins->scratchbuf);
13428     }
13429 }
13430
13431 static void
13432 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13433 {
13434   int reg;
13435   const char **names = ins->names_xmm;
13436
13437   FETCH_DATA (ins->info, ins->codep + 1);
13438   reg = *ins->codep++;
13439
13440   if (bytemode != x_mode && bytemode != scalar_mode)
13441     abort ();
13442
13443   reg >>= 4;
13444   if (ins->address_mode != mode_64bit)
13445     reg &= 7;
13446
13447   if (bytemode == x_mode && ins->vex.length == 256)
13448     names = ins->names_ymm;
13449
13450   oappend (ins, names[reg]);
13451
13452   if (ins->vex.w)
13453     {
13454       /* Swap 3rd and 4th operands.  */
13455       strcpy (ins->scratchbuf, ins->op_out[3]);
13456       strcpy (ins->op_out[3], ins->op_out[2]);
13457       strcpy (ins->op_out[2], ins->scratchbuf);
13458     }
13459 }
13460
13461 static void
13462 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13463           int sizeflag ATTRIBUTE_UNUSED)
13464 {
13465   ins->scratchbuf[0] = '$';
13466   print_operand_value (ins, ins->scratchbuf + 1, 1, ins->codep[-1] & 0xf);
13467   oappend_maybe_intel (ins, ins->scratchbuf);
13468 }
13469
13470 static void
13471 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13472              int sizeflag ATTRIBUTE_UNUSED)
13473 {
13474   unsigned int cmp_type;
13475
13476   if (!ins->vex.evex)
13477     abort ();
13478
13479   FETCH_DATA (ins->info, ins->codep + 1);
13480   cmp_type = *ins->codep++ & 0xff;
13481   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13482      If it's the case, print suffix, otherwise - print the immediate.  */
13483   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13484       && cmp_type != 3
13485       && cmp_type != 7)
13486     {
13487       char suffix[3];
13488       char *p = ins->mnemonicendp - 2;
13489
13490       /* vpcmp* can have both one- and two-lettered suffix.  */
13491       if (p[0] == 'p')
13492         {
13493           p++;
13494           suffix[0] = p[0];
13495           suffix[1] = '\0';
13496         }
13497       else
13498         {
13499           suffix[0] = p[0];
13500           suffix[1] = p[1];
13501           suffix[2] = '\0';
13502         }
13503
13504       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13505       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13506     }
13507   else
13508     {
13509       /* We have a reserved extension byte.  Output it directly.  */
13510       ins->scratchbuf[0] = '$';
13511       print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
13512       oappend_maybe_intel (ins, ins->scratchbuf);
13513       ins->scratchbuf[0] = '\0';
13514     }
13515 }
13516
13517 static const struct op xop_cmp_op[] =
13518 {
13519   { STRING_COMMA_LEN ("lt") },
13520   { STRING_COMMA_LEN ("le") },
13521   { STRING_COMMA_LEN ("gt") },
13522   { STRING_COMMA_LEN ("ge") },
13523   { STRING_COMMA_LEN ("eq") },
13524   { STRING_COMMA_LEN ("neq") },
13525   { STRING_COMMA_LEN ("false") },
13526   { STRING_COMMA_LEN ("true") }
13527 };
13528
13529 static void
13530 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13531              int sizeflag ATTRIBUTE_UNUSED)
13532 {
13533   unsigned int cmp_type;
13534
13535   FETCH_DATA (ins->info, ins->codep + 1);
13536   cmp_type = *ins->codep++ & 0xff;
13537   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13538     {
13539       char suffix[3];
13540       char *p = ins->mnemonicendp - 2;
13541
13542       /* vpcom* can have both one- and two-lettered suffix.  */
13543       if (p[0] == 'm')
13544         {
13545           p++;
13546           suffix[0] = p[0];
13547           suffix[1] = '\0';
13548         }
13549       else
13550         {
13551           suffix[0] = p[0];
13552           suffix[1] = p[1];
13553           suffix[2] = '\0';
13554         }
13555
13556       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13557       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13558     }
13559   else
13560     {
13561       /* We have a reserved extension byte.  Output it directly.  */
13562       ins->scratchbuf[0] = '$';
13563       print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
13564       oappend_maybe_intel (ins, ins->scratchbuf);
13565       ins->scratchbuf[0] = '\0';
13566     }
13567 }
13568
13569 static const struct op pclmul_op[] =
13570 {
13571   { STRING_COMMA_LEN ("lql") },
13572   { STRING_COMMA_LEN ("hql") },
13573   { STRING_COMMA_LEN ("lqh") },
13574   { STRING_COMMA_LEN ("hqh") }
13575 };
13576
13577 static void
13578 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13579               int sizeflag ATTRIBUTE_UNUSED)
13580 {
13581   unsigned int pclmul_type;
13582
13583   FETCH_DATA (ins->info, ins->codep + 1);
13584   pclmul_type = *ins->codep++ & 0xff;
13585   switch (pclmul_type)
13586     {
13587     case 0x10:
13588       pclmul_type = 2;
13589       break;
13590     case 0x11:
13591       pclmul_type = 3;
13592       break;
13593     default:
13594       break;
13595     }
13596   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13597     {
13598       char suffix[4];
13599       char *p = ins->mnemonicendp - 3;
13600       suffix[0] = p[0];
13601       suffix[1] = p[1];
13602       suffix[2] = p[2];
13603       suffix[3] = '\0';
13604       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13605       ins->mnemonicendp += pclmul_op[pclmul_type].len;
13606     }
13607   else
13608     {
13609       /* We have a reserved extension byte.  Output it directly.  */
13610       ins->scratchbuf[0] = '$';
13611       print_operand_value (ins, ins->scratchbuf + 1, 1, pclmul_type);
13612       oappend_maybe_intel (ins, ins->scratchbuf);
13613       ins->scratchbuf[0] = '\0';
13614     }
13615 }
13616
13617 static void
13618 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13619 {
13620   /* Add proper suffix to "movsxd".  */
13621   char *p = ins->mnemonicendp;
13622
13623   switch (bytemode)
13624     {
13625     case movsxd_mode:
13626       if (!ins->intel_syntax)
13627         {
13628           USED_REX (REX_W);
13629           if (ins->rex & REX_W)
13630             {
13631               *p++ = 'l';
13632               *p++ = 'q';
13633               break;
13634             }
13635         }
13636
13637       *p++ = 'x';
13638       *p++ = 'd';
13639       break;
13640     default:
13641       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13642       break;
13643     }
13644
13645   ins->mnemonicendp = p;
13646   *p = '\0';
13647   OP_E (ins, bytemode, sizeflag);
13648 }
13649
13650 static void
13651 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13652 {
13653   unsigned int reg = ins->vex.register_specifier;
13654   unsigned int modrm_reg = ins->modrm.reg;
13655   unsigned int modrm_rm = ins->modrm.rm;
13656
13657   /* Calc destination register number.  */
13658   if (ins->rex & REX_R)
13659     modrm_reg += 8;
13660   if (!ins->vex.r)
13661     modrm_reg += 16;
13662
13663   /* Calc src1 register number.  */
13664   if (ins->address_mode != mode_64bit)
13665     reg &= 7;
13666   else if (ins->vex.evex && !ins->vex.v)
13667     reg += 16;
13668
13669   /* Calc src2 register number.  */
13670   if (ins->modrm.mod == 3)
13671     {
13672       if (ins->rex & REX_B)
13673         modrm_rm += 8;
13674       if (ins->rex & REX_X)
13675         modrm_rm += 16;
13676     }
13677
13678   /* Destination and source registers must be distinct, output bad if
13679      dest == src1 or dest == src2.  */
13680   if (modrm_reg == reg
13681       || (ins->modrm.mod == 3
13682           && modrm_reg == modrm_rm))
13683     {
13684       oappend (ins, "(bad)");
13685     }
13686   else
13687     OP_XMM (ins, bytemode, sizeflag);
13688 }
13689
13690 static void
13691 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13692 {
13693   if (ins->modrm.mod != 3 || !ins->vex.b)
13694     return;
13695
13696   switch (bytemode)
13697     {
13698     case evex_rounding_64_mode:
13699       if (ins->address_mode != mode_64bit || !ins->vex.w)
13700         return;
13701       /* Fall through.  */
13702     case evex_rounding_mode:
13703       ins->evex_used |= EVEX_b_used;
13704       oappend (ins, names_rounding[ins->vex.ll]);
13705       break;
13706     case evex_sae_mode:
13707       ins->evex_used |= EVEX_b_used;
13708       oappend (ins, "{");
13709       break;
13710     default:
13711       abort ();
13712     }
13713   oappend (ins, "sae}");
13714 }