opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2022 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #include <limits.h>
  23 #ifndef CHAR_BIT
  24 #define CHAR_BIT 8
  25 #endif
  26
  27 /* Position of cpu flags bitfiled.  */
  28
  29 enum
  30 {
  31   /* i186 or better required */
  32   Cpu186 = 0,
  33   /* i286 or better required */
  34   Cpu286,
  35   /* i386 or better required */
  36   Cpu386,
  37   /* i486 or better required */
  38   Cpu486,
  39   /* i585 or better required */
  40   Cpu586,
  41   /* i686 or better required */
  42   Cpu686,
  43   /* CMOV Instruction support required */
  44   CpuCMOV,
  45   /* FXSR Instruction support required */
  46   CpuFXSR,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* LZCNT support required */
  88   CpuLZCNT,
  89   /* POPCNT support required */
  90   CpuPOPCNT,
  91   /* SSE4.1 support required */
  92   CpuSSE4_1,
  93   /* SSE4.2 support required */
  94   CpuSSE4_2,
  95   /* AVX support required */
  96   CpuAVX,
  97   /* AVX2 support required */
  98   CpuAVX2,
  99   /* Intel AVX-512 Foundation Instructions support required */
 100   CpuAVX512F,
 101   /* Intel AVX-512 Conflict Detection Instructions support required */
 102   CpuAVX512CD,
 103   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 104      required */
 105   CpuAVX512ER,
 106   /* Intel AVX-512 Prefetch Instructions support required */
 107   CpuAVX512PF,
 108   /* Intel AVX-512 VL Instructions support required.  */
 109   CpuAVX512VL,
 110   /* Intel AVX-512 DQ Instructions support required.  */
 111   CpuAVX512DQ,
 112   /* Intel AVX-512 BW Instructions support required.  */
 113   CpuAVX512BW,
 114   /* Intel L1OM support required */
 115   CpuL1OM,
 116   /* Intel K1OM support required */
 117   CpuK1OM,
 118   /* Intel IAMCU support required */
 119   CpuIAMCU,
 120   /* Xsave/xrstor New Instructions support required */
 121   CpuXsave,
 122   /* Xsaveopt New Instructions support required */
 123   CpuXsaveopt,
 124   /* AES support required */
 125   CpuAES,
 126   /* PCLMUL support required */
 127   CpuPCLMUL,
 128   /* FMA support required */
 129   CpuFMA,
 130   /* FMA4 support required */
 131   CpuFMA4,
 132   /* XOP support required */
 133   CpuXOP,
 134   /* LWP support required */
 135   CpuLWP,
 136   /* BMI support required */
 137   CpuBMI,
 138   /* TBM support required */
 139   CpuTBM,
 140   /* MOVBE Instruction support required */
 141   CpuMovbe,
 142   /* CMPXCHG16B instruction support required.  */
 143   CpuCX16,
 144   /* EPT Instructions required */
 145   CpuEPT,
 146   /* RDTSCP Instruction support required */
 147   CpuRdtscp,
 148   /* FSGSBASE Instructions required */
 149   CpuFSGSBase,
 150   /* RDRND Instructions required */
 151   CpuRdRnd,
 152   /* F16C Instructions required */
 153   CpuF16C,
 154   /* Intel BMI2 support required */
 155   CpuBMI2,
 156   /* HLE support required */
 157   CpuHLE,
 158   /* RTM support required */
 159   CpuRTM,
 160   /* INVPCID Instructions required */
 161   CpuINVPCID,
 162   /* VMFUNC Instruction required */
 163   CpuVMFUNC,
 164   /* Intel MPX Instructions required  */
 165   CpuMPX,
 166   /* 64bit support available, used by -march= in assembler.  */
 167   CpuLM,
 168   /* RDRSEED instruction required.  */
 169   CpuRDSEED,
 170   /* Multi-presisionn add-carry instructions are required.  */
 171   CpuADX,
 172   /* Supports prefetchw and prefetch instructions.  */
 173   CpuPRFCHW,
 174   /* SMAP instructions required.  */
 175   CpuSMAP,
 176   /* SHA instructions required.  */
 177   CpuSHA,
 178   /* CLFLUSHOPT instruction required */
 179   CpuClflushOpt,
 180   /* XSAVES/XRSTORS instruction required */
 181   CpuXSAVES,
 182   /* XSAVEC instruction required */
 183   CpuXSAVEC,
 184   /* PREFETCHWT1 instruction required */
 185   CpuPREFETCHWT1,
 186   /* SE1 instruction required */
 187   CpuSE1,
 188   /* CLWB instruction required */
 189   CpuCLWB,
 190   /* Intel AVX-512 IFMA Instructions support required.  */
 191   CpuAVX512IFMA,
 192   /* Intel AVX-512 VBMI Instructions support required.  */
 193   CpuAVX512VBMI,
 194   /* Intel AVX-512 4FMAPS Instructions support required.  */
 195   CpuAVX512_4FMAPS,
 196   /* Intel AVX-512 4VNNIW Instructions support required.  */
 197   CpuAVX512_4VNNIW,
 198   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 199   CpuAVX512_VPOPCNTDQ,
 200   /* Intel AVX-512 VBMI2 Instructions support required.  */
 201   CpuAVX512_VBMI2,
 202   /* Intel AVX-512 VNNI Instructions support required.  */
 203   CpuAVX512_VNNI,
 204   /* Intel AVX-512 BITALG Instructions support required.  */
 205   CpuAVX512_BITALG,
 206   /* Intel AVX-512 BF16 Instructions support required.  */
 207   CpuAVX512_BF16,
 208   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 209   CpuAVX512_VP2INTERSECT,
 210   /* TDX Instructions support required.  */
 211   CpuTDX,
 212   /* Intel AVX VNNI Instructions support required.  */
 213   CpuAVX_VNNI,
 214   /* Intel AVX-512 FP16 Instructions support required.  */
 215   CpuAVX512_FP16,
 216   /* mwaitx instruction required */
 217   CpuMWAITX,
 218   /* Clzero instruction required */
 219   CpuCLZERO,
 220   /* OSPKE instruction required */
 221   CpuOSPKE,
 222   /* RDPID instruction required */
 223   CpuRDPID,
 224   /* PTWRITE instruction required */
 225   CpuPTWRITE,
 226   /* CET instructions support required */
 227   CpuIBT,
 228   CpuSHSTK,
 229   /* AMX-INT8 instructions required */
 230   CpuAMX_INT8,
 231   /* AMX-BF16 instructions required */
 232   CpuAMX_BF16,
 233   /* AMX-TILE instructions required */
 234   CpuAMX_TILE,
 235   /* GFNI instructions required */
 236   CpuGFNI,
 237   /* VAES instructions required */
 238   CpuVAES,
 239   /* VPCLMULQDQ instructions required */
 240   CpuVPCLMULQDQ,
 241   /* WBNOINVD instructions required */
 242   CpuWBNOINVD,
 243   /* PCONFIG instructions required */
 244   CpuPCONFIG,
 245   /* WAITPKG instructions required */
 246   CpuWAITPKG,
 247   /* UINTR instructions required */
 248   CpuUINTR,
 249   /* CLDEMOTE instruction required */
 250   CpuCLDEMOTE,
 251   /* MOVDIRI instruction support required */
 252   CpuMOVDIRI,
 253   /* MOVDIRR64B instruction required */
 254   CpuMOVDIR64B,
 255   /* ENQCMD instruction required */
 256   CpuENQCMD,
 257   /* SERIALIZE instruction required */
 258   CpuSERIALIZE,
 259   /* RDPRU instruction required */
 260   CpuRDPRU,
 261   /* MCOMMIT instruction required */
 262   CpuMCOMMIT,
 263   /* SEV-ES instruction(s) required */
 264   CpuSEV_ES,
 265   /* TSXLDTRK instruction required */
 266   CpuTSXLDTRK,
 267   /* KL instruction support required */
 268   CpuKL,
 269   /* WideKL instruction support required */
 270   CpuWideKL,
 271   /* HRESET instruction required */
 272   CpuHRESET,
 273   /* INVLPGB instructions required */
 274   CpuINVLPGB,
 275   /* TLBSYNC instructions required */
 276   CpuTLBSYNC,
 277   /* SNP instructions required */
 278   CpuSNP,
 279   /* 64bit support required  */
 280   Cpu64,
 281   /* Not supported in the 64bit mode  */
 282   CpuNo64,
 283   /* The last bitfield in i386_cpu_flags.  */
 284   CpuMax = CpuNo64
 285 };
 286
 287 #define CpuNumOfUints \
 288   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 289 #define CpuNumOfBits \
 290   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 291
 292 /* If you get a compiler error for zero width of the unused field,
 293    comment it out.  */
 294 #define CpuUnused       (CpuMax + 1)
 295
 296 /* We can check if an instruction is available with array instead
 297    of bitfield. */
 298 typedef union i386_cpu_flags
 299 {
 300   struct
 301     {
 302       unsigned int cpui186:1;
 303       unsigned int cpui286:1;
 304       unsigned int cpui386:1;
 305       unsigned int cpui486:1;
 306       unsigned int cpui586:1;
 307       unsigned int cpui686:1;
 308       unsigned int cpucmov:1;
 309       unsigned int cpufxsr:1;
 310       unsigned int cpuclflush:1;
 311       unsigned int cpunop:1;
 312       unsigned int cpusyscall:1;
 313       unsigned int cpu8087:1;
 314       unsigned int cpu287:1;
 315       unsigned int cpu387:1;
 316       unsigned int cpu687:1;
 317       unsigned int cpufisttp:1;
 318       unsigned int cpummx:1;
 319       unsigned int cpusse:1;
 320       unsigned int cpusse2:1;
 321       unsigned int cpua3dnow:1;
 322       unsigned int cpua3dnowa:1;
 323       unsigned int cpusse3:1;
 324       unsigned int cpupadlock:1;
 325       unsigned int cpusvme:1;
 326       unsigned int cpuvmx:1;
 327       unsigned int cpusmx:1;
 328       unsigned int cpussse3:1;
 329       unsigned int cpusse4a:1;
 330       unsigned int cpulzcnt:1;
 331       unsigned int cpupopcnt:1;
 332       unsigned int cpusse4_1:1;
 333       unsigned int cpusse4_2:1;
 334       unsigned int cpuavx:1;
 335       unsigned int cpuavx2:1;
 336       unsigned int cpuavx512f:1;
 337       unsigned int cpuavx512cd:1;
 338       unsigned int cpuavx512er:1;
 339       unsigned int cpuavx512pf:1;
 340       unsigned int cpuavx512vl:1;
 341       unsigned int cpuavx512dq:1;
 342       unsigned int cpuavx512bw:1;
 343       unsigned int cpul1om:1;
 344       unsigned int cpuk1om:1;
 345       unsigned int cpuiamcu:1;
 346       unsigned int cpuxsave:1;
 347       unsigned int cpuxsaveopt:1;
 348       unsigned int cpuaes:1;
 349       unsigned int cpupclmul:1;
 350       unsigned int cpufma:1;
 351       unsigned int cpufma4:1;
 352       unsigned int cpuxop:1;
 353       unsigned int cpulwp:1;
 354       unsigned int cpubmi:1;
 355       unsigned int cputbm:1;
 356       unsigned int cpumovbe:1;
 357       unsigned int cpucx16:1;
 358       unsigned int cpuept:1;
 359       unsigned int cpurdtscp:1;
 360       unsigned int cpufsgsbase:1;
 361       unsigned int cpurdrnd:1;
 362       unsigned int cpuf16c:1;
 363       unsigned int cpubmi2:1;
 364       unsigned int cpuhle:1;
 365       unsigned int cpurtm:1;
 366       unsigned int cpuinvpcid:1;
 367       unsigned int cpuvmfunc:1;
 368       unsigned int cpumpx:1;
 369       unsigned int cpulm:1;
 370       unsigned int cpurdseed:1;
 371       unsigned int cpuadx:1;
 372       unsigned int cpuprfchw:1;
 373       unsigned int cpusmap:1;
 374       unsigned int cpusha:1;
 375       unsigned int cpuclflushopt:1;
 376       unsigned int cpuxsaves:1;
 377       unsigned int cpuxsavec:1;
 378       unsigned int cpuprefetchwt1:1;
 379       unsigned int cpuse1:1;
 380       unsigned int cpuclwb:1;
 381       unsigned int cpuavx512ifma:1;
 382       unsigned int cpuavx512vbmi:1;
 383       unsigned int cpuavx512_4fmaps:1;
 384       unsigned int cpuavx512_4vnniw:1;
 385       unsigned int cpuavx512_vpopcntdq:1;
 386       unsigned int cpuavx512_vbmi2:1;
 387       unsigned int cpuavx512_vnni:1;
 388       unsigned int cpuavx512_bitalg:1;
 389       unsigned int cpuavx512_bf16:1;
 390       unsigned int cpuavx512_vp2intersect:1;
 391       unsigned int cputdx:1;
 392       unsigned int cpuavx_vnni:1;
 393       unsigned int cpuavx512_fp16:1;
 394       unsigned int cpumwaitx:1;
 395       unsigned int cpuclzero:1;
 396       unsigned int cpuospke:1;
 397       unsigned int cpurdpid:1;
 398       unsigned int cpuptwrite:1;
 399       unsigned int cpuibt:1;
 400       unsigned int cpushstk:1;
 401       unsigned int cpuamx_int8:1;
 402       unsigned int cpuamx_bf16:1;
 403       unsigned int cpuamx_tile:1;
 404       unsigned int cpugfni:1;
 405       unsigned int cpuvaes:1;
 406       unsigned int cpuvpclmulqdq:1;
 407       unsigned int cpuwbnoinvd:1;
 408       unsigned int cpupconfig:1;
 409       unsigned int cpuwaitpkg:1;
 410       unsigned int cpuuintr:1;
 411       unsigned int cpucldemote:1;
 412       unsigned int cpumovdiri:1;
 413       unsigned int cpumovdir64b:1;
 414       unsigned int cpuenqcmd:1;
 415       unsigned int cpuserialize:1;
 416       unsigned int cpurdpru:1;
 417       unsigned int cpumcommit:1;
 418       unsigned int cpusev_es:1;
 419       unsigned int cputsxldtrk:1;
 420       unsigned int cpukl:1;
 421       unsigned int cpuwidekl:1;
 422       unsigned int cpuhreset:1;
 423       unsigned int cpuinvlpgb:1;
 424       unsigned int cputlbsync:1;
 425       unsigned int cpusnp:1;
 426       unsigned int cpu64:1;
 427       unsigned int cpuno64:1;
 428 #ifdef CpuUnused
 429       unsigned int unused:(CpuNumOfBits - CpuUnused);
 430 #endif
 431     } bitfield;
 432   unsigned int array[CpuNumOfUints];
 433 } i386_cpu_flags;
 434
 435 /* Position of opcode_modifier bits.  */
 436
 437 enum
 438 {
 439   /* has direction bit. */
 440   D = 0,
 441   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 442      canonical way; the base_opcode field should hold the encoding for byte
 443      operands  */
 444   W,
 445   /* load form instruction. Must be placed before store form.  */
 446   Load,
 447   /* insn has a modrm byte. */
 448   Modrm,
 449   /* special case for jump insns; value has to be 1 */
 450 #define JUMP 1
 451   /* call and jump */
 452 #define JUMP_DWORD 2
 453   /* loop and jecxz */
 454 #define JUMP_BYTE 3
 455   /* special case for intersegment leaps/calls */
 456 #define JUMP_INTERSEGMENT 4
 457   /* absolute address for jump */
 458 #define JUMP_ABSOLUTE 5
 459   Jump,
 460   /* FP insn memory format bit, sized by 0x4 */
 461   FloatMF,
 462   /* src/dest swap for floats. */
 463   FloatR,
 464   /* needs size prefix if in 32-bit mode */
 465 #define SIZE16 1
 466   /* needs size prefix if in 16-bit mode */
 467 #define SIZE32 2
 468   /* needs size prefix if in 64-bit mode */
 469 #define SIZE64 3
 470   Size,
 471   /* check register size.  */
 472   CheckRegSize,
 473   /* Instrucion requires that destination must be distinct from source
 474      registers.  */
 475   DistinctDest,
 476   /* instruction ignores operand size prefix and in Intel mode ignores
 477      mnemonic size suffix check.  */
 478 #define IGNORESIZE      1
 479   /* default insn size depends on mode */
 480 #define DEFAULTSIZE     2
 481   MnemonicSize,
 482   /* any memory size */
 483   Anysize,
 484   /* b suffix on instruction illegal */
 485   No_bSuf,
 486   /* w suffix on instruction illegal */
 487   No_wSuf,
 488   /* l suffix on instruction illegal */
 489   No_lSuf,
 490   /* s suffix on instruction illegal */
 491   No_sSuf,
 492   /* q suffix on instruction illegal */
 493   No_qSuf,
 494   /* long double suffix on instruction illegal */
 495   No_ldSuf,
 496   /* instruction needs FWAIT */
 497   FWait,
 498   /* IsString provides for a quick test for string instructions, and
 499      its actual value also indicates which of the operands (if any)
 500      requires use of the %es segment.  */
 501 #define IS_STRING_ES_OP0 2
 502 #define IS_STRING_ES_OP1 3
 503   IsString,
 504   /* RegMem is for instructions with a modrm byte where the register
 505      destination operand should be encoded in the mod and regmem fields.
 506      Normally, it will be encoded in the reg field. We add a RegMem
 507      flag to indicate that it should be encoded in the regmem field.  */
 508   RegMem,
 509   /* quick test if branch instruction is MPX supported */
 510   BNDPrefixOk,
 511   /* fake an extra reg operand for clr, imul and special register
 512      processing for some instructions.  */
 513   RegKludge,
 514   /* An implicit xmm0 as the first operand */
 515   Implicit1stXmm0,
 516 #define PrefixNone              0
 517 #define PrefixRep               1
 518 #define PrefixHLERelease        2 /* Okay with an XRELEASE (0xf3) prefix. */
 519 #define PrefixNoTrack           3
 520   /* Prefixes implying "LOCK okay" must come after Lock. All others have
 521      to come before.  */
 522 #define PrefixLock              4
 523 #define PrefixHLELock           5 /* Okay with a LOCK prefix.  */
 524 #define PrefixHLEAny            6 /* Okay with or without a LOCK prefix.  */
 525   PrefixOk,
 526   /* Convert to DWORD */
 527   ToDword,
 528   /* Convert to QWORD */
 529   ToQword,
 530   /* Address prefix changes register operand */
 531   AddrPrefixOpReg,
 532   /* opcode is a prefix */
 533   IsPrefix,
 534   /* instruction has extension in 8 bit imm */
 535   ImmExt,
 536   /* instruction don't need Rex64 prefix.  */
 537   NoRex64,
 538   /* deprecated fp insn, gets a warning */
 539   Ugh,
 540   /* Intel AVX Instructions support via {vex} prefix */
 541   PseudoVexPrefix,
 542   /* insn has VEX prefix:
 543         1: 128bit VEX prefix (or operand dependent).
 544         2: 256bit VEX prefix.
 545         3: Scalar VEX prefix.
 546    */
 547 #define VEX128          1
 548 #define VEX256          2
 549 #define VEXScalar       3
 550   Vex,
 551   /* How to encode VEX.vvvv:
 552      0: VEX.vvvv must be 1111b.
 553      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 554         the content of source registers will be preserved.
 555         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 556         where the content of first source register will be overwritten
 557         by the result.
 558         VEX.NDD2.  The second destination register operand is encoded in
 559         VEX.vvvv for instructions with 2 destination register operands.
 560         For assembler, there are no difference between VEX.NDS, VEX.DDS
 561         and VEX.NDD2.
 562      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 563      instructions with 1 destination register operand.
 564      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 565         of the operands can access a memory location.
 566    */
 567 #define VEXXDS  1
 568 #define VEXNDD  2
 569 #define VEXLWP  3
 570   VexVVVV,
 571   /* How the VEX.W bit is used:
 572      0: Set by the REX.W bit.
 573      1: VEX.W0.  Should always be 0.
 574      2: VEX.W1.  Should always be 1.
 575      3: VEX.WIG. The VEX.W bit is ignored.
 576    */
 577 #define VEXW0   1
 578 #define VEXW1   2
 579 #define VEXWIG  3
 580   VexW,
 581   /* Opcode encoding space (values chosen to be usable directly in
 582      VEX/XOP mmmmm and EVEX mm fields):
 583      0: Base opcode space.
 584      1: 0F opcode prefix / space.
 585      2: 0F38 opcode prefix / space.
 586      3: 0F3A opcode prefix / space.
 587      5: EVEXMAP5 opcode prefix / space.
 588      6: EVEXMAP6 opcode prefix / space.
 589      8: XOP 08 opcode space.
 590      9: XOP 09 opcode space.
 591      A: XOP 0A opcode space.
 592    */
 593 #define SPACE_BASE      0
 594 #define SPACE_0F        1
 595 #define SPACE_0F38      2
 596 #define SPACE_0F3A      3
 597 #define SPACE_EVEXMAP5  5
 598 #define SPACE_EVEXMAP6  6
 599 #define SPACE_XOP08     8
 600 #define SPACE_XOP09     9
 601 #define SPACE_XOP0A     0xA
 602   OpcodeSpace,
 603   /* Opcode prefix (values chosen to be usable directly in
 604      VEX/XOP/EVEX pp fields):
 605      0: None
 606      1: Add 0x66 opcode prefix.
 607      2: Add 0xf3 opcode prefix.
 608      3: Add 0xf2 opcode prefix.
 609    */
 610 #define PREFIX_NONE     0
 611 #define PREFIX_0X66     1
 612 #define PREFIX_0XF3     2
 613 #define PREFIX_0XF2     3
 614   OpcodePrefix,
 615   /* number of VEX source operands:
 616      0: <= 2 source operands.
 617      1: 2 XOP source operands.
 618      2: 3 source operands.
 619    */
 620 #define XOP2SOURCES     1
 621 #define VEX3SOURCES     2
 622   VexSources,
 623   /* Instruction with a mandatory SIB byte:
 624         1: 128bit vector register.
 625         2: 256bit vector register.
 626         3: 512bit vector register.
 627    */
 628 #define VECSIB128       1
 629 #define VECSIB256       2
 630 #define VECSIB512       3
 631 #define SIBMEM          4
 632   SIB,
 633
 634   /* SSE to AVX support required */
 635   SSE2AVX,
 636   /* No AVX equivalent */
 637   NoAVX,
 638
 639   /* insn has EVEX prefix:
 640         1: 512bit EVEX prefix.
 641         2: 128bit EVEX prefix.
 642         3: 256bit EVEX prefix.
 643         4: Length-ignored (LIG) EVEX prefix.
 644         5: Length determined from actual operands.
 645    */
 646 #define EVEX512                1
 647 #define EVEX128                2
 648 #define EVEX256                3
 649 #define EVEXLIG                4
 650 #define EVEXDYN                5
 651   EVex,
 652
 653   /* AVX512 masking support:
 654         1: Zeroing or merging masking depending on operands.
 655         2: Merging-masking.
 656         3: Both zeroing and merging masking.
 657    */
 658 #define DYNAMIC_MASKING 1
 659 #define MERGING_MASKING 2
 660 #define BOTH_MASKING    3
 661   Masking,
 662
 663   /* AVX512 broadcast support.  The number of bytes to broadcast is
 664      1 << (Broadcast - 1):
 665         1: Byte broadcast.
 666         2: Word broadcast.
 667         3: Dword broadcast.
 668         4: Qword broadcast.
 669    */
 670 #define BYTE_BROADCAST  1
 671 #define WORD_BROADCAST  2
 672 #define DWORD_BROADCAST 3
 673 #define QWORD_BROADCAST 4
 674   Broadcast,
 675
 676   /* Static rounding control is supported.  */
 677   StaticRounding,
 678
 679   /* Supress All Exceptions is supported.  */
 680   SAE,
 681
 682   /* Compressed Disp8*N attribute.  */
 683 #define DISP8_SHIFT_VL 7
 684   Disp8MemShift,
 685
 686   /* Default mask isn't allowed.  */
 687   NoDefMask,
 688
 689   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 690      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 691    */
 692   ImplicitQuadGroup,
 693
 694   /* Two source operands are swapped.  */
 695   SwapSources,
 696
 697   /* Support encoding optimization.  */
 698   Optimize,
 699
 700   /* AT&T mnemonic.  */
 701   ATTMnemonic,
 702   /* AT&T syntax.  */
 703   ATTSyntax,
 704   /* Intel syntax.  */
 705   IntelSyntax,
 706   /* ISA64: Don't change the order without other code adjustments.
 707         0: Common to AMD64 and Intel64.
 708         1: AMD64.
 709         2: Intel64.
 710         3: Only in Intel64.
 711    */
 712 #define AMD64           1
 713 #define INTEL64         2
 714 #define INTEL64ONLY     3
 715   ISA64,
 716   /* The last bitfield in i386_opcode_modifier.  */
 717   Opcode_Modifier_Num
 718 };
 719
 720 typedef struct i386_opcode_modifier
 721 {
 722   unsigned int d:1;
 723   unsigned int w:1;
 724   unsigned int load:1;
 725   unsigned int modrm:1;
 726   unsigned int jump:3;
 727   unsigned int floatmf:1;
 728   unsigned int floatr:1;
 729   unsigned int size:2;
 730   unsigned int checkregsize:1;
 731   unsigned int distinctdest:1;
 732   unsigned int mnemonicsize:2;
 733   unsigned int anysize:1;
 734   unsigned int no_bsuf:1;
 735   unsigned int no_wsuf:1;
 736   unsigned int no_lsuf:1;
 737   unsigned int no_ssuf:1;
 738   unsigned int no_qsuf:1;
 739   unsigned int no_ldsuf:1;
 740   unsigned int fwait:1;
 741   unsigned int isstring:2;
 742   unsigned int regmem:1;
 743   unsigned int bndprefixok:1;
 744   unsigned int regkludge:1;
 745   unsigned int implicit1stxmm0:1;
 746   unsigned int prefixok:3;
 747   unsigned int todword:1;
 748   unsigned int toqword:1;
 749   unsigned int addrprefixopreg:1;
 750   unsigned int isprefix:1;
 751   unsigned int immext:1;
 752   unsigned int norex64:1;
 753   unsigned int ugh:1;
 754   unsigned int pseudovexprefix:1;
 755   unsigned int vex:2;
 756   unsigned int vexvvvv:2;
 757   unsigned int vexw:2;
 758   unsigned int opcodespace:4;
 759   unsigned int opcodeprefix:2;
 760   unsigned int vexsources:2;
 761   unsigned int sib:3;
 762   unsigned int sse2avx:1;
 763   unsigned int noavx:1;
 764   unsigned int evex:3;
 765   unsigned int masking:2;
 766   unsigned int broadcast:3;
 767   unsigned int staticrounding:1;
 768   unsigned int sae:1;
 769   unsigned int disp8memshift:3;
 770   unsigned int nodefmask:1;
 771   unsigned int implicitquadgroup:1;
 772   unsigned int swapsources:1;
 773   unsigned int optimize:1;
 774   unsigned int attmnemonic:1;
 775   unsigned int attsyntax:1;
 776   unsigned int intelsyntax:1;
 777   unsigned int isa64:2;
 778 } i386_opcode_modifier;
 779
 780 /* Operand classes.  */
 781
 782 #define CLASS_WIDTH 4
 783 enum operand_class
 784 {
 785   ClassNone,
 786   Reg, /* GPRs and FP regs, distinguished by operand size */
 787   SReg, /* Segment register */
 788   RegCR, /* Control register */
 789   RegDR, /* Debug register */
 790   RegTR, /* Test register */
 791   RegMMX, /* MMX register */
 792   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 793   RegMask, /* Vector Mask register */
 794   RegBND, /* Bound register */
 795 };
 796
 797 /* Special operand instances.  */
 798
 799 #define INSTANCE_WIDTH 3
 800 enum operand_instance
 801 {
 802   InstanceNone,
 803   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 804   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 805   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 806   RegB,  /* %bl / %bx / %ebx / %rbx */
 807 };
 808
 809 /* Position of operand_type bits.  */
 810
 811 enum
 812 {
 813   /* Class and Instance */
 814   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 815   /* 1 bit immediate */
 816   Imm1,
 817   /* 8 bit immediate */
 818   Imm8,
 819   /* 8 bit immediate sign extended */
 820   Imm8S,
 821   /* 16 bit immediate */
 822   Imm16,
 823   /* 32 bit immediate */
 824   Imm32,
 825   /* 32 bit immediate sign extended */
 826   Imm32S,
 827   /* 64 bit immediate */
 828   Imm64,
 829   /* 8bit/16bit/32bit displacements are used in different ways,
 830      depending on the instruction.  For jumps, they specify the
 831      size of the PC relative displacement, for instructions with
 832      memory operand, they specify the size of the offset relative
 833      to the base register, and for instructions with memory offset
 834      such as `mov 1234,%al' they specify the size of the offset
 835      relative to the segment base.  */
 836   /* 8 bit displacement */
 837   Disp8,
 838   /* 16 bit displacement */
 839   Disp16,
 840   /* 32 bit displacement */
 841   Disp32,
 842   /* 32 bit signed displacement */
 843   Disp32S,
 844   /* 64 bit displacement */
 845   Disp64,
 846   /* Register which can be used for base or index in memory operand.  */
 847   BaseIndex,
 848   /* BYTE size. */
 849   Byte,
 850   /* WORD size. 2 byte */
 851   Word,
 852   /* DWORD size. 4 byte */
 853   Dword,
 854   /* FWORD size. 6 byte */
 855   Fword,
 856   /* QWORD size. 8 byte */
 857   Qword,
 858   /* TBYTE size. 10 byte */
 859   Tbyte,
 860   /* XMMWORD size. */
 861   Xmmword,
 862   /* YMMWORD size. */
 863   Ymmword,
 864   /* ZMMWORD size.  */
 865   Zmmword,
 866   /* TMMWORD size.  */
 867   Tmmword,
 868   /* Unspecified memory size.  */
 869   Unspecified,
 870
 871   /* The number of bits in i386_operand_type.  */
 872   OTNum
 873 };
 874
 875 #define OTNumOfUints \
 876   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 877 #define OTNumOfBits \
 878   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 879
 880 /* If you get a compiler error for zero width of the unused field,
 881    comment it out.  */
 882 #define OTUnused                OTNum
 883
 884 typedef union i386_operand_type
 885 {
 886   struct
 887     {
 888       unsigned int class:CLASS_WIDTH;
 889       unsigned int instance:INSTANCE_WIDTH;
 890       unsigned int imm1:1;
 891       unsigned int imm8:1;
 892       unsigned int imm8s:1;
 893       unsigned int imm16:1;
 894       unsigned int imm32:1;
 895       unsigned int imm32s:1;
 896       unsigned int imm64:1;
 897       unsigned int disp8:1;
 898       unsigned int disp16:1;
 899       unsigned int disp32:1;
 900       unsigned int disp32s:1;
 901       unsigned int disp64:1;
 902       unsigned int baseindex:1;
 903       unsigned int byte:1;
 904       unsigned int word:1;
 905       unsigned int dword:1;
 906       unsigned int fword:1;
 907       unsigned int qword:1;
 908       unsigned int tbyte:1;
 909       unsigned int xmmword:1;
 910       unsigned int ymmword:1;
 911       unsigned int zmmword:1;
 912       unsigned int tmmword:1;
 913       unsigned int unspecified:1;
 914 #ifdef OTUnused
 915       unsigned int unused:(OTNumOfBits - OTUnused);
 916 #endif
 917     } bitfield;
 918   unsigned int array[OTNumOfUints];
 919 } i386_operand_type;
 920
 921 typedef struct insn_template
 922 {
 923   /* instruction name sans width suffix ("mov" for movl insns) */
 924   char *name;
 925
 926   /* base_opcode is the fundamental opcode byte without optional
 927      prefix(es).  */
 928   unsigned int base_opcode:16;
 929 #define Opcode_D        0x2 /* Direction bit:
 930                                set if Reg --> Regmem;
 931                                unset if Regmem --> Reg. */
 932 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 933 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 934 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 935 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 936
 937 /* (Fake) base opcode value for pseudo prefixes.  */
 938 #define PSEUDO_PREFIX 0
 939
 940   /* extension_opcode is the 3 bit extension for group <n> insns.
 941      This field is also used to store the 8-bit opcode suffix for the
 942      AMD 3DNow! instructions.
 943      If this template has no extension opcode (the usual case) use None
 944      Instructions */
 945   signed int extension_opcode:9;
 946 #define None (-1)               /* If no extension_opcode is possible.  */
 947
 948 /* Pseudo prefixes.  */
 949 #define Prefix_Disp8            0       /* {disp8} */
 950 #define Prefix_Disp16           1       /* {disp16} */
 951 #define Prefix_Disp32           2       /* {disp32} */
 952 #define Prefix_Load             3       /* {load} */
 953 #define Prefix_Store            4       /* {store} */
 954 #define Prefix_VEX              5       /* {vex} */
 955 #define Prefix_VEX3             6       /* {vex3} */
 956 #define Prefix_EVEX             7       /* {evex} */
 957 #define Prefix_REX              8       /* {rex} */
 958 #define Prefix_NoOptimize       9       /* {nooptimize} */
 959
 960   /* how many operands */
 961   unsigned int operands:3;
 962
 963   /* the bits in opcode_modifier are used to generate the final opcode from
 964      the base_opcode.  These bits also are used to detect alternate forms of
 965      the same instruction */
 966   i386_opcode_modifier opcode_modifier;
 967
 968   /* cpu feature flags */
 969   i386_cpu_flags cpu_flags;
 970
 971   /* operand_types[i] describes the type of operand i.  This is made
 972      by OR'ing together all of the possible type masks.  (e.g.
 973      'operand_types[i] = Reg|Imm' specifies that operand i can be
 974      either a register or an immediate operand.  */
 975   i386_operand_type operand_types[MAX_OPERANDS];
 976 }
 977 insn_template;
 978
 979 extern const insn_template i386_optab[];
 980
 981 /* these are for register name --> number & type hash lookup */
 982 typedef struct
 983 {
 984   const char *reg_name;
 985   i386_operand_type reg_type;
 986   unsigned char reg_flags;
 987 #define RegRex      0x1  /* Extended register.  */
 988 #define RegRex64    0x2  /* Extended 8 bit register.  */
 989 #define RegVRex     0x4  /* Extended vector register.  */
 990   unsigned char reg_num;
 991 #define RegIP   ((unsigned char ) ~0)
 992 /* EIZ and RIZ are fake index registers.  */
 993 #define RegIZ   (RegIP - 1)
 994 /* FLAT is a fake segment register (Intel mode).  */
 995 #define RegFlat     ((unsigned char) ~0)
 996   signed char dw2_regnum[2];
 997 #define Dw2Inval (-1)
 998 }
 999 reg_entry;
1000
1001 extern const reg_entry i386_regtab[];
1002 extern const unsigned int i386_regtab_size;
1003 extern const unsigned char i386_seg_prefixes[6];