1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS USED TO GENERATE i960c-opc.c.
6 Copyright (C) 1998, 1999 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
30 #include "i960c-opc.h"
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
39 static int asm_hash_insn_p
PARAMS ((const CGEN_INSN
*));
40 static unsigned int asm_hash_insn
PARAMS ((const char *));
41 static int dis_hash_insn_p
PARAMS ((const CGEN_INSN
*));
42 static unsigned int dis_hash_insn
PARAMS ((const char *, CGEN_INSN_INT
));
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
52 The result is a pointer to the insn table entry, or NULL if the instruction
56 i960_cgen_lookup_insn (od
, insn
, insn_value
, length
, fields
, alias_p
)
58 const CGEN_INSN
*insn
;
59 CGEN_INSN_BYTES insn_value
;
64 unsigned char buf
[CGEN_MAX_INSN_SIZE
];
66 CGEN_INSN_INT base_insn
;
68 CGEN_EXTRACT_INFO
*info
= NULL
;
70 CGEN_EXTRACT_INFO ex_info
;
71 CGEN_EXTRACT_INFO
*info
= &ex_info
;
75 cgen_put_insn_value (od
, buf
, length
, insn_value
);
77 base_insn
= insn_value
; /*???*/
79 ex_info
.dis_info
= NULL
;
80 ex_info
.insn_bytes
= insn_value
;
82 base_insn
= cgen_get_insn_value (od
, buf
, length
);
88 const CGEN_INSN_LIST
*insn_list
;
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
93 insn_list
= CGEN_DIS_LOOKUP_INSN (od
, bufp
, base_insn
);
94 while (insn_list
!= NULL
)
96 insn
= insn_list
->insn
;
99 || ! CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
104 if ((base_insn
& CGEN_INSN_BASE_MASK (insn
))
105 == CGEN_INSN_BASE_VALUE (insn
))
107 /* ??? 0 is passed for `pc' */
108 int elength
= (*CGEN_EXTRACT_FN (insn
)) (od
, insn
, info
,
114 if (length
!= 0 && length
!= elength
)
121 insn_list
= CGEN_DIS_NEXT_INSN (insn_list
);
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
128 && CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
130 /* Sanity check: length must be correct. */
131 if (length
!= CGEN_INSN_BITSIZE (insn
))
134 /* ??? 0 is passed for `pc' */
135 length
= (*CGEN_EXTRACT_FN (insn
)) (od
, insn
, info
, base_insn
, fields
,
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
152 i960_cgen_get_insn_operands (od
, insn
, fields
, indices
)
154 const CGEN_INSN
* insn
;
155 const CGEN_FIELDS
* fields
;
158 const CGEN_OPERAND_INSTANCE
*opinst
;
161 for (i
= 0, opinst
= CGEN_INSN_OPERANDS (insn
);
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst
) != CGEN_OPERAND_INSTANCE_END
;
166 const CGEN_OPERAND
*op
= CGEN_OPERAND_INSTANCE_OPERAND (opinst
);
168 indices
[i
] = CGEN_OPERAND_INSTANCE_INDEX (opinst
);
170 indices
[i
] = i960_cgen_get_int_operand (CGEN_OPERAND_INDEX (op
),
175 /* Cover function to i960_cgen_get_insn_operands when either INSN or FIELDS
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 i960_cgen_lookup_insn unchanged.
180 The result is the insn table entry or NULL if the instruction wasn't
184 i960_cgen_lookup_get_insn_operands (od
, insn
, insn_value
, length
, indices
)
186 const CGEN_INSN
*insn
;
187 CGEN_INSN_BYTES insn_value
;
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn
= i960_cgen_lookup_insn (od
, insn
, insn_value
, length
, &fields
,
200 i960_cgen_get_insn_operands (od
, insn
, &fields
, indices
);
205 static const CGEN_ATTR_ENTRY bool_attr
[] =
212 static const CGEN_ATTR_ENTRY MACH_attr
[] =
214 { "base", MACH_BASE
},
215 { "i960_ka_sa", MACH_I960_KA_SA
},
216 { "i960_ca", MACH_I960_CA
},
221 const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table
[] =
223 { "MACH", & MACH_attr
[0] },
224 { "VIRTUAL", &bool_attr
[0], &bool_attr
[0] },
225 { "UNSIGNED", &bool_attr
[0], &bool_attr
[0] },
226 { "PCREL-ADDR", &bool_attr
[0], &bool_attr
[0] },
227 { "ABS-ADDR", &bool_attr
[0], &bool_attr
[0] },
228 { "RESERVED", &bool_attr
[0], &bool_attr
[0] },
229 { "SIGN-OPT", &bool_attr
[0], &bool_attr
[0] },
233 const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table
[] =
235 { "MACH", & MACH_attr
[0] },
236 { "VIRTUAL", &bool_attr
[0], &bool_attr
[0] },
237 { "UNSIGNED", &bool_attr
[0], &bool_attr
[0] },
238 { "SIGNED", &bool_attr
[0], &bool_attr
[0] },
239 { "CACHE-ADDR", &bool_attr
[0], &bool_attr
[0] },
240 { "FUN-ACCESS", &bool_attr
[0], &bool_attr
[0] },
241 { "PC", &bool_attr
[0], &bool_attr
[0] },
242 { "PROFILE", &bool_attr
[0], &bool_attr
[0] },
246 const CGEN_ATTR_TABLE i960_cgen_operand_attr_table
[] =
248 { "MACH", & MACH_attr
[0] },
249 { "VIRTUAL", &bool_attr
[0], &bool_attr
[0] },
250 { "UNSIGNED", &bool_attr
[0], &bool_attr
[0] },
251 { "PCREL-ADDR", &bool_attr
[0], &bool_attr
[0] },
252 { "ABS-ADDR", &bool_attr
[0], &bool_attr
[0] },
253 { "SIGN-OPT", &bool_attr
[0], &bool_attr
[0] },
254 { "NEGATIVE", &bool_attr
[0], &bool_attr
[0] },
255 { "RELAX", &bool_attr
[0], &bool_attr
[0] },
256 { "SEM-ONLY", &bool_attr
[0], &bool_attr
[0] },
260 const CGEN_ATTR_TABLE i960_cgen_insn_attr_table
[] =
262 { "MACH", & MACH_attr
[0] },
263 { "VIRTUAL", &bool_attr
[0], &bool_attr
[0] },
264 { "UNCOND-CTI", &bool_attr
[0], &bool_attr
[0] },
265 { "COND-CTI", &bool_attr
[0], &bool_attr
[0] },
266 { "SKIP-CTI", &bool_attr
[0], &bool_attr
[0] },
267 { "DELAY-SLOT", &bool_attr
[0], &bool_attr
[0] },
268 { "RELAXABLE", &bool_attr
[0], &bool_attr
[0] },
269 { "RELAX", &bool_attr
[0], &bool_attr
[0] },
270 { "ALIAS", &bool_attr
[0], &bool_attr
[0] },
271 { "NO-DIS", &bool_attr
[0], &bool_attr
[0] },
272 { "PBB", &bool_attr
[0], &bool_attr
[0] },
276 CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries
[] =
314 CGEN_KEYWORD i960_cgen_opval_h_gr
=
316 & i960_cgen_opval_h_gr_entries
[0],
320 CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries
[] =
325 CGEN_KEYWORD i960_cgen_opval_h_cc
=
327 & i960_cgen_opval_h_cc_entries
[0],
332 /* The hardware table. */
334 #define HW_ENT(n) i960_cgen_hw_entries[n]
335 static const CGEN_HW_ENTRY i960_cgen_hw_entries
[] =
337 { HW_H_PC
, & HW_ENT (HW_H_PC
+ 1), "h-pc", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0|(1<<CGEN_HW_PROFILE
)|(1<<CGEN_HW_PC
), { (1<<MACH_BASE
) } } },
338 { HW_H_MEMORY
, & HW_ENT (HW_H_MEMORY
+ 1), "h-memory", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
339 { HW_H_SINT
, & HW_ENT (HW_H_SINT
+ 1), "h-sint", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
340 { HW_H_UINT
, & HW_ENT (HW_H_UINT
+ 1), "h-uint", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
341 { HW_H_ADDR
, & HW_ENT (HW_H_ADDR
+ 1), "h-addr", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
342 { HW_H_IADDR
, & HW_ENT (HW_H_IADDR
+ 1), "h-iaddr", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
343 { HW_H_GR
, & HW_ENT (HW_H_GR
+ 1), "h-gr", CGEN_ASM_KEYWORD
, (PTR
) & i960_cgen_opval_h_gr
, { CGEN_HW_NBOOL_ATTRS
, 0|(1<<CGEN_HW_CACHE_ADDR
)|(1<<CGEN_HW_PROFILE
), { (1<<MACH_BASE
) } } },
344 { HW_H_CC
, & HW_ENT (HW_H_CC
+ 1), "h-cc", CGEN_ASM_KEYWORD
, (PTR
) & i960_cgen_opval_h_cc
, { CGEN_HW_NBOOL_ATTRS
, 0|(1<<CGEN_HW_CACHE_ADDR
)|(1<<CGEN_HW_PROFILE
), { (1<<MACH_BASE
) } } },
348 /* The instruction field table. */
350 static const CGEN_IFLD i960_cgen_ifld_table
[] =
352 { I960_F_NIL
, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
353 { I960_F_OPCODE
, "f-opcode", 0, 32, 0, 8, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
354 { I960_F_SRCDST
, "f-srcdst", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
355 { I960_F_SRC2
, "f-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
356 { I960_F_M3
, "f-m3", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
357 { I960_F_M2
, "f-m2", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
358 { I960_F_M1
, "f-m1", 0, 32, 20, 1, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
359 { I960_F_OPCODE2
, "f-opcode2", 0, 32, 21, 4, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
360 { I960_F_ZERO
, "f-zero", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
361 { I960_F_SRC1
, "f-src1", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
362 { I960_F_ABASE
, "f-abase", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
363 { I960_F_MODEA
, "f-modea", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
364 { I960_F_ZEROA
, "f-zeroa", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
365 { I960_F_OFFSET
, "f-offset", 0, 32, 20, 12, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
366 { I960_F_MODEB
, "f-modeb", 0, 32, 18, 4, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
367 { I960_F_SCALE
, "f-scale", 0, 32, 22, 3, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
368 { I960_F_ZEROB
, "f-zerob", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
369 { I960_F_INDEX
, "f-index", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
370 { I960_F_OPTDISP
, "f-optdisp", 32, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
371 { I960_F_BR_SRC1
, "f-br-src1", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
372 { I960_F_BR_SRC2
, "f-br-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
373 { I960_F_BR_M1
, "f-br-m1", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
374 { I960_F_BR_DISP
, "f-br-disp", 0, 32, 19, 11, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_PCREL_ADDR
), { (1<<MACH_BASE
) } } },
375 { I960_F_BR_ZERO
, "f-br-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
376 { I960_F_CTRL_DISP
, "f-ctrl-disp", 0, 32, 8, 22, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_PCREL_ADDR
), { (1<<MACH_BASE
) } } },
377 { I960_F_CTRL_ZERO
, "f-ctrl-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS
, 0|(1<<CGEN_IFLD_UNSIGNED
), { (1<<MACH_BASE
) } } },
381 /* The operand table. */
383 #define OPERAND(op) CONCAT2 (I960_OPERAND_,op)
384 #define OP_ENT(op) i960_cgen_operand_table[OPERAND (op)]
386 const CGEN_OPERAND i960_cgen_operand_table
[MAX_OPERANDS
] =
388 /* pc: program counter */
389 { "pc", & HW_ENT (HW_H_PC
), 0, 0,
390 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { (1<<MACH_BASE
) } } },
391 /* src1: source register 1 */
392 { "src1", & HW_ENT (HW_H_GR
), 27, 5,
393 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
394 /* src2: source register 2 */
395 { "src2", & HW_ENT (HW_H_GR
), 13, 5,
396 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
397 /* dst: source/dest register */
398 { "dst", & HW_ENT (HW_H_GR
), 8, 5,
399 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
400 /* lit1: literal 1 */
401 { "lit1", & HW_ENT (HW_H_UINT
), 27, 5,
402 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
403 /* lit2: literal 2 */
404 { "lit2", & HW_ENT (HW_H_UINT
), 13, 5,
405 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
406 /* st_src: store src */
407 { "st_src", & HW_ENT (HW_H_GR
), 8, 5,
408 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
410 { "abase", & HW_ENT (HW_H_GR
), 13, 5,
411 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
413 { "offset", & HW_ENT (HW_H_UINT
), 20, 12,
414 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
416 { "scale", & HW_ENT (HW_H_UINT
), 22, 3,
417 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
419 { "index", & HW_ENT (HW_H_GR
), 27, 5,
420 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
421 /* optdisp: optional displacement */
422 { "optdisp", & HW_ENT (HW_H_UINT
), 0, 32,
423 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
424 /* br_src1: branch src1 */
425 { "br_src1", & HW_ENT (HW_H_GR
), 8, 5,
426 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
427 /* br_src2: branch src2 */
428 { "br_src2", & HW_ENT (HW_H_GR
), 13, 5,
429 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
430 /* br_disp: branch displacement */
431 { "br_disp", & HW_ENT (HW_H_IADDR
), 19, 11,
432 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_PCREL_ADDR
), { (1<<MACH_BASE
) } } },
433 /* br_lit1: branch literal 1 */
434 { "br_lit1", & HW_ENT (HW_H_UINT
), 8, 5,
435 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_UNSIGNED
), { (1<<MACH_BASE
) } } },
436 /* ctrl_disp: ctrl branch disp */
437 { "ctrl_disp", & HW_ENT (HW_H_IADDR
), 8, 22,
438 { CGEN_OPERAND_NBOOL_ATTRS
, 0|(1<<CGEN_OPERAND_PCREL_ADDR
), { (1<<MACH_BASE
) } } },
441 /* Instruction formats. */
443 #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
445 static const CGEN_IFMT ifmt_empty
= {
449 static const CGEN_IFMT ifmt_mulo
= {
450 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
453 static const CGEN_IFMT ifmt_mulo1
= {
454 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
457 static const CGEN_IFMT ifmt_mulo2
= {
458 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
461 static const CGEN_IFMT ifmt_mulo3
= {
462 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
465 static const CGEN_IFMT ifmt_lda_offset
= {
466 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
469 static const CGEN_IFMT ifmt_lda_indirect
= {
470 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
473 static const CGEN_IFMT ifmt_lda_disp
= {
474 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
477 static const CGEN_IFMT ifmt_st_offset
= {
478 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
481 static const CGEN_IFMT ifmt_st_indirect
= {
482 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
485 static const CGEN_IFMT ifmt_st_disp
= {
486 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
489 static const CGEN_IFMT ifmt_cmpobe_reg
= {
490 32, 32, 0xff002003, { F (F_OPCODE
), F (F_BR_SRC1
), F (F_BR_SRC2
), F (F_BR_M1
), F (F_BR_DISP
), F (F_BR_ZERO
), 0 }
493 static const CGEN_IFMT ifmt_cmpobe_lit
= {
494 32, 32, 0xff002003, { F (F_OPCODE
), F (F_BR_SRC1
), F (F_BR_SRC2
), F (F_BR_M1
), F (F_BR_DISP
), F (F_BR_ZERO
), 0 }
497 static const CGEN_IFMT ifmt_bno
= {
498 32, 32, 0xff000003, { F (F_OPCODE
), F (F_CTRL_DISP
), F (F_CTRL_ZERO
), 0 }
503 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
504 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
505 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
507 /* The instruction table.
508 This is currently non-static because the simulator accesses it
511 const CGEN_INSN i960_cgen_insn_table_entries
[MAX_INSNS
] =
513 /* Special null first entry.
514 A `num' value of zero is thus invalid.
515 Also, the special `invalid' insn resides here. */
517 /* mulo $src1, $src2, $dst */
520 I960_INSN_MULO
, "mulo", "mulo",
521 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
522 & ifmt_mulo
, { 0x70000080 },
524 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
526 /* mulo $lit1, $src2, $dst */
529 I960_INSN_MULO1
, "mulo1", "mulo",
530 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
531 & ifmt_mulo1
, { 0x70000880 },
533 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
535 /* mulo $src1, $lit2, $dst */
538 I960_INSN_MULO2
, "mulo2", "mulo",
539 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
540 & ifmt_mulo2
, { 0x70001080 },
542 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
544 /* mulo $lit1, $lit2, $dst */
547 I960_INSN_MULO3
, "mulo3", "mulo",
548 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
549 & ifmt_mulo3
, { 0x70001880 },
551 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
553 /* remo $src1, $src2, $dst */
556 I960_INSN_REMO
, "remo", "remo",
557 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
558 & ifmt_mulo
, { 0x70000400 },
560 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
562 /* remo $lit1, $src2, $dst */
565 I960_INSN_REMO1
, "remo1", "remo",
566 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
567 & ifmt_mulo1
, { 0x70000c00 },
569 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
571 /* remo $src1, $lit2, $dst */
574 I960_INSN_REMO2
, "remo2", "remo",
575 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
576 & ifmt_mulo2
, { 0x70001400 },
578 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
580 /* remo $lit1, $lit2, $dst */
583 I960_INSN_REMO3
, "remo3", "remo",
584 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
585 & ifmt_mulo3
, { 0x70001c00 },
587 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
589 /* divo $src1, $src2, $dst */
592 I960_INSN_DIVO
, "divo", "divo",
593 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
594 & ifmt_mulo
, { 0x70000580 },
596 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
598 /* divo $lit1, $src2, $dst */
601 I960_INSN_DIVO1
, "divo1", "divo",
602 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
603 & ifmt_mulo1
, { 0x70000d80 },
605 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
607 /* divo $src1, $lit2, $dst */
610 I960_INSN_DIVO2
, "divo2", "divo",
611 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
612 & ifmt_mulo2
, { 0x70001580 },
614 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
616 /* divo $lit1, $lit2, $dst */
619 I960_INSN_DIVO3
, "divo3", "divo",
620 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
621 & ifmt_mulo3
, { 0x70001d80 },
623 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
625 /* remi $src1, $src2, $dst */
628 I960_INSN_REMI
, "remi", "remi",
629 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
630 & ifmt_mulo
, { 0x74000400 },
632 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
634 /* remi $lit1, $src2, $dst */
637 I960_INSN_REMI1
, "remi1", "remi",
638 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
639 & ifmt_mulo1
, { 0x74000c00 },
641 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
643 /* remi $src1, $lit2, $dst */
646 I960_INSN_REMI2
, "remi2", "remi",
647 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
648 & ifmt_mulo2
, { 0x74001400 },
650 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
652 /* remi $lit1, $lit2, $dst */
655 I960_INSN_REMI3
, "remi3", "remi",
656 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
657 & ifmt_mulo3
, { 0x74001c00 },
659 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
661 /* divi $src1, $src2, $dst */
664 I960_INSN_DIVI
, "divi", "divi",
665 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
666 & ifmt_mulo
, { 0x74000580 },
668 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
670 /* divi $lit1, $src2, $dst */
673 I960_INSN_DIVI1
, "divi1", "divi",
674 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
675 & ifmt_mulo1
, { 0x74000d80 },
677 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
679 /* divi $src1, $lit2, $dst */
682 I960_INSN_DIVI2
, "divi2", "divi",
683 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
684 & ifmt_mulo2
, { 0x74001580 },
686 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
688 /* divi $lit1, $lit2, $dst */
691 I960_INSN_DIVI3
, "divi3", "divi",
692 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
693 & ifmt_mulo3
, { 0x74001d80 },
695 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
697 /* addo $src1, $src2, $dst */
700 I960_INSN_ADDO
, "addo", "addo",
701 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
702 & ifmt_mulo
, { 0x59000000 },
704 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
706 /* addo $lit1, $src2, $dst */
709 I960_INSN_ADDO1
, "addo1", "addo",
710 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
711 & ifmt_mulo1
, { 0x59000800 },
713 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
715 /* addo $src1, $lit2, $dst */
718 I960_INSN_ADDO2
, "addo2", "addo",
719 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
720 & ifmt_mulo2
, { 0x59001000 },
722 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
724 /* addo $lit1, $lit2, $dst */
727 I960_INSN_ADDO3
, "addo3", "addo",
728 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
729 & ifmt_mulo3
, { 0x59001800 },
731 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
733 /* subo $src1, $src2, $dst */
736 I960_INSN_SUBO
, "subo", "subo",
737 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
738 & ifmt_mulo
, { 0x59000100 },
740 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
742 /* subo $lit1, $src2, $dst */
745 I960_INSN_SUBO1
, "subo1", "subo",
746 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
747 & ifmt_mulo1
, { 0x59000900 },
749 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
751 /* subo $src1, $lit2, $dst */
754 I960_INSN_SUBO2
, "subo2", "subo",
755 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
756 & ifmt_mulo2
, { 0x59001100 },
758 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
760 /* subo $lit1, $lit2, $dst */
763 I960_INSN_SUBO3
, "subo3", "subo",
764 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
765 & ifmt_mulo3
, { 0x59001900 },
767 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
769 /* notbit $src1, $src2, $dst */
772 I960_INSN_NOTBIT
, "notbit", "notbit",
773 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
774 & ifmt_mulo
, { 0x58000000 },
776 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
778 /* notbit $lit1, $src2, $dst */
781 I960_INSN_NOTBIT1
, "notbit1", "notbit",
782 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
783 & ifmt_mulo1
, { 0x58000800 },
785 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
787 /* notbit $src1, $lit2, $dst */
790 I960_INSN_NOTBIT2
, "notbit2", "notbit",
791 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
792 & ifmt_mulo2
, { 0x58001000 },
794 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
796 /* notbit $lit1, $lit2, $dst */
799 I960_INSN_NOTBIT3
, "notbit3", "notbit",
800 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
801 & ifmt_mulo3
, { 0x58001800 },
803 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
805 /* and $src1, $src2, $dst */
808 I960_INSN_AND
, "and", "and",
809 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
810 & ifmt_mulo
, { 0x58000080 },
812 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
814 /* and $lit1, $src2, $dst */
817 I960_INSN_AND1
, "and1", "and",
818 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
819 & ifmt_mulo1
, { 0x58000880 },
821 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
823 /* and $src1, $lit2, $dst */
826 I960_INSN_AND2
, "and2", "and",
827 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
828 & ifmt_mulo2
, { 0x58001080 },
830 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
832 /* and $lit1, $lit2, $dst */
835 I960_INSN_AND3
, "and3", "and",
836 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
837 & ifmt_mulo3
, { 0x58001880 },
839 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
841 /* andnot $src1, $src2, $dst */
844 I960_INSN_ANDNOT
, "andnot", "andnot",
845 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
846 & ifmt_mulo
, { 0x58000100 },
848 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
850 /* andnot $lit1, $src2, $dst */
853 I960_INSN_ANDNOT1
, "andnot1", "andnot",
854 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
855 & ifmt_mulo1
, { 0x58000900 },
857 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
859 /* andnot $src1, $lit2, $dst */
862 I960_INSN_ANDNOT2
, "andnot2", "andnot",
863 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
864 & ifmt_mulo2
, { 0x58001100 },
866 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
868 /* andnot $lit1, $lit2, $dst */
871 I960_INSN_ANDNOT3
, "andnot3", "andnot",
872 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
873 & ifmt_mulo3
, { 0x58001900 },
875 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
877 /* setbit $src1, $src2, $dst */
880 I960_INSN_SETBIT
, "setbit", "setbit",
881 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
882 & ifmt_mulo
, { 0x58000180 },
884 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
886 /* setbit $lit1, $src2, $dst */
889 I960_INSN_SETBIT1
, "setbit1", "setbit",
890 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
891 & ifmt_mulo1
, { 0x58000980 },
893 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
895 /* setbit $src1, $lit2, $dst */
898 I960_INSN_SETBIT2
, "setbit2", "setbit",
899 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
900 & ifmt_mulo2
, { 0x58001180 },
902 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
904 /* setbit $lit1, $lit2, $dst */
907 I960_INSN_SETBIT3
, "setbit3", "setbit",
908 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
909 & ifmt_mulo3
, { 0x58001980 },
911 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
913 /* notand $src1, $src2, $dst */
916 I960_INSN_NOTAND
, "notand", "notand",
917 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
918 & ifmt_mulo
, { 0x58000200 },
920 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
922 /* notand $lit1, $src2, $dst */
925 I960_INSN_NOTAND1
, "notand1", "notand",
926 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
927 & ifmt_mulo1
, { 0x58000a00 },
929 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
931 /* notand $src1, $lit2, $dst */
934 I960_INSN_NOTAND2
, "notand2", "notand",
935 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
936 & ifmt_mulo2
, { 0x58001200 },
938 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
940 /* notand $lit1, $lit2, $dst */
943 I960_INSN_NOTAND3
, "notand3", "notand",
944 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
945 & ifmt_mulo3
, { 0x58001a00 },
947 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
949 /* xor $src1, $src2, $dst */
952 I960_INSN_XOR
, "xor", "xor",
953 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
954 & ifmt_mulo
, { 0x58000300 },
956 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
958 /* xor $lit1, $src2, $dst */
961 I960_INSN_XOR1
, "xor1", "xor",
962 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
963 & ifmt_mulo1
, { 0x58000b00 },
965 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
967 /* xor $src1, $lit2, $dst */
970 I960_INSN_XOR2
, "xor2", "xor",
971 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
972 & ifmt_mulo2
, { 0x58001300 },
974 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
976 /* xor $lit1, $lit2, $dst */
979 I960_INSN_XOR3
, "xor3", "xor",
980 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
981 & ifmt_mulo3
, { 0x58001b00 },
983 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
985 /* or $src1, $src2, $dst */
988 I960_INSN_OR
, "or", "or",
989 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
990 & ifmt_mulo
, { 0x58000380 },
992 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
994 /* or $lit1, $src2, $dst */
997 I960_INSN_OR1
, "or1", "or",
998 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
999 & ifmt_mulo1
, { 0x58000b80 },
1001 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1003 /* or $src1, $lit2, $dst */
1006 I960_INSN_OR2
, "or2", "or",
1007 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1008 & ifmt_mulo2
, { 0x58001380 },
1010 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1012 /* or $lit1, $lit2, $dst */
1015 I960_INSN_OR3
, "or3", "or",
1016 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1017 & ifmt_mulo3
, { 0x58001b80 },
1019 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1021 /* nor $src1, $src2, $dst */
1024 I960_INSN_NOR
, "nor", "nor",
1025 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1026 & ifmt_mulo
, { 0x58000400 },
1028 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1030 /* nor $lit1, $src2, $dst */
1033 I960_INSN_NOR1
, "nor1", "nor",
1034 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1035 & ifmt_mulo1
, { 0x58000c00 },
1037 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1039 /* nor $src1, $lit2, $dst */
1042 I960_INSN_NOR2
, "nor2", "nor",
1043 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1044 & ifmt_mulo2
, { 0x58001400 },
1046 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1048 /* nor $lit1, $lit2, $dst */
1051 I960_INSN_NOR3
, "nor3", "nor",
1052 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1053 & ifmt_mulo3
, { 0x58001c00 },
1055 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1057 /* not $src1, $src2, $dst */
1060 I960_INSN_NOT
, "not", "not",
1061 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1062 & ifmt_mulo
, { 0x58000500 },
1064 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1066 /* not $lit1, $src2, $dst */
1069 I960_INSN_NOT1
, "not1", "not",
1070 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1071 & ifmt_mulo1
, { 0x58000d00 },
1073 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1075 /* not $src1, $lit2, $dst */
1078 I960_INSN_NOT2
, "not2", "not",
1079 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1080 & ifmt_mulo2
, { 0x58001500 },
1082 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1084 /* not $lit1, $lit2, $dst */
1087 I960_INSN_NOT3
, "not3", "not",
1088 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1089 & ifmt_mulo3
, { 0x58001d00 },
1091 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1093 /* clrbit $src1, $src2, $dst */
1096 I960_INSN_CLRBIT
, "clrbit", "clrbit",
1097 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1098 & ifmt_mulo
, { 0x58000600 },
1100 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1102 /* clrbit $lit1, $src2, $dst */
1105 I960_INSN_CLRBIT1
, "clrbit1", "clrbit",
1106 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1107 & ifmt_mulo1
, { 0x58000e00 },
1109 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1111 /* clrbit $src1, $lit2, $dst */
1114 I960_INSN_CLRBIT2
, "clrbit2", "clrbit",
1115 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1116 & ifmt_mulo2
, { 0x58001600 },
1118 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1120 /* clrbit $lit1, $lit2, $dst */
1123 I960_INSN_CLRBIT3
, "clrbit3", "clrbit",
1124 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1125 & ifmt_mulo3
, { 0x58001e00 },
1127 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1129 /* shlo $src1, $src2, $dst */
1132 I960_INSN_SHLO
, "shlo", "shlo",
1133 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1134 & ifmt_mulo
, { 0x59000600 },
1136 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1138 /* shlo $lit1, $src2, $dst */
1141 I960_INSN_SHLO1
, "shlo1", "shlo",
1142 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1143 & ifmt_mulo1
, { 0x59000e00 },
1145 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1147 /* shlo $src1, $lit2, $dst */
1150 I960_INSN_SHLO2
, "shlo2", "shlo",
1151 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1152 & ifmt_mulo2
, { 0x59001600 },
1154 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1156 /* shlo $lit1, $lit2, $dst */
1159 I960_INSN_SHLO3
, "shlo3", "shlo",
1160 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1161 & ifmt_mulo3
, { 0x59001e00 },
1163 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1165 /* shro $src1, $src2, $dst */
1168 I960_INSN_SHRO
, "shro", "shro",
1169 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1170 & ifmt_mulo
, { 0x59000400 },
1172 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1174 /* shro $lit1, $src2, $dst */
1177 I960_INSN_SHRO1
, "shro1", "shro",
1178 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1179 & ifmt_mulo1
, { 0x59000c00 },
1181 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1183 /* shro $src1, $lit2, $dst */
1186 I960_INSN_SHRO2
, "shro2", "shro",
1187 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1188 & ifmt_mulo2
, { 0x59001400 },
1190 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1192 /* shro $lit1, $lit2, $dst */
1195 I960_INSN_SHRO3
, "shro3", "shro",
1196 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1197 & ifmt_mulo3
, { 0x59001c00 },
1199 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1201 /* shli $src1, $src2, $dst */
1204 I960_INSN_SHLI
, "shli", "shli",
1205 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1206 & ifmt_mulo
, { 0x59000700 },
1208 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1210 /* shli $lit1, $src2, $dst */
1213 I960_INSN_SHLI1
, "shli1", "shli",
1214 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1215 & ifmt_mulo1
, { 0x59000f00 },
1217 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1219 /* shli $src1, $lit2, $dst */
1222 I960_INSN_SHLI2
, "shli2", "shli",
1223 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1224 & ifmt_mulo2
, { 0x59001700 },
1226 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1228 /* shli $lit1, $lit2, $dst */
1231 I960_INSN_SHLI3
, "shli3", "shli",
1232 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1233 & ifmt_mulo3
, { 0x59001f00 },
1235 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1237 /* shri $src1, $src2, $dst */
1240 I960_INSN_SHRI
, "shri", "shri",
1241 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1242 & ifmt_mulo
, { 0x59000580 },
1244 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1246 /* shri $lit1, $src2, $dst */
1249 I960_INSN_SHRI1
, "shri1", "shri",
1250 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1251 & ifmt_mulo1
, { 0x59000d80 },
1253 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1255 /* shri $src1, $lit2, $dst */
1258 I960_INSN_SHRI2
, "shri2", "shri",
1259 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1260 & ifmt_mulo2
, { 0x59001580 },
1262 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1264 /* shri $lit1, $lit2, $dst */
1267 I960_INSN_SHRI3
, "shri3", "shri",
1268 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1269 & ifmt_mulo3
, { 0x59001d80 },
1271 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1273 /* emul $src1, $src2, $dst */
1276 I960_INSN_EMUL
, "emul", "emul",
1277 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1278 & ifmt_mulo
, { 0x67000000 },
1280 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1282 /* emul $lit1, $src2, $dst */
1285 I960_INSN_EMUL1
, "emul1", "emul",
1286 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1287 & ifmt_mulo1
, { 0x67000800 },
1289 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1291 /* emul $src1, $lit2, $dst */
1294 I960_INSN_EMUL2
, "emul2", "emul",
1295 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1296 & ifmt_mulo2
, { 0x67001000 },
1298 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1300 /* emul $lit1, $lit2, $dst */
1303 I960_INSN_EMUL3
, "emul3", "emul",
1304 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
1305 & ifmt_mulo3
, { 0x67001800 },
1307 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1309 /* mov $src1, $dst */
1312 I960_INSN_MOV
, "mov", "mov",
1313 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (DST
), 0 } },
1314 & ifmt_mulo2
, { 0x5c001600 },
1316 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1318 /* mov $lit1, $dst */
1321 I960_INSN_MOV1
, "mov1", "mov",
1322 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (DST
), 0 } },
1323 & ifmt_mulo3
, { 0x5c001e00 },
1325 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1327 /* movl $src1, $dst */
1330 I960_INSN_MOVL
, "movl", "movl",
1331 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (DST
), 0 } },
1332 & ifmt_mulo2
, { 0x5d001600 },
1334 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1336 /* movl $lit1, $dst */
1339 I960_INSN_MOVL1
, "movl1", "movl",
1340 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (DST
), 0 } },
1341 & ifmt_mulo3
, { 0x5d001e00 },
1343 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1345 /* movt $src1, $dst */
1348 I960_INSN_MOVT
, "movt", "movt",
1349 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (DST
), 0 } },
1350 & ifmt_mulo2
, { 0x5e001600 },
1352 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1354 /* movt $lit1, $dst */
1357 I960_INSN_MOVT1
, "movt1", "movt",
1358 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (DST
), 0 } },
1359 & ifmt_mulo3
, { 0x5e001e00 },
1361 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1363 /* movq $src1, $dst */
1366 I960_INSN_MOVQ
, "movq", "movq",
1367 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (DST
), 0 } },
1368 & ifmt_mulo2
, { 0x5f001600 },
1370 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1372 /* movq $lit1, $dst */
1375 I960_INSN_MOVQ1
, "movq1", "movq",
1376 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (DST
), 0 } },
1377 & ifmt_mulo3
, { 0x5f001e00 },
1379 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1381 /* modpc $src1, $src2, $dst */
1384 I960_INSN_MODPC
, "modpc", "modpc",
1385 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1386 & ifmt_mulo
, { 0x65000280 },
1388 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1390 /* modac $src1, $src2, $dst */
1393 I960_INSN_MODAC
, "modac", "modac",
1394 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
1395 & ifmt_mulo
, { 0x64000280 },
1397 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1399 /* lda $offset, $dst */
1402 I960_INSN_LDA_OFFSET
, "lda-offset", "lda",
1403 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
1404 & ifmt_lda_offset
, { 0x8c000000 },
1406 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1408 /* lda $offset($abase), $dst */
1411 I960_INSN_LDA_INDIRECT_OFFSET
, "lda-indirect-offset", "lda",
1412 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1413 & ifmt_lda_offset
, { 0x8c002000 },
1415 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1417 /* lda ($abase), $dst */
1420 I960_INSN_LDA_INDIRECT
, "lda-indirect", "lda",
1421 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1422 & ifmt_lda_indirect
, { 0x8c001000 },
1424 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1426 /* lda ($abase)[$index*S$scale], $dst */
1429 I960_INSN_LDA_INDIRECT_INDEX
, "lda-indirect-index", "lda",
1430 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1431 & ifmt_lda_indirect
, { 0x8c001c00 },
1433 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1435 /* lda $optdisp, $dst */
1438 I960_INSN_LDA_DISP
, "lda-disp", "lda",
1439 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
1440 & ifmt_lda_disp
, { 0x8c003000 },
1442 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1444 /* lda $optdisp($abase), $dst */
1447 I960_INSN_LDA_INDIRECT_DISP
, "lda-indirect-disp", "lda",
1448 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1449 & ifmt_lda_disp
, { 0x8c003400 },
1451 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1453 /* lda $optdisp[$index*S$scale], $dst */
1456 I960_INSN_LDA_INDEX_DISP
, "lda-index-disp", "lda",
1457 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1458 & ifmt_lda_disp
, { 0x8c003800 },
1460 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1462 /* lda $optdisp($abase)[$index*S$scale], $dst */
1465 I960_INSN_LDA_INDIRECT_INDEX_DISP
, "lda-indirect-index-disp", "lda",
1466 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1467 & ifmt_lda_disp
, { 0x8c003c00 },
1469 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1471 /* ld $offset, $dst */
1474 I960_INSN_LD_OFFSET
, "ld-offset", "ld",
1475 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
1476 & ifmt_lda_offset
, { 0x90000000 },
1478 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1480 /* ld $offset($abase), $dst */
1483 I960_INSN_LD_INDIRECT_OFFSET
, "ld-indirect-offset", "ld",
1484 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1485 & ifmt_lda_offset
, { 0x90002000 },
1487 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1489 /* ld ($abase), $dst */
1492 I960_INSN_LD_INDIRECT
, "ld-indirect", "ld",
1493 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1494 & ifmt_lda_indirect
, { 0x90001000 },
1496 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1498 /* ld ($abase)[$index*S$scale], $dst */
1501 I960_INSN_LD_INDIRECT_INDEX
, "ld-indirect-index", "ld",
1502 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1503 & ifmt_lda_indirect
, { 0x90001c00 },
1505 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1507 /* ld $optdisp, $dst */
1510 I960_INSN_LD_DISP
, "ld-disp", "ld",
1511 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
1512 & ifmt_lda_disp
, { 0x90003000 },
1514 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1516 /* ld $optdisp($abase), $dst */
1519 I960_INSN_LD_INDIRECT_DISP
, "ld-indirect-disp", "ld",
1520 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1521 & ifmt_lda_disp
, { 0x90003400 },
1523 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1525 /* ld $optdisp[$index*S$scale], $dst */
1528 I960_INSN_LD_INDEX_DISP
, "ld-index-disp", "ld",
1529 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1530 & ifmt_lda_disp
, { 0x90003800 },
1532 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1534 /* ld $optdisp($abase)[$index*S$scale], $dst */
1537 I960_INSN_LD_INDIRECT_INDEX_DISP
, "ld-indirect-index-disp", "ld",
1538 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1539 & ifmt_lda_disp
, { 0x90003c00 },
1541 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1543 /* ldob $offset, $dst */
1546 I960_INSN_LDOB_OFFSET
, "ldob-offset", "ldob",
1547 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
1548 & ifmt_lda_offset
, { 0x80000000 },
1550 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1552 /* ldob $offset($abase), $dst */
1555 I960_INSN_LDOB_INDIRECT_OFFSET
, "ldob-indirect-offset", "ldob",
1556 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1557 & ifmt_lda_offset
, { 0x80002000 },
1559 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1561 /* ldob ($abase), $dst */
1564 I960_INSN_LDOB_INDIRECT
, "ldob-indirect", "ldob",
1565 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1566 & ifmt_lda_indirect
, { 0x80001000 },
1568 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1570 /* ldob ($abase)[$index*S$scale], $dst */
1573 I960_INSN_LDOB_INDIRECT_INDEX
, "ldob-indirect-index", "ldob",
1574 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1575 & ifmt_lda_indirect
, { 0x80001c00 },
1577 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1579 /* ldob $optdisp, $dst */
1582 I960_INSN_LDOB_DISP
, "ldob-disp", "ldob",
1583 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
1584 & ifmt_lda_disp
, { 0x80003000 },
1586 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1588 /* ldob $optdisp($abase), $dst */
1591 I960_INSN_LDOB_INDIRECT_DISP
, "ldob-indirect-disp", "ldob",
1592 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1593 & ifmt_lda_disp
, { 0x80003400 },
1595 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1597 /* ldob $optdisp[$index*S$scale], $dst */
1600 I960_INSN_LDOB_INDEX_DISP
, "ldob-index-disp", "ldob",
1601 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1602 & ifmt_lda_disp
, { 0x80003800 },
1604 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1606 /* ldob $optdisp($abase)[$index*S$scale], $dst */
1609 I960_INSN_LDOB_INDIRECT_INDEX_DISP
, "ldob-indirect-index-disp", "ldob",
1610 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1611 & ifmt_lda_disp
, { 0x80003c00 },
1613 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1615 /* ldos $offset, $dst */
1618 I960_INSN_LDOS_OFFSET
, "ldos-offset", "ldos",
1619 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
1620 & ifmt_lda_offset
, { 0x88000000 },
1622 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1624 /* ldos $offset($abase), $dst */
1627 I960_INSN_LDOS_INDIRECT_OFFSET
, "ldos-indirect-offset", "ldos",
1628 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1629 & ifmt_lda_offset
, { 0x88002000 },
1631 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1633 /* ldos ($abase), $dst */
1636 I960_INSN_LDOS_INDIRECT
, "ldos-indirect", "ldos",
1637 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1638 & ifmt_lda_indirect
, { 0x88001000 },
1640 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1642 /* ldos ($abase)[$index*S$scale], $dst */
1645 I960_INSN_LDOS_INDIRECT_INDEX
, "ldos-indirect-index", "ldos",
1646 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1647 & ifmt_lda_indirect
, { 0x88001c00 },
1649 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1651 /* ldos $optdisp, $dst */
1654 I960_INSN_LDOS_DISP
, "ldos-disp", "ldos",
1655 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
1656 & ifmt_lda_disp
, { 0x88003000 },
1658 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1660 /* ldos $optdisp($abase), $dst */
1663 I960_INSN_LDOS_INDIRECT_DISP
, "ldos-indirect-disp", "ldos",
1664 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1665 & ifmt_lda_disp
, { 0x88003400 },
1667 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1669 /* ldos $optdisp[$index*S$scale], $dst */
1672 I960_INSN_LDOS_INDEX_DISP
, "ldos-index-disp", "ldos",
1673 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1674 & ifmt_lda_disp
, { 0x88003800 },
1676 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1678 /* ldos $optdisp($abase)[$index*S$scale], $dst */
1681 I960_INSN_LDOS_INDIRECT_INDEX_DISP
, "ldos-indirect-index-disp", "ldos",
1682 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1683 & ifmt_lda_disp
, { 0x88003c00 },
1685 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1687 /* ldib $offset, $dst */
1690 I960_INSN_LDIB_OFFSET
, "ldib-offset", "ldib",
1691 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
1692 & ifmt_lda_offset
, { 0xc0000000 },
1694 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1696 /* ldib $offset($abase), $dst */
1699 I960_INSN_LDIB_INDIRECT_OFFSET
, "ldib-indirect-offset", "ldib",
1700 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1701 & ifmt_lda_offset
, { 0xc0002000 },
1703 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1705 /* ldib ($abase), $dst */
1708 I960_INSN_LDIB_INDIRECT
, "ldib-indirect", "ldib",
1709 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1710 & ifmt_lda_indirect
, { 0xc0001000 },
1712 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1714 /* ldib ($abase)[$index*S$scale], $dst */
1717 I960_INSN_LDIB_INDIRECT_INDEX
, "ldib-indirect-index", "ldib",
1718 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1719 & ifmt_lda_indirect
, { 0xc0001c00 },
1721 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1723 /* ldib $optdisp, $dst */
1726 I960_INSN_LDIB_DISP
, "ldib-disp", "ldib",
1727 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
1728 & ifmt_lda_disp
, { 0xc0003000 },
1730 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1732 /* ldib $optdisp($abase), $dst */
1735 I960_INSN_LDIB_INDIRECT_DISP
, "ldib-indirect-disp", "ldib",
1736 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1737 & ifmt_lda_disp
, { 0xc0003400 },
1739 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1741 /* ldib $optdisp[$index*S$scale], $dst */
1744 I960_INSN_LDIB_INDEX_DISP
, "ldib-index-disp", "ldib",
1745 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1746 & ifmt_lda_disp
, { 0xc0003800 },
1748 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1750 /* ldib $optdisp($abase)[$index*S$scale], $dst */
1753 I960_INSN_LDIB_INDIRECT_INDEX_DISP
, "ldib-indirect-index-disp", "ldib",
1754 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1755 & ifmt_lda_disp
, { 0xc0003c00 },
1757 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1759 /* ldis $offset, $dst */
1762 I960_INSN_LDIS_OFFSET
, "ldis-offset", "ldis",
1763 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
1764 & ifmt_lda_offset
, { 0xc8000000 },
1766 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1768 /* ldis $offset($abase), $dst */
1771 I960_INSN_LDIS_INDIRECT_OFFSET
, "ldis-indirect-offset", "ldis",
1772 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1773 & ifmt_lda_offset
, { 0xc8002000 },
1775 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1777 /* ldis ($abase), $dst */
1780 I960_INSN_LDIS_INDIRECT
, "ldis-indirect", "ldis",
1781 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1782 & ifmt_lda_indirect
, { 0xc8001000 },
1784 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1786 /* ldis ($abase)[$index*S$scale], $dst */
1789 I960_INSN_LDIS_INDIRECT_INDEX
, "ldis-indirect-index", "ldis",
1790 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1791 & ifmt_lda_indirect
, { 0xc8001c00 },
1793 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1795 /* ldis $optdisp, $dst */
1798 I960_INSN_LDIS_DISP
, "ldis-disp", "ldis",
1799 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
1800 & ifmt_lda_disp
, { 0xc8003000 },
1802 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1804 /* ldis $optdisp($abase), $dst */
1807 I960_INSN_LDIS_INDIRECT_DISP
, "ldis-indirect-disp", "ldis",
1808 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1809 & ifmt_lda_disp
, { 0xc8003400 },
1811 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1813 /* ldis $optdisp[$index*S$scale], $dst */
1816 I960_INSN_LDIS_INDEX_DISP
, "ldis-index-disp", "ldis",
1817 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1818 & ifmt_lda_disp
, { 0xc8003800 },
1820 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1822 /* ldis $optdisp($abase)[$index*S$scale], $dst */
1825 I960_INSN_LDIS_INDIRECT_INDEX_DISP
, "ldis-indirect-index-disp", "ldis",
1826 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1827 & ifmt_lda_disp
, { 0xc8003c00 },
1829 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1831 /* ldl $offset, $dst */
1834 I960_INSN_LDL_OFFSET
, "ldl-offset", "ldl",
1835 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
1836 & ifmt_lda_offset
, { 0x98000000 },
1838 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1840 /* ldl $offset($abase), $dst */
1843 I960_INSN_LDL_INDIRECT_OFFSET
, "ldl-indirect-offset", "ldl",
1844 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1845 & ifmt_lda_offset
, { 0x98002000 },
1847 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1849 /* ldl ($abase), $dst */
1852 I960_INSN_LDL_INDIRECT
, "ldl-indirect", "ldl",
1853 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1854 & ifmt_lda_indirect
, { 0x98001000 },
1856 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1858 /* ldl ($abase)[$index*S$scale], $dst */
1861 I960_INSN_LDL_INDIRECT_INDEX
, "ldl-indirect-index", "ldl",
1862 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1863 & ifmt_lda_indirect
, { 0x98001c00 },
1865 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1867 /* ldl $optdisp, $dst */
1870 I960_INSN_LDL_DISP
, "ldl-disp", "ldl",
1871 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
1872 & ifmt_lda_disp
, { 0x98003000 },
1874 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1876 /* ldl $optdisp($abase), $dst */
1879 I960_INSN_LDL_INDIRECT_DISP
, "ldl-indirect-disp", "ldl",
1880 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1881 & ifmt_lda_disp
, { 0x98003400 },
1883 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1885 /* ldl $optdisp[$index*S$scale], $dst */
1888 I960_INSN_LDL_INDEX_DISP
, "ldl-index-disp", "ldl",
1889 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1890 & ifmt_lda_disp
, { 0x98003800 },
1892 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1894 /* ldl $optdisp($abase)[$index*S$scale], $dst */
1897 I960_INSN_LDL_INDIRECT_INDEX_DISP
, "ldl-indirect-index-disp", "ldl",
1898 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1899 & ifmt_lda_disp
, { 0x98003c00 },
1901 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1903 /* ldt $offset, $dst */
1906 I960_INSN_LDT_OFFSET
, "ldt-offset", "ldt",
1907 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
1908 & ifmt_lda_offset
, { 0xa0000000 },
1910 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1912 /* ldt $offset($abase), $dst */
1915 I960_INSN_LDT_INDIRECT_OFFSET
, "ldt-indirect-offset", "ldt",
1916 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1917 & ifmt_lda_offset
, { 0xa0002000 },
1919 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1921 /* ldt ($abase), $dst */
1924 I960_INSN_LDT_INDIRECT
, "ldt-indirect", "ldt",
1925 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1926 & ifmt_lda_indirect
, { 0xa0001000 },
1928 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1930 /* ldt ($abase)[$index*S$scale], $dst */
1933 I960_INSN_LDT_INDIRECT_INDEX
, "ldt-indirect-index", "ldt",
1934 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1935 & ifmt_lda_indirect
, { 0xa0001c00 },
1937 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1939 /* ldt $optdisp, $dst */
1942 I960_INSN_LDT_DISP
, "ldt-disp", "ldt",
1943 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
1944 & ifmt_lda_disp
, { 0xa0003000 },
1946 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1948 /* ldt $optdisp($abase), $dst */
1951 I960_INSN_LDT_INDIRECT_DISP
, "ldt-indirect-disp", "ldt",
1952 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1953 & ifmt_lda_disp
, { 0xa0003400 },
1955 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1957 /* ldt $optdisp[$index*S$scale], $dst */
1960 I960_INSN_LDT_INDEX_DISP
, "ldt-index-disp", "ldt",
1961 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1962 & ifmt_lda_disp
, { 0xa0003800 },
1964 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1966 /* ldt $optdisp($abase)[$index*S$scale], $dst */
1969 I960_INSN_LDT_INDIRECT_INDEX_DISP
, "ldt-indirect-index-disp", "ldt",
1970 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
1971 & ifmt_lda_disp
, { 0xa0003c00 },
1973 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1975 /* ldq $offset, $dst */
1978 I960_INSN_LDQ_OFFSET
, "ldq-offset", "ldq",
1979 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
1980 & ifmt_lda_offset
, { 0xb0000000 },
1982 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1984 /* ldq $offset($abase), $dst */
1987 I960_INSN_LDQ_INDIRECT_OFFSET
, "ldq-indirect-offset", "ldq",
1988 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1989 & ifmt_lda_offset
, { 0xb0002000 },
1991 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
1993 /* ldq ($abase), $dst */
1996 I960_INSN_LDQ_INDIRECT
, "ldq-indirect", "ldq",
1997 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
1998 & ifmt_lda_indirect
, { 0xb0001000 },
2000 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2002 /* ldq ($abase)[$index*S$scale], $dst */
2005 I960_INSN_LDQ_INDIRECT_INDEX
, "ldq-indirect-index", "ldq",
2006 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
2007 & ifmt_lda_indirect
, { 0xb0001c00 },
2009 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2011 /* ldq $optdisp, $dst */
2014 I960_INSN_LDQ_DISP
, "ldq-disp", "ldq",
2015 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
2016 & ifmt_lda_disp
, { 0xb0003000 },
2018 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2020 /* ldq $optdisp($abase), $dst */
2023 I960_INSN_LDQ_INDIRECT_DISP
, "ldq-indirect-disp", "ldq",
2024 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
2025 & ifmt_lda_disp
, { 0xb0003400 },
2027 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2029 /* ldq $optdisp[$index*S$scale], $dst */
2032 I960_INSN_LDQ_INDEX_DISP
, "ldq-index-disp", "ldq",
2033 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
2034 & ifmt_lda_disp
, { 0xb0003800 },
2036 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2038 /* ldq $optdisp($abase)[$index*S$scale], $dst */
2041 I960_INSN_LDQ_INDIRECT_INDEX_DISP
, "ldq-indirect-index-disp", "ldq",
2042 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
2043 & ifmt_lda_disp
, { 0xb0003c00 },
2045 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2047 /* st $st_src, $offset */
2050 I960_INSN_ST_OFFSET
, "st-offset", "st",
2051 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
2052 & ifmt_st_offset
, { 0x92000000 },
2054 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2056 /* st $st_src, $offset($abase) */
2059 I960_INSN_ST_INDIRECT_OFFSET
, "st-indirect-offset", "st",
2060 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
2061 & ifmt_st_offset
, { 0x92002000 },
2063 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2065 /* st $st_src, ($abase) */
2068 I960_INSN_ST_INDIRECT
, "st-indirect", "st",
2069 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
2070 & ifmt_st_indirect
, { 0x92001000 },
2072 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2074 /* st $st_src, ($abase)[$index*S$scale] */
2077 I960_INSN_ST_INDIRECT_INDEX
, "st-indirect-index", "st",
2078 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2079 & ifmt_st_indirect
, { 0x92001c00 },
2081 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2083 /* st $st_src, $optdisp */
2086 I960_INSN_ST_DISP
, "st-disp", "st",
2087 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
2088 & ifmt_st_disp
, { 0x92003000 },
2090 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2092 /* st $st_src, $optdisp($abase) */
2095 I960_INSN_ST_INDIRECT_DISP
, "st-indirect-disp", "st",
2096 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
2097 & ifmt_st_disp
, { 0x92003400 },
2099 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2101 /* st $st_src, $optdisp[$index*S$scale */
2104 I960_INSN_ST_INDEX_DISP
, "st-index-disp", "st",
2105 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
2106 & ifmt_st_disp
, { 0x92003800 },
2108 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2110 /* st $st_src, $optdisp($abase)[$index*S$scale] */
2113 I960_INSN_ST_INDIRECT_INDEX_DISP
, "st-indirect-index-disp", "st",
2114 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2115 & ifmt_st_disp
, { 0x92003c00 },
2117 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2119 /* stob $st_src, $offset */
2122 I960_INSN_STOB_OFFSET
, "stob-offset", "stob",
2123 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
2124 & ifmt_st_offset
, { 0x82000000 },
2126 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2128 /* stob $st_src, $offset($abase) */
2131 I960_INSN_STOB_INDIRECT_OFFSET
, "stob-indirect-offset", "stob",
2132 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
2133 & ifmt_st_offset
, { 0x82002000 },
2135 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2137 /* stob $st_src, ($abase) */
2140 I960_INSN_STOB_INDIRECT
, "stob-indirect", "stob",
2141 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
2142 & ifmt_st_indirect
, { 0x82001000 },
2144 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2146 /* stob $st_src, ($abase)[$index*S$scale] */
2149 I960_INSN_STOB_INDIRECT_INDEX
, "stob-indirect-index", "stob",
2150 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2151 & ifmt_st_indirect
, { 0x82001c00 },
2153 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2155 /* stob $st_src, $optdisp */
2158 I960_INSN_STOB_DISP
, "stob-disp", "stob",
2159 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
2160 & ifmt_st_disp
, { 0x82003000 },
2162 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2164 /* stob $st_src, $optdisp($abase) */
2167 I960_INSN_STOB_INDIRECT_DISP
, "stob-indirect-disp", "stob",
2168 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
2169 & ifmt_st_disp
, { 0x82003400 },
2171 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2173 /* stob $st_src, $optdisp[$index*S$scale */
2176 I960_INSN_STOB_INDEX_DISP
, "stob-index-disp", "stob",
2177 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
2178 & ifmt_st_disp
, { 0x82003800 },
2180 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2182 /* stob $st_src, $optdisp($abase)[$index*S$scale] */
2185 I960_INSN_STOB_INDIRECT_INDEX_DISP
, "stob-indirect-index-disp", "stob",
2186 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2187 & ifmt_st_disp
, { 0x82003c00 },
2189 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2191 /* stos $st_src, $offset */
2194 I960_INSN_STOS_OFFSET
, "stos-offset", "stos",
2195 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
2196 & ifmt_st_offset
, { 0x8a000000 },
2198 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2200 /* stos $st_src, $offset($abase) */
2203 I960_INSN_STOS_INDIRECT_OFFSET
, "stos-indirect-offset", "stos",
2204 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
2205 & ifmt_st_offset
, { 0x8a002000 },
2207 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2209 /* stos $st_src, ($abase) */
2212 I960_INSN_STOS_INDIRECT
, "stos-indirect", "stos",
2213 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
2214 & ifmt_st_indirect
, { 0x8a001000 },
2216 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2218 /* stos $st_src, ($abase)[$index*S$scale] */
2221 I960_INSN_STOS_INDIRECT_INDEX
, "stos-indirect-index", "stos",
2222 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2223 & ifmt_st_indirect
, { 0x8a001c00 },
2225 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2227 /* stos $st_src, $optdisp */
2230 I960_INSN_STOS_DISP
, "stos-disp", "stos",
2231 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
2232 & ifmt_st_disp
, { 0x8a003000 },
2234 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2236 /* stos $st_src, $optdisp($abase) */
2239 I960_INSN_STOS_INDIRECT_DISP
, "stos-indirect-disp", "stos",
2240 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
2241 & ifmt_st_disp
, { 0x8a003400 },
2243 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2245 /* stos $st_src, $optdisp[$index*S$scale */
2248 I960_INSN_STOS_INDEX_DISP
, "stos-index-disp", "stos",
2249 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
2250 & ifmt_st_disp
, { 0x8a003800 },
2252 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2254 /* stos $st_src, $optdisp($abase)[$index*S$scale] */
2257 I960_INSN_STOS_INDIRECT_INDEX_DISP
, "stos-indirect-index-disp", "stos",
2258 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2259 & ifmt_st_disp
, { 0x8a003c00 },
2261 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2263 /* stl $st_src, $offset */
2266 I960_INSN_STL_OFFSET
, "stl-offset", "stl",
2267 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
2268 & ifmt_st_offset
, { 0x9a000000 },
2270 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2272 /* stl $st_src, $offset($abase) */
2275 I960_INSN_STL_INDIRECT_OFFSET
, "stl-indirect-offset", "stl",
2276 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
2277 & ifmt_st_offset
, { 0x9a002000 },
2279 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2281 /* stl $st_src, ($abase) */
2284 I960_INSN_STL_INDIRECT
, "stl-indirect", "stl",
2285 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
2286 & ifmt_st_indirect
, { 0x9a001000 },
2288 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2290 /* stl $st_src, ($abase)[$index*S$scale] */
2293 I960_INSN_STL_INDIRECT_INDEX
, "stl-indirect-index", "stl",
2294 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2295 & ifmt_st_indirect
, { 0x9a001c00 },
2297 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2299 /* stl $st_src, $optdisp */
2302 I960_INSN_STL_DISP
, "stl-disp", "stl",
2303 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
2304 & ifmt_st_disp
, { 0x9a003000 },
2306 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2308 /* stl $st_src, $optdisp($abase) */
2311 I960_INSN_STL_INDIRECT_DISP
, "stl-indirect-disp", "stl",
2312 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
2313 & ifmt_st_disp
, { 0x9a003400 },
2315 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2317 /* stl $st_src, $optdisp[$index*S$scale */
2320 I960_INSN_STL_INDEX_DISP
, "stl-index-disp", "stl",
2321 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
2322 & ifmt_st_disp
, { 0x9a003800 },
2324 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2326 /* stl $st_src, $optdisp($abase)[$index*S$scale] */
2329 I960_INSN_STL_INDIRECT_INDEX_DISP
, "stl-indirect-index-disp", "stl",
2330 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2331 & ifmt_st_disp
, { 0x9a003c00 },
2333 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2335 /* stt $st_src, $offset */
2338 I960_INSN_STT_OFFSET
, "stt-offset", "stt",
2339 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
2340 & ifmt_st_offset
, { 0xa2000000 },
2342 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2344 /* stt $st_src, $offset($abase) */
2347 I960_INSN_STT_INDIRECT_OFFSET
, "stt-indirect-offset", "stt",
2348 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
2349 & ifmt_st_offset
, { 0xa2002000 },
2351 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2353 /* stt $st_src, ($abase) */
2356 I960_INSN_STT_INDIRECT
, "stt-indirect", "stt",
2357 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
2358 & ifmt_st_indirect
, { 0xa2001000 },
2360 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2362 /* stt $st_src, ($abase)[$index*S$scale] */
2365 I960_INSN_STT_INDIRECT_INDEX
, "stt-indirect-index", "stt",
2366 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2367 & ifmt_st_indirect
, { 0xa2001c00 },
2369 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2371 /* stt $st_src, $optdisp */
2374 I960_INSN_STT_DISP
, "stt-disp", "stt",
2375 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
2376 & ifmt_st_disp
, { 0xa2003000 },
2378 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2380 /* stt $st_src, $optdisp($abase) */
2383 I960_INSN_STT_INDIRECT_DISP
, "stt-indirect-disp", "stt",
2384 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
2385 & ifmt_st_disp
, { 0xa2003400 },
2387 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2389 /* stt $st_src, $optdisp[$index*S$scale */
2392 I960_INSN_STT_INDEX_DISP
, "stt-index-disp", "stt",
2393 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
2394 & ifmt_st_disp
, { 0xa2003800 },
2396 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2398 /* stt $st_src, $optdisp($abase)[$index*S$scale] */
2401 I960_INSN_STT_INDIRECT_INDEX_DISP
, "stt-indirect-index-disp", "stt",
2402 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2403 & ifmt_st_disp
, { 0xa2003c00 },
2405 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2407 /* stq $st_src, $offset */
2410 I960_INSN_STQ_OFFSET
, "stq-offset", "stq",
2411 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
2412 & ifmt_st_offset
, { 0xb2000000 },
2414 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2416 /* stq $st_src, $offset($abase) */
2419 I960_INSN_STQ_INDIRECT_OFFSET
, "stq-indirect-offset", "stq",
2420 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
2421 & ifmt_st_offset
, { 0xb2002000 },
2423 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2425 /* stq $st_src, ($abase) */
2428 I960_INSN_STQ_INDIRECT
, "stq-indirect", "stq",
2429 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
2430 & ifmt_st_indirect
, { 0xb2001000 },
2432 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2434 /* stq $st_src, ($abase)[$index*S$scale] */
2437 I960_INSN_STQ_INDIRECT_INDEX
, "stq-indirect-index", "stq",
2438 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2439 & ifmt_st_indirect
, { 0xb2001c00 },
2441 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2443 /* stq $st_src, $optdisp */
2446 I960_INSN_STQ_DISP
, "stq-disp", "stq",
2447 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
2448 & ifmt_st_disp
, { 0xb2003000 },
2450 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2452 /* stq $st_src, $optdisp($abase) */
2455 I960_INSN_STQ_INDIRECT_DISP
, "stq-indirect-disp", "stq",
2456 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
2457 & ifmt_st_disp
, { 0xb2003400 },
2459 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2461 /* stq $st_src, $optdisp[$index*S$scale */
2464 I960_INSN_STQ_INDEX_DISP
, "stq-index-disp", "stq",
2465 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
2466 & ifmt_st_disp
, { 0xb2003800 },
2468 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2470 /* stq $st_src, $optdisp($abase)[$index*S$scale] */
2473 I960_INSN_STQ_INDIRECT_INDEX_DISP
, "stq-indirect-index-disp", "stq",
2474 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2475 & ifmt_st_disp
, { 0xb2003c00 },
2477 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2479 /* cmpobe $br_src1, $br_src2, $br_disp */
2482 I960_INSN_CMPOBE_REG
, "cmpobe-reg", "cmpobe",
2483 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2484 & ifmt_cmpobe_reg
, { 0x32000000 },
2486 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2488 /* cmpobe $br_lit1, $br_src2, $br_disp */
2491 I960_INSN_CMPOBE_LIT
, "cmpobe-lit", "cmpobe",
2492 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2493 & ifmt_cmpobe_lit
, { 0x32002000 },
2495 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2497 /* cmpobne $br_src1, $br_src2, $br_disp */
2500 I960_INSN_CMPOBNE_REG
, "cmpobne-reg", "cmpobne",
2501 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2502 & ifmt_cmpobe_reg
, { 0x35000000 },
2504 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2506 /* cmpobne $br_lit1, $br_src2, $br_disp */
2509 I960_INSN_CMPOBNE_LIT
, "cmpobne-lit", "cmpobne",
2510 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2511 & ifmt_cmpobe_lit
, { 0x35002000 },
2513 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2515 /* cmpobl $br_src1, $br_src2, $br_disp */
2518 I960_INSN_CMPOBL_REG
, "cmpobl-reg", "cmpobl",
2519 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2520 & ifmt_cmpobe_reg
, { 0x34000000 },
2522 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2524 /* cmpobl $br_lit1, $br_src2, $br_disp */
2527 I960_INSN_CMPOBL_LIT
, "cmpobl-lit", "cmpobl",
2528 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2529 & ifmt_cmpobe_lit
, { 0x34002000 },
2531 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2533 /* cmpoble $br_src1, $br_src2, $br_disp */
2536 I960_INSN_CMPOBLE_REG
, "cmpoble-reg", "cmpoble",
2537 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2538 & ifmt_cmpobe_reg
, { 0x36000000 },
2540 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2542 /* cmpoble $br_lit1, $br_src2, $br_disp */
2545 I960_INSN_CMPOBLE_LIT
, "cmpoble-lit", "cmpoble",
2546 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2547 & ifmt_cmpobe_lit
, { 0x36002000 },
2549 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2551 /* cmpobg $br_src1, $br_src2, $br_disp */
2554 I960_INSN_CMPOBG_REG
, "cmpobg-reg", "cmpobg",
2555 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2556 & ifmt_cmpobe_reg
, { 0x31000000 },
2558 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2560 /* cmpobg $br_lit1, $br_src2, $br_disp */
2563 I960_INSN_CMPOBG_LIT
, "cmpobg-lit", "cmpobg",
2564 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2565 & ifmt_cmpobe_lit
, { 0x31002000 },
2567 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2569 /* cmpobge $br_src1, $br_src2, $br_disp */
2572 I960_INSN_CMPOBGE_REG
, "cmpobge-reg", "cmpobge",
2573 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2574 & ifmt_cmpobe_reg
, { 0x33000000 },
2576 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2578 /* cmpobge $br_lit1, $br_src2, $br_disp */
2581 I960_INSN_CMPOBGE_LIT
, "cmpobge-lit", "cmpobge",
2582 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2583 & ifmt_cmpobe_lit
, { 0x33002000 },
2585 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2587 /* cmpibe $br_src1, $br_src2, $br_disp */
2590 I960_INSN_CMPIBE_REG
, "cmpibe-reg", "cmpibe",
2591 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2592 & ifmt_cmpobe_reg
, { 0x3a000000 },
2594 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2596 /* cmpibe $br_lit1, $br_src2, $br_disp */
2599 I960_INSN_CMPIBE_LIT
, "cmpibe-lit", "cmpibe",
2600 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2601 & ifmt_cmpobe_lit
, { 0x3a002000 },
2603 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2605 /* cmpibne $br_src1, $br_src2, $br_disp */
2608 I960_INSN_CMPIBNE_REG
, "cmpibne-reg", "cmpibne",
2609 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2610 & ifmt_cmpobe_reg
, { 0x3d000000 },
2612 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2614 /* cmpibne $br_lit1, $br_src2, $br_disp */
2617 I960_INSN_CMPIBNE_LIT
, "cmpibne-lit", "cmpibne",
2618 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2619 & ifmt_cmpobe_lit
, { 0x3d002000 },
2621 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2623 /* cmpibl $br_src1, $br_src2, $br_disp */
2626 I960_INSN_CMPIBL_REG
, "cmpibl-reg", "cmpibl",
2627 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2628 & ifmt_cmpobe_reg
, { 0x3c000000 },
2630 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2632 /* cmpibl $br_lit1, $br_src2, $br_disp */
2635 I960_INSN_CMPIBL_LIT
, "cmpibl-lit", "cmpibl",
2636 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2637 & ifmt_cmpobe_lit
, { 0x3c002000 },
2639 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2641 /* cmpible $br_src1, $br_src2, $br_disp */
2644 I960_INSN_CMPIBLE_REG
, "cmpible-reg", "cmpible",
2645 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2646 & ifmt_cmpobe_reg
, { 0x3e000000 },
2648 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2650 /* cmpible $br_lit1, $br_src2, $br_disp */
2653 I960_INSN_CMPIBLE_LIT
, "cmpible-lit", "cmpible",
2654 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2655 & ifmt_cmpobe_lit
, { 0x3e002000 },
2657 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2659 /* cmpibg $br_src1, $br_src2, $br_disp */
2662 I960_INSN_CMPIBG_REG
, "cmpibg-reg", "cmpibg",
2663 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2664 & ifmt_cmpobe_reg
, { 0x39000000 },
2666 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2668 /* cmpibg $br_lit1, $br_src2, $br_disp */
2671 I960_INSN_CMPIBG_LIT
, "cmpibg-lit", "cmpibg",
2672 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2673 & ifmt_cmpobe_lit
, { 0x39002000 },
2675 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2677 /* cmpibge $br_src1, $br_src2, $br_disp */
2680 I960_INSN_CMPIBGE_REG
, "cmpibge-reg", "cmpibge",
2681 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2682 & ifmt_cmpobe_reg
, { 0x3b000000 },
2684 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2686 /* cmpibge $br_lit1, $br_src2, $br_disp */
2689 I960_INSN_CMPIBGE_LIT
, "cmpibge-lit", "cmpibge",
2690 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2691 & ifmt_cmpobe_lit
, { 0x3b002000 },
2693 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2695 /* bbc $br_src1, $br_src2, $br_disp */
2698 I960_INSN_BBC_REG
, "bbc-reg", "bbc",
2699 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2700 & ifmt_cmpobe_reg
, { 0x30000000 },
2702 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2704 /* bbc $br_lit1, $br_src2, $br_disp */
2707 I960_INSN_BBC_LIT
, "bbc-lit", "bbc",
2708 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2709 & ifmt_cmpobe_lit
, { 0x30002000 },
2711 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2713 /* bbs $br_src1, $br_src2, $br_disp */
2716 I960_INSN_BBS_REG
, "bbs-reg", "bbs",
2717 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2718 & ifmt_cmpobe_reg
, { 0x37000000 },
2720 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2722 /* bbs $br_lit1, $br_src2, $br_disp */
2725 I960_INSN_BBS_LIT
, "bbs-lit", "bbs",
2726 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
2727 & ifmt_cmpobe_lit
, { 0x37002000 },
2729 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2731 /* cmpi $src1, $src2 */
2734 I960_INSN_CMPI
, "cmpi", "cmpi",
2735 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), 0 } },
2736 & ifmt_mulo
, { 0x5a002080 },
2738 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2740 /* cmpi $lit1, $src2 */
2743 I960_INSN_CMPI1
, "cmpi1", "cmpi",
2744 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), 0 } },
2745 & ifmt_mulo1
, { 0x5a002880 },
2747 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2749 /* cmpi $src1, $lit2 */
2752 I960_INSN_CMPI2
, "cmpi2", "cmpi",
2753 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), 0 } },
2754 & ifmt_mulo2
, { 0x5a003080 },
2756 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2758 /* cmpi $lit1, $lit2 */
2761 I960_INSN_CMPI3
, "cmpi3", "cmpi",
2762 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), 0 } },
2763 & ifmt_mulo3
, { 0x5a003880 },
2765 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2767 /* cmpo $src1, $src2 */
2770 I960_INSN_CMPO
, "cmpo", "cmpo",
2771 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), 0 } },
2772 & ifmt_mulo
, { 0x5a002000 },
2774 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2776 /* cmpo $lit1, $src2 */
2779 I960_INSN_CMPO1
, "cmpo1", "cmpo",
2780 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), 0 } },
2781 & ifmt_mulo1
, { 0x5a002800 },
2783 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2785 /* cmpo $src1, $lit2 */
2788 I960_INSN_CMPO2
, "cmpo2", "cmpo",
2789 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), 0 } },
2790 & ifmt_mulo2
, { 0x5a003000 },
2792 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2794 /* cmpo $lit1, $lit2 */
2797 I960_INSN_CMPO3
, "cmpo3", "cmpo",
2798 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), 0 } },
2799 & ifmt_mulo3
, { 0x5a003800 },
2801 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2803 /* testno $br_src1 */
2806 I960_INSN_TESTNO_REG
, "testno-reg", "testno",
2807 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
2808 & ifmt_cmpobe_reg
, { 0x20000000 },
2810 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2812 /* testg $br_src1 */
2815 I960_INSN_TESTG_REG
, "testg-reg", "testg",
2816 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
2817 & ifmt_cmpobe_reg
, { 0x21000000 },
2819 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2821 /* teste $br_src1 */
2824 I960_INSN_TESTE_REG
, "teste-reg", "teste",
2825 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
2826 & ifmt_cmpobe_reg
, { 0x22000000 },
2828 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2830 /* testge $br_src1 */
2833 I960_INSN_TESTGE_REG
, "testge-reg", "testge",
2834 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
2835 & ifmt_cmpobe_reg
, { 0x23000000 },
2837 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2839 /* testl $br_src1 */
2842 I960_INSN_TESTL_REG
, "testl-reg", "testl",
2843 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
2844 & ifmt_cmpobe_reg
, { 0x24000000 },
2846 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2848 /* testne $br_src1 */
2851 I960_INSN_TESTNE_REG
, "testne-reg", "testne",
2852 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
2853 & ifmt_cmpobe_reg
, { 0x25000000 },
2855 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2857 /* testle $br_src1 */
2860 I960_INSN_TESTLE_REG
, "testle-reg", "testle",
2861 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
2862 & ifmt_cmpobe_reg
, { 0x26000000 },
2864 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2866 /* testo $br_src1 */
2869 I960_INSN_TESTO_REG
, "testo-reg", "testo",
2870 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
2871 & ifmt_cmpobe_reg
, { 0x27000000 },
2873 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
2875 /* bno $ctrl_disp */
2878 I960_INSN_BNO
, "bno", "bno",
2879 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
2880 & ifmt_bno
, { 0x10000000 },
2882 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2887 I960_INSN_BG
, "bg", "bg",
2888 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
2889 & ifmt_bno
, { 0x11000000 },
2891 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2896 I960_INSN_BE
, "be", "be",
2897 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
2898 & ifmt_bno
, { 0x12000000 },
2900 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2902 /* bge $ctrl_disp */
2905 I960_INSN_BGE
, "bge", "bge",
2906 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
2907 & ifmt_bno
, { 0x13000000 },
2909 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2914 I960_INSN_BL
, "bl", "bl",
2915 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
2916 & ifmt_bno
, { 0x14000000 },
2918 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2920 /* bne $ctrl_disp */
2923 I960_INSN_BNE
, "bne", "bne",
2924 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
2925 & ifmt_bno
, { 0x15000000 },
2927 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2929 /* ble $ctrl_disp */
2932 I960_INSN_BLE
, "ble", "ble",
2933 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
2934 & ifmt_bno
, { 0x16000000 },
2936 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2941 I960_INSN_BO
, "bo", "bo",
2942 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
2943 & ifmt_bno
, { 0x17000000 },
2945 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
) } }
2950 I960_INSN_B
, "b", "b",
2951 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
2952 & ifmt_bno
, { 0x8000000 },
2954 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
2956 /* bx $offset($abase) */
2959 I960_INSN_BX_INDIRECT_OFFSET
, "bx-indirect-offset", "bx",
2960 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
2961 & ifmt_lda_offset
, { 0x84002000 },
2963 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
2968 I960_INSN_BX_INDIRECT
, "bx-indirect", "bx",
2969 { { MNEM
, ' ', '(', OP (ABASE
), ')', 0 } },
2970 & ifmt_lda_indirect
, { 0x84001000 },
2972 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
2974 /* bx ($abase)[$index*S$scale] */
2977 I960_INSN_BX_INDIRECT_INDEX
, "bx-indirect-index", "bx",
2978 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
2979 & ifmt_lda_indirect
, { 0x84001c00 },
2981 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
2986 I960_INSN_BX_DISP
, "bx-disp", "bx",
2987 { { MNEM
, ' ', OP (OPTDISP
), 0 } },
2988 & ifmt_lda_disp
, { 0x84003000 },
2990 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
2992 /* bx $optdisp($abase) */
2995 I960_INSN_BX_INDIRECT_DISP
, "bx-indirect-disp", "bx",
2996 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
2997 & ifmt_lda_disp
, { 0x84003400 },
2999 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
3001 /* callx $optdisp */
3004 I960_INSN_CALLX_DISP
, "callx-disp", "callx",
3005 { { MNEM
, ' ', OP (OPTDISP
), 0 } },
3006 & ifmt_lda_disp
, { 0x86003000 },
3008 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
3010 /* callx ($abase) */
3013 I960_INSN_CALLX_INDIRECT
, "callx-indirect", "callx",
3014 { { MNEM
, ' ', '(', OP (ABASE
), ')', 0 } },
3015 & ifmt_lda_indirect
, { 0x86001000 },
3017 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
3019 /* callx $offset($abase) */
3022 I960_INSN_CALLX_INDIRECT_OFFSET
, "callx-indirect-offset", "callx",
3023 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
3024 & ifmt_lda_offset
, { 0x86002000 },
3026 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
3031 I960_INSN_RET
, "ret", "ret",
3033 & ifmt_bno
, { 0xa000000 },
3035 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
3040 I960_INSN_CALLS
, "calls", "calls",
3041 { { MNEM
, ' ', OP (SRC1
), 0 } },
3042 & ifmt_mulo
, { 0x66003000 },
3044 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
3049 I960_INSN_FMARK
, "fmark", "fmark",
3051 & ifmt_mulo
, { 0x66003e00 },
3053 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
) } }
3058 I960_INSN_FLUSHREG
, "flushreg", "flushreg",
3060 & ifmt_mulo
, { 0x66003e80 },
3062 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } }
3070 static const CGEN_INSN_TABLE insn_table
=
3072 & i960_cgen_insn_table_entries
[0],
3078 /* Formats for ALIAS macro-insns. */
3080 #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
3084 /* Each non-simple macro entry points to an array of expansion possibilities. */
3086 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
3087 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
3088 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
3090 /* The macro instruction table. */
3092 static const CGEN_INSN macro_insn_table_entries
[] =
3100 static const CGEN_INSN_TABLE macro_insn_table
=
3102 & macro_insn_table_entries
[0],
3104 (sizeof (macro_insn_table_entries
) /
3105 sizeof (macro_insn_table_entries
[0])),
3114 /* Return non-zero if INSN is to be added to the hash table.
3115 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3118 asm_hash_insn_p (insn
)
3119 const CGEN_INSN
* insn
;
3121 return CGEN_ASM_HASH_P (insn
);
3125 dis_hash_insn_p (insn
)
3126 const CGEN_INSN
* insn
;
3128 /* If building the hash table and the NO-DIS attribute is present,
3130 if (CGEN_INSN_ATTR (insn
, CGEN_INSN_NO_DIS
))
3132 return CGEN_DIS_HASH_P (insn
);
3135 /* The result is the hash value of the insn.
3136 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
3139 asm_hash_insn (mnem
)
3142 return CGEN_ASM_HASH (mnem
);
3145 /* BUF is a pointer to the insn's bytes in target order.
3146 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3150 dis_hash_insn (buf
, value
)
3152 CGEN_INSN_INT value
;
3154 return CGEN_DIS_HASH (buf
, value
);
3157 /* Initialize an opcode table and return a descriptor.
3158 It's much like opening a file, and must be the first function called. */
3161 i960_cgen_opcode_open (mach
, endian
)
3163 enum cgen_endian endian
;
3165 CGEN_OPCODE_TABLE
* table
= (CGEN_OPCODE_TABLE
*) xmalloc (sizeof (CGEN_OPCODE_TABLE
));
3174 memset (table
, 0, sizeof (*table
));
3176 CGEN_OPCODE_MACH (table
) = mach
;
3177 CGEN_OPCODE_ENDIAN (table
) = endian
;
3178 /* FIXME: for the sparc case we can determine insn-endianness statically.
3179 The worry here is where both data and insn endian can be independently
3180 chosen, in which case this function will need another argument.
3181 Actually, will want to allow for more arguments in the future anyway. */
3182 CGEN_OPCODE_INSN_ENDIAN (table
) = endian
;
3184 CGEN_OPCODE_HW_LIST (table
) = & i960_cgen_hw_entries
[0];
3186 CGEN_OPCODE_IFLD_TABLE (table
) = & i960_cgen_ifld_table
[0];
3188 CGEN_OPCODE_OPERAND_TABLE (table
) = & i960_cgen_operand_table
[0];
3190 * CGEN_OPCODE_INSN_TABLE (table
) = insn_table
;
3192 * CGEN_OPCODE_MACRO_INSN_TABLE (table
) = macro_insn_table
;
3194 CGEN_OPCODE_ASM_HASH_P (table
) = asm_hash_insn_p
;
3195 CGEN_OPCODE_ASM_HASH (table
) = asm_hash_insn
;
3196 CGEN_OPCODE_ASM_HASH_SIZE (table
) = CGEN_ASM_HASH_SIZE
;
3198 CGEN_OPCODE_DIS_HASH_P (table
) = dis_hash_insn_p
;
3199 CGEN_OPCODE_DIS_HASH (table
) = dis_hash_insn
;
3200 CGEN_OPCODE_DIS_HASH_SIZE (table
) = CGEN_DIS_HASH_SIZE
;
3202 return (CGEN_OPCODE_DESC
) table
;
3205 /* Close an opcode table. */
3208 i960_cgen_opcode_close (desc
)
3209 CGEN_OPCODE_DESC desc
;
3214 /* Getting values from cgen_fields is handled by a collection of functions.
3215 They are distinguished by the type of the VALUE argument they return.
3216 TODO: floating point, inlining support, remove cases where result type
3220 i960_cgen_get_int_operand (opindex
, fields
)
3222 const CGEN_FIELDS
* fields
;
3228 case I960_OPERAND_SRC1
:
3229 value
= fields
->f_src1
;
3231 case I960_OPERAND_SRC2
:
3232 value
= fields
->f_src2
;
3234 case I960_OPERAND_DST
:
3235 value
= fields
->f_srcdst
;
3237 case I960_OPERAND_LIT1
:
3238 value
= fields
->f_src1
;
3240 case I960_OPERAND_LIT2
:
3241 value
= fields
->f_src2
;
3243 case I960_OPERAND_ST_SRC
:
3244 value
= fields
->f_srcdst
;
3246 case I960_OPERAND_ABASE
:
3247 value
= fields
->f_abase
;
3249 case I960_OPERAND_OFFSET
:
3250 value
= fields
->f_offset
;
3252 case I960_OPERAND_SCALE
:
3253 value
= fields
->f_scale
;
3255 case I960_OPERAND_INDEX
:
3256 value
= fields
->f_index
;
3258 case I960_OPERAND_OPTDISP
:
3259 value
= fields
->f_optdisp
;
3261 case I960_OPERAND_BR_SRC1
:
3262 value
= fields
->f_br_src1
;
3264 case I960_OPERAND_BR_SRC2
:
3265 value
= fields
->f_br_src2
;
3267 case I960_OPERAND_BR_DISP
:
3268 value
= fields
->f_br_disp
;
3270 case I960_OPERAND_BR_LIT1
:
3271 value
= fields
->f_br_src1
;
3273 case I960_OPERAND_CTRL_DISP
:
3274 value
= fields
->f_ctrl_disp
;
3278 /* xgettext:c-format */
3279 fprintf (stderr
, _("Unrecognized field %d while getting int operand.\n"),
3288 i960_cgen_get_vma_operand (opindex
, fields
)
3290 const CGEN_FIELDS
* fields
;
3296 case I960_OPERAND_SRC1
:
3297 value
= fields
->f_src1
;
3299 case I960_OPERAND_SRC2
:
3300 value
= fields
->f_src2
;
3302 case I960_OPERAND_DST
:
3303 value
= fields
->f_srcdst
;
3305 case I960_OPERAND_LIT1
:
3306 value
= fields
->f_src1
;
3308 case I960_OPERAND_LIT2
:
3309 value
= fields
->f_src2
;
3311 case I960_OPERAND_ST_SRC
:
3312 value
= fields
->f_srcdst
;
3314 case I960_OPERAND_ABASE
:
3315 value
= fields
->f_abase
;
3317 case I960_OPERAND_OFFSET
:
3318 value
= fields
->f_offset
;
3320 case I960_OPERAND_SCALE
:
3321 value
= fields
->f_scale
;
3323 case I960_OPERAND_INDEX
:
3324 value
= fields
->f_index
;
3326 case I960_OPERAND_OPTDISP
:
3327 value
= fields
->f_optdisp
;
3329 case I960_OPERAND_BR_SRC1
:
3330 value
= fields
->f_br_src1
;
3332 case I960_OPERAND_BR_SRC2
:
3333 value
= fields
->f_br_src2
;
3335 case I960_OPERAND_BR_DISP
:
3336 value
= fields
->f_br_disp
;
3338 case I960_OPERAND_BR_LIT1
:
3339 value
= fields
->f_br_src1
;
3341 case I960_OPERAND_CTRL_DISP
:
3342 value
= fields
->f_ctrl_disp
;
3346 /* xgettext:c-format */
3347 fprintf (stderr
, _("Unrecognized field %d while getting vma operand.\n"),
3355 /* Stuffing values in cgen_fields is handled by a collection of functions.
3356 They are distinguished by the type of the VALUE argument they accept.
3357 TODO: floating point, inlining support, remove cases where argument type
3361 i960_cgen_set_int_operand (opindex
, fields
, value
)
3363 CGEN_FIELDS
* fields
;
3368 case I960_OPERAND_SRC1
:
3369 fields
->f_src1
= value
;
3371 case I960_OPERAND_SRC2
:
3372 fields
->f_src2
= value
;
3374 case I960_OPERAND_DST
:
3375 fields
->f_srcdst
= value
;
3377 case I960_OPERAND_LIT1
:
3378 fields
->f_src1
= value
;
3380 case I960_OPERAND_LIT2
:
3381 fields
->f_src2
= value
;
3383 case I960_OPERAND_ST_SRC
:
3384 fields
->f_srcdst
= value
;
3386 case I960_OPERAND_ABASE
:
3387 fields
->f_abase
= value
;
3389 case I960_OPERAND_OFFSET
:
3390 fields
->f_offset
= value
;
3392 case I960_OPERAND_SCALE
:
3393 fields
->f_scale
= value
;
3395 case I960_OPERAND_INDEX
:
3396 fields
->f_index
= value
;
3398 case I960_OPERAND_OPTDISP
:
3399 fields
->f_optdisp
= value
;
3401 case I960_OPERAND_BR_SRC1
:
3402 fields
->f_br_src1
= value
;
3404 case I960_OPERAND_BR_SRC2
:
3405 fields
->f_br_src2
= value
;
3407 case I960_OPERAND_BR_DISP
:
3408 fields
->f_br_disp
= value
;
3410 case I960_OPERAND_BR_LIT1
:
3411 fields
->f_br_src1
= value
;
3413 case I960_OPERAND_CTRL_DISP
:
3414 fields
->f_ctrl_disp
= value
;
3418 /* xgettext:c-format */
3419 fprintf (stderr
, _("Unrecognized field %d while setting int operand.\n"),
3426 i960_cgen_set_vma_operand (opindex
, fields
, value
)
3428 CGEN_FIELDS
* fields
;
3433 case I960_OPERAND_SRC1
:
3434 fields
->f_src1
= value
;
3436 case I960_OPERAND_SRC2
:
3437 fields
->f_src2
= value
;
3439 case I960_OPERAND_DST
:
3440 fields
->f_srcdst
= value
;
3442 case I960_OPERAND_LIT1
:
3443 fields
->f_src1
= value
;
3445 case I960_OPERAND_LIT2
:
3446 fields
->f_src2
= value
;
3448 case I960_OPERAND_ST_SRC
:
3449 fields
->f_srcdst
= value
;
3451 case I960_OPERAND_ABASE
:
3452 fields
->f_abase
= value
;
3454 case I960_OPERAND_OFFSET
:
3455 fields
->f_offset
= value
;
3457 case I960_OPERAND_SCALE
:
3458 fields
->f_scale
= value
;
3460 case I960_OPERAND_INDEX
:
3461 fields
->f_index
= value
;
3463 case I960_OPERAND_OPTDISP
:
3464 fields
->f_optdisp
= value
;
3466 case I960_OPERAND_BR_SRC1
:
3467 fields
->f_br_src1
= value
;
3469 case I960_OPERAND_BR_SRC2
:
3470 fields
->f_br_src2
= value
;
3472 case I960_OPERAND_BR_DISP
:
3473 fields
->f_br_disp
= value
;
3475 case I960_OPERAND_BR_LIT1
:
3476 fields
->f_br_src1
= value
;
3478 case I960_OPERAND_CTRL_DISP
:
3479 fields
->f_ctrl_disp
= value
;
3483 /* xgettext:c-format */
3484 fprintf (stderr
, _("Unrecognized field %d while setting vma operand.\n"),