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fix comments and some indentation.
[binutils-gdb.git] / opcodes / i960c-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS USED TO GENERATE i960c-opc.c.
5
6 Copyright (C) 1998, 1999 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "i960c-opc.h"
31 #include "opintl.h"
32
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
35
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40 static unsigned int asm_hash_insn PARAMS ((const char *));
41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
43
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
52 The result is a pointer to the insn table entry, or NULL if the instruction
53 wasn't recognized. */
54
55 const CGEN_INSN *
56 i960_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63 {
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
65 unsigned char *bufp;
66 CGEN_INSN_INT base_insn;
67 #if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69 #else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72 #endif
73
74 #if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78 #else
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
81 ex_info.valid = -1;
82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
84 #endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
109 base_insn, fields,
110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145 }
146
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151 void
152 i960_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157 {
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = i960_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173 }
174
175 /* Cover function to i960_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 i960_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183 const CGEN_INSN *
184 i960_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190 {
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = i960_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 i960_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202 }
203 /* Attributes. */
204
205 static const CGEN_ATTR_ENTRY bool_attr[] =
206 {
207 { "#f", 0 },
208 { "#t", 1 },
209 { 0, 0 }
210 };
211
212 static const CGEN_ATTR_ENTRY MACH_attr[] =
213 {
214 { "base", MACH_BASE },
215 { "i960_ka_sa", MACH_I960_KA_SA },
216 { "i960_ca", MACH_I960_CA },
217 { "max", MACH_MAX },
218 { 0, 0 }
219 };
220
221 const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[] =
222 {
223 { "MACH", & MACH_attr[0] },
224 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
225 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
226 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
227 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
228 { "RESERVED", &bool_attr[0], &bool_attr[0] },
229 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
230 { 0, 0, 0 }
231 };
232
233 const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] =
234 {
235 { "MACH", & MACH_attr[0] },
236 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
237 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
238 { "SIGNED", &bool_attr[0], &bool_attr[0] },
239 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
240 { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
241 { "PC", &bool_attr[0], &bool_attr[0] },
242 { "PROFILE", &bool_attr[0], &bool_attr[0] },
243 { 0, 0, 0 }
244 };
245
246 const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] =
247 {
248 { "MACH", & MACH_attr[0] },
249 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
250 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
251 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
252 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
253 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
254 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
255 { "RELAX", &bool_attr[0], &bool_attr[0] },
256 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
257 { 0, 0, 0 }
258 };
259
260 const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] =
261 {
262 { "MACH", & MACH_attr[0] },
263 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
264 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
265 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
266 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
267 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
268 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
269 { "RELAX", &bool_attr[0], &bool_attr[0] },
270 { "ALIAS", &bool_attr[0], &bool_attr[0] },
271 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
272 { "PBB", &bool_attr[0], &bool_attr[0] },
273 { 0, 0, 0 }
274 };
275
276 CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] =
277 {
278 { "fp", 31 },
279 { "sp", 1 },
280 { "r0", 0 },
281 { "r1", 1 },
282 { "r2", 2 },
283 { "r3", 3 },
284 { "r4", 4 },
285 { "r5", 5 },
286 { "r6", 6 },
287 { "r7", 7 },
288 { "r8", 8 },
289 { "r9", 9 },
290 { "r10", 10 },
291 { "r11", 11 },
292 { "r12", 12 },
293 { "r13", 13 },
294 { "r14", 14 },
295 { "r15", 15 },
296 { "g0", 16 },
297 { "g1", 17 },
298 { "g2", 18 },
299 { "g3", 19 },
300 { "g4", 20 },
301 { "g5", 21 },
302 { "g6", 22 },
303 { "g7", 23 },
304 { "g8", 24 },
305 { "g9", 25 },
306 { "g10", 26 },
307 { "g11", 27 },
308 { "g12", 28 },
309 { "g13", 29 },
310 { "g14", 30 },
311 { "g15", 31 }
312 };
313
314 CGEN_KEYWORD i960_cgen_opval_h_gr =
315 {
316 & i960_cgen_opval_h_gr_entries[0],
317 34
318 };
319
320 CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] =
321 {
322 { "cc", 0 }
323 };
324
325 CGEN_KEYWORD i960_cgen_opval_h_cc =
326 {
327 & i960_cgen_opval_h_cc_entries[0],
328 1
329 };
330
331
332 /* The hardware table. */
333
334 #define HW_ENT(n) i960_cgen_hw_entries[n]
335 static const CGEN_HW_ENTRY i960_cgen_hw_entries[] =
336 {
337 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
338 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
339 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
340 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
341 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
342 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
343 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
344 { HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
345 { 0 }
346 };
347
348 /* The instruction field table. */
349
350 static const CGEN_IFLD i960_cgen_ifld_table[] =
351 {
352 { I960_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
353 { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
354 { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
355 { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
356 { I960_F_M3, "f-m3", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
357 { I960_F_M2, "f-m2", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
358 { I960_F_M1, "f-m1", 0, 32, 20, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
359 { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
360 { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
361 { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
362 { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
363 { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
364 { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
365 { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
366 { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
367 { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
368 { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
369 { I960_F_INDEX, "f-index", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
370 { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
371 { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
372 { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
373 { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
374 { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
375 { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
376 { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
377 { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
378 { 0 }
379 };
380
381 /* The operand table. */
382
383 #define OPERAND(op) CONCAT2 (I960_OPERAND_,op)
384 #define OP_ENT(op) i960_cgen_operand_table[OPERAND (op)]
385
386 const CGEN_OPERAND i960_cgen_operand_table[MAX_OPERANDS] =
387 {
388 /* pc: program counter */
389 { "pc", & HW_ENT (HW_H_PC), 0, 0,
390 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
391 /* src1: source register 1 */
392 { "src1", & HW_ENT (HW_H_GR), 27, 5,
393 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
394 /* src2: source register 2 */
395 { "src2", & HW_ENT (HW_H_GR), 13, 5,
396 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
397 /* dst: source/dest register */
398 { "dst", & HW_ENT (HW_H_GR), 8, 5,
399 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
400 /* lit1: literal 1 */
401 { "lit1", & HW_ENT (HW_H_UINT), 27, 5,
402 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
403 /* lit2: literal 2 */
404 { "lit2", & HW_ENT (HW_H_UINT), 13, 5,
405 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
406 /* st_src: store src */
407 { "st_src", & HW_ENT (HW_H_GR), 8, 5,
408 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
409 /* abase: abase */
410 { "abase", & HW_ENT (HW_H_GR), 13, 5,
411 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
412 /* offset: offset */
413 { "offset", & HW_ENT (HW_H_UINT), 20, 12,
414 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
415 /* scale: scale */
416 { "scale", & HW_ENT (HW_H_UINT), 22, 3,
417 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
418 /* index: index */
419 { "index", & HW_ENT (HW_H_GR), 27, 5,
420 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
421 /* optdisp: optional displacement */
422 { "optdisp", & HW_ENT (HW_H_UINT), 0, 32,
423 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
424 /* br_src1: branch src1 */
425 { "br_src1", & HW_ENT (HW_H_GR), 8, 5,
426 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
427 /* br_src2: branch src2 */
428 { "br_src2", & HW_ENT (HW_H_GR), 13, 5,
429 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
430 /* br_disp: branch displacement */
431 { "br_disp", & HW_ENT (HW_H_IADDR), 19, 11,
432 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
433 /* br_lit1: branch literal 1 */
434 { "br_lit1", & HW_ENT (HW_H_UINT), 8, 5,
435 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
436 /* ctrl_disp: ctrl branch disp */
437 { "ctrl_disp", & HW_ENT (HW_H_IADDR), 8, 22,
438 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
439 };
440
441 /* Instruction formats. */
442
443 #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
444
445 static const CGEN_IFMT fmt_empty = {
446 0, 0, 0x0, { 0 }
447 };
448
449 static const CGEN_IFMT fmt_mulo = {
450 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
451 };
452
453 static const CGEN_IFMT fmt_mulo1 = {
454 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
455 };
456
457 static const CGEN_IFMT fmt_mulo2 = {
458 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
459 };
460
461 static const CGEN_IFMT fmt_mulo3 = {
462 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
463 };
464
465 static const CGEN_IFMT fmt_remo = {
466 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
467 };
468
469 static const CGEN_IFMT fmt_remo1 = {
470 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
471 };
472
473 static const CGEN_IFMT fmt_remo2 = {
474 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
475 };
476
477 static const CGEN_IFMT fmt_remo3 = {
478 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
479 };
480
481 static const CGEN_IFMT fmt_not = {
482 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
483 };
484
485 static const CGEN_IFMT fmt_not1 = {
486 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
487 };
488
489 static const CGEN_IFMT fmt_not2 = {
490 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
491 };
492
493 static const CGEN_IFMT fmt_not3 = {
494 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
495 };
496
497 static const CGEN_IFMT fmt_emul = {
498 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
499 };
500
501 static const CGEN_IFMT fmt_emul1 = {
502 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
503 };
504
505 static const CGEN_IFMT fmt_emul2 = {
506 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
507 };
508
509 static const CGEN_IFMT fmt_emul3 = {
510 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
511 };
512
513 static const CGEN_IFMT fmt_movl = {
514 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
515 };
516
517 static const CGEN_IFMT fmt_movl1 = {
518 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
519 };
520
521 static const CGEN_IFMT fmt_movt = {
522 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
523 };
524
525 static const CGEN_IFMT fmt_movt1 = {
526 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
527 };
528
529 static const CGEN_IFMT fmt_movq = {
530 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
531 };
532
533 static const CGEN_IFMT fmt_movq1 = {
534 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
535 };
536
537 static const CGEN_IFMT fmt_modpc = {
538 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
539 };
540
541 static const CGEN_IFMT fmt_lda_offset = {
542 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
543 };
544
545 static const CGEN_IFMT fmt_lda_indirect_offset = {
546 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
547 };
548
549 static const CGEN_IFMT fmt_lda_indirect = {
550 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
551 };
552
553 static const CGEN_IFMT fmt_lda_indirect_index = {
554 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
555 };
556
557 static const CGEN_IFMT fmt_lda_disp = {
558 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
559 };
560
561 static const CGEN_IFMT fmt_lda_indirect_disp = {
562 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
563 };
564
565 static const CGEN_IFMT fmt_lda_index_disp = {
566 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
567 };
568
569 static const CGEN_IFMT fmt_lda_indirect_index_disp = {
570 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
571 };
572
573 static const CGEN_IFMT fmt_ld_offset = {
574 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
575 };
576
577 static const CGEN_IFMT fmt_ld_indirect_offset = {
578 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
579 };
580
581 static const CGEN_IFMT fmt_ld_indirect = {
582 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
583 };
584
585 static const CGEN_IFMT fmt_ld_indirect_index = {
586 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
587 };
588
589 static const CGEN_IFMT fmt_ld_disp = {
590 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
591 };
592
593 static const CGEN_IFMT fmt_ld_indirect_disp = {
594 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
595 };
596
597 static const CGEN_IFMT fmt_ld_index_disp = {
598 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
599 };
600
601 static const CGEN_IFMT fmt_ld_indirect_index_disp = {
602 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
603 };
604
605 static const CGEN_IFMT fmt_ldob_offset = {
606 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
607 };
608
609 static const CGEN_IFMT fmt_ldob_indirect_offset = {
610 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
611 };
612
613 static const CGEN_IFMT fmt_ldob_indirect = {
614 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
615 };
616
617 static const CGEN_IFMT fmt_ldob_indirect_index = {
618 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
619 };
620
621 static const CGEN_IFMT fmt_ldob_disp = {
622 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
623 };
624
625 static const CGEN_IFMT fmt_ldob_indirect_disp = {
626 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
627 };
628
629 static const CGEN_IFMT fmt_ldob_index_disp = {
630 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
631 };
632
633 static const CGEN_IFMT fmt_ldob_indirect_index_disp = {
634 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
635 };
636
637 static const CGEN_IFMT fmt_ldos_offset = {
638 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
639 };
640
641 static const CGEN_IFMT fmt_ldos_indirect_offset = {
642 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
643 };
644
645 static const CGEN_IFMT fmt_ldos_indirect = {
646 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
647 };
648
649 static const CGEN_IFMT fmt_ldos_indirect_index = {
650 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
651 };
652
653 static const CGEN_IFMT fmt_ldos_disp = {
654 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
655 };
656
657 static const CGEN_IFMT fmt_ldos_indirect_disp = {
658 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
659 };
660
661 static const CGEN_IFMT fmt_ldos_index_disp = {
662 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
663 };
664
665 static const CGEN_IFMT fmt_ldos_indirect_index_disp = {
666 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
667 };
668
669 static const CGEN_IFMT fmt_ldib_offset = {
670 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
671 };
672
673 static const CGEN_IFMT fmt_ldib_indirect_offset = {
674 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
675 };
676
677 static const CGEN_IFMT fmt_ldib_indirect = {
678 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
679 };
680
681 static const CGEN_IFMT fmt_ldib_indirect_index = {
682 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
683 };
684
685 static const CGEN_IFMT fmt_ldib_disp = {
686 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
687 };
688
689 static const CGEN_IFMT fmt_ldib_indirect_disp = {
690 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
691 };
692
693 static const CGEN_IFMT fmt_ldib_index_disp = {
694 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
695 };
696
697 static const CGEN_IFMT fmt_ldib_indirect_index_disp = {
698 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
699 };
700
701 static const CGEN_IFMT fmt_ldis_offset = {
702 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
703 };
704
705 static const CGEN_IFMT fmt_ldis_indirect_offset = {
706 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
707 };
708
709 static const CGEN_IFMT fmt_ldis_indirect = {
710 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
711 };
712
713 static const CGEN_IFMT fmt_ldis_indirect_index = {
714 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
715 };
716
717 static const CGEN_IFMT fmt_ldis_disp = {
718 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
719 };
720
721 static const CGEN_IFMT fmt_ldis_indirect_disp = {
722 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
723 };
724
725 static const CGEN_IFMT fmt_ldis_index_disp = {
726 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
727 };
728
729 static const CGEN_IFMT fmt_ldis_indirect_index_disp = {
730 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
731 };
732
733 static const CGEN_IFMT fmt_ldl_offset = {
734 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
735 };
736
737 static const CGEN_IFMT fmt_ldl_indirect_offset = {
738 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
739 };
740
741 static const CGEN_IFMT fmt_ldl_indirect = {
742 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
743 };
744
745 static const CGEN_IFMT fmt_ldl_indirect_index = {
746 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
747 };
748
749 static const CGEN_IFMT fmt_ldl_disp = {
750 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
751 };
752
753 static const CGEN_IFMT fmt_ldl_indirect_disp = {
754 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
755 };
756
757 static const CGEN_IFMT fmt_ldl_index_disp = {
758 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
759 };
760
761 static const CGEN_IFMT fmt_ldl_indirect_index_disp = {
762 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
763 };
764
765 static const CGEN_IFMT fmt_ldt_offset = {
766 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
767 };
768
769 static const CGEN_IFMT fmt_ldt_indirect_offset = {
770 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
771 };
772
773 static const CGEN_IFMT fmt_ldt_indirect = {
774 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
775 };
776
777 static const CGEN_IFMT fmt_ldt_indirect_index = {
778 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
779 };
780
781 static const CGEN_IFMT fmt_ldt_disp = {
782 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
783 };
784
785 static const CGEN_IFMT fmt_ldt_indirect_disp = {
786 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
787 };
788
789 static const CGEN_IFMT fmt_ldt_index_disp = {
790 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
791 };
792
793 static const CGEN_IFMT fmt_ldt_indirect_index_disp = {
794 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
795 };
796
797 static const CGEN_IFMT fmt_ldq_offset = {
798 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
799 };
800
801 static const CGEN_IFMT fmt_ldq_indirect_offset = {
802 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
803 };
804
805 static const CGEN_IFMT fmt_ldq_indirect = {
806 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
807 };
808
809 static const CGEN_IFMT fmt_ldq_indirect_index = {
810 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
811 };
812
813 static const CGEN_IFMT fmt_ldq_disp = {
814 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
815 };
816
817 static const CGEN_IFMT fmt_ldq_indirect_disp = {
818 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
819 };
820
821 static const CGEN_IFMT fmt_ldq_index_disp = {
822 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
823 };
824
825 static const CGEN_IFMT fmt_ldq_indirect_index_disp = {
826 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
827 };
828
829 static const CGEN_IFMT fmt_st_offset = {
830 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
831 };
832
833 static const CGEN_IFMT fmt_st_indirect_offset = {
834 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
835 };
836
837 static const CGEN_IFMT fmt_st_indirect = {
838 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
839 };
840
841 static const CGEN_IFMT fmt_st_indirect_index = {
842 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
843 };
844
845 static const CGEN_IFMT fmt_st_disp = {
846 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
847 };
848
849 static const CGEN_IFMT fmt_st_indirect_disp = {
850 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
851 };
852
853 static const CGEN_IFMT fmt_st_index_disp = {
854 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
855 };
856
857 static const CGEN_IFMT fmt_st_indirect_index_disp = {
858 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
859 };
860
861 static const CGEN_IFMT fmt_stob_offset = {
862 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
863 };
864
865 static const CGEN_IFMT fmt_stob_indirect_offset = {
866 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
867 };
868
869 static const CGEN_IFMT fmt_stob_indirect = {
870 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
871 };
872
873 static const CGEN_IFMT fmt_stob_indirect_index = {
874 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
875 };
876
877 static const CGEN_IFMT fmt_stob_disp = {
878 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
879 };
880
881 static const CGEN_IFMT fmt_stob_indirect_disp = {
882 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
883 };
884
885 static const CGEN_IFMT fmt_stob_index_disp = {
886 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
887 };
888
889 static const CGEN_IFMT fmt_stob_indirect_index_disp = {
890 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
891 };
892
893 static const CGEN_IFMT fmt_stos_offset = {
894 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
895 };
896
897 static const CGEN_IFMT fmt_stos_indirect_offset = {
898 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
899 };
900
901 static const CGEN_IFMT fmt_stos_indirect = {
902 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
903 };
904
905 static const CGEN_IFMT fmt_stos_indirect_index = {
906 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
907 };
908
909 static const CGEN_IFMT fmt_stos_disp = {
910 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
911 };
912
913 static const CGEN_IFMT fmt_stos_indirect_disp = {
914 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
915 };
916
917 static const CGEN_IFMT fmt_stos_index_disp = {
918 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
919 };
920
921 static const CGEN_IFMT fmt_stos_indirect_index_disp = {
922 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
923 };
924
925 static const CGEN_IFMT fmt_stl_offset = {
926 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
927 };
928
929 static const CGEN_IFMT fmt_stl_indirect_offset = {
930 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
931 };
932
933 static const CGEN_IFMT fmt_stl_indirect = {
934 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
935 };
936
937 static const CGEN_IFMT fmt_stl_indirect_index = {
938 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
939 };
940
941 static const CGEN_IFMT fmt_stl_disp = {
942 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
943 };
944
945 static const CGEN_IFMT fmt_stl_indirect_disp = {
946 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
947 };
948
949 static const CGEN_IFMT fmt_stl_index_disp = {
950 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
951 };
952
953 static const CGEN_IFMT fmt_stl_indirect_index_disp = {
954 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
955 };
956
957 static const CGEN_IFMT fmt_stt_offset = {
958 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
959 };
960
961 static const CGEN_IFMT fmt_stt_indirect_offset = {
962 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
963 };
964
965 static const CGEN_IFMT fmt_stt_indirect = {
966 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
967 };
968
969 static const CGEN_IFMT fmt_stt_indirect_index = {
970 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
971 };
972
973 static const CGEN_IFMT fmt_stt_disp = {
974 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
975 };
976
977 static const CGEN_IFMT fmt_stt_indirect_disp = {
978 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
979 };
980
981 static const CGEN_IFMT fmt_stt_index_disp = {
982 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
983 };
984
985 static const CGEN_IFMT fmt_stt_indirect_index_disp = {
986 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
987 };
988
989 static const CGEN_IFMT fmt_stq_offset = {
990 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
991 };
992
993 static const CGEN_IFMT fmt_stq_indirect_offset = {
994 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
995 };
996
997 static const CGEN_IFMT fmt_stq_indirect = {
998 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
999 };
1000
1001 static const CGEN_IFMT fmt_stq_indirect_index = {
1002 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1003 };
1004
1005 static const CGEN_IFMT fmt_stq_disp = {
1006 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1007 };
1008
1009 static const CGEN_IFMT fmt_stq_indirect_disp = {
1010 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1011 };
1012
1013 static const CGEN_IFMT fmt_stq_index_disp = {
1014 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1015 };
1016
1017 static const CGEN_IFMT fmt_stq_indirect_index_disp = {
1018 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1019 };
1020
1021 static const CGEN_IFMT fmt_cmpobe_reg = {
1022 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
1023 };
1024
1025 static const CGEN_IFMT fmt_cmpobe_lit = {
1026 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
1027 };
1028
1029 static const CGEN_IFMT fmt_cmpobl_reg = {
1030 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
1031 };
1032
1033 static const CGEN_IFMT fmt_cmpobl_lit = {
1034 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
1035 };
1036
1037 static const CGEN_IFMT fmt_bbc_lit = {
1038 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
1039 };
1040
1041 static const CGEN_IFMT fmt_cmpi = {
1042 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
1043 };
1044
1045 static const CGEN_IFMT fmt_cmpi1 = {
1046 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
1047 };
1048
1049 static const CGEN_IFMT fmt_cmpi2 = {
1050 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
1051 };
1052
1053 static const CGEN_IFMT fmt_cmpi3 = {
1054 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
1055 };
1056
1057 static const CGEN_IFMT fmt_testno_reg = {
1058 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
1059 };
1060
1061 static const CGEN_IFMT fmt_bno = {
1062 32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
1063 };
1064
1065 static const CGEN_IFMT fmt_b = {
1066 32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
1067 };
1068
1069 static const CGEN_IFMT fmt_bx_indirect_offset = {
1070 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
1071 };
1072
1073 static const CGEN_IFMT fmt_bx_indirect = {
1074 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1075 };
1076
1077 static const CGEN_IFMT fmt_bx_indirect_index = {
1078 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1079 };
1080
1081 static const CGEN_IFMT fmt_bx_disp = {
1082 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1083 };
1084
1085 static const CGEN_IFMT fmt_bx_indirect_disp = {
1086 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1087 };
1088
1089 static const CGEN_IFMT fmt_callx_disp = {
1090 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1091 };
1092
1093 static const CGEN_IFMT fmt_callx_indirect = {
1094 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
1095 };
1096
1097 static const CGEN_IFMT fmt_callx_indirect_offset = {
1098 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
1099 };
1100
1101 static const CGEN_IFMT fmt_ret = {
1102 32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
1103 };
1104
1105 static const CGEN_IFMT fmt_calls = {
1106 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
1107 };
1108
1109 static const CGEN_IFMT fmt_fmark = {
1110 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
1111 };
1112
1113 static const CGEN_IFMT fmt_flushreg = {
1114 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
1115 };
1116
1117 #undef F
1118
1119 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1120 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1121 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1122
1123 /* The instruction table.
1124 This is currently non-static because the simulator accesses it
1125 directly. */
1126
1127 const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
1128 {
1129 /* Special null first entry.
1130 A `num' value of zero is thus invalid.
1131 Also, the special `invalid' insn resides here. */
1132 { { 0 }, 0 },
1133 /* mulo $src1, $src2, $dst */
1134 {
1135 { 1, 1, 1, 1 },
1136 I960_INSN_MULO, "mulo", "mulo",
1137 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1138 & fmt_mulo, { 0x70000080 },
1139 (PTR) 0,
1140 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1141 },
1142 /* mulo $lit1, $src2, $dst */
1143 {
1144 { 1, 1, 1, 1 },
1145 I960_INSN_MULO1, "mulo1", "mulo",
1146 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1147 & fmt_mulo1, { 0x70000880 },
1148 (PTR) 0,
1149 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1150 },
1151 /* mulo $src1, $lit2, $dst */
1152 {
1153 { 1, 1, 1, 1 },
1154 I960_INSN_MULO2, "mulo2", "mulo",
1155 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1156 & fmt_mulo2, { 0x70001080 },
1157 (PTR) 0,
1158 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1159 },
1160 /* mulo $lit1, $lit2, $dst */
1161 {
1162 { 1, 1, 1, 1 },
1163 I960_INSN_MULO3, "mulo3", "mulo",
1164 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1165 & fmt_mulo3, { 0x70001880 },
1166 (PTR) 0,
1167 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1168 },
1169 /* remo $src1, $src2, $dst */
1170 {
1171 { 1, 1, 1, 1 },
1172 I960_INSN_REMO, "remo", "remo",
1173 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1174 & fmt_remo, { 0x70000400 },
1175 (PTR) 0,
1176 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1177 },
1178 /* remo $lit1, $src2, $dst */
1179 {
1180 { 1, 1, 1, 1 },
1181 I960_INSN_REMO1, "remo1", "remo",
1182 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1183 & fmt_remo1, { 0x70000c00 },
1184 (PTR) 0,
1185 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1186 },
1187 /* remo $src1, $lit2, $dst */
1188 {
1189 { 1, 1, 1, 1 },
1190 I960_INSN_REMO2, "remo2", "remo",
1191 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1192 & fmt_remo2, { 0x70001400 },
1193 (PTR) 0,
1194 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1195 },
1196 /* remo $lit1, $lit2, $dst */
1197 {
1198 { 1, 1, 1, 1 },
1199 I960_INSN_REMO3, "remo3", "remo",
1200 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1201 & fmt_remo3, { 0x70001c00 },
1202 (PTR) 0,
1203 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1204 },
1205 /* divo $src1, $src2, $dst */
1206 {
1207 { 1, 1, 1, 1 },
1208 I960_INSN_DIVO, "divo", "divo",
1209 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1210 & fmt_remo, { 0x70000580 },
1211 (PTR) 0,
1212 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1213 },
1214 /* divo $lit1, $src2, $dst */
1215 {
1216 { 1, 1, 1, 1 },
1217 I960_INSN_DIVO1, "divo1", "divo",
1218 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1219 & fmt_remo1, { 0x70000d80 },
1220 (PTR) 0,
1221 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1222 },
1223 /* divo $src1, $lit2, $dst */
1224 {
1225 { 1, 1, 1, 1 },
1226 I960_INSN_DIVO2, "divo2", "divo",
1227 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1228 & fmt_remo2, { 0x70001580 },
1229 (PTR) 0,
1230 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1231 },
1232 /* divo $lit1, $lit2, $dst */
1233 {
1234 { 1, 1, 1, 1 },
1235 I960_INSN_DIVO3, "divo3", "divo",
1236 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1237 & fmt_remo3, { 0x70001d80 },
1238 (PTR) 0,
1239 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1240 },
1241 /* remi $src1, $src2, $dst */
1242 {
1243 { 1, 1, 1, 1 },
1244 I960_INSN_REMI, "remi", "remi",
1245 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1246 & fmt_remo, { 0x74000400 },
1247 (PTR) 0,
1248 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1249 },
1250 /* remi $lit1, $src2, $dst */
1251 {
1252 { 1, 1, 1, 1 },
1253 I960_INSN_REMI1, "remi1", "remi",
1254 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1255 & fmt_remo1, { 0x74000c00 },
1256 (PTR) 0,
1257 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1258 },
1259 /* remi $src1, $lit2, $dst */
1260 {
1261 { 1, 1, 1, 1 },
1262 I960_INSN_REMI2, "remi2", "remi",
1263 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1264 & fmt_remo2, { 0x74001400 },
1265 (PTR) 0,
1266 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1267 },
1268 /* remi $lit1, $lit2, $dst */
1269 {
1270 { 1, 1, 1, 1 },
1271 I960_INSN_REMI3, "remi3", "remi",
1272 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1273 & fmt_remo3, { 0x74001c00 },
1274 (PTR) 0,
1275 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1276 },
1277 /* divi $src1, $src2, $dst */
1278 {
1279 { 1, 1, 1, 1 },
1280 I960_INSN_DIVI, "divi", "divi",
1281 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1282 & fmt_remo, { 0x74000580 },
1283 (PTR) 0,
1284 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1285 },
1286 /* divi $lit1, $src2, $dst */
1287 {
1288 { 1, 1, 1, 1 },
1289 I960_INSN_DIVI1, "divi1", "divi",
1290 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1291 & fmt_remo1, { 0x74000d80 },
1292 (PTR) 0,
1293 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1294 },
1295 /* divi $src1, $lit2, $dst */
1296 {
1297 { 1, 1, 1, 1 },
1298 I960_INSN_DIVI2, "divi2", "divi",
1299 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1300 & fmt_remo2, { 0x74001580 },
1301 (PTR) 0,
1302 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1303 },
1304 /* divi $lit1, $lit2, $dst */
1305 {
1306 { 1, 1, 1, 1 },
1307 I960_INSN_DIVI3, "divi3", "divi",
1308 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1309 & fmt_remo3, { 0x74001d80 },
1310 (PTR) 0,
1311 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1312 },
1313 /* addo $src1, $src2, $dst */
1314 {
1315 { 1, 1, 1, 1 },
1316 I960_INSN_ADDO, "addo", "addo",
1317 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1318 & fmt_mulo, { 0x59000000 },
1319 (PTR) 0,
1320 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1321 },
1322 /* addo $lit1, $src2, $dst */
1323 {
1324 { 1, 1, 1, 1 },
1325 I960_INSN_ADDO1, "addo1", "addo",
1326 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1327 & fmt_mulo1, { 0x59000800 },
1328 (PTR) 0,
1329 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1330 },
1331 /* addo $src1, $lit2, $dst */
1332 {
1333 { 1, 1, 1, 1 },
1334 I960_INSN_ADDO2, "addo2", "addo",
1335 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1336 & fmt_mulo2, { 0x59001000 },
1337 (PTR) 0,
1338 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1339 },
1340 /* addo $lit1, $lit2, $dst */
1341 {
1342 { 1, 1, 1, 1 },
1343 I960_INSN_ADDO3, "addo3", "addo",
1344 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1345 & fmt_mulo3, { 0x59001800 },
1346 (PTR) 0,
1347 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1348 },
1349 /* subo $src1, $src2, $dst */
1350 {
1351 { 1, 1, 1, 1 },
1352 I960_INSN_SUBO, "subo", "subo",
1353 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1354 & fmt_remo, { 0x59000100 },
1355 (PTR) 0,
1356 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1357 },
1358 /* subo $lit1, $src2, $dst */
1359 {
1360 { 1, 1, 1, 1 },
1361 I960_INSN_SUBO1, "subo1", "subo",
1362 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1363 & fmt_remo1, { 0x59000900 },
1364 (PTR) 0,
1365 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1366 },
1367 /* subo $src1, $lit2, $dst */
1368 {
1369 { 1, 1, 1, 1 },
1370 I960_INSN_SUBO2, "subo2", "subo",
1371 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1372 & fmt_remo2, { 0x59001100 },
1373 (PTR) 0,
1374 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1375 },
1376 /* subo $lit1, $lit2, $dst */
1377 {
1378 { 1, 1, 1, 1 },
1379 I960_INSN_SUBO3, "subo3", "subo",
1380 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1381 & fmt_remo3, { 0x59001900 },
1382 (PTR) 0,
1383 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1384 },
1385 /* notbit $src1, $src2, $dst */
1386 {
1387 { 1, 1, 1, 1 },
1388 I960_INSN_NOTBIT, "notbit", "notbit",
1389 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1390 & fmt_mulo, { 0x58000000 },
1391 (PTR) 0,
1392 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1393 },
1394 /* notbit $lit1, $src2, $dst */
1395 {
1396 { 1, 1, 1, 1 },
1397 I960_INSN_NOTBIT1, "notbit1", "notbit",
1398 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1399 & fmt_mulo1, { 0x58000800 },
1400 (PTR) 0,
1401 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1402 },
1403 /* notbit $src1, $lit2, $dst */
1404 {
1405 { 1, 1, 1, 1 },
1406 I960_INSN_NOTBIT2, "notbit2", "notbit",
1407 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1408 & fmt_mulo2, { 0x58001000 },
1409 (PTR) 0,
1410 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1411 },
1412 /* notbit $lit1, $lit2, $dst */
1413 {
1414 { 1, 1, 1, 1 },
1415 I960_INSN_NOTBIT3, "notbit3", "notbit",
1416 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1417 & fmt_mulo3, { 0x58001800 },
1418 (PTR) 0,
1419 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1420 },
1421 /* and $src1, $src2, $dst */
1422 {
1423 { 1, 1, 1, 1 },
1424 I960_INSN_AND, "and", "and",
1425 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1426 & fmt_mulo, { 0x58000080 },
1427 (PTR) 0,
1428 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1429 },
1430 /* and $lit1, $src2, $dst */
1431 {
1432 { 1, 1, 1, 1 },
1433 I960_INSN_AND1, "and1", "and",
1434 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1435 & fmt_mulo1, { 0x58000880 },
1436 (PTR) 0,
1437 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1438 },
1439 /* and $src1, $lit2, $dst */
1440 {
1441 { 1, 1, 1, 1 },
1442 I960_INSN_AND2, "and2", "and",
1443 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1444 & fmt_mulo2, { 0x58001080 },
1445 (PTR) 0,
1446 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1447 },
1448 /* and $lit1, $lit2, $dst */
1449 {
1450 { 1, 1, 1, 1 },
1451 I960_INSN_AND3, "and3", "and",
1452 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1453 & fmt_mulo3, { 0x58001880 },
1454 (PTR) 0,
1455 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1456 },
1457 /* andnot $src1, $src2, $dst */
1458 {
1459 { 1, 1, 1, 1 },
1460 I960_INSN_ANDNOT, "andnot", "andnot",
1461 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1462 & fmt_remo, { 0x58000100 },
1463 (PTR) 0,
1464 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1465 },
1466 /* andnot $lit1, $src2, $dst */
1467 {
1468 { 1, 1, 1, 1 },
1469 I960_INSN_ANDNOT1, "andnot1", "andnot",
1470 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1471 & fmt_remo1, { 0x58000900 },
1472 (PTR) 0,
1473 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1474 },
1475 /* andnot $src1, $lit2, $dst */
1476 {
1477 { 1, 1, 1, 1 },
1478 I960_INSN_ANDNOT2, "andnot2", "andnot",
1479 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1480 & fmt_remo2, { 0x58001100 },
1481 (PTR) 0,
1482 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1483 },
1484 /* andnot $lit1, $lit2, $dst */
1485 {
1486 { 1, 1, 1, 1 },
1487 I960_INSN_ANDNOT3, "andnot3", "andnot",
1488 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1489 & fmt_remo3, { 0x58001900 },
1490 (PTR) 0,
1491 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1492 },
1493 /* setbit $src1, $src2, $dst */
1494 {
1495 { 1, 1, 1, 1 },
1496 I960_INSN_SETBIT, "setbit", "setbit",
1497 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1498 & fmt_mulo, { 0x58000180 },
1499 (PTR) 0,
1500 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1501 },
1502 /* setbit $lit1, $src2, $dst */
1503 {
1504 { 1, 1, 1, 1 },
1505 I960_INSN_SETBIT1, "setbit1", "setbit",
1506 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1507 & fmt_mulo1, { 0x58000980 },
1508 (PTR) 0,
1509 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1510 },
1511 /* setbit $src1, $lit2, $dst */
1512 {
1513 { 1, 1, 1, 1 },
1514 I960_INSN_SETBIT2, "setbit2", "setbit",
1515 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1516 & fmt_mulo2, { 0x58001180 },
1517 (PTR) 0,
1518 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1519 },
1520 /* setbit $lit1, $lit2, $dst */
1521 {
1522 { 1, 1, 1, 1 },
1523 I960_INSN_SETBIT3, "setbit3", "setbit",
1524 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1525 & fmt_mulo3, { 0x58001980 },
1526 (PTR) 0,
1527 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1528 },
1529 /* notand $src1, $src2, $dst */
1530 {
1531 { 1, 1, 1, 1 },
1532 I960_INSN_NOTAND, "notand", "notand",
1533 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1534 & fmt_remo, { 0x58000200 },
1535 (PTR) 0,
1536 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1537 },
1538 /* notand $lit1, $src2, $dst */
1539 {
1540 { 1, 1, 1, 1 },
1541 I960_INSN_NOTAND1, "notand1", "notand",
1542 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1543 & fmt_remo1, { 0x58000a00 },
1544 (PTR) 0,
1545 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1546 },
1547 /* notand $src1, $lit2, $dst */
1548 {
1549 { 1, 1, 1, 1 },
1550 I960_INSN_NOTAND2, "notand2", "notand",
1551 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1552 & fmt_remo2, { 0x58001200 },
1553 (PTR) 0,
1554 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1555 },
1556 /* notand $lit1, $lit2, $dst */
1557 {
1558 { 1, 1, 1, 1 },
1559 I960_INSN_NOTAND3, "notand3", "notand",
1560 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1561 & fmt_remo3, { 0x58001a00 },
1562 (PTR) 0,
1563 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1564 },
1565 /* xor $src1, $src2, $dst */
1566 {
1567 { 1, 1, 1, 1 },
1568 I960_INSN_XOR, "xor", "xor",
1569 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1570 & fmt_mulo, { 0x58000300 },
1571 (PTR) 0,
1572 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1573 },
1574 /* xor $lit1, $src2, $dst */
1575 {
1576 { 1, 1, 1, 1 },
1577 I960_INSN_XOR1, "xor1", "xor",
1578 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1579 & fmt_mulo1, { 0x58000b00 },
1580 (PTR) 0,
1581 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1582 },
1583 /* xor $src1, $lit2, $dst */
1584 {
1585 { 1, 1, 1, 1 },
1586 I960_INSN_XOR2, "xor2", "xor",
1587 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1588 & fmt_mulo2, { 0x58001300 },
1589 (PTR) 0,
1590 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1591 },
1592 /* xor $lit1, $lit2, $dst */
1593 {
1594 { 1, 1, 1, 1 },
1595 I960_INSN_XOR3, "xor3", "xor",
1596 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1597 & fmt_mulo3, { 0x58001b00 },
1598 (PTR) 0,
1599 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1600 },
1601 /* or $src1, $src2, $dst */
1602 {
1603 { 1, 1, 1, 1 },
1604 I960_INSN_OR, "or", "or",
1605 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1606 & fmt_mulo, { 0x58000380 },
1607 (PTR) 0,
1608 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1609 },
1610 /* or $lit1, $src2, $dst */
1611 {
1612 { 1, 1, 1, 1 },
1613 I960_INSN_OR1, "or1", "or",
1614 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1615 & fmt_mulo1, { 0x58000b80 },
1616 (PTR) 0,
1617 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1618 },
1619 /* or $src1, $lit2, $dst */
1620 {
1621 { 1, 1, 1, 1 },
1622 I960_INSN_OR2, "or2", "or",
1623 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1624 & fmt_mulo2, { 0x58001380 },
1625 (PTR) 0,
1626 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1627 },
1628 /* or $lit1, $lit2, $dst */
1629 {
1630 { 1, 1, 1, 1 },
1631 I960_INSN_OR3, "or3", "or",
1632 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1633 & fmt_mulo3, { 0x58001b80 },
1634 (PTR) 0,
1635 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1636 },
1637 /* nor $src1, $src2, $dst */
1638 {
1639 { 1, 1, 1, 1 },
1640 I960_INSN_NOR, "nor", "nor",
1641 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1642 & fmt_remo, { 0x58000400 },
1643 (PTR) 0,
1644 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1645 },
1646 /* nor $lit1, $src2, $dst */
1647 {
1648 { 1, 1, 1, 1 },
1649 I960_INSN_NOR1, "nor1", "nor",
1650 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1651 & fmt_remo1, { 0x58000c00 },
1652 (PTR) 0,
1653 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1654 },
1655 /* nor $src1, $lit2, $dst */
1656 {
1657 { 1, 1, 1, 1 },
1658 I960_INSN_NOR2, "nor2", "nor",
1659 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1660 & fmt_remo2, { 0x58001400 },
1661 (PTR) 0,
1662 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1663 },
1664 /* nor $lit1, $lit2, $dst */
1665 {
1666 { 1, 1, 1, 1 },
1667 I960_INSN_NOR3, "nor3", "nor",
1668 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1669 & fmt_remo3, { 0x58001c00 },
1670 (PTR) 0,
1671 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1672 },
1673 /* not $src1, $src2, $dst */
1674 {
1675 { 1, 1, 1, 1 },
1676 I960_INSN_NOT, "not", "not",
1677 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1678 & fmt_not, { 0x58000500 },
1679 (PTR) 0,
1680 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1681 },
1682 /* not $lit1, $src2, $dst */
1683 {
1684 { 1, 1, 1, 1 },
1685 I960_INSN_NOT1, "not1", "not",
1686 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1687 & fmt_not1, { 0x58000d00 },
1688 (PTR) 0,
1689 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1690 },
1691 /* not $src1, $lit2, $dst */
1692 {
1693 { 1, 1, 1, 1 },
1694 I960_INSN_NOT2, "not2", "not",
1695 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1696 & fmt_not2, { 0x58001500 },
1697 (PTR) 0,
1698 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1699 },
1700 /* not $lit1, $lit2, $dst */
1701 {
1702 { 1, 1, 1, 1 },
1703 I960_INSN_NOT3, "not3", "not",
1704 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1705 & fmt_not3, { 0x58001d00 },
1706 (PTR) 0,
1707 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1708 },
1709 /* clrbit $src1, $src2, $dst */
1710 {
1711 { 1, 1, 1, 1 },
1712 I960_INSN_CLRBIT, "clrbit", "clrbit",
1713 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1714 & fmt_mulo, { 0x58000600 },
1715 (PTR) 0,
1716 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1717 },
1718 /* clrbit $lit1, $src2, $dst */
1719 {
1720 { 1, 1, 1, 1 },
1721 I960_INSN_CLRBIT1, "clrbit1", "clrbit",
1722 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1723 & fmt_mulo1, { 0x58000e00 },
1724 (PTR) 0,
1725 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1726 },
1727 /* clrbit $src1, $lit2, $dst */
1728 {
1729 { 1, 1, 1, 1 },
1730 I960_INSN_CLRBIT2, "clrbit2", "clrbit",
1731 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1732 & fmt_mulo2, { 0x58001600 },
1733 (PTR) 0,
1734 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1735 },
1736 /* clrbit $lit1, $lit2, $dst */
1737 {
1738 { 1, 1, 1, 1 },
1739 I960_INSN_CLRBIT3, "clrbit3", "clrbit",
1740 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1741 & fmt_mulo3, { 0x58001e00 },
1742 (PTR) 0,
1743 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1744 },
1745 /* shlo $src1, $src2, $dst */
1746 {
1747 { 1, 1, 1, 1 },
1748 I960_INSN_SHLO, "shlo", "shlo",
1749 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1750 & fmt_remo, { 0x59000600 },
1751 (PTR) 0,
1752 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1753 },
1754 /* shlo $lit1, $src2, $dst */
1755 {
1756 { 1, 1, 1, 1 },
1757 I960_INSN_SHLO1, "shlo1", "shlo",
1758 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1759 & fmt_remo1, { 0x59000e00 },
1760 (PTR) 0,
1761 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1762 },
1763 /* shlo $src1, $lit2, $dst */
1764 {
1765 { 1, 1, 1, 1 },
1766 I960_INSN_SHLO2, "shlo2", "shlo",
1767 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1768 & fmt_remo2, { 0x59001600 },
1769 (PTR) 0,
1770 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1771 },
1772 /* shlo $lit1, $lit2, $dst */
1773 {
1774 { 1, 1, 1, 1 },
1775 I960_INSN_SHLO3, "shlo3", "shlo",
1776 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1777 & fmt_remo3, { 0x59001e00 },
1778 (PTR) 0,
1779 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1780 },
1781 /* shro $src1, $src2, $dst */
1782 {
1783 { 1, 1, 1, 1 },
1784 I960_INSN_SHRO, "shro", "shro",
1785 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1786 & fmt_remo, { 0x59000400 },
1787 (PTR) 0,
1788 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1789 },
1790 /* shro $lit1, $src2, $dst */
1791 {
1792 { 1, 1, 1, 1 },
1793 I960_INSN_SHRO1, "shro1", "shro",
1794 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1795 & fmt_remo1, { 0x59000c00 },
1796 (PTR) 0,
1797 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1798 },
1799 /* shro $src1, $lit2, $dst */
1800 {
1801 { 1, 1, 1, 1 },
1802 I960_INSN_SHRO2, "shro2", "shro",
1803 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1804 & fmt_remo2, { 0x59001400 },
1805 (PTR) 0,
1806 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1807 },
1808 /* shro $lit1, $lit2, $dst */
1809 {
1810 { 1, 1, 1, 1 },
1811 I960_INSN_SHRO3, "shro3", "shro",
1812 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1813 & fmt_remo3, { 0x59001c00 },
1814 (PTR) 0,
1815 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1816 },
1817 /* shli $src1, $src2, $dst */
1818 {
1819 { 1, 1, 1, 1 },
1820 I960_INSN_SHLI, "shli", "shli",
1821 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1822 & fmt_remo, { 0x59000700 },
1823 (PTR) 0,
1824 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1825 },
1826 /* shli $lit1, $src2, $dst */
1827 {
1828 { 1, 1, 1, 1 },
1829 I960_INSN_SHLI1, "shli1", "shli",
1830 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1831 & fmt_remo1, { 0x59000f00 },
1832 (PTR) 0,
1833 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1834 },
1835 /* shli $src1, $lit2, $dst */
1836 {
1837 { 1, 1, 1, 1 },
1838 I960_INSN_SHLI2, "shli2", "shli",
1839 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1840 & fmt_remo2, { 0x59001700 },
1841 (PTR) 0,
1842 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1843 },
1844 /* shli $lit1, $lit2, $dst */
1845 {
1846 { 1, 1, 1, 1 },
1847 I960_INSN_SHLI3, "shli3", "shli",
1848 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1849 & fmt_remo3, { 0x59001f00 },
1850 (PTR) 0,
1851 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1852 },
1853 /* shri $src1, $src2, $dst */
1854 {
1855 { 1, 1, 1, 1 },
1856 I960_INSN_SHRI, "shri", "shri",
1857 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1858 & fmt_remo, { 0x59000580 },
1859 (PTR) 0,
1860 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1861 },
1862 /* shri $lit1, $src2, $dst */
1863 {
1864 { 1, 1, 1, 1 },
1865 I960_INSN_SHRI1, "shri1", "shri",
1866 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1867 & fmt_remo1, { 0x59000d80 },
1868 (PTR) 0,
1869 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1870 },
1871 /* shri $src1, $lit2, $dst */
1872 {
1873 { 1, 1, 1, 1 },
1874 I960_INSN_SHRI2, "shri2", "shri",
1875 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1876 & fmt_remo2, { 0x59001580 },
1877 (PTR) 0,
1878 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1879 },
1880 /* shri $lit1, $lit2, $dst */
1881 {
1882 { 1, 1, 1, 1 },
1883 I960_INSN_SHRI3, "shri3", "shri",
1884 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1885 & fmt_remo3, { 0x59001d80 },
1886 (PTR) 0,
1887 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1888 },
1889 /* emul $src1, $src2, $dst */
1890 {
1891 { 1, 1, 1, 1 },
1892 I960_INSN_EMUL, "emul", "emul",
1893 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1894 & fmt_emul, { 0x67000000 },
1895 (PTR) 0,
1896 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1897 },
1898 /* emul $lit1, $src2, $dst */
1899 {
1900 { 1, 1, 1, 1 },
1901 I960_INSN_EMUL1, "emul1", "emul",
1902 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1903 & fmt_emul1, { 0x67000800 },
1904 (PTR) 0,
1905 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1906 },
1907 /* emul $src1, $lit2, $dst */
1908 {
1909 { 1, 1, 1, 1 },
1910 I960_INSN_EMUL2, "emul2", "emul",
1911 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1912 & fmt_emul2, { 0x67001000 },
1913 (PTR) 0,
1914 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1915 },
1916 /* emul $lit1, $lit2, $dst */
1917 {
1918 { 1, 1, 1, 1 },
1919 I960_INSN_EMUL3, "emul3", "emul",
1920 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1921 & fmt_emul3, { 0x67001800 },
1922 (PTR) 0,
1923 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1924 },
1925 /* mov $src1, $dst */
1926 {
1927 { 1, 1, 1, 1 },
1928 I960_INSN_MOV, "mov", "mov",
1929 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
1930 & fmt_not2, { 0x5c001600 },
1931 (PTR) 0,
1932 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1933 },
1934 /* mov $lit1, $dst */
1935 {
1936 { 1, 1, 1, 1 },
1937 I960_INSN_MOV1, "mov1", "mov",
1938 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
1939 & fmt_not3, { 0x5c001e00 },
1940 (PTR) 0,
1941 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1942 },
1943 /* movl $src1, $dst */
1944 {
1945 { 1, 1, 1, 1 },
1946 I960_INSN_MOVL, "movl", "movl",
1947 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
1948 & fmt_movl, { 0x5d001600 },
1949 (PTR) 0,
1950 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1951 },
1952 /* movl $lit1, $dst */
1953 {
1954 { 1, 1, 1, 1 },
1955 I960_INSN_MOVL1, "movl1", "movl",
1956 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
1957 & fmt_movl1, { 0x5d001e00 },
1958 (PTR) 0,
1959 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1960 },
1961 /* movt $src1, $dst */
1962 {
1963 { 1, 1, 1, 1 },
1964 I960_INSN_MOVT, "movt", "movt",
1965 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
1966 & fmt_movt, { 0x5e001600 },
1967 (PTR) 0,
1968 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1969 },
1970 /* movt $lit1, $dst */
1971 {
1972 { 1, 1, 1, 1 },
1973 I960_INSN_MOVT1, "movt1", "movt",
1974 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
1975 & fmt_movt1, { 0x5e001e00 },
1976 (PTR) 0,
1977 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1978 },
1979 /* movq $src1, $dst */
1980 {
1981 { 1, 1, 1, 1 },
1982 I960_INSN_MOVQ, "movq", "movq",
1983 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
1984 & fmt_movq, { 0x5f001600 },
1985 (PTR) 0,
1986 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1987 },
1988 /* movq $lit1, $dst */
1989 {
1990 { 1, 1, 1, 1 },
1991 I960_INSN_MOVQ1, "movq1", "movq",
1992 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
1993 & fmt_movq1, { 0x5f001e00 },
1994 (PTR) 0,
1995 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1996 },
1997 /* modpc $src1, $src2, $dst */
1998 {
1999 { 1, 1, 1, 1 },
2000 I960_INSN_MODPC, "modpc", "modpc",
2001 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
2002 & fmt_modpc, { 0x65000280 },
2003 (PTR) 0,
2004 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2005 },
2006 /* modac $src1, $src2, $dst */
2007 {
2008 { 1, 1, 1, 1 },
2009 I960_INSN_MODAC, "modac", "modac",
2010 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
2011 & fmt_modpc, { 0x64000280 },
2012 (PTR) 0,
2013 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2014 },
2015 /* lda $offset, $dst */
2016 {
2017 { 1, 1, 1, 1 },
2018 I960_INSN_LDA_OFFSET, "lda-offset", "lda",
2019 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
2020 & fmt_lda_offset, { 0x8c000000 },
2021 (PTR) 0,
2022 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2023 },
2024 /* lda $offset($abase), $dst */
2025 {
2026 { 1, 1, 1, 1 },
2027 I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda",
2028 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2029 & fmt_lda_indirect_offset, { 0x8c002000 },
2030 (PTR) 0,
2031 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2032 },
2033 /* lda ($abase), $dst */
2034 {
2035 { 1, 1, 1, 1 },
2036 I960_INSN_LDA_INDIRECT, "lda-indirect", "lda",
2037 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2038 & fmt_lda_indirect, { 0x8c001000 },
2039 (PTR) 0,
2040 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2041 },
2042 /* lda ($abase)[$index*S$scale], $dst */
2043 {
2044 { 1, 1, 1, 1 },
2045 I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda",
2046 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2047 & fmt_lda_indirect_index, { 0x8c001c00 },
2048 (PTR) 0,
2049 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2050 },
2051 /* lda $optdisp, $dst */
2052 {
2053 { 1, 1, 1, 1 },
2054 I960_INSN_LDA_DISP, "lda-disp", "lda",
2055 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
2056 & fmt_lda_disp, { 0x8c003000 },
2057 (PTR) 0,
2058 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2059 },
2060 /* lda $optdisp($abase), $dst */
2061 {
2062 { 1, 1, 1, 1 },
2063 I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda",
2064 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2065 & fmt_lda_indirect_disp, { 0x8c003400 },
2066 (PTR) 0,
2067 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2068 },
2069 /* lda $optdisp[$index*S$scale], $dst */
2070 {
2071 { 1, 1, 1, 1 },
2072 I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda",
2073 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2074 & fmt_lda_index_disp, { 0x8c003800 },
2075 (PTR) 0,
2076 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2077 },
2078 /* lda $optdisp($abase)[$index*S$scale], $dst */
2079 {
2080 { 1, 1, 1, 1 },
2081 I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda",
2082 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2083 & fmt_lda_indirect_index_disp, { 0x8c003c00 },
2084 (PTR) 0,
2085 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2086 },
2087 /* ld $offset, $dst */
2088 {
2089 { 1, 1, 1, 1 },
2090 I960_INSN_LD_OFFSET, "ld-offset", "ld",
2091 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
2092 & fmt_ld_offset, { 0x90000000 },
2093 (PTR) 0,
2094 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2095 },
2096 /* ld $offset($abase), $dst */
2097 {
2098 { 1, 1, 1, 1 },
2099 I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld",
2100 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2101 & fmt_ld_indirect_offset, { 0x90002000 },
2102 (PTR) 0,
2103 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2104 },
2105 /* ld ($abase), $dst */
2106 {
2107 { 1, 1, 1, 1 },
2108 I960_INSN_LD_INDIRECT, "ld-indirect", "ld",
2109 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2110 & fmt_ld_indirect, { 0x90001000 },
2111 (PTR) 0,
2112 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2113 },
2114 /* ld ($abase)[$index*S$scale], $dst */
2115 {
2116 { 1, 1, 1, 1 },
2117 I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld",
2118 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2119 & fmt_ld_indirect_index, { 0x90001c00 },
2120 (PTR) 0,
2121 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2122 },
2123 /* ld $optdisp, $dst */
2124 {
2125 { 1, 1, 1, 1 },
2126 I960_INSN_LD_DISP, "ld-disp", "ld",
2127 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
2128 & fmt_ld_disp, { 0x90003000 },
2129 (PTR) 0,
2130 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2131 },
2132 /* ld $optdisp($abase), $dst */
2133 {
2134 { 1, 1, 1, 1 },
2135 I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld",
2136 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2137 & fmt_ld_indirect_disp, { 0x90003400 },
2138 (PTR) 0,
2139 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2140 },
2141 /* ld $optdisp[$index*S$scale], $dst */
2142 {
2143 { 1, 1, 1, 1 },
2144 I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld",
2145 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2146 & fmt_ld_index_disp, { 0x90003800 },
2147 (PTR) 0,
2148 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2149 },
2150 /* ld $optdisp($abase)[$index*S$scale], $dst */
2151 {
2152 { 1, 1, 1, 1 },
2153 I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld",
2154 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2155 & fmt_ld_indirect_index_disp, { 0x90003c00 },
2156 (PTR) 0,
2157 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2158 },
2159 /* ldob $offset, $dst */
2160 {
2161 { 1, 1, 1, 1 },
2162 I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob",
2163 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
2164 & fmt_ldob_offset, { 0x80000000 },
2165 (PTR) 0,
2166 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2167 },
2168 /* ldob $offset($abase), $dst */
2169 {
2170 { 1, 1, 1, 1 },
2171 I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob",
2172 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2173 & fmt_ldob_indirect_offset, { 0x80002000 },
2174 (PTR) 0,
2175 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2176 },
2177 /* ldob ($abase), $dst */
2178 {
2179 { 1, 1, 1, 1 },
2180 I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob",
2181 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2182 & fmt_ldob_indirect, { 0x80001000 },
2183 (PTR) 0,
2184 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2185 },
2186 /* ldob ($abase)[$index*S$scale], $dst */
2187 {
2188 { 1, 1, 1, 1 },
2189 I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob",
2190 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2191 & fmt_ldob_indirect_index, { 0x80001c00 },
2192 (PTR) 0,
2193 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2194 },
2195 /* ldob $optdisp, $dst */
2196 {
2197 { 1, 1, 1, 1 },
2198 I960_INSN_LDOB_DISP, "ldob-disp", "ldob",
2199 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
2200 & fmt_ldob_disp, { 0x80003000 },
2201 (PTR) 0,
2202 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2203 },
2204 /* ldob $optdisp($abase), $dst */
2205 {
2206 { 1, 1, 1, 1 },
2207 I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob",
2208 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2209 & fmt_ldob_indirect_disp, { 0x80003400 },
2210 (PTR) 0,
2211 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2212 },
2213 /* ldob $optdisp[$index*S$scale], $dst */
2214 {
2215 { 1, 1, 1, 1 },
2216 I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob",
2217 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2218 & fmt_ldob_index_disp, { 0x80003800 },
2219 (PTR) 0,
2220 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2221 },
2222 /* ldob $optdisp($abase)[$index*S$scale], $dst */
2223 {
2224 { 1, 1, 1, 1 },
2225 I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob",
2226 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2227 & fmt_ldob_indirect_index_disp, { 0x80003c00 },
2228 (PTR) 0,
2229 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2230 },
2231 /* ldos $offset, $dst */
2232 {
2233 { 1, 1, 1, 1 },
2234 I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos",
2235 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
2236 & fmt_ldos_offset, { 0x88000000 },
2237 (PTR) 0,
2238 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2239 },
2240 /* ldos $offset($abase), $dst */
2241 {
2242 { 1, 1, 1, 1 },
2243 I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos",
2244 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2245 & fmt_ldos_indirect_offset, { 0x88002000 },
2246 (PTR) 0,
2247 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2248 },
2249 /* ldos ($abase), $dst */
2250 {
2251 { 1, 1, 1, 1 },
2252 I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos",
2253 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2254 & fmt_ldos_indirect, { 0x88001000 },
2255 (PTR) 0,
2256 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2257 },
2258 /* ldos ($abase)[$index*S$scale], $dst */
2259 {
2260 { 1, 1, 1, 1 },
2261 I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos",
2262 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2263 & fmt_ldos_indirect_index, { 0x88001c00 },
2264 (PTR) 0,
2265 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2266 },
2267 /* ldos $optdisp, $dst */
2268 {
2269 { 1, 1, 1, 1 },
2270 I960_INSN_LDOS_DISP, "ldos-disp", "ldos",
2271 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
2272 & fmt_ldos_disp, { 0x88003000 },
2273 (PTR) 0,
2274 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2275 },
2276 /* ldos $optdisp($abase), $dst */
2277 {
2278 { 1, 1, 1, 1 },
2279 I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos",
2280 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2281 & fmt_ldos_indirect_disp, { 0x88003400 },
2282 (PTR) 0,
2283 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2284 },
2285 /* ldos $optdisp[$index*S$scale], $dst */
2286 {
2287 { 1, 1, 1, 1 },
2288 I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos",
2289 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2290 & fmt_ldos_index_disp, { 0x88003800 },
2291 (PTR) 0,
2292 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2293 },
2294 /* ldos $optdisp($abase)[$index*S$scale], $dst */
2295 {
2296 { 1, 1, 1, 1 },
2297 I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos",
2298 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2299 & fmt_ldos_indirect_index_disp, { 0x88003c00 },
2300 (PTR) 0,
2301 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2302 },
2303 /* ldib $offset, $dst */
2304 {
2305 { 1, 1, 1, 1 },
2306 I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib",
2307 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
2308 & fmt_ldib_offset, { 0xc0000000 },
2309 (PTR) 0,
2310 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2311 },
2312 /* ldib $offset($abase), $dst */
2313 {
2314 { 1, 1, 1, 1 },
2315 I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib",
2316 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2317 & fmt_ldib_indirect_offset, { 0xc0002000 },
2318 (PTR) 0,
2319 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2320 },
2321 /* ldib ($abase), $dst */
2322 {
2323 { 1, 1, 1, 1 },
2324 I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib",
2325 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2326 & fmt_ldib_indirect, { 0xc0001000 },
2327 (PTR) 0,
2328 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2329 },
2330 /* ldib ($abase)[$index*S$scale], $dst */
2331 {
2332 { 1, 1, 1, 1 },
2333 I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib",
2334 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2335 & fmt_ldib_indirect_index, { 0xc0001c00 },
2336 (PTR) 0,
2337 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2338 },
2339 /* ldib $optdisp, $dst */
2340 {
2341 { 1, 1, 1, 1 },
2342 I960_INSN_LDIB_DISP, "ldib-disp", "ldib",
2343 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
2344 & fmt_ldib_disp, { 0xc0003000 },
2345 (PTR) 0,
2346 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2347 },
2348 /* ldib $optdisp($abase), $dst */
2349 {
2350 { 1, 1, 1, 1 },
2351 I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib",
2352 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2353 & fmt_ldib_indirect_disp, { 0xc0003400 },
2354 (PTR) 0,
2355 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2356 },
2357 /* ldib $optdisp[$index*S$scale], $dst */
2358 {
2359 { 1, 1, 1, 1 },
2360 I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib",
2361 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2362 & fmt_ldib_index_disp, { 0xc0003800 },
2363 (PTR) 0,
2364 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2365 },
2366 /* ldib $optdisp($abase)[$index*S$scale], $dst */
2367 {
2368 { 1, 1, 1, 1 },
2369 I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib",
2370 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2371 & fmt_ldib_indirect_index_disp, { 0xc0003c00 },
2372 (PTR) 0,
2373 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2374 },
2375 /* ldis $offset, $dst */
2376 {
2377 { 1, 1, 1, 1 },
2378 I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis",
2379 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
2380 & fmt_ldis_offset, { 0xc8000000 },
2381 (PTR) 0,
2382 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2383 },
2384 /* ldis $offset($abase), $dst */
2385 {
2386 { 1, 1, 1, 1 },
2387 I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis",
2388 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2389 & fmt_ldis_indirect_offset, { 0xc8002000 },
2390 (PTR) 0,
2391 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2392 },
2393 /* ldis ($abase), $dst */
2394 {
2395 { 1, 1, 1, 1 },
2396 I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis",
2397 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2398 & fmt_ldis_indirect, { 0xc8001000 },
2399 (PTR) 0,
2400 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2401 },
2402 /* ldis ($abase)[$index*S$scale], $dst */
2403 {
2404 { 1, 1, 1, 1 },
2405 I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis",
2406 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2407 & fmt_ldis_indirect_index, { 0xc8001c00 },
2408 (PTR) 0,
2409 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2410 },
2411 /* ldis $optdisp, $dst */
2412 {
2413 { 1, 1, 1, 1 },
2414 I960_INSN_LDIS_DISP, "ldis-disp", "ldis",
2415 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
2416 & fmt_ldis_disp, { 0xc8003000 },
2417 (PTR) 0,
2418 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2419 },
2420 /* ldis $optdisp($abase), $dst */
2421 {
2422 { 1, 1, 1, 1 },
2423 I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis",
2424 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2425 & fmt_ldis_indirect_disp, { 0xc8003400 },
2426 (PTR) 0,
2427 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2428 },
2429 /* ldis $optdisp[$index*S$scale], $dst */
2430 {
2431 { 1, 1, 1, 1 },
2432 I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis",
2433 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2434 & fmt_ldis_index_disp, { 0xc8003800 },
2435 (PTR) 0,
2436 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2437 },
2438 /* ldis $optdisp($abase)[$index*S$scale], $dst */
2439 {
2440 { 1, 1, 1, 1 },
2441 I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis",
2442 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2443 & fmt_ldis_indirect_index_disp, { 0xc8003c00 },
2444 (PTR) 0,
2445 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2446 },
2447 /* ldl $offset, $dst */
2448 {
2449 { 1, 1, 1, 1 },
2450 I960_INSN_LDL_OFFSET, "ldl-offset", "ldl",
2451 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
2452 & fmt_ldl_offset, { 0x98000000 },
2453 (PTR) 0,
2454 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2455 },
2456 /* ldl $offset($abase), $dst */
2457 {
2458 { 1, 1, 1, 1 },
2459 I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl",
2460 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2461 & fmt_ldl_indirect_offset, { 0x98002000 },
2462 (PTR) 0,
2463 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2464 },
2465 /* ldl ($abase), $dst */
2466 {
2467 { 1, 1, 1, 1 },
2468 I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl",
2469 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2470 & fmt_ldl_indirect, { 0x98001000 },
2471 (PTR) 0,
2472 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2473 },
2474 /* ldl ($abase)[$index*S$scale], $dst */
2475 {
2476 { 1, 1, 1, 1 },
2477 I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl",
2478 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2479 & fmt_ldl_indirect_index, { 0x98001c00 },
2480 (PTR) 0,
2481 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2482 },
2483 /* ldl $optdisp, $dst */
2484 {
2485 { 1, 1, 1, 1 },
2486 I960_INSN_LDL_DISP, "ldl-disp", "ldl",
2487 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
2488 & fmt_ldl_disp, { 0x98003000 },
2489 (PTR) 0,
2490 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2491 },
2492 /* ldl $optdisp($abase), $dst */
2493 {
2494 { 1, 1, 1, 1 },
2495 I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl",
2496 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2497 & fmt_ldl_indirect_disp, { 0x98003400 },
2498 (PTR) 0,
2499 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2500 },
2501 /* ldl $optdisp[$index*S$scale], $dst */
2502 {
2503 { 1, 1, 1, 1 },
2504 I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl",
2505 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2506 & fmt_ldl_index_disp, { 0x98003800 },
2507 (PTR) 0,
2508 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2509 },
2510 /* ldl $optdisp($abase)[$index*S$scale], $dst */
2511 {
2512 { 1, 1, 1, 1 },
2513 I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl",
2514 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2515 & fmt_ldl_indirect_index_disp, { 0x98003c00 },
2516 (PTR) 0,
2517 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2518 },
2519 /* ldt $offset, $dst */
2520 {
2521 { 1, 1, 1, 1 },
2522 I960_INSN_LDT_OFFSET, "ldt-offset", "ldt",
2523 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
2524 & fmt_ldt_offset, { 0xa0000000 },
2525 (PTR) 0,
2526 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2527 },
2528 /* ldt $offset($abase), $dst */
2529 {
2530 { 1, 1, 1, 1 },
2531 I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt",
2532 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2533 & fmt_ldt_indirect_offset, { 0xa0002000 },
2534 (PTR) 0,
2535 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2536 },
2537 /* ldt ($abase), $dst */
2538 {
2539 { 1, 1, 1, 1 },
2540 I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt",
2541 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2542 & fmt_ldt_indirect, { 0xa0001000 },
2543 (PTR) 0,
2544 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2545 },
2546 /* ldt ($abase)[$index*S$scale], $dst */
2547 {
2548 { 1, 1, 1, 1 },
2549 I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt",
2550 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2551 & fmt_ldt_indirect_index, { 0xa0001c00 },
2552 (PTR) 0,
2553 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2554 },
2555 /* ldt $optdisp, $dst */
2556 {
2557 { 1, 1, 1, 1 },
2558 I960_INSN_LDT_DISP, "ldt-disp", "ldt",
2559 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
2560 & fmt_ldt_disp, { 0xa0003000 },
2561 (PTR) 0,
2562 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2563 },
2564 /* ldt $optdisp($abase), $dst */
2565 {
2566 { 1, 1, 1, 1 },
2567 I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt",
2568 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2569 & fmt_ldt_indirect_disp, { 0xa0003400 },
2570 (PTR) 0,
2571 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2572 },
2573 /* ldt $optdisp[$index*S$scale], $dst */
2574 {
2575 { 1, 1, 1, 1 },
2576 I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt",
2577 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2578 & fmt_ldt_index_disp, { 0xa0003800 },
2579 (PTR) 0,
2580 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2581 },
2582 /* ldt $optdisp($abase)[$index*S$scale], $dst */
2583 {
2584 { 1, 1, 1, 1 },
2585 I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt",
2586 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2587 & fmt_ldt_indirect_index_disp, { 0xa0003c00 },
2588 (PTR) 0,
2589 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2590 },
2591 /* ldq $offset, $dst */
2592 {
2593 { 1, 1, 1, 1 },
2594 I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq",
2595 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
2596 & fmt_ldq_offset, { 0xb0000000 },
2597 (PTR) 0,
2598 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2599 },
2600 /* ldq $offset($abase), $dst */
2601 {
2602 { 1, 1, 1, 1 },
2603 I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq",
2604 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2605 & fmt_ldq_indirect_offset, { 0xb0002000 },
2606 (PTR) 0,
2607 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2608 },
2609 /* ldq ($abase), $dst */
2610 {
2611 { 1, 1, 1, 1 },
2612 I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq",
2613 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2614 & fmt_ldq_indirect, { 0xb0001000 },
2615 (PTR) 0,
2616 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2617 },
2618 /* ldq ($abase)[$index*S$scale], $dst */
2619 {
2620 { 1, 1, 1, 1 },
2621 I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq",
2622 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2623 & fmt_ldq_indirect_index, { 0xb0001c00 },
2624 (PTR) 0,
2625 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2626 },
2627 /* ldq $optdisp, $dst */
2628 {
2629 { 1, 1, 1, 1 },
2630 I960_INSN_LDQ_DISP, "ldq-disp", "ldq",
2631 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
2632 & fmt_ldq_disp, { 0xb0003000 },
2633 (PTR) 0,
2634 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2635 },
2636 /* ldq $optdisp($abase), $dst */
2637 {
2638 { 1, 1, 1, 1 },
2639 I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq",
2640 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2641 & fmt_ldq_indirect_disp, { 0xb0003400 },
2642 (PTR) 0,
2643 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2644 },
2645 /* ldq $optdisp[$index*S$scale], $dst */
2646 {
2647 { 1, 1, 1, 1 },
2648 I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq",
2649 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2650 & fmt_ldq_index_disp, { 0xb0003800 },
2651 (PTR) 0,
2652 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2653 },
2654 /* ldq $optdisp($abase)[$index*S$scale], $dst */
2655 {
2656 { 1, 1, 1, 1 },
2657 I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq",
2658 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2659 & fmt_ldq_indirect_index_disp, { 0xb0003c00 },
2660 (PTR) 0,
2661 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2662 },
2663 /* st $st_src, $offset */
2664 {
2665 { 1, 1, 1, 1 },
2666 I960_INSN_ST_OFFSET, "st-offset", "st",
2667 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2668 & fmt_st_offset, { 0x92000000 },
2669 (PTR) 0,
2670 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2671 },
2672 /* st $st_src, $offset($abase) */
2673 {
2674 { 1, 1, 1, 1 },
2675 I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st",
2676 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2677 & fmt_st_indirect_offset, { 0x92002000 },
2678 (PTR) 0,
2679 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2680 },
2681 /* st $st_src, ($abase) */
2682 {
2683 { 1, 1, 1, 1 },
2684 I960_INSN_ST_INDIRECT, "st-indirect", "st",
2685 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2686 & fmt_st_indirect, { 0x92001000 },
2687 (PTR) 0,
2688 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2689 },
2690 /* st $st_src, ($abase)[$index*S$scale] */
2691 {
2692 { 1, 1, 1, 1 },
2693 I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st",
2694 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2695 & fmt_st_indirect_index, { 0x92001c00 },
2696 (PTR) 0,
2697 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2698 },
2699 /* st $st_src, $optdisp */
2700 {
2701 { 1, 1, 1, 1 },
2702 I960_INSN_ST_DISP, "st-disp", "st",
2703 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2704 & fmt_st_disp, { 0x92003000 },
2705 (PTR) 0,
2706 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2707 },
2708 /* st $st_src, $optdisp($abase) */
2709 {
2710 { 1, 1, 1, 1 },
2711 I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st",
2712 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2713 & fmt_st_indirect_disp, { 0x92003400 },
2714 (PTR) 0,
2715 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2716 },
2717 /* st $st_src, $optdisp[$index*S$scale */
2718 {
2719 { 1, 1, 1, 1 },
2720 I960_INSN_ST_INDEX_DISP, "st-index-disp", "st",
2721 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
2722 & fmt_st_index_disp, { 0x92003800 },
2723 (PTR) 0,
2724 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2725 },
2726 /* st $st_src, $optdisp($abase)[$index*S$scale] */
2727 {
2728 { 1, 1, 1, 1 },
2729 I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st",
2730 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2731 & fmt_st_indirect_index_disp, { 0x92003c00 },
2732 (PTR) 0,
2733 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2734 },
2735 /* stob $st_src, $offset */
2736 {
2737 { 1, 1, 1, 1 },
2738 I960_INSN_STOB_OFFSET, "stob-offset", "stob",
2739 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2740 & fmt_stob_offset, { 0x82000000 },
2741 (PTR) 0,
2742 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2743 },
2744 /* stob $st_src, $offset($abase) */
2745 {
2746 { 1, 1, 1, 1 },
2747 I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob",
2748 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2749 & fmt_stob_indirect_offset, { 0x82002000 },
2750 (PTR) 0,
2751 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2752 },
2753 /* stob $st_src, ($abase) */
2754 {
2755 { 1, 1, 1, 1 },
2756 I960_INSN_STOB_INDIRECT, "stob-indirect", "stob",
2757 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2758 & fmt_stob_indirect, { 0x82001000 },
2759 (PTR) 0,
2760 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2761 },
2762 /* stob $st_src, ($abase)[$index*S$scale] */
2763 {
2764 { 1, 1, 1, 1 },
2765 I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob",
2766 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2767 & fmt_stob_indirect_index, { 0x82001c00 },
2768 (PTR) 0,
2769 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2770 },
2771 /* stob $st_src, $optdisp */
2772 {
2773 { 1, 1, 1, 1 },
2774 I960_INSN_STOB_DISP, "stob-disp", "stob",
2775 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2776 & fmt_stob_disp, { 0x82003000 },
2777 (PTR) 0,
2778 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2779 },
2780 /* stob $st_src, $optdisp($abase) */
2781 {
2782 { 1, 1, 1, 1 },
2783 I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob",
2784 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2785 & fmt_stob_indirect_disp, { 0x82003400 },
2786 (PTR) 0,
2787 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2788 },
2789 /* stob $st_src, $optdisp[$index*S$scale */
2790 {
2791 { 1, 1, 1, 1 },
2792 I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob",
2793 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
2794 & fmt_stob_index_disp, { 0x82003800 },
2795 (PTR) 0,
2796 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2797 },
2798 /* stob $st_src, $optdisp($abase)[$index*S$scale] */
2799 {
2800 { 1, 1, 1, 1 },
2801 I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob",
2802 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2803 & fmt_stob_indirect_index_disp, { 0x82003c00 },
2804 (PTR) 0,
2805 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2806 },
2807 /* stos $st_src, $offset */
2808 {
2809 { 1, 1, 1, 1 },
2810 I960_INSN_STOS_OFFSET, "stos-offset", "stos",
2811 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2812 & fmt_stos_offset, { 0x8a000000 },
2813 (PTR) 0,
2814 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2815 },
2816 /* stos $st_src, $offset($abase) */
2817 {
2818 { 1, 1, 1, 1 },
2819 I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos",
2820 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2821 & fmt_stos_indirect_offset, { 0x8a002000 },
2822 (PTR) 0,
2823 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2824 },
2825 /* stos $st_src, ($abase) */
2826 {
2827 { 1, 1, 1, 1 },
2828 I960_INSN_STOS_INDIRECT, "stos-indirect", "stos",
2829 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2830 & fmt_stos_indirect, { 0x8a001000 },
2831 (PTR) 0,
2832 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2833 },
2834 /* stos $st_src, ($abase)[$index*S$scale] */
2835 {
2836 { 1, 1, 1, 1 },
2837 I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos",
2838 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2839 & fmt_stos_indirect_index, { 0x8a001c00 },
2840 (PTR) 0,
2841 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2842 },
2843 /* stos $st_src, $optdisp */
2844 {
2845 { 1, 1, 1, 1 },
2846 I960_INSN_STOS_DISP, "stos-disp", "stos",
2847 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2848 & fmt_stos_disp, { 0x8a003000 },
2849 (PTR) 0,
2850 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2851 },
2852 /* stos $st_src, $optdisp($abase) */
2853 {
2854 { 1, 1, 1, 1 },
2855 I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos",
2856 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2857 & fmt_stos_indirect_disp, { 0x8a003400 },
2858 (PTR) 0,
2859 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2860 },
2861 /* stos $st_src, $optdisp[$index*S$scale */
2862 {
2863 { 1, 1, 1, 1 },
2864 I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos",
2865 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
2866 & fmt_stos_index_disp, { 0x8a003800 },
2867 (PTR) 0,
2868 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2869 },
2870 /* stos $st_src, $optdisp($abase)[$index*S$scale] */
2871 {
2872 { 1, 1, 1, 1 },
2873 I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos",
2874 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2875 & fmt_stos_indirect_index_disp, { 0x8a003c00 },
2876 (PTR) 0,
2877 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2878 },
2879 /* stl $st_src, $offset */
2880 {
2881 { 1, 1, 1, 1 },
2882 I960_INSN_STL_OFFSET, "stl-offset", "stl",
2883 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2884 & fmt_stl_offset, { 0x9a000000 },
2885 (PTR) 0,
2886 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2887 },
2888 /* stl $st_src, $offset($abase) */
2889 {
2890 { 1, 1, 1, 1 },
2891 I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl",
2892 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2893 & fmt_stl_indirect_offset, { 0x9a002000 },
2894 (PTR) 0,
2895 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2896 },
2897 /* stl $st_src, ($abase) */
2898 {
2899 { 1, 1, 1, 1 },
2900 I960_INSN_STL_INDIRECT, "stl-indirect", "stl",
2901 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2902 & fmt_stl_indirect, { 0x9a001000 },
2903 (PTR) 0,
2904 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2905 },
2906 /* stl $st_src, ($abase)[$index*S$scale] */
2907 {
2908 { 1, 1, 1, 1 },
2909 I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl",
2910 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2911 & fmt_stl_indirect_index, { 0x9a001c00 },
2912 (PTR) 0,
2913 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2914 },
2915 /* stl $st_src, $optdisp */
2916 {
2917 { 1, 1, 1, 1 },
2918 I960_INSN_STL_DISP, "stl-disp", "stl",
2919 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2920 & fmt_stl_disp, { 0x9a003000 },
2921 (PTR) 0,
2922 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2923 },
2924 /* stl $st_src, $optdisp($abase) */
2925 {
2926 { 1, 1, 1, 1 },
2927 I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl",
2928 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2929 & fmt_stl_indirect_disp, { 0x9a003400 },
2930 (PTR) 0,
2931 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2932 },
2933 /* stl $st_src, $optdisp[$index*S$scale */
2934 {
2935 { 1, 1, 1, 1 },
2936 I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl",
2937 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
2938 & fmt_stl_index_disp, { 0x9a003800 },
2939 (PTR) 0,
2940 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2941 },
2942 /* stl $st_src, $optdisp($abase)[$index*S$scale] */
2943 {
2944 { 1, 1, 1, 1 },
2945 I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl",
2946 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2947 & fmt_stl_indirect_index_disp, { 0x9a003c00 },
2948 (PTR) 0,
2949 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2950 },
2951 /* stt $st_src, $offset */
2952 {
2953 { 1, 1, 1, 1 },
2954 I960_INSN_STT_OFFSET, "stt-offset", "stt",
2955 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2956 & fmt_stt_offset, { 0xa2000000 },
2957 (PTR) 0,
2958 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2959 },
2960 /* stt $st_src, $offset($abase) */
2961 {
2962 { 1, 1, 1, 1 },
2963 I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt",
2964 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2965 & fmt_stt_indirect_offset, { 0xa2002000 },
2966 (PTR) 0,
2967 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2968 },
2969 /* stt $st_src, ($abase) */
2970 {
2971 { 1, 1, 1, 1 },
2972 I960_INSN_STT_INDIRECT, "stt-indirect", "stt",
2973 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2974 & fmt_stt_indirect, { 0xa2001000 },
2975 (PTR) 0,
2976 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2977 },
2978 /* stt $st_src, ($abase)[$index*S$scale] */
2979 {
2980 { 1, 1, 1, 1 },
2981 I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt",
2982 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2983 & fmt_stt_indirect_index, { 0xa2001c00 },
2984 (PTR) 0,
2985 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2986 },
2987 /* stt $st_src, $optdisp */
2988 {
2989 { 1, 1, 1, 1 },
2990 I960_INSN_STT_DISP, "stt-disp", "stt",
2991 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2992 & fmt_stt_disp, { 0xa2003000 },
2993 (PTR) 0,
2994 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2995 },
2996 /* stt $st_src, $optdisp($abase) */
2997 {
2998 { 1, 1, 1, 1 },
2999 I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt",
3000 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
3001 & fmt_stt_indirect_disp, { 0xa2003400 },
3002 (PTR) 0,
3003 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3004 },
3005 /* stt $st_src, $optdisp[$index*S$scale */
3006 {
3007 { 1, 1, 1, 1 },
3008 I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt",
3009 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
3010 & fmt_stt_index_disp, { 0xa2003800 },
3011 (PTR) 0,
3012 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3013 },
3014 /* stt $st_src, $optdisp($abase)[$index*S$scale] */
3015 {
3016 { 1, 1, 1, 1 },
3017 I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt",
3018 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
3019 & fmt_stt_indirect_index_disp, { 0xa2003c00 },
3020 (PTR) 0,
3021 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3022 },
3023 /* stq $st_src, $offset */
3024 {
3025 { 1, 1, 1, 1 },
3026 I960_INSN_STQ_OFFSET, "stq-offset", "stq",
3027 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
3028 & fmt_stq_offset, { 0xb2000000 },
3029 (PTR) 0,
3030 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3031 },
3032 /* stq $st_src, $offset($abase) */
3033 {
3034 { 1, 1, 1, 1 },
3035 I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq",
3036 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
3037 & fmt_stq_indirect_offset, { 0xb2002000 },
3038 (PTR) 0,
3039 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3040 },
3041 /* stq $st_src, ($abase) */
3042 {
3043 { 1, 1, 1, 1 },
3044 I960_INSN_STQ_INDIRECT, "stq-indirect", "stq",
3045 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
3046 & fmt_stq_indirect, { 0xb2001000 },
3047 (PTR) 0,
3048 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3049 },
3050 /* stq $st_src, ($abase)[$index*S$scale] */
3051 {
3052 { 1, 1, 1, 1 },
3053 I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq",
3054 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
3055 & fmt_stq_indirect_index, { 0xb2001c00 },
3056 (PTR) 0,
3057 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3058 },
3059 /* stq $st_src, $optdisp */
3060 {
3061 { 1, 1, 1, 1 },
3062 I960_INSN_STQ_DISP, "stq-disp", "stq",
3063 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
3064 & fmt_stq_disp, { 0xb2003000 },
3065 (PTR) 0,
3066 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3067 },
3068 /* stq $st_src, $optdisp($abase) */
3069 {
3070 { 1, 1, 1, 1 },
3071 I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq",
3072 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
3073 & fmt_stq_indirect_disp, { 0xb2003400 },
3074 (PTR) 0,
3075 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3076 },
3077 /* stq $st_src, $optdisp[$index*S$scale */
3078 {
3079 { 1, 1, 1, 1 },
3080 I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq",
3081 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
3082 & fmt_stq_index_disp, { 0xb2003800 },
3083 (PTR) 0,
3084 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3085 },
3086 /* stq $st_src, $optdisp($abase)[$index*S$scale] */
3087 {
3088 { 1, 1, 1, 1 },
3089 I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq",
3090 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
3091 & fmt_stq_indirect_index_disp, { 0xb2003c00 },
3092 (PTR) 0,
3093 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3094 },
3095 /* cmpobe $br_src1, $br_src2, $br_disp */
3096 {
3097 { 1, 1, 1, 1 },
3098 I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe",
3099 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3100 & fmt_cmpobe_reg, { 0x32000000 },
3101 (PTR) 0,
3102 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3103 },
3104 /* cmpobe $br_lit1, $br_src2, $br_disp */
3105 {
3106 { 1, 1, 1, 1 },
3107 I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe",
3108 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3109 & fmt_cmpobe_lit, { 0x32002000 },
3110 (PTR) 0,
3111 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3112 },
3113 /* cmpobne $br_src1, $br_src2, $br_disp */
3114 {
3115 { 1, 1, 1, 1 },
3116 I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne",
3117 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3118 & fmt_cmpobe_reg, { 0x35000000 },
3119 (PTR) 0,
3120 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3121 },
3122 /* cmpobne $br_lit1, $br_src2, $br_disp */
3123 {
3124 { 1, 1, 1, 1 },
3125 I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne",
3126 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3127 & fmt_cmpobe_lit, { 0x35002000 },
3128 (PTR) 0,
3129 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3130 },
3131 /* cmpobl $br_src1, $br_src2, $br_disp */
3132 {
3133 { 1, 1, 1, 1 },
3134 I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl",
3135 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3136 & fmt_cmpobl_reg, { 0x34000000 },
3137 (PTR) 0,
3138 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3139 },
3140 /* cmpobl $br_lit1, $br_src2, $br_disp */
3141 {
3142 { 1, 1, 1, 1 },
3143 I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl",
3144 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3145 & fmt_cmpobl_lit, { 0x34002000 },
3146 (PTR) 0,
3147 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3148 },
3149 /* cmpoble $br_src1, $br_src2, $br_disp */
3150 {
3151 { 1, 1, 1, 1 },
3152 I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble",
3153 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3154 & fmt_cmpobl_reg, { 0x36000000 },
3155 (PTR) 0,
3156 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3157 },
3158 /* cmpoble $br_lit1, $br_src2, $br_disp */
3159 {
3160 { 1, 1, 1, 1 },
3161 I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble",
3162 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3163 & fmt_cmpobl_lit, { 0x36002000 },
3164 (PTR) 0,
3165 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3166 },
3167 /* cmpobg $br_src1, $br_src2, $br_disp */
3168 {
3169 { 1, 1, 1, 1 },
3170 I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg",
3171 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3172 & fmt_cmpobl_reg, { 0x31000000 },
3173 (PTR) 0,
3174 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3175 },
3176 /* cmpobg $br_lit1, $br_src2, $br_disp */
3177 {
3178 { 1, 1, 1, 1 },
3179 I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg",
3180 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3181 & fmt_cmpobl_lit, { 0x31002000 },
3182 (PTR) 0,
3183 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3184 },
3185 /* cmpobge $br_src1, $br_src2, $br_disp */
3186 {
3187 { 1, 1, 1, 1 },
3188 I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge",
3189 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3190 & fmt_cmpobl_reg, { 0x33000000 },
3191 (PTR) 0,
3192 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3193 },
3194 /* cmpobge $br_lit1, $br_src2, $br_disp */
3195 {
3196 { 1, 1, 1, 1 },
3197 I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge",
3198 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3199 & fmt_cmpobl_lit, { 0x33002000 },
3200 (PTR) 0,
3201 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3202 },
3203 /* cmpibe $br_src1, $br_src2, $br_disp */
3204 {
3205 { 1, 1, 1, 1 },
3206 I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe",
3207 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3208 & fmt_cmpobe_reg, { 0x3a000000 },
3209 (PTR) 0,
3210 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3211 },
3212 /* cmpibe $br_lit1, $br_src2, $br_disp */
3213 {
3214 { 1, 1, 1, 1 },
3215 I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe",
3216 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3217 & fmt_cmpobe_lit, { 0x3a002000 },
3218 (PTR) 0,
3219 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3220 },
3221 /* cmpibne $br_src1, $br_src2, $br_disp */
3222 {
3223 { 1, 1, 1, 1 },
3224 I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne",
3225 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3226 & fmt_cmpobe_reg, { 0x3d000000 },
3227 (PTR) 0,
3228 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3229 },
3230 /* cmpibne $br_lit1, $br_src2, $br_disp */
3231 {
3232 { 1, 1, 1, 1 },
3233 I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne",
3234 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3235 & fmt_cmpobe_lit, { 0x3d002000 },
3236 (PTR) 0,
3237 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3238 },
3239 /* cmpibl $br_src1, $br_src2, $br_disp */
3240 {
3241 { 1, 1, 1, 1 },
3242 I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl",
3243 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3244 & fmt_cmpobe_reg, { 0x3c000000 },
3245 (PTR) 0,
3246 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3247 },
3248 /* cmpibl $br_lit1, $br_src2, $br_disp */
3249 {
3250 { 1, 1, 1, 1 },
3251 I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl",
3252 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3253 & fmt_cmpobe_lit, { 0x3c002000 },
3254 (PTR) 0,
3255 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3256 },
3257 /* cmpible $br_src1, $br_src2, $br_disp */
3258 {
3259 { 1, 1, 1, 1 },
3260 I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible",
3261 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3262 & fmt_cmpobe_reg, { 0x3e000000 },
3263 (PTR) 0,
3264 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3265 },
3266 /* cmpible $br_lit1, $br_src2, $br_disp */
3267 {
3268 { 1, 1, 1, 1 },
3269 I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible",
3270 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3271 & fmt_cmpobe_lit, { 0x3e002000 },
3272 (PTR) 0,
3273 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3274 },
3275 /* cmpibg $br_src1, $br_src2, $br_disp */
3276 {
3277 { 1, 1, 1, 1 },
3278 I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg",
3279 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3280 & fmt_cmpobe_reg, { 0x39000000 },
3281 (PTR) 0,
3282 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3283 },
3284 /* cmpibg $br_lit1, $br_src2, $br_disp */
3285 {
3286 { 1, 1, 1, 1 },
3287 I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg",
3288 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3289 & fmt_cmpobe_lit, { 0x39002000 },
3290 (PTR) 0,
3291 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3292 },
3293 /* cmpibge $br_src1, $br_src2, $br_disp */
3294 {
3295 { 1, 1, 1, 1 },
3296 I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge",
3297 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3298 & fmt_cmpobe_reg, { 0x3b000000 },
3299 (PTR) 0,
3300 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3301 },
3302 /* cmpibge $br_lit1, $br_src2, $br_disp */
3303 {
3304 { 1, 1, 1, 1 },
3305 I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge",
3306 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3307 & fmt_cmpobe_lit, { 0x3b002000 },
3308 (PTR) 0,
3309 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3310 },
3311 /* bbc $br_src1, $br_src2, $br_disp */
3312 {
3313 { 1, 1, 1, 1 },
3314 I960_INSN_BBC_REG, "bbc-reg", "bbc",
3315 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3316 & fmt_cmpobe_reg, { 0x30000000 },
3317 (PTR) 0,
3318 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3319 },
3320 /* bbc $br_lit1, $br_src2, $br_disp */
3321 {
3322 { 1, 1, 1, 1 },
3323 I960_INSN_BBC_LIT, "bbc-lit", "bbc",
3324 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3325 & fmt_bbc_lit, { 0x30002000 },
3326 (PTR) 0,
3327 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3328 },
3329 /* bbs $br_src1, $br_src2, $br_disp */
3330 {
3331 { 1, 1, 1, 1 },
3332 I960_INSN_BBS_REG, "bbs-reg", "bbs",
3333 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3334 & fmt_cmpobe_reg, { 0x37000000 },
3335 (PTR) 0,
3336 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3337 },
3338 /* bbs $br_lit1, $br_src2, $br_disp */
3339 {
3340 { 1, 1, 1, 1 },
3341 I960_INSN_BBS_LIT, "bbs-lit", "bbs",
3342 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
3343 & fmt_bbc_lit, { 0x37002000 },
3344 (PTR) 0,
3345 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3346 },
3347 /* cmpi $src1, $src2 */
3348 {
3349 { 1, 1, 1, 1 },
3350 I960_INSN_CMPI, "cmpi", "cmpi",
3351 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
3352 & fmt_cmpi, { 0x5a002080 },
3353 (PTR) 0,
3354 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3355 },
3356 /* cmpi $lit1, $src2 */
3357 {
3358 { 1, 1, 1, 1 },
3359 I960_INSN_CMPI1, "cmpi1", "cmpi",
3360 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
3361 & fmt_cmpi1, { 0x5a002880 },
3362 (PTR) 0,
3363 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3364 },
3365 /* cmpi $src1, $lit2 */
3366 {
3367 { 1, 1, 1, 1 },
3368 I960_INSN_CMPI2, "cmpi2", "cmpi",
3369 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
3370 & fmt_cmpi2, { 0x5a003080 },
3371 (PTR) 0,
3372 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3373 },
3374 /* cmpi $lit1, $lit2 */
3375 {
3376 { 1, 1, 1, 1 },
3377 I960_INSN_CMPI3, "cmpi3", "cmpi",
3378 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
3379 & fmt_cmpi3, { 0x5a003880 },
3380 (PTR) 0,
3381 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3382 },
3383 /* cmpo $src1, $src2 */
3384 {
3385 { 1, 1, 1, 1 },
3386 I960_INSN_CMPO, "cmpo", "cmpo",
3387 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
3388 & fmt_cmpi, { 0x5a002000 },
3389 (PTR) 0,
3390 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3391 },
3392 /* cmpo $lit1, $src2 */
3393 {
3394 { 1, 1, 1, 1 },
3395 I960_INSN_CMPO1, "cmpo1", "cmpo",
3396 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
3397 & fmt_cmpi1, { 0x5a002800 },
3398 (PTR) 0,
3399 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3400 },
3401 /* cmpo $src1, $lit2 */
3402 {
3403 { 1, 1, 1, 1 },
3404 I960_INSN_CMPO2, "cmpo2", "cmpo",
3405 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
3406 & fmt_cmpi2, { 0x5a003000 },
3407 (PTR) 0,
3408 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3409 },
3410 /* cmpo $lit1, $lit2 */
3411 {
3412 { 1, 1, 1, 1 },
3413 I960_INSN_CMPO3, "cmpo3", "cmpo",
3414 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
3415 & fmt_cmpi3, { 0x5a003800 },
3416 (PTR) 0,
3417 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3418 },
3419 /* testno $br_src1 */
3420 {
3421 { 1, 1, 1, 1 },
3422 I960_INSN_TESTNO_REG, "testno-reg", "testno",
3423 { { MNEM, ' ', OP (BR_SRC1), 0 } },
3424 & fmt_testno_reg, { 0x20000000 },
3425 (PTR) 0,
3426 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3427 },
3428 /* testg $br_src1 */
3429 {
3430 { 1, 1, 1, 1 },
3431 I960_INSN_TESTG_REG, "testg-reg", "testg",
3432 { { MNEM, ' ', OP (BR_SRC1), 0 } },
3433 & fmt_testno_reg, { 0x21000000 },
3434 (PTR) 0,
3435 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3436 },
3437 /* teste $br_src1 */
3438 {
3439 { 1, 1, 1, 1 },
3440 I960_INSN_TESTE_REG, "teste-reg", "teste",
3441 { { MNEM, ' ', OP (BR_SRC1), 0 } },
3442 & fmt_testno_reg, { 0x22000000 },
3443 (PTR) 0,
3444 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3445 },
3446 /* testge $br_src1 */
3447 {
3448 { 1, 1, 1, 1 },
3449 I960_INSN_TESTGE_REG, "testge-reg", "testge",
3450 { { MNEM, ' ', OP (BR_SRC1), 0 } },
3451 & fmt_testno_reg, { 0x23000000 },
3452 (PTR) 0,
3453 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3454 },
3455 /* testl $br_src1 */
3456 {
3457 { 1, 1, 1, 1 },
3458 I960_INSN_TESTL_REG, "testl-reg", "testl",
3459 { { MNEM, ' ', OP (BR_SRC1), 0 } },
3460 & fmt_testno_reg, { 0x24000000 },
3461 (PTR) 0,
3462 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3463 },
3464 /* testne $br_src1 */
3465 {
3466 { 1, 1, 1, 1 },
3467 I960_INSN_TESTNE_REG, "testne-reg", "testne",
3468 { { MNEM, ' ', OP (BR_SRC1), 0 } },
3469 & fmt_testno_reg, { 0x25000000 },
3470 (PTR) 0,
3471 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3472 },
3473 /* testle $br_src1 */
3474 {
3475 { 1, 1, 1, 1 },
3476 I960_INSN_TESTLE_REG, "testle-reg", "testle",
3477 { { MNEM, ' ', OP (BR_SRC1), 0 } },
3478 & fmt_testno_reg, { 0x26000000 },
3479 (PTR) 0,
3480 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3481 },
3482 /* testo $br_src1 */
3483 {
3484 { 1, 1, 1, 1 },
3485 I960_INSN_TESTO_REG, "testo-reg", "testo",
3486 { { MNEM, ' ', OP (BR_SRC1), 0 } },
3487 & fmt_testno_reg, { 0x27000000 },
3488 (PTR) 0,
3489 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3490 },
3491 /* bno $ctrl_disp */
3492 {
3493 { 1, 1, 1, 1 },
3494 I960_INSN_BNO, "bno", "bno",
3495 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
3496 & fmt_bno, { 0x10000000 },
3497 (PTR) 0,
3498 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3499 },
3500 /* bg $ctrl_disp */
3501 {
3502 { 1, 1, 1, 1 },
3503 I960_INSN_BG, "bg", "bg",
3504 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
3505 & fmt_bno, { 0x11000000 },
3506 (PTR) 0,
3507 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3508 },
3509 /* be $ctrl_disp */
3510 {
3511 { 1, 1, 1, 1 },
3512 I960_INSN_BE, "be", "be",
3513 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
3514 & fmt_bno, { 0x12000000 },
3515 (PTR) 0,
3516 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3517 },
3518 /* bge $ctrl_disp */
3519 {
3520 { 1, 1, 1, 1 },
3521 I960_INSN_BGE, "bge", "bge",
3522 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
3523 & fmt_bno, { 0x13000000 },
3524 (PTR) 0,
3525 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3526 },
3527 /* bl $ctrl_disp */
3528 {
3529 { 1, 1, 1, 1 },
3530 I960_INSN_BL, "bl", "bl",
3531 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
3532 & fmt_bno, { 0x14000000 },
3533 (PTR) 0,
3534 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3535 },
3536 /* bne $ctrl_disp */
3537 {
3538 { 1, 1, 1, 1 },
3539 I960_INSN_BNE, "bne", "bne",
3540 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
3541 & fmt_bno, { 0x15000000 },
3542 (PTR) 0,
3543 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3544 },
3545 /* ble $ctrl_disp */
3546 {
3547 { 1, 1, 1, 1 },
3548 I960_INSN_BLE, "ble", "ble",
3549 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
3550 & fmt_bno, { 0x16000000 },
3551 (PTR) 0,
3552 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3553 },
3554 /* bo $ctrl_disp */
3555 {
3556 { 1, 1, 1, 1 },
3557 I960_INSN_BO, "bo", "bo",
3558 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
3559 & fmt_bno, { 0x17000000 },
3560 (PTR) 0,
3561 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
3562 },
3563 /* b $ctrl_disp */
3564 {
3565 { 1, 1, 1, 1 },
3566 I960_INSN_B, "b", "b",
3567 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
3568 & fmt_b, { 0x8000000 },
3569 (PTR) 0,
3570 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3571 },
3572 /* bx $offset($abase) */
3573 {
3574 { 1, 1, 1, 1 },
3575 I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx",
3576 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
3577 & fmt_bx_indirect_offset, { 0x84002000 },
3578 (PTR) 0,
3579 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3580 },
3581 /* bx ($abase) */
3582 {
3583 { 1, 1, 1, 1 },
3584 I960_INSN_BX_INDIRECT, "bx-indirect", "bx",
3585 { { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
3586 & fmt_bx_indirect, { 0x84001000 },
3587 (PTR) 0,
3588 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3589 },
3590 /* bx ($abase)[$index*S$scale] */
3591 {
3592 { 1, 1, 1, 1 },
3593 I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx",
3594 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
3595 & fmt_bx_indirect_index, { 0x84001c00 },
3596 (PTR) 0,
3597 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3598 },
3599 /* bx $optdisp */
3600 {
3601 { 1, 1, 1, 1 },
3602 I960_INSN_BX_DISP, "bx-disp", "bx",
3603 { { MNEM, ' ', OP (OPTDISP), 0 } },
3604 & fmt_bx_disp, { 0x84003000 },
3605 (PTR) 0,
3606 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3607 },
3608 /* bx $optdisp($abase) */
3609 {
3610 { 1, 1, 1, 1 },
3611 I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx",
3612 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
3613 & fmt_bx_indirect_disp, { 0x84003400 },
3614 (PTR) 0,
3615 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3616 },
3617 /* callx $optdisp */
3618 {
3619 { 1, 1, 1, 1 },
3620 I960_INSN_CALLX_DISP, "callx-disp", "callx",
3621 { { MNEM, ' ', OP (OPTDISP), 0 } },
3622 & fmt_callx_disp, { 0x86003000 },
3623 (PTR) 0,
3624 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3625 },
3626 /* callx ($abase) */
3627 {
3628 { 1, 1, 1, 1 },
3629 I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx",
3630 { { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
3631 & fmt_callx_indirect, { 0x86001000 },
3632 (PTR) 0,
3633 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3634 },
3635 /* callx $offset($abase) */
3636 {
3637 { 1, 1, 1, 1 },
3638 I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx",
3639 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
3640 & fmt_callx_indirect_offset, { 0x86002000 },
3641 (PTR) 0,
3642 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3643 },
3644 /* ret */
3645 {
3646 { 1, 1, 1, 1 },
3647 I960_INSN_RET, "ret", "ret",
3648 { { MNEM, 0 } },
3649 & fmt_ret, { 0xa000000 },
3650 (PTR) 0,
3651 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3652 },
3653 /* calls $src1 */
3654 {
3655 { 1, 1, 1, 1 },
3656 I960_INSN_CALLS, "calls", "calls",
3657 { { MNEM, ' ', OP (SRC1), 0 } },
3658 & fmt_calls, { 0x66003000 },
3659 (PTR) 0,
3660 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3661 },
3662 /* fmark */
3663 {
3664 { 1, 1, 1, 1 },
3665 I960_INSN_FMARK, "fmark", "fmark",
3666 { { MNEM, 0 } },
3667 & fmt_fmark, { 0x66003e00 },
3668 (PTR) 0,
3669 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3670 },
3671 /* flushreg */
3672 {
3673 { 1, 1, 1, 1 },
3674 I960_INSN_FLUSHREG, "flushreg", "flushreg",
3675 { { MNEM, 0 } },
3676 & fmt_flushreg, { 0x66003e80 },
3677 (PTR) 0,
3678 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3679 },
3680 };
3681
3682 #undef A
3683 #undef MNEM
3684 #undef OP
3685
3686 static const CGEN_INSN_TABLE insn_table =
3687 {
3688 & i960_cgen_insn_table_entries[0],
3689 sizeof (CGEN_INSN),
3690 MAX_INSNS,
3691 NULL
3692 };
3693
3694 /* Formats for ALIAS macro-insns. */
3695
3696 #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
3697
3698 #undef F
3699
3700 /* Each non-simple macro entry points to an array of expansion possibilities. */
3701
3702 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
3703 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
3704 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
3705
3706 /* The macro instruction table. */
3707
3708 static const CGEN_INSN macro_insn_table_entries[] =
3709 {
3710 };
3711
3712 #undef A
3713 #undef MNEM
3714 #undef OP
3715
3716 static const CGEN_INSN_TABLE macro_insn_table =
3717 {
3718 & macro_insn_table_entries[0],
3719 sizeof (CGEN_INSN),
3720 (sizeof (macro_insn_table_entries) /
3721 sizeof (macro_insn_table_entries[0])),
3722 NULL
3723 };
3724
3725 static void
3726 init_tables ()
3727 {
3728 }
3729
3730 /* Return non-zero if INSN is to be added to the hash table.
3731 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3732
3733 static int
3734 asm_hash_insn_p (insn)
3735 const CGEN_INSN * insn;
3736 {
3737 return CGEN_ASM_HASH_P (insn);
3738 }
3739
3740 static int
3741 dis_hash_insn_p (insn)
3742 const CGEN_INSN * insn;
3743 {
3744 /* If building the hash table and the NO-DIS attribute is present,
3745 ignore. */
3746 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
3747 return 0;
3748 return CGEN_DIS_HASH_P (insn);
3749 }
3750
3751 /* The result is the hash value of the insn.
3752 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
3753
3754 static unsigned int
3755 asm_hash_insn (mnem)
3756 const char * mnem;
3757 {
3758 return CGEN_ASM_HASH (mnem);
3759 }
3760
3761 /* BUF is a pointer to the insn's bytes in target order.
3762 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3763 host order. */
3764
3765 static unsigned int
3766 dis_hash_insn (buf, value)
3767 const char * buf;
3768 CGEN_INSN_INT value;
3769 {
3770 return CGEN_DIS_HASH (buf, value);
3771 }
3772
3773 /* Initialize an opcode table and return a descriptor.
3774 It's much like opening a file, and must be the first function called. */
3775
3776 CGEN_OPCODE_DESC
3777 i960_cgen_opcode_open (mach, endian)
3778 int mach;
3779 enum cgen_endian endian;
3780 {
3781 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
3782 static int init_p;
3783
3784 if (! init_p)
3785 {
3786 init_tables ();
3787 init_p = 1;
3788 }
3789
3790 memset (table, 0, sizeof (*table));
3791
3792 CGEN_OPCODE_MACH (table) = mach;
3793 CGEN_OPCODE_ENDIAN (table) = endian;
3794 /* FIXME: for the sparc case we can determine insn-endianness statically.
3795 The worry here is where both data and insn endian can be independently
3796 chosen, in which case this function will need another argument.
3797 Actually, will want to allow for more arguments in the future anyway. */
3798 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
3799
3800 CGEN_OPCODE_HW_LIST (table) = & i960_cgen_hw_entries[0];
3801
3802 CGEN_OPCODE_IFLD_TABLE (table) = & i960_cgen_ifld_table[0];
3803
3804 CGEN_OPCODE_OPERAND_TABLE (table) = & i960_cgen_operand_table[0];
3805
3806 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
3807
3808 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
3809
3810 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
3811 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
3812 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
3813
3814 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
3815 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
3816 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
3817
3818 return (CGEN_OPCODE_DESC) table;
3819 }
3820
3821 /* Close an opcode table. */
3822
3823 void
3824 i960_cgen_opcode_close (desc)
3825 CGEN_OPCODE_DESC desc;
3826 {
3827 free (desc);
3828 }
3829
3830 /* Getting values from cgen_fields is handled by a collection of functions.
3831 They are distinguished by the type of the VALUE argument they return.
3832 TODO: floating point, inlining support, remove cases where result type
3833 not appropriate. */
3834
3835 int
3836 i960_cgen_get_int_operand (opindex, fields)
3837 int opindex;
3838 const CGEN_FIELDS * fields;
3839 {
3840 int value;
3841
3842 switch (opindex)
3843 {
3844 case I960_OPERAND_SRC1 :
3845 value = fields->f_src1;
3846 break;
3847 case I960_OPERAND_SRC2 :
3848 value = fields->f_src2;
3849 break;
3850 case I960_OPERAND_DST :
3851 value = fields->f_srcdst;
3852 break;
3853 case I960_OPERAND_LIT1 :
3854 value = fields->f_src1;
3855 break;
3856 case I960_OPERAND_LIT2 :
3857 value = fields->f_src2;
3858 break;
3859 case I960_OPERAND_ST_SRC :
3860 value = fields->f_srcdst;
3861 break;
3862 case I960_OPERAND_ABASE :
3863 value = fields->f_abase;
3864 break;
3865 case I960_OPERAND_OFFSET :
3866 value = fields->f_offset;
3867 break;
3868 case I960_OPERAND_SCALE :
3869 value = fields->f_scale;
3870 break;
3871 case I960_OPERAND_INDEX :
3872 value = fields->f_index;
3873 break;
3874 case I960_OPERAND_OPTDISP :
3875 value = fields->f_optdisp;
3876 break;
3877 case I960_OPERAND_BR_SRC1 :
3878 value = fields->f_br_src1;
3879 break;
3880 case I960_OPERAND_BR_SRC2 :
3881 value = fields->f_br_src2;
3882 break;
3883 case I960_OPERAND_BR_DISP :
3884 value = fields->f_br_disp;
3885 break;
3886 case I960_OPERAND_BR_LIT1 :
3887 value = fields->f_br_src1;
3888 break;
3889 case I960_OPERAND_CTRL_DISP :
3890 value = fields->f_ctrl_disp;
3891 break;
3892
3893 default :
3894 /* xgettext:c-format */
3895 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3896 opindex);
3897 abort ();
3898 }
3899
3900 return value;
3901 }
3902
3903 bfd_vma
3904 i960_cgen_get_vma_operand (opindex, fields)
3905 int opindex;
3906 const CGEN_FIELDS * fields;
3907 {
3908 bfd_vma value;
3909
3910 switch (opindex)
3911 {
3912 case I960_OPERAND_SRC1 :
3913 value = fields->f_src1;
3914 break;
3915 case I960_OPERAND_SRC2 :
3916 value = fields->f_src2;
3917 break;
3918 case I960_OPERAND_DST :
3919 value = fields->f_srcdst;
3920 break;
3921 case I960_OPERAND_LIT1 :
3922 value = fields->f_src1;
3923 break;
3924 case I960_OPERAND_LIT2 :
3925 value = fields->f_src2;
3926 break;
3927 case I960_OPERAND_ST_SRC :
3928 value = fields->f_srcdst;
3929 break;
3930 case I960_OPERAND_ABASE :
3931 value = fields->f_abase;
3932 break;
3933 case I960_OPERAND_OFFSET :
3934 value = fields->f_offset;
3935 break;
3936 case I960_OPERAND_SCALE :
3937 value = fields->f_scale;
3938 break;
3939 case I960_OPERAND_INDEX :
3940 value = fields->f_index;
3941 break;
3942 case I960_OPERAND_OPTDISP :
3943 value = fields->f_optdisp;
3944 break;
3945 case I960_OPERAND_BR_SRC1 :
3946 value = fields->f_br_src1;
3947 break;
3948 case I960_OPERAND_BR_SRC2 :
3949 value = fields->f_br_src2;
3950 break;
3951 case I960_OPERAND_BR_DISP :
3952 value = fields->f_br_disp;
3953 break;
3954 case I960_OPERAND_BR_LIT1 :
3955 value = fields->f_br_src1;
3956 break;
3957 case I960_OPERAND_CTRL_DISP :
3958 value = fields->f_ctrl_disp;
3959 break;
3960
3961 default :
3962 /* xgettext:c-format */
3963 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3964 opindex);
3965 abort ();
3966 }
3967
3968 return value;
3969 }
3970
3971 /* Stuffing values in cgen_fields is handled by a collection of functions.
3972 They are distinguished by the type of the VALUE argument they accept.
3973 TODO: floating point, inlining support, remove cases where argument type
3974 not appropriate. */
3975
3976 void
3977 i960_cgen_set_int_operand (opindex, fields, value)
3978 int opindex;
3979 CGEN_FIELDS * fields;
3980 int value;
3981 {
3982 switch (opindex)
3983 {
3984 case I960_OPERAND_SRC1 :
3985 fields->f_src1 = value;
3986 break;
3987 case I960_OPERAND_SRC2 :
3988 fields->f_src2 = value;
3989 break;
3990 case I960_OPERAND_DST :
3991 fields->f_srcdst = value;
3992 break;
3993 case I960_OPERAND_LIT1 :
3994 fields->f_src1 = value;
3995 break;
3996 case I960_OPERAND_LIT2 :
3997 fields->f_src2 = value;
3998 break;
3999 case I960_OPERAND_ST_SRC :
4000 fields->f_srcdst = value;
4001 break;
4002 case I960_OPERAND_ABASE :
4003 fields->f_abase = value;
4004 break;
4005 case I960_OPERAND_OFFSET :
4006 fields->f_offset = value;
4007 break;
4008 case I960_OPERAND_SCALE :
4009 fields->f_scale = value;
4010 break;
4011 case I960_OPERAND_INDEX :
4012 fields->f_index = value;
4013 break;
4014 case I960_OPERAND_OPTDISP :
4015 fields->f_optdisp = value;
4016 break;
4017 case I960_OPERAND_BR_SRC1 :
4018 fields->f_br_src1 = value;
4019 break;
4020 case I960_OPERAND_BR_SRC2 :
4021 fields->f_br_src2 = value;
4022 break;
4023 case I960_OPERAND_BR_DISP :
4024 fields->f_br_disp = value;
4025 break;
4026 case I960_OPERAND_BR_LIT1 :
4027 fields->f_br_src1 = value;
4028 break;
4029 case I960_OPERAND_CTRL_DISP :
4030 fields->f_ctrl_disp = value;
4031 break;
4032
4033 default :
4034 /* xgettext:c-format */
4035 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
4036 opindex);
4037 abort ();
4038 }
4039 }
4040
4041 void
4042 i960_cgen_set_vma_operand (opindex, fields, value)
4043 int opindex;
4044 CGEN_FIELDS * fields;
4045 bfd_vma value;
4046 {
4047 switch (opindex)
4048 {
4049 case I960_OPERAND_SRC1 :
4050 fields->f_src1 = value;
4051 break;
4052 case I960_OPERAND_SRC2 :
4053 fields->f_src2 = value;
4054 break;
4055 case I960_OPERAND_DST :
4056 fields->f_srcdst = value;
4057 break;
4058 case I960_OPERAND_LIT1 :
4059 fields->f_src1 = value;
4060 break;
4061 case I960_OPERAND_LIT2 :
4062 fields->f_src2 = value;
4063 break;
4064 case I960_OPERAND_ST_SRC :
4065 fields->f_srcdst = value;
4066 break;
4067 case I960_OPERAND_ABASE :
4068 fields->f_abase = value;
4069 break;
4070 case I960_OPERAND_OFFSET :
4071 fields->f_offset = value;
4072 break;
4073 case I960_OPERAND_SCALE :
4074 fields->f_scale = value;
4075 break;
4076 case I960_OPERAND_INDEX :
4077 fields->f_index = value;
4078 break;
4079 case I960_OPERAND_OPTDISP :
4080 fields->f_optdisp = value;
4081 break;
4082 case I960_OPERAND_BR_SRC1 :
4083 fields->f_br_src1 = value;
4084 break;
4085 case I960_OPERAND_BR_SRC2 :
4086 fields->f_br_src2 = value;
4087 break;
4088 case I960_OPERAND_BR_DISP :
4089 fields->f_br_disp = value;
4090 break;
4091 case I960_OPERAND_BR_LIT1 :
4092 fields->f_br_src1 = value;
4093 break;
4094 case I960_OPERAND_CTRL_DISP :
4095 fields->f_ctrl_disp = value;
4096 break;
4097
4098 default :
4099 /* xgettext:c-format */
4100 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
4101 opindex);
4102 abort ();
4103 }
4104 }
4105