opcodes/m32r-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 This file is used to generate m32r-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software
  22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "m32r-opc.h"
  31
  32 /* Look up instruction INSN_VALUE and extract its fields.
  33    If non-null INSN is the insn table entry.
  34    Otherwise INSN_VALUE is examined to compute it.
  35    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  36    ALIAS_P is non-zero if alias insns are to be included in the search.
  37    The result a pointer to the insn table entry, or NULL if the instruction
  38    wasn't recognized.  */
  39
  40 const CGEN_INSN *
  41 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
  42      const CGEN_INSN *insn;
  43      cgen_insn_t insn_value;
  44      int length;
  45      CGEN_FIELDS *fields;
  46 {
  47   char buf[16];
  48
  49   if (!insn)
  50     {
  51       const CGEN_INSN_LIST *insn_list;
  52
  53 #ifdef CGEN_INT_INSN
  54       switch (length)
  55         {
  56         case 8:
  57           buf[0] = insn_value;
  58           break;
  59         case 16:
  60           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  61             bfd_putb16 (insn_value, buf);
  62           else
  63             bfd_putl16 (insn_value, buf);
  64           break;
  65         case 32:
  66           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  67             bfd_putb32 (insn_value, buf);
  68           else
  69             bfd_putl32 (insn_value, buf);
  70           break;
  71         default:
  72           abort ();
  73         }
  74 #else
  75       abort (); /* FIXME: unfinished */
  76 #endif
  77
  78       /* The instructions are stored in hash lists.
  79          Pick the first one and keep trying until we find the right one.  */
  80
  81       insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
  82       while (insn_list != NULL)
  83         {
  84           insn = insn_list->insn;
  85
  86           if (alias_p
  87               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  88             {
  89               /* Basic bit mask must be correct.  */
  90               /* ??? May wish to allow target to defer this check until the
  91                  extract handler.  */
  92               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
  93                 {
  94                   length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
  95                   if (length > 0)
  96                     return insn;
  97                 }
  98             }
  99
 100           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 101         }
 102     }
 103   else
 104     {
 105       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 106       if (! alias_p
 107           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 108         abort ();
 109
 110       length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
 111       if (length > 0)
 112         return insn;
 113     }
 114
 115   return NULL;
 116 }
 117
 118 /* Fill in the operand instances used by insn INSN_VALUE.
 119    If non-null INS is the insn table entry.
 120    Otherwise INSN_VALUE is examined to compute it.
 121    LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
 122    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 123    in.
 124    The result a pointer to the insn table entry, or NULL if the instruction
 125    wasn't recognized.  */
 126
 127 const CGEN_INSN *
 128 m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
 129      const CGEN_INSN *insn;
 130      cgen_insn_t insn_value;
 131      int length;
 132      int *indices;
 133 {
 134   CGEN_FIELDS fields;
 135   const CGEN_OPERAND_INSTANCE *opinst;
 136   int i;
 137
 138   /* FIXME: ALIAS insns are in transition from being record in the insn table
 139      to being recorded separately as macros.  They don't have semantic code
 140      so they can't be used here.  Thus we currently always ignore the INSN
 141      argument.  */
 142   insn = m32r_cgen_lookup_insn (NULL, insn_value, length, &fields, 0);
 143   if (! insn)
 144     return NULL;
 145
 146   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 147        opinst != NULL
 148          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 149        ++i, ++opinst)
 150     {
 151       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 152       if (op == NULL)
 153         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 154       else
 155         indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
 156     }
 157
 158   return insn;
 159 }
 160 /* Attributes.  */
 161
 162 static const CGEN_ATTR_ENTRY MACH_attr[] =
 163 {
 164   { "m32r", MACH_M32R },
 165 /* start-sanitize-m32rx */
 166   { "m32rx", MACH_M32RX },
 167 /* end-sanitize-m32rx */
 168   { "max", MACH_MAX },
 169   { 0, 0 }
 170 };
 171
 172 /* start-sanitize-m32rx */
 173 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 174 {
 175   { "NONE", PIPE_NONE },
 176   { "O", PIPE_O },
 177   { "S", PIPE_S },
 178   { "OS", PIPE_OS },
 179   { 0, 0 }
 180 };
 181
 182 /* end-sanitize-m32rx */
 183 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 184 {
 185   { "ABS-ADDR", NULL },
 186   { "FAKE", NULL },
 187   { "NEGATIVE", NULL },
 188   { "PC", NULL },
 189   { "PCREL-ADDR", NULL },
 190   { "RELAX", NULL },
 191   { "RELOC", NULL },
 192   { "SIGN-OPT", NULL },
 193   { "UNSIGNED", NULL },
 194   { 0, 0 }
 195 };
 196
 197 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 198 {
 199   { "MACH", & MACH_attr[0] },
 200 /* start-sanitize-m32rx */
 201   { "PIPE", & PIPE_attr[0] },
 202 /* end-sanitize-m32rx */
 203   { "ALIAS", NULL },
 204   { "COND-CTI", NULL },
 205   { "FILL-SLOT", NULL },
 206   { "PARALLEL", NULL },
 207   { "RELAX", NULL },
 208   { "RELAXABLE", NULL },
 209   { "UNCOND-CTI", NULL },
 210   { 0, 0 }
 211 };
 212
 213 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
 214 {
 215   { "fp", 13 },
 216   { "lr", 14 },
 217   { "sp", 15 },
 218   { "r0", 0 },
 219   { "r1", 1 },
 220   { "r2", 2 },
 221   { "r3", 3 },
 222   { "r4", 4 },
 223   { "r5", 5 },
 224   { "r6", 6 },
 225   { "r7", 7 },
 226   { "r8", 8 },
 227   { "r9", 9 },
 228   { "r10", 10 },
 229   { "r11", 11 },
 230   { "r12", 12 },
 231   { "r13", 13 },
 232   { "r14", 14 },
 233   { "r15", 15 }
 234 };
 235
 236 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 237 {
 238   & m32r_cgen_opval_h_gr_entries[0],
 239   19
 240 };
 241
 242 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 243 {
 244   { "psw", 0 },
 245   { "cbr", 1 },
 246   { "spi", 2 },
 247   { "spu", 3 },
 248   { "bpc", 6 },
 249   { "cr0", 0 },
 250   { "cr1", 1 },
 251   { "cr2", 2 },
 252   { "cr3", 3 },
 253   { "cr4", 4 },
 254   { "cr5", 5 },
 255   { "cr6", 6 }
 256 };
 257
 258 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 259 {
 260   & m32r_cgen_opval_h_cr_entries[0],
 261   12
 262 };
 263
 264 /* start-sanitize-m32rx */
 265 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 266 {
 267   { "a0", 0 },
 268   { "a1", 1 }
 269 };
 270
 271 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 272 {
 273   & m32r_cgen_opval_h_accums_entries[0],
 274   2
 275 };
 276
 277 /* end-sanitize-m32rx */
 278
 279 /* The hardware table.  */
 280
 281 #define HW_ENT(n) m32r_cgen_hw_entries[n]
 282 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 283 {
 284   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
 285   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
 286   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
 287   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
 288   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
 289   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
 290   { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
 291   { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 292   { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 293   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
 294   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
 295   { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
 296 /* start-sanitize-m32rx */
 297   { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
 298 /* end-sanitize-m32rx */
 299 /* start-sanitize-m32rx */
 300   { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
 301 /* end-sanitize-m32rx */
 302   { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
 303   { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
 304   { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
 305   { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
 306   { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
 307   { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
 308   { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
 309   { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
 310   { 0 }
 311 };
 312
 313 /* The operand table.  */
 314
 315 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
 316 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
 317 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 318 {
 319 /* pc: program counter */
 320   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 321     { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } }  },
 322 /* sr: source register */
 323   { "sr", & HW_ENT (HW_H_GR), 12, 4,
 324     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 325 /* dr: destination register */
 326   { "dr", & HW_ENT (HW_H_GR), 4, 4,
 327     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 328 /* src1: source register 1 */
 329   { "src1", & HW_ENT (HW_H_GR), 4, 4,
 330     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 331 /* src2: source register 2 */
 332   { "src2", & HW_ENT (HW_H_GR), 12, 4,
 333     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 334 /* scr: source control register */
 335   { "scr", & HW_ENT (HW_H_CR), 12, 4,
 336     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 337 /* dcr: destination control register */
 338   { "dcr", & HW_ENT (HW_H_CR), 4, 4,
 339     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 340 /* simm8: 8 bit signed immediate */
 341   { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
 342     { 0, 0, { 0 } }  },
 343 /* simm16: 16 bit signed immediate */
 344   { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
 345     { 0, 0, { 0 } }  },
 346 /* uimm4: 4 bit trap number */
 347   { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
 348     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 349 /* uimm5: 5 bit shift count */
 350   { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
 351     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 352 /* uimm16: 16 bit unsigned immediate */
 353   { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
 354     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 355 /* start-sanitize-m32rx */
 356 /* imm1: 1 bit immediate */
 357   { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
 358     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 359 /* end-sanitize-m32rx */
 360 /* start-sanitize-m32rx */
 361 /* accd: accumulator destination register */
 362   { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
 363     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 364 /* end-sanitize-m32rx */
 365 /* start-sanitize-m32rx */
 366 /* accs: accumulator source register */
 367   { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
 368     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 369 /* end-sanitize-m32rx */
 370 /* start-sanitize-m32rx */
 371 /* acc: accumulator reg (d) */
 372   { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
 373     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 374 /* end-sanitize-m32rx */
 375 /* hi16: high 16 bit immediate, sign optional */
 376   { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
 377     { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 378 /* slo16: 16 bit signed immediate, for low() */
 379   { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
 380     { 0, 0, { 0 } }  },
 381 /* ulo16: 16 bit unsigned immediate, for low() */
 382   { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
 383     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 384 /* uimm24: 24 bit address */
 385   { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
 386     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 387 /* disp8: 8 bit displacement */
 388   { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
 389     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 390 /* disp16: 16 bit displacement */
 391   { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
 392     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 393 /* disp24: 24 bit displacement */
 394   { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
 395     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 396 /* condbit: condition bit */
 397   { "condbit", & HW_ENT (HW_H_COND), 0, 0,
 398     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 399 /* accum: accumulator */
 400   { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
 401     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 402 /* start-sanitize-m32rx */
 403 /* abort-parallel-execution: abort parallel execution */
 404   { "abort-parallel-execution", & HW_ENT (HW_H_ABORT), 0, 0,
 405     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 406 /* end-sanitize-m32rx */
 407 };
 408
 409 /* Operand references.  */
 410
 411 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 412 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 413
 414 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
 415   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 416   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 417   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 418   { 0 }
 419 };
 420
 421 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
 422   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 423   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 424   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 425   { 0 }
 426 };
 427
 428 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
 429   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 430   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 431   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 432   { 0 }
 433 };
 434
 435 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
 436   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 437   { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
 438   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 439   { 0 }
 440 };
 441
 442 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
 443   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 444   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 445   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 446   { 0 }
 447 };
 448
 449 static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops[] = {
 450   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 451   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 452   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 453   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 454   { 0 }
 455 };
 456
 457 static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops[] = {
 458   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 459   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 460   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 461   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 462   { 0 }
 463 };
 464
 465 static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = {
 466   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 467   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 468   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 469   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 470   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 471   { 0 }
 472 };
 473
 474 static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops[] = {
 475   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 476   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 477   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 478   { 0 }
 479 };
 480
 481 static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops[] = {
 482   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 483   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 484   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 485   { 0 }
 486 };
 487
 488 static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = {
 489   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 490   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 491   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 492   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 493   { 0 }
 494 };
 495
 496 static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops[] = {
 497   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 498   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 499   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 500   { 0 }
 501 };
 502
 503 static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = {
 504   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 505   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 506   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 507   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 508   { 0 }
 509 };
 510
 511 static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = {
 512   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 513   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 514   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 515   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 516   { 0 }
 517 };
 518
 519 static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
 520   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 521   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 522   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 523   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 524   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 525   { 0 }
 526 };
 527
 528 static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
 529   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 530   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 531   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 532   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 533   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 534   { 0 }
 535 };
 536
 537 static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = {
 538   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 539   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 540   { 0 }
 541 };
 542
 543 static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops[] = {
 544   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 545   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 546   { 0 }
 547 };
 548
 549 static const CGEN_OPERAND_INSTANCE fmt_20_cmp_ops[] = {
 550   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 551   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 552   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 553   { 0 }
 554 };
 555
 556 static const CGEN_OPERAND_INSTANCE fmt_21_cmpi_ops[] = {
 557   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 558   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 559   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 560   { 0 }
 561 };
 562
 563 static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops[] = {
 564   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 565   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 566   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 567   { 0 }
 568 };
 569
 570 static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops[] = {
 571   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 572   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 573   { 0 }
 574 };
 575
 576 static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
 577   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 578   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 579   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 580   { 0 }
 581 };
 582
 583 static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
 584   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 585   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 586   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 587   { 0 }
 588 };
 589
 590 static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = {
 591   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 592   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 593   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 594   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 595   { 0 }
 596 };
 597
 598 static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops[] = {
 599   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 600   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 601   { 0 }
 602 };
 603
 604 static const CGEN_OPERAND_INSTANCE fmt_28_ld_ops[] = {
 605   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 606   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 607   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 608   { 0 }
 609 };
 610
 611 static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops[] = {
 612   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 613   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 614   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 615   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 616   { 0 }
 617 };
 618
 619 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_ops[] = {
 620   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 621   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 622   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 623   { 0 }
 624 };
 625
 626 static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops[] = {
 627   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 628   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 629   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 630   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 631   { 0 }
 632 };
 633
 634 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_ops[] = {
 635   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 636   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 637   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 638   { 0 }
 639 };
 640
 641 static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops[] = {
 642   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 643   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 644   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 645   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 646   { 0 }
 647 };
 648
 649 static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops[] = {
 650   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 651   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 652   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 653   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 654   { 0 }
 655 };
 656
 657 static const CGEN_OPERAND_INSTANCE fmt_37_ld24_ops[] = {
 658   { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
 659   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 660   { 0 }
 661 };
 662
 663 static const CGEN_OPERAND_INSTANCE fmt_38_ldi8_ops[] = {
 664   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 665   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 666   { 0 }
 667 };
 668
 669 static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops[] = {
 670   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 671   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 672   { 0 }
 673 };
 674
 675 static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = {
 676   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 677   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 678   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 679   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 680   { 0 }
 681 };
 682
 683 static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = {
 684   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 685   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 686   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 687   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 688   { 0 }
 689 };
 690
 691 static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = {
 692   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 693   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 694   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 695   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 696   { 0 }
 697 };
 698
 699 static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = {
 700   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 701   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 702   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 703   { 0 }
 704 };
 705
 706 static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = {
 707   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 708   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 709   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 710   { 0 }
 711 };
 712
 713 static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops[] = {
 714   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 715   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 716   { 0 }
 717 };
 718
 719 static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops[] = {
 720   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 721   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 722   { 0 }
 723 };
 724
 725 static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = {
 726   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 727   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 728   { 0 }
 729 };
 730
 731 static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = {
 732   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
 733   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 734   { 0 }
 735 };
 736
 737 static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = {
 738   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 739   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 740   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 741   { 0 }
 742 };
 743
 744 static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
 745   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 746   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 747   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 748   { 0 }
 749 };
 750
 751 static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = {
 752   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 753   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
 754   { 0 }
 755 };
 756
 757 static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = {
 758   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 759   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 760   { 0 }
 761 };
 762
 763 static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
 764   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 765   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
 766   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 767   { 0 }
 768 };
 769
 770 static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = {
 771   { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
 772   { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
 773   { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
 774   { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
 775   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 776   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 777   { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
 778   { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
 779   { 0 }
 780 };
 781
 782 static const CGEN_OPERAND_INSTANCE fmt_58_seth_ops[] = {
 783   { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
 784   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 785   { 0 }
 786 };
 787
 788 static const CGEN_OPERAND_INSTANCE fmt_59_sll3_ops[] = {
 789   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 790   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 791   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 792   { 0 }
 793 };
 794
 795 static const CGEN_OPERAND_INSTANCE fmt_60_slli_ops[] = {
 796   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 797   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
 798   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 799   { 0 }
 800 };
 801
 802 static const CGEN_OPERAND_INSTANCE fmt_61_st_ops[] = {
 803   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 804   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 805   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 806   { 0 }
 807 };
 808
 809 static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops[] = {
 810   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 811   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 812   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 813   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 814   { 0 }
 815 };
 816
 817 static const CGEN_OPERAND_INSTANCE fmt_65_stb_ops[] = {
 818   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 819   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 820   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 821   { 0 }
 822 };
 823
 824 static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops[] = {
 825   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 826   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 827   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 828   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 829   { 0 }
 830 };
 831
 832 static const CGEN_OPERAND_INSTANCE fmt_67_sth_ops[] = {
 833   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 834   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 835   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 836   { 0 }
 837 };
 838
 839 static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops[] = {
 840   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 841   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 842   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 843   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 844   { 0 }
 845 };
 846
 847 static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = {
 848   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 849   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 850   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 851   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 852   { 0 }
 853 };
 854
 855 static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = {
 856   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 857   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
 858   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
 859   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 860   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
 861   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 6 },
 862   { 0 }
 863 };
 864
 865 static const CGEN_OPERAND_INSTANCE fmt_72_unlock_ops[] = {
 866   { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 867   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 868   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 869   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 870   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 871   { 0 }
 872 };
 873
 874 static const CGEN_OPERAND_INSTANCE fmt_75_satb_ops[] = {
 875   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 876   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 877   { 0 }
 878 };
 879
 880 static const CGEN_OPERAND_INSTANCE fmt_76_sat_ops[] = {
 881   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 882   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 883   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 884   { 0 }
 885 };
 886
 887 static const CGEN_OPERAND_INSTANCE fmt_77_sadd_ops[] = {
 888   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 889   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 890   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 891   { 0 }
 892 };
 893
 894 static const CGEN_OPERAND_INSTANCE fmt_78_macwu1_ops[] = {
 895   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 896   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 897   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 898   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 899   { 0 }
 900 };
 901
 902 static const CGEN_OPERAND_INSTANCE fmt_79_mulwu1_ops[] = {
 903   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 904   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 905   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 906   { 0 }
 907 };
 908
 909 static const CGEN_OPERAND_INSTANCE fmt_80_sc_ops[] = {
 910   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 911   { OUTPUT, & HW_ENT (HW_H_ABORT), CGEN_MODE_UBI, 0, 0 },
 912   { 0 }
 913 };
 914
 915 #undef INPUT
 916 #undef OUTPUT
 917
 918 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 919 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 920
 921 static const CGEN_SYNTAX syntax_table[] =
 922 {
 923 /* <mnem> $dr,$sr */
 924 /*   0 */  { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
 925 /* <mnem> $dr,$sr,#$slo16 */
 926 /*   1 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SLO16), 0 },
 927 /* <mnem> $dr,$sr,$slo16 */
 928 /*   2 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SLO16), 0 },
 929 /* <mnem> $dr,$sr,#$uimm16 */
 930 /*   3 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (UIMM16), 0 },
 931 /* <mnem> $dr,$sr,$uimm16 */
 932 /*   4 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
 933 /* <mnem> $dr,$sr,#$ulo16 */
 934 /*   5 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (ULO16), 0 },
 935 /* <mnem> $dr,$sr,$ulo16 */
 936 /*   6 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (ULO16), 0 },
 937 /* <mnem> $dr,#$simm8 */
 938 /*   7 */  { MNEM, ' ', OP (DR), ',', '#', OP (SIMM8), 0 },
 939 /* <mnem> $dr,$simm8 */
 940 /*   8 */  { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
 941 /* <mnem> $dr,$sr,#$simm16 */
 942 /*   9 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
 943 /* <mnem> $dr,$sr,$simm16 */
 944 /*  10 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
 945 /* <mnem> $disp8 */
 946 /*  11 */  { MNEM, ' ', OP (DISP8), 0 },
 947 /* <mnem> $disp24 */
 948 /*  12 */  { MNEM, ' ', OP (DISP24), 0 },
 949 /* <mnem> $src1,$src2,$disp16 */
 950 /*  13 */  { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
 951 /* <mnem> $src2,$disp16 */
 952 /*  14 */  { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
 953 /* <mnem> $src1,$src2 */
 954 /*  15 */  { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
 955 /* <mnem> $src2,#$simm16 */
 956 /*  16 */  { MNEM, ' ', OP (SRC2), ',', '#', OP (SIMM16), 0 },
 957 /* <mnem> $src2,$simm16 */
 958 /*  17 */  { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
 959 /* <mnem> $src2,#$uimm16 */
 960 /*  18 */  { MNEM, ' ', OP (SRC2), ',', '#', OP (UIMM16), 0 },
 961 /* <mnem> $src2,$uimm16 */
 962 /*  19 */  { MNEM, ' ', OP (SRC2), ',', OP (UIMM16), 0 },
 963 /* <mnem> $src2 */
 964 /*  20 */  { MNEM, ' ', OP (SRC2), 0 },
 965 /* <mnem> $sr */
 966 /*  21 */  { MNEM, ' ', OP (SR), 0 },
 967 /* <mnem> $dr,@$sr */
 968 /*  22 */  { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
 969 /* <mnem> $dr,@($sr) */
 970 /*  23 */  { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
 971 /* <mnem> $dr,@($slo16,$sr) */
 972 /*  24 */  { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
 973 /* <mnem> $dr,@($sr,$slo16) */
 974 /*  25 */  { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
 975 /* <mnem> $dr,@$sr+ */
 976 /*  26 */  { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
 977 /* <mnem> $dr,#$uimm24 */
 978 /*  27 */  { MNEM, ' ', OP (DR), ',', '#', OP (UIMM24), 0 },
 979 /* <mnem> $dr,$uimm24 */
 980 /*  28 */  { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
 981 /* <mnem> $dr,$slo16 */
 982 /*  29 */  { MNEM, ' ', OP (DR), ',', OP (SLO16), 0 },
 983 /* <mnem> $src1,$src2,$acc */
 984 /*  30 */  { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
 985 /* <mnem> $dr */
 986 /*  31 */  { MNEM, ' ', OP (DR), 0 },
 987 /* <mnem> $dr,$accs */
 988 /*  32 */  { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
 989 /* <mnem> $dr,$scr */
 990 /*  33 */  { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
 991 /* <mnem> $src1 */
 992 /*  34 */  { MNEM, ' ', OP (SRC1), 0 },
 993 /* <mnem> $src1,$accs */
 994 /*  35 */  { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
 995 /* <mnem> $sr,$dcr */
 996 /*  36 */  { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
 997 /* <mnem> */
 998 /*  37 */  { MNEM, 0 },
 999 /* <mnem> $accd */
1000 /*  38 */  { MNEM, ' ', OP (ACCD), 0 },
1001 /* <mnem> $accd,$accs */
1002 /*  39 */  { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
1003 /* <mnem> $accd,$accs,#$imm1 */
1004 /*  40 */  { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', '#', OP (IMM1), 0 },
1005 /* <mnem> $dr,#$hi16 */
1006 /*  41 */  { MNEM, ' ', OP (DR), ',', '#', OP (HI16), 0 },
1007 /* <mnem> $dr,$hi16 */
1008 /*  42 */  { MNEM, ' ', OP (DR), ',', OP (HI16), 0 },
1009 /* <mnem> $dr,#$uimm5 */
1010 /*  43 */  { MNEM, ' ', OP (DR), ',', '#', OP (UIMM5), 0 },
1011 /* <mnem> $dr,$uimm5 */
1012 /*  44 */  { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1013 /* <mnem> $src1,@$src2 */
1014 /*  45 */  { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
1015 /* <mnem> $src1,@($src2) */
1016 /*  46 */  { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
1017 /* <mnem> $src1,@($slo16,$src2) */
1018 /*  47 */  { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
1019 /* <mnem> $src1,@($src2,$slo16) */
1020 /*  48 */  { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
1021 /* <mnem> $src1,@+$src2 */
1022 /*  49 */  { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
1023 /* <mnem> $src1,@-$src2 */
1024 /*  50 */  { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
1025 /* <mnem> #$uimm4 */
1026 /*  51 */  { MNEM, ' ', '#', OP (UIMM4), 0 },
1027 /* <mnem> $uimm4 */
1028 /*  52 */  { MNEM, ' ', OP (UIMM4), 0 },
1029 };
1030
1031 #undef MNEM
1032 #undef OP
1033
1034 static const CGEN_FORMAT format_table[] =
1035 {
1036 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(dr SI) */
1037 /*   0 */  { 16, 16, 0xf0f0 },
1038 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(slo16 HI)(sr SI)(dr SI) */
1039 /*   1 */  { 32, 32, 0xf0f00000 },
1040 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 uimm16)(sr SI)(uimm16 USI)(dr SI) */
1041 /*   2 */  { 32, 32, 0xf0f00000 },
1042 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 ulo16)(sr SI)(ulo16 UHI)(dr SI) */
1043 /*   3 */  { 32, 32, 0xf0f00000 },
1044 /* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(dr SI)(simm8 SI)(dr SI) */
1045 /*   4 */  { 16, 16, 0xf000 },
1046 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(condbit UBI)(dr SI) */
1047 /*   5 */  { 16, 16, 0xf0f0 },
1048 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(condbit UBI)(dr SI) */
1049 /*   6 */  { 32, 32, 0xf0f00000 },
1050 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(condbit UBI)(dr SI)(sr SI)(condbit UBI)(dr SI) */
1051 /*   7 */  { 16, 16, 0xf0f0 },
1052 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI) */
1053 /*   8 */  { 16, 16, 0xff00 },
1054 /* (f-op1 #)(f-r1 #)(f-disp8 disp8) */
1055 /*   9 */  { 16, 16, 0xff00 },
1056 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI) */
1057 /*  10 */  { 32, 32, 0xff000000 },
1058 /* (f-op1 #)(f-r1 #)(f-disp24 disp24) */
1059 /*  11 */  { 32, 32, 0xff000000 },
1060 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src1 SI)(src2 SI)(pc USI) */
1061 /*  12 */  { 32, 32, 0xf0f00000 },
1062 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src2 SI)(pc USI) */
1063 /*  13 */  { 32, 32, 0xfff00000 },
1064 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI)(pc USI)(h-gr-14 SI) */
1065 /*  14 */  { 16, 16, 0xff00 },
1066 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI)(pc USI)(h-gr-14 SI) */
1067 /*  15 */  { 32, 32, 0xff000000 },
1068 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI)(pc USI)(h-gr-14 SI) */
1069 /*  16 */  { 16, 16, 0xff00 },
1070 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI)(pc USI)(h-gr-14 SI) */
1071 /*  17 */  { 32, 32, 0xff000000 },
1072 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI) */
1073 /*  18 */  { 16, 16, 0xff00 },
1074 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI) */
1075 /*  19 */  { 32, 32, 0xff000000 },
1076 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(condbit UBI) */
1077 /*  20 */  { 16, 16, 0xf0f0 },
1078 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-simm16 simm16)(simm16 SI)(src2 SI)(condbit UBI) */
1079 /*  21 */  { 32, 32, 0xfff00000 },
1080 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-uimm16 uimm16)(src2 SI)(uimm16 USI)(condbit UBI) */
1081 /*  22 */  { 32, 32, 0xfff00000 },
1082 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(src2 SI)(condbit UBI) */
1083 /*  23 */  { 16, 16, 0xfff0 },
1084 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 #)(dr SI)(sr SI)(dr SI) */
1085 /*  24 */  { 32, 32, 0xf0f0ffff },
1086 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(condbit UBI)(sr SI)(pc USI) */
1087 /*  25 */  { 16, 16, 0xfff0 },
1088 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(pc USI)(sr SI)(pc USI)(h-gr-14 SI) */
1089 /*  26 */  { 16, 16, 0xfff0 },
1090 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(sr SI)(pc USI) */
1091 /*  27 */  { 16, 16, 0xfff0 },
1092 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI) */
1093 /*  28 */  { 16, 16, 0xf0f0 },
1094 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr) */
1095 /*  29 */  { 16, 16, 0xf0f0 },
1096 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 SI)(slo16 HI)(sr SI)(dr SI) */
1097 /*  30 */  { 32, 32, 0xf0f00000 },
1098 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16) */
1099 /*  31 */  { 32, 32, 0xf0f00000 },
1100 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr QI)(sr SI)(dr SI) */
1101 /*  32 */  { 16, 16, 0xf0f0 },
1102 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 QI)(slo16 HI)(sr SI)(dr SI) */
1103 /*  33 */  { 32, 32, 0xf0f00000 },
1104 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr HI)(sr SI)(dr SI) */
1105 /*  34 */  { 16, 16, 0xf0f0 },
1106 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 HI)(slo16 HI)(sr SI)(dr SI) */
1107 /*  35 */  { 32, 32, 0xf0f00000 },
1108 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(sr SI) */
1109 /*  36 */  { 16, 16, 0xf0f0 },
1110 /* (f-op1 #)(f-r1 dr)(f-uimm24 uimm24)(uimm24 VM)(dr SI) */
1111 /*  37 */  { 32, 32, 0xf0000000 },
1112 /* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(simm8 SI)(dr SI) */
1113 /*  38 */  { 16, 16, 0xf000 },
1114 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-simm16 slo16)(slo16 HI)(dr SI) */
1115 /*  39 */  { 32, 32, 0xf0ff0000 },
1116 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(h-lock-0 UBI) */
1117 /*  40 */  { 16, 16, 0xf0f0 },
1118 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(accum DI)(src1 SI)(src2 SI)(accum DI) */
1119 /*  41 */  { 16, 16, 0xf0f0 },
1120 /* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(acc DI)(src1 SI)(src2 SI)(acc DI) */
1121 /*  42 */  { 16, 16, 0xf070 },
1122 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(accum DI) */
1123 /*  43 */  { 16, 16, 0xf0f0 },
1124 /* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(src1 SI)(src2 SI)(acc DI) */
1125 /*  44 */  { 16, 16, 0xf070 },
1126 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(sr SI)(dr SI) */
1127 /*  45 */  { 16, 16, 0xf0f0 },
1128 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(accum DI)(dr SI) */
1129 /*  46 */  { 16, 16, 0xf0ff },
1130 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(dr SI) */
1131 /*  47 */  { 16, 16, 0xf0f3 },
1132 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 scr)(scr USI)(dr SI) */
1133 /*  48 */  { 16, 16, 0xf0f0 },
1134 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #)(accum DI)(src1 SI)(accum DI) */
1135 /*  49 */  { 16, 16, 0xf0ff },
1136 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(src1 SI)(accs DI) */
1137 /*  50 */  { 16, 16, 0xf0f3 },
1138 /* (f-op1 #)(f-r1 dcr)(f-op2 #)(f-r2 sr)(sr SI)(dcr USI) */
1139 /*  51 */  { 16, 16, 0xf0f0 },
1140 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #) */
1141 /*  52 */  { 16, 16, 0xffff },
1142 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(accum DI)(accum DI) */
1143 /*  53 */  { 16, 16, 0xffff },
1144 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs #)(f-bit14 #)(f-imm1 #) */
1145 /*  54 */  { 16, 16, 0xf3ff },
1146 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 #) */
1147 /*  55 */  { 16, 16, 0xf3f3 },
1148 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 imm1)(accs DI)(imm1 USI)(accd DI) */
1149 /*  56 */  { 16, 16, 0xf3f2 },
1150 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-bcond-0 VM)(h-bie-0 VM)(h-bpc-0 VM)(h-bsm-0 VM)(condbit UBI)(pc USI)(h-ie-0 VM)(h-sm-0 VM) */
1151 /*  57 */  { 16, 16, 0xffff },
1152 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-hi16 hi16)(hi16 UHI)(dr SI) */
1153 /*  58 */  { 32, 32, 0xf0ff0000 },
1154 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(dr SI) */
1155 /*  59 */  { 32, 32, 0xf0f00000 },
1156 /* (f-op1 #)(f-r1 dr)(f-shift-op2 #)(f-uimm5 uimm5)(dr SI)(uimm5 USI)(dr SI) */
1157 /*  60 */  { 16, 16, 0xf0e0 },
1158 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI) */
1159 /*  61 */  { 16, 16, 0xf0f0 },
1160 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2) */
1161 /*  62 */  { 16, 16, 0xf0f0 },
1162 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 SI) */
1163 /*  63 */  { 32, 32, 0xf0f00000 },
1164 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16) */
1165 /*  64 */  { 32, 32, 0xf0f00000 },
1166 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 QI) */
1167 /*  65 */  { 16, 16, 0xf0f0 },
1168 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 QI) */
1169 /*  66 */  { 32, 32, 0xf0f00000 },
1170 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 HI) */
1171 /*  67 */  { 16, 16, 0xf0f0 },
1172 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 HI) */
1173 /*  68 */  { 32, 32, 0xf0f00000 },
1174 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI)(src2 SI) */
1175 /*  69 */  { 16, 16, 0xf0f0 },
1176 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4)(pc USI)(h-cr-0 SI)(uimm4 USI)(pc USI)(h-cr-0 SI)(h-cr-6 SI) */
1177 /*  70 */  { 16, 16, 0xfff0 },
1178 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4) */
1179 /*  71 */  { 16, 16, 0xfff0 },
1180 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-lock-0 UBI)(src1 SI)(src2 SI)(h-memory-src2 SI)(h-lock-0 UBI) */
1181 /*  72 */  { 16, 16, 0xf0f0 },
1182 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #) */
1183 /*  73 */  { 16, 16, 0xf0ff },
1184 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #) */
1185 /*  74 */  { 16, 16, 0xf0ff },
1186 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(sr SI)(dr SI) */
1187 /*  75 */  { 32, 32, 0xf0f0ffff },
1188 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(condbit UBI)(sr SI)(dr SI) */
1189 /*  76 */  { 32, 32, 0xf0f0ffff },
1190 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-accums-0 DI)(h-accums-1 DI)(h-accums-0 DI) */
1191 /*  77 */  { 16, 16, 0xffff },
1192 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-accums-1 DI)(src1 SI)(src2 SI)(h-accums-1 DI) */
1193 /*  78 */  { 16, 16, 0xf0f0 },
1194 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-accums-1 DI) */
1195 /*  79 */  { 16, 16, 0xf0f0 },
1196 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(condbit UBI)(abort-parallel-execution UBI) */
1197 /*  80 */  { 16, 16, 0xffff },
1198 };
1199
1200 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
1201 #define SYN(n) (& syntax_table[n])
1202 #define FMT(n) (& format_table[n])
1203
1204 /* The instruction table.  */
1205
1206 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
1207 {
1208   /* null first entry, end of all hash chains */
1209   { { 0 }, 0 },
1210 /* add $dr,$sr */
1211   {
1212     { 1, 1, 1, 1 },
1213     "add", "add", SYN (0), FMT (0), 0xa0,
1214     & fmt_0_add_ops[0],
1215     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1216   },
1217 /* add3 $dr,$sr,#$slo16 */
1218   {
1219     { 1, 1, 1, 1 },
1220     "add3", "add3", SYN (1), FMT (1), 0x80a00000,
1221     & fmt_1_add3_ops[0],
1222     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1223   },
1224 /* add3 $dr,$sr,$slo16 */
1225   {
1226     { 1, 1, 1, 1 },
1227     "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
1228     & fmt_1_add3_ops[0],
1229     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1230   },
1231 /* and $dr,$sr */
1232   {
1233     { 1, 1, 1, 1 },
1234     "and", "and", SYN (0), FMT (0), 0xc0,
1235     & fmt_0_add_ops[0],
1236     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1237   },
1238 /* and3 $dr,$sr,#$uimm16 */
1239   {
1240     { 1, 1, 1, 1 },
1241     "and3", "and3", SYN (3), FMT (2), 0x80c00000,
1242     & fmt_2_and3_ops[0],
1243     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1244   },
1245 /* and3 $dr,$sr,$uimm16 */
1246   {
1247     { 1, 1, 1, 1 },
1248     "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
1249     & fmt_2_and3_ops[0],
1250     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1251   },
1252 /* or $dr,$sr */
1253   {
1254     { 1, 1, 1, 1 },
1255     "or", "or", SYN (0), FMT (0), 0xe0,
1256     & fmt_0_add_ops[0],
1257     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1258   },
1259 /* or3 $dr,$sr,#$ulo16 */
1260   {
1261     { 1, 1, 1, 1 },
1262     "or3", "or3", SYN (5), FMT (3), 0x80e00000,
1263     & fmt_3_or3_ops[0],
1264     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1265   },
1266 /* or3 $dr,$sr,$ulo16 */
1267   {
1268     { 1, 1, 1, 1 },
1269     "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
1270     & fmt_3_or3_ops[0],
1271     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1272   },
1273 /* xor $dr,$sr */
1274   {
1275     { 1, 1, 1, 1 },
1276     "xor", "xor", SYN (0), FMT (0), 0xd0,
1277     & fmt_0_add_ops[0],
1278     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1279   },
1280 /* xor3 $dr,$sr,#$uimm16 */
1281   {
1282     { 1, 1, 1, 1 },
1283     "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
1284     & fmt_2_and3_ops[0],
1285     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1286   },
1287 /* xor3 $dr,$sr,$uimm16 */
1288   {
1289     { 1, 1, 1, 1 },
1290     "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
1291     & fmt_2_and3_ops[0],
1292     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1293   },
1294 /* addi $dr,#$simm8 */
1295   {
1296     { 1, 1, 1, 1 },
1297     "addi", "addi", SYN (7), FMT (4), 0x4000,
1298     & fmt_4_addi_ops[0],
1299     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1300   },
1301 /* addi $dr,$simm8 */
1302   {
1303     { 1, 1, 1, 1 },
1304     "addi.a", "addi", SYN (8), FMT (4), 0x4000,
1305     & fmt_4_addi_ops[0],
1306     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1307   },
1308 /* addv $dr,$sr */
1309   {
1310     { 1, 1, 1, 1 },
1311     "addv", "addv", SYN (0), FMT (5), 0x80,
1312     & fmt_5_addv_ops[0],
1313     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1314   },
1315 /* addv3 $dr,$sr,#$simm16 */
1316   {
1317     { 1, 1, 1, 1 },
1318     "addv3", "addv3", SYN (9), FMT (6), 0x80800000,
1319     & fmt_6_addv3_ops[0],
1320     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1321   },
1322 /* addv3 $dr,$sr,$simm16 */
1323   {
1324     { 1, 1, 1, 1 },
1325     "addv3.a", "addv3", SYN (10), FMT (6), 0x80800000,
1326     & fmt_6_addv3_ops[0],
1327     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1328   },
1329 /* addx $dr,$sr */
1330   {
1331     { 1, 1, 1, 1 },
1332     "addx", "addx", SYN (0), FMT (7), 0x90,
1333     & fmt_7_addx_ops[0],
1334     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1335   },
1336 /* bc $disp8 */
1337   {
1338     { 1, 1, 1, 1 },
1339     "bc8", "bc", SYN (11), FMT (8), 0x7c00,
1340     & fmt_8_bc8_ops[0],
1341     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1342   },
1343 /* bc.s $disp8 */
1344   {
1345     { 1, 1, 1, 1 },
1346     "bc8.s", "bc.s", SYN (11), FMT (9), 0x7c00,
1347     0,
1348     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1349   },
1350 /* bc $disp24 */
1351   {
1352     { 1, 1, 1, 1 },
1353     "bc24", "bc", SYN (12), FMT (10), 0xfc000000,
1354     & fmt_10_bc24_ops[0],
1355     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1356   },
1357 /* bc.l $disp24 */
1358   {
1359     { 1, 1, 1, 1 },
1360     "bc24.l", "bc.l", SYN (12), FMT (11), 0xfc000000,
1361     0,
1362     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1363   },
1364 /* beq $src1,$src2,$disp16 */
1365   {
1366     { 1, 1, 1, 1 },
1367     "beq", "beq", SYN (13), FMT (12), 0xb0000000,
1368     & fmt_12_beq_ops[0],
1369     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1370   },
1371 /* beqz $src2,$disp16 */
1372   {
1373     { 1, 1, 1, 1 },
1374     "beqz", "beqz", SYN (14), FMT (13), 0xb0800000,
1375     & fmt_13_beqz_ops[0],
1376     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1377   },
1378 /* bgez $src2,$disp16 */
1379   {
1380     { 1, 1, 1, 1 },
1381     "bgez", "bgez", SYN (14), FMT (13), 0xb0b00000,
1382     & fmt_13_beqz_ops[0],
1383     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1384   },
1385 /* bgtz $src2,$disp16 */
1386   {
1387     { 1, 1, 1, 1 },
1388     "bgtz", "bgtz", SYN (14), FMT (13), 0xb0d00000,
1389     & fmt_13_beqz_ops[0],
1390     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1391   },
1392 /* blez $src2,$disp16 */
1393   {
1394     { 1, 1, 1, 1 },
1395     "blez", "blez", SYN (14), FMT (13), 0xb0c00000,
1396     & fmt_13_beqz_ops[0],
1397     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1398   },
1399 /* bltz $src2,$disp16 */
1400   {
1401     { 1, 1, 1, 1 },
1402     "bltz", "bltz", SYN (14), FMT (13), 0xb0a00000,
1403     & fmt_13_beqz_ops[0],
1404     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1405   },
1406 /* bnez $src2,$disp16 */
1407   {
1408     { 1, 1, 1, 1 },
1409     "bnez", "bnez", SYN (14), FMT (13), 0xb0900000,
1410     & fmt_13_beqz_ops[0],
1411     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1412   },
1413 /* bl $disp8 */
1414   {
1415     { 1, 1, 1, 1 },
1416     "bl8", "bl", SYN (11), FMT (14), 0x7e00,
1417     & fmt_14_bl8_ops[0],
1418     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1419   },
1420 /* bl.s $disp8 */
1421   {
1422     { 1, 1, 1, 1 },
1423     "bl8.s", "bl.s", SYN (11), FMT (9), 0x7e00,
1424     0,
1425     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1426   },
1427 /* bl $disp24 */
1428   {
1429     { 1, 1, 1, 1 },
1430     "bl24", "bl", SYN (12), FMT (15), 0xfe000000,
1431     & fmt_15_bl24_ops[0],
1432     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1433   },
1434 /* bl.l $disp24 */
1435   {
1436     { 1, 1, 1, 1 },
1437     "bl24.l", "bl.l", SYN (12), FMT (11), 0xfe000000,
1438     0,
1439     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1440   },
1441 /* start-sanitize-m32rx */
1442 /* bcl $disp8 */
1443   {
1444     { 1, 1, 1, 1 },
1445     "bcl8", "bcl", SYN (11), FMT (16), 0x7800,
1446     & fmt_16_bcl8_ops[0],
1447     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1448   },
1449 /* end-sanitize-m32rx */
1450 /* start-sanitize-m32rx */
1451 /* bcl.s $disp8 */
1452   {
1453     { 1, 1, 1, 1 },
1454     "bcl8.s", "bcl.s", SYN (11), FMT (9), 0x7800,
1455     0,
1456     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1457   },
1458 /* end-sanitize-m32rx */
1459 /* start-sanitize-m32rx */
1460 /* bcl $disp24 */
1461   {
1462     { 1, 1, 1, 1 },
1463     "bcl24", "bcl", SYN (12), FMT (17), 0xf8000000,
1464     & fmt_17_bcl24_ops[0],
1465     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1466   },
1467 /* end-sanitize-m32rx */
1468 /* start-sanitize-m32rx */
1469 /* bcl.l $disp24 */
1470   {
1471     { 1, 1, 1, 1 },
1472     "bcl24.l", "bcl.l", SYN (12), FMT (11), 0xf8000000,
1473     0,
1474     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1475   },
1476 /* end-sanitize-m32rx */
1477 /* bnc $disp8 */
1478   {
1479     { 1, 1, 1, 1 },
1480     "bnc8", "bnc", SYN (11), FMT (8), 0x7d00,
1481     & fmt_8_bc8_ops[0],
1482     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1483   },
1484 /* bnc.s $disp8 */
1485   {
1486     { 1, 1, 1, 1 },
1487     "bnc8.s", "bnc.s", SYN (11), FMT (9), 0x7d00,
1488     0,
1489     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1490   },
1491 /* bnc $disp24 */
1492   {
1493     { 1, 1, 1, 1 },
1494     "bnc24", "bnc", SYN (12), FMT (10), 0xfd000000,
1495     & fmt_10_bc24_ops[0],
1496     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1497   },
1498 /* bnc.l $disp24 */
1499   {
1500     { 1, 1, 1, 1 },
1501     "bnc24.l", "bnc.l", SYN (12), FMT (11), 0xfd000000,
1502     0,
1503     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1504   },
1505 /* bne $src1,$src2,$disp16 */
1506   {
1507     { 1, 1, 1, 1 },
1508     "bne", "bne", SYN (13), FMT (12), 0xb0100000,
1509     & fmt_12_beq_ops[0],
1510     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1511   },
1512 /* bra $disp8 */
1513   {
1514     { 1, 1, 1, 1 },
1515     "bra8", "bra", SYN (11), FMT (18), 0x7f00,
1516     & fmt_18_bra8_ops[0],
1517     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1518   },
1519 /* bra.s $disp8 */
1520   {
1521     { 1, 1, 1, 1 },
1522     "bra8.s", "bra.s", SYN (11), FMT (9), 0x7f00,
1523     0,
1524     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1525   },
1526 /* bra $disp24 */
1527   {
1528     { 1, 1, 1, 1 },
1529     "bra24", "bra", SYN (12), FMT (19), 0xff000000,
1530     & fmt_19_bra24_ops[0],
1531     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1532   },
1533 /* bra.l $disp24 */
1534   {
1535     { 1, 1, 1, 1 },
1536     "bra24.l", "bra.l", SYN (12), FMT (11), 0xff000000,
1537     0,
1538     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1539   },
1540 /* start-sanitize-m32rx */
1541 /* bncl $disp8 */
1542   {
1543     { 1, 1, 1, 1 },
1544     "bncl8", "bncl", SYN (11), FMT (16), 0x7900,
1545     & fmt_16_bcl8_ops[0],
1546     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1547   },
1548 /* end-sanitize-m32rx */
1549 /* start-sanitize-m32rx */
1550 /* bncl.s $disp8 */
1551   {
1552     { 1, 1, 1, 1 },
1553     "bncl8.s", "bncl.s", SYN (11), FMT (9), 0x7900,
1554     0,
1555     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1556   },
1557 /* end-sanitize-m32rx */
1558 /* start-sanitize-m32rx */
1559 /* bncl $disp24 */
1560   {
1561     { 1, 1, 1, 1 },
1562     "bncl24", "bncl", SYN (12), FMT (17), 0xf9000000,
1563     & fmt_17_bcl24_ops[0],
1564     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1565   },
1566 /* end-sanitize-m32rx */
1567 /* start-sanitize-m32rx */
1568 /* bncl.l $disp24 */
1569   {
1570     { 1, 1, 1, 1 },
1571     "bncl24.l", "bncl.l", SYN (12), FMT (11), 0xf9000000,
1572     0,
1573     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1574   },
1575 /* end-sanitize-m32rx */
1576 /* cmp $src1,$src2 */
1577   {
1578     { 1, 1, 1, 1 },
1579     "cmp", "cmp", SYN (15), FMT (20), 0x40,
1580     & fmt_20_cmp_ops[0],
1581     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1582   },
1583 /* cmpi $src2,#$simm16 */
1584   {
1585     { 1, 1, 1, 1 },
1586     "cmpi", "cmpi", SYN (16), FMT (21), 0x80400000,
1587     & fmt_21_cmpi_ops[0],
1588     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1589   },
1590 /* cmpi $src2,$simm16 */
1591   {
1592     { 1, 1, 1, 1 },
1593     "cmpi.a", "cmpi", SYN (17), FMT (21), 0x80400000,
1594     & fmt_21_cmpi_ops[0],
1595     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1596   },
1597 /* cmpu $src1,$src2 */
1598   {
1599     { 1, 1, 1, 1 },
1600     "cmpu", "cmpu", SYN (15), FMT (20), 0x50,
1601     & fmt_20_cmp_ops[0],
1602     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1603   },
1604 /* cmpui $src2,#$uimm16 */
1605   {
1606     { 1, 1, 1, 1 },
1607     "cmpui", "cmpui", SYN (18), FMT (22), 0x80500000,
1608     & fmt_22_cmpui_ops[0],
1609     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1610   },
1611 /* cmpui $src2,$uimm16 */
1612   {
1613     { 1, 1, 1, 1 },
1614     "cmpui.a", "cmpui", SYN (19), FMT (22), 0x80500000,
1615     & fmt_22_cmpui_ops[0],
1616     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1617   },
1618 /* start-sanitize-m32rx */
1619 /* cmpeq $src1,$src2 */
1620   {
1621     { 1, 1, 1, 1 },
1622     "cmpeq", "cmpeq", SYN (15), FMT (20), 0x60,
1623     & fmt_20_cmp_ops[0],
1624     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1625   },
1626 /* end-sanitize-m32rx */
1627 /* start-sanitize-m32rx */
1628 /* cmpz $src2 */
1629   {
1630     { 1, 1, 1, 1 },
1631     "cmpz", "cmpz", SYN (20), FMT (23), 0x70,
1632     & fmt_23_cmpz_ops[0],
1633     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1634   },
1635 /* end-sanitize-m32rx */
1636 /* div $dr,$sr */
1637   {
1638     { 1, 1, 1, 1 },
1639     "div", "div", SYN (0), FMT (24), 0x90000000,
1640     & fmt_24_div_ops[0],
1641     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1642   },
1643 /* divu $dr,$sr */
1644   {
1645     { 1, 1, 1, 1 },
1646     "divu", "divu", SYN (0), FMT (24), 0x90100000,
1647     & fmt_24_div_ops[0],
1648     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1649   },
1650 /* rem $dr,$sr */
1651   {
1652     { 1, 1, 1, 1 },
1653     "rem", "rem", SYN (0), FMT (24), 0x90200000,
1654     & fmt_24_div_ops[0],
1655     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1656   },
1657 /* remu $dr,$sr */
1658   {
1659     { 1, 1, 1, 1 },
1660     "remu", "remu", SYN (0), FMT (24), 0x90300000,
1661     & fmt_24_div_ops[0],
1662     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1663   },
1664 /* start-sanitize-m32rx */
1665 /* divh $dr,$sr */
1666   {
1667     { 1, 1, 1, 1 },
1668     "divh", "divh", SYN (0), FMT (24), 0x90000010,
1669     & fmt_24_div_ops[0],
1670     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1671   },
1672 /* end-sanitize-m32rx */
1673 /* start-sanitize-m32rx */
1674 /* jc $sr */
1675   {
1676     { 1, 1, 1, 1 },
1677     "jc", "jc", SYN (21), FMT (25), 0x1cc0,
1678     & fmt_25_jc_ops[0],
1679     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1680   },
1681 /* end-sanitize-m32rx */
1682 /* start-sanitize-m32rx */
1683 /* jnc $sr */
1684   {
1685     { 1, 1, 1, 1 },
1686     "jnc", "jnc", SYN (21), FMT (25), 0x1dc0,
1687     & fmt_25_jc_ops[0],
1688     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1689   },
1690 /* end-sanitize-m32rx */
1691 /* jl $sr */
1692   {
1693     { 1, 1, 1, 1 },
1694     "jl", "jl", SYN (21), FMT (26), 0x1ec0,
1695     & fmt_26_jl_ops[0],
1696     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1697   },
1698 /* jmp $sr */
1699   {
1700     { 1, 1, 1, 1 },
1701     "jmp", "jmp", SYN (21), FMT (27), 0x1fc0,
1702     & fmt_27_jmp_ops[0],
1703     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1704   },
1705 /* ld $dr,@$sr */
1706   {
1707     { 1, 1, 1, 1 },
1708     "ld", "ld", SYN (22), FMT (28), 0x20c0,
1709     & fmt_28_ld_ops[0],
1710     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1711   },
1712 /* ld $dr,@($sr) */
1713   {
1714     { 1, 1, 1, 1 },
1715     "ld-2", "ld", SYN (23), FMT (29), 0x20c0,
1716     0,
1717     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1718   },
1719 /* ld $dr,@($slo16,$sr) */
1720   {
1721     { 1, 1, 1, 1 },
1722     "ld-d", "ld", SYN (24), FMT (30), 0xa0c00000,
1723     & fmt_30_ld_d_ops[0],
1724     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1725   },
1726 /* ld $dr,@($sr,$slo16) */
1727   {
1728     { 1, 1, 1, 1 },
1729     "ld-d2", "ld", SYN (25), FMT (31), 0xa0c00000,
1730     0,
1731     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1732   },
1733 /* ldb $dr,@$sr */
1734   {
1735     { 1, 1, 1, 1 },
1736     "ldb", "ldb", SYN (22), FMT (32), 0x2080,
1737     & fmt_32_ldb_ops[0],
1738     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1739   },
1740 /* ldb $dr,@($sr) */
1741   {
1742     { 1, 1, 1, 1 },
1743     "ldb-2", "ldb", SYN (23), FMT (29), 0x2080,
1744     0,
1745     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1746   },
1747 /* ldb $dr,@($slo16,$sr) */
1748   {
1749     { 1, 1, 1, 1 },
1750     "ldb-d", "ldb", SYN (24), FMT (33), 0xa0800000,
1751     & fmt_33_ldb_d_ops[0],
1752     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1753   },
1754 /* ldb $dr,@($sr,$slo16) */
1755   {
1756     { 1, 1, 1, 1 },
1757     "ldb-d2", "ldb", SYN (25), FMT (31), 0xa0800000,
1758     0,
1759     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1760   },
1761 /* ldh $dr,@$sr */
1762   {
1763     { 1, 1, 1, 1 },
1764     "ldh", "ldh", SYN (22), FMT (34), 0x20a0,
1765     & fmt_34_ldh_ops[0],
1766     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1767   },
1768 /* ldh $dr,@($sr) */
1769   {
1770     { 1, 1, 1, 1 },
1771     "ldh-2", "ldh", SYN (23), FMT (29), 0x20a0,
1772     0,
1773     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1774   },
1775 /* ldh $dr,@($slo16,$sr) */
1776   {
1777     { 1, 1, 1, 1 },
1778     "ldh-d", "ldh", SYN (24), FMT (35), 0xa0a00000,
1779     & fmt_35_ldh_d_ops[0],
1780     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1781   },
1782 /* ldh $dr,@($sr,$slo16) */
1783   {
1784     { 1, 1, 1, 1 },
1785     "ldh-d2", "ldh", SYN (25), FMT (31), 0xa0a00000,
1786     0,
1787     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1788   },
1789 /* ldub $dr,@$sr */
1790   {
1791     { 1, 1, 1, 1 },
1792     "ldub", "ldub", SYN (22), FMT (32), 0x2090,
1793     & fmt_32_ldb_ops[0],
1794     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1795   },
1796 /* ldub $dr,@($sr) */
1797   {
1798     { 1, 1, 1, 1 },
1799     "ldub-2", "ldub", SYN (23), FMT (29), 0x2090,
1800     0,
1801     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1802   },
1803 /* ldub $dr,@($slo16,$sr) */
1804   {
1805     { 1, 1, 1, 1 },
1806     "ldub-d", "ldub", SYN (24), FMT (33), 0xa0900000,
1807     & fmt_33_ldb_d_ops[0],
1808     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1809   },
1810 /* ldub $dr,@($sr,$slo16) */
1811   {
1812     { 1, 1, 1, 1 },
1813     "ldub-d2", "ldub", SYN (25), FMT (31), 0xa0900000,
1814     0,
1815     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1816   },
1817 /* lduh $dr,@$sr */
1818   {
1819     { 1, 1, 1, 1 },
1820     "lduh", "lduh", SYN (22), FMT (34), 0x20b0,
1821     & fmt_34_ldh_ops[0],
1822     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1823   },
1824 /* lduh $dr,@($sr) */
1825   {
1826     { 1, 1, 1, 1 },
1827     "lduh-2", "lduh", SYN (23), FMT (29), 0x20b0,
1828     0,
1829     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1830   },
1831 /* lduh $dr,@($slo16,$sr) */
1832   {
1833     { 1, 1, 1, 1 },
1834     "lduh-d", "lduh", SYN (24), FMT (35), 0xa0b00000,
1835     & fmt_35_ldh_d_ops[0],
1836     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1837   },
1838 /* lduh $dr,@($sr,$slo16) */
1839   {
1840     { 1, 1, 1, 1 },
1841     "lduh-d2", "lduh", SYN (25), FMT (31), 0xa0b00000,
1842     0,
1843     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1844   },
1845 /* ld $dr,@$sr+ */
1846   {
1847     { 1, 1, 1, 1 },
1848     "ld-plus", "ld", SYN (26), FMT (36), 0x20e0,
1849     & fmt_36_ld_plus_ops[0],
1850     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1851   },
1852 /* ld24 $dr,#$uimm24 */
1853   {
1854     { 1, 1, 1, 1 },
1855     "ld24", "ld24", SYN (27), FMT (37), 0xe0000000,
1856     & fmt_37_ld24_ops[0],
1857     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1858   },
1859 /* ld24 $dr,$uimm24 */
1860   {
1861     { 1, 1, 1, 1 },
1862     "ld24.a", "ld24", SYN (28), FMT (37), 0xe0000000,
1863     & fmt_37_ld24_ops[0],
1864     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1865   },
1866 /* ldi $dr,#$simm8 */
1867   {
1868     { 1, 1, 1, 1 },
1869     "ldi8", "ldi", SYN (7), FMT (38), 0x6000,
1870     & fmt_38_ldi8_ops[0],
1871     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1872   },
1873 /* ldi $dr,$simm8 */
1874   {
1875     { 1, 1, 1, 1 },
1876     "ldi8.a", "ldi", SYN (8), FMT (38), 0x6000,
1877     & fmt_38_ldi8_ops[0],
1878     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1879   },
1880 /* ldi8 $dr,#$simm8 */
1881   {
1882     { 1, 1, 1, 1 },
1883     "ldi8a", "ldi8", SYN (7), FMT (38), 0x6000,
1884     & fmt_38_ldi8_ops[0],
1885     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1886   },
1887 /* ldi8 $dr,$simm8 */
1888   {
1889     { 1, 1, 1, 1 },
1890     "ldi8a.a", "ldi8", SYN (8), FMT (38), 0x6000,
1891     & fmt_38_ldi8_ops[0],
1892     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1893   },
1894 /* ldi $dr,$slo16 */
1895   {
1896     { 1, 1, 1, 1 },
1897     "ldi16", "ldi", SYN (29), FMT (39), 0x90f00000,
1898     & fmt_39_ldi16_ops[0],
1899     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1900   },
1901 /* ldi16 $dr,$slo16 */
1902   {
1903     { 1, 1, 1, 1 },
1904     "ldi16a", "ldi16", SYN (29), FMT (39), 0x90f00000,
1905     & fmt_39_ldi16_ops[0],
1906     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1907   },
1908 /* lock $dr,@$sr */
1909   {
1910     { 1, 1, 1, 1 },
1911     "lock", "lock", SYN (22), FMT (40), 0x20d0,
1912     & fmt_40_lock_ops[0],
1913     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1914   },
1915 /* machi $src1,$src2 */
1916   {
1917     { 1, 1, 1, 1 },
1918     "machi", "machi", SYN (15), FMT (41), 0x3040,
1919     & fmt_41_machi_ops[0],
1920     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1921   },
1922 /* start-sanitize-m32rx */
1923 /* machi $src1,$src2,$acc */
1924   {
1925     { 1, 1, 1, 1 },
1926     "machi-a", "machi", SYN (30), FMT (42), 0x3040,
1927     & fmt_42_machi_a_ops[0],
1928     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1929   },
1930 /* end-sanitize-m32rx */
1931 /* maclo $src1,$src2 */
1932   {
1933     { 1, 1, 1, 1 },
1934     "maclo", "maclo", SYN (15), FMT (41), 0x3050,
1935     & fmt_41_machi_ops[0],
1936     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1937   },
1938 /* start-sanitize-m32rx */
1939 /* maclo $src1,$src2,$acc */
1940   {
1941     { 1, 1, 1, 1 },
1942     "maclo-a", "maclo", SYN (30), FMT (42), 0x3050,
1943     & fmt_42_machi_a_ops[0],
1944     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1945   },
1946 /* end-sanitize-m32rx */
1947 /* macwhi $src1,$src2 */
1948   {
1949     { 1, 1, 1, 1 },
1950     "macwhi", "macwhi", SYN (15), FMT (41), 0x3060,
1951     & fmt_41_machi_ops[0],
1952     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1953   },
1954 /* macwlo $src1,$src2 */
1955   {
1956     { 1, 1, 1, 1 },
1957     "macwlo", "macwlo", SYN (15), FMT (41), 0x3070,
1958     & fmt_41_machi_ops[0],
1959     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1960   },
1961 /* mul $dr,$sr */
1962   {
1963     { 1, 1, 1, 1 },
1964     "mul", "mul", SYN (0), FMT (0), 0x1060,
1965     & fmt_0_add_ops[0],
1966     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1967   },
1968 /* mulhi $src1,$src2 */
1969   {
1970     { 1, 1, 1, 1 },
1971     "mulhi", "mulhi", SYN (15), FMT (43), 0x3000,
1972     & fmt_43_mulhi_ops[0],
1973     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1974   },
1975 /* start-sanitize-m32rx */
1976 /* mulhi $src1,$src2,$acc */
1977   {
1978     { 1, 1, 1, 1 },
1979     "mulhi-a", "mulhi", SYN (30), FMT (44), 0x3000,
1980     & fmt_44_mulhi_a_ops[0],
1981     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1982   },
1983 /* end-sanitize-m32rx */
1984 /* mullo $src1,$src2 */
1985   {
1986     { 1, 1, 1, 1 },
1987     "mullo", "mullo", SYN (15), FMT (43), 0x3010,
1988     & fmt_43_mulhi_ops[0],
1989     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1990   },
1991 /* start-sanitize-m32rx */
1992 /* mullo $src1,$src2,$acc */
1993   {
1994     { 1, 1, 1, 1 },
1995     "mullo-a", "mullo", SYN (30), FMT (44), 0x3010,
1996     & fmt_44_mulhi_a_ops[0],
1997     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1998   },
1999 /* end-sanitize-m32rx */
2000 /* mulwhi $src1,$src2 */
2001   {
2002     { 1, 1, 1, 1 },
2003     "mulwhi", "mulwhi", SYN (15), FMT (43), 0x3020,
2004     & fmt_43_mulhi_ops[0],
2005     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2006   },
2007 /* mulwlo $src1,$src2 */
2008   {
2009     { 1, 1, 1, 1 },
2010     "mulwlo", "mulwlo", SYN (15), FMT (43), 0x3030,
2011     & fmt_43_mulhi_ops[0],
2012     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2013   },
2014 /* mv $dr,$sr */
2015   {
2016     { 1, 1, 1, 1 },
2017     "mv", "mv", SYN (0), FMT (45), 0x1080,
2018     & fmt_45_mv_ops[0],
2019     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2020   },
2021 /* mvfachi $dr */
2022   {
2023     { 1, 1, 1, 1 },
2024     "mvfachi", "mvfachi", SYN (31), FMT (46), 0x50f0,
2025     & fmt_46_mvfachi_ops[0],
2026     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2027   },
2028 /* start-sanitize-m32rx */
2029 /* mvfachi $dr,$accs */
2030   {
2031     { 1, 1, 1, 1 },
2032     "mvfachi-a", "mvfachi", SYN (32), FMT (47), 0x50f0,
2033     & fmt_47_mvfachi_a_ops[0],
2034     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2035   },
2036 /* end-sanitize-m32rx */
2037 /* mvfaclo $dr */
2038   {
2039     { 1, 1, 1, 1 },
2040     "mvfaclo", "mvfaclo", SYN (31), FMT (46), 0x50f1,
2041     & fmt_46_mvfachi_ops[0],
2042     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2043   },
2044 /* start-sanitize-m32rx */
2045 /* mvfaclo $dr,$accs */
2046   {
2047     { 1, 1, 1, 1 },
2048     "mvfaclo-a", "mvfaclo", SYN (32), FMT (47), 0x50f1,
2049     & fmt_47_mvfachi_a_ops[0],
2050     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2051   },
2052 /* end-sanitize-m32rx */
2053 /* mvfacmi $dr */
2054   {
2055     { 1, 1, 1, 1 },
2056     "mvfacmi", "mvfacmi", SYN (31), FMT (46), 0x50f2,
2057     & fmt_46_mvfachi_ops[0],
2058     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2059   },
2060 /* start-sanitize-m32rx */
2061 /* mvfacmi $dr,$accs */
2062   {
2063     { 1, 1, 1, 1 },
2064     "mvfacmi-a", "mvfacmi", SYN (32), FMT (47), 0x50f2,
2065     & fmt_47_mvfachi_a_ops[0],
2066     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2067   },
2068 /* end-sanitize-m32rx */
2069 /* mvfc $dr,$scr */
2070   {
2071     { 1, 1, 1, 1 },
2072     "mvfc", "mvfc", SYN (33), FMT (48), 0x1090,
2073     & fmt_48_mvfc_ops[0],
2074     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2075   },
2076 /* mvtachi $src1 */
2077   {
2078     { 1, 1, 1, 1 },
2079     "mvtachi", "mvtachi", SYN (34), FMT (49), 0x5070,
2080     & fmt_49_mvtachi_ops[0],
2081     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2082   },
2083 /* start-sanitize-m32rx */
2084 /* mvtachi $src1,$accs */
2085   {
2086     { 1, 1, 1, 1 },
2087     "mvtachi-a", "mvtachi", SYN (35), FMT (50), 0x5070,
2088     & fmt_50_mvtachi_a_ops[0],
2089     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2090   },
2091 /* end-sanitize-m32rx */
2092 /* mvtaclo $src1 */
2093   {
2094     { 1, 1, 1, 1 },
2095     "mvtaclo", "mvtaclo", SYN (34), FMT (49), 0x5071,
2096     & fmt_49_mvtachi_ops[0],
2097     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2098   },
2099 /* start-sanitize-m32rx */
2100 /* mvtaclo $src1,$accs */
2101   {
2102     { 1, 1, 1, 1 },
2103     "mvtaclo-a", "mvtaclo", SYN (35), FMT (50), 0x5071,
2104     & fmt_50_mvtachi_a_ops[0],
2105     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2106   },
2107 /* end-sanitize-m32rx */
2108 /* mvtc $sr,$dcr */
2109   {
2110     { 1, 1, 1, 1 },
2111     "mvtc", "mvtc", SYN (36), FMT (51), 0x10a0,
2112     & fmt_51_mvtc_ops[0],
2113     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2114   },
2115 /* neg $dr,$sr */
2116   {
2117     { 1, 1, 1, 1 },
2118     "neg", "neg", SYN (0), FMT (45), 0x30,
2119     & fmt_45_mv_ops[0],
2120     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2121   },
2122 /* nop */
2123   {
2124     { 1, 1, 1, 1 },
2125     "nop", "nop", SYN (37), FMT (52), 0x7000,
2126     0,
2127     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2128   },
2129 /* not $dr,$sr */
2130   {
2131     { 1, 1, 1, 1 },
2132     "not", "not", SYN (0), FMT (45), 0xb0,
2133     & fmt_45_mv_ops[0],
2134     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2135   },
2136 /* rac */
2137   {
2138     { 1, 1, 1, 1 },
2139     "rac", "rac", SYN (37), FMT (53), 0x5090,
2140     & fmt_53_rac_ops[0],
2141     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2142   },
2143 /* start-sanitize-m32rx */
2144 /* rac $accd */
2145   {
2146     { 1, 1, 1, 1 },
2147     "rac-d", "rac", SYN (38), FMT (54), 0x5090,
2148     0,
2149     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2150   },
2151 /* end-sanitize-m32rx */
2152 /* start-sanitize-m32rx */
2153 /* rac $accd,$accs */
2154   {
2155     { 1, 1, 1, 1 },
2156     "rac-ds", "rac", SYN (39), FMT (55), 0x5090,
2157     0,
2158     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2159   },
2160 /* end-sanitize-m32rx */
2161 /* start-sanitize-m32rx */
2162 /* rac $accd,$accs,#$imm1 */
2163   {
2164     { 1, 1, 1, 1 },
2165     "rac-dsi", "rac", SYN (40), FMT (56), 0x5090,
2166     & fmt_56_rac_dsi_ops[0],
2167     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2168   },
2169 /* end-sanitize-m32rx */
2170 /* rach */
2171   {
2172     { 1, 1, 1, 1 },
2173     "rach", "rach", SYN (37), FMT (53), 0x5080,
2174     & fmt_53_rac_ops[0],
2175     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2176   },
2177 /* start-sanitize-m32rx */
2178 /* rach $accd */
2179   {
2180     { 1, 1, 1, 1 },
2181     "rach-d", "rach", SYN (38), FMT (54), 0x5080,
2182     0,
2183     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2184   },
2185 /* end-sanitize-m32rx */
2186 /* start-sanitize-m32rx */
2187 /* rach $accd,$accs */
2188   {
2189     { 1, 1, 1, 1 },
2190     "rach-ds", "rach", SYN (39), FMT (55), 0x5080,
2191     0,
2192     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2193   },
2194 /* end-sanitize-m32rx */
2195 /* start-sanitize-m32rx */
2196 /* rach $accd,$accs,#$imm1 */
2197   {
2198     { 1, 1, 1, 1 },
2199     "rach-dsi", "rach", SYN (40), FMT (56), 0x5080,
2200     & fmt_56_rac_dsi_ops[0],
2201     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2202   },
2203 /* end-sanitize-m32rx */
2204 /* rte */
2205   {
2206     { 1, 1, 1, 1 },
2207     "rte", "rte", SYN (37), FMT (57), 0x10d6,
2208     & fmt_57_rte_ops[0],
2209     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2210   },
2211 /* seth $dr,#$hi16 */
2212   {
2213     { 1, 1, 1, 1 },
2214     "seth", "seth", SYN (41), FMT (58), 0xd0c00000,
2215     & fmt_58_seth_ops[0],
2216     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2217   },
2218 /* seth $dr,$hi16 */
2219   {
2220     { 1, 1, 1, 1 },
2221     "seth.a", "seth", SYN (42), FMT (58), 0xd0c00000,
2222     & fmt_58_seth_ops[0],
2223     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2224   },
2225 /* sll $dr,$sr */
2226   {
2227     { 1, 1, 1, 1 },
2228     "sll", "sll", SYN (0), FMT (0), 0x1040,
2229     & fmt_0_add_ops[0],
2230     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2231   },
2232 /* sll3 $dr,$sr,#$simm16 */
2233   {
2234     { 1, 1, 1, 1 },
2235     "sll3", "sll3", SYN (9), FMT (59), 0x90c00000,
2236     & fmt_59_sll3_ops[0],
2237     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2238   },
2239 /* sll3 $dr,$sr,$simm16 */
2240   {
2241     { 1, 1, 1, 1 },
2242     "sll3.a", "sll3", SYN (10), FMT (59), 0x90c00000,
2243     & fmt_59_sll3_ops[0],
2244     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2245   },
2246 /* slli $dr,#$uimm5 */
2247   {
2248     { 1, 1, 1, 1 },
2249     "slli", "slli", SYN (43), FMT (60), 0x5040,
2250     & fmt_60_slli_ops[0],
2251     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2252   },
2253 /* slli $dr,$uimm5 */
2254   {
2255     { 1, 1, 1, 1 },
2256     "slli.a", "slli", SYN (44), FMT (60), 0x5040,
2257     & fmt_60_slli_ops[0],
2258     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2259   },
2260 /* sra $dr,$sr */
2261   {
2262     { 1, 1, 1, 1 },
2263     "sra", "sra", SYN (0), FMT (0), 0x1020,
2264     & fmt_0_add_ops[0],
2265     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2266   },
2267 /* sra3 $dr,$sr,#$simm16 */
2268   {
2269     { 1, 1, 1, 1 },
2270     "sra3", "sra3", SYN (9), FMT (59), 0x90a00000,
2271     & fmt_59_sll3_ops[0],
2272     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2273   },
2274 /* sra3 $dr,$sr,$simm16 */
2275   {
2276     { 1, 1, 1, 1 },
2277     "sra3.a", "sra3", SYN (10), FMT (59), 0x90a00000,
2278     & fmt_59_sll3_ops[0],
2279     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2280   },
2281 /* srai $dr,#$uimm5 */
2282   {
2283     { 1, 1, 1, 1 },
2284     "srai", "srai", SYN (43), FMT (60), 0x5020,
2285     & fmt_60_slli_ops[0],
2286     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2287   },
2288 /* srai $dr,$uimm5 */
2289   {
2290     { 1, 1, 1, 1 },
2291     "srai.a", "srai", SYN (44), FMT (60), 0x5020,
2292     & fmt_60_slli_ops[0],
2293     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2294   },
2295 /* srl $dr,$sr */
2296   {
2297     { 1, 1, 1, 1 },
2298     "srl", "srl", SYN (0), FMT (0), 0x1000,
2299     & fmt_0_add_ops[0],
2300     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2301   },
2302 /* srl3 $dr,$sr,#$simm16 */
2303   {
2304     { 1, 1, 1, 1 },
2305     "srl3", "srl3", SYN (9), FMT (59), 0x90800000,
2306     & fmt_59_sll3_ops[0],
2307     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2308   },
2309 /* srl3 $dr,$sr,$simm16 */
2310   {
2311     { 1, 1, 1, 1 },
2312     "srl3.a", "srl3", SYN (10), FMT (59), 0x90800000,
2313     & fmt_59_sll3_ops[0],
2314     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2315   },
2316 /* srli $dr,#$uimm5 */
2317   {
2318     { 1, 1, 1, 1 },
2319     "srli", "srli", SYN (43), FMT (60), 0x5000,
2320     & fmt_60_slli_ops[0],
2321     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2322   },
2323 /* srli $dr,$uimm5 */
2324   {
2325     { 1, 1, 1, 1 },
2326     "srli.a", "srli", SYN (44), FMT (60), 0x5000,
2327     & fmt_60_slli_ops[0],
2328     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2329   },
2330 /* st $src1,@$src2 */
2331   {
2332     { 1, 1, 1, 1 },
2333     "st", "st", SYN (45), FMT (61), 0x2040,
2334     & fmt_61_st_ops[0],
2335     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2336   },
2337 /* st $src1,@($src2) */
2338   {
2339     { 1, 1, 1, 1 },
2340     "st-2", "st", SYN (46), FMT (62), 0x2040,
2341     0,
2342     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2343   },
2344 /* st $src1,@($slo16,$src2) */
2345   {
2346     { 1, 1, 1, 1 },
2347     "st-d", "st", SYN (47), FMT (63), 0xa0400000,
2348     & fmt_63_st_d_ops[0],
2349     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2350   },
2351 /* st $src1,@($src2,$slo16) */
2352   {
2353     { 1, 1, 1, 1 },
2354     "st-d2", "st", SYN (48), FMT (64), 0xa0400000,
2355     0,
2356     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2357   },
2358 /* stb $src1,@$src2 */
2359   {
2360     { 1, 1, 1, 1 },
2361     "stb", "stb", SYN (45), FMT (65), 0x2000,
2362     & fmt_65_stb_ops[0],
2363     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2364   },
2365 /* stb $src1,@($src2) */
2366   {
2367     { 1, 1, 1, 1 },
2368     "stb-2", "stb", SYN (46), FMT (62), 0x2000,
2369     0,
2370     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2371   },
2372 /* stb $src1,@($slo16,$src2) */
2373   {
2374     { 1, 1, 1, 1 },
2375     "stb-d", "stb", SYN (47), FMT (66), 0xa0000000,
2376     & fmt_66_stb_d_ops[0],
2377     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2378   },
2379 /* stb $src1,@($src2,$slo16) */
2380   {
2381     { 1, 1, 1, 1 },
2382     "stb-d2", "stb", SYN (48), FMT (64), 0xa0000000,
2383     0,
2384     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2385   },
2386 /* sth $src1,@$src2 */
2387   {
2388     { 1, 1, 1, 1 },
2389     "sth", "sth", SYN (45), FMT (67), 0x2020,
2390     & fmt_67_sth_ops[0],
2391     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2392   },
2393 /* sth $src1,@($src2) */
2394   {
2395     { 1, 1, 1, 1 },
2396     "sth-2", "sth", SYN (46), FMT (62), 0x2020,
2397     0,
2398     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2399   },
2400 /* sth $src1,@($slo16,$src2) */
2401   {
2402     { 1, 1, 1, 1 },
2403     "sth-d", "sth", SYN (47), FMT (68), 0xa0200000,
2404     & fmt_68_sth_d_ops[0],
2405     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2406   },
2407 /* sth $src1,@($src2,$slo16) */
2408   {
2409     { 1, 1, 1, 1 },
2410     "sth-d2", "sth", SYN (48), FMT (64), 0xa0200000,
2411     0,
2412     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2413   },
2414 /* st $src1,@+$src2 */
2415   {
2416     { 1, 1, 1, 1 },
2417     "st-plus", "st", SYN (49), FMT (69), 0x2060,
2418     & fmt_69_st_plus_ops[0],
2419     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2420   },
2421 /* st $src1,@-$src2 */
2422   {
2423     { 1, 1, 1, 1 },
2424     "st-minus", "st", SYN (50), FMT (69), 0x2070,
2425     & fmt_69_st_plus_ops[0],
2426     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2427   },
2428 /* sub $dr,$sr */
2429   {
2430     { 1, 1, 1, 1 },
2431     "sub", "sub", SYN (0), FMT (0), 0x20,
2432     & fmt_0_add_ops[0],
2433     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2434   },
2435 /* subv $dr,$sr */
2436   {
2437     { 1, 1, 1, 1 },
2438     "subv", "subv", SYN (0), FMT (5), 0x0,
2439     & fmt_5_addv_ops[0],
2440     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2441   },
2442 /* subx $dr,$sr */
2443   {
2444     { 1, 1, 1, 1 },
2445     "subx", "subx", SYN (0), FMT (7), 0x10,
2446     & fmt_7_addx_ops[0],
2447     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2448   },
2449 /* trap #$uimm4 */
2450   {
2451     { 1, 1, 1, 1 },
2452     "trap", "trap", SYN (51), FMT (70), 0x10f0,
2453     & fmt_70_trap_ops[0],
2454     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2455   },
2456 /* trap $uimm4 */
2457   {
2458     { 1, 1, 1, 1 },
2459     "trap.a", "trap", SYN (52), FMT (71), 0x10f0,
2460     0,
2461     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2462   },
2463 /* unlock $src1,@$src2 */
2464   {
2465     { 1, 1, 1, 1 },
2466     "unlock", "unlock", SYN (45), FMT (72), 0x2050,
2467     & fmt_72_unlock_ops[0],
2468     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2469   },
2470 /* push $src1 */
2471   {
2472     { 1, 1, 1, 1 },
2473     "push", "push", SYN (34), FMT (73), 0x207f,
2474     0,
2475     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2476   },
2477 /* pop $dr */
2478   {
2479     { 1, 1, 1, 1 },
2480     "pop", "pop", SYN (31), FMT (74), 0x20ef,
2481     0,
2482     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2483   },
2484 /* start-sanitize-m32rx */
2485 /* satb $dr,$sr */
2486   {
2487     { 1, 1, 1, 1 },
2488     "satb", "satb", SYN (0), FMT (75), 0x80000100,
2489     & fmt_75_satb_ops[0],
2490     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2491   },
2492 /* end-sanitize-m32rx */
2493 /* start-sanitize-m32rx */
2494 /* sath $dr,$sr */
2495   {
2496     { 1, 1, 1, 1 },
2497     "sath", "sath", SYN (0), FMT (75), 0x80000200,
2498     & fmt_75_satb_ops[0],
2499     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2500   },
2501 /* end-sanitize-m32rx */
2502 /* start-sanitize-m32rx */
2503 /* sat $dr,$sr */
2504   {
2505     { 1, 1, 1, 1 },
2506     "sat", "sat", SYN (0), FMT (76), 0x80000000,
2507     & fmt_76_sat_ops[0],
2508     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2509   },
2510 /* end-sanitize-m32rx */
2511 /* start-sanitize-m32rx */
2512 /* pcmpbz $src2 */
2513   {
2514     { 1, 1, 1, 1 },
2515     "pcmpbz", "pcmpbz", SYN (20), FMT (23), 0x370,
2516     & fmt_23_cmpz_ops[0],
2517     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
2518   },
2519 /* end-sanitize-m32rx */
2520 /* start-sanitize-m32rx */
2521 /* sadd */
2522   {
2523     { 1, 1, 1, 1 },
2524     "sadd", "sadd", SYN (37), FMT (77), 0x50e4,
2525     & fmt_77_sadd_ops[0],
2526     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2527   },
2528 /* end-sanitize-m32rx */
2529 /* start-sanitize-m32rx */
2530 /* macwu1 $src1,$src2 */
2531   {
2532     { 1, 1, 1, 1 },
2533     "macwu1", "macwu1", SYN (15), FMT (78), 0x50b0,
2534     & fmt_78_macwu1_ops[0],
2535     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2536   },
2537 /* end-sanitize-m32rx */
2538 /* start-sanitize-m32rx */
2539 /* msblo $src1,$src2 */
2540   {
2541     { 1, 1, 1, 1 },
2542     "msblo", "msblo", SYN (15), FMT (41), 0x50d0,
2543     & fmt_41_machi_ops[0],
2544     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2545   },
2546 /* end-sanitize-m32rx */
2547 /* start-sanitize-m32rx */
2548 /* mulwu1 $src1,$src2 */
2549   {
2550     { 1, 1, 1, 1 },
2551     "mulwu1", "mulwu1", SYN (15), FMT (79), 0x50a0,
2552     & fmt_79_mulwu1_ops[0],
2553     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2554   },
2555 /* end-sanitize-m32rx */
2556 /* start-sanitize-m32rx */
2557 /* maclh1 $src1,$src2 */
2558   {
2559     { 1, 1, 1, 1 },
2560     "maclh1", "maclh1", SYN (15), FMT (78), 0x50c0,
2561     & fmt_78_macwu1_ops[0],
2562     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2563   },
2564 /* end-sanitize-m32rx */
2565 /* start-sanitize-m32rx */
2566 /* sc */
2567   {
2568     { 1, 1, 1, 1 },
2569     "sc", "sc", SYN (37), FMT (80), 0x7401,
2570     & fmt_80_sc_ops[0],
2571     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2572   },
2573 /* end-sanitize-m32rx */
2574 /* start-sanitize-m32rx */
2575 /* snc */
2576   {
2577     { 1, 1, 1, 1 },
2578     "snc", "snc", SYN (37), FMT (80), 0x7501,
2579     & fmt_80_sc_ops[0],
2580     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2581   },
2582 /* end-sanitize-m32rx */
2583 };
2584
2585 #undef A
2586 #undef SYN
2587 #undef FMT
2588
2589 CGEN_INSN_TABLE m32r_cgen_insn_table =
2590 {
2591   & m32r_cgen_insn_table_entries[0],
2592   sizeof (CGEN_INSN),
2593   MAX_INSNS,
2594   NULL,
2595   m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
2596   m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
2597 };
2598
2599 /* The hash functions are recorded here to help keep assembler code out of
2600    the disassembler and vice versa.  */
2601
2602 unsigned int
2603 m32r_cgen_asm_hash_insn (insn)
2604      const char * insn;
2605 {
2606   return CGEN_ASM_HASH (insn);
2607 }
2608
2609 unsigned int
2610 m32r_cgen_dis_hash_insn (buf, value)
2611      const char * buf;
2612      unsigned long value;
2613 {
2614   return CGEN_DIS_HASH (buf, value);
2615 }
2616
2617 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
2618 {
2619   & m32r_cgen_hw_entries[0],
2620   & m32r_cgen_insn_table,
2621 };
2622
2623 void
2624 m32r_cgen_init_tables (mach)
2625     int mach;
2626 {
2627 }
2628
2629 /* Main entry point for stuffing values in cgen_fields.  */
2630
2631 CGEN_INLINE void
2632 m32r_cgen_set_operand (opindex, valuep, fields)
2633      int opindex;
2634      const long * valuep;
2635      CGEN_FIELDS * fields;
2636 {
2637   switch (opindex)
2638     {
2639     case M32R_OPERAND_SR :
2640       fields->f_r2 = * valuep;
2641       break;
2642     case M32R_OPERAND_DR :
2643       fields->f_r1 = * valuep;
2644       break;
2645     case M32R_OPERAND_SRC1 :
2646       fields->f_r1 = * valuep;
2647       break;
2648     case M32R_OPERAND_SRC2 :
2649       fields->f_r2 = * valuep;
2650       break;
2651     case M32R_OPERAND_SCR :
2652       fields->f_r2 = * valuep;
2653       break;
2654     case M32R_OPERAND_DCR :
2655       fields->f_r1 = * valuep;
2656       break;
2657     case M32R_OPERAND_SIMM8 :
2658       fields->f_simm8 = * valuep;
2659       break;
2660     case M32R_OPERAND_SIMM16 :
2661       fields->f_simm16 = * valuep;
2662       break;
2663     case M32R_OPERAND_UIMM4 :
2664       fields->f_uimm4 = * valuep;
2665       break;
2666     case M32R_OPERAND_UIMM5 :
2667       fields->f_uimm5 = * valuep;
2668       break;
2669     case M32R_OPERAND_UIMM16 :
2670       fields->f_uimm16 = * valuep;
2671       break;
2672 /* start-sanitize-m32rx */
2673     case M32R_OPERAND_IMM1 :
2674       fields->f_imm1 = * valuep;
2675       break;
2676 /* end-sanitize-m32rx */
2677 /* start-sanitize-m32rx */
2678     case M32R_OPERAND_ACCD :
2679       fields->f_accd = * valuep;
2680       break;
2681 /* end-sanitize-m32rx */
2682 /* start-sanitize-m32rx */
2683     case M32R_OPERAND_ACCS :
2684       fields->f_accs = * valuep;
2685       break;
2686 /* end-sanitize-m32rx */
2687 /* start-sanitize-m32rx */
2688     case M32R_OPERAND_ACC :
2689       fields->f_acc = * valuep;
2690       break;
2691 /* end-sanitize-m32rx */
2692     case M32R_OPERAND_HI16 :
2693       fields->f_hi16 = * valuep;
2694       break;
2695     case M32R_OPERAND_SLO16 :
2696       fields->f_simm16 = * valuep;
2697       break;
2698     case M32R_OPERAND_ULO16 :
2699       fields->f_uimm16 = * valuep;
2700       break;
2701     case M32R_OPERAND_UIMM24 :
2702       fields->f_uimm24 = * valuep;
2703       break;
2704     case M32R_OPERAND_DISP8 :
2705       fields->f_disp8 = * valuep;
2706       break;
2707     case M32R_OPERAND_DISP16 :
2708       fields->f_disp16 = * valuep;
2709       break;
2710     case M32R_OPERAND_DISP24 :
2711       fields->f_disp24 = * valuep;
2712       break;
2713
2714     default :
2715       fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2716                        opindex);
2717       abort ();
2718   }
2719 }
2720
2721 /* Main entry point for getting values from cgen_fields.  */
2722
2723 CGEN_INLINE long
2724 m32r_cgen_get_operand (opindex, fields)
2725      int opindex;
2726      const CGEN_FIELDS * fields;
2727 {
2728   long value;
2729
2730   switch (opindex)
2731     {
2732     case M32R_OPERAND_SR :
2733       value = fields->f_r2;
2734       break;
2735     case M32R_OPERAND_DR :
2736       value = fields->f_r1;
2737       break;
2738     case M32R_OPERAND_SRC1 :
2739       value = fields->f_r1;
2740       break;
2741     case M32R_OPERAND_SRC2 :
2742       value = fields->f_r2;
2743       break;
2744     case M32R_OPERAND_SCR :
2745       value = fields->f_r2;
2746       break;
2747     case M32R_OPERAND_DCR :
2748       value = fields->f_r1;
2749       break;
2750     case M32R_OPERAND_SIMM8 :
2751       value = fields->f_simm8;
2752       break;
2753     case M32R_OPERAND_SIMM16 :
2754       value = fields->f_simm16;
2755       break;
2756     case M32R_OPERAND_UIMM4 :
2757       value = fields->f_uimm4;
2758       break;
2759     case M32R_OPERAND_UIMM5 :
2760       value = fields->f_uimm5;
2761       break;
2762     case M32R_OPERAND_UIMM16 :
2763       value = fields->f_uimm16;
2764       break;
2765 /* start-sanitize-m32rx */
2766     case M32R_OPERAND_IMM1 :
2767       value = fields->f_imm1;
2768       break;
2769 /* end-sanitize-m32rx */
2770 /* start-sanitize-m32rx */
2771     case M32R_OPERAND_ACCD :
2772       value = fields->f_accd;
2773       break;
2774 /* end-sanitize-m32rx */
2775 /* start-sanitize-m32rx */
2776     case M32R_OPERAND_ACCS :
2777       value = fields->f_accs;
2778       break;
2779 /* end-sanitize-m32rx */
2780 /* start-sanitize-m32rx */
2781     case M32R_OPERAND_ACC :
2782       value = fields->f_acc;
2783       break;
2784 /* end-sanitize-m32rx */
2785     case M32R_OPERAND_HI16 :
2786       value = fields->f_hi16;
2787       break;
2788     case M32R_OPERAND_SLO16 :
2789       value = fields->f_simm16;
2790       break;
2791     case M32R_OPERAND_ULO16 :
2792       value = fields->f_uimm16;
2793       break;
2794     case M32R_OPERAND_UIMM24 :
2795       value = fields->f_uimm24;
2796       break;
2797     case M32R_OPERAND_DISP8 :
2798       value = fields->f_disp8;
2799       break;
2800     case M32R_OPERAND_DISP16 :
2801       value = fields->f_disp16;
2802       break;
2803     case M32R_OPERAND_DISP24 :
2804       value = fields->f_disp24;
2805       break;
2806
2807     default :
2808       fprintf (stderr, "Unrecognized field %d while getting operand.\n",
2809                        opindex);
2810       abort ();
2811   }
2812
2813   return value;
2814 }
2815