opcodes/mep-desc.c

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* CPU data for mep.
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5
   6 Copyright (C) 1996-2022 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   9
  10    This file is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3, or (at your option)
  13    any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with this program; if not, write to the Free Software Foundation, Inc.,
  22    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include "sysdep.h"
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include <stdlib.h>
  30 #include "ansidecl.h"
  31 #include "bfd.h"
  32 #include "symcat.h"
  33 #include "mep-desc.h"
  34 #include "mep-opc.h"
  35 #include "opintl.h"
  36 #include "libiberty.h"
  37 #include "xregex.h"
  38
  39 /* Attributes.  */
  40
  41 static const CGEN_ATTR_ENTRY bool_attr[] =
  42 {
  43   { "#f", 0 },
  44   { "#t", 1 },
  45   { 0, 0 }
  46 };
  47
  48 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  49 {
  50   { "base", MACH_BASE },
  51   { "mep", MACH_MEP },
  52   { "h1", MACH_H1 },
  53   { "c5", MACH_C5 },
  54   { "max", MACH_MAX },
  55   { 0, 0 }
  56 };
  57
  58 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  59 {
  60   { "mep", ISA_MEP },
  61   { "ext_core1", ISA_EXT_CORE1 },
  62   { "ext_cop1_16", ISA_EXT_COP1_16 },
  63   { "ext_cop1_32", ISA_EXT_COP1_32 },
  64   { "ext_cop1_48", ISA_EXT_COP1_48 },
  65   { "ext_cop1_64", ISA_EXT_COP1_64 },
  66   { "max", ISA_MAX },
  67   { 0, 0 }
  68 };
  69
  70 static const CGEN_ATTR_ENTRY CDATA_attr[] ATTRIBUTE_UNUSED =
  71 {
  72   { "LABEL", CDATA_LABEL },
  73   { "REGNUM", CDATA_REGNUM },
  74   { "FMAX_FLOAT", CDATA_FMAX_FLOAT },
  75   { "FMAX_INT", CDATA_FMAX_INT },
  76   { "POINTER", CDATA_POINTER },
  77   { "LONG", CDATA_LONG },
  78   { "ULONG", CDATA_ULONG },
  79   { "SHORT", CDATA_SHORT },
  80   { "USHORT", CDATA_USHORT },
  81   { "CHAR", CDATA_CHAR },
  82   { "UCHAR", CDATA_UCHAR },
  83   { "CP_DATA_BUS_INT", CDATA_CP_DATA_BUS_INT },
  84   { 0, 0 }
  85 };
  86
  87 static const CGEN_ATTR_ENTRY CPTYPE_attr[] ATTRIBUTE_UNUSED =
  88 {
  89   { "CP_DATA_BUS_INT", CPTYPE_CP_DATA_BUS_INT },
  90   { "VECT", CPTYPE_VECT },
  91   { "V2SI", CPTYPE_V2SI },
  92   { "V4HI", CPTYPE_V4HI },
  93   { "V8QI", CPTYPE_V8QI },
  94   { "V2USI", CPTYPE_V2USI },
  95   { "V4UHI", CPTYPE_V4UHI },
  96   { "V8UQI", CPTYPE_V8UQI },
  97   { 0, 0 }
  98 };
  99
 100 static const CGEN_ATTR_ENTRY CRET_attr[] ATTRIBUTE_UNUSED =
 101 {
 102   { "VOID", CRET_VOID },
 103   { "FIRST", CRET_FIRST },
 104   { "FIRSTCOPY", CRET_FIRSTCOPY },
 105   { 0, 0 }
 106 };
 107
 108 static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
 109 {
 110   {"integer", 1},
 111   { 0, 0 }
 112 };
 113
 114 static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
 115 {
 116   {"integer", 0},
 117   { 0, 0 }
 118 };
 119
 120 static const CGEN_ATTR_ENTRY CONFIG_attr[] ATTRIBUTE_UNUSED =
 121 {
 122   { "NONE", CONFIG_NONE },
 123   { "default", CONFIG_DEFAULT },
 124   { 0, 0 }
 125 };
 126
 127 static const CGEN_ATTR_ENTRY SLOTS_attr[] ATTRIBUTE_UNUSED =
 128 {
 129   { "CORE", SLOTS_CORE },
 130   { "C3", SLOTS_C3 },
 131   { "P0S", SLOTS_P0S },
 132   { "P0", SLOTS_P0 },
 133   { "P1", SLOTS_P1 },
 134   { 0, 0 }
 135 };
 136
 137 const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[] =
 138 {
 139   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 140   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 141   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 142   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 143   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 144   { "RESERVED", &bool_attr[0], &bool_attr[0] },
 145   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 146   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 147   { 0, 0, 0 }
 148 };
 149
 150 const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[] =
 151 {
 152   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 153   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 154   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 155   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
 156   { "PC", &bool_attr[0], &bool_attr[0] },
 157   { "PROFILE", &bool_attr[0], &bool_attr[0] },
 158   { "IS_FLOAT", &bool_attr[0], &bool_attr[0] },
 159   { 0, 0, 0 }
 160 };
 161
 162 const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[] =
 163 {
 164   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 165   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 166   { "CDATA", & CDATA_attr[0], & CDATA_attr[0] },
 167   { "ALIGN", & ALIGN_attr[0], & ALIGN_attr[0] },
 168   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 169   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 170   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 171   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 172   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 173   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 174   { "RELAX", &bool_attr[0], &bool_attr[0] },
 175   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 176   { "RELOC_IMPLIES_OVERFLOW", &bool_attr[0], &bool_attr[0] },
 177   { 0, 0, 0 }
 178 };
 179
 180 const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[] =
 181 {
 182   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 183   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 184   { "CPTYPE", & CPTYPE_attr[0], & CPTYPE_attr[0] },
 185   { "CRET", & CRET_attr[0], & CRET_attr[0] },
 186   { "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] },
 187   { "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] },
 188   { "SLOTS", & SLOTS_attr[0], & SLOTS_attr[0] },
 189   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 190   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 191   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 192   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 193   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 194   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 195   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 196   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 197   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 198   { "PBB", &bool_attr[0], &bool_attr[0] },
 199   { "OPTIONAL_BIT_INSN", &bool_attr[0], &bool_attr[0] },
 200   { "OPTIONAL_MUL_INSN", &bool_attr[0], &bool_attr[0] },
 201   { "OPTIONAL_DIV_INSN", &bool_attr[0], &bool_attr[0] },
 202   { "OPTIONAL_DEBUG_INSN", &bool_attr[0], &bool_attr[0] },
 203   { "OPTIONAL_LDZ_INSN", &bool_attr[0], &bool_attr[0] },
 204   { "OPTIONAL_ABS_INSN", &bool_attr[0], &bool_attr[0] },
 205   { "OPTIONAL_AVE_INSN", &bool_attr[0], &bool_attr[0] },
 206   { "OPTIONAL_MINMAX_INSN", &bool_attr[0], &bool_attr[0] },
 207   { "OPTIONAL_CLIP_INSN", &bool_attr[0], &bool_attr[0] },
 208   { "OPTIONAL_SAT_INSN", &bool_attr[0], &bool_attr[0] },
 209   { "OPTIONAL_UCI_INSN", &bool_attr[0], &bool_attr[0] },
 210   { "OPTIONAL_DSP_INSN", &bool_attr[0], &bool_attr[0] },
 211   { "OPTIONAL_CP_INSN", &bool_attr[0], &bool_attr[0] },
 212   { "OPTIONAL_CP64_INSN", &bool_attr[0], &bool_attr[0] },
 213   { "OPTIONAL_VLIW64", &bool_attr[0], &bool_attr[0] },
 214   { "MAY_TRAP", &bool_attr[0], &bool_attr[0] },
 215   { "VLIW_ALONE", &bool_attr[0], &bool_attr[0] },
 216   { "VLIW_NO_CORE_NOP", &bool_attr[0], &bool_attr[0] },
 217   { "VLIW_NO_COP_NOP", &bool_attr[0], &bool_attr[0] },
 218   { "VLIW64_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
 219   { "VLIW32_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
 220   { "VOLATILE", &bool_attr[0], &bool_attr[0] },
 221   { 0, 0, 0 }
 222 };
 223
 224 /* Instruction set variants.  */
 225
 226 static const CGEN_ISA mep_cgen_isa_table[] = {
 227   { "mep", 32, 32, 16, 32 },
 228   { "ext_core1", 32, 32, 16, 32 },
 229   { "ext_cop1_16", 32, 32, 32, 32 },
 230   { "ext_cop1_32", 32, 32, 32, 32 },
 231   { "ext_cop1_48", 32, 32, 32, 32 },
 232   { "ext_cop1_64", 32, 32, 32, 32 },
 233   { 0, 0, 0, 0, 0 }
 234 };
 235
 236 /* Machine variants.  */
 237
 238 static const CGEN_MACH mep_cgen_mach_table[] = {
 239   { "mep", "mep", MACH_MEP, 16 },
 240   { "h1", "h1", MACH_H1, 16 },
 241   { "c5", "c5", MACH_C5, 16 },
 242   { 0, 0, 0, 0 }
 243 };
 244
 245 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_gpr_entries[] =
 246 {
 247   { "$0", 0, {0, {{{0, 0}}}}, 0, 0 },
 248   { "$1", 1, {0, {{{0, 0}}}}, 0, 0 },
 249   { "$2", 2, {0, {{{0, 0}}}}, 0, 0 },
 250   { "$3", 3, {0, {{{0, 0}}}}, 0, 0 },
 251   { "$4", 4, {0, {{{0, 0}}}}, 0, 0 },
 252   { "$5", 5, {0, {{{0, 0}}}}, 0, 0 },
 253   { "$6", 6, {0, {{{0, 0}}}}, 0, 0 },
 254   { "$7", 7, {0, {{{0, 0}}}}, 0, 0 },
 255   { "$8", 8, {0, {{{0, 0}}}}, 0, 0 },
 256   { "$9", 9, {0, {{{0, 0}}}}, 0, 0 },
 257   { "$10", 10, {0, {{{0, 0}}}}, 0, 0 },
 258   { "$11", 11, {0, {{{0, 0}}}}, 0, 0 },
 259   { "$fp", 8, {0, {{{0, 0}}}}, 0, 0 },
 260   { "$tp", 13, {0, {{{0, 0}}}}, 0, 0 },
 261   { "$gp", 14, {0, {{{0, 0}}}}, 0, 0 },
 262   { "$sp", 15, {0, {{{0, 0}}}}, 0, 0 },
 263   { "$12", 12, {0, {{{0, 0}}}}, 0, 0 },
 264   { "$13", 13, {0, {{{0, 0}}}}, 0, 0 },
 265   { "$14", 14, {0, {{{0, 0}}}}, 0, 0 },
 266   { "$15", 15, {0, {{{0, 0}}}}, 0, 0 }
 267 };
 268
 269 CGEN_KEYWORD mep_cgen_opval_h_gpr =
 270 {
 271   & mep_cgen_opval_h_gpr_entries[0],
 272   20,
 273   0, 0, 0, 0, ""
 274 };
 275
 276 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_csr_entries[] =
 277 {
 278   { "$pc", 0, {0, {{{0, 0}}}}, 0, 0 },
 279   { "$lp", 1, {0, {{{0, 0}}}}, 0, 0 },
 280   { "$sar", 2, {0, {{{0, 0}}}}, 0, 0 },
 281   { "$rpb", 4, {0, {{{0, 0}}}}, 0, 0 },
 282   { "$rpe", 5, {0, {{{0, 0}}}}, 0, 0 },
 283   { "$rpc", 6, {0, {{{0, 0}}}}, 0, 0 },
 284   { "$hi", 7, {0, {{{0, 0}}}}, 0, 0 },
 285   { "$lo", 8, {0, {{{0, 0}}}}, 0, 0 },
 286   { "$mb0", 12, {0, {{{0, 0}}}}, 0, 0 },
 287   { "$me0", 13, {0, {{{0, 0}}}}, 0, 0 },
 288   { "$mb1", 14, {0, {{{0, 0}}}}, 0, 0 },
 289   { "$me1", 15, {0, {{{0, 0}}}}, 0, 0 },
 290   { "$psw", 16, {0, {{{0, 0}}}}, 0, 0 },
 291   { "$id", 17, {0, {{{0, 0}}}}, 0, 0 },
 292   { "$tmp", 18, {0, {{{0, 0}}}}, 0, 0 },
 293   { "$epc", 19, {0, {{{0, 0}}}}, 0, 0 },
 294   { "$exc", 20, {0, {{{0, 0}}}}, 0, 0 },
 295   { "$cfg", 21, {0, {{{0, 0}}}}, 0, 0 },
 296   { "$npc", 23, {0, {{{0, 0}}}}, 0, 0 },
 297   { "$dbg", 24, {0, {{{0, 0}}}}, 0, 0 },
 298   { "$depc", 25, {0, {{{0, 0}}}}, 0, 0 },
 299   { "$opt", 26, {0, {{{0, 0}}}}, 0, 0 },
 300   { "$rcfg", 27, {0, {{{0, 0}}}}, 0, 0 },
 301   { "$ccfg", 28, {0, {{{0, 0}}}}, 0, 0 },
 302   { "$vid", 22, {0, {{{0, 0}}}}, 0, 0 }
 303 };
 304
 305 CGEN_KEYWORD mep_cgen_opval_h_csr =
 306 {
 307   & mep_cgen_opval_h_csr_entries[0],
 308   25,
 309   0, 0, 0, 0, ""
 310 };
 311
 312 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr64_entries[] =
 313 {
 314   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
 315   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
 316   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
 317   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
 318   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
 319   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
 320   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
 321   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
 322   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
 323   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
 324   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
 325   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
 326   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
 327   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
 328   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
 329   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
 330   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
 331   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
 332   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
 333   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
 334   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
 335   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
 336   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
 337   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
 338   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
 339   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
 340   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
 341   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
 342   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
 343   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
 344   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
 345   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
 346 };
 347
 348 CGEN_KEYWORD mep_cgen_opval_h_cr64 =
 349 {
 350   & mep_cgen_opval_h_cr64_entries[0],
 351   32,
 352   0, 0, 0, 0, ""
 353 };
 354
 355 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_entries[] =
 356 {
 357   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
 358   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
 359   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
 360   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
 361   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
 362   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
 363   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
 364   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
 365   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
 366   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
 367   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
 368   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
 369   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
 370   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
 371   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
 372   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
 373   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
 374   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
 375   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
 376   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
 377   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
 378   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
 379   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
 380   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
 381   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
 382   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
 383   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
 384   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
 385   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
 386   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
 387   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
 388   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
 389 };
 390
 391 CGEN_KEYWORD mep_cgen_opval_h_cr =
 392 {
 393   & mep_cgen_opval_h_cr_entries[0],
 394   32,
 395   0, 0, 0, 0, ""
 396 };
 397
 398 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_entries[] =
 399 {
 400   { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
 401   { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
 402   { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
 403   { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
 404   { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
 405   { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
 406   { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
 407   { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
 408   { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
 409   { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
 410   { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
 411   { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
 412   { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
 413   { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
 414   { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
 415   { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
 416   { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
 417   { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
 418   { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
 419   { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
 420   { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
 421   { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
 422   { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
 423   { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
 424   { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
 425   { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
 426   { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
 427   { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
 428   { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
 429   { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
 430   { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
 431   { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 },
 432   { "$ccr32", 32, {0, {{{0, 0}}}}, 0, 0 },
 433   { "$ccr33", 33, {0, {{{0, 0}}}}, 0, 0 },
 434   { "$ccr34", 34, {0, {{{0, 0}}}}, 0, 0 },
 435   { "$ccr35", 35, {0, {{{0, 0}}}}, 0, 0 },
 436   { "$ccr36", 36, {0, {{{0, 0}}}}, 0, 0 },
 437   { "$ccr37", 37, {0, {{{0, 0}}}}, 0, 0 },
 438   { "$ccr38", 38, {0, {{{0, 0}}}}, 0, 0 },
 439   { "$ccr39", 39, {0, {{{0, 0}}}}, 0, 0 },
 440   { "$ccr40", 40, {0, {{{0, 0}}}}, 0, 0 },
 441   { "$ccr41", 41, {0, {{{0, 0}}}}, 0, 0 },
 442   { "$ccr42", 42, {0, {{{0, 0}}}}, 0, 0 },
 443   { "$ccr43", 43, {0, {{{0, 0}}}}, 0, 0 },
 444   { "$ccr44", 44, {0, {{{0, 0}}}}, 0, 0 },
 445   { "$ccr45", 45, {0, {{{0, 0}}}}, 0, 0 },
 446   { "$ccr46", 46, {0, {{{0, 0}}}}, 0, 0 },
 447   { "$ccr47", 47, {0, {{{0, 0}}}}, 0, 0 },
 448   { "$ccr48", 48, {0, {{{0, 0}}}}, 0, 0 },
 449   { "$ccr49", 49, {0, {{{0, 0}}}}, 0, 0 },
 450   { "$ccr50", 50, {0, {{{0, 0}}}}, 0, 0 },
 451   { "$ccr51", 51, {0, {{{0, 0}}}}, 0, 0 },
 452   { "$ccr52", 52, {0, {{{0, 0}}}}, 0, 0 },
 453   { "$ccr53", 53, {0, {{{0, 0}}}}, 0, 0 },
 454   { "$ccr54", 54, {0, {{{0, 0}}}}, 0, 0 },
 455   { "$ccr55", 55, {0, {{{0, 0}}}}, 0, 0 },
 456   { "$ccr56", 56, {0, {{{0, 0}}}}, 0, 0 },
 457   { "$ccr57", 57, {0, {{{0, 0}}}}, 0, 0 },
 458   { "$ccr58", 58, {0, {{{0, 0}}}}, 0, 0 },
 459   { "$ccr59", 59, {0, {{{0, 0}}}}, 0, 0 },
 460   { "$ccr60", 60, {0, {{{0, 0}}}}, 0, 0 },
 461   { "$ccr61", 61, {0, {{{0, 0}}}}, 0, 0 },
 462   { "$ccr62", 62, {0, {{{0, 0}}}}, 0, 0 },
 463   { "$ccr63", 63, {0, {{{0, 0}}}}, 0, 0 }
 464 };
 465
 466 CGEN_KEYWORD mep_cgen_opval_h_ccr =
 467 {
 468   & mep_cgen_opval_h_ccr_entries[0],
 469   64,
 470   0, 0, 0, 0, ""
 471 };
 472
 473 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_ivc2_entries[] =
 474 {
 475   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
 476   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
 477   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
 478   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
 479   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
 480   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
 481   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
 482   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 }
 483 };
 484
 485 CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2 =
 486 {
 487   & mep_cgen_opval_h_cr_ivc2_entries[0],
 488   8,
 489   0, 0, 0, 0, ""
 490 };
 491
 492 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_ivc2_entries[] =
 493 {
 494   { "$csar0", 0, {0, {{{0, 0}}}}, 0, 0 },
 495   { "$cc", 1, {0, {{{0, 0}}}}, 0, 0 },
 496   { "$cofr0", 4, {0, {{{0, 0}}}}, 0, 0 },
 497   { "$cofr1", 5, {0, {{{0, 0}}}}, 0, 0 },
 498   { "$cofa0", 6, {0, {{{0, 0}}}}, 0, 0 },
 499   { "$cofa1", 7, {0, {{{0, 0}}}}, 0, 0 },
 500   { "$csar1", 15, {0, {{{0, 0}}}}, 0, 0 },
 501   { "$acc0_0", 16, {0, {{{0, 0}}}}, 0, 0 },
 502   { "$acc0_1", 17, {0, {{{0, 0}}}}, 0, 0 },
 503   { "$acc0_2", 18, {0, {{{0, 0}}}}, 0, 0 },
 504   { "$acc0_3", 19, {0, {{{0, 0}}}}, 0, 0 },
 505   { "$acc0_4", 20, {0, {{{0, 0}}}}, 0, 0 },
 506   { "$acc0_5", 21, {0, {{{0, 0}}}}, 0, 0 },
 507   { "$acc0_6", 22, {0, {{{0, 0}}}}, 0, 0 },
 508   { "$acc0_7", 23, {0, {{{0, 0}}}}, 0, 0 },
 509   { "$acc1_0", 24, {0, {{{0, 0}}}}, 0, 0 },
 510   { "$acc1_1", 25, {0, {{{0, 0}}}}, 0, 0 },
 511   { "$acc1_2", 26, {0, {{{0, 0}}}}, 0, 0 },
 512   { "$acc1_3", 27, {0, {{{0, 0}}}}, 0, 0 },
 513   { "$acc1_4", 28, {0, {{{0, 0}}}}, 0, 0 },
 514   { "$acc1_5", 29, {0, {{{0, 0}}}}, 0, 0 },
 515   { "$acc1_6", 30, {0, {{{0, 0}}}}, 0, 0 },
 516   { "$acc1_7", 31, {0, {{{0, 0}}}}, 0, 0 },
 517   { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
 518   { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
 519   { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
 520   { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
 521   { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
 522   { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
 523   { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
 524   { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
 525   { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
 526   { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
 527   { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
 528   { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
 529   { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
 530   { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
 531   { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
 532   { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
 533   { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
 534   { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
 535   { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
 536   { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
 537   { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
 538   { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
 539   { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
 540   { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
 541   { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
 542   { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
 543   { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
 544   { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
 545   { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
 546   { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
 547   { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
 548   { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 }
 549 };
 550
 551 CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2 =
 552 {
 553   & mep_cgen_opval_h_ccr_ivc2_entries[0],
 554   55,
 555   0, 0, 0, 0, ""
 556 };
 557
 558
 559 /* The hardware table.  */
 560
 561 #define A(a) (1 << CGEN_HW_##a)
 562
 563 const CGEN_HW_ENTRY mep_cgen_hw_table[] =
 564 {
 565   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 566   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 567   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 568   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 569   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 570   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 571   { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 572   { "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 573   { "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 574   { "h-cr64-w", HW_H_CR64_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 575   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 576   { "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 577   { "h-ccr-w", HW_H_CCR_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 578   { "h-cr-ivc2", HW_H_CR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
 579   { "h-ccr-ivc2", HW_H_CCR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
 580   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 581 };
 582
 583 #undef A
 584
 585
 586 /* The instruction field table.  */
 587
 588 #define A(a) (1 << CGEN_IFLD_##a)
 589
 590 const CGEN_IFLD mep_cgen_ifld_table[] =
 591 {
 592   { MEP_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 593   { MEP_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 594   { MEP_F_MAJOR, "f-major", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 595   { MEP_F_RN, "f-rn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 596   { MEP_F_RN3, "f-rn3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 597   { MEP_F_RM, "f-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 598   { MEP_F_RL, "f-rl", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 599   { MEP_F_SUB2, "f-sub2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 600   { MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 601   { MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 602   { MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 603   { MEP_F_EXT4, "f-ext4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 604   { MEP_F_EXT62, "f-ext62", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 605   { MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 606   { MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 607   { MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 608   { MEP_F_CSRN, "f-csrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 609   { MEP_F_CRNX_HI, "f-crnx-hi", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 610   { MEP_F_CRNX_LO, "f-crnx-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 611   { MEP_F_CRNX, "f-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 612   { MEP_F_0, "f-0", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 613   { MEP_F_1, "f-1", 0, 32, 1, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 614   { MEP_F_2, "f-2", 0, 32, 2, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 615   { MEP_F_3, "f-3", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 616   { MEP_F_4, "f-4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 617   { MEP_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 618   { MEP_F_6, "f-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 619   { MEP_F_7, "f-7", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 620   { MEP_F_8, "f-8", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 621   { MEP_F_9, "f-9", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 622   { MEP_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 623   { MEP_F_11, "f-11", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 624   { MEP_F_12, "f-12", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 625   { MEP_F_13, "f-13", 0, 32, 13, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 626   { MEP_F_14, "f-14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 627   { MEP_F_15, "f-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 628   { MEP_F_16, "f-16", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 629   { MEP_F_17, "f-17", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 630   { MEP_F_18, "f-18", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 631   { MEP_F_19, "f-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 632   { MEP_F_20, "f-20", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 633   { MEP_F_21, "f-21", 0, 32, 21, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 634   { MEP_F_22, "f-22", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 635   { MEP_F_23, "f-23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 636   { MEP_F_24, "f-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 637   { MEP_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 638   { MEP_F_26, "f-26", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 639   { MEP_F_27, "f-27", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 640   { MEP_F_28, "f-28", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 641   { MEP_F_29, "f-29", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 642   { MEP_F_30, "f-30", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 643   { MEP_F_31, "f-31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 644   { MEP_F_8S8A2, "f-8s8a2", 0, 32, 8, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 645   { MEP_F_12S4A2, "f-12s4a2", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 646   { MEP_F_17S16A2, "f-17s16a2", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 647   { MEP_F_24S5A2N_HI, "f-24s5a2n-hi", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 648   { MEP_F_24S5A2N_LO, "f-24s5a2n-lo", 0, 32, 5, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 649   { MEP_F_24S5A2N, "f-24s5a2n", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 650   { MEP_F_24U5A2N_HI, "f-24u5a2n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 651   { MEP_F_24U5A2N_LO, "f-24u5a2n-lo", 0, 32, 5, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 652   { MEP_F_24U5A2N, "f-24u5a2n", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 653   { MEP_F_2U6, "f-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 654   { MEP_F_7U9, "f-7u9", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 655   { MEP_F_7U9A2, "f-7u9a2", 0, 32, 9, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 656   { MEP_F_7U9A4, "f-7u9a4", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 657   { MEP_F_16S16, "f-16s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 658   { MEP_F_2U10, "f-2u10", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 659   { MEP_F_3U5, "f-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 660   { MEP_F_4U8, "f-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 661   { MEP_F_5U8, "f-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 662   { MEP_F_5U24, "f-5u24", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 663   { MEP_F_6S8, "f-6s8", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 664   { MEP_F_8S8, "f-8s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 665   { MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 666   { MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 667   { MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 668   { MEP_F_CDISP10, "f-cdisp10", 0, 32, 22, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 669   { MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 670   { MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 671   { MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 672   { MEP_F_24U8N_HI, "f-24u8n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 673   { MEP_F_24U8N_LO, "f-24u8n-lo", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 674   { MEP_F_24U8N, "f-24u8n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 675   { MEP_F_24U4N_HI, "f-24u4n-hi", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 676   { MEP_F_24U4N_LO, "f-24u4n-lo", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 677   { MEP_F_24U4N, "f-24u4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 678   { MEP_F_CALLNUM, "f-callnum", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 679   { MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 680   { MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 681   { MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 682   { MEP_F_C5N4, "f-c5n4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 683   { MEP_F_C5N5, "f-c5n5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 684   { MEP_F_C5N6, "f-c5n6", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 685   { MEP_F_C5N7, "f-c5n7", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 686   { MEP_F_RL5, "f-rl5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 687   { MEP_F_12S20, "f-12s20", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
 688   { MEP_F_C5_RNM, "f-c5-rnm", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 689   { MEP_F_C5_RM, "f-c5-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 690   { MEP_F_C5_16U16, "f-c5-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 691   { MEP_F_C5_RMUIMM20, "f-c5-rmuimm20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 692   { MEP_F_C5_RNMUIMM24, "f-c5-rnmuimm24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 693   { MEP_F_IVC2_2U4, "f-ivc2-2u4", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 694   { MEP_F_IVC2_3U4, "f-ivc2-3u4", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 695   { MEP_F_IVC2_8U4, "f-ivc2-8u4", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 696   { MEP_F_IVC2_8S4, "f-ivc2-8s4", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 697   { MEP_F_IVC2_1U6, "f-ivc2-1u6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 698   { MEP_F_IVC2_2U6, "f-ivc2-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 699   { MEP_F_IVC2_3U6, "f-ivc2-3u6", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 700   { MEP_F_IVC2_6U6, "f-ivc2-6u6", 0, 32, 6, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 701   { MEP_F_IVC2_5U7, "f-ivc2-5u7", 0, 32, 7, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 702   { MEP_F_IVC2_4U8, "f-ivc2-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 703   { MEP_F_IVC2_3U9, "f-ivc2-3u9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 704   { MEP_F_IVC2_5U16, "f-ivc2-5u16", 0, 32, 16, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 705   { MEP_F_IVC2_5U21, "f-ivc2-5u21", 0, 32, 21, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 706   { MEP_F_IVC2_5U26, "f-ivc2-5u26", 0, 32, 26, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 707   { MEP_F_IVC2_1U31, "f-ivc2-1u31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 708   { MEP_F_IVC2_4U16, "f-ivc2-4u16", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 709   { MEP_F_IVC2_4U20, "f-ivc2-4u20", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 710   { MEP_F_IVC2_4U24, "f-ivc2-4u24", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 711   { MEP_F_IVC2_4U28, "f-ivc2-4u28", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 712   { MEP_F_IVC2_2U0, "f-ivc2-2u0", 0, 32, 0, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 713   { MEP_F_IVC2_3U0, "f-ivc2-3u0", 0, 32, 0, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 714   { MEP_F_IVC2_4U0, "f-ivc2-4u0", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 715   { MEP_F_IVC2_5U0, "f-ivc2-5u0", 0, 32, 0, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 716   { MEP_F_IVC2_8U0, "f-ivc2-8u0", 0, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 717   { MEP_F_IVC2_8S0, "f-ivc2-8s0", 0, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 718   { MEP_F_IVC2_6U2, "f-ivc2-6u2", 0, 32, 2, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 719   { MEP_F_IVC2_5U3, "f-ivc2-5u3", 0, 32, 3, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 720   { MEP_F_IVC2_4U4, "f-ivc2-4u4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 721   { MEP_F_IVC2_3U5, "f-ivc2-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 722   { MEP_F_IVC2_5U8, "f-ivc2-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 723   { MEP_F_IVC2_4U10, "f-ivc2-4u10", 0, 32, 10, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 724   { MEP_F_IVC2_3U12, "f-ivc2-3u12", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 725   { MEP_F_IVC2_5U13, "f-ivc2-5u13", 0, 32, 13, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 726   { MEP_F_IVC2_2U18, "f-ivc2-2u18", 0, 32, 18, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 727   { MEP_F_IVC2_5U18, "f-ivc2-5u18", 0, 32, 18, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 728   { MEP_F_IVC2_8U20, "f-ivc2-8u20", 0, 32, 20, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 729   { MEP_F_IVC2_8S20, "f-ivc2-8s20", 0, 32, 20, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 730   { MEP_F_IVC2_5U23, "f-ivc2-5u23", 0, 32, 23, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 731   { MEP_F_IVC2_2U23, "f-ivc2-2u23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 732   { MEP_F_IVC2_3U25, "f-ivc2-3u25", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 733   { MEP_F_IVC2_IMM16P0, "f-ivc2-imm16p0", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 734   { MEP_F_IVC2_SIMM16P0, "f-ivc2-simm16p0", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 735   { MEP_F_IVC2_CCRN_C3HI, "f-ivc2-ccrn-c3hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 736   { MEP_F_IVC2_CCRN_C3LO, "f-ivc2-ccrn-c3lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 737   { MEP_F_IVC2_CRN, "f-ivc2-crn", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 738   { MEP_F_IVC2_CRM, "f-ivc2-crm", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 739   { MEP_F_IVC2_CCRN_H1, "f-ivc2-ccrn-h1", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 740   { MEP_F_IVC2_CCRN_H2, "f-ivc2-ccrn-h2", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 741   { MEP_F_IVC2_CCRN_LO, "f-ivc2-ccrn-lo", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 742   { MEP_F_IVC2_CMOV1, "f-ivc2-cmov1", 0, 32, 8, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 743   { MEP_F_IVC2_CMOV2, "f-ivc2-cmov2", 0, 32, 22, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 744   { MEP_F_IVC2_CMOV3, "f-ivc2-cmov3", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 745   { MEP_F_IVC2_CCRN_C3, "f-ivc2-ccrn-c3", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 746   { MEP_F_IVC2_CCRN, "f-ivc2-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 747   { MEP_F_IVC2_CRNX, "f-ivc2-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
 748   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 749 };
 750
 751 #undef A
 752
 753
 754
 755 /* multi ifield declarations */
 756
 757 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [];
 758 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [];
 759 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [];
 760 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [];
 761 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [];
 762 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [];
 763 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [];
 764 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [];
 765 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [];
 766 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [];
 767 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [];
 768 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_IMM16P0_MULTI_IFIELD [];
 769 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [];
 770 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_C3_MULTI_IFIELD [];
 771 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [];
 772 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [];
 773
 774
 775 /* multi ifield definitions */
 776
 777 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [] =
 778 {
 779     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_HI] } },
 780     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_LO] } },
 781     { 0, { (const PTR) 0 } }
 782 };
 783 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [] =
 784 {
 785     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_HI] } },
 786     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_LO] } },
 787     { 0, { (const PTR) 0 } }
 788 };
 789 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [] =
 790 {
 791     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } },
 792     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } },
 793     { 0, { (const PTR) 0 } }
 794 };
 795 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [] =
 796 {
 797     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } },
 798     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } },
 799     { 0, { (const PTR) 0 } }
 800 };
 801 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [] =
 802 {
 803     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } },
 804     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } },
 805     { 0, { (const PTR) 0 } }
 806 };
 807 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [] =
 808 {
 809     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_HI] } },
 810     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_LO] } },
 811     { 0, { (const PTR) 0 } }
 812 };
 813 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [] =
 814 {
 815     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_HI] } },
 816     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_LO] } },
 817     { 0, { (const PTR) 0 } }
 818 };
 819 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [] =
 820 {
 821     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5] } },
 822     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6] } },
 823     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7] } },
 824     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_11] } },
 825     { 0, { (const PTR) 0 } }
 826 };
 827 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] =
 828 {
 829     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_HI] } },
 830     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
 831     { 0, { (const PTR) 0 } }
 832 };
 833 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [] =
 834 {
 835     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RM] } },
 836     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
 837     { 0, { (const PTR) 0 } }
 838 };
 839 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [] =
 840 {
 841     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RNM] } },
 842     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
 843     { 0, { (const PTR) 0 } }
 844 };
 845 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_IMM16P0_MULTI_IFIELD [] =
 846 {
 847     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
 848     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
 849     { 0, { (const PTR) 0 } }
 850 };
 851 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [] =
 852 {
 853     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
 854     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
 855     { 0, { (const PTR) 0 } }
 856 };
 857 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_C3_MULTI_IFIELD [] =
 858 {
 859     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3HI] } },
 860     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3LO] } },
 861     { 0, { (const PTR) 0 } }
 862 };
 863 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [] =
 864 {
 865     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H2] } },
 866     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
 867     { 0, { (const PTR) 0 } }
 868 };
 869 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [] =
 870 {
 871     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H1] } },
 872     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
 873     { 0, { (const PTR) 0 } }
 874 };
 875
 876 /* The operand table.  */
 877
 878 #define A(a) (1 << CGEN_OPERAND_##a)
 879 #define OPERAND(op) MEP_OPERAND_##op
 880
 881 const CGEN_OPERAND mep_cgen_operand_table[] =
 882 {
 883 /* pc: program counter */
 884   { "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
 885     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
 886     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 887 /* r0: register 0 */
 888   { "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
 889     { 0, { (const PTR) 0 } },
 890     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 891 /* rn: register Rn */
 892   { "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
 893     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 894     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 895 /* rm: register Rm */
 896   { "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
 897     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
 898     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 899 /* rl: register Rl */
 900   { "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
 901     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
 902     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 903 /* rn3: register 0-7 */
 904   { "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
 905     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 906     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 907 /* rma: register Rm holding pointer */
 908   { "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
 909     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
 910     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } }  },
 911 /* rnc: register Rn holding char */
 912   { "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
 913     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 914     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 915 /* rnuc: register Rn holding unsigned char */
 916   { "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
 917     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 918     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 919 /* rns: register Rn holding short */
 920   { "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
 921     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 922     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 923 /* rnus: register Rn holding unsigned short */
 924   { "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
 925     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 926     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 927 /* rnl: register Rn holding long */
 928   { "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
 929     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 930     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 931 /* rnul: register Rn holding unsigned  long */
 932   { "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
 933     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
 934     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
 935 /* rn3c: register 0-7 holding unsigned char */
 936   { "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
 937     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 938     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 939 /* rn3uc: register 0-7 holding byte */
 940   { "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
 941     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 942     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 943 /* rn3s: register 0-7 holding unsigned short */
 944   { "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
 945     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 946     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 947 /* rn3us: register 0-7 holding short */
 948   { "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
 949     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 950     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 951 /* rn3l: register 0-7 holding unsigned long */
 952   { "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
 953     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 954     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 955 /* rn3ul: register 0-7 holding long */
 956   { "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
 957     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
 958     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
 959 /* lp: link pointer */
 960   { "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
 961     { 0, { (const PTR) 0 } },
 962     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 963 /* sar: shift amount register */
 964   { "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
 965     { 0, { (const PTR) 0 } },
 966     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 967 /* hi: high result */
 968   { "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
 969     { 0, { (const PTR) 0 } },
 970     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 971 /* lo: low result */
 972   { "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
 973     { 0, { (const PTR) 0 } },
 974     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 975 /* mb0: modulo begin register 0 */
 976   { "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
 977     { 0, { (const PTR) 0 } },
 978     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 979 /* me0: modulo end register 0 */
 980   { "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
 981     { 0, { (const PTR) 0 } },
 982     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 983 /* mb1: modulo begin register 1 */
 984   { "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
 985     { 0, { (const PTR) 0 } },
 986     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 987 /* me1: modulo end register 1 */
 988   { "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
 989     { 0, { (const PTR) 0 } },
 990     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 991 /* psw: program status word */
 992   { "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
 993     { 0, { (const PTR) 0 } },
 994     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 995 /* epc: exception prog counter */
 996   { "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
 997     { 0, { (const PTR) 0 } },
 998     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
 999 /* exc: exception cause */
1000   { "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
1001     { 0, { (const PTR) 0 } },
1002     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1003 /* npc: nmi program counter */
1004   { "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
1005     { 0, { (const PTR) 0 } },
1006     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1007 /* dbg: debug register */
1008   { "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
1009     { 0, { (const PTR) 0 } },
1010     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1011 /* depc: debug exception pc */
1012   { "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
1013     { 0, { (const PTR) 0 } },
1014     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1015 /* opt: option register */
1016   { "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
1017     { 0, { (const PTR) 0 } },
1018     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1019 /* r1: register 1 */
1020   { "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
1021     { 0, { (const PTR) 0 } },
1022     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1023 /* tp: tiny data area pointer */
1024   { "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
1025     { 0, { (const PTR) 0 } },
1026     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1027 /* sp: stack pointer */
1028   { "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
1029     { 0, { (const PTR) 0 } },
1030     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1031 /* tpr: comment */
1032   { "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
1033     { 0, { (const PTR) 0 } },
1034     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1035 /* spr: comment */
1036   { "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
1037     { 0, { (const PTR) 0 } },
1038     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1039 /* csrn: control/special register */
1040   { "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
1041     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
1042     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1043 /* csrn-idx: control/special reg idx */
1044   { "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
1045     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
1046     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1047 /* crn64: copro Rn (64-bit) */
1048   { "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
1049     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
1050     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1051 /* crn: copro Rn (32-bit) */
1052   { "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
1053     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
1054     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1055 /* crnx64: copro Rn (0-31, 64-bit) */
1056   { "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
1057     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
1058     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1059 /* crnx: copro Rn (0-31, 32-bit) */
1060   { "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
1061     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
1062     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1063 /* ccrn: copro control reg CCRn */
1064   { "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
1065     { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
1066     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1067 /* cccc: copro flags */
1068   { "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
1069     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
1070     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1071 /* pcrel8a2: comment */
1072   { "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
1073     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
1074     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1075 /* pcrel12a2: comment */
1076   { "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
1077     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
1078     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1079 /* pcrel17a2: comment */
1080   { "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
1081     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
1082     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1083 /* pcrel24a2: comment */
1084   { "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
1085     { 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
1086     { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1087 /* pcabs24a2: comment */
1088   { "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
1089     { 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
1090     { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1091 /* sdisp16: comment */
1092   { "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
1093     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
1094     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1095 /* simm16: comment */
1096   { "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
1097     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
1098     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1099 /* uimm16: comment */
1100   { "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
1101     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
1102     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1103 /* code16: uci/dsp code (16 bits) */
1104   { "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
1105     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
1106     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1107 /* udisp2: SSARB addend (2 bits) */
1108   { "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
1109     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
1110     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1111 /* uimm2: interrupt (2 bits) */
1112   { "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
1113     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
1114     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1115 /* simm6: add const (6 bits) */
1116   { "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
1117     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
1118     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1119 /* simm8: mov const (8 bits) */
1120   { "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
1121     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
1122     { 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1123 /* addr24a4: comment */
1124   { "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
1125     { 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
1126     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
1127 /* code24: coprocessor code */
1128   { "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
1129     { 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
1130     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1131 /* callnum: system call number */
1132   { "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
1133     { 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
1134     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1135 /* uimm3: bit immediate (3 bits) */
1136   { "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
1137     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
1138     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1139 /* uimm4: bCC const (4 bits) */
1140   { "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
1141     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
1142     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1143 /* uimm5: bit/shift val (5 bits) */
1144   { "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
1145     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
1146     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1147 /* udisp7: comment */
1148   { "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
1149     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
1150     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1151 /* udisp7a2: comment */
1152   { "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
1153     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
1154     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } }  },
1155 /* udisp7a4: comment */
1156   { "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
1157     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
1158     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
1159 /* uimm7a4: comment */
1160   { "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
1161     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
1162     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
1163 /* uimm24: immediate (24 bits) */
1164   { "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
1165     { 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
1166     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1167 /* cimm4: cache immed'te (4 bits) */
1168   { "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
1169     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
1170     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1171 /* cimm5: clip immediate (5 bits) */
1172   { "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
1173     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
1174     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1175 /* cdisp10: comment */
1176   { "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
1177     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1178     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1179 /* cdisp10a2: comment */
1180   { "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
1181     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1182     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1183 /* cdisp10a4: comment */
1184   { "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
1185     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1186     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1187 /* cdisp10a8: comment */
1188   { "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
1189     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1190     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1191 /* zero: Zero operand */
1192   { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
1193     { 0, { (const PTR) 0 } },
1194     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1195 /* rl5: register Rl c5 */
1196   { "rl5", MEP_OPERAND_RL5, HW_H_GPR, 20, 4,
1197     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } },
1198     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1199 /* cdisp12: copro addend (12 bits) */
1200   { "cdisp12", MEP_OPERAND_CDISP12, HW_H_SINT, 20, 12,
1201     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } },
1202     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1203 /* c5rmuimm20: 20-bit immediate in rm and imm16 */
1204   { "c5rmuimm20", MEP_OPERAND_C5RMUIMM20, HW_H_UINT, 8, 20,
1205     { 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
1206     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1207 /* c5rnmuimm24: 24-bit immediate in rn, rm, and imm16 */
1208   { "c5rnmuimm24", MEP_OPERAND_C5RNMUIMM24, HW_H_UINT, 4, 24,
1209     { 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
1210     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1211 /* cp_flag: branch condition register */
1212   { "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
1213     { 0, { (const PTR) 0 } },
1214     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1215 /* ivc2_csar0: ivc2_csar0 */
1216   { "ivc2_csar0", MEP_OPERAND_IVC2_CSAR0, HW_H_CCR_IVC2, 0, 0,
1217     { 0, { (const PTR) 0 } },
1218     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1219 /* ivc2_cc: ivc2_cc */
1220   { "ivc2_cc", MEP_OPERAND_IVC2_CC, HW_H_CCR_IVC2, 0, 0,
1221     { 0, { (const PTR) 0 } },
1222     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1223 /* ivc2_cofr0: ivc2_cofr0 */
1224   { "ivc2_cofr0", MEP_OPERAND_IVC2_COFR0, HW_H_CCR_IVC2, 0, 0,
1225     { 0, { (const PTR) 0 } },
1226     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1227 /* ivc2_cofr1: ivc2_cofr1 */
1228   { "ivc2_cofr1", MEP_OPERAND_IVC2_COFR1, HW_H_CCR_IVC2, 0, 0,
1229     { 0, { (const PTR) 0 } },
1230     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1231 /* ivc2_cofa0: ivc2_cofa0 */
1232   { "ivc2_cofa0", MEP_OPERAND_IVC2_COFA0, HW_H_CCR_IVC2, 0, 0,
1233     { 0, { (const PTR) 0 } },
1234     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1235 /* ivc2_cofa1: ivc2_cofa1 */
1236   { "ivc2_cofa1", MEP_OPERAND_IVC2_COFA1, HW_H_CCR_IVC2, 0, 0,
1237     { 0, { (const PTR) 0 } },
1238     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1239 /* ivc2_csar1: ivc2_csar1 */
1240   { "ivc2_csar1", MEP_OPERAND_IVC2_CSAR1, HW_H_CCR_IVC2, 0, 0,
1241     { 0, { (const PTR) 0 } },
1242     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1243 /* ivc2_acc0_0: acc0_0 */
1244   { "ivc2_acc0_0", MEP_OPERAND_IVC2_ACC0_0, HW_H_CCR_IVC2, 0, 0,
1245     { 0, { (const PTR) 0 } },
1246     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1247 /* ivc2_acc0_1: acc0_1 */
1248   { "ivc2_acc0_1", MEP_OPERAND_IVC2_ACC0_1, HW_H_CCR_IVC2, 0, 0,
1249     { 0, { (const PTR) 0 } },
1250     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1251 /* ivc2_acc0_2: acc0_2 */
1252   { "ivc2_acc0_2", MEP_OPERAND_IVC2_ACC0_2, HW_H_CCR_IVC2, 0, 0,
1253     { 0, { (const PTR) 0 } },
1254     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1255 /* ivc2_acc0_3: acc0_3 */
1256   { "ivc2_acc0_3", MEP_OPERAND_IVC2_ACC0_3, HW_H_CCR_IVC2, 0, 0,
1257     { 0, { (const PTR) 0 } },
1258     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1259 /* ivc2_acc0_4: acc0_4 */
1260   { "ivc2_acc0_4", MEP_OPERAND_IVC2_ACC0_4, HW_H_CCR_IVC2, 0, 0,
1261     { 0, { (const PTR) 0 } },
1262     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1263 /* ivc2_acc0_5: acc0_5 */
1264   { "ivc2_acc0_5", MEP_OPERAND_IVC2_ACC0_5, HW_H_CCR_IVC2, 0, 0,
1265     { 0, { (const PTR) 0 } },
1266     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1267 /* ivc2_acc0_6: acc0_6 */
1268   { "ivc2_acc0_6", MEP_OPERAND_IVC2_ACC0_6, HW_H_CCR_IVC2, 0, 0,
1269     { 0, { (const PTR) 0 } },
1270     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1271 /* ivc2_acc0_7: acc0_7 */
1272   { "ivc2_acc0_7", MEP_OPERAND_IVC2_ACC0_7, HW_H_CCR_IVC2, 0, 0,
1273     { 0, { (const PTR) 0 } },
1274     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1275 /* ivc2_acc1_0: acc1_0 */
1276   { "ivc2_acc1_0", MEP_OPERAND_IVC2_ACC1_0, HW_H_CCR_IVC2, 0, 0,
1277     { 0, { (const PTR) 0 } },
1278     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1279 /* ivc2_acc1_1: acc1_1 */
1280   { "ivc2_acc1_1", MEP_OPERAND_IVC2_ACC1_1, HW_H_CCR_IVC2, 0, 0,
1281     { 0, { (const PTR) 0 } },
1282     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1283 /* ivc2_acc1_2: acc1_2 */
1284   { "ivc2_acc1_2", MEP_OPERAND_IVC2_ACC1_2, HW_H_CCR_IVC2, 0, 0,
1285     { 0, { (const PTR) 0 } },
1286     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1287 /* ivc2_acc1_3: acc1_3 */
1288   { "ivc2_acc1_3", MEP_OPERAND_IVC2_ACC1_3, HW_H_CCR_IVC2, 0, 0,
1289     { 0, { (const PTR) 0 } },
1290     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1291 /* ivc2_acc1_4: acc1_4 */
1292   { "ivc2_acc1_4", MEP_OPERAND_IVC2_ACC1_4, HW_H_CCR_IVC2, 0, 0,
1293     { 0, { (const PTR) 0 } },
1294     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1295 /* ivc2_acc1_5: acc1_5 */
1296   { "ivc2_acc1_5", MEP_OPERAND_IVC2_ACC1_5, HW_H_CCR_IVC2, 0, 0,
1297     { 0, { (const PTR) 0 } },
1298     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1299 /* ivc2_acc1_6: acc1_6 */
1300   { "ivc2_acc1_6", MEP_OPERAND_IVC2_ACC1_6, HW_H_CCR_IVC2, 0, 0,
1301     { 0, { (const PTR) 0 } },
1302     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1303 /* ivc2_acc1_7: acc1_7 */
1304   { "ivc2_acc1_7", MEP_OPERAND_IVC2_ACC1_7, HW_H_CCR_IVC2, 0, 0,
1305     { 0, { (const PTR) 0 } },
1306     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1307 /* croc: $CRo C3 */
1308   { "croc", MEP_OPERAND_CROC, HW_H_CR64, 7, 5,
1309     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
1310     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1311 /* crqc: $CRq C3 */
1312   { "crqc", MEP_OPERAND_CRQC, HW_H_CR64, 21, 5,
1313     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U21] } },
1314     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1315 /* crpc: $CRp C3 */
1316   { "crpc", MEP_OPERAND_CRPC, HW_H_CR64, 26, 5,
1317     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U26] } },
1318     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1319 /* ivc-x-6-1: filler */
1320   { "ivc-x-6-1", MEP_OPERAND_IVC_X_6_1, HW_H_UINT, 6, 1,
1321     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_1U6] } },
1322     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1323 /* ivc-x-6-2: filler */
1324   { "ivc-x-6-2", MEP_OPERAND_IVC_X_6_2, HW_H_UINT, 6, 2,
1325     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U6] } },
1326     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1327 /* ivc-x-6-3: filler */
1328   { "ivc-x-6-3", MEP_OPERAND_IVC_X_6_3, HW_H_UINT, 6, 3,
1329     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U6] } },
1330     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1331 /* imm3p4: Imm3p4 */
1332   { "imm3p4", MEP_OPERAND_IMM3P4, HW_H_UINT, 4, 3,
1333     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U4] } },
1334     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1335 /* imm3p9: Imm3p9 */
1336   { "imm3p9", MEP_OPERAND_IMM3P9, HW_H_UINT, 9, 3,
1337     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U9] } },
1338     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1339 /* imm4p8: Imm4p8 */
1340   { "imm4p8", MEP_OPERAND_IMM4P8, HW_H_UINT, 8, 4,
1341     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U8] } },
1342     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1343 /* imm5p7: Imm5p7 */
1344   { "imm5p7", MEP_OPERAND_IMM5P7, HW_H_UINT, 7, 5,
1345     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
1346     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1347 /* imm6p6: Imm6p6 */
1348   { "imm6p6", MEP_OPERAND_IMM6P6, HW_H_UINT, 6, 6,
1349     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U6] } },
1350     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1351 /* imm8p4: Imm8p4 */
1352   { "imm8p4", MEP_OPERAND_IMM8P4, HW_H_UINT, 4, 8,
1353     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U4] } },
1354     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1355 /* simm8p4: sImm8p4 */
1356   { "simm8p4", MEP_OPERAND_SIMM8P4, HW_H_SINT, 4, 8,
1357     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S4] } },
1358     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1359 /* imm3p5: Imm3p5 */
1360   { "imm3p5", MEP_OPERAND_IMM3P5, HW_H_UINT, 5, 3,
1361     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U5] } },
1362     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1363 /* imm3p12: Imm3p12 */
1364   { "imm3p12", MEP_OPERAND_IMM3P12, HW_H_UINT, 12, 3,
1365     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U12] } },
1366     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1367 /* imm4p4: Imm4p4 */
1368   { "imm4p4", MEP_OPERAND_IMM4P4, HW_H_UINT, 4, 4,
1369     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U4] } },
1370     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1371 /* imm4p10: Imm4p10 */
1372   { "imm4p10", MEP_OPERAND_IMM4P10, HW_H_UINT, 10, 4,
1373     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U10] } },
1374     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1375 /* imm5p8: Imm5p8 */
1376   { "imm5p8", MEP_OPERAND_IMM5P8, HW_H_UINT, 8, 5,
1377     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U8] } },
1378     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1379 /* imm5p3: Imm5p3 */
1380   { "imm5p3", MEP_OPERAND_IMM5P3, HW_H_UINT, 3, 5,
1381     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U3] } },
1382     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1383 /* imm6p2: Imm6p2 */
1384   { "imm6p2", MEP_OPERAND_IMM6P2, HW_H_UINT, 2, 6,
1385     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U2] } },
1386     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1387 /* imm5p23: Imm5p23 */
1388   { "imm5p23", MEP_OPERAND_IMM5P23, HW_H_UINT, 23, 5,
1389     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
1390     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1391 /* imm3p25: Imm3p25 */
1392   { "imm3p25", MEP_OPERAND_IMM3P25, HW_H_UINT, 25, 3,
1393     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U25] } },
1394     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1395 /* imm8p0: Imm8p0 */
1396   { "imm8p0", MEP_OPERAND_IMM8P0, HW_H_UINT, 0, 8,
1397     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
1398     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1399 /* simm8p0: sImm8p0 */
1400   { "simm8p0", MEP_OPERAND_SIMM8P0, HW_H_SINT, 0, 8,
1401     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S0] } },
1402     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1403 /* simm8p20: sImm8p20 */
1404   { "simm8p20", MEP_OPERAND_SIMM8P20, HW_H_SINT, 20, 8,
1405     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S20] } },
1406     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1407 /* imm8p20: Imm8p20 */
1408   { "imm8p20", MEP_OPERAND_IMM8P20, HW_H_UINT, 20, 8,
1409     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
1410     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1411 /* crop: $CRo Pn */
1412   { "crop", MEP_OPERAND_CROP, HW_H_CR64, 23, 5,
1413     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
1414     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1415 /* crqp: $CRq Pn */
1416   { "crqp", MEP_OPERAND_CRQP, HW_H_CR64, 13, 5,
1417     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U13] } },
1418     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1419 /* crpp: $CRp Pn */
1420   { "crpp", MEP_OPERAND_CRPP, HW_H_CR64, 18, 5,
1421     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U18] } },
1422     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1423 /* ivc-x-0-2: filler */
1424   { "ivc-x-0-2", MEP_OPERAND_IVC_X_0_2, HW_H_UINT, 0, 2,
1425     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U0] } },
1426     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1427 /* ivc-x-0-3: filler */
1428   { "ivc-x-0-3", MEP_OPERAND_IVC_X_0_3, HW_H_UINT, 0, 3,
1429     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U0] } },
1430     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1431 /* ivc-x-0-4: filler */
1432   { "ivc-x-0-4", MEP_OPERAND_IVC_X_0_4, HW_H_UINT, 0, 4,
1433     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U0] } },
1434     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1435 /* ivc-x-0-5: filler */
1436   { "ivc-x-0-5", MEP_OPERAND_IVC_X_0_5, HW_H_UINT, 0, 5,
1437     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U0] } },
1438     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1439 /* imm16p0: comment */
1440   { "imm16p0", MEP_OPERAND_IMM16P0, HW_H_UINT, 0, 16,
1441     { 2, { (const PTR) &MEP_F_IVC2_IMM16P0_MULTI_IFIELD[0] } },
1442     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1443 /* simm16p0: comment */
1444   { "simm16p0", MEP_OPERAND_SIMM16P0, HW_H_SINT, 0, 16,
1445     { 2, { (const PTR) &MEP_F_IVC2_SIMM16P0_MULTI_IFIELD[0] } },
1446     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1447 /* ivc2rm: reg Rm */
1448   { "ivc2rm", MEP_OPERAND_IVC2RM, HW_H_GPR, 4, 4,
1449     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CRM] } },
1450     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1451 /* ivc2crn: copro Rn (0-31, 64-bit */
1452   { "ivc2crn", MEP_OPERAND_IVC2CRN, HW_H_CR64, 0, 5,
1453     { 2, { (const PTR) &MEP_F_IVC2_CRNX_MULTI_IFIELD[0] } },
1454     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1455 /* ivc2ccrn: copro control reg CCRn */
1456   { "ivc2ccrn", MEP_OPERAND_IVC2CCRN, HW_H_CCR_IVC2, 0, 6,
1457     { 2, { (const PTR) &MEP_F_IVC2_CCRN_MULTI_IFIELD[0] } },
1458     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1459 /* ivc2c3ccrn: copro control reg CCRn */
1460   { "ivc2c3ccrn", MEP_OPERAND_IVC2C3CCRN, HW_H_CCR_IVC2, 4, 6,
1461     { 2, { (const PTR) &MEP_F_IVC2_CCRN_C3_MULTI_IFIELD[0] } },
1462     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1463 /* sentinel */
1464   { 0, 0, 0, 0, 0,
1465     { 0, { (const PTR) 0 } },
1466     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }
1467 };
1468
1469 #undef A
1470
1471
1472 /* The instruction table.  */
1473
1474 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1475 #define A(a) (1 << CGEN_INSN_##a)
1476
1477 static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
1478 {
1479   /* Special null first entry.
1480      A `num' value of zero is thus invalid.
1481      Also, the special `invalid' insn resides here.  */
1482   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } } },
1483 /* stcb $rn,($rma) */
1484   {
1485     MEP_INSN_STCB_R, "stcb_r", "stcb", 16,
1486     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1487   },
1488 /* ldcb $rn,($rma) */
1489   {
1490     MEP_INSN_LDCB_R, "ldcb_r", "ldcb", 16,
1491     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1492   },
1493 /* pref $cimm4,($rma) */
1494   {
1495     MEP_INSN_PREF, "pref", "pref", 16,
1496     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1497   },
1498 /* pref $cimm4,$sdisp16($rma) */
1499   {
1500     MEP_INSN_PREFD, "prefd", "pref", 32,
1501     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1502   },
1503 /* casb3 $rl5,$rn,($rm) */
1504   {
1505     MEP_INSN_CASB3, "casb3", "casb3", 32,
1506     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1507   },
1508 /* cash3 $rl5,$rn,($rm) */
1509   {
1510     MEP_INSN_CASH3, "cash3", "cash3", 32,
1511     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1512   },
1513 /* casw3 $rl5,$rn,($rm) */
1514   {
1515     MEP_INSN_CASW3, "casw3", "casw3", 32,
1516     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1517   },
1518 /* sbcp $crn,$cdisp12($rma) */
1519   {
1520     MEP_INSN_SBCP, "sbcp", "sbcp", 32,
1521     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1522   },
1523 /* lbcp $crn,$cdisp12($rma) */
1524   {
1525     MEP_INSN_LBCP, "lbcp", "lbcp", 32,
1526     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1527   },
1528 /* lbucp $crn,$cdisp12($rma) */
1529   {
1530     MEP_INSN_LBUCP, "lbucp", "lbucp", 32,
1531     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1532   },
1533 /* shcp $crn,$cdisp12($rma) */
1534   {
1535     MEP_INSN_SHCP, "shcp", "shcp", 32,
1536     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1537   },
1538 /* lhcp $crn,$cdisp12($rma) */
1539   {
1540     MEP_INSN_LHCP, "lhcp", "lhcp", 32,
1541     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1542   },
1543 /* lhucp $crn,$cdisp12($rma) */
1544   {
1545     MEP_INSN_LHUCP, "lhucp", "lhucp", 32,
1546     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1547   },
1548 /* lbucpa $crn,($rma+),$cdisp10 */
1549   {
1550     MEP_INSN_LBUCPA, "lbucpa", "lbucpa", 32,
1551     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1552   },
1553 /* lhucpa $crn,($rma+),$cdisp10a2 */
1554   {
1555     MEP_INSN_LHUCPA, "lhucpa", "lhucpa", 32,
1556     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1557   },
1558 /* lbucpm0 $crn,($rma+),$cdisp10 */
1559   {
1560     MEP_INSN_LBUCPM0, "lbucpm0", "lbucpm0", 32,
1561     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1562   },
1563 /* lhucpm0 $crn,($rma+),$cdisp10a2 */
1564   {
1565     MEP_INSN_LHUCPM0, "lhucpm0", "lhucpm0", 32,
1566     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1567   },
1568 /* lbucpm1 $crn,($rma+),$cdisp10 */
1569   {
1570     MEP_INSN_LBUCPM1, "lbucpm1", "lbucpm1", 32,
1571     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1572   },
1573 /* lhucpm1 $crn,($rma+),$cdisp10a2 */
1574   {
1575     MEP_INSN_LHUCPM1, "lhucpm1", "lhucpm1", 32,
1576     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1577   },
1578 /* uci $rn,$rm,$uimm16 */
1579   {
1580     MEP_INSN_UCI, "uci", "uci", 32,
1581     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1582   },
1583 /* dsp $rn,$rm,$uimm16 */
1584   {
1585     MEP_INSN_DSP, "dsp", "dsp", 32,
1586     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1587   },
1588 /* dsp0 $c5rnmuimm24 */
1589   {
1590     -1, "dsp0", "dsp0", 32,
1591     { 0|A(ALIAS)|A(NO_DIS)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1592   },
1593 /* dsp1 $rn,$c5rmuimm20 */
1594   {
1595     -1, "dsp1", "dsp1", 32,
1596     { 0|A(ALIAS)|A(NO_DIS)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1597   },
1598 /* sb $rnc,($rma) */
1599   {
1600     MEP_INSN_SB, "sb", "sb", 16,
1601     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1602   },
1603 /* sh $rns,($rma) */
1604   {
1605     MEP_INSN_SH, "sh", "sh", 16,
1606     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1607   },
1608 /* sw $rnl,($rma) */
1609   {
1610     MEP_INSN_SW, "sw", "sw", 16,
1611     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1612   },
1613 /* lb $rnc,($rma) */
1614   {
1615     MEP_INSN_LB, "lb", "lb", 16,
1616     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1617   },
1618 /* lh $rns,($rma) */
1619   {
1620     MEP_INSN_LH, "lh", "lh", 16,
1621     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1622   },
1623 /* lw $rnl,($rma) */
1624   {
1625     MEP_INSN_LW, "lw", "lw", 16,
1626     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1627   },
1628 /* lbu $rnuc,($rma) */
1629   {
1630     MEP_INSN_LBU, "lbu", "lbu", 16,
1631     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1632   },
1633 /* lhu $rnus,($rma) */
1634   {
1635     MEP_INSN_LHU, "lhu", "lhu", 16,
1636     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1637   },
1638 /* sw $rnl,$udisp7a4($spr) */
1639   {
1640     MEP_INSN_SW_SP, "sw-sp", "sw", 16,
1641     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1642   },
1643 /* lw $rnl,$udisp7a4($spr) */
1644   {
1645     MEP_INSN_LW_SP, "lw-sp", "lw", 16,
1646     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1647   },
1648 /* sb $rn3c,$udisp7($tpr) */
1649   {
1650     MEP_INSN_SB_TP, "sb-tp", "sb", 16,
1651     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1652   },
1653 /* sh $rn3s,$udisp7a2($tpr) */
1654   {
1655     MEP_INSN_SH_TP, "sh-tp", "sh", 16,
1656     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1657   },
1658 /* sw $rn3l,$udisp7a4($tpr) */
1659   {
1660     MEP_INSN_SW_TP, "sw-tp", "sw", 16,
1661     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1662   },
1663 /* lb $rn3c,$udisp7($tpr) */
1664   {
1665     MEP_INSN_LB_TP, "lb-tp", "lb", 16,
1666     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1667   },
1668 /* lh $rn3s,$udisp7a2($tpr) */
1669   {
1670     MEP_INSN_LH_TP, "lh-tp", "lh", 16,
1671     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1672   },
1673 /* lw $rn3l,$udisp7a4($tpr) */
1674   {
1675     MEP_INSN_LW_TP, "lw-tp", "lw", 16,
1676     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1677   },
1678 /* lbu $rn3uc,$udisp7($tpr) */
1679   {
1680     MEP_INSN_LBU_TP, "lbu-tp", "lbu", 16,
1681     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1682   },
1683 /* lhu $rn3us,$udisp7a2($tpr) */
1684   {
1685     MEP_INSN_LHU_TP, "lhu-tp", "lhu", 16,
1686     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1687   },
1688 /* sb $rnc,$sdisp16($rma) */
1689   {
1690     MEP_INSN_SB16, "sb16", "sb", 32,
1691     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1692   },
1693 /* sh $rns,$sdisp16($rma) */
1694   {
1695     MEP_INSN_SH16, "sh16", "sh", 32,
1696     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1697   },
1698 /* sw $rnl,$sdisp16($rma) */
1699   {
1700     MEP_INSN_SW16, "sw16", "sw", 32,
1701     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1702   },
1703 /* lb $rnc,$sdisp16($rma) */
1704   {
1705     MEP_INSN_LB16, "lb16", "lb", 32,
1706     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1707   },
1708 /* lh $rns,$sdisp16($rma) */
1709   {
1710     MEP_INSN_LH16, "lh16", "lh", 32,
1711     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1712   },
1713 /* lw $rnl,$sdisp16($rma) */
1714   {
1715     MEP_INSN_LW16, "lw16", "lw", 32,
1716     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1717   },
1718 /* lbu $rnuc,$sdisp16($rma) */
1719   {
1720     MEP_INSN_LBU16, "lbu16", "lbu", 32,
1721     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1722   },
1723 /* lhu $rnus,$sdisp16($rma) */
1724   {
1725     MEP_INSN_LHU16, "lhu16", "lhu", 32,
1726     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1727   },
1728 /* sw $rnl,($addr24a4) */
1729   {
1730     MEP_INSN_SW24, "sw24", "sw", 32,
1731     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1732   },
1733 /* lw $rnl,($addr24a4) */
1734   {
1735     MEP_INSN_LW24, "lw24", "lw", 32,
1736     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1737   },
1738 /* extb $rn */
1739   {
1740     MEP_INSN_EXTB, "extb", "extb", 16,
1741     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1742   },
1743 /* exth $rn */
1744   {
1745     MEP_INSN_EXTH, "exth", "exth", 16,
1746     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1747   },
1748 /* extub $rn */
1749   {
1750     MEP_INSN_EXTUB, "extub", "extub", 16,
1751     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1752   },
1753 /* extuh $rn */
1754   {
1755     MEP_INSN_EXTUH, "extuh", "extuh", 16,
1756     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1757   },
1758 /* ssarb $udisp2($rm) */
1759   {
1760     MEP_INSN_SSARB, "ssarb", "ssarb", 16,
1761     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1762   },
1763 /* mov $rn,$rm */
1764   {
1765     MEP_INSN_MOV, "mov", "mov", 16,
1766     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1767   },
1768 /* mov $rn,$simm8 */
1769   {
1770     MEP_INSN_MOVI8, "movi8", "mov", 16,
1771     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1772   },
1773 /* mov $rn,$simm16 */
1774   {
1775     MEP_INSN_MOVI16, "movi16", "mov", 32,
1776     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1777   },
1778 /* movu $rn3,$uimm24 */
1779   {
1780     MEP_INSN_MOVU24, "movu24", "movu", 32,
1781     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1782   },
1783 /* movu $rn,$uimm16 */
1784   {
1785     MEP_INSN_MOVU16, "movu16", "movu", 32,
1786     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1787   },
1788 /* movh $rn,$uimm16 */
1789   {
1790     MEP_INSN_MOVH, "movh", "movh", 32,
1791     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1792   },
1793 /* add3 $rl,$rn,$rm */
1794   {
1795     MEP_INSN_ADD3, "add3", "add3", 16,
1796     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1797   },
1798 /* add $rn,$simm6 */
1799   {
1800     MEP_INSN_ADD, "add", "add", 16,
1801     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1802   },
1803 /* add3 $rn,$spr,$uimm7a4 */
1804   {
1805     MEP_INSN_ADD3I, "add3i", "add3", 16,
1806     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1807   },
1808 /* advck3 \$0,$rn,$rm */
1809   {
1810     MEP_INSN_ADVCK3, "advck3", "advck3", 16,
1811     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1812   },
1813 /* sub $rn,$rm */
1814   {
1815     MEP_INSN_SUB, "sub", "sub", 16,
1816     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1817   },
1818 /* sbvck3 \$0,$rn,$rm */
1819   {
1820     MEP_INSN_SBVCK3, "sbvck3", "sbvck3", 16,
1821     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1822   },
1823 /* neg $rn,$rm */
1824   {
1825     MEP_INSN_NEG, "neg", "neg", 16,
1826     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1827   },
1828 /* slt3 \$0,$rn,$rm */
1829   {
1830     MEP_INSN_SLT3, "slt3", "slt3", 16,
1831     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1832   },
1833 /* sltu3 \$0,$rn,$rm */
1834   {
1835     MEP_INSN_SLTU3, "sltu3", "sltu3", 16,
1836     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1837   },
1838 /* slt3 \$0,$rn,$uimm5 */
1839   {
1840     MEP_INSN_SLT3I, "slt3i", "slt3", 16,
1841     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1842   },
1843 /* sltu3 \$0,$rn,$uimm5 */
1844   {
1845     MEP_INSN_SLTU3I, "sltu3i", "sltu3", 16,
1846     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1847   },
1848 /* sl1ad3 \$0,$rn,$rm */
1849   {
1850     MEP_INSN_SL1AD3, "sl1ad3", "sl1ad3", 16,
1851     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1852   },
1853 /* sl2ad3 \$0,$rn,$rm */
1854   {
1855     MEP_INSN_SL2AD3, "sl2ad3", "sl2ad3", 16,
1856     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1857   },
1858 /* add3 $rn,$rm,$simm16 */
1859   {
1860     MEP_INSN_ADD3X, "add3x", "add3", 32,
1861     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1862   },
1863 /* slt3 $rn,$rm,$simm16 */
1864   {
1865     MEP_INSN_SLT3X, "slt3x", "slt3", 32,
1866     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1867   },
1868 /* sltu3 $rn,$rm,$uimm16 */
1869   {
1870     MEP_INSN_SLTU3X, "sltu3x", "sltu3", 32,
1871     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1872   },
1873 /* or $rn,$rm */
1874   {
1875     MEP_INSN_OR, "or", "or", 16,
1876     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1877   },
1878 /* and $rn,$rm */
1879   {
1880     MEP_INSN_AND, "and", "and", 16,
1881     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1882   },
1883 /* xor $rn,$rm */
1884   {
1885     MEP_INSN_XOR, "xor", "xor", 16,
1886     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1887   },
1888 /* nor $rn,$rm */
1889   {
1890     MEP_INSN_NOR, "nor", "nor", 16,
1891     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1892   },
1893 /* or3 $rn,$rm,$uimm16 */
1894   {
1895     MEP_INSN_OR3, "or3", "or3", 32,
1896     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1897   },
1898 /* and3 $rn,$rm,$uimm16 */
1899   {
1900     MEP_INSN_AND3, "and3", "and3", 32,
1901     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1902   },
1903 /* xor3 $rn,$rm,$uimm16 */
1904   {
1905     MEP_INSN_XOR3, "xor3", "xor3", 32,
1906     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1907   },
1908 /* sra $rn,$rm */
1909   {
1910     MEP_INSN_SRA, "sra", "sra", 16,
1911     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1912   },
1913 /* srl $rn,$rm */
1914   {
1915     MEP_INSN_SRL, "srl", "srl", 16,
1916     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1917   },
1918 /* sll $rn,$rm */
1919   {
1920     MEP_INSN_SLL, "sll", "sll", 16,
1921     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1922   },
1923 /* sra $rn,$uimm5 */
1924   {
1925     MEP_INSN_SRAI, "srai", "sra", 16,
1926     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1927   },
1928 /* srl $rn,$uimm5 */
1929   {
1930     MEP_INSN_SRLI, "srli", "srl", 16,
1931     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1932   },
1933 /* sll $rn,$uimm5 */
1934   {
1935     MEP_INSN_SLLI, "slli", "sll", 16,
1936     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1937   },
1938 /* sll3 \$0,$rn,$uimm5 */
1939   {
1940     MEP_INSN_SLL3, "sll3", "sll3", 16,
1941     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1942   },
1943 /* fsft $rn,$rm */
1944   {
1945     MEP_INSN_FSFT, "fsft", "fsft", 16,
1946     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1947   },
1948 /* bra $pcrel12a2 */
1949   {
1950     MEP_INSN_BRA, "bra", "bra", 16,
1951     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1952   },
1953 /* beqz $rn,$pcrel8a2 */
1954   {
1955     MEP_INSN_BEQZ, "beqz", "beqz", 16,
1956     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1957   },
1958 /* bnez $rn,$pcrel8a2 */
1959   {
1960     MEP_INSN_BNEZ, "bnez", "bnez", 16,
1961     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1962   },
1963 /* beqi $rn,$uimm4,$pcrel17a2 */
1964   {
1965     MEP_INSN_BEQI, "beqi", "beqi", 32,
1966     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1967   },
1968 /* bnei $rn,$uimm4,$pcrel17a2 */
1969   {
1970     MEP_INSN_BNEI, "bnei", "bnei", 32,
1971     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1972   },
1973 /* blti $rn,$uimm4,$pcrel17a2 */
1974   {
1975     MEP_INSN_BLTI, "blti", "blti", 32,
1976     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1977   },
1978 /* bgei $rn,$uimm4,$pcrel17a2 */
1979   {
1980     MEP_INSN_BGEI, "bgei", "bgei", 32,
1981     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1982   },
1983 /* beq $rn,$rm,$pcrel17a2 */
1984   {
1985     MEP_INSN_BEQ, "beq", "beq", 32,
1986     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1987   },
1988 /* bne $rn,$rm,$pcrel17a2 */
1989   {
1990     MEP_INSN_BNE, "bne", "bne", 32,
1991     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1992   },
1993 /* bsr $pcrel12a2 */
1994   {
1995     MEP_INSN_BSR12, "bsr12", "bsr", 16,
1996     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1997   },
1998 /* bsr $pcrel24a2 */
1999   {
2000     MEP_INSN_BSR24, "bsr24", "bsr", 32,
2001     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2002   },
2003 /* jmp $rm */
2004   {
2005     MEP_INSN_JMP, "jmp", "jmp", 16,
2006     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2007   },
2008 /* jmp $pcabs24a2 */
2009   {
2010     MEP_INSN_JMP24, "jmp24", "jmp", 32,
2011     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2012   },
2013 /* jsr $rm */
2014   {
2015     MEP_INSN_JSR, "jsr", "jsr", 16,
2016     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2017   },
2018 /* ret */
2019   {
2020     MEP_INSN_RET, "ret", "ret", 16,
2021     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2022   },
2023 /* repeat $rn,$pcrel17a2 */
2024   {
2025     MEP_INSN_REPEAT, "repeat", "repeat", 32,
2026     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2027   },
2028 /* erepeat $pcrel17a2 */
2029   {
2030     MEP_INSN_EREPEAT, "erepeat", "erepeat", 32,
2031     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2032   },
2033 /* stc $rn,\$lp */
2034   {
2035     MEP_INSN_STC_LP, "stc_lp", "stc", 16,
2036     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2037   },
2038 /* stc $rn,\$hi */
2039   {
2040     MEP_INSN_STC_HI, "stc_hi", "stc", 16,
2041     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2042   },
2043 /* stc $rn,\$lo */
2044   {
2045     MEP_INSN_STC_LO, "stc_lo", "stc", 16,
2046     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2047   },
2048 /* stc $rn,$csrn */
2049   {
2050     MEP_INSN_STC, "stc", "stc", 16,
2051     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2052   },
2053 /* ldc $rn,\$lp */
2054   {
2055     MEP_INSN_LDC_LP, "ldc_lp", "ldc", 16,
2056     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2057   },
2058 /* ldc $rn,\$hi */
2059   {
2060     MEP_INSN_LDC_HI, "ldc_hi", "ldc", 16,
2061     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2062   },
2063 /* ldc $rn,\$lo */
2064   {
2065     MEP_INSN_LDC_LO, "ldc_lo", "ldc", 16,
2066     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2067   },
2068 /* ldc $rn,$csrn */
2069   {
2070     MEP_INSN_LDC, "ldc", "ldc", 16,
2071     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2072   },
2073 /* di */
2074   {
2075     MEP_INSN_DI, "di", "di", 16,
2076     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2077   },
2078 /* ei */
2079   {
2080     MEP_INSN_EI, "ei", "ei", 16,
2081     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2082   },
2083 /* reti */
2084   {
2085     MEP_INSN_RETI, "reti", "reti", 16,
2086     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2087   },
2088 /* halt */
2089   {
2090     MEP_INSN_HALT, "halt", "halt", 16,
2091     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2092   },
2093 /* sleep */
2094   {
2095     MEP_INSN_SLEEP, "sleep", "sleep", 16,
2096     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2097   },
2098 /* swi $uimm2 */
2099   {
2100     MEP_INSN_SWI, "swi", "swi", 16,
2101     { 0|A(VOLATILE)|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2102   },
2103 /* break */
2104   {
2105     MEP_INSN_BREAK, "break", "break", 16,
2106     { 0|A(VOLATILE)|A(MAY_TRAP)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2107   },
2108 /* syncm */
2109   {
2110     MEP_INSN_SYNCM, "syncm", "syncm", 16,
2111     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2112   },
2113 /* stcb $rn,$uimm16 */
2114   {
2115     MEP_INSN_STCB, "stcb", "stcb", 32,
2116     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2117   },
2118 /* ldcb $rn,$uimm16 */
2119   {
2120     MEP_INSN_LDCB, "ldcb", "ldcb", 32,
2121     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2122   },
2123 /* bsetm ($rma),$uimm3 */
2124   {
2125     MEP_INSN_BSETM, "bsetm", "bsetm", 16,
2126     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2127   },
2128 /* bclrm ($rma),$uimm3 */
2129   {
2130     MEP_INSN_BCLRM, "bclrm", "bclrm", 16,
2131     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2132   },
2133 /* bnotm ($rma),$uimm3 */
2134   {
2135     MEP_INSN_BNOTM, "bnotm", "bnotm", 16,
2136     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2137   },
2138 /* btstm \$0,($rma),$uimm3 */
2139   {
2140     MEP_INSN_BTSTM, "btstm", "btstm", 16,
2141     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2142   },
2143 /* tas $rn,($rma) */
2144   {
2145     MEP_INSN_TAS, "tas", "tas", 16,
2146     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2147   },
2148 /* cache $cimm4,($rma) */
2149   {
2150     MEP_INSN_CACHE, "cache", "cache", 16,
2151     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2152   },
2153 /* mul $rn,$rm */
2154   {
2155     MEP_INSN_MUL, "mul", "mul", 16,
2156     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2157   },
2158 /* mulu $rn,$rm */
2159   {
2160     MEP_INSN_MULU, "mulu", "mulu", 16,
2161     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2162   },
2163 /* mulr $rn,$rm */
2164   {
2165     MEP_INSN_MULR, "mulr", "mulr", 16,
2166     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2167   },
2168 /* mulru $rn,$rm */
2169   {
2170     MEP_INSN_MULRU, "mulru", "mulru", 16,
2171     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2172   },
2173 /* madd $rn,$rm */
2174   {
2175     MEP_INSN_MADD, "madd", "madd", 32,
2176     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2177   },
2178 /* maddu $rn,$rm */
2179   {
2180     MEP_INSN_MADDU, "maddu", "maddu", 32,
2181     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2182   },
2183 /* maddr $rn,$rm */
2184   {
2185     MEP_INSN_MADDR, "maddr", "maddr", 32,
2186     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2187   },
2188 /* maddru $rn,$rm */
2189   {
2190     MEP_INSN_MADDRU, "maddru", "maddru", 32,
2191     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2192   },
2193 /* div $rn,$rm */
2194   {
2195     MEP_INSN_DIV, "div", "div", 16,
2196     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2197   },
2198 /* divu $rn,$rm */
2199   {
2200     MEP_INSN_DIVU, "divu", "divu", 16,
2201     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2202   },
2203 /* dret */
2204   {
2205     MEP_INSN_DRET, "dret", "dret", 16,
2206     { 0|A(OPTIONAL_DEBUG_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2207   },
2208 /* dbreak */
2209   {
2210     MEP_INSN_DBREAK, "dbreak", "dbreak", 16,
2211     { 0|A(VOLATILE)|A(MAY_TRAP)|A(OPTIONAL_DEBUG_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2212   },
2213 /* ldz $rn,$rm */
2214   {
2215     MEP_INSN_LDZ, "ldz", "ldz", 32,
2216     { 0|A(OPTIONAL_LDZ_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2217   },
2218 /* abs $rn,$rm */
2219   {
2220     MEP_INSN_ABS, "abs", "abs", 32,
2221     { 0|A(OPTIONAL_ABS_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2222   },
2223 /* ave $rn,$rm */
2224   {
2225     MEP_INSN_AVE, "ave", "ave", 32,
2226     { 0|A(OPTIONAL_AVE_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2227   },
2228 /* min $rn,$rm */
2229   {
2230     MEP_INSN_MIN, "min", "min", 32,
2231     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2232   },
2233 /* max $rn,$rm */
2234   {
2235     MEP_INSN_MAX, "max", "max", 32,
2236     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2237   },
2238 /* minu $rn,$rm */
2239   {
2240     MEP_INSN_MINU, "minu", "minu", 32,
2241     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2242   },
2243 /* maxu $rn,$rm */
2244   {
2245     MEP_INSN_MAXU, "maxu", "maxu", 32,
2246     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2247   },
2248 /* clip $rn,$cimm5 */
2249   {
2250     MEP_INSN_CLIP, "clip", "clip", 32,
2251     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2252   },
2253 /* clipu $rn,$cimm5 */
2254   {
2255     MEP_INSN_CLIPU, "clipu", "clipu", 32,
2256     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2257   },
2258 /* sadd $rn,$rm */
2259   {
2260     MEP_INSN_SADD, "sadd", "sadd", 32,
2261     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2262   },
2263 /* ssub $rn,$rm */
2264   {
2265     MEP_INSN_SSUB, "ssub", "ssub", 32,
2266     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2267   },
2268 /* saddu $rn,$rm */
2269   {
2270     MEP_INSN_SADDU, "saddu", "saddu", 32,
2271     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2272   },
2273 /* ssubu $rn,$rm */
2274   {
2275     MEP_INSN_SSUBU, "ssubu", "ssubu", 32,
2276     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2277   },
2278 /* swcp $crn,($rma) */
2279   {
2280     MEP_INSN_SWCP, "swcp", "swcp", 16,
2281     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2282   },
2283 /* lwcp $crn,($rma) */
2284   {
2285     MEP_INSN_LWCP, "lwcp", "lwcp", 16,
2286     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2287   },
2288 /* smcp $crn64,($rma) */
2289   {
2290     MEP_INSN_SMCP, "smcp", "smcp", 16,
2291     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2292   },
2293 /* lmcp $crn64,($rma) */
2294   {
2295     MEP_INSN_LMCP, "lmcp", "lmcp", 16,
2296     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2297   },
2298 /* swcpi $crn,($rma+) */
2299   {
2300     MEP_INSN_SWCPI, "swcpi", "swcpi", 16,
2301     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2302   },
2303 /* lwcpi $crn,($rma+) */
2304   {
2305     MEP_INSN_LWCPI, "lwcpi", "lwcpi", 16,
2306     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2307   },
2308 /* smcpi $crn64,($rma+) */
2309   {
2310     MEP_INSN_SMCPI, "smcpi", "smcpi", 16,
2311     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2312   },
2313 /* lmcpi $crn64,($rma+) */
2314   {
2315     MEP_INSN_LMCPI, "lmcpi", "lmcpi", 16,
2316     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2317   },
2318 /* swcp $crn,$sdisp16($rma) */
2319   {
2320     MEP_INSN_SWCP16, "swcp16", "swcp", 32,
2321     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2322   },
2323 /* lwcp $crn,$sdisp16($rma) */
2324   {
2325     MEP_INSN_LWCP16, "lwcp16", "lwcp", 32,
2326     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2327   },
2328 /* smcp $crn64,$sdisp16($rma) */
2329   {
2330     MEP_INSN_SMCP16, "smcp16", "smcp", 32,
2331     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2332   },
2333 /* lmcp $crn64,$sdisp16($rma) */
2334   {
2335     MEP_INSN_LMCP16, "lmcp16", "lmcp", 32,
2336     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2337   },
2338 /* sbcpa $crn,($rma+),$cdisp10 */
2339   {
2340     MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32,
2341     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2342   },
2343 /* lbcpa $crn,($rma+),$cdisp10 */
2344   {
2345     MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32,
2346     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2347   },
2348 /* shcpa $crn,($rma+),$cdisp10a2 */
2349   {
2350     MEP_INSN_SHCPA, "shcpa", "shcpa", 32,
2351     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2352   },
2353 /* lhcpa $crn,($rma+),$cdisp10a2 */
2354   {
2355     MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32,
2356     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2357   },
2358 /* swcpa $crn,($rma+),$cdisp10a4 */
2359   {
2360     MEP_INSN_SWCPA, "swcpa", "swcpa", 32,
2361     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2362   },
2363 /* lwcpa $crn,($rma+),$cdisp10a4 */
2364   {
2365     MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32,
2366     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2367   },
2368 /* smcpa $crn64,($rma+),$cdisp10a8 */
2369   {
2370     MEP_INSN_SMCPA, "smcpa", "smcpa", 32,
2371     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2372   },
2373 /* lmcpa $crn64,($rma+),$cdisp10a8 */
2374   {
2375     MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32,
2376     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2377   },
2378 /* sbcpm0 $crn,($rma+),$cdisp10 */
2379   {
2380     MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32,
2381     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2382   },
2383 /* lbcpm0 $crn,($rma+),$cdisp10 */
2384   {
2385     MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32,
2386     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2387   },
2388 /* shcpm0 $crn,($rma+),$cdisp10a2 */
2389   {
2390     MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32,
2391     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2392   },
2393 /* lhcpm0 $crn,($rma+),$cdisp10a2 */
2394   {
2395     MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32,
2396     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2397   },
2398 /* swcpm0 $crn,($rma+),$cdisp10a4 */
2399   {
2400     MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32,
2401     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2402   },
2403 /* lwcpm0 $crn,($rma+),$cdisp10a4 */
2404   {
2405     MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32,
2406     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2407   },
2408 /* smcpm0 $crn64,($rma+),$cdisp10a8 */
2409   {
2410     MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32,
2411     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2412   },
2413 /* lmcpm0 $crn64,($rma+),$cdisp10a8 */
2414   {
2415     MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32,
2416     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2417   },
2418 /* sbcpm1 $crn,($rma+),$cdisp10 */
2419   {
2420     MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32,
2421     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2422   },
2423 /* lbcpm1 $crn,($rma+),$cdisp10 */
2424   {
2425     MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32,
2426     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2427   },
2428 /* shcpm1 $crn,($rma+),$cdisp10a2 */
2429   {
2430     MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32,
2431     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2432   },
2433 /* lhcpm1 $crn,($rma+),$cdisp10a2 */
2434   {
2435     MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32,
2436     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2437   },
2438 /* swcpm1 $crn,($rma+),$cdisp10a4 */
2439   {
2440     MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32,
2441     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2442   },
2443 /* lwcpm1 $crn,($rma+),$cdisp10a4 */
2444   {
2445     MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32,
2446     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2447   },
2448 /* smcpm1 $crn64,($rma+),$cdisp10a8 */
2449   {
2450     MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32,
2451     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2452   },
2453 /* lmcpm1 $crn64,($rma+),$cdisp10a8 */
2454   {
2455     MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32,
2456     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2457   },
2458 /* bcpeq $cccc,$pcrel17a2 */
2459   {
2460     MEP_INSN_BCPEQ, "bcpeq", "bcpeq", 32,
2461     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2462   },
2463 /* bcpne $cccc,$pcrel17a2 */
2464   {
2465     MEP_INSN_BCPNE, "bcpne", "bcpne", 32,
2466     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2467   },
2468 /* bcpat $cccc,$pcrel17a2 */
2469   {
2470     MEP_INSN_BCPAT, "bcpat", "bcpat", 32,
2471     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2472   },
2473 /* bcpaf $cccc,$pcrel17a2 */
2474   {
2475     MEP_INSN_BCPAF, "bcpaf", "bcpaf", 32,
2476     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2477   },
2478 /* synccp */
2479   {
2480     MEP_INSN_SYNCCP, "synccp", "synccp", 16,
2481     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2482   },
2483 /* jsrv $rm */
2484   {
2485     MEP_INSN_JSRV, "jsrv", "jsrv", 16,
2486     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2487   },
2488 /* bsrv $pcrel24a2 */
2489   {
2490     MEP_INSN_BSRV, "bsrv", "bsrv", 32,
2491     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2492   },
2493 /* --syscall-- */
2494   {
2495     MEP_INSN_SIM_SYSCALL, "sim-syscall", "--syscall--", 16,
2496     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2497   },
2498 /* --reserved-- */
2499   {
2500     MEP_INSN_RI_0, "ri-0", "--reserved--", 16,
2501     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2502   },
2503 /* --reserved-- */
2504   {
2505     MEP_INSN_RI_1, "ri-1", "--reserved--", 16,
2506     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2507   },
2508 /* --reserved-- */
2509   {
2510     MEP_INSN_RI_2, "ri-2", "--reserved--", 16,
2511     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2512   },
2513 /* --reserved-- */
2514   {
2515     MEP_INSN_RI_3, "ri-3", "--reserved--", 16,
2516     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2517   },
2518 /* --reserved-- */
2519   {
2520     MEP_INSN_RI_4, "ri-4", "--reserved--", 16,
2521     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2522   },
2523 /* --reserved-- */
2524   {
2525     MEP_INSN_RI_5, "ri-5", "--reserved--", 16,
2526     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2527   },
2528 /* --reserved-- */
2529   {
2530     MEP_INSN_RI_6, "ri-6", "--reserved--", 16,
2531     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2532   },
2533 /* --reserved-- */
2534   {
2535     MEP_INSN_RI_7, "ri-7", "--reserved--", 16,
2536     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2537   },
2538 /* --reserved-- */
2539   {
2540     MEP_INSN_RI_8, "ri-8", "--reserved--", 16,
2541     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2542   },
2543 /* --reserved-- */
2544   {
2545     MEP_INSN_RI_9, "ri-9", "--reserved--", 16,
2546     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2547   },
2548 /* --reserved-- */
2549   {
2550     MEP_INSN_RI_10, "ri-10", "--reserved--", 16,
2551     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2552   },
2553 /* --reserved-- */
2554   {
2555     MEP_INSN_RI_11, "ri-11", "--reserved--", 16,
2556     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2557   },
2558 /* --reserved-- */
2559   {
2560     MEP_INSN_RI_12, "ri-12", "--reserved--", 16,
2561     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2562   },
2563 /* --reserved-- */
2564   {
2565     MEP_INSN_RI_13, "ri-13", "--reserved--", 16,
2566     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2567   },
2568 /* --reserved-- */
2569   {
2570     MEP_INSN_RI_14, "ri-14", "--reserved--", 16,
2571     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2572   },
2573 /* --reserved-- */
2574   {
2575     MEP_INSN_RI_15, "ri-15", "--reserved--", 16,
2576     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2577   },
2578 /* --reserved-- */
2579   {
2580     MEP_INSN_RI_17, "ri-17", "--reserved--", 16,
2581     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2582   },
2583 /* --reserved-- */
2584   {
2585     MEP_INSN_RI_20, "ri-20", "--reserved--", 16,
2586     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2587   },
2588 /* --reserved-- */
2589   {
2590     MEP_INSN_RI_21, "ri-21", "--reserved--", 16,
2591     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2592   },
2593 /* --reserved-- */
2594   {
2595     MEP_INSN_RI_22, "ri-22", "--reserved--", 16,
2596     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2597   },
2598 /* --reserved-- */
2599   {
2600     MEP_INSN_RI_23, "ri-23", "--reserved--", 16,
2601     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2602   },
2603 /* --reserved-- */
2604   {
2605     MEP_INSN_RI_26, "ri-26", "--reserved--", 16,
2606     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2607   },
2608 /* cmov $crnx64,$rm */
2609   {
2610     MEP_INSN_CMOV_CRN_RM, "cmov-crn-rm", "cmov", 32,
2611     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2612   },
2613 /* cmov $rm,$crnx64 */
2614   {
2615     MEP_INSN_CMOV_RN_CRM, "cmov-rn-crm", "cmov", 32,
2616     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2617   },
2618 /* cmovc $ivc2c3ccrn,$rm */
2619   {
2620     MEP_INSN_CMOVC_CCRN_RM, "cmovc-ccrn-rm", "cmovc", 32,
2621     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2622   },
2623 /* cmovc $rm,$ivc2c3ccrn */
2624   {
2625     MEP_INSN_CMOVC_RN_CCRM, "cmovc-rn-ccrm", "cmovc", 32,
2626     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2627   },
2628 /* cmovh $crnx64,$rm */
2629   {
2630     MEP_INSN_CMOVH_CRN_RM, "cmovh-crn-rm", "cmovh", 32,
2631     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2632   },
2633 /* cmovh $rm,$crnx64 */
2634   {
2635     MEP_INSN_CMOVH_RN_CRM, "cmovh-rn-crm", "cmovh", 32,
2636     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2637   },
2638 /* cmov $ivc2crn,$ivc2rm */
2639   {
2640     MEP_INSN_CMOV_CRN_RM_P0, "cmov-crn-rm-p0", "cmov", 32,
2641     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2642   },
2643 /* cmov $ivc2rm,$ivc2crn */
2644   {
2645     MEP_INSN_CMOV_RN_CRM_P0, "cmov-rn-crm-p0", "cmov", 32,
2646     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2647   },
2648 /* cmovc $ivc2ccrn,$ivc2rm */
2649   {
2650     MEP_INSN_CMOVC_CCRN_RM_P0, "cmovc-ccrn-rm-p0", "cmovc", 32,
2651     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2652   },
2653 /* cmovc $ivc2rm,$ivc2ccrn */
2654   {
2655     MEP_INSN_CMOVC_RN_CCRM_P0, "cmovc-rn-ccrm-p0", "cmovc", 32,
2656     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2657   },
2658 /* cmovh $ivc2crn,$ivc2rm */
2659   {
2660     MEP_INSN_CMOVH_CRN_RM_P0, "cmovh-crn-rm-p0", "cmovh", 32,
2661     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2662   },
2663 /* cmovh $ivc2rm,$ivc2crn */
2664   {
2665     MEP_INSN_CMOVH_RN_CRM_P0, "cmovh-rn-crm-p0", "cmovh", 32,
2666     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2667   },
2668 /* cpadd3.b $croc,$crqc,$crpc */
2669   {
2670     MEP_INSN_CPADD3_B_C3, "cpadd3_b_C3", "cpadd3.b", 32,
2671     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2672   },
2673 /* cpadd3.h $croc,$crqc,$crpc */
2674   {
2675     MEP_INSN_CPADD3_H_C3, "cpadd3_h_C3", "cpadd3.h", 32,
2676     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2677   },
2678 /* cpadd3.w $croc,$crqc,$crpc */
2679   {
2680     MEP_INSN_CPADD3_W_C3, "cpadd3_w_C3", "cpadd3.w", 32,
2681     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2682   },
2683 /* cdadd3 $croc,$crqc,$crpc */
2684   {
2685     MEP_INSN_CDADD3_C3, "cdadd3_C3", "cdadd3", 32,
2686     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2687   },
2688 /* cpsub3.b $croc,$crqc,$crpc */
2689   {
2690     MEP_INSN_CPSUB3_B_C3, "cpsub3_b_C3", "cpsub3.b", 32,
2691     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2692   },
2693 /* cpsub3.h $croc,$crqc,$crpc */
2694   {
2695     MEP_INSN_CPSUB3_H_C3, "cpsub3_h_C3", "cpsub3.h", 32,
2696     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2697   },
2698 /* cpsub3.w $croc,$crqc,$crpc */
2699   {
2700     MEP_INSN_CPSUB3_W_C3, "cpsub3_w_C3", "cpsub3.w", 32,
2701     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2702   },
2703 /* cdsub3 $croc,$crqc,$crpc */
2704   {
2705     MEP_INSN_CDSUB3_C3, "cdsub3_C3", "cdsub3", 32,
2706     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2707   },
2708 /* cpand3 $croc,$crqc,$crpc */
2709   {
2710     MEP_INSN_CPAND3_C3, "cpand3_C3", "cpand3", 32,
2711     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2712   },
2713 /* cpor3 $croc,$crqc,$crpc */
2714   {
2715     MEP_INSN_CPOR3_C3, "cpor3_C3", "cpor3", 32,
2716     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2717   },
2718 /* cpnor3 $croc,$crqc,$crpc */
2719   {
2720     MEP_INSN_CPNOR3_C3, "cpnor3_C3", "cpnor3", 32,
2721     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2722   },
2723 /* cpxor3 $croc,$crqc,$crpc */
2724   {
2725     MEP_INSN_CPXOR3_C3, "cpxor3_C3", "cpxor3", 32,
2726     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2727   },
2728 /* cpsel $croc,$crqc,$crpc */
2729   {
2730     MEP_INSN_CPSEL_C3, "cpsel_C3", "cpsel", 32,
2731     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2732   },
2733 /* cpfsftbi $croc,$crqc,$crpc,$imm3p4 */
2734   {
2735     MEP_INSN_CPFSFTBI_C3, "cpfsftbi_C3", "cpfsftbi", 32,
2736     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2737   },
2738 /* cpfsftbs0 $croc,$crqc,$crpc */
2739   {
2740     MEP_INSN_CPFSFTBS0_C3, "cpfsftbs0_C3", "cpfsftbs0", 32,
2741     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2742   },
2743 /* cpfsftbs1 $croc,$crqc,$crpc */
2744   {
2745     MEP_INSN_CPFSFTBS1_C3, "cpfsftbs1_C3", "cpfsftbs1", 32,
2746     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2747   },
2748 /* cpunpacku.b $croc,$crqc,$crpc */
2749   {
2750     MEP_INSN_CPUNPACKU_B_C3, "cpunpacku_b_C3", "cpunpacku.b", 32,
2751     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2752   },
2753 /* cpunpacku.h $croc,$crqc,$crpc */
2754   {
2755     MEP_INSN_CPUNPACKU_H_C3, "cpunpacku_h_C3", "cpunpacku.h", 32,
2756     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2757   },
2758 /* cpunpacku.w $croc,$crqc,$crpc */
2759   {
2760     MEP_INSN_CPUNPACKU_W_C3, "cpunpacku_w_C3", "cpunpacku.w", 32,
2761     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2762   },
2763 /* cpunpackl.b $croc,$crqc,$crpc */
2764   {
2765     MEP_INSN_CPUNPACKL_B_C3, "cpunpackl_b_C3", "cpunpackl.b", 32,
2766     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2767   },
2768 /* cpunpackl.h $croc,$crqc,$crpc */
2769   {
2770     MEP_INSN_CPUNPACKL_H_C3, "cpunpackl_h_C3", "cpunpackl.h", 32,
2771     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2772   },
2773 /* cpunpackl.w $croc,$crqc,$crpc */
2774   {
2775     MEP_INSN_CPUNPACKL_W_C3, "cpunpackl_w_C3", "cpunpackl.w", 32,
2776     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2777   },
2778 /* cppacku.b $croc,$crqc,$crpc */
2779   {
2780     MEP_INSN_CPPACKU_B_C3, "cppacku_b_C3", "cppacku.b", 32,
2781     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2782   },
2783 /* cppack.b $croc,$crqc,$crpc */
2784   {
2785     MEP_INSN_CPPACK_B_C3, "cppack_b_C3", "cppack.b", 32,
2786     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2787   },
2788 /* cppack.h $croc,$crqc,$crpc */
2789   {
2790     MEP_INSN_CPPACK_H_C3, "cppack_h_C3", "cppack.h", 32,
2791     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2792   },
2793 /* cpsrl3.b $croc,$crqc,$crpc */
2794   {
2795     MEP_INSN_CPSRL3_B_C3, "cpsrl3_b_C3", "cpsrl3.b", 32,
2796     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2797   },
2798 /* cpssrl3.b $croc,$crqc,$crpc */
2799   {
2800     MEP_INSN_CPSSRL3_B_C3, "cpssrl3_b_C3", "cpssrl3.b", 32,
2801     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2802   },
2803 /* cpsrl3.h $croc,$crqc,$crpc */
2804   {
2805     MEP_INSN_CPSRL3_H_C3, "cpsrl3_h_C3", "cpsrl3.h", 32,
2806     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2807   },
2808 /* cpssrl3.h $croc,$crqc,$crpc */
2809   {
2810     MEP_INSN_CPSSRL3_H_C3, "cpssrl3_h_C3", "cpssrl3.h", 32,
2811     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2812   },
2813 /* cpsrl3.w $croc,$crqc,$crpc */
2814   {
2815     MEP_INSN_CPSRL3_W_C3, "cpsrl3_w_C3", "cpsrl3.w", 32,
2816     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2817   },
2818 /* cpssrl3.w $croc,$crqc,$crpc */
2819   {
2820     MEP_INSN_CPSSRL3_W_C3, "cpssrl3_w_C3", "cpssrl3.w", 32,
2821     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2822   },
2823 /* cdsrl3 $croc,$crqc,$crpc */
2824   {
2825     MEP_INSN_CDSRL3_C3, "cdsrl3_C3", "cdsrl3", 32,
2826     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2827   },
2828 /* cpsra3.b $croc,$crqc,$crpc */
2829   {
2830     MEP_INSN_CPSRA3_B_C3, "cpsra3_b_C3", "cpsra3.b", 32,
2831     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2832   },
2833 /* cpssra3.b $croc,$crqc,$crpc */
2834   {
2835     MEP_INSN_CPSSRA3_B_C3, "cpssra3_b_C3", "cpssra3.b", 32,
2836     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2837   },
2838 /* cpsra3.h $croc,$crqc,$crpc */
2839   {
2840     MEP_INSN_CPSRA3_H_C3, "cpsra3_h_C3", "cpsra3.h", 32,
2841     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2842   },
2843 /* cpssra3.h $croc,$crqc,$crpc */
2844   {
2845     MEP_INSN_CPSSRA3_H_C3, "cpssra3_h_C3", "cpssra3.h", 32,
2846     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2847   },
2848 /* cpsra3.w $croc,$crqc,$crpc */
2849   {
2850     MEP_INSN_CPSRA3_W_C3, "cpsra3_w_C3", "cpsra3.w", 32,
2851     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2852   },
2853 /* cpssra3.w $croc,$crqc,$crpc */
2854   {
2855     MEP_INSN_CPSSRA3_W_C3, "cpssra3_w_C3", "cpssra3.w", 32,
2856     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2857   },
2858 /* cdsra3 $croc,$crqc,$crpc */
2859   {
2860     MEP_INSN_CDSRA3_C3, "cdsra3_C3", "cdsra3", 32,
2861     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2862   },
2863 /* cpsll3.b $croc,$crqc,$crpc */
2864   {
2865     MEP_INSN_CPSLL3_B_C3, "cpsll3_b_C3", "cpsll3.b", 32,
2866     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2867   },
2868 /* cpssll3.b $croc,$crqc,$crpc */
2869   {
2870     MEP_INSN_CPSSLL3_B_C3, "cpssll3_b_C3", "cpssll3.b", 32,
2871     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2872   },
2873 /* cpsll3.h $croc,$crqc,$crpc */
2874   {
2875     MEP_INSN_CPSLL3_H_C3, "cpsll3_h_C3", "cpsll3.h", 32,
2876     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2877   },
2878 /* cpssll3.h $croc,$crqc,$crpc */
2879   {
2880     MEP_INSN_CPSSLL3_H_C3, "cpssll3_h_C3", "cpssll3.h", 32,
2881     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2882   },
2883 /* cpsll3.w $croc,$crqc,$crpc */
2884   {
2885     MEP_INSN_CPSLL3_W_C3, "cpsll3_w_C3", "cpsll3.w", 32,
2886     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2887   },
2888 /* cpssll3.w $croc,$crqc,$crpc */
2889   {
2890     MEP_INSN_CPSSLL3_W_C3, "cpssll3_w_C3", "cpssll3.w", 32,
2891     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2892   },
2893 /* cdsll3 $croc,$crqc,$crpc */
2894   {
2895     MEP_INSN_CDSLL3_C3, "cdsll3_C3", "cdsll3", 32,
2896     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2897   },
2898 /* cpsla3.h $croc,$crqc,$crpc */
2899   {
2900     MEP_INSN_CPSLA3_H_C3, "cpsla3_h_C3", "cpsla3.h", 32,
2901     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2902   },
2903 /* cpsla3.w $croc,$crqc,$crpc */
2904   {
2905     MEP_INSN_CPSLA3_W_C3, "cpsla3_w_C3", "cpsla3.w", 32,
2906     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2907   },
2908 /* cpsadd3.h $croc,$crqc,$crpc */
2909   {
2910     MEP_INSN_CPSADD3_H_C3, "cpsadd3_h_C3", "cpsadd3.h", 32,
2911     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2912   },
2913 /* cpsadd3.w $croc,$crqc,$crpc */
2914   {
2915     MEP_INSN_CPSADD3_W_C3, "cpsadd3_w_C3", "cpsadd3.w", 32,
2916     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2917   },
2918 /* cpssub3.h $croc,$crqc,$crpc */
2919   {
2920     MEP_INSN_CPSSUB3_H_C3, "cpssub3_h_C3", "cpssub3.h", 32,
2921     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2922   },
2923 /* cpssub3.w $croc,$crqc,$crpc */
2924   {
2925     MEP_INSN_CPSSUB3_W_C3, "cpssub3_w_C3", "cpssub3.w", 32,
2926     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2927   },
2928 /* cpextuaddu3.b $croc,$crqc,$crpc */
2929   {
2930     MEP_INSN_CPEXTUADDU3_B_C3, "cpextuaddu3_b_C3", "cpextuaddu3.b", 32,
2931     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2932   },
2933 /* cpextuadd3.b $croc,$crqc,$crpc */
2934   {
2935     MEP_INSN_CPEXTUADD3_B_C3, "cpextuadd3_b_C3", "cpextuadd3.b", 32,
2936     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2937   },
2938 /* cpextladdu3.b $croc,$crqc,$crpc */
2939   {
2940     MEP_INSN_CPEXTLADDU3_B_C3, "cpextladdu3_b_C3", "cpextladdu3.b", 32,
2941     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2942   },
2943 /* cpextladd3.b $croc,$crqc,$crpc */
2944   {
2945     MEP_INSN_CPEXTLADD3_B_C3, "cpextladd3_b_C3", "cpextladd3.b", 32,
2946     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2947   },
2948 /* cpextusubu3.b $croc,$crqc,$crpc */
2949   {
2950     MEP_INSN_CPEXTUSUBU3_B_C3, "cpextusubu3_b_C3", "cpextusubu3.b", 32,
2951     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2952   },
2953 /* cpextusub3.b $croc,$crqc,$crpc */
2954   {
2955     MEP_INSN_CPEXTUSUB3_B_C3, "cpextusub3_b_C3", "cpextusub3.b", 32,
2956     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2957   },
2958 /* cpextlsubu3.b $croc,$crqc,$crpc */
2959   {
2960     MEP_INSN_CPEXTLSUBU3_B_C3, "cpextlsubu3_b_C3", "cpextlsubu3.b", 32,
2961     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2962   },
2963 /* cpextlsub3.b $croc,$crqc,$crpc */
2964   {
2965     MEP_INSN_CPEXTLSUB3_B_C3, "cpextlsub3_b_C3", "cpextlsub3.b", 32,
2966     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2967   },
2968 /* cpaveu3.b $croc,$crqc,$crpc */
2969   {
2970     MEP_INSN_CPAVEU3_B_C3, "cpaveu3_b_C3", "cpaveu3.b", 32,
2971     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2972   },
2973 /* cpave3.b $croc,$crqc,$crpc */
2974   {
2975     MEP_INSN_CPAVE3_B_C3, "cpave3_b_C3", "cpave3.b", 32,
2976     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2977   },
2978 /* cpave3.h $croc,$crqc,$crpc */
2979   {
2980     MEP_INSN_CPAVE3_H_C3, "cpave3_h_C3", "cpave3.h", 32,
2981     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2982   },
2983 /* cpave3.w $croc,$crqc,$crpc */
2984   {
2985     MEP_INSN_CPAVE3_W_C3, "cpave3_w_C3", "cpave3.w", 32,
2986     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2987   },
2988 /* cpaddsru3.b $croc,$crqc,$crpc */
2989   {
2990     MEP_INSN_CPADDSRU3_B_C3, "cpaddsru3_b_C3", "cpaddsru3.b", 32,
2991     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2992   },
2993 /* cpaddsr3.b $croc,$crqc,$crpc */
2994   {
2995     MEP_INSN_CPADDSR3_B_C3, "cpaddsr3_b_C3", "cpaddsr3.b", 32,
2996     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2997   },
2998 /* cpaddsr3.h $croc,$crqc,$crpc */
2999   {
3000     MEP_INSN_CPADDSR3_H_C3, "cpaddsr3_h_C3", "cpaddsr3.h", 32,
3001     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3002   },
3003 /* cpaddsr3.w $croc,$crqc,$crpc */
3004   {
3005     MEP_INSN_CPADDSR3_W_C3, "cpaddsr3_w_C3", "cpaddsr3.w", 32,
3006     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3007   },
3008 /* cpabsu3.b $croc,$crqc,$crpc */
3009   {
3010     MEP_INSN_CPABSU3_B_C3, "cpabsu3_b_C3", "cpabsu3.b", 32,
3011     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3012   },
3013 /* cpabs3.b $croc,$crqc,$crpc */
3014   {
3015     MEP_INSN_CPABS3_B_C3, "cpabs3_b_C3", "cpabs3.b", 32,
3016     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3017   },
3018 /* cpabs3.h $croc,$crqc,$crpc */
3019   {
3020     MEP_INSN_CPABS3_H_C3, "cpabs3_h_C3", "cpabs3.h", 32,
3021     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3022   },
3023 /* cpmaxu3.b $croc,$crqc,$crpc */
3024   {
3025     MEP_INSN_CPMAXU3_B_C3, "cpmaxu3_b_C3", "cpmaxu3.b", 32,
3026     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3027   },
3028 /* cpmax3.b $croc,$crqc,$crpc */
3029   {
3030     MEP_INSN_CPMAX3_B_C3, "cpmax3_b_C3", "cpmax3.b", 32,
3031     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3032   },
3033 /* cpmax3.h $croc,$crqc,$crpc */
3034   {
3035     MEP_INSN_CPMAX3_H_C3, "cpmax3_h_C3", "cpmax3.h", 32,
3036     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3037   },
3038 /* cpmaxu3.w $croc,$crqc,$crpc */
3039   {
3040     MEP_INSN_CPMAXU3_W_C3, "cpmaxu3_w_C3", "cpmaxu3.w", 32,
3041     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3042   },
3043 /* cpmax3.w $croc,$crqc,$crpc */
3044   {
3045     MEP_INSN_CPMAX3_W_C3, "cpmax3_w_C3", "cpmax3.w", 32,
3046     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3047   },
3048 /* cpminu3.b $croc,$crqc,$crpc */
3049   {
3050     MEP_INSN_CPMINU3_B_C3, "cpminu3_b_C3", "cpminu3.b", 32,
3051     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3052   },
3053 /* cpmin3.b $croc,$crqc,$crpc */
3054   {
3055     MEP_INSN_CPMIN3_B_C3, "cpmin3_b_C3", "cpmin3.b", 32,
3056     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3057   },
3058 /* cpmin3.h $croc,$crqc,$crpc */
3059   {
3060     MEP_INSN_CPMIN3_H_C3, "cpmin3_h_C3", "cpmin3.h", 32,
3061     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3062   },
3063 /* cpminu3.w $croc,$crqc,$crpc */
3064   {
3065     MEP_INSN_CPMINU3_W_C3, "cpminu3_w_C3", "cpminu3.w", 32,
3066     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3067   },
3068 /* cpmin3.w $croc,$crqc,$crpc */
3069   {
3070     MEP_INSN_CPMIN3_W_C3, "cpmin3_w_C3", "cpmin3.w", 32,
3071     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3072   },
3073 /* cpmovfrcsar0 $croc */
3074   {
3075     MEP_INSN_CPMOVFRCSAR0_C3, "cpmovfrcsar0_C3", "cpmovfrcsar0", 32,
3076     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3077   },
3078 /* cpmovfrcsar1 $croc */
3079   {
3080     MEP_INSN_CPMOVFRCSAR1_C3, "cpmovfrcsar1_C3", "cpmovfrcsar1", 32,
3081     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3082   },
3083 /* cpmovfrcc $croc */
3084   {
3085     MEP_INSN_CPMOVFRCC_C3, "cpmovfrcc_C3", "cpmovfrcc", 32,
3086     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3087   },
3088 /* cpmovtocsar0 $crqc */
3089   {
3090     MEP_INSN_CPMOVTOCSAR0_C3, "cpmovtocsar0_C3", "cpmovtocsar0", 32,
3091     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3092   },
3093 /* cpmovtocsar1 $crqc */
3094   {
3095     MEP_INSN_CPMOVTOCSAR1_C3, "cpmovtocsar1_C3", "cpmovtocsar1", 32,
3096     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3097   },
3098 /* cpmovtocc $crqc */
3099   {
3100     MEP_INSN_CPMOVTOCC_C3, "cpmovtocc_C3", "cpmovtocc", 32,
3101     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3102   },
3103 /* cpmov $croc,$crqc */
3104   {
3105     MEP_INSN_CPMOV_C3, "cpmov_C3", "cpmov", 32,
3106     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3107   },
3108 /* cpabsz.b $croc,$crqc */
3109   {
3110     MEP_INSN_CPABSZ_B_C3, "cpabsz_b_C3", "cpabsz.b", 32,
3111     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3112   },
3113 /* cpabsz.h $croc,$crqc */
3114   {
3115     MEP_INSN_CPABSZ_H_C3, "cpabsz_h_C3", "cpabsz.h", 32,
3116     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3117   },
3118 /* cpabsz.w $croc,$crqc */
3119   {
3120     MEP_INSN_CPABSZ_W_C3, "cpabsz_w_C3", "cpabsz.w", 32,
3121     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3122   },
3123 /* cpldz.h $croc,$crqc */
3124   {
3125     MEP_INSN_CPLDZ_H_C3, "cpldz_h_C3", "cpldz.h", 32,
3126     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3127   },
3128 /* cpldz.w $croc,$crqc */
3129   {
3130     MEP_INSN_CPLDZ_W_C3, "cpldz_w_C3", "cpldz.w", 32,
3131     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3132   },
3133 /* cpnorm.h $croc,$crqc */
3134   {
3135     MEP_INSN_CPNORM_H_C3, "cpnorm_h_C3", "cpnorm.h", 32,
3136     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3137   },
3138 /* cpnorm.w $croc,$crqc */
3139   {
3140     MEP_INSN_CPNORM_W_C3, "cpnorm_w_C3", "cpnorm.w", 32,
3141     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3142   },
3143 /* cphaddu.b $croc,$crqc */
3144   {
3145     MEP_INSN_CPHADDU_B_C3, "cphaddu_b_C3", "cphaddu.b", 32,
3146     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3147   },
3148 /* cphadd.b $croc,$crqc */
3149   {
3150     MEP_INSN_CPHADD_B_C3, "cphadd_b_C3", "cphadd.b", 32,
3151     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3152   },
3153 /* cphadd.h $croc,$crqc */
3154   {
3155     MEP_INSN_CPHADD_H_C3, "cphadd_h_C3", "cphadd.h", 32,
3156     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3157   },
3158 /* cphadd.w $croc,$crqc */
3159   {
3160     MEP_INSN_CPHADD_W_C3, "cphadd_w_C3", "cphadd.w", 32,
3161     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3162   },
3163 /* cpccadd.b $crqc */
3164   {
3165     MEP_INSN_CPCCADD_B_C3, "cpccadd_b_C3", "cpccadd.b", 32,
3166     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRSTCOPY, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3167   },
3168 /* cpbcast.b $croc,$crqc */
3169   {
3170     MEP_INSN_CPBCAST_B_C3, "cpbcast_b_C3", "cpbcast.b", 32,
3171     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3172   },
3173 /* cpbcast.h $croc,$crqc */
3174   {
3175     MEP_INSN_CPBCAST_H_C3, "cpbcast_h_C3", "cpbcast.h", 32,
3176     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3177   },
3178 /* cpbcast.w $croc,$crqc */
3179   {
3180     MEP_INSN_CPBCAST_W_C3, "cpbcast_w_C3", "cpbcast.w", 32,
3181     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3182   },
3183 /* cpextuu.b $croc,$crqc */
3184   {
3185     MEP_INSN_CPEXTUU_B_C3, "cpextuu_b_C3", "cpextuu.b", 32,
3186     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3187   },
3188 /* cpextu.b $croc,$crqc */
3189   {
3190     MEP_INSN_CPEXTU_B_C3, "cpextu_b_C3", "cpextu.b", 32,
3191     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3192   },
3193 /* cpextuu.h $croc,$crqc */
3194   {
3195     MEP_INSN_CPEXTUU_H_C3, "cpextuu_h_C3", "cpextuu.h", 32,
3196     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3197   },
3198 /* cpextu.h $croc,$crqc */
3199   {
3200     MEP_INSN_CPEXTU_H_C3, "cpextu_h_C3", "cpextu.h", 32,
3201     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3202   },
3203 /* cpextlu.b $croc,$crqc */
3204   {
3205     MEP_INSN_CPEXTLU_B_C3, "cpextlu_b_C3", "cpextlu.b", 32,
3206     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3207   },
3208 /* cpextl.b $croc,$crqc */
3209   {
3210     MEP_INSN_CPEXTL_B_C3, "cpextl_b_C3", "cpextl.b", 32,
3211     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3212   },
3213 /* cpextlu.h $croc,$crqc */
3214   {
3215     MEP_INSN_CPEXTLU_H_C3, "cpextlu_h_C3", "cpextlu.h", 32,
3216     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3217   },
3218 /* cpextl.h $croc,$crqc */
3219   {
3220     MEP_INSN_CPEXTL_H_C3, "cpextl_h_C3", "cpextl.h", 32,
3221     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3222   },
3223 /* cpcastub.h $croc,$crqc */
3224   {
3225     MEP_INSN_CPCASTUB_H_C3, "cpcastub_h_C3", "cpcastub.h", 32,
3226     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3227   },
3228 /* cpcastb.h $croc,$crqc */
3229   {
3230     MEP_INSN_CPCASTB_H_C3, "cpcastb_h_C3", "cpcastb.h", 32,
3231     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3232   },
3233 /* cpcastub.w $croc,$crqc */
3234   {
3235     MEP_INSN_CPCASTUB_W_C3, "cpcastub_w_C3", "cpcastub.w", 32,
3236     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3237   },
3238 /* cpcastb.w $croc,$crqc */
3239   {
3240     MEP_INSN_CPCASTB_W_C3, "cpcastb_w_C3", "cpcastb.w", 32,
3241     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3242   },
3243 /* cpcastuh.w $croc,$crqc */
3244   {
3245     MEP_INSN_CPCASTUH_W_C3, "cpcastuh_w_C3", "cpcastuh.w", 32,
3246     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3247   },
3248 /* cpcasth.w $croc,$crqc */
3249   {
3250     MEP_INSN_CPCASTH_W_C3, "cpcasth_w_C3", "cpcasth.w", 32,
3251     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3252   },
3253 /* cdcastuw $croc,$crqc */
3254   {
3255     MEP_INSN_CDCASTUW_C3, "cdcastuw_C3", "cdcastuw", 32,
3256     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3257   },
3258 /* cdcastw $croc,$crqc */
3259   {
3260     MEP_INSN_CDCASTW_C3, "cdcastw_C3", "cdcastw", 32,
3261     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3262   },
3263 /* cpcmpeqz.b $crqc,$crpc */
3264   {
3265     MEP_INSN_CPCMPEQZ_B_C3, "cpcmpeqz_b_C3", "cpcmpeqz.b", 32,
3266     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3267   },
3268 /* cpcmpeq.b $crqc,$crpc */
3269   {
3270     MEP_INSN_CPCMPEQ_B_C3, "cpcmpeq_b_C3", "cpcmpeq.b", 32,
3271     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3272   },
3273 /* cpcmpeq.h $crqc,$crpc */
3274   {
3275     MEP_INSN_CPCMPEQ_H_C3, "cpcmpeq_h_C3", "cpcmpeq.h", 32,
3276     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3277   },
3278 /* cpcmpeq.w $crqc,$crpc */
3279   {
3280     MEP_INSN_CPCMPEQ_W_C3, "cpcmpeq_w_C3", "cpcmpeq.w", 32,
3281     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3282   },
3283 /* cpcmpne.b $crqc,$crpc */
3284   {
3285     MEP_INSN_CPCMPNE_B_C3, "cpcmpne_b_C3", "cpcmpne.b", 32,
3286     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3287   },
3288 /* cpcmpne.h $crqc,$crpc */
3289   {
3290     MEP_INSN_CPCMPNE_H_C3, "cpcmpne_h_C3", "cpcmpne.h", 32,
3291     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3292   },
3293 /* cpcmpne.w $crqc,$crpc */
3294   {
3295     MEP_INSN_CPCMPNE_W_C3, "cpcmpne_w_C3", "cpcmpne.w", 32,
3296     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3297   },
3298 /* cpcmpgtu.b $crqc,$crpc */
3299   {
3300     MEP_INSN_CPCMPGTU_B_C3, "cpcmpgtu_b_C3", "cpcmpgtu.b", 32,
3301     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3302   },
3303 /* cpcmpgt.b $crqc,$crpc */
3304   {
3305     MEP_INSN_CPCMPGT_B_C3, "cpcmpgt_b_C3", "cpcmpgt.b", 32,
3306     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3307   },
3308 /* cpcmpgt.h $crqc,$crpc */
3309   {
3310     MEP_INSN_CPCMPGT_H_C3, "cpcmpgt_h_C3", "cpcmpgt.h", 32,
3311     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3312   },
3313 /* cpcmpgtu.w $crqc,$crpc */
3314   {
3315     MEP_INSN_CPCMPGTU_W_C3, "cpcmpgtu_w_C3", "cpcmpgtu.w", 32,
3316     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3317   },
3318 /* cpcmpgt.w $crqc,$crpc */
3319   {
3320     MEP_INSN_CPCMPGT_W_C3, "cpcmpgt_w_C3", "cpcmpgt.w", 32,
3321     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3322   },
3323 /* cpcmpgeu.b $crqc,$crpc */
3324   {
3325     MEP_INSN_CPCMPGEU_B_C3, "cpcmpgeu_b_C3", "cpcmpgeu.b", 32,
3326     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3327   },
3328 /* cpcmpge.b $crqc,$crpc */
3329   {
3330     MEP_INSN_CPCMPGE_B_C3, "cpcmpge_b_C3", "cpcmpge.b", 32,
3331     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3332   },
3333 /* cpcmpge.h $crqc,$crpc */
3334   {
3335     MEP_INSN_CPCMPGE_H_C3, "cpcmpge_h_C3", "cpcmpge.h", 32,
3336     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3337   },
3338 /* cpcmpgeu.w $crqc,$crpc */
3339   {
3340     MEP_INSN_CPCMPGEU_W_C3, "cpcmpgeu_w_C3", "cpcmpgeu.w", 32,
3341     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3342   },
3343 /* cpcmpge.w $crqc,$crpc */
3344   {
3345     MEP_INSN_CPCMPGE_W_C3, "cpcmpge_w_C3", "cpcmpge.w", 32,
3346     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3347   },
3348 /* cpacmpeq.b $crqc,$crpc */
3349   {
3350     MEP_INSN_CPACMPEQ_B_C3, "cpacmpeq_b_C3", "cpacmpeq.b", 32,
3351     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3352   },
3353 /* cpacmpeq.h $crqc,$crpc */
3354   {
3355     MEP_INSN_CPACMPEQ_H_C3, "cpacmpeq_h_C3", "cpacmpeq.h", 32,
3356     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3357   },
3358 /* cpacmpeq.w $crqc,$crpc */
3359   {
3360     MEP_INSN_CPACMPEQ_W_C3, "cpacmpeq_w_C3", "cpacmpeq.w", 32,
3361     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3362   },
3363 /* cpacmpne.b $crqc,$crpc */
3364   {
3365     MEP_INSN_CPACMPNE_B_C3, "cpacmpne_b_C3", "cpacmpne.b", 32,
3366     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3367   },
3368 /* cpacmpne.h $crqc,$crpc */
3369   {
3370     MEP_INSN_CPACMPNE_H_C3, "cpacmpne_h_C3", "cpacmpne.h", 32,
3371     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3372   },
3373 /* cpacmpne.w $crqc,$crpc */
3374   {
3375     MEP_INSN_CPACMPNE_W_C3, "cpacmpne_w_C3", "cpacmpne.w", 32,
3376     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3377   },
3378 /* cpacmpgtu.b $crqc,$crpc */
3379   {
3380     MEP_INSN_CPACMPGTU_B_C3, "cpacmpgtu_b_C3", "cpacmpgtu.b", 32,
3381     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3382   },
3383 /* cpacmpgt.b $crqc,$crpc */
3384   {
3385     MEP_INSN_CPACMPGT_B_C3, "cpacmpgt_b_C3", "cpacmpgt.b", 32,
3386     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3387   },
3388 /* cpacmpgt.h $crqc,$crpc */
3389   {
3390     MEP_INSN_CPACMPGT_H_C3, "cpacmpgt_h_C3", "cpacmpgt.h", 32,
3391     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3392   },
3393 /* cpacmpgtu.w $crqc,$crpc */
3394   {
3395     MEP_INSN_CPACMPGTU_W_C3, "cpacmpgtu_w_C3", "cpacmpgtu.w", 32,
3396     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3397   },
3398 /* cpacmpgt.w $crqc,$crpc */
3399   {
3400     MEP_INSN_CPACMPGT_W_C3, "cpacmpgt_w_C3", "cpacmpgt.w", 32,
3401     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3402   },
3403 /* cpacmpgeu.b $crqc,$crpc */
3404   {
3405     MEP_INSN_CPACMPGEU_B_C3, "cpacmpgeu_b_C3", "cpacmpgeu.b", 32,
3406     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3407   },
3408 /* cpacmpge.b $crqc,$crpc */
3409   {
3410     MEP_INSN_CPACMPGE_B_C3, "cpacmpge_b_C3", "cpacmpge.b", 32,
3411     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3412   },
3413 /* cpacmpge.h $crqc,$crpc */
3414   {
3415     MEP_INSN_CPACMPGE_H_C3, "cpacmpge_h_C3", "cpacmpge.h", 32,
3416     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3417   },
3418 /* cpacmpgeu.w $crqc,$crpc */
3419   {
3420     MEP_INSN_CPACMPGEU_W_C3, "cpacmpgeu_w_C3", "cpacmpgeu.w", 32,
3421     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3422   },
3423 /* cpacmpge.w $crqc,$crpc */
3424   {
3425     MEP_INSN_CPACMPGE_W_C3, "cpacmpge_w_C3", "cpacmpge.w", 32,
3426     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3427   },
3428 /* cpocmpeq.b $crqc,$crpc */
3429   {
3430     MEP_INSN_CPOCMPEQ_B_C3, "cpocmpeq_b_C3", "cpocmpeq.b", 32,
3431     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3432   },
3433 /* cpocmpeq.h $crqc,$crpc */
3434   {
3435     MEP_INSN_CPOCMPEQ_H_C3, "cpocmpeq_h_C3", "cpocmpeq.h", 32,
3436     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3437   },
3438 /* cpocmpeq.w $crqc,$crpc */
3439   {
3440     MEP_INSN_CPOCMPEQ_W_C3, "cpocmpeq_w_C3", "cpocmpeq.w", 32,
3441     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3442   },
3443 /* cpocmpne.b $crqc,$crpc */
3444   {
3445     MEP_INSN_CPOCMPNE_B_C3, "cpocmpne_b_C3", "cpocmpne.b", 32,
3446     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3447   },
3448 /* cpocmpne.h $crqc,$crpc */
3449   {
3450     MEP_INSN_CPOCMPNE_H_C3, "cpocmpne_h_C3", "cpocmpne.h", 32,
3451     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3452   },
3453 /* cpocmpne.w $crqc,$crpc */
3454   {
3455     MEP_INSN_CPOCMPNE_W_C3, "cpocmpne_w_C3", "cpocmpne.w", 32,
3456     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3457   },
3458 /* cpocmpgtu.b $crqc,$crpc */
3459   {
3460     MEP_INSN_CPOCMPGTU_B_C3, "cpocmpgtu_b_C3", "cpocmpgtu.b", 32,
3461     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3462   },
3463 /* cpocmpgt.b $crqc,$crpc */
3464   {
3465     MEP_INSN_CPOCMPGT_B_C3, "cpocmpgt_b_C3", "cpocmpgt.b", 32,
3466     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3467   },
3468 /* cpocmpgt.h $crqc,$crpc */
3469   {
3470     MEP_INSN_CPOCMPGT_H_C3, "cpocmpgt_h_C3", "cpocmpgt.h", 32,
3471     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3472   },
3473 /* cpocmpgtu.w $crqc,$crpc */
3474   {
3475     MEP_INSN_CPOCMPGTU_W_C3, "cpocmpgtu_w_C3", "cpocmpgtu.w", 32,
3476     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3477   },
3478 /* cpocmpgt.w $crqc,$crpc */
3479   {
3480     MEP_INSN_CPOCMPGT_W_C3, "cpocmpgt_w_C3", "cpocmpgt.w", 32,
3481     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3482   },
3483 /* cpocmpgeu.b $crqc,$crpc */
3484   {
3485     MEP_INSN_CPOCMPGEU_B_C3, "cpocmpgeu_b_C3", "cpocmpgeu.b", 32,
3486     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3487   },
3488 /* cpocmpge.b $crqc,$crpc */
3489   {
3490     MEP_INSN_CPOCMPGE_B_C3, "cpocmpge_b_C3", "cpocmpge.b", 32,
3491     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3492   },
3493 /* cpocmpge.h $crqc,$crpc */
3494   {
3495     MEP_INSN_CPOCMPGE_H_C3, "cpocmpge_h_C3", "cpocmpge.h", 32,
3496     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3497   },
3498 /* cpocmpgeu.w $crqc,$crpc */
3499   {
3500     MEP_INSN_CPOCMPGEU_W_C3, "cpocmpgeu_w_C3", "cpocmpgeu.w", 32,
3501     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3502   },
3503 /* cpocmpge.w $crqc,$crpc */
3504   {
3505     MEP_INSN_CPOCMPGE_W_C3, "cpocmpge_w_C3", "cpocmpge.w", 32,
3506     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3507   },
3508 /* cpsrli3.b $crqc,$crpc,$imm3p9 */
3509   {
3510     MEP_INSN_CPSRLI3_B_C3, "cpsrli3_b_C3", "cpsrli3.b", 32,
3511     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3512   },
3513 /* cpsrli3.h $crqc,$crpc,$imm4p8 */
3514   {
3515     MEP_INSN_CPSRLI3_H_C3, "cpsrli3_h_C3", "cpsrli3.h", 32,
3516     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3517   },
3518 /* cpsrli3.w $crqc,$crpc,$imm5p7 */
3519   {
3520     MEP_INSN_CPSRLI3_W_C3, "cpsrli3_w_C3", "cpsrli3.w", 32,
3521     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3522   },
3523 /* cdsrli3 $crqc,$crpc,$imm6p6 */
3524   {
3525     MEP_INSN_CDSRLI3_C3, "cdsrli3_C3", "cdsrli3", 32,
3526     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3527   },
3528 /* cpsrai3.b $crqc,$crpc,$imm3p9 */
3529   {
3530     MEP_INSN_CPSRAI3_B_C3, "cpsrai3_b_C3", "cpsrai3.b", 32,
3531     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3532   },
3533 /* cpsrai3.h $crqc,$crpc,$imm4p8 */
3534   {
3535     MEP_INSN_CPSRAI3_H_C3, "cpsrai3_h_C3", "cpsrai3.h", 32,
3536     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3537   },
3538 /* cpsrai3.w $crqc,$crpc,$imm5p7 */
3539   {
3540     MEP_INSN_CPSRAI3_W_C3, "cpsrai3_w_C3", "cpsrai3.w", 32,
3541     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3542   },
3543 /* cdsrai3 $crqc,$crpc,$imm6p6 */
3544   {
3545     MEP_INSN_CDSRAI3_C3, "cdsrai3_C3", "cdsrai3", 32,
3546     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3547   },
3548 /* cpslli3.b $crqc,$crpc,$imm3p9 */
3549   {
3550     MEP_INSN_CPSLLI3_B_C3, "cpslli3_b_C3", "cpslli3.b", 32,
3551     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3552   },
3553 /* cpslli3.h $crqc,$crpc,$imm4p8 */
3554   {
3555     MEP_INSN_CPSLLI3_H_C3, "cpslli3_h_C3", "cpslli3.h", 32,
3556     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3557   },
3558 /* cpslli3.w $crqc,$crpc,$imm5p7 */
3559   {
3560     MEP_INSN_CPSLLI3_W_C3, "cpslli3_w_C3", "cpslli3.w", 32,
3561     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3562   },
3563 /* cdslli3 $crqc,$crpc,$imm6p6 */
3564   {
3565     MEP_INSN_CDSLLI3_C3, "cdslli3_C3", "cdslli3", 32,
3566     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3567   },
3568 /* cpslai3.h $crqc,$crpc,$imm4p8 */
3569   {
3570     MEP_INSN_CPSLAI3_H_C3, "cpslai3_h_C3", "cpslai3.h", 32,
3571     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3572   },
3573 /* cpslai3.w $crqc,$crpc,$imm5p7 */
3574   {
3575     MEP_INSN_CPSLAI3_W_C3, "cpslai3_w_C3", "cpslai3.w", 32,
3576     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3577   },
3578 /* cpclipiu3.w $crqc,$crpc,$imm5p7 */
3579   {
3580     MEP_INSN_CPCLIPIU3_W_C3, "cpclipiu3_w_C3", "cpclipiu3.w", 32,
3581     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3582   },
3583 /* cpclipi3.w $crqc,$crpc,$imm5p7 */
3584   {
3585     MEP_INSN_CPCLIPI3_W_C3, "cpclipi3_w_C3", "cpclipi3.w", 32,
3586     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3587   },
3588 /* cdclipiu3 $crqc,$crpc,$imm6p6 */
3589   {
3590     MEP_INSN_CDCLIPIU3_C3, "cdclipiu3_C3", "cdclipiu3", 32,
3591     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3592   },
3593 /* cdclipi3 $crqc,$crpc,$imm6p6 */
3594   {
3595     MEP_INSN_CDCLIPI3_C3, "cdclipi3_C3", "cdclipi3", 32,
3596     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3597   },
3598 /* cpmovi.b $crqc,$simm8p4 */
3599   {
3600     MEP_INSN_CPMOVI_B_C3, "cpmovi_b_C3", "cpmovi.b", 32,
3601     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3602   },
3603 /* cpmoviu.h $crqc,$imm8p4 */
3604   {
3605     MEP_INSN_CPMOVIU_H_C3, "cpmoviu_h_C3", "cpmoviu.h", 32,
3606     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3607   },
3608 /* cpmovi.h $crqc,$simm8p4 */
3609   {
3610     MEP_INSN_CPMOVI_H_C3, "cpmovi_h_C3", "cpmovi.h", 32,
3611     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3612   },
3613 /* cpmoviu.w $crqc,$imm8p4 */
3614   {
3615     MEP_INSN_CPMOVIU_W_C3, "cpmoviu_w_C3", "cpmoviu.w", 32,
3616     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3617   },
3618 /* cpmovi.w $crqc,$simm8p4 */
3619   {
3620     MEP_INSN_CPMOVI_W_C3, "cpmovi_w_C3", "cpmovi.w", 32,
3621     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3622   },
3623 /* cdmoviu $crqc,$imm8p4 */
3624   {
3625     MEP_INSN_CDMOVIU_C3, "cdmoviu_C3", "cdmoviu", 32,
3626     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3627   },
3628 /* cdmovi $crqc,$simm8p4 */
3629   {
3630     MEP_INSN_CDMOVI_C3, "cdmovi_C3", "cdmovi", 32,
3631     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3632   },
3633 /* cpadda1u.b $crqc,$crpc */
3634   {
3635     MEP_INSN_CPADDA1U_B_C3, "cpadda1u_b_C3", "cpadda1u.b", 32,
3636     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3637   },
3638 /* cpadda1.b $crqc,$crpc */
3639   {
3640     MEP_INSN_CPADDA1_B_C3, "cpadda1_b_C3", "cpadda1.b", 32,
3641     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3642   },
3643 /* cpaddua1.h $crqc,$crpc */
3644   {
3645     MEP_INSN_CPADDUA1_H_C3, "cpaddua1_h_C3", "cpaddua1.h", 32,
3646     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3647   },
3648 /* cpaddla1.h $crqc,$crpc */
3649   {
3650     MEP_INSN_CPADDLA1_H_C3, "cpaddla1_h_C3", "cpaddla1.h", 32,
3651     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3652   },
3653 /* cpaddaca1u.b $crqc,$crpc */
3654   {
3655     MEP_INSN_CPADDACA1U_B_C3, "cpaddaca1u_b_C3", "cpaddaca1u.b", 32,
3656     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3657   },
3658 /* cpaddaca1.b $crqc,$crpc */
3659   {
3660     MEP_INSN_CPADDACA1_B_C3, "cpaddaca1_b_C3", "cpaddaca1.b", 32,
3661     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3662   },
3663 /* cpaddacua1.h $crqc,$crpc */
3664   {
3665     MEP_INSN_CPADDACUA1_H_C3, "cpaddacua1_h_C3", "cpaddacua1.h", 32,
3666     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3667   },
3668 /* cpaddacla1.h $crqc,$crpc */
3669   {
3670     MEP_INSN_CPADDACLA1_H_C3, "cpaddacla1_h_C3", "cpaddacla1.h", 32,
3671     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3672   },
3673 /* cpsuba1u.b $crqc,$crpc */
3674   {
3675     MEP_INSN_CPSUBA1U_B_C3, "cpsuba1u_b_C3", "cpsuba1u.b", 32,
3676     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3677   },
3678 /* cpsuba1.b $crqc,$crpc */
3679   {
3680     MEP_INSN_CPSUBA1_B_C3, "cpsuba1_b_C3", "cpsuba1.b", 32,
3681     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3682   },
3683 /* cpsubua1.h $crqc,$crpc */
3684   {
3685     MEP_INSN_CPSUBUA1_H_C3, "cpsubua1_h_C3", "cpsubua1.h", 32,
3686     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3687   },
3688 /* cpsubla1.h $crqc,$crpc */
3689   {
3690     MEP_INSN_CPSUBLA1_H_C3, "cpsubla1_h_C3", "cpsubla1.h", 32,
3691     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3692   },
3693 /* cpsubaca1u.b $crqc,$crpc */
3694   {
3695     MEP_INSN_CPSUBACA1U_B_C3, "cpsubaca1u_b_C3", "cpsubaca1u.b", 32,
3696     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3697   },
3698 /* cpsubaca1.b $crqc,$crpc */
3699   {
3700     MEP_INSN_CPSUBACA1_B_C3, "cpsubaca1_b_C3", "cpsubaca1.b", 32,
3701     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3702   },
3703 /* cpsubacua1.h $crqc,$crpc */
3704   {
3705     MEP_INSN_CPSUBACUA1_H_C3, "cpsubacua1_h_C3", "cpsubacua1.h", 32,
3706     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3707   },
3708 /* cpsubacla1.h $crqc,$crpc */
3709   {
3710     MEP_INSN_CPSUBACLA1_H_C3, "cpsubacla1_h_C3", "cpsubacla1.h", 32,
3711     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3712   },
3713 /* cpabsa1u.b $crqc,$crpc */
3714   {
3715     MEP_INSN_CPABSA1U_B_C3, "cpabsa1u_b_C3", "cpabsa1u.b", 32,
3716     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3717   },
3718 /* cpabsa1.b $crqc,$crpc */
3719   {
3720     MEP_INSN_CPABSA1_B_C3, "cpabsa1_b_C3", "cpabsa1.b", 32,
3721     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3722   },
3723 /* cpabsua1.h $crqc,$crpc */
3724   {
3725     MEP_INSN_CPABSUA1_H_C3, "cpabsua1_h_C3", "cpabsua1.h", 32,
3726     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3727   },
3728 /* cpabsla1.h $crqc,$crpc */
3729   {
3730     MEP_INSN_CPABSLA1_H_C3, "cpabsla1_h_C3", "cpabsla1.h", 32,
3731     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3732   },
3733 /* cpsada1u.b $crqc,$crpc */
3734   {
3735     MEP_INSN_CPSADA1U_B_C3, "cpsada1u_b_C3", "cpsada1u.b", 32,
3736     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3737   },
3738 /* cpsada1.b $crqc,$crpc */
3739   {
3740     MEP_INSN_CPSADA1_B_C3, "cpsada1_b_C3", "cpsada1.b", 32,
3741     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3742   },
3743 /* cpsadua1.h $crqc,$crpc */
3744   {
3745     MEP_INSN_CPSADUA1_H_C3, "cpsadua1_h_C3", "cpsadua1.h", 32,
3746     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3747   },
3748 /* cpsadla1.h $crqc,$crpc */
3749   {
3750     MEP_INSN_CPSADLA1_H_C3, "cpsadla1_h_C3", "cpsadla1.h", 32,
3751     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3752   },
3753 /* cpseta1.h $crqc,$crpc */
3754   {
3755     MEP_INSN_CPSETA1_H_C3, "cpseta1_h_C3", "cpseta1.h", 32,
3756     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3757   },
3758 /* cpsetua1.w $crqc,$crpc */
3759   {
3760     MEP_INSN_CPSETUA1_W_C3, "cpsetua1_w_C3", "cpsetua1.w", 32,
3761     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3762   },
3763 /* cpsetla1.w $crqc,$crpc */
3764   {
3765     MEP_INSN_CPSETLA1_W_C3, "cpsetla1_w_C3", "cpsetla1.w", 32,
3766     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3767   },
3768 /* cpmova1.b $croc */
3769   {
3770     MEP_INSN_CPMOVA1_B_C3, "cpmova1_b_C3", "cpmova1.b", 32,
3771     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3772   },
3773 /* cpmovua1.h $croc */
3774   {
3775     MEP_INSN_CPMOVUA1_H_C3, "cpmovua1_h_C3", "cpmovua1.h", 32,
3776     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3777   },
3778 /* cpmovla1.h $croc */
3779   {
3780     MEP_INSN_CPMOVLA1_H_C3, "cpmovla1_h_C3", "cpmovla1.h", 32,
3781     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3782   },
3783 /* cpmovuua1.w $croc */
3784   {
3785     MEP_INSN_CPMOVUUA1_W_C3, "cpmovuua1_w_C3", "cpmovuua1.w", 32,
3786     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3787   },
3788 /* cpmovula1.w $croc */
3789   {
3790     MEP_INSN_CPMOVULA1_W_C3, "cpmovula1_w_C3", "cpmovula1.w", 32,
3791     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3792   },
3793 /* cpmovlua1.w $croc */
3794   {
3795     MEP_INSN_CPMOVLUA1_W_C3, "cpmovlua1_w_C3", "cpmovlua1.w", 32,
3796     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3797   },
3798 /* cpmovlla1.w $croc */
3799   {
3800     MEP_INSN_CPMOVLLA1_W_C3, "cpmovlla1_w_C3", "cpmovlla1.w", 32,
3801     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3802   },
3803 /* cppacka1u.b $croc */
3804   {
3805     MEP_INSN_CPPACKA1U_B_C3, "cppacka1u_b_C3", "cppacka1u.b", 32,
3806     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3807   },
3808 /* cppacka1.b $croc */
3809   {
3810     MEP_INSN_CPPACKA1_B_C3, "cppacka1_b_C3", "cppacka1.b", 32,
3811     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3812   },
3813 /* cppackua1.h $croc */
3814   {
3815     MEP_INSN_CPPACKUA1_H_C3, "cppackua1_h_C3", "cppackua1.h", 32,
3816     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3817   },
3818 /* cppackla1.h $croc */
3819   {
3820     MEP_INSN_CPPACKLA1_H_C3, "cppackla1_h_C3", "cppackla1.h", 32,
3821     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3822   },
3823 /* cppackua1.w $croc */
3824   {
3825     MEP_INSN_CPPACKUA1_W_C3, "cppackua1_w_C3", "cppackua1.w", 32,
3826     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3827   },
3828 /* cppackla1.w $croc */
3829   {
3830     MEP_INSN_CPPACKLA1_W_C3, "cppackla1_w_C3", "cppackla1.w", 32,
3831     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3832   },
3833 /* cpmovhua1.w $croc */
3834   {
3835     MEP_INSN_CPMOVHUA1_W_C3, "cpmovhua1_w_C3", "cpmovhua1.w", 32,
3836     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3837   },
3838 /* cpmovhla1.w $croc */
3839   {
3840     MEP_INSN_CPMOVHLA1_W_C3, "cpmovhla1_w_C3", "cpmovhla1.w", 32,
3841     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3842   },
3843 /* cpsrla1 $crqc */
3844   {
3845     MEP_INSN_CPSRLA1_C3, "cpsrla1_C3", "cpsrla1", 32,
3846     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3847   },
3848 /* cpsraa1 $crqc */
3849   {
3850     MEP_INSN_CPSRAA1_C3, "cpsraa1_C3", "cpsraa1", 32,
3851     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3852   },
3853 /* cpslla1 $crqc */
3854   {
3855     MEP_INSN_CPSLLA1_C3, "cpslla1_C3", "cpslla1", 32,
3856     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3857   },
3858 /* cpsrlia1 $imm5p7 */
3859   {
3860     MEP_INSN_CPSRLIA1_P1, "cpsrlia1_P1", "cpsrlia1", 32,
3861     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3862   },
3863 /* cpsraia1 $imm5p7 */
3864   {
3865     MEP_INSN_CPSRAIA1_P1, "cpsraia1_P1", "cpsraia1", 32,
3866     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3867   },
3868 /* cpsllia1 $imm5p7 */
3869   {
3870     MEP_INSN_CPSLLIA1_P1, "cpsllia1_P1", "cpsllia1", 32,
3871     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3872   },
3873 /* cpssqa1u.b $crqc,$crpc */
3874   {
3875     MEP_INSN_CPSSQA1U_B_C3, "cpssqa1u_b_C3", "cpssqa1u.b", 32,
3876     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3877   },
3878 /* cpssqa1.b $crqc,$crpc */
3879   {
3880     MEP_INSN_CPSSQA1_B_C3, "cpssqa1_b_C3", "cpssqa1.b", 32,
3881     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3882   },
3883 /* cpssda1u.b $crqc,$crpc */
3884   {
3885     MEP_INSN_CPSSDA1U_B_C3, "cpssda1u_b_C3", "cpssda1u.b", 32,
3886     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3887   },
3888 /* cpssda1.b $crqc,$crpc */
3889   {
3890     MEP_INSN_CPSSDA1_B_C3, "cpssda1_b_C3", "cpssda1.b", 32,
3891     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3892   },
3893 /* cpmula1u.b $crqc,$crpc */
3894   {
3895     MEP_INSN_CPMULA1U_B_C3, "cpmula1u_b_C3", "cpmula1u.b", 32,
3896     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3897   },
3898 /* cpmula1.b $crqc,$crpc */
3899   {
3900     MEP_INSN_CPMULA1_B_C3, "cpmula1_b_C3", "cpmula1.b", 32,
3901     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3902   },
3903 /* cpmulua1.h $crqc,$crpc */
3904   {
3905     MEP_INSN_CPMULUA1_H_C3, "cpmulua1_h_C3", "cpmulua1.h", 32,
3906     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3907   },
3908 /* cpmulla1.h $crqc,$crpc */
3909   {
3910     MEP_INSN_CPMULLA1_H_C3, "cpmulla1_h_C3", "cpmulla1.h", 32,
3911     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3912   },
3913 /* cpmulua1u.w $crqc,$crpc */
3914   {
3915     MEP_INSN_CPMULUA1U_W_C3, "cpmulua1u_w_C3", "cpmulua1u.w", 32,
3916     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3917   },
3918 /* cpmulla1u.w $crqc,$crpc */
3919   {
3920     MEP_INSN_CPMULLA1U_W_C3, "cpmulla1u_w_C3", "cpmulla1u.w", 32,
3921     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3922   },
3923 /* cpmulua1.w $crqc,$crpc */
3924   {
3925     MEP_INSN_CPMULUA1_W_C3, "cpmulua1_w_C3", "cpmulua1.w", 32,
3926     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3927   },
3928 /* cpmulla1.w $crqc,$crpc */
3929   {
3930     MEP_INSN_CPMULLA1_W_C3, "cpmulla1_w_C3", "cpmulla1.w", 32,
3931     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3932   },
3933 /* cpmada1u.b $crqc,$crpc */
3934   {
3935     MEP_INSN_CPMADA1U_B_C3, "cpmada1u_b_C3", "cpmada1u.b", 32,
3936     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3937   },
3938 /* cpmada1.b $crqc,$crpc */
3939   {
3940     MEP_INSN_CPMADA1_B_C3, "cpmada1_b_C3", "cpmada1.b", 32,
3941     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3942   },
3943 /* cpmadua1.h $crqc,$crpc */
3944   {
3945     MEP_INSN_CPMADUA1_H_C3, "cpmadua1_h_C3", "cpmadua1.h", 32,
3946     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3947   },
3948 /* cpmadla1.h $crqc,$crpc */
3949   {
3950     MEP_INSN_CPMADLA1_H_C3, "cpmadla1_h_C3", "cpmadla1.h", 32,
3951     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3952   },
3953 /* cpmadua1u.w $crqc,$crpc */
3954   {
3955     MEP_INSN_CPMADUA1U_W_C3, "cpmadua1u_w_C3", "cpmadua1u.w", 32,
3956     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3957   },
3958 /* cpmadla1u.w $crqc,$crpc */
3959   {
3960     MEP_INSN_CPMADLA1U_W_C3, "cpmadla1u_w_C3", "cpmadla1u.w", 32,
3961     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3962   },
3963 /* cpmadua1.w $crqc,$crpc */
3964   {
3965     MEP_INSN_CPMADUA1_W_C3, "cpmadua1_w_C3", "cpmadua1.w", 32,
3966     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3967   },
3968 /* cpmadla1.w $crqc,$crpc */
3969   {
3970     MEP_INSN_CPMADLA1_W_C3, "cpmadla1_w_C3", "cpmadla1.w", 32,
3971     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3972   },
3973 /* cpmsbua1.h $crqc,$crpc */
3974   {
3975     MEP_INSN_CPMSBUA1_H_C3, "cpmsbua1_h_C3", "cpmsbua1.h", 32,
3976     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3977   },
3978 /* cpmsbla1.h $crqc,$crpc */
3979   {
3980     MEP_INSN_CPMSBLA1_H_C3, "cpmsbla1_h_C3", "cpmsbla1.h", 32,
3981     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3982   },
3983 /* cpmsbua1u.w $crqc,$crpc */
3984   {
3985     MEP_INSN_CPMSBUA1U_W_C3, "cpmsbua1u_w_C3", "cpmsbua1u.w", 32,
3986     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3987   },
3988 /* cpmsbla1u.w $crqc,$crpc */
3989   {
3990     MEP_INSN_CPMSBLA1U_W_C3, "cpmsbla1u_w_C3", "cpmsbla1u.w", 32,
3991     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3992   },
3993 /* cpmsbua1.w $crqc,$crpc */
3994   {
3995     MEP_INSN_CPMSBUA1_W_C3, "cpmsbua1_w_C3", "cpmsbua1.w", 32,
3996     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3997   },
3998 /* cpmsbla1.w $crqc,$crpc */
3999   {
4000     MEP_INSN_CPMSBLA1_W_C3, "cpmsbla1_w_C3", "cpmsbla1.w", 32,
4001     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4002   },
4003 /* cpsmadua1.h $crqc,$crpc */
4004   {
4005     MEP_INSN_CPSMADUA1_H_C3, "cpsmadua1_h_C3", "cpsmadua1.h", 32,
4006     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4007   },
4008 /* cpsmadla1.h $crqc,$crpc */
4009   {
4010     MEP_INSN_CPSMADLA1_H_C3, "cpsmadla1_h_C3", "cpsmadla1.h", 32,
4011     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4012   },
4013 /* cpsmadua1.w $crqc,$crpc */
4014   {
4015     MEP_INSN_CPSMADUA1_W_C3, "cpsmadua1_w_C3", "cpsmadua1.w", 32,
4016     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4017   },
4018 /* cpsmadla1.w $crqc,$crpc */
4019   {
4020     MEP_INSN_CPSMADLA1_W_C3, "cpsmadla1_w_C3", "cpsmadla1.w", 32,
4021     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4022   },
4023 /* cpsmsbua1.h $crqc,$crpc */
4024   {
4025     MEP_INSN_CPSMSBUA1_H_C3, "cpsmsbua1_h_C3", "cpsmsbua1.h", 32,
4026     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4027   },
4028 /* cpsmsbla1.h $crqc,$crpc */
4029   {
4030     MEP_INSN_CPSMSBLA1_H_C3, "cpsmsbla1_h_C3", "cpsmsbla1.h", 32,
4031     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4032   },
4033 /* cpsmsbua1.w $crqc,$crpc */
4034   {
4035     MEP_INSN_CPSMSBUA1_W_C3, "cpsmsbua1_w_C3", "cpsmsbua1.w", 32,
4036     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4037   },
4038 /* cpsmsbla1.w $crqc,$crpc */
4039   {
4040     MEP_INSN_CPSMSBLA1_W_C3, "cpsmsbla1_w_C3", "cpsmsbla1.w", 32,
4041     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4042   },
4043 /* cpmulslua1.h $crqc,$crpc */
4044   {
4045     MEP_INSN_CPMULSLUA1_H_C3, "cpmulslua1_h_C3", "cpmulslua1.h", 32,
4046     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4047   },
4048 /* cpmulslla1.h $crqc,$crpc */
4049   {
4050     MEP_INSN_CPMULSLLA1_H_C3, "cpmulslla1_h_C3", "cpmulslla1.h", 32,
4051     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4052   },
4053 /* cpmulslua1.w $crqc,$crpc */
4054   {
4055     MEP_INSN_CPMULSLUA1_W_C3, "cpmulslua1_w_C3", "cpmulslua1.w", 32,
4056     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4057   },
4058 /* cpmulslla1.w $crqc,$crpc */
4059   {
4060     MEP_INSN_CPMULSLLA1_W_C3, "cpmulslla1_w_C3", "cpmulslla1.w", 32,
4061     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4062   },
4063 /* cpsmadslua1.h $crqc,$crpc */
4064   {
4065     MEP_INSN_CPSMADSLUA1_H_C3, "cpsmadslua1_h_C3", "cpsmadslua1.h", 32,
4066     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4067   },
4068 /* cpsmadslla1.h $crqc,$crpc */
4069   {
4070     MEP_INSN_CPSMADSLLA1_H_C3, "cpsmadslla1_h_C3", "cpsmadslla1.h", 32,
4071     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4072   },
4073 /* cpsmadslua1.w $crqc,$crpc */
4074   {
4075     MEP_INSN_CPSMADSLUA1_W_C3, "cpsmadslua1_w_C3", "cpsmadslua1.w", 32,
4076     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4077   },
4078 /* cpsmadslla1.w $crqc,$crpc */
4079   {
4080     MEP_INSN_CPSMADSLLA1_W_C3, "cpsmadslla1_w_C3", "cpsmadslla1.w", 32,
4081     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4082   },
4083 /* cpsmsbslua1.h $crqc,$crpc */
4084   {
4085     MEP_INSN_CPSMSBSLUA1_H_C3, "cpsmsbslua1_h_C3", "cpsmsbslua1.h", 32,
4086     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4087   },
4088 /* cpsmsbslla1.h $crqc,$crpc */
4089   {
4090     MEP_INSN_CPSMSBSLLA1_H_C3, "cpsmsbslla1_h_C3", "cpsmsbslla1.h", 32,
4091     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4092   },
4093 /* cpsmsbslua1.w $crqc,$crpc */
4094   {
4095     MEP_INSN_CPSMSBSLUA1_W_C3, "cpsmsbslua1_w_C3", "cpsmsbslua1.w", 32,
4096     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4097   },
4098 /* cpsmsbslla1.w $crqc,$crpc */
4099   {
4100     MEP_INSN_CPSMSBSLLA1_W_C3, "cpsmsbslla1_w_C3", "cpsmsbslla1.w", 32,
4101     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4102   },
4103 /* c0nop */
4104   {
4105     MEP_INSN_C0NOP_P0_P0S, "c0nop_P0_P0S", "c0nop", 32,
4106     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x28" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P0S), 0 } } } }
4107   },
4108 /* cpadd3.b $crop,$crqp,$crpp */
4109   {
4110     MEP_INSN_CPADD3_B_P0S_P1, "cpadd3_b_P0S_P1", "cpadd3.b", 32,
4111     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4112   },
4113 /* cpadd3.h $crop,$crqp,$crpp */
4114   {
4115     MEP_INSN_CPADD3_H_P0S_P1, "cpadd3_h_P0S_P1", "cpadd3.h", 32,
4116     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4117   },
4118 /* cpadd3.w $crop,$crqp,$crpp */
4119   {
4120     MEP_INSN_CPADD3_W_P0S_P1, "cpadd3_w_P0S_P1", "cpadd3.w", 32,
4121     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4122   },
4123 /* cpunpacku.b $crop,$crqp,$crpp */
4124   {
4125     MEP_INSN_CPUNPACKU_B_P0S_P1, "cpunpacku_b_P0S_P1", "cpunpacku.b", 32,
4126     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4127   },
4128 /* cpunpacku.h $crop,$crqp,$crpp */
4129   {
4130     MEP_INSN_CPUNPACKU_H_P0S_P1, "cpunpacku_h_P0S_P1", "cpunpacku.h", 32,
4131     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4132   },
4133 /* cpunpacku.w $crop,$crqp,$crpp */
4134   {
4135     MEP_INSN_CPUNPACKU_W_P0S_P1, "cpunpacku_w_P0S_P1", "cpunpacku.w", 32,
4136     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4137   },
4138 /* cpunpackl.b $crop,$crqp,$crpp */
4139   {
4140     MEP_INSN_CPUNPACKL_B_P0S_P1, "cpunpackl_b_P0S_P1", "cpunpackl.b", 32,
4141     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4142   },
4143 /* cpunpackl.h $crop,$crqp,$crpp */
4144   {
4145     MEP_INSN_CPUNPACKL_H_P0S_P1, "cpunpackl_h_P0S_P1", "cpunpackl.h", 32,
4146     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4147   },
4148 /* cpunpackl.w $crop,$crqp,$crpp */
4149   {
4150     MEP_INSN_CPUNPACKL_W_P0S_P1, "cpunpackl_w_P0S_P1", "cpunpackl.w", 32,
4151     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4152   },
4153 /* cpsel $crop,$crqp,$crpp */
4154   {
4155     MEP_INSN_CPSEL_P0S_P1, "cpsel_P0S_P1", "cpsel", 32,
4156     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4157   },
4158 /* cpfsftbs0 $crop,$crqp,$crpp */
4159   {
4160     MEP_INSN_CPFSFTBS0_P0S_P1, "cpfsftbs0_P0S_P1", "cpfsftbs0", 32,
4161     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4162   },
4163 /* cpfsftbs1 $crop,$crqp,$crpp */
4164   {
4165     MEP_INSN_CPFSFTBS1_P0S_P1, "cpfsftbs1_P0S_P1", "cpfsftbs1", 32,
4166     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4167   },
4168 /* cpmov $crop,$crqp */
4169   {
4170     MEP_INSN_CPMOV_P0S_P1, "cpmov_P0S_P1", "cpmov", 32,
4171     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4172   },
4173 /* cpabsz.b $crop,$crqp */
4174   {
4175     MEP_INSN_CPABSZ_B_P0S_P1, "cpabsz_b_P0S_P1", "cpabsz.b", 32,
4176     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4177   },
4178 /* cpabsz.h $crop,$crqp */
4179   {
4180     MEP_INSN_CPABSZ_H_P0S_P1, "cpabsz_h_P0S_P1", "cpabsz.h", 32,
4181     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4182   },
4183 /* cpabsz.w $crop,$crqp */
4184   {
4185     MEP_INSN_CPABSZ_W_P0S_P1, "cpabsz_w_P0S_P1", "cpabsz.w", 32,
4186     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4187   },
4188 /* cpldz.h $crop,$crqp */
4189   {
4190     MEP_INSN_CPLDZ_H_P0S_P1, "cpldz_h_P0S_P1", "cpldz.h", 32,
4191     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4192   },
4193 /* cpldz.w $crop,$crqp */
4194   {
4195     MEP_INSN_CPLDZ_W_P0S_P1, "cpldz_w_P0S_P1", "cpldz.w", 32,
4196     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4197   },
4198 /* cpnorm.h $crop,$crqp */
4199   {
4200     MEP_INSN_CPNORM_H_P0S_P1, "cpnorm_h_P0S_P1", "cpnorm.h", 32,
4201     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4202   },
4203 /* cpnorm.w $crop,$crqp */
4204   {
4205     MEP_INSN_CPNORM_W_P0S_P1, "cpnorm_w_P0S_P1", "cpnorm.w", 32,
4206     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4207   },
4208 /* cphaddu.b $crop,$crqp */
4209   {
4210     MEP_INSN_CPHADDU_B_P0S_P1, "cphaddu_b_P0S_P1", "cphaddu.b", 32,
4211     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4212   },
4213 /* cphadd.b $crop,$crqp */
4214   {
4215     MEP_INSN_CPHADD_B_P0S_P1, "cphadd_b_P0S_P1", "cphadd.b", 32,
4216     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4217   },
4218 /* cphadd.h $crop,$crqp */
4219   {
4220     MEP_INSN_CPHADD_H_P0S_P1, "cphadd_h_P0S_P1", "cphadd.h", 32,
4221     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4222   },
4223 /* cphadd.w $crop,$crqp */
4224   {
4225     MEP_INSN_CPHADD_W_P0S_P1, "cphadd_w_P0S_P1", "cphadd.w", 32,
4226     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4227   },
4228 /* cpccadd.b $crqp */
4229   {
4230     MEP_INSN_CPCCADD_B_P0S_P1, "cpccadd_b_P0S_P1", "cpccadd.b", 32,
4231     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRSTCOPY, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4232   },
4233 /* cpbcast.b $crop,$crqp */
4234   {
4235     MEP_INSN_CPBCAST_B_P0S_P1, "cpbcast_b_P0S_P1", "cpbcast.b", 32,
4236     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4237   },
4238 /* cpbcast.h $crop,$crqp */
4239   {
4240     MEP_INSN_CPBCAST_H_P0S_P1, "cpbcast_h_P0S_P1", "cpbcast.h", 32,
4241     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4242   },
4243 /* cpbcast.w $crop,$crqp */
4244   {
4245     MEP_INSN_CPBCAST_W_P0S_P1, "cpbcast_w_P0S_P1", "cpbcast.w", 32,
4246     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4247   },
4248 /* cpextuu.b $crop,$crqp */
4249   {
4250     MEP_INSN_CPEXTUU_B_P0S_P1, "cpextuu_b_P0S_P1", "cpextuu.b", 32,
4251     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4252   },
4253 /* cpextu.b $crop,$crqp */
4254   {
4255     MEP_INSN_CPEXTU_B_P0S_P1, "cpextu_b_P0S_P1", "cpextu.b", 32,
4256     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4257   },
4258 /* cpextuu.h $crop,$crqp */
4259   {
4260     MEP_INSN_CPEXTUU_H_P0S_P1, "cpextuu_h_P0S_P1", "cpextuu.h", 32,
4261     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4262   },
4263 /* cpextu.h $crop,$crqp */
4264   {
4265     MEP_INSN_CPEXTU_H_P0S_P1, "cpextu_h_P0S_P1", "cpextu.h", 32,
4266     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4267   },
4268 /* cpextlu.b $crop,$crqp */
4269   {
4270     MEP_INSN_CPEXTLU_B_P0S_P1, "cpextlu_b_P0S_P1", "cpextlu.b", 32,
4271     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4272   },
4273 /* cpextl.b $crop,$crqp */
4274   {
4275     MEP_INSN_CPEXTL_B_P0S_P1, "cpextl_b_P0S_P1", "cpextl.b", 32,
4276     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4277   },
4278 /* cpextlu.h $crop,$crqp */
4279   {
4280     MEP_INSN_CPEXTLU_H_P0S_P1, "cpextlu_h_P0S_P1", "cpextlu.h", 32,
4281     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4282   },
4283 /* cpextl.h $crop,$crqp */
4284   {
4285     MEP_INSN_CPEXTL_H_P0S_P1, "cpextl_h_P0S_P1", "cpextl.h", 32,
4286     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4287   },
4288 /* cpcastub.h $crop,$crqp */
4289   {
4290     MEP_INSN_CPCASTUB_H_P0S_P1, "cpcastub_h_P0S_P1", "cpcastub.h", 32,
4291     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4292   },
4293 /* cpcastb.h $crop,$crqp */
4294   {
4295     MEP_INSN_CPCASTB_H_P0S_P1, "cpcastb_h_P0S_P1", "cpcastb.h", 32,
4296     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4297   },
4298 /* cpcastub.w $crop,$crqp */
4299   {
4300     MEP_INSN_CPCASTUB_W_P0S_P1, "cpcastub_w_P0S_P1", "cpcastub.w", 32,
4301     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4302   },
4303 /* cpcastb.w $crop,$crqp */
4304   {
4305     MEP_INSN_CPCASTB_W_P0S_P1, "cpcastb_w_P0S_P1", "cpcastb.w", 32,
4306     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4307   },
4308 /* cpcastuh.w $crop,$crqp */
4309   {
4310     MEP_INSN_CPCASTUH_W_P0S_P1, "cpcastuh_w_P0S_P1", "cpcastuh.w", 32,
4311     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4312   },
4313 /* cpcasth.w $crop,$crqp */
4314   {
4315     MEP_INSN_CPCASTH_W_P0S_P1, "cpcasth_w_P0S_P1", "cpcasth.w", 32,
4316     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4317   },
4318 /* cdcastuw $crop,$crqp */
4319   {
4320     MEP_INSN_CDCASTUW_P0S_P1, "cdcastuw_P0S_P1", "cdcastuw", 32,
4321     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4322   },
4323 /* cdcastw $crop,$crqp */
4324   {
4325     MEP_INSN_CDCASTW_P0S_P1, "cdcastw_P0S_P1", "cdcastw", 32,
4326     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4327   },
4328 /* cpmovfrcsar0 $crop */
4329   {
4330     MEP_INSN_CPMOVFRCSAR0_P0S_P1, "cpmovfrcsar0_P0S_P1", "cpmovfrcsar0", 32,
4331     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4332   },
4333 /* cpmovfrcsar1 $crop */
4334   {
4335     MEP_INSN_CPMOVFRCSAR1_P0S_P1, "cpmovfrcsar1_P0S_P1", "cpmovfrcsar1", 32,
4336     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4337   },
4338 /* cpmovfrcc $crop */
4339   {
4340     MEP_INSN_CPMOVFRCC_P0S_P1, "cpmovfrcc_P0S_P1", "cpmovfrcc", 32,
4341     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4342   },
4343 /* cpmovtocsar0 $crqp */
4344   {
4345     MEP_INSN_CPMOVTOCSAR0_P0S_P1, "cpmovtocsar0_P0S_P1", "cpmovtocsar0", 32,
4346     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4347   },
4348 /* cpmovtocsar1 $crqp */
4349   {
4350     MEP_INSN_CPMOVTOCSAR1_P0S_P1, "cpmovtocsar1_P0S_P1", "cpmovtocsar1", 32,
4351     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4352   },
4353 /* cpmovtocc $crqp */
4354   {
4355     MEP_INSN_CPMOVTOCC_P0S_P1, "cpmovtocc_P0S_P1", "cpmovtocc", 32,
4356     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4357   },
4358 /* cpcmpeqz.b $crqp,$crpp */
4359   {
4360     MEP_INSN_CPCMPEQZ_B_P0S_P1, "cpcmpeqz_b_P0S_P1", "cpcmpeqz.b", 32,
4361     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4362   },
4363 /* cpcmpeq.b $crqp,$crpp */
4364   {
4365     MEP_INSN_CPCMPEQ_B_P0S_P1, "cpcmpeq_b_P0S_P1", "cpcmpeq.b", 32,
4366     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4367   },
4368 /* cpcmpeq.h $crqp,$crpp */
4369   {
4370     MEP_INSN_CPCMPEQ_H_P0S_P1, "cpcmpeq_h_P0S_P1", "cpcmpeq.h", 32,
4371     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4372   },
4373 /* cpcmpeq.w $crqp,$crpp */
4374   {
4375     MEP_INSN_CPCMPEQ_W_P0S_P1, "cpcmpeq_w_P0S_P1", "cpcmpeq.w", 32,
4376     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4377   },
4378 /* cpcmpne.b $crqp,$crpp */
4379   {
4380     MEP_INSN_CPCMPNE_B_P0S_P1, "cpcmpne_b_P0S_P1", "cpcmpne.b", 32,
4381     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4382   },
4383 /* cpcmpne.h $crqp,$crpp */
4384   {
4385     MEP_INSN_CPCMPNE_H_P0S_P1, "cpcmpne_h_P0S_P1", "cpcmpne.h", 32,
4386     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4387   },
4388 /* cpcmpne.w $crqp,$crpp */
4389   {
4390     MEP_INSN_CPCMPNE_W_P0S_P1, "cpcmpne_w_P0S_P1", "cpcmpne.w", 32,
4391     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4392   },
4393 /* cpcmpgtu.b $crqp,$crpp */
4394   {
4395     MEP_INSN_CPCMPGTU_B_P0S_P1, "cpcmpgtu_b_P0S_P1", "cpcmpgtu.b", 32,
4396     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4397   },
4398 /* cpcmpgt.b $crqp,$crpp */
4399   {
4400     MEP_INSN_CPCMPGT_B_P0S_P1, "cpcmpgt_b_P0S_P1", "cpcmpgt.b", 32,
4401     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4402   },
4403 /* cpcmpgt.h $crqp,$crpp */
4404   {
4405     MEP_INSN_CPCMPGT_H_P0S_P1, "cpcmpgt_h_P0S_P1", "cpcmpgt.h", 32,
4406     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4407   },
4408 /* cpcmpgtu.w $crqp,$crpp */
4409   {
4410     MEP_INSN_CPCMPGTU_W_P0S_P1, "cpcmpgtu_w_P0S_P1", "cpcmpgtu.w", 32,
4411     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4412   },
4413 /* cpcmpgt.w $crqp,$crpp */
4414   {
4415     MEP_INSN_CPCMPGT_W_P0S_P1, "cpcmpgt_w_P0S_P1", "cpcmpgt.w", 32,
4416     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4417   },
4418 /* cpcmpgeu.b $crqp,$crpp */
4419   {
4420     MEP_INSN_CPCMPGEU_B_P0S_P1, "cpcmpgeu_b_P0S_P1", "cpcmpgeu.b", 32,
4421     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4422   },
4423 /* cpcmpge.b $crqp,$crpp */
4424   {
4425     MEP_INSN_CPCMPGE_B_P0S_P1, "cpcmpge_b_P0S_P1", "cpcmpge.b", 32,
4426     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4427   },
4428 /* cpcmpge.h $crqp,$crpp */
4429   {
4430     MEP_INSN_CPCMPGE_H_P0S_P1, "cpcmpge_h_P0S_P1", "cpcmpge.h", 32,
4431     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4432   },
4433 /* cpcmpgeu.w $crqp,$crpp */
4434   {
4435     MEP_INSN_CPCMPGEU_W_P0S_P1, "cpcmpgeu_w_P0S_P1", "cpcmpgeu.w", 32,
4436     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4437   },
4438 /* cpcmpge.w $crqp,$crpp */
4439   {
4440     MEP_INSN_CPCMPGE_W_P0S_P1, "cpcmpge_w_P0S_P1", "cpcmpge.w", 32,
4441     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4442   },
4443 /* cpadda0u.b $crqp,$crpp */
4444   {
4445     MEP_INSN_CPADDA0U_B_P0S, "cpadda0u_b_P0S", "cpadda0u.b", 32,
4446     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4447   },
4448 /* cpadda0.b $crqp,$crpp */
4449   {
4450     MEP_INSN_CPADDA0_B_P0S, "cpadda0_b_P0S", "cpadda0.b", 32,
4451     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4452   },
4453 /* cpaddua0.h $crqp,$crpp */
4454   {
4455     MEP_INSN_CPADDUA0_H_P0S, "cpaddua0_h_P0S", "cpaddua0.h", 32,
4456     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4457   },
4458 /* cpaddla0.h $crqp,$crpp */
4459   {
4460     MEP_INSN_CPADDLA0_H_P0S, "cpaddla0_h_P0S", "cpaddla0.h", 32,
4461     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4462   },
4463 /* cpaddaca0u.b $crqp,$crpp */
4464   {
4465     MEP_INSN_CPADDACA0U_B_P0S, "cpaddaca0u_b_P0S", "cpaddaca0u.b", 32,
4466     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4467   },
4468 /* cpaddaca0.b $crqp,$crpp */
4469   {
4470     MEP_INSN_CPADDACA0_B_P0S, "cpaddaca0_b_P0S", "cpaddaca0.b", 32,
4471     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4472   },
4473 /* cpaddacua0.h $crqp,$crpp */
4474   {
4475     MEP_INSN_CPADDACUA0_H_P0S, "cpaddacua0_h_P0S", "cpaddacua0.h", 32,
4476     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4477   },
4478 /* cpaddacla0.h $crqp,$crpp */
4479   {
4480     MEP_INSN_CPADDACLA0_H_P0S, "cpaddacla0_h_P0S", "cpaddacla0.h", 32,
4481     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4482   },
4483 /* cpsuba0u.b $crqp,$crpp */
4484   {
4485     MEP_INSN_CPSUBA0U_B_P0S, "cpsuba0u_b_P0S", "cpsuba0u.b", 32,
4486     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4487   },
4488 /* cpsuba0.b $crqp,$crpp */
4489   {
4490     MEP_INSN_CPSUBA0_B_P0S, "cpsuba0_b_P0S", "cpsuba0.b", 32,
4491     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4492   },
4493 /* cpsubua0.h $crqp,$crpp */
4494   {
4495     MEP_INSN_CPSUBUA0_H_P0S, "cpsubua0_h_P0S", "cpsubua0.h", 32,
4496     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4497   },
4498 /* cpsubla0.h $crqp,$crpp */
4499   {
4500     MEP_INSN_CPSUBLA0_H_P0S, "cpsubla0_h_P0S", "cpsubla0.h", 32,
4501     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4502   },
4503 /* cpsubaca0u.b $crqp,$crpp */
4504   {
4505     MEP_INSN_CPSUBACA0U_B_P0S, "cpsubaca0u_b_P0S", "cpsubaca0u.b", 32,
4506     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4507   },
4508 /* cpsubaca0.b $crqp,$crpp */
4509   {
4510     MEP_INSN_CPSUBACA0_B_P0S, "cpsubaca0_b_P0S", "cpsubaca0.b", 32,
4511     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4512   },
4513 /* cpsubacua0.h $crqp,$crpp */
4514   {
4515     MEP_INSN_CPSUBACUA0_H_P0S, "cpsubacua0_h_P0S", "cpsubacua0.h", 32,
4516     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4517   },
4518 /* cpsubacla0.h $crqp,$crpp */
4519   {
4520     MEP_INSN_CPSUBACLA0_H_P0S, "cpsubacla0_h_P0S", "cpsubacla0.h", 32,
4521     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4522   },
4523 /* cpabsa0u.b $crqp,$crpp */
4524   {
4525     MEP_INSN_CPABSA0U_B_P0S, "cpabsa0u_b_P0S", "cpabsa0u.b", 32,
4526     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4527   },
4528 /* cpabsa0.b $crqp,$crpp */
4529   {
4530     MEP_INSN_CPABSA0_B_P0S, "cpabsa0_b_P0S", "cpabsa0.b", 32,
4531     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4532   },
4533 /* cpabsua0.h $crqp,$crpp */
4534   {
4535     MEP_INSN_CPABSUA0_H_P0S, "cpabsua0_h_P0S", "cpabsua0.h", 32,
4536     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4537   },
4538 /* cpabsla0.h $crqp,$crpp */
4539   {
4540     MEP_INSN_CPABSLA0_H_P0S, "cpabsla0_h_P0S", "cpabsla0.h", 32,
4541     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4542   },
4543 /* cpsada0u.b $crqp,$crpp */
4544   {
4545     MEP_INSN_CPSADA0U_B_P0S, "cpsada0u_b_P0S", "cpsada0u.b", 32,
4546     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4547   },
4548 /* cpsada0.b $crqp,$crpp */
4549   {
4550     MEP_INSN_CPSADA0_B_P0S, "cpsada0_b_P0S", "cpsada0.b", 32,
4551     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4552   },
4553 /* cpsadua0.h $crqp,$crpp */
4554   {
4555     MEP_INSN_CPSADUA0_H_P0S, "cpsadua0_h_P0S", "cpsadua0.h", 32,
4556     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4557   },
4558 /* cpsadla0.h $crqp,$crpp */
4559   {
4560     MEP_INSN_CPSADLA0_H_P0S, "cpsadla0_h_P0S", "cpsadla0.h", 32,
4561     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4562   },
4563 /* cpseta0.h $crqp,$crpp */
4564   {
4565     MEP_INSN_CPSETA0_H_P0S, "cpseta0_h_P0S", "cpseta0.h", 32,
4566     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4567   },
4568 /* cpsetua0.w $crqp,$crpp */
4569   {
4570     MEP_INSN_CPSETUA0_W_P0S, "cpsetua0_w_P0S", "cpsetua0.w", 32,
4571     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4572   },
4573 /* cpsetla0.w $crqp,$crpp */
4574   {
4575     MEP_INSN_CPSETLA0_W_P0S, "cpsetla0_w_P0S", "cpsetla0.w", 32,
4576     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4577   },
4578 /* cpmova0.b $crop */
4579   {
4580     MEP_INSN_CPMOVA0_B_P0S, "cpmova0_b_P0S", "cpmova0.b", 32,
4581     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4582   },
4583 /* cpmovua0.h $crop */
4584   {
4585     MEP_INSN_CPMOVUA0_H_P0S, "cpmovua0_h_P0S", "cpmovua0.h", 32,
4586     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4587   },
4588 /* cpmovla0.h $crop */
4589   {
4590     MEP_INSN_CPMOVLA0_H_P0S, "cpmovla0_h_P0S", "cpmovla0.h", 32,
4591     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4592   },
4593 /* cpmovuua0.w $crop */
4594   {
4595     MEP_INSN_CPMOVUUA0_W_P0S, "cpmovuua0_w_P0S", "cpmovuua0.w", 32,
4596     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4597   },
4598 /* cpmovula0.w $crop */
4599   {
4600     MEP_INSN_CPMOVULA0_W_P0S, "cpmovula0_w_P0S", "cpmovula0.w", 32,
4601     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4602   },
4603 /* cpmovlua0.w $crop */
4604   {
4605     MEP_INSN_CPMOVLUA0_W_P0S, "cpmovlua0_w_P0S", "cpmovlua0.w", 32,
4606     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4607   },
4608 /* cpmovlla0.w $crop */
4609   {
4610     MEP_INSN_CPMOVLLA0_W_P0S, "cpmovlla0_w_P0S", "cpmovlla0.w", 32,
4611     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4612   },
4613 /* cppacka0u.b $crop */
4614   {
4615     MEP_INSN_CPPACKA0U_B_P0S, "cppacka0u_b_P0S", "cppacka0u.b", 32,
4616     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4617   },
4618 /* cppacka0.b $crop */
4619   {
4620     MEP_INSN_CPPACKA0_B_P0S, "cppacka0_b_P0S", "cppacka0.b", 32,
4621     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4622   },
4623 /* cppackua0.h $crop */
4624   {
4625     MEP_INSN_CPPACKUA0_H_P0S, "cppackua0_h_P0S", "cppackua0.h", 32,
4626     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4627   },
4628 /* cppackla0.h $crop */
4629   {
4630     MEP_INSN_CPPACKLA0_H_P0S, "cppackla0_h_P0S", "cppackla0.h", 32,
4631     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4632   },
4633 /* cppackua0.w $crop */
4634   {
4635     MEP_INSN_CPPACKUA0_W_P0S, "cppackua0_w_P0S", "cppackua0.w", 32,
4636     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4637   },
4638 /* cppackla0.w $crop */
4639   {
4640     MEP_INSN_CPPACKLA0_W_P0S, "cppackla0_w_P0S", "cppackla0.w", 32,
4641     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4642   },
4643 /* cpmovhua0.w $crop */
4644   {
4645     MEP_INSN_CPMOVHUA0_W_P0S, "cpmovhua0_w_P0S", "cpmovhua0.w", 32,
4646     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4647   },
4648 /* cpmovhla0.w $crop */
4649   {
4650     MEP_INSN_CPMOVHLA0_W_P0S, "cpmovhla0_w_P0S", "cpmovhla0.w", 32,
4651     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4652   },
4653 /* cpacsuma0 */
4654   {
4655     MEP_INSN_CPACSUMA0_P0S, "cpacsuma0_P0S", "cpacsuma0", 32,
4656     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4657   },
4658 /* cpaccpa0 */
4659   {
4660     MEP_INSN_CPACCPA0_P0S, "cpaccpa0_P0S", "cpaccpa0", 32,
4661     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4662   },
4663 /* cpsrla0 $crqp */
4664   {
4665     MEP_INSN_CPSRLA0_P0S, "cpsrla0_P0S", "cpsrla0", 32,
4666     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4667   },
4668 /* cpsraa0 $crqp */
4669   {
4670     MEP_INSN_CPSRAA0_P0S, "cpsraa0_P0S", "cpsraa0", 32,
4671     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4672   },
4673 /* cpslla0 $crqp */
4674   {
4675     MEP_INSN_CPSLLA0_P0S, "cpslla0_P0S", "cpslla0", 32,
4676     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4677   },
4678 /* cpsrlia0 $imm5p23 */
4679   {
4680     MEP_INSN_CPSRLIA0_P0S, "cpsrlia0_P0S", "cpsrlia0", 32,
4681     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4682   },
4683 /* cpsraia0 $imm5p23 */
4684   {
4685     MEP_INSN_CPSRAIA0_P0S, "cpsraia0_P0S", "cpsraia0", 32,
4686     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4687   },
4688 /* cpsllia0 $imm5p23 */
4689   {
4690     MEP_INSN_CPSLLIA0_P0S, "cpsllia0_P0S", "cpsllia0", 32,
4691     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4692   },
4693 /* cpfsftba0s0u.b $crqp,$crpp */
4694   {
4695     MEP_INSN_CPFSFTBA0S0U_B_P0S, "cpfsftba0s0u_b_P0S", "cpfsftba0s0u.b", 32,
4696     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4697   },
4698 /* cpfsftba0s0.b $crqp,$crpp */
4699   {
4700     MEP_INSN_CPFSFTBA0S0_B_P0S, "cpfsftba0s0_b_P0S", "cpfsftba0s0.b", 32,
4701     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4702   },
4703 /* cpfsftbua0s0.h $crqp,$crpp */
4704   {
4705     MEP_INSN_CPFSFTBUA0S0_H_P0S, "cpfsftbua0s0_h_P0S", "cpfsftbua0s0.h", 32,
4706     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4707   },
4708 /* cpfsftbla0s0.h $crqp,$crpp */
4709   {
4710     MEP_INSN_CPFSFTBLA0S0_H_P0S, "cpfsftbla0s0_h_P0S", "cpfsftbla0s0.h", 32,
4711     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4712   },
4713 /* cpfaca0s0u.b $crqp,$crpp */
4714   {
4715     MEP_INSN_CPFACA0S0U_B_P0S, "cpfaca0s0u_b_P0S", "cpfaca0s0u.b", 32,
4716     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4717   },
4718 /* cpfaca0s0.b $crqp,$crpp */
4719   {
4720     MEP_INSN_CPFACA0S0_B_P0S, "cpfaca0s0_b_P0S", "cpfaca0s0.b", 32,
4721     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4722   },
4723 /* cpfacua0s0.h $crqp,$crpp */
4724   {
4725     MEP_INSN_CPFACUA0S0_H_P0S, "cpfacua0s0_h_P0S", "cpfacua0s0.h", 32,
4726     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4727   },
4728 /* cpfacla0s0.h $crqp,$crpp */
4729   {
4730     MEP_INSN_CPFACLA0S0_H_P0S, "cpfacla0s0_h_P0S", "cpfacla0s0.h", 32,
4731     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4732   },
4733 /* cpfsftba0s1u.b $crqp,$crpp */
4734   {
4735     MEP_INSN_CPFSFTBA0S1U_B_P0S, "cpfsftba0s1u_b_P0S", "cpfsftba0s1u.b", 32,
4736     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4737   },
4738 /* cpfsftba0s1.b $crqp,$crpp */
4739   {
4740     MEP_INSN_CPFSFTBA0S1_B_P0S, "cpfsftba0s1_b_P0S", "cpfsftba0s1.b", 32,
4741     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4742   },
4743 /* cpfsftbua0s1.h $crqp,$crpp */
4744   {
4745     MEP_INSN_CPFSFTBUA0S1_H_P0S, "cpfsftbua0s1_h_P0S", "cpfsftbua0s1.h", 32,
4746     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4747   },
4748 /* cpfsftbla0s1.h $crqp,$crpp */
4749   {
4750     MEP_INSN_CPFSFTBLA0S1_H_P0S, "cpfsftbla0s1_h_P0S", "cpfsftbla0s1.h", 32,
4751     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4752   },
4753 /* cpfaca0s1u.b $crqp,$crpp */
4754   {
4755     MEP_INSN_CPFACA0S1U_B_P0S, "cpfaca0s1u_b_P0S", "cpfaca0s1u.b", 32,
4756     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4757   },
4758 /* cpfaca0s1.b $crqp,$crpp */
4759   {
4760     MEP_INSN_CPFACA0S1_B_P0S, "cpfaca0s1_b_P0S", "cpfaca0s1.b", 32,
4761     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4762   },
4763 /* cpfacua0s1.h $crqp,$crpp */
4764   {
4765     MEP_INSN_CPFACUA0S1_H_P0S, "cpfacua0s1_h_P0S", "cpfacua0s1.h", 32,
4766     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4767   },
4768 /* cpfacla0s1.h $crqp,$crpp */
4769   {
4770     MEP_INSN_CPFACLA0S1_H_P0S, "cpfacla0s1_h_P0S", "cpfacla0s1.h", 32,
4771     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4772   },
4773 /* cpfsftbi $crop,$crqp,$crpp,$imm3p5 */
4774   {
4775     MEP_INSN_CPFSFTBI_P0_P1, "cpfsftbi_P0_P1", "cpfsftbi", 32,
4776     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4777   },
4778 /* cpacmpeq.b $crqp,$crpp */
4779   {
4780     MEP_INSN_CPACMPEQ_B_P0_P1, "cpacmpeq_b_P0_P1", "cpacmpeq.b", 32,
4781     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4782   },
4783 /* cpacmpeq.h $crqp,$crpp */
4784   {
4785     MEP_INSN_CPACMPEQ_H_P0_P1, "cpacmpeq_h_P0_P1", "cpacmpeq.h", 32,
4786     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4787   },
4788 /* cpacmpeq.w $crqp,$crpp */
4789   {
4790     MEP_INSN_CPACMPEQ_W_P0_P1, "cpacmpeq_w_P0_P1", "cpacmpeq.w", 32,
4791     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4792   },
4793 /* cpacmpne.b $crqp,$crpp */
4794   {
4795     MEP_INSN_CPACMPNE_B_P0_P1, "cpacmpne_b_P0_P1", "cpacmpne.b", 32,
4796     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4797   },
4798 /* cpacmpne.h $crqp,$crpp */
4799   {
4800     MEP_INSN_CPACMPNE_H_P0_P1, "cpacmpne_h_P0_P1", "cpacmpne.h", 32,
4801     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4802   },
4803 /* cpacmpne.w $crqp,$crpp */
4804   {
4805     MEP_INSN_CPACMPNE_W_P0_P1, "cpacmpne_w_P0_P1", "cpacmpne.w", 32,
4806     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4807   },
4808 /* cpacmpgtu.b $crqp,$crpp */
4809   {
4810     MEP_INSN_CPACMPGTU_B_P0_P1, "cpacmpgtu_b_P0_P1", "cpacmpgtu.b", 32,
4811     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4812   },
4813 /* cpacmpgt.b $crqp,$crpp */
4814   {
4815     MEP_INSN_CPACMPGT_B_P0_P1, "cpacmpgt_b_P0_P1", "cpacmpgt.b", 32,
4816     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4817   },
4818 /* cpacmpgt.h $crqp,$crpp */
4819   {
4820     MEP_INSN_CPACMPGT_H_P0_P1, "cpacmpgt_h_P0_P1", "cpacmpgt.h", 32,
4821     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4822   },
4823 /* cpacmpgtu.w $crqp,$crpp */
4824   {
4825     MEP_INSN_CPACMPGTU_W_P0_P1, "cpacmpgtu_w_P0_P1", "cpacmpgtu.w", 32,
4826     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4827   },
4828 /* cpacmpgt.w $crqp,$crpp */
4829   {
4830     MEP_INSN_CPACMPGT_W_P0_P1, "cpacmpgt_w_P0_P1", "cpacmpgt.w", 32,
4831     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4832   },
4833 /* cpacmpgeu.b $crqp,$crpp */
4834   {
4835     MEP_INSN_CPACMPGEU_B_P0_P1, "cpacmpgeu_b_P0_P1", "cpacmpgeu.b", 32,
4836     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4837   },
4838 /* cpacmpge.b $crqp,$crpp */
4839   {
4840     MEP_INSN_CPACMPGE_B_P0_P1, "cpacmpge_b_P0_P1", "cpacmpge.b", 32,
4841     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4842   },
4843 /* cpacmpge.h $crqp,$crpp */
4844   {
4845     MEP_INSN_CPACMPGE_H_P0_P1, "cpacmpge_h_P0_P1", "cpacmpge.h", 32,
4846     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4847   },
4848 /* cpacmpgeu.w $crqp,$crpp */
4849   {
4850     MEP_INSN_CPACMPGEU_W_P0_P1, "cpacmpgeu_w_P0_P1", "cpacmpgeu.w", 32,
4851     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4852   },
4853 /* cpacmpge.w $crqp,$crpp */
4854   {
4855     MEP_INSN_CPACMPGE_W_P0_P1, "cpacmpge_w_P0_P1", "cpacmpge.w", 32,
4856     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4857   },
4858 /* cpocmpeq.b $crqp,$crpp */
4859   {
4860     MEP_INSN_CPOCMPEQ_B_P0_P1, "cpocmpeq_b_P0_P1", "cpocmpeq.b", 32,
4861     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4862   },
4863 /* cpocmpeq.h $crqp,$crpp */
4864   {
4865     MEP_INSN_CPOCMPEQ_H_P0_P1, "cpocmpeq_h_P0_P1", "cpocmpeq.h", 32,
4866     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4867   },
4868 /* cpocmpeq.w $crqp,$crpp */
4869   {
4870     MEP_INSN_CPOCMPEQ_W_P0_P1, "cpocmpeq_w_P0_P1", "cpocmpeq.w", 32,
4871     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4872   },
4873 /* cpocmpne.b $crqp,$crpp */
4874   {
4875     MEP_INSN_CPOCMPNE_B_P0_P1, "cpocmpne_b_P0_P1", "cpocmpne.b", 32,
4876     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4877   },
4878 /* cpocmpne.h $crqp,$crpp */
4879   {
4880     MEP_INSN_CPOCMPNE_H_P0_P1, "cpocmpne_h_P0_P1", "cpocmpne.h", 32,
4881     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4882   },
4883 /* cpocmpne.w $crqp,$crpp */
4884   {
4885     MEP_INSN_CPOCMPNE_W_P0_P1, "cpocmpne_w_P0_P1", "cpocmpne.w", 32,
4886     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4887   },
4888 /* cpocmpgtu.b $crqp,$crpp */
4889   {
4890     MEP_INSN_CPOCMPGTU_B_P0_P1, "cpocmpgtu_b_P0_P1", "cpocmpgtu.b", 32,
4891     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4892   },
4893 /* cpocmpgt.b $crqp,$crpp */
4894   {
4895     MEP_INSN_CPOCMPGT_B_P0_P1, "cpocmpgt_b_P0_P1", "cpocmpgt.b", 32,
4896     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4897   },
4898 /* cpocmpgt.h $crqp,$crpp */
4899   {
4900     MEP_INSN_CPOCMPGT_H_P0_P1, "cpocmpgt_h_P0_P1", "cpocmpgt.h", 32,
4901     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4902   },
4903 /* cpocmpgtu.w $crqp,$crpp */
4904   {
4905     MEP_INSN_CPOCMPGTU_W_P0_P1, "cpocmpgtu_w_P0_P1", "cpocmpgtu.w", 32,
4906     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4907   },
4908 /* cpocmpgt.w $crqp,$crpp */
4909   {
4910     MEP_INSN_CPOCMPGT_W_P0_P1, "cpocmpgt_w_P0_P1", "cpocmpgt.w", 32,
4911     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4912   },
4913 /* cpocmpgeu.b $crqp,$crpp */
4914   {
4915     MEP_INSN_CPOCMPGEU_B_P0_P1, "cpocmpgeu_b_P0_P1", "cpocmpgeu.b", 32,
4916     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4917   },
4918 /* cpocmpge.b $crqp,$crpp */
4919   {
4920     MEP_INSN_CPOCMPGE_B_P0_P1, "cpocmpge_b_P0_P1", "cpocmpge.b", 32,
4921     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4922   },
4923 /* cpocmpge.h $crqp,$crpp */
4924   {
4925     MEP_INSN_CPOCMPGE_H_P0_P1, "cpocmpge_h_P0_P1", "cpocmpge.h", 32,
4926     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4927   },
4928 /* cpocmpgeu.w $crqp,$crpp */
4929   {
4930     MEP_INSN_CPOCMPGEU_W_P0_P1, "cpocmpgeu_w_P0_P1", "cpocmpgeu.w", 32,
4931     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4932   },
4933 /* cpocmpge.w $crqp,$crpp */
4934   {
4935     MEP_INSN_CPOCMPGE_W_P0_P1, "cpocmpge_w_P0_P1", "cpocmpge.w", 32,
4936     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4937   },
4938 /* cdadd3 $crop,$crqp,$crpp */
4939   {
4940     MEP_INSN_CDADD3_P0_P1, "cdadd3_P0_P1", "cdadd3", 32,
4941     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4942   },
4943 /* cpsub3.b $crop,$crqp,$crpp */
4944   {
4945     MEP_INSN_CPSUB3_B_P0_P1, "cpsub3_b_P0_P1", "cpsub3.b", 32,
4946     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4947   },
4948 /* cpsub3.h $crop,$crqp,$crpp */
4949   {
4950     MEP_INSN_CPSUB3_H_P0_P1, "cpsub3_h_P0_P1", "cpsub3.h", 32,
4951     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4952   },
4953 /* cpsub3.w $crop,$crqp,$crpp */
4954   {
4955     MEP_INSN_CPSUB3_W_P0_P1, "cpsub3_w_P0_P1", "cpsub3.w", 32,
4956     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4957   },
4958 /* cdsub3 $crop,$crqp,$crpp */
4959   {
4960     MEP_INSN_CDSUB3_P0_P1, "cdsub3_P0_P1", "cdsub3", 32,
4961     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4962   },
4963 /* cpsadd3.h $crop,$crqp,$crpp */
4964   {
4965     MEP_INSN_CPSADD3_H_P0_P1, "cpsadd3_h_P0_P1", "cpsadd3.h", 32,
4966     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4967   },
4968 /* cpsadd3.w $crop,$crqp,$crpp */
4969   {
4970     MEP_INSN_CPSADD3_W_P0_P1, "cpsadd3_w_P0_P1", "cpsadd3.w", 32,
4971     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4972   },
4973 /* cpssub3.h $crop,$crqp,$crpp */
4974   {
4975     MEP_INSN_CPSSUB3_H_P0_P1, "cpssub3_h_P0_P1", "cpssub3.h", 32,
4976     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4977   },
4978 /* cpssub3.w $crop,$crqp,$crpp */
4979   {
4980     MEP_INSN_CPSSUB3_W_P0_P1, "cpssub3_w_P0_P1", "cpssub3.w", 32,
4981     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4982   },
4983 /* cpextuaddu3.b $crop,$crqp,$crpp */
4984   {
4985     MEP_INSN_CPEXTUADDU3_B_P0_P1, "cpextuaddu3_b_P0_P1", "cpextuaddu3.b", 32,
4986     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4987   },
4988 /* cpextuadd3.b $crop,$crqp,$crpp */
4989   {
4990     MEP_INSN_CPEXTUADD3_B_P0_P1, "cpextuadd3_b_P0_P1", "cpextuadd3.b", 32,
4991     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4992   },
4993 /* cpextladdu3.b $crop,$crqp,$crpp */
4994   {
4995     MEP_INSN_CPEXTLADDU3_B_P0_P1, "cpextladdu3_b_P0_P1", "cpextladdu3.b", 32,
4996     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4997   },
4998 /* cpextladd3.b $crop,$crqp,$crpp */
4999   {
5000     MEP_INSN_CPEXTLADD3_B_P0_P1, "cpextladd3_b_P0_P1", "cpextladd3.b", 32,
5001     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5002   },
5003 /* cpextusubu3.b $crop,$crqp,$crpp */
5004   {
5005     MEP_INSN_CPEXTUSUBU3_B_P0_P1, "cpextusubu3_b_P0_P1", "cpextusubu3.b", 32,
5006     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5007   },
5008 /* cpextusub3.b $crop,$crqp,$crpp */
5009   {
5010     MEP_INSN_CPEXTUSUB3_B_P0_P1, "cpextusub3_b_P0_P1", "cpextusub3.b", 32,
5011     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5012   },
5013 /* cpextlsubu3.b $crop,$crqp,$crpp */
5014   {
5015     MEP_INSN_CPEXTLSUBU3_B_P0_P1, "cpextlsubu3_b_P0_P1", "cpextlsubu3.b", 32,
5016     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5017   },
5018 /* cpextlsub3.b $crop,$crqp,$crpp */
5019   {
5020     MEP_INSN_CPEXTLSUB3_B_P0_P1, "cpextlsub3_b_P0_P1", "cpextlsub3.b", 32,
5021     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5022   },
5023 /* cpaveu3.b $crop,$crqp,$crpp */
5024   {
5025     MEP_INSN_CPAVEU3_B_P0_P1, "cpaveu3_b_P0_P1", "cpaveu3.b", 32,
5026     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5027   },
5028 /* cpave3.b $crop,$crqp,$crpp */
5029   {
5030     MEP_INSN_CPAVE3_B_P0_P1, "cpave3_b_P0_P1", "cpave3.b", 32,
5031     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5032   },
5033 /* cpave3.h $crop,$crqp,$crpp */
5034   {
5035     MEP_INSN_CPAVE3_H_P0_P1, "cpave3_h_P0_P1", "cpave3.h", 32,
5036     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5037   },
5038 /* cpave3.w $crop,$crqp,$crpp */
5039   {
5040     MEP_INSN_CPAVE3_W_P0_P1, "cpave3_w_P0_P1", "cpave3.w", 32,
5041     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5042   },
5043 /* cpaddsru3.b $crop,$crqp,$crpp */
5044   {
5045     MEP_INSN_CPADDSRU3_B_P0_P1, "cpaddsru3_b_P0_P1", "cpaddsru3.b", 32,
5046     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5047   },
5048 /* cpaddsr3.b $crop,$crqp,$crpp */
5049   {
5050     MEP_INSN_CPADDSR3_B_P0_P1, "cpaddsr3_b_P0_P1", "cpaddsr3.b", 32,
5051     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5052   },
5053 /* cpaddsr3.h $crop,$crqp,$crpp */
5054   {
5055     MEP_INSN_CPADDSR3_H_P0_P1, "cpaddsr3_h_P0_P1", "cpaddsr3.h", 32,
5056     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5057   },
5058 /* cpaddsr3.w $crop,$crqp,$crpp */
5059   {
5060     MEP_INSN_CPADDSR3_W_P0_P1, "cpaddsr3_w_P0_P1", "cpaddsr3.w", 32,
5061     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5062   },
5063 /* cpabsu3.b $crop,$crqp,$crpp */
5064   {
5065     MEP_INSN_CPABSU3_B_P0_P1, "cpabsu3_b_P0_P1", "cpabsu3.b", 32,
5066     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5067   },
5068 /* cpabs3.b $crop,$crqp,$crpp */
5069   {
5070     MEP_INSN_CPABS3_B_P0_P1, "cpabs3_b_P0_P1", "cpabs3.b", 32,
5071     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5072   },
5073 /* cpabs3.h $crop,$crqp,$crpp */
5074   {
5075     MEP_INSN_CPABS3_H_P0_P1, "cpabs3_h_P0_P1", "cpabs3.h", 32,
5076     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5077   },
5078 /* cpand3 $crop,$crqp,$crpp */
5079   {
5080     MEP_INSN_CPAND3_P0_P1, "cpand3_P0_P1", "cpand3", 32,
5081     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5082   },
5083 /* cpor3 $crop,$crqp,$crpp */
5084   {
5085     MEP_INSN_CPOR3_P0_P1, "cpor3_P0_P1", "cpor3", 32,
5086     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5087   },
5088 /* cpnor3 $crop,$crqp,$crpp */
5089   {
5090     MEP_INSN_CPNOR3_P0_P1, "cpnor3_P0_P1", "cpnor3", 32,
5091     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5092   },
5093 /* cpxor3 $crop,$crqp,$crpp */
5094   {
5095     MEP_INSN_CPXOR3_P0_P1, "cpxor3_P0_P1", "cpxor3", 32,
5096     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5097   },
5098 /* cppacku.b $crop,$crqp,$crpp */
5099   {
5100     MEP_INSN_CPPACKU_B_P0_P1, "cppacku_b_P0_P1", "cppacku.b", 32,
5101     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5102   },
5103 /* cppack.b $crop,$crqp,$crpp */
5104   {
5105     MEP_INSN_CPPACK_B_P0_P1, "cppack_b_P0_P1", "cppack.b", 32,
5106     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5107   },
5108 /* cppack.h $crop,$crqp,$crpp */
5109   {
5110     MEP_INSN_CPPACK_H_P0_P1, "cppack_h_P0_P1", "cppack.h", 32,
5111     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5112   },
5113 /* cpmaxu3.b $crop,$crqp,$crpp */
5114   {
5115     MEP_INSN_CPMAXU3_B_P0_P1, "cpmaxu3_b_P0_P1", "cpmaxu3.b", 32,
5116     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5117   },
5118 /* cpmax3.b $crop,$crqp,$crpp */
5119   {
5120     MEP_INSN_CPMAX3_B_P0_P1, "cpmax3_b_P0_P1", "cpmax3.b", 32,
5121     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5122   },
5123 /* cpmax3.h $crop,$crqp,$crpp */
5124   {
5125     MEP_INSN_CPMAX3_H_P0_P1, "cpmax3_h_P0_P1", "cpmax3.h", 32,
5126     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5127   },
5128 /* cpmaxu3.w $crop,$crqp,$crpp */
5129   {
5130     MEP_INSN_CPMAXU3_W_P0_P1, "cpmaxu3_w_P0_P1", "cpmaxu3.w", 32,
5131     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5132   },
5133 /* cpmax3.w $crop,$crqp,$crpp */
5134   {
5135     MEP_INSN_CPMAX3_W_P0_P1, "cpmax3_w_P0_P1", "cpmax3.w", 32,
5136     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5137   },
5138 /* cpminu3.b $crop,$crqp,$crpp */
5139   {
5140     MEP_INSN_CPMINU3_B_P0_P1, "cpminu3_b_P0_P1", "cpminu3.b", 32,
5141     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5142   },
5143 /* cpmin3.b $crop,$crqp,$crpp */
5144   {
5145     MEP_INSN_CPMIN3_B_P0_P1, "cpmin3_b_P0_P1", "cpmin3.b", 32,
5146     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5147   },
5148 /* cpmin3.h $crop,$crqp,$crpp */
5149   {
5150     MEP_INSN_CPMIN3_H_P0_P1, "cpmin3_h_P0_P1", "cpmin3.h", 32,
5151     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5152   },
5153 /* cpminu3.w $crop,$crqp,$crpp */
5154   {
5155     MEP_INSN_CPMINU3_W_P0_P1, "cpminu3_w_P0_P1", "cpminu3.w", 32,
5156     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5157   },
5158 /* cpmin3.w $crop,$crqp,$crpp */
5159   {
5160     MEP_INSN_CPMIN3_W_P0_P1, "cpmin3_w_P0_P1", "cpmin3.w", 32,
5161     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5162   },
5163 /* cpsrl3.b $crop,$crqp,$crpp */
5164   {
5165     MEP_INSN_CPSRL3_B_P0_P1, "cpsrl3_b_P0_P1", "cpsrl3.b", 32,
5166     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5167   },
5168 /* cpssrl3.b $crop,$crqp,$crpp */
5169   {
5170     MEP_INSN_CPSSRL3_B_P0_P1, "cpssrl3_b_P0_P1", "cpssrl3.b", 32,
5171     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5172   },
5173 /* cpsrl3.h $crop,$crqp,$crpp */
5174   {
5175     MEP_INSN_CPSRL3_H_P0_P1, "cpsrl3_h_P0_P1", "cpsrl3.h", 32,
5176     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5177   },
5178 /* cpssrl3.h $crop,$crqp,$crpp */
5179   {
5180     MEP_INSN_CPSSRL3_H_P0_P1, "cpssrl3_h_P0_P1", "cpssrl3.h", 32,
5181     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5182   },
5183 /* cpsrl3.w $crop,$crqp,$crpp */
5184   {
5185     MEP_INSN_CPSRL3_W_P0_P1, "cpsrl3_w_P0_P1", "cpsrl3.w", 32,
5186     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5187   },
5188 /* cpssrl3.w $crop,$crqp,$crpp */
5189   {
5190     MEP_INSN_CPSSRL3_W_P0_P1, "cpssrl3_w_P0_P1", "cpssrl3.w", 32,
5191     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5192   },
5193 /* cdsrl3 $crop,$crqp,$crpp */
5194   {
5195     MEP_INSN_CDSRL3_P0_P1, "cdsrl3_P0_P1", "cdsrl3", 32,
5196     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5197   },
5198 /* cpsra3.b $crop,$crqp,$crpp */
5199   {
5200     MEP_INSN_CPSRA3_B_P0_P1, "cpsra3_b_P0_P1", "cpsra3.b", 32,
5201     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5202   },
5203 /* cpssra3.b $crop,$crqp,$crpp */
5204   {
5205     MEP_INSN_CPSSRA3_B_P0_P1, "cpssra3_b_P0_P1", "cpssra3.b", 32,
5206     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5207   },
5208 /* cpsra3.h $crop,$crqp,$crpp */
5209   {
5210     MEP_INSN_CPSRA3_H_P0_P1, "cpsra3_h_P0_P1", "cpsra3.h", 32,
5211     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5212   },
5213 /* cpssra3.h $crop,$crqp,$crpp */
5214   {
5215     MEP_INSN_CPSSRA3_H_P0_P1, "cpssra3_h_P0_P1", "cpssra3.h", 32,
5216     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5217   },
5218 /* cpsra3.w $crop,$crqp,$crpp */
5219   {
5220     MEP_INSN_CPSRA3_W_P0_P1, "cpsra3_w_P0_P1", "cpsra3.w", 32,
5221     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5222   },
5223 /* cpssra3.w $crop,$crqp,$crpp */
5224   {
5225     MEP_INSN_CPSSRA3_W_P0_P1, "cpssra3_w_P0_P1", "cpssra3.w", 32,
5226     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5227   },
5228 /* cdsra3 $crop,$crqp,$crpp */
5229   {
5230     MEP_INSN_CDSRA3_P0_P1, "cdsra3_P0_P1", "cdsra3", 32,
5231     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5232   },
5233 /* cpsll3.b $crop,$crqp,$crpp */
5234   {
5235     MEP_INSN_CPSLL3_B_P0_P1, "cpsll3_b_P0_P1", "cpsll3.b", 32,
5236     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5237   },
5238 /* cpssll3.b $crop,$crqp,$crpp */
5239   {
5240     MEP_INSN_CPSSLL3_B_P0_P1, "cpssll3_b_P0_P1", "cpssll3.b", 32,
5241     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5242   },
5243 /* cpsll3.h $crop,$crqp,$crpp */
5244   {
5245     MEP_INSN_CPSLL3_H_P0_P1, "cpsll3_h_P0_P1", "cpsll3.h", 32,
5246     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5247   },
5248 /* cpssll3.h $crop,$crqp,$crpp */
5249   {
5250     MEP_INSN_CPSSLL3_H_P0_P1, "cpssll3_h_P0_P1", "cpssll3.h", 32,
5251     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5252   },
5253 /* cpsll3.w $crop,$crqp,$crpp */
5254   {
5255     MEP_INSN_CPSLL3_W_P0_P1, "cpsll3_w_P0_P1", "cpsll3.w", 32,
5256     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5257   },
5258 /* cpssll3.w $crop,$crqp,$crpp */
5259   {
5260     MEP_INSN_CPSSLL3_W_P0_P1, "cpssll3_w_P0_P1", "cpssll3.w", 32,
5261     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5262   },
5263 /* cdsll3 $crop,$crqp,$crpp */
5264   {
5265     MEP_INSN_CDSLL3_P0_P1, "cdsll3_P0_P1", "cdsll3", 32,
5266     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5267   },
5268 /* cpsla3.h $crop,$crqp,$crpp */
5269   {
5270     MEP_INSN_CPSLA3_H_P0_P1, "cpsla3_h_P0_P1", "cpsla3.h", 32,
5271     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5272   },
5273 /* cpsla3.w $crop,$crqp,$crpp */
5274   {
5275     MEP_INSN_CPSLA3_W_P0_P1, "cpsla3_w_P0_P1", "cpsla3.w", 32,
5276     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5277   },
5278 /* cpsrli3.b $crop,$crqp,$imm3p5 */
5279   {
5280     MEP_INSN_CPSRLI3_B_P0_P1, "cpsrli3_b_P0_P1", "cpsrli3.b", 32,
5281     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5282   },
5283 /* cpsrli3.h $crop,$crqp,$imm4p4 */
5284   {
5285     MEP_INSN_CPSRLI3_H_P0_P1, "cpsrli3_h_P0_P1", "cpsrli3.h", 32,
5286     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5287   },
5288 /* cpsrli3.w $crop,$crqp,$imm5p3 */
5289   {
5290     MEP_INSN_CPSRLI3_W_P0_P1, "cpsrli3_w_P0_P1", "cpsrli3.w", 32,
5291     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5292   },
5293 /* cdsrli3 $crop,$crqp,$imm6p2 */
5294   {
5295     MEP_INSN_CDSRLI3_P0_P1, "cdsrli3_P0_P1", "cdsrli3", 32,
5296     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5297   },
5298 /* cpsrai3.b $crop,$crqp,$imm3p5 */
5299   {
5300     MEP_INSN_CPSRAI3_B_P0_P1, "cpsrai3_b_P0_P1", "cpsrai3.b", 32,
5301     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5302   },
5303 /* cpsrai3.h $crop,$crqp,$imm4p4 */
5304   {
5305     MEP_INSN_CPSRAI3_H_P0_P1, "cpsrai3_h_P0_P1", "cpsrai3.h", 32,
5306     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5307   },
5308 /* cpsrai3.w $crop,$crqp,$imm5p3 */
5309   {
5310     MEP_INSN_CPSRAI3_W_P0_P1, "cpsrai3_w_P0_P1", "cpsrai3.w", 32,
5311     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5312   },
5313 /* cdsrai3 $crop,$crqp,$imm6p2 */
5314   {
5315     MEP_INSN_CDSRAI3_P0_P1, "cdsrai3_P0_P1", "cdsrai3", 32,
5316     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5317   },
5318 /* cpslli3.b $crop,$crqp,$imm3p5 */
5319   {
5320     MEP_INSN_CPSLLI3_B_P0_P1, "cpslli3_b_P0_P1", "cpslli3.b", 32,
5321     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5322   },
5323 /* cpslli3.h $crop,$crqp,$imm4p4 */
5324   {
5325     MEP_INSN_CPSLLI3_H_P0_P1, "cpslli3_h_P0_P1", "cpslli3.h", 32,
5326     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5327   },
5328 /* cpslli3.w $crop,$crqp,$imm5p3 */
5329   {
5330     MEP_INSN_CPSLLI3_W_P0_P1, "cpslli3_w_P0_P1", "cpslli3.w", 32,
5331     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5332   },
5333 /* cdslli3 $crop,$crqp,$imm6p2 */
5334   {
5335     MEP_INSN_CDSLLI3_P0_P1, "cdslli3_P0_P1", "cdslli3", 32,
5336     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5337   },
5338 /* cpslai3.h $crop,$crqp,$imm4p4 */
5339   {
5340     MEP_INSN_CPSLAI3_H_P0_P1, "cpslai3_h_P0_P1", "cpslai3.h", 32,
5341     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5342   },
5343 /* cpslai3.w $crop,$crqp,$imm5p3 */
5344   {
5345     MEP_INSN_CPSLAI3_W_P0_P1, "cpslai3_w_P0_P1", "cpslai3.w", 32,
5346     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5347   },
5348 /* cpclipiu3.w $crop,$crqp,$imm5p3 */
5349   {
5350     MEP_INSN_CPCLIPIU3_W_P0_P1, "cpclipiu3_w_P0_P1", "cpclipiu3.w", 32,
5351     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5352   },
5353 /* cpclipi3.w $crop,$crqp,$imm5p3 */
5354   {
5355     MEP_INSN_CPCLIPI3_W_P0_P1, "cpclipi3_w_P0_P1", "cpclipi3.w", 32,
5356     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5357   },
5358 /* cdclipiu3 $crop,$crqp,$imm6p2 */
5359   {
5360     MEP_INSN_CDCLIPIU3_P0_P1, "cdclipiu3_P0_P1", "cdclipiu3", 32,
5361     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5362   },
5363 /* cdclipi3 $crop,$crqp,$imm6p2 */
5364   {
5365     MEP_INSN_CDCLIPI3_P0_P1, "cdclipi3_P0_P1", "cdclipi3", 32,
5366     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5367   },
5368 /* cpmovi.h $crqp,$simm16p0 */
5369   {
5370     MEP_INSN_CPMOVI_H_P0_P1, "cpmovi_h_P0_P1", "cpmovi.h", 32,
5371     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5372   },
5373 /* cpmoviu.w $crqp,$imm16p0 */
5374   {
5375     MEP_INSN_CPMOVIU_W_P0_P1, "cpmoviu_w_P0_P1", "cpmoviu.w", 32,
5376     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5377   },
5378 /* cpmovi.w $crqp,$simm16p0 */
5379   {
5380     MEP_INSN_CPMOVI_W_P0_P1, "cpmovi_w_P0_P1", "cpmovi.w", 32,
5381     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5382   },
5383 /* cdmoviu $crqp,$imm16p0 */
5384   {
5385     MEP_INSN_CDMOVIU_P0_P1, "cdmoviu_P0_P1", "cdmoviu", 32,
5386     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5387   },
5388 /* cdmovi $crqp,$simm16p0 */
5389   {
5390     MEP_INSN_CDMOVI_P0_P1, "cdmovi_P0_P1", "cdmovi", 32,
5391     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5392   },
5393 /* c1nop */
5394   {
5395     MEP_INSN_C1NOP_P1, "c1nop_P1", "c1nop", 32,
5396     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5397   },
5398 /* cpmovi.b $crqp,$simm8p20 */
5399   {
5400     MEP_INSN_CPMOVI_B_P0S_P1, "cpmovi_b_P0S_P1", "cpmovi.b", 32,
5401     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
5402   },
5403 /* cpadda1u.b $crqp,$crpp */
5404   {
5405     MEP_INSN_CPADDA1U_B_P1, "cpadda1u_b_P1", "cpadda1u.b", 32,
5406     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5407   },
5408 /* cpadda1.b $crqp,$crpp */
5409   {
5410     MEP_INSN_CPADDA1_B_P1, "cpadda1_b_P1", "cpadda1.b", 32,
5411     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5412   },
5413 /* cpaddua1.h $crqp,$crpp */
5414   {
5415     MEP_INSN_CPADDUA1_H_P1, "cpaddua1_h_P1", "cpaddua1.h", 32,
5416     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5417   },
5418 /* cpaddla1.h $crqp,$crpp */
5419   {
5420     MEP_INSN_CPADDLA1_H_P1, "cpaddla1_h_P1", "cpaddla1.h", 32,
5421     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5422   },
5423 /* cpaddaca1u.b $crqp,$crpp */
5424   {
5425     MEP_INSN_CPADDACA1U_B_P1, "cpaddaca1u_b_P1", "cpaddaca1u.b", 32,
5426     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5427   },
5428 /* cpaddaca1.b $crqp,$crpp */
5429   {
5430     MEP_INSN_CPADDACA1_B_P1, "cpaddaca1_b_P1", "cpaddaca1.b", 32,
5431     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5432   },
5433 /* cpaddacua1.h $crqp,$crpp */
5434   {
5435     MEP_INSN_CPADDACUA1_H_P1, "cpaddacua1_h_P1", "cpaddacua1.h", 32,
5436     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5437   },
5438 /* cpaddacla1.h $crqp,$crpp */
5439   {
5440     MEP_INSN_CPADDACLA1_H_P1, "cpaddacla1_h_P1", "cpaddacla1.h", 32,
5441     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5442   },
5443 /* cpsuba1u.b $crqp,$crpp */
5444   {
5445     MEP_INSN_CPSUBA1U_B_P1, "cpsuba1u_b_P1", "cpsuba1u.b", 32,
5446     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5447   },
5448 /* cpsuba1.b $crqp,$crpp */
5449   {
5450     MEP_INSN_CPSUBA1_B_P1, "cpsuba1_b_P1", "cpsuba1.b", 32,
5451     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5452   },
5453 /* cpsubua1.h $crqp,$crpp */
5454   {
5455     MEP_INSN_CPSUBUA1_H_P1, "cpsubua1_h_P1", "cpsubua1.h", 32,
5456     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5457   },
5458 /* cpsubla1.h $crqp,$crpp */
5459   {
5460     MEP_INSN_CPSUBLA1_H_P1, "cpsubla1_h_P1", "cpsubla1.h", 32,
5461     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5462   },
5463 /* cpsubaca1u.b $crqp,$crpp */
5464   {
5465     MEP_INSN_CPSUBACA1U_B_P1, "cpsubaca1u_b_P1", "cpsubaca1u.b", 32,
5466     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5467   },
5468 /* cpsubaca1.b $crqp,$crpp */
5469   {
5470     MEP_INSN_CPSUBACA1_B_P1, "cpsubaca1_b_P1", "cpsubaca1.b", 32,
5471     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5472   },
5473 /* cpsubacua1.h $crqp,$crpp */
5474   {
5475     MEP_INSN_CPSUBACUA1_H_P1, "cpsubacua1_h_P1", "cpsubacua1.h", 32,
5476     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5477   },
5478 /* cpsubacla1.h $crqp,$crpp */
5479   {
5480     MEP_INSN_CPSUBACLA1_H_P1, "cpsubacla1_h_P1", "cpsubacla1.h", 32,
5481     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5482   },
5483 /* cpabsa1u.b $crqp,$crpp */
5484   {
5485     MEP_INSN_CPABSA1U_B_P1, "cpabsa1u_b_P1", "cpabsa1u.b", 32,
5486     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5487   },
5488 /* cpabsa1.b $crqp,$crpp */
5489   {
5490     MEP_INSN_CPABSA1_B_P1, "cpabsa1_b_P1", "cpabsa1.b", 32,
5491     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5492   },
5493 /* cpabsua1.h $crqp,$crpp */
5494   {
5495     MEP_INSN_CPABSUA1_H_P1, "cpabsua1_h_P1", "cpabsua1.h", 32,
5496     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5497   },
5498 /* cpabsla1.h $crqp,$crpp */
5499   {
5500     MEP_INSN_CPABSLA1_H_P1, "cpabsla1_h_P1", "cpabsla1.h", 32,
5501     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5502   },
5503 /* cpsada1u.b $crqp,$crpp */
5504   {
5505     MEP_INSN_CPSADA1U_B_P1, "cpsada1u_b_P1", "cpsada1u.b", 32,
5506     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5507   },
5508 /* cpsada1.b $crqp,$crpp */
5509   {
5510     MEP_INSN_CPSADA1_B_P1, "cpsada1_b_P1", "cpsada1.b", 32,
5511     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5512   },
5513 /* cpsadua1.h $crqp,$crpp */
5514   {
5515     MEP_INSN_CPSADUA1_H_P1, "cpsadua1_h_P1", "cpsadua1.h", 32,
5516     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5517   },
5518 /* cpsadla1.h $crqp,$crpp */
5519   {
5520     MEP_INSN_CPSADLA1_H_P1, "cpsadla1_h_P1", "cpsadla1.h", 32,
5521     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5522   },
5523 /* cpseta1.h $crqp,$crpp */
5524   {
5525     MEP_INSN_CPSETA1_H_P1, "cpseta1_h_P1", "cpseta1.h", 32,
5526     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5527   },
5528 /* cpsetua1.w $crqp,$crpp */
5529   {
5530     MEP_INSN_CPSETUA1_W_P1, "cpsetua1_w_P1", "cpsetua1.w", 32,
5531     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5532   },
5533 /* cpsetla1.w $crqp,$crpp */
5534   {
5535     MEP_INSN_CPSETLA1_W_P1, "cpsetla1_w_P1", "cpsetla1.w", 32,
5536     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5537   },
5538 /* cpmova1.b $crop */
5539   {
5540     MEP_INSN_CPMOVA1_B_P1, "cpmova1_b_P1", "cpmova1.b", 32,
5541     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5542   },
5543 /* cpmovua1.h $crop */
5544   {
5545     MEP_INSN_CPMOVUA1_H_P1, "cpmovua1_h_P1", "cpmovua1.h", 32,
5546     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5547   },
5548 /* cpmovla1.h $crop */
5549   {
5550     MEP_INSN_CPMOVLA1_H_P1, "cpmovla1_h_P1", "cpmovla1.h", 32,
5551     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5552   },
5553 /* cpmovuua1.w $crop */
5554   {
5555     MEP_INSN_CPMOVUUA1_W_P1, "cpmovuua1_w_P1", "cpmovuua1.w", 32,
5556     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5557   },
5558 /* cpmovula1.w $crop */
5559   {
5560     MEP_INSN_CPMOVULA1_W_P1, "cpmovula1_w_P1", "cpmovula1.w", 32,
5561     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5562   },
5563 /* cpmovlua1.w $crop */
5564   {
5565     MEP_INSN_CPMOVLUA1_W_P1, "cpmovlua1_w_P1", "cpmovlua1.w", 32,
5566     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5567   },
5568 /* cpmovlla1.w $crop */
5569   {
5570     MEP_INSN_CPMOVLLA1_W_P1, "cpmovlla1_w_P1", "cpmovlla1.w", 32,
5571     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5572   },
5573 /* cppacka1u.b $crop */
5574   {
5575     MEP_INSN_CPPACKA1U_B_P1, "cppacka1u_b_P1", "cppacka1u.b", 32,
5576     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5577   },
5578 /* cppacka1.b $crop */
5579   {
5580     MEP_INSN_CPPACKA1_B_P1, "cppacka1_b_P1", "cppacka1.b", 32,
5581     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5582   },
5583 /* cppackua1.h $crop */
5584   {
5585     MEP_INSN_CPPACKUA1_H_P1, "cppackua1_h_P1", "cppackua1.h", 32,
5586     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5587   },
5588 /* cppackla1.h $crop */
5589   {
5590     MEP_INSN_CPPACKLA1_H_P1, "cppackla1_h_P1", "cppackla1.h", 32,
5591     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5592   },
5593 /* cppackua1.w $crop */
5594   {
5595     MEP_INSN_CPPACKUA1_W_P1, "cppackua1_w_P1", "cppackua1.w", 32,
5596     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5597   },
5598 /* cppackla1.w $crop */
5599   {
5600     MEP_INSN_CPPACKLA1_W_P1, "cppackla1_w_P1", "cppackla1.w", 32,
5601     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5602   },
5603 /* cpmovhua1.w $crop */
5604   {
5605     MEP_INSN_CPMOVHUA1_W_P1, "cpmovhua1_w_P1", "cpmovhua1.w", 32,
5606     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5607   },
5608 /* cpmovhla1.w $crop */
5609   {
5610     MEP_INSN_CPMOVHLA1_W_P1, "cpmovhla1_w_P1", "cpmovhla1.w", 32,
5611     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5612   },
5613 /* cpacsuma1 */
5614   {
5615     MEP_INSN_CPACSUMA1_P1, "cpacsuma1_P1", "cpacsuma1", 32,
5616     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5617   },
5618 /* cpaccpa1 */
5619   {
5620     MEP_INSN_CPACCPA1_P1, "cpaccpa1_P1", "cpaccpa1", 32,
5621     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5622   },
5623 /* cpacswp */
5624   {
5625     MEP_INSN_CPACSWP_P1, "cpacswp_P1", "cpacswp", 32,
5626     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5627   },
5628 /* cpsrla1 $crqp */
5629   {
5630     MEP_INSN_CPSRLA1_P1, "cpsrla1_P1", "cpsrla1", 32,
5631     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5632   },
5633 /* cpsraa1 $crqp */
5634   {
5635     MEP_INSN_CPSRAA1_P1, "cpsraa1_P1", "cpsraa1", 32,
5636     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5637   },
5638 /* cpslla1 $crqp */
5639   {
5640     MEP_INSN_CPSLLA1_P1, "cpslla1_P1", "cpslla1", 32,
5641     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5642   },
5643 /* cpsrlia1 $imm5p23 */
5644   {
5645     MEP_INSN_CPSRLIA1_1_P1, "cpsrlia1_1_p1", "cpsrlia1", 32,
5646     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5647   },
5648 /* cpsraia1 $imm5p23 */
5649   {
5650     MEP_INSN_CPSRAIA1_1_P1, "cpsraia1_1_p1", "cpsraia1", 32,
5651     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5652   },
5653 /* cpsllia1 $imm5p23 */
5654   {
5655     MEP_INSN_CPSLLIA1_1_P1, "cpsllia1_1_p1", "cpsllia1", 32,
5656     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5657   },
5658 /* cpfmulia1s0u.b $crqp,$crpp,$simm8p0 */
5659   {
5660     MEP_INSN_CPFMULIA1S0U_B_P1, "cpfmulia1s0u_b_P1", "cpfmulia1s0u.b", 32,
5661     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5662   },
5663 /* cpfmulia1s0.b $crqp,$crpp,$simm8p0 */
5664   {
5665     MEP_INSN_CPFMULIA1S0_B_P1, "cpfmulia1s0_b_P1", "cpfmulia1s0.b", 32,
5666     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5667   },
5668 /* cpfmuliua1s0.h $crqp,$crpp,$simm8p0 */
5669   {
5670     MEP_INSN_CPFMULIUA1S0_H_P1, "cpfmuliua1s0_h_P1", "cpfmuliua1s0.h", 32,
5671     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5672   },
5673 /* cpfmulila1s0.h $crqp,$crpp,$simm8p0 */
5674   {
5675     MEP_INSN_CPFMULILA1S0_H_P1, "cpfmulila1s0_h_P1", "cpfmulila1s0.h", 32,
5676     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5677   },
5678 /* cpfmadia1s0u.b $crqp,$crpp,$simm8p0 */
5679   {
5680     MEP_INSN_CPFMADIA1S0U_B_P1, "cpfmadia1s0u_b_P1", "cpfmadia1s0u.b", 32,
5681     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5682   },
5683 /* cpfmadia1s0.b $crqp,$crpp,$simm8p0 */
5684   {
5685     MEP_INSN_CPFMADIA1S0_B_P1, "cpfmadia1s0_b_P1", "cpfmadia1s0.b", 32,
5686     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5687   },
5688 /* cpfmadiua1s0.h $crqp,$crpp,$simm8p0 */
5689   {
5690     MEP_INSN_CPFMADIUA1S0_H_P1, "cpfmadiua1s0_h_P1", "cpfmadiua1s0.h", 32,
5691     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5692   },
5693 /* cpfmadila1s0.h $crqp,$crpp,$simm8p0 */
5694   {
5695     MEP_INSN_CPFMADILA1S0_H_P1, "cpfmadila1s0_h_P1", "cpfmadila1s0.h", 32,
5696     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5697   },
5698 /* cpfmulia1s1u.b $crqp,$crpp,$simm8p0 */
5699   {
5700     MEP_INSN_CPFMULIA1S1U_B_P1, "cpfmulia1s1u_b_P1", "cpfmulia1s1u.b", 32,
5701     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5702   },
5703 /* cpfmulia1s1.b $crqp,$crpp,$simm8p0 */
5704   {
5705     MEP_INSN_CPFMULIA1S1_B_P1, "cpfmulia1s1_b_P1", "cpfmulia1s1.b", 32,
5706     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5707   },
5708 /* cpfmuliua1s1.h $crqp,$crpp,$simm8p0 */
5709   {
5710     MEP_INSN_CPFMULIUA1S1_H_P1, "cpfmuliua1s1_h_P1", "cpfmuliua1s1.h", 32,
5711     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5712   },
5713 /* cpfmulila1s1.h $crqp,$crpp,$simm8p0 */
5714   {
5715     MEP_INSN_CPFMULILA1S1_H_P1, "cpfmulila1s1_h_P1", "cpfmulila1s1.h", 32,
5716     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5717   },
5718 /* cpfmadia1s1u.b $crqp,$crpp,$simm8p0 */
5719   {
5720     MEP_INSN_CPFMADIA1S1U_B_P1, "cpfmadia1s1u_b_P1", "cpfmadia1s1u.b", 32,
5721     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5722   },
5723 /* cpfmadia1s1.b $crqp,$crpp,$simm8p0 */
5724   {
5725     MEP_INSN_CPFMADIA1S1_B_P1, "cpfmadia1s1_b_P1", "cpfmadia1s1.b", 32,
5726     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5727   },
5728 /* cpfmadiua1s1.h $crqp,$crpp,$simm8p0 */
5729   {
5730     MEP_INSN_CPFMADIUA1S1_H_P1, "cpfmadiua1s1_h_P1", "cpfmadiua1s1.h", 32,
5731     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5732   },
5733 /* cpfmadila1s1.h $crqp,$crpp,$simm8p0 */
5734   {
5735     MEP_INSN_CPFMADILA1S1_H_P1, "cpfmadila1s1_h_P1", "cpfmadila1s1.h", 32,
5736     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5737   },
5738 /* cpamulia1u.b $crqp,$crpp,$simm8p0 */
5739   {
5740     MEP_INSN_CPAMULIA1U_B_P1, "cpamulia1u_b_P1", "cpamulia1u.b", 32,
5741     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5742   },
5743 /* cpamulia1.b $crqp,$crpp,$simm8p0 */
5744   {
5745     MEP_INSN_CPAMULIA1_B_P1, "cpamulia1_b_P1", "cpamulia1.b", 32,
5746     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5747   },
5748 /* cpamuliua1.h $crqp,$crpp,$simm8p0 */
5749   {
5750     MEP_INSN_CPAMULIUA1_H_P1, "cpamuliua1_h_P1", "cpamuliua1.h", 32,
5751     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5752   },
5753 /* cpamulila1.h $crqp,$crpp,$simm8p0 */
5754   {
5755     MEP_INSN_CPAMULILA1_H_P1, "cpamulila1_h_P1", "cpamulila1.h", 32,
5756     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5757   },
5758 /* cpamadia1u.b $crqp,$crpp,$simm8p0 */
5759   {
5760     MEP_INSN_CPAMADIA1U_B_P1, "cpamadia1u_b_P1", "cpamadia1u.b", 32,
5761     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5762   },
5763 /* cpamadia1.b $crqp,$crpp,$simm8p0 */
5764   {
5765     MEP_INSN_CPAMADIA1_B_P1, "cpamadia1_b_P1", "cpamadia1.b", 32,
5766     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5767   },
5768 /* cpamadiua1.h $crqp,$crpp,$simm8p0 */
5769   {
5770     MEP_INSN_CPAMADIUA1_H_P1, "cpamadiua1_h_P1", "cpamadiua1.h", 32,
5771     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5772   },
5773 /* cpamadila1.h $crqp,$crpp,$simm8p0 */
5774   {
5775     MEP_INSN_CPAMADILA1_H_P1, "cpamadila1_h_P1", "cpamadila1.h", 32,
5776     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5777   },
5778 /* cpfmulia1u.b $crqp,$crpp,$imm3p25,$simm8p0 */
5779   {
5780     MEP_INSN_CPFMULIA1U_B_P1, "cpfmulia1u_b_P1", "cpfmulia1u.b", 32,
5781     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5782   },
5783 /* cpfmulia1.b $crqp,$crpp,$imm3p25,$simm8p0 */
5784   {
5785     MEP_INSN_CPFMULIA1_B_P1, "cpfmulia1_b_P1", "cpfmulia1.b", 32,
5786     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5787   },
5788 /* cpfmuliua1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5789   {
5790     MEP_INSN_CPFMULIUA1_H_P1, "cpfmuliua1_h_P1", "cpfmuliua1.h", 32,
5791     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5792   },
5793 /* cpfmulila1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5794   {
5795     MEP_INSN_CPFMULILA1_H_P1, "cpfmulila1_h_P1", "cpfmulila1.h", 32,
5796     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5797   },
5798 /* cpfmadia1u.b $crqp,$crpp,$imm3p25,$simm8p0 */
5799   {
5800     MEP_INSN_CPFMADIA1U_B_P1, "cpfmadia1u_b_P1", "cpfmadia1u.b", 32,
5801     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5802   },
5803 /* cpfmadia1.b $crqp,$crpp,$imm3p25,$simm8p0 */
5804   {
5805     MEP_INSN_CPFMADIA1_B_P1, "cpfmadia1_b_P1", "cpfmadia1.b", 32,
5806     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5807   },
5808 /* cpfmadiua1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5809   {
5810     MEP_INSN_CPFMADIUA1_H_P1, "cpfmadiua1_h_P1", "cpfmadiua1.h", 32,
5811     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5812   },
5813 /* cpfmadila1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5814   {
5815     MEP_INSN_CPFMADILA1_H_P1, "cpfmadila1_h_P1", "cpfmadila1.h", 32,
5816     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5817   },
5818 /* cpssqa1u.b $crqp,$crpp */
5819   {
5820     MEP_INSN_CPSSQA1U_B_P1, "cpssqa1u_b_P1", "cpssqa1u.b", 32,
5821     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5822   },
5823 /* cpssqa1.b $crqp,$crpp */
5824   {
5825     MEP_INSN_CPSSQA1_B_P1, "cpssqa1_b_P1", "cpssqa1.b", 32,
5826     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5827   },
5828 /* cpssda1u.b $crqp,$crpp */
5829   {
5830     MEP_INSN_CPSSDA1U_B_P1, "cpssda1u_b_P1", "cpssda1u.b", 32,
5831     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5832   },
5833 /* cpssda1.b $crqp,$crpp */
5834   {
5835     MEP_INSN_CPSSDA1_B_P1, "cpssda1_b_P1", "cpssda1.b", 32,
5836     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5837   },
5838 /* cpmula1u.b $crqp,$crpp */
5839   {
5840     MEP_INSN_CPMULA1U_B_P1, "cpmula1u_b_P1", "cpmula1u.b", 32,
5841     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5842   },
5843 /* cpmula1.b $crqp,$crpp */
5844   {
5845     MEP_INSN_CPMULA1_B_P1, "cpmula1_b_P1", "cpmula1.b", 32,
5846     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5847   },
5848 /* cpmulua1.h $crqp,$crpp */
5849   {
5850     MEP_INSN_CPMULUA1_H_P1, "cpmulua1_h_P1", "cpmulua1.h", 32,
5851     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5852   },
5853 /* cpmulla1.h $crqp,$crpp */
5854   {
5855     MEP_INSN_CPMULLA1_H_P1, "cpmulla1_h_P1", "cpmulla1.h", 32,
5856     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5857   },
5858 /* cpmulua1u.w $crqp,$crpp */
5859   {
5860     MEP_INSN_CPMULUA1U_W_P1, "cpmulua1u_w_P1", "cpmulua1u.w", 32,
5861     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5862   },
5863 /* cpmulla1u.w $crqp,$crpp */
5864   {
5865     MEP_INSN_CPMULLA1U_W_P1, "cpmulla1u_w_P1", "cpmulla1u.w", 32,
5866     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5867   },
5868 /* cpmulua1.w $crqp,$crpp */
5869   {
5870     MEP_INSN_CPMULUA1_W_P1, "cpmulua1_w_P1", "cpmulua1.w", 32,
5871     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5872   },
5873 /* cpmulla1.w $crqp,$crpp */
5874   {
5875     MEP_INSN_CPMULLA1_W_P1, "cpmulla1_w_P1", "cpmulla1.w", 32,
5876     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5877   },
5878 /* cpmada1u.b $crqp,$crpp */
5879   {
5880     MEP_INSN_CPMADA1U_B_P1, "cpmada1u_b_P1", "cpmada1u.b", 32,
5881     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5882   },
5883 /* cpmada1.b $crqp,$crpp */
5884   {
5885     MEP_INSN_CPMADA1_B_P1, "cpmada1_b_P1", "cpmada1.b", 32,
5886     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5887   },
5888 /* cpmadua1.h $crqp,$crpp */
5889   {
5890     MEP_INSN_CPMADUA1_H_P1, "cpmadua1_h_P1", "cpmadua1.h", 32,
5891     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5892   },
5893 /* cpmadla1.h $crqp,$crpp */
5894   {
5895     MEP_INSN_CPMADLA1_H_P1, "cpmadla1_h_P1", "cpmadla1.h", 32,
5896     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5897   },
5898 /* cpmadua1u.w $crqp,$crpp */
5899   {
5900     MEP_INSN_CPMADUA1U_W_P1, "cpmadua1u_w_P1", "cpmadua1u.w", 32,
5901     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5902   },
5903 /* cpmadla1u.w $crqp,$crpp */
5904   {
5905     MEP_INSN_CPMADLA1U_W_P1, "cpmadla1u_w_P1", "cpmadla1u.w", 32,
5906     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5907   },
5908 /* cpmadua1.w $crqp,$crpp */
5909   {
5910     MEP_INSN_CPMADUA1_W_P1, "cpmadua1_w_P1", "cpmadua1.w", 32,
5911     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5912   },
5913 /* cpmadla1.w $crqp,$crpp */
5914   {
5915     MEP_INSN_CPMADLA1_W_P1, "cpmadla1_w_P1", "cpmadla1.w", 32,
5916     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5917   },
5918 /* cpmsbua1.h $crqp,$crpp */
5919   {
5920     MEP_INSN_CPMSBUA1_H_P1, "cpmsbua1_h_P1", "cpmsbua1.h", 32,
5921     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5922   },
5923 /* cpmsbla1.h $crqp,$crpp */
5924   {
5925     MEP_INSN_CPMSBLA1_H_P1, "cpmsbla1_h_P1", "cpmsbla1.h", 32,
5926     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5927   },
5928 /* cpmsbua1u.w $crqp,$crpp */
5929   {
5930     MEP_INSN_CPMSBUA1U_W_P1, "cpmsbua1u_w_P1", "cpmsbua1u.w", 32,
5931     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5932   },
5933 /* cpmsbla1u.w $crqp,$crpp */
5934   {
5935     MEP_INSN_CPMSBLA1U_W_P1, "cpmsbla1u_w_P1", "cpmsbla1u.w", 32,
5936     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5937   },
5938 /* cpmsbua1.w $crqp,$crpp */
5939   {
5940     MEP_INSN_CPMSBUA1_W_P1, "cpmsbua1_w_P1", "cpmsbua1.w", 32,
5941     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5942   },
5943 /* cpmsbla1.w $crqp,$crpp */
5944   {
5945     MEP_INSN_CPMSBLA1_W_P1, "cpmsbla1_w_P1", "cpmsbla1.w", 32,
5946     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5947   },
5948 /* cpsmadua1.h $crqp,$crpp */
5949   {
5950     MEP_INSN_CPSMADUA1_H_P1, "cpsmadua1_h_P1", "cpsmadua1.h", 32,
5951     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5952   },
5953 /* cpsmadla1.h $crqp,$crpp */
5954   {
5955     MEP_INSN_CPSMADLA1_H_P1, "cpsmadla1_h_P1", "cpsmadla1.h", 32,
5956     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5957   },
5958 /* cpsmadua1.w $crqp,$crpp */
5959   {
5960     MEP_INSN_CPSMADUA1_W_P1, "cpsmadua1_w_P1", "cpsmadua1.w", 32,
5961     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5962   },
5963 /* cpsmadla1.w $crqp,$crpp */
5964   {
5965     MEP_INSN_CPSMADLA1_W_P1, "cpsmadla1_w_P1", "cpsmadla1.w", 32,
5966     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5967   },
5968 /* cpsmsbua1.h $crqp,$crpp */
5969   {
5970     MEP_INSN_CPSMSBUA1_H_P1, "cpsmsbua1_h_P1", "cpsmsbua1.h", 32,
5971     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5972   },
5973 /* cpsmsbla1.h $crqp,$crpp */
5974   {
5975     MEP_INSN_CPSMSBLA1_H_P1, "cpsmsbla1_h_P1", "cpsmsbla1.h", 32,
5976     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5977   },
5978 /* cpsmsbua1.w $crqp,$crpp */
5979   {
5980     MEP_INSN_CPSMSBUA1_W_P1, "cpsmsbua1_w_P1", "cpsmsbua1.w", 32,
5981     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5982   },
5983 /* cpsmsbla1.w $crqp,$crpp */
5984   {
5985     MEP_INSN_CPSMSBLA1_W_P1, "cpsmsbla1_w_P1", "cpsmsbla1.w", 32,
5986     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5987   },
5988 /* cpmulslua1.h $crqp,$crpp */
5989   {
5990     MEP_INSN_CPMULSLUA1_H_P1, "cpmulslua1_h_P1", "cpmulslua1.h", 32,
5991     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5992   },
5993 /* cpmulslla1.h $crqp,$crpp */
5994   {
5995     MEP_INSN_CPMULSLLA1_H_P1, "cpmulslla1_h_P1", "cpmulslla1.h", 32,
5996     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5997   },
5998 /* cpmulslua1.w $crqp,$crpp */
5999   {
6000     MEP_INSN_CPMULSLUA1_W_P1, "cpmulslua1_w_P1", "cpmulslua1.w", 32,
6001     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6002   },
6003 /* cpmulslla1.w $crqp,$crpp */
6004   {
6005     MEP_INSN_CPMULSLLA1_W_P1, "cpmulslla1_w_P1", "cpmulslla1.w", 32,
6006     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6007   },
6008 /* cpsmadslua1.h $crqp,$crpp */
6009   {
6010     MEP_INSN_CPSMADSLUA1_H_P1, "cpsmadslua1_h_P1", "cpsmadslua1.h", 32,
6011     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6012   },
6013 /* cpsmadslla1.h $crqp,$crpp */
6014   {
6015     MEP_INSN_CPSMADSLLA1_H_P1, "cpsmadslla1_h_P1", "cpsmadslla1.h", 32,
6016     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6017   },
6018 /* cpsmadslua1.w $crqp,$crpp */
6019   {
6020     MEP_INSN_CPSMADSLUA1_W_P1, "cpsmadslua1_w_P1", "cpsmadslua1.w", 32,
6021     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6022   },
6023 /* cpsmadslla1.w $crqp,$crpp */
6024   {
6025     MEP_INSN_CPSMADSLLA1_W_P1, "cpsmadslla1_w_P1", "cpsmadslla1.w", 32,
6026     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6027   },
6028 /* cpsmsbslua1.h $crqp,$crpp */
6029   {
6030     MEP_INSN_CPSMSBSLUA1_H_P1, "cpsmsbslua1_h_P1", "cpsmsbslua1.h", 32,
6031     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6032   },
6033 /* cpsmsbslla1.h $crqp,$crpp */
6034   {
6035     MEP_INSN_CPSMSBSLLA1_H_P1, "cpsmsbslla1_h_P1", "cpsmsbslla1.h", 32,
6036     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6037   },
6038 /* cpsmsbslua1.w $crqp,$crpp */
6039   {
6040     MEP_INSN_CPSMSBSLUA1_W_P1, "cpsmsbslua1_w_P1", "cpsmsbslua1.w", 32,
6041     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6042   },
6043 /* cpsmsbslla1.w $crqp,$crpp */
6044   {
6045     MEP_INSN_CPSMSBSLLA1_W_P1, "cpsmsbslla1_w_P1", "cpsmsbslla1.w", 32,
6046     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6047   },
6048 };
6049
6050 #undef OP
6051 #undef A
6052
6053 /* Initialize anything needed to be done once, before any cpu_open call.  */
6054
6055 static void
6056 init_tables (void)
6057 {
6058 }
6059
6060 #ifndef opcodes_error_handler
6061 #define opcodes_error_handler(...) \
6062   fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
6063 #endif
6064
6065 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
6066 static void build_hw_table      (CGEN_CPU_TABLE *);
6067 static void build_ifield_table  (CGEN_CPU_TABLE *);
6068 static void build_operand_table (CGEN_CPU_TABLE *);
6069 static void build_insn_table    (CGEN_CPU_TABLE *);
6070 static void mep_cgen_rebuild_tables (CGEN_CPU_TABLE *);
6071
6072 /* Subroutine of mep_cgen_cpu_open to look up a mach via its bfd name.  */
6073
6074 static const CGEN_MACH *
6075 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
6076 {
6077   while (table->name)
6078     {
6079       if (strcmp (name, table->bfd_name) == 0)
6080         return table;
6081       ++table;
6082     }
6083   return NULL;
6084 }
6085
6086 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
6087
6088 static void
6089 build_hw_table (CGEN_CPU_TABLE *cd)
6090 {
6091   int i;
6092   int machs = cd->machs;
6093   const CGEN_HW_ENTRY *init = & mep_cgen_hw_table[0];
6094   /* MAX_HW is only an upper bound on the number of selected entries.
6095      However each entry is indexed by it's enum so there can be holes in
6096      the table.  */
6097   const CGEN_HW_ENTRY **selected =
6098     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
6099
6100   cd->hw_table.init_entries = init;
6101   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
6102   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
6103   /* ??? For now we just use machs to determine which ones we want.  */
6104   for (i = 0; init[i].name != NULL; ++i)
6105     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
6106         & machs)
6107       selected[init[i].type] = &init[i];
6108   cd->hw_table.entries = selected;
6109   cd->hw_table.num_entries = MAX_HW;
6110 }
6111
6112 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
6113
6114 static void
6115 build_ifield_table (CGEN_CPU_TABLE *cd)
6116 {
6117   cd->ifld_table = & mep_cgen_ifld_table[0];
6118 }
6119
6120 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
6121
6122 static void
6123 build_operand_table (CGEN_CPU_TABLE *cd)
6124 {
6125   int i;
6126   int machs = cd->machs;
6127   const CGEN_OPERAND *init = & mep_cgen_operand_table[0];
6128   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
6129      However each entry is indexed by it's enum so there can be holes in
6130      the table.  */
6131   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
6132
6133   cd->operand_table.init_entries = init;
6134   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
6135   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6136   /* ??? For now we just use mach to determine which ones we want.  */
6137   for (i = 0; init[i].name != NULL; ++i)
6138     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
6139         & machs)
6140       selected[init[i].type] = &init[i];
6141   cd->operand_table.entries = selected;
6142   cd->operand_table.num_entries = MAX_OPERANDS;
6143 }
6144
6145 /* Subroutine of mep_cgen_cpu_open to build the hardware table.
6146    ??? This could leave out insns not supported by the specified mach/isa,
6147    but that would cause errors like "foo only supported by bar" to become
6148    "unknown insn", so for now we include all insns and require the app to
6149    do the checking later.
6150    ??? On the other hand, parsing of such insns may require their hardware or
6151    operand elements to be in the table [which they mightn't be].  */
6152
6153 static void
6154 build_insn_table (CGEN_CPU_TABLE *cd)
6155 {
6156   int i;
6157   const CGEN_IBASE *ib = & mep_cgen_insn_table[0];
6158   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
6159
6160   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
6161   for (i = 0; i < MAX_INSNS; ++i)
6162     insns[i].base = &ib[i];
6163   cd->insn_table.init_entries = insns;
6164   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
6165   cd->insn_table.num_init_entries = MAX_INSNS;
6166 }
6167
6168 /* Subroutine of mep_cgen_cpu_open to rebuild the tables.  */
6169
6170 static void
6171 mep_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
6172 {
6173   int i;
6174   CGEN_BITSET *isas = cd->isas;
6175   unsigned int machs = cd->machs;
6176
6177   cd->int_insn_p = CGEN_INT_INSN_P;
6178
6179   /* Data derived from the isa spec.  */
6180 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
6181   cd->default_insn_bitsize = UNSET;
6182   cd->base_insn_bitsize = UNSET;
6183   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
6184   cd->max_insn_bitsize = 0;
6185   for (i = 0; i < MAX_ISAS; ++i)
6186     if (cgen_bitset_contains (isas, i))
6187       {
6188         const CGEN_ISA *isa = & mep_cgen_isa_table[i];
6189
6190         /* Default insn sizes of all selected isas must be
6191            equal or we set the result to 0, meaning "unknown".  */
6192         if (cd->default_insn_bitsize == UNSET)
6193           cd->default_insn_bitsize = isa->default_insn_bitsize;
6194         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
6195           ; /* This is ok.  */
6196         else
6197           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
6198
6199         /* Base insn sizes of all selected isas must be equal
6200            or we set the result to 0, meaning "unknown".  */
6201         if (cd->base_insn_bitsize == UNSET)
6202           cd->base_insn_bitsize = isa->base_insn_bitsize;
6203         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
6204           ; /* This is ok.  */
6205         else
6206           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
6207
6208         /* Set min,max insn sizes.  */
6209         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
6210           cd->min_insn_bitsize = isa->min_insn_bitsize;
6211         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
6212           cd->max_insn_bitsize = isa->max_insn_bitsize;
6213       }
6214
6215   /* Data derived from the mach spec.  */
6216   for (i = 0; i < MAX_MACHS; ++i)
6217     if (((1 << i) & machs) != 0)
6218       {
6219         const CGEN_MACH *mach = & mep_cgen_mach_table[i];
6220
6221         if (mach->insn_chunk_bitsize != 0)
6222         {
6223           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
6224             {
6225               opcodes_error_handler
6226                 (/* xgettext:c-format */
6227                  _("internal error: mep_cgen_rebuild_tables: "
6228                    "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
6229                  cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
6230               abort ();
6231             }
6232
6233           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
6234         }
6235       }
6236
6237   /* Determine which hw elements are used by MACH.  */
6238   build_hw_table (cd);
6239
6240   /* Build the ifield table.  */
6241   build_ifield_table (cd);
6242
6243   /* Determine which operands are used by MACH/ISA.  */
6244   build_operand_table (cd);
6245
6246   /* Build the instruction table.  */
6247   build_insn_table (cd);
6248 }
6249
6250 /* Initialize a cpu table and return a descriptor.
6251    It's much like opening a file, and must be the first function called.
6252    The arguments are a set of (type/value) pairs, terminated with
6253    CGEN_CPU_OPEN_END.
6254
6255    Currently supported values:
6256    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
6257    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
6258    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
6259    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
6260    CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
6261    CGEN_CPU_OPEN_END:     terminates arguments
6262
6263    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
6264    precluded.  */
6265
6266 CGEN_CPU_DESC
6267 mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
6268 {
6269   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
6270   static int init_p;
6271   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
6272   unsigned int machs = 0; /* 0 = "unspecified" */
6273   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
6274   enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
6275   va_list ap;
6276
6277   if (! init_p)
6278     {
6279       init_tables ();
6280       init_p = 1;
6281     }
6282
6283   memset (cd, 0, sizeof (*cd));
6284
6285   va_start (ap, arg_type);
6286   while (arg_type != CGEN_CPU_OPEN_END)
6287     {
6288       switch (arg_type)
6289         {
6290         case CGEN_CPU_OPEN_ISAS :
6291           isas = va_arg (ap, CGEN_BITSET *);
6292           break;
6293         case CGEN_CPU_OPEN_MACHS :
6294           machs = va_arg (ap, unsigned int);
6295           break;
6296         case CGEN_CPU_OPEN_BFDMACH :
6297           {
6298             const char *name = va_arg (ap, const char *);
6299             const CGEN_MACH *mach =
6300               lookup_mach_via_bfd_name (mep_cgen_mach_table, name);
6301
6302             if (mach != NULL)
6303               machs |= 1 << mach->num;
6304             break;
6305           }
6306         case CGEN_CPU_OPEN_ENDIAN :
6307           endian = va_arg (ap, enum cgen_endian);
6308           break;
6309         case CGEN_CPU_OPEN_INSN_ENDIAN :
6310           insn_endian = va_arg (ap, enum cgen_endian);
6311           break;
6312         default :
6313           opcodes_error_handler
6314             (/* xgettext:c-format */
6315              _("internal error: mep_cgen_cpu_open: "
6316                "unsupported argument `%d'"),
6317              arg_type);
6318           abort (); /* ??? return NULL? */
6319         }
6320       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
6321     }
6322   va_end (ap);
6323
6324   /* Mach unspecified means "all".  */
6325   if (machs == 0)
6326     machs = (1 << MAX_MACHS) - 1;
6327   /* Base mach is always selected.  */
6328   machs |= 1;
6329   if (endian == CGEN_ENDIAN_UNKNOWN)
6330     {
6331       /* ??? If target has only one, could have a default.  */
6332       opcodes_error_handler
6333         (/* xgettext:c-format */
6334          _("internal error: mep_cgen_cpu_open: no endianness specified"));
6335       abort ();
6336     }
6337
6338   cd->isas = cgen_bitset_copy (isas);
6339   cd->machs = machs;
6340   cd->endian = endian;
6341   cd->insn_endian
6342     = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
6343
6344   /* Table (re)builder.  */
6345   cd->rebuild_tables = mep_cgen_rebuild_tables;
6346   mep_cgen_rebuild_tables (cd);
6347
6348   /* Default to not allowing signed overflow.  */
6349   cd->signed_overflow_ok_p = 0;
6350
6351   return (CGEN_CPU_DESC) cd;
6352 }
6353
6354 /* Cover fn to mep_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
6355    MACH_NAME is the bfd name of the mach.  */
6356
6357 CGEN_CPU_DESC
6358 mep_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
6359 {
6360   return mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
6361                                CGEN_CPU_OPEN_ENDIAN, endian,
6362                                CGEN_CPU_OPEN_END);
6363 }
6364
6365 /* Close a cpu table.
6366    ??? This can live in a machine independent file, but there's currently
6367    no place to put this file (there's no libcgen).  libopcodes is the wrong
6368    place as some simulator ports use this but they don't use libopcodes.  */
6369
6370 void
6371 mep_cgen_cpu_close (CGEN_CPU_DESC cd)
6372 {
6373   unsigned int i;
6374   const CGEN_INSN *insns;
6375
6376   if (cd->macro_insn_table.init_entries)
6377     {
6378       insns = cd->macro_insn_table.init_entries;
6379       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
6380         if (CGEN_INSN_RX ((insns)))
6381           regfree (CGEN_INSN_RX (insns));
6382     }
6383
6384   if (cd->insn_table.init_entries)
6385     {
6386       insns = cd->insn_table.init_entries;
6387       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
6388         if (CGEN_INSN_RX (insns))
6389           regfree (CGEN_INSN_RX (insns));
6390     }
6391
6392   free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
6393   free ((CGEN_INSN *) cd->insn_table.init_entries);
6394   free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
6395   free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
6396   free (cd);
6397 }
6398