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* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
[binutils-gdb.git] / opcodes / mips-dis.c
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
63 static const char * const mips_gpr_names_numeric[32] =
64 {
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
69 };
70
71 static const char * const mips_gpr_names_oldabi[32] =
72 {
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
77 };
78
79 static const char * const mips_gpr_names_newabi[32] =
80 {
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85 };
86
87 static const char * const mips_fpr_names_numeric[32] =
88 {
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93 };
94
95 static const char * const mips_fpr_names_32[32] =
96 {
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101 };
102
103 static const char * const mips_fpr_names_n32[32] =
104 {
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109 };
110
111 static const char * const mips_fpr_names_64[32] =
112 {
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117 };
118
119 static const char * const mips_cp0_names_numeric[32] =
120 {
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125 };
126
127 static const char * const mips_cp0_names_mips3264[32] =
128 {
129 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
130 "c0_context", "c0_pagemask", "c0_wired", "$7",
131 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
132 "c0_status", "c0_cause", "c0_epc", "c0_prid",
133 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
134 "c0_xcontext", "$21", "$22", "c0_debug",
135 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
136 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
137 };
138
139 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
140 {
141 { 16, 1, "c0_config1" },
142 { 16, 2, "c0_config2" },
143 { 16, 3, "c0_config3" },
144 { 18, 1, "c0_watchlo,1" },
145 { 18, 2, "c0_watchlo,2" },
146 { 18, 3, "c0_watchlo,3" },
147 { 18, 4, "c0_watchlo,4" },
148 { 18, 5, "c0_watchlo,5" },
149 { 18, 6, "c0_watchlo,6" },
150 { 18, 7, "c0_watchlo,7" },
151 { 19, 1, "c0_watchhi,1" },
152 { 19, 2, "c0_watchhi,2" },
153 { 19, 3, "c0_watchhi,3" },
154 { 19, 4, "c0_watchhi,4" },
155 { 19, 5, "c0_watchhi,5" },
156 { 19, 6, "c0_watchhi,6" },
157 { 19, 7, "c0_watchhi,7" },
158 { 25, 1, "c0_perfcnt,1" },
159 { 25, 2, "c0_perfcnt,2" },
160 { 25, 3, "c0_perfcnt,3" },
161 { 25, 4, "c0_perfcnt,4" },
162 { 25, 5, "c0_perfcnt,5" },
163 { 25, 6, "c0_perfcnt,6" },
164 { 25, 7, "c0_perfcnt,7" },
165 { 27, 1, "c0_cacheerr,1" },
166 { 27, 2, "c0_cacheerr,2" },
167 { 27, 3, "c0_cacheerr,3" },
168 { 28, 1, "c0_datalo" },
169 { 29, 1, "c0_datahi" }
170 };
171
172 static const char * const mips_cp0_names_mips3264r2[32] =
173 {
174 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
175 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
176 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
177 "c0_status", "c0_cause", "c0_epc", "c0_prid",
178 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
179 "c0_xcontext", "$21", "$22", "c0_debug",
180 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
181 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
182 };
183
184 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
185 {
186 { 4, 1, "c0_contextconfig" },
187 { 0, 1, "c0_mvpcontrol" },
188 { 0, 2, "c0_mvpconf0" },
189 { 0, 3, "c0_mvpconf1" },
190 { 1, 1, "c0_vpecontrol" },
191 { 1, 2, "c0_vpeconf0" },
192 { 1, 3, "c0_vpeconf1" },
193 { 1, 4, "c0_yqmask" },
194 { 1, 5, "c0_vpeschedule" },
195 { 1, 6, "c0_vpeschefback" },
196 { 2, 1, "c0_tcstatus" },
197 { 2, 2, "c0_tcbind" },
198 { 2, 3, "c0_tcrestart" },
199 { 2, 4, "c0_tchalt" },
200 { 2, 5, "c0_tccontext" },
201 { 2, 6, "c0_tcschedule" },
202 { 2, 7, "c0_tcschefback" },
203 { 5, 1, "c0_pagegrain" },
204 { 6, 1, "c0_srsconf0" },
205 { 6, 2, "c0_srsconf1" },
206 { 6, 3, "c0_srsconf2" },
207 { 6, 4, "c0_srsconf3" },
208 { 6, 5, "c0_srsconf4" },
209 { 12, 1, "c0_intctl" },
210 { 12, 2, "c0_srsctl" },
211 { 12, 3, "c0_srsmap" },
212 { 15, 1, "c0_ebase" },
213 { 16, 1, "c0_config1" },
214 { 16, 2, "c0_config2" },
215 { 16, 3, "c0_config3" },
216 { 18, 1, "c0_watchlo,1" },
217 { 18, 2, "c0_watchlo,2" },
218 { 18, 3, "c0_watchlo,3" },
219 { 18, 4, "c0_watchlo,4" },
220 { 18, 5, "c0_watchlo,5" },
221 { 18, 6, "c0_watchlo,6" },
222 { 18, 7, "c0_watchlo,7" },
223 { 19, 1, "c0_watchhi,1" },
224 { 19, 2, "c0_watchhi,2" },
225 { 19, 3, "c0_watchhi,3" },
226 { 19, 4, "c0_watchhi,4" },
227 { 19, 5, "c0_watchhi,5" },
228 { 19, 6, "c0_watchhi,6" },
229 { 19, 7, "c0_watchhi,7" },
230 { 23, 1, "c0_tracecontrol" },
231 { 23, 2, "c0_tracecontrol2" },
232 { 23, 3, "c0_usertracedata" },
233 { 23, 4, "c0_tracebpc" },
234 { 25, 1, "c0_perfcnt,1" },
235 { 25, 2, "c0_perfcnt,2" },
236 { 25, 3, "c0_perfcnt,3" },
237 { 25, 4, "c0_perfcnt,4" },
238 { 25, 5, "c0_perfcnt,5" },
239 { 25, 6, "c0_perfcnt,6" },
240 { 25, 7, "c0_perfcnt,7" },
241 { 27, 1, "c0_cacheerr,1" },
242 { 27, 2, "c0_cacheerr,2" },
243 { 27, 3, "c0_cacheerr,3" },
244 { 28, 1, "c0_datalo" },
245 { 28, 2, "c0_taglo1" },
246 { 28, 3, "c0_datalo1" },
247 { 28, 4, "c0_taglo2" },
248 { 28, 5, "c0_datalo2" },
249 { 28, 6, "c0_taglo3" },
250 { 28, 7, "c0_datalo3" },
251 { 29, 1, "c0_datahi" },
252 { 29, 2, "c0_taghi1" },
253 { 29, 3, "c0_datahi1" },
254 { 29, 4, "c0_taghi2" },
255 { 29, 5, "c0_datahi2" },
256 { 29, 6, "c0_taghi3" },
257 { 29, 7, "c0_datahi3" },
258 };
259
260 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
261 static const char * const mips_cp0_names_sb1[32] =
262 {
263 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
264 "c0_context", "c0_pagemask", "c0_wired", "$7",
265 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
266 "c0_status", "c0_cause", "c0_epc", "c0_prid",
267 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
268 "c0_xcontext", "$21", "$22", "c0_debug",
269 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
270 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
271 };
272
273 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
274 {
275 { 16, 1, "c0_config1" },
276 { 18, 1, "c0_watchlo,1" },
277 { 19, 1, "c0_watchhi,1" },
278 { 22, 0, "c0_perftrace" },
279 { 23, 3, "c0_edebug" },
280 { 25, 1, "c0_perfcnt,1" },
281 { 25, 2, "c0_perfcnt,2" },
282 { 25, 3, "c0_perfcnt,3" },
283 { 25, 4, "c0_perfcnt,4" },
284 { 25, 5, "c0_perfcnt,5" },
285 { 25, 6, "c0_perfcnt,6" },
286 { 25, 7, "c0_perfcnt,7" },
287 { 26, 1, "c0_buserr_pa" },
288 { 27, 1, "c0_cacheerr_d" },
289 { 27, 3, "c0_cacheerr_d_pa" },
290 { 28, 1, "c0_datalo_i" },
291 { 28, 2, "c0_taglo_d" },
292 { 28, 3, "c0_datalo_d" },
293 { 29, 1, "c0_datahi_i" },
294 { 29, 2, "c0_taghi_d" },
295 { 29, 3, "c0_datahi_d" },
296 };
297
298 static const char * const mips_hwr_names_numeric[32] =
299 {
300 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
301 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
302 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
303 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
304 };
305
306 static const char * const mips_hwr_names_mips3264r2[32] =
307 {
308 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
309 "$4", "$5", "$6", "$7",
310 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
311 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
312 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
313 };
314
315 struct mips_abi_choice
316 {
317 const char * name;
318 const char * const *gpr_names;
319 const char * const *fpr_names;
320 };
321
322 struct mips_abi_choice mips_abi_choices[] =
323 {
324 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
325 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
326 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
327 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
328 };
329
330 struct mips_arch_choice
331 {
332 const char *name;
333 int bfd_mach_valid;
334 unsigned long bfd_mach;
335 int processor;
336 int isa;
337 const char * const *cp0_names;
338 const struct mips_cp0sel_name *cp0sel_names;
339 unsigned int cp0sel_names_len;
340 const char * const *hwr_names;
341 };
342
343 const struct mips_arch_choice mips_arch_choices[] =
344 {
345 { "numeric", 0, 0, 0, 0,
346 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
347
348 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
349 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
350 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
351 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
352 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
353 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
354 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
355 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
356 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
357 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
358 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
359 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
360 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
361 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
362 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
363 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
364 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
365 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
366 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
367 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
368 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
369 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
370 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
371 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
372 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
373 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
374 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
376 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
377 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
378 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
380 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
382 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
384 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
386 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
388 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
389 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
390
391 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
392 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
393 _MIPS32 Architecture For Programmers Volume I: Introduction to the
394 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
395 page 1. */
396 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
397 ISA_MIPS32 | INSN_MIPS16 | INSN_DSP,
398 mips_cp0_names_mips3264,
399 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
400 mips_hwr_names_numeric },
401
402 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
403 ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
404 mips_cp0_names_mips3264r2,
405 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
406 mips_hwr_names_mips3264r2 },
407
408 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
409 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
410 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
411 mips_cp0_names_mips3264,
412 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
413 mips_hwr_names_numeric },
414
415 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
416 ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
417 mips_cp0_names_mips3264r2,
418 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
419 mips_hwr_names_mips3264r2 },
420
421 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
422 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
423 mips_cp0_names_sb1,
424 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
425 mips_hwr_names_numeric },
426
427 /* This entry, mips16, is here only for ISA/processor selection; do
428 not print its name. */
429 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
430 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
431 };
432
433 /* ISA and processor type to disassemble for, and register names to use.
434 set_default_mips_dis_options and parse_mips_dis_options fill in these
435 values. */
436 static int mips_processor;
437 static int mips_isa;
438 static const char * const *mips_gpr_names;
439 static const char * const *mips_fpr_names;
440 static const char * const *mips_cp0_names;
441 static const struct mips_cp0sel_name *mips_cp0sel_names;
442 static int mips_cp0sel_names_len;
443 static const char * const *mips_hwr_names;
444
445 /* Other options */
446 static int no_aliases; /* If set disassemble as most general inst. */
447 \f
448 static const struct mips_abi_choice *
449 choose_abi_by_name (const char *name, unsigned int namelen)
450 {
451 const struct mips_abi_choice *c;
452 unsigned int i;
453
454 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
455 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
456 && strlen (mips_abi_choices[i].name) == namelen)
457 c = &mips_abi_choices[i];
458
459 return c;
460 }
461
462 static const struct mips_arch_choice *
463 choose_arch_by_name (const char *name, unsigned int namelen)
464 {
465 const struct mips_arch_choice *c = NULL;
466 unsigned int i;
467
468 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
469 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
470 && strlen (mips_arch_choices[i].name) == namelen)
471 c = &mips_arch_choices[i];
472
473 return c;
474 }
475
476 static const struct mips_arch_choice *
477 choose_arch_by_number (unsigned long mach)
478 {
479 static unsigned long hint_bfd_mach;
480 static const struct mips_arch_choice *hint_arch_choice;
481 const struct mips_arch_choice *c;
482 unsigned int i;
483
484 /* We optimize this because even if the user specifies no
485 flags, this will be done for every instruction! */
486 if (hint_bfd_mach == mach
487 && hint_arch_choice != NULL
488 && hint_arch_choice->bfd_mach == hint_bfd_mach)
489 return hint_arch_choice;
490
491 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
492 {
493 if (mips_arch_choices[i].bfd_mach_valid
494 && mips_arch_choices[i].bfd_mach == mach)
495 {
496 c = &mips_arch_choices[i];
497 hint_bfd_mach = mach;
498 hint_arch_choice = c;
499 }
500 }
501 return c;
502 }
503
504 /* Check if the object uses NewABI conventions. */
505
506 static int
507 is_newabi (Elf_Internal_Ehdr *header)
508 {
509 /* There are no old-style ABIs which use 64-bit ELF. */
510 if (header->e_ident[EI_CLASS] == ELFCLASS64)
511 return 1;
512
513 /* If a 32-bit ELF file, n32 is a new-style ABI. */
514 if ((header->e_flags & EF_MIPS_ABI2) != 0)
515 return 1;
516
517 return 0;
518 }
519
520 static void
521 set_default_mips_dis_options (struct disassemble_info *info)
522 {
523 const struct mips_arch_choice *chosen_arch;
524
525 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
526 and numeric FPR, CP0 register, and HWR names. */
527 mips_isa = ISA_MIPS3;
528 mips_processor = CPU_R3000;
529 mips_gpr_names = mips_gpr_names_oldabi;
530 mips_fpr_names = mips_fpr_names_numeric;
531 mips_cp0_names = mips_cp0_names_numeric;
532 mips_cp0sel_names = NULL;
533 mips_cp0sel_names_len = 0;
534 mips_hwr_names = mips_hwr_names_numeric;
535 no_aliases = 0;
536
537 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
538 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
539 {
540 Elf_Internal_Ehdr *header;
541
542 header = elf_elfheader (info->section->owner);
543 if (is_newabi (header))
544 mips_gpr_names = mips_gpr_names_newabi;
545 }
546
547 /* Set ISA, architecture, and cp0 register names as best we can. */
548 #if ! SYMTAB_AVAILABLE
549 /* This is running out on a target machine, not in a host tool.
550 FIXME: Where does mips_target_info come from? */
551 target_processor = mips_target_info.processor;
552 mips_isa = mips_target_info.isa;
553 #else
554 chosen_arch = choose_arch_by_number (info->mach);
555 if (chosen_arch != NULL)
556 {
557 mips_processor = chosen_arch->processor;
558 mips_isa = chosen_arch->isa;
559 mips_cp0_names = chosen_arch->cp0_names;
560 mips_cp0sel_names = chosen_arch->cp0sel_names;
561 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
562 mips_hwr_names = chosen_arch->hwr_names;
563 }
564 #endif
565 }
566
567 static void
568 parse_mips_dis_option (const char *option, unsigned int len)
569 {
570 unsigned int i, optionlen, vallen;
571 const char *val;
572 const struct mips_abi_choice *chosen_abi;
573 const struct mips_arch_choice *chosen_arch;
574
575 /* Try to match options that are simple flags */
576 if (strncmp (option, "no-aliases", 10) == 0)
577 {
578 no_aliases = 1;
579 return;
580 }
581
582 /* Look for the = that delimits the end of the option name. */
583 for (i = 0; i < len; i++)
584 if (option[i] == '=')
585 break;
586
587 if (i == 0) /* Invalid option: no name before '='. */
588 return;
589 if (i == len) /* Invalid option: no '='. */
590 return;
591 if (i == (len - 1)) /* Invalid option: no value after '='. */
592 return;
593
594 optionlen = i;
595 val = option + (optionlen + 1);
596 vallen = len - (optionlen + 1);
597
598 if (strncmp ("gpr-names", option, optionlen) == 0
599 && strlen ("gpr-names") == optionlen)
600 {
601 chosen_abi = choose_abi_by_name (val, vallen);
602 if (chosen_abi != NULL)
603 mips_gpr_names = chosen_abi->gpr_names;
604 return;
605 }
606
607 if (strncmp ("fpr-names", option, optionlen) == 0
608 && strlen ("fpr-names") == optionlen)
609 {
610 chosen_abi = choose_abi_by_name (val, vallen);
611 if (chosen_abi != NULL)
612 mips_fpr_names = chosen_abi->fpr_names;
613 return;
614 }
615
616 if (strncmp ("cp0-names", option, optionlen) == 0
617 && strlen ("cp0-names") == optionlen)
618 {
619 chosen_arch = choose_arch_by_name (val, vallen);
620 if (chosen_arch != NULL)
621 {
622 mips_cp0_names = chosen_arch->cp0_names;
623 mips_cp0sel_names = chosen_arch->cp0sel_names;
624 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
625 }
626 return;
627 }
628
629 if (strncmp ("hwr-names", option, optionlen) == 0
630 && strlen ("hwr-names") == optionlen)
631 {
632 chosen_arch = choose_arch_by_name (val, vallen);
633 if (chosen_arch != NULL)
634 mips_hwr_names = chosen_arch->hwr_names;
635 return;
636 }
637
638 if (strncmp ("reg-names", option, optionlen) == 0
639 && strlen ("reg-names") == optionlen)
640 {
641 /* We check both ABI and ARCH here unconditionally, so
642 that "numeric" will do the desirable thing: select
643 numeric register names for all registers. Other than
644 that, a given name probably won't match both. */
645 chosen_abi = choose_abi_by_name (val, vallen);
646 if (chosen_abi != NULL)
647 {
648 mips_gpr_names = chosen_abi->gpr_names;
649 mips_fpr_names = chosen_abi->fpr_names;
650 }
651 chosen_arch = choose_arch_by_name (val, vallen);
652 if (chosen_arch != NULL)
653 {
654 mips_cp0_names = chosen_arch->cp0_names;
655 mips_cp0sel_names = chosen_arch->cp0sel_names;
656 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
657 mips_hwr_names = chosen_arch->hwr_names;
658 }
659 return;
660 }
661
662 /* Invalid option. */
663 }
664
665 static void
666 parse_mips_dis_options (const char *options)
667 {
668 const char *option_end;
669
670 if (options == NULL)
671 return;
672
673 while (*options != '\0')
674 {
675 /* Skip empty options. */
676 if (*options == ',')
677 {
678 options++;
679 continue;
680 }
681
682 /* We know that *options is neither NUL or a comma. */
683 option_end = options + 1;
684 while (*option_end != ',' && *option_end != '\0')
685 option_end++;
686
687 parse_mips_dis_option (options, option_end - options);
688
689 /* Go on to the next one. If option_end points to a comma, it
690 will be skipped above. */
691 options = option_end;
692 }
693 }
694
695 static const struct mips_cp0sel_name *
696 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
697 unsigned int len,
698 unsigned int cp0reg,
699 unsigned int sel)
700 {
701 unsigned int i;
702
703 for (i = 0; i < len; i++)
704 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
705 return &names[i];
706 return NULL;
707 }
708 \f
709 /* Print insn arguments for 32/64-bit code. */
710
711 static void
712 print_insn_args (const char *d,
713 register unsigned long int l,
714 bfd_vma pc,
715 struct disassemble_info *info,
716 const struct mips_opcode *opp)
717 {
718 int op, delta;
719 unsigned int lsb, msb, msbd;
720
721 lsb = 0;
722
723 for (; *d != '\0'; d++)
724 {
725 switch (*d)
726 {
727 case ',':
728 case '(':
729 case ')':
730 case '[':
731 case ']':
732 (*info->fprintf_func) (info->stream, "%c", *d);
733 break;
734
735 case '+':
736 /* Extension character; switch for second char. */
737 d++;
738 switch (*d)
739 {
740 case '\0':
741 /* xgettext:c-format */
742 (*info->fprintf_func) (info->stream,
743 _("# internal error, incomplete extension sequence (+)"));
744 return;
745
746 case 'A':
747 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
748 (*info->fprintf_func) (info->stream, "0x%x", lsb);
749 break;
750
751 case 'B':
752 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
753 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
754 break;
755
756 case '1':
757 (*info->fprintf_func) (info->stream, "0x%lx",
758 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
759 break;
760
761 case '2':
762 (*info->fprintf_func) (info->stream, "0x%lx",
763 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
764 break;
765
766 case '3':
767 (*info->fprintf_func) (info->stream, "0x%lx",
768 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
769 break;
770
771 case '4':
772 (*info->fprintf_func) (info->stream, "0x%lx",
773 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
774 break;
775
776 case 'C':
777 case 'H':
778 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
779 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
780 break;
781
782 case 'D':
783 {
784 const struct mips_cp0sel_name *n;
785 unsigned int cp0reg, sel;
786
787 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
788 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
789
790 /* CP0 register including 'sel' code for mtcN (et al.), to be
791 printed textually if known. If not known, print both
792 CP0 register name and sel numerically since CP0 register
793 with sel 0 may have a name unrelated to register being
794 printed. */
795 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
796 mips_cp0sel_names_len, cp0reg, sel);
797 if (n != NULL)
798 (*info->fprintf_func) (info->stream, "%s", n->name);
799 else
800 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
801 break;
802 }
803
804 case 'E':
805 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
806 (*info->fprintf_func) (info->stream, "0x%x", lsb);
807 break;
808
809 case 'F':
810 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
811 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
812 break;
813
814 case 'G':
815 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
816 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
817 break;
818
819 case 't': /* Coprocessor 0 reg name */
820 (*info->fprintf_func) (info->stream, "%s",
821 mips_cp0_names[(l >> OP_SH_RT) &
822 OP_MASK_RT]);
823 break;
824
825 case 'T': /* Coprocessor 0 reg name */
826 {
827 const struct mips_cp0sel_name *n;
828 unsigned int cp0reg, sel;
829
830 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
831 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
832
833 /* CP0 register including 'sel' code for mftc0, to be
834 printed textually if known. If not known, print both
835 CP0 register name and sel numerically since CP0 register
836 with sel 0 may have a name unrelated to register being
837 printed. */
838 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
839 mips_cp0sel_names_len, cp0reg, sel);
840 if (n != NULL)
841 (*info->fprintf_func) (info->stream, "%s", n->name);
842 else
843 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
844 break;
845 }
846
847 default:
848 /* xgettext:c-format */
849 (*info->fprintf_func) (info->stream,
850 _("# internal error, undefined extension sequence (+%c)"),
851 *d);
852 return;
853 }
854 break;
855
856 case '3':
857 (*info->fprintf_func) (info->stream, "0x%lx",
858 (l >> OP_SH_SA3) & OP_MASK_SA3);
859 break;
860
861 case '4':
862 (*info->fprintf_func) (info->stream, "0x%lx",
863 (l >> OP_SH_SA4) & OP_MASK_SA4);
864 break;
865
866 case '5':
867 (*info->fprintf_func) (info->stream, "0x%lx",
868 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
869 break;
870
871 case '6':
872 (*info->fprintf_func) (info->stream, "0x%lx",
873 (l >> OP_SH_RS) & OP_MASK_RS);
874 break;
875
876 case '7':
877 (*info->fprintf_func) (info->stream, "$ac%ld",
878 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
879 break;
880
881 case '8':
882 (*info->fprintf_func) (info->stream, "0x%lx",
883 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
884 break;
885
886 case '9':
887 (*info->fprintf_func) (info->stream, "$ac%ld",
888 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
889 break;
890
891 case '0': /* dsp 6-bit signed immediate in bit 20 */
892 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
893 if (delta & 0x20) /* test sign bit */
894 delta |= ~OP_MASK_DSPSFT;
895 (*info->fprintf_func) (info->stream, "%d", delta);
896 break;
897
898 case ':': /* dsp 7-bit signed immediate in bit 19 */
899 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
900 if (delta & 0x40) /* test sign bit */
901 delta |= ~OP_MASK_DSPSFT_7;
902 (*info->fprintf_func) (info->stream, "%d", delta);
903 break;
904
905 case '\'':
906 (*info->fprintf_func) (info->stream, "0x%lx",
907 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
908 break;
909
910 case '@': /* dsp 10-bit signed immediate in bit 16 */
911 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
912 if (delta & 0x200) /* test sign bit */
913 delta |= ~OP_MASK_IMM10;
914 (*info->fprintf_func) (info->stream, "%d", delta);
915 break;
916
917 case '!':
918 (*info->fprintf_func) (info->stream, "%ld",
919 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
920 break;
921
922 case '$':
923 (*info->fprintf_func) (info->stream, "%ld",
924 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
925 break;
926
927 case '*':
928 (*info->fprintf_func) (info->stream, "$ac%ld",
929 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
930 break;
931
932 case '&':
933 (*info->fprintf_func) (info->stream, "$ac%ld",
934 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
935 break;
936
937 case 'g':
938 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
939 (*info->fprintf_func) (info->stream, "$%ld",
940 (l >> OP_SH_RD) & OP_MASK_RD);
941 break;
942
943 case 's':
944 case 'b':
945 case 'r':
946 case 'v':
947 (*info->fprintf_func) (info->stream, "%s",
948 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
949 break;
950
951 case 't':
952 case 'w':
953 (*info->fprintf_func) (info->stream, "%s",
954 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
955 break;
956
957 case 'i':
958 case 'u':
959 (*info->fprintf_func) (info->stream, "0x%lx",
960 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
961 break;
962
963 case 'j': /* Same as i, but sign-extended. */
964 case 'o':
965 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
966 if (delta & 0x8000)
967 delta |= ~0xffff;
968 (*info->fprintf_func) (info->stream, "%d",
969 delta);
970 break;
971
972 case 'h':
973 (*info->fprintf_func) (info->stream, "0x%x",
974 (unsigned int) ((l >> OP_SH_PREFX)
975 & OP_MASK_PREFX));
976 break;
977
978 case 'k':
979 (*info->fprintf_func) (info->stream, "0x%x",
980 (unsigned int) ((l >> OP_SH_CACHE)
981 & OP_MASK_CACHE));
982 break;
983
984 case 'a':
985 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
986 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
987 /* For gdb disassembler, force odd address on jalx. */
988 if (info->flavour == bfd_target_unknown_flavour
989 && strcmp (opp->name, "jalx") == 0)
990 info->target |= 1;
991 (*info->print_address_func) (info->target, info);
992 break;
993
994 case 'p':
995 /* Sign extend the displacement. */
996 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
997 if (delta & 0x8000)
998 delta |= ~0xffff;
999 info->target = (delta << 2) + pc + INSNLEN;
1000 (*info->print_address_func) (info->target, info);
1001 break;
1002
1003 case 'd':
1004 (*info->fprintf_func) (info->stream, "%s",
1005 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1006 break;
1007
1008 case 'U':
1009 {
1010 /* First check for both rd and rt being equal. */
1011 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1012 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1013 (*info->fprintf_func) (info->stream, "%s",
1014 mips_gpr_names[reg]);
1015 else
1016 {
1017 /* If one is zero use the other. */
1018 if (reg == 0)
1019 (*info->fprintf_func) (info->stream, "%s",
1020 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1021 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1022 (*info->fprintf_func) (info->stream, "%s",
1023 mips_gpr_names[reg]);
1024 else /* Bogus, result depends on processor. */
1025 (*info->fprintf_func) (info->stream, "%s or %s",
1026 mips_gpr_names[reg],
1027 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1028 }
1029 }
1030 break;
1031
1032 case 'z':
1033 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1034 break;
1035
1036 case '<':
1037 (*info->fprintf_func) (info->stream, "0x%lx",
1038 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1039 break;
1040
1041 case 'c':
1042 (*info->fprintf_func) (info->stream, "0x%lx",
1043 (l >> OP_SH_CODE) & OP_MASK_CODE);
1044 break;
1045
1046 case 'q':
1047 (*info->fprintf_func) (info->stream, "0x%lx",
1048 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1049 break;
1050
1051 case 'C':
1052 (*info->fprintf_func) (info->stream, "0x%lx",
1053 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1054 break;
1055
1056 case 'B':
1057 (*info->fprintf_func) (info->stream, "0x%lx",
1058
1059 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1060 break;
1061
1062 case 'J':
1063 (*info->fprintf_func) (info->stream, "0x%lx",
1064 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1065 break;
1066
1067 case 'S':
1068 case 'V':
1069 (*info->fprintf_func) (info->stream, "%s",
1070 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1071 break;
1072
1073 case 'T':
1074 case 'W':
1075 (*info->fprintf_func) (info->stream, "%s",
1076 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1077 break;
1078
1079 case 'D':
1080 (*info->fprintf_func) (info->stream, "%s",
1081 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1082 break;
1083
1084 case 'R':
1085 (*info->fprintf_func) (info->stream, "%s",
1086 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1087 break;
1088
1089 case 'E':
1090 /* Coprocessor register for lwcN instructions, et al.
1091
1092 Note that there is no load/store cp0 instructions, and
1093 that FPU (cp1) instructions disassemble this field using
1094 'T' format. Therefore, until we gain understanding of
1095 cp2 register names, we can simply print the register
1096 numbers. */
1097 (*info->fprintf_func) (info->stream, "$%ld",
1098 (l >> OP_SH_RT) & OP_MASK_RT);
1099 break;
1100
1101 case 'G':
1102 /* Coprocessor register for mtcN instructions, et al. Note
1103 that FPU (cp1) instructions disassemble this field using
1104 'S' format. Therefore, we only need to worry about cp0,
1105 cp2, and cp3. */
1106 op = (l >> OP_SH_OP) & OP_MASK_OP;
1107 if (op == OP_OP_COP0)
1108 (*info->fprintf_func) (info->stream, "%s",
1109 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1110 else
1111 (*info->fprintf_func) (info->stream, "$%ld",
1112 (l >> OP_SH_RD) & OP_MASK_RD);
1113 break;
1114
1115 case 'K':
1116 (*info->fprintf_func) (info->stream, "%s",
1117 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1118 break;
1119
1120 case 'N':
1121 (*info->fprintf_func) (info->stream,
1122 ((opp->pinfo & (FP_D | FP_S)) != 0
1123 ? "$fcc%ld" : "$cc%ld"),
1124 (l >> OP_SH_BCC) & OP_MASK_BCC);
1125 break;
1126
1127 case 'M':
1128 (*info->fprintf_func) (info->stream, "$fcc%ld",
1129 (l >> OP_SH_CCC) & OP_MASK_CCC);
1130 break;
1131
1132 case 'P':
1133 (*info->fprintf_func) (info->stream, "%ld",
1134 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1135 break;
1136
1137 case 'e':
1138 (*info->fprintf_func) (info->stream, "%ld",
1139 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1140 break;
1141
1142 case '%':
1143 (*info->fprintf_func) (info->stream, "%ld",
1144 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1145 break;
1146
1147 case 'H':
1148 (*info->fprintf_func) (info->stream, "%ld",
1149 (l >> OP_SH_SEL) & OP_MASK_SEL);
1150 break;
1151
1152 case 'O':
1153 (*info->fprintf_func) (info->stream, "%ld",
1154 (l >> OP_SH_ALN) & OP_MASK_ALN);
1155 break;
1156
1157 case 'Q':
1158 {
1159 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1160
1161 if ((vsel & 0x10) == 0)
1162 {
1163 int fmt;
1164
1165 vsel &= 0x0f;
1166 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1167 if ((vsel & 1) == 0)
1168 break;
1169 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1170 (l >> OP_SH_FT) & OP_MASK_FT,
1171 vsel >> 1);
1172 }
1173 else if ((vsel & 0x08) == 0)
1174 {
1175 (*info->fprintf_func) (info->stream, "$v%ld",
1176 (l >> OP_SH_FT) & OP_MASK_FT);
1177 }
1178 else
1179 {
1180 (*info->fprintf_func) (info->stream, "0x%lx",
1181 (l >> OP_SH_FT) & OP_MASK_FT);
1182 }
1183 }
1184 break;
1185
1186 case 'X':
1187 (*info->fprintf_func) (info->stream, "$v%ld",
1188 (l >> OP_SH_FD) & OP_MASK_FD);
1189 break;
1190
1191 case 'Y':
1192 (*info->fprintf_func) (info->stream, "$v%ld",
1193 (l >> OP_SH_FS) & OP_MASK_FS);
1194 break;
1195
1196 case 'Z':
1197 (*info->fprintf_func) (info->stream, "$v%ld",
1198 (l >> OP_SH_FT) & OP_MASK_FT);
1199 break;
1200
1201 default:
1202 /* xgettext:c-format */
1203 (*info->fprintf_func) (info->stream,
1204 _("# internal error, undefined modifier(%c)"),
1205 *d);
1206 return;
1207 }
1208 }
1209 }
1210 \f
1211 /* Print the mips instruction at address MEMADDR in debugged memory,
1212 on using INFO. Returns length of the instruction, in bytes, which is
1213 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1214 this is little-endian code. */
1215
1216 static int
1217 print_insn_mips (bfd_vma memaddr,
1218 unsigned long int word,
1219 struct disassemble_info *info)
1220 {
1221 const struct mips_opcode *op;
1222 static bfd_boolean init = 0;
1223 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1224
1225 /* Build a hash table to shorten the search time. */
1226 if (! init)
1227 {
1228 unsigned int i;
1229
1230 for (i = 0; i <= OP_MASK_OP; i++)
1231 {
1232 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1233 {
1234 if (op->pinfo == INSN_MACRO
1235 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1236 continue;
1237 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1238 {
1239 mips_hash[i] = op;
1240 break;
1241 }
1242 }
1243 }
1244
1245 init = 1;
1246 }
1247
1248 info->bytes_per_chunk = INSNLEN;
1249 info->display_endian = info->endian;
1250 info->insn_info_valid = 1;
1251 info->branch_delay_insns = 0;
1252 info->data_size = 0;
1253 info->insn_type = dis_nonbranch;
1254 info->target = 0;
1255 info->target2 = 0;
1256
1257 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1258 if (op != NULL)
1259 {
1260 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1261 {
1262 if (op->pinfo != INSN_MACRO
1263 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1264 && (word & op->mask) == op->match)
1265 {
1266 const char *d;
1267
1268 /* We always allow to disassemble the jalx instruction. */
1269 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1270 && strcmp (op->name, "jalx"))
1271 continue;
1272
1273 /* Figure out instruction type and branch delay information. */
1274 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1275 {
1276 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1277 info->insn_type = dis_jsr;
1278 else
1279 info->insn_type = dis_branch;
1280 info->branch_delay_insns = 1;
1281 }
1282 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1283 | INSN_COND_BRANCH_LIKELY)) != 0)
1284 {
1285 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1286 info->insn_type = dis_condjsr;
1287 else
1288 info->insn_type = dis_condbranch;
1289 info->branch_delay_insns = 1;
1290 }
1291 else if ((op->pinfo & (INSN_STORE_MEMORY
1292 | INSN_LOAD_MEMORY_DELAY)) != 0)
1293 info->insn_type = dis_dref;
1294
1295 (*info->fprintf_func) (info->stream, "%s", op->name);
1296
1297 d = op->args;
1298 if (d != NULL && *d != '\0')
1299 {
1300 (*info->fprintf_func) (info->stream, "\t");
1301 print_insn_args (d, word, memaddr, info, op);
1302 }
1303
1304 return INSNLEN;
1305 }
1306 }
1307 }
1308
1309 /* Handle undefined instructions. */
1310 info->insn_type = dis_noninsn;
1311 (*info->fprintf_func) (info->stream, "0x%lx", word);
1312 return INSNLEN;
1313 }
1314 \f
1315 /* Disassemble an operand for a mips16 instruction. */
1316
1317 static void
1318 print_mips16_insn_arg (char type,
1319 const struct mips_opcode *op,
1320 int l,
1321 bfd_boolean use_extend,
1322 int extend,
1323 bfd_vma memaddr,
1324 struct disassemble_info *info)
1325 {
1326 switch (type)
1327 {
1328 case ',':
1329 case '(':
1330 case ')':
1331 (*info->fprintf_func) (info->stream, "%c", type);
1332 break;
1333
1334 case 'y':
1335 case 'w':
1336 (*info->fprintf_func) (info->stream, "%s",
1337 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1338 & MIPS16OP_MASK_RY)));
1339 break;
1340
1341 case 'x':
1342 case 'v':
1343 (*info->fprintf_func) (info->stream, "%s",
1344 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1345 & MIPS16OP_MASK_RX)));
1346 break;
1347
1348 case 'z':
1349 (*info->fprintf_func) (info->stream, "%s",
1350 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1351 & MIPS16OP_MASK_RZ)));
1352 break;
1353
1354 case 'Z':
1355 (*info->fprintf_func) (info->stream, "%s",
1356 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1357 & MIPS16OP_MASK_MOVE32Z)));
1358 break;
1359
1360 case '0':
1361 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1362 break;
1363
1364 case 'S':
1365 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1366 break;
1367
1368 case 'P':
1369 (*info->fprintf_func) (info->stream, "$pc");
1370 break;
1371
1372 case 'R':
1373 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1374 break;
1375
1376 case 'X':
1377 (*info->fprintf_func) (info->stream, "%s",
1378 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1379 & MIPS16OP_MASK_REGR32)]);
1380 break;
1381
1382 case 'Y':
1383 (*info->fprintf_func) (info->stream, "%s",
1384 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1385 break;
1386
1387 case '<':
1388 case '>':
1389 case '[':
1390 case ']':
1391 case '4':
1392 case '5':
1393 case 'H':
1394 case 'W':
1395 case 'D':
1396 case 'j':
1397 case '6':
1398 case '8':
1399 case 'V':
1400 case 'C':
1401 case 'U':
1402 case 'k':
1403 case 'K':
1404 case 'p':
1405 case 'q':
1406 case 'A':
1407 case 'B':
1408 case 'E':
1409 {
1410 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1411
1412 shift = 0;
1413 signedp = 0;
1414 extbits = 16;
1415 pcrel = 0;
1416 extu = 0;
1417 branch = 0;
1418 switch (type)
1419 {
1420 case '<':
1421 nbits = 3;
1422 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1423 extbits = 5;
1424 extu = 1;
1425 break;
1426 case '>':
1427 nbits = 3;
1428 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1429 extbits = 5;
1430 extu = 1;
1431 break;
1432 case '[':
1433 nbits = 3;
1434 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1435 extbits = 6;
1436 extu = 1;
1437 break;
1438 case ']':
1439 nbits = 3;
1440 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1441 extbits = 6;
1442 extu = 1;
1443 break;
1444 case '4':
1445 nbits = 4;
1446 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1447 signedp = 1;
1448 extbits = 15;
1449 break;
1450 case '5':
1451 nbits = 5;
1452 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1453 info->insn_type = dis_dref;
1454 info->data_size = 1;
1455 break;
1456 case 'H':
1457 nbits = 5;
1458 shift = 1;
1459 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1460 info->insn_type = dis_dref;
1461 info->data_size = 2;
1462 break;
1463 case 'W':
1464 nbits = 5;
1465 shift = 2;
1466 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1467 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1468 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1469 {
1470 info->insn_type = dis_dref;
1471 info->data_size = 4;
1472 }
1473 break;
1474 case 'D':
1475 nbits = 5;
1476 shift = 3;
1477 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1478 info->insn_type = dis_dref;
1479 info->data_size = 8;
1480 break;
1481 case 'j':
1482 nbits = 5;
1483 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1484 signedp = 1;
1485 break;
1486 case '6':
1487 nbits = 6;
1488 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1489 break;
1490 case '8':
1491 nbits = 8;
1492 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1493 break;
1494 case 'V':
1495 nbits = 8;
1496 shift = 2;
1497 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1498 /* FIXME: This might be lw, or it might be addiu to $sp or
1499 $pc. We assume it's load. */
1500 info->insn_type = dis_dref;
1501 info->data_size = 4;
1502 break;
1503 case 'C':
1504 nbits = 8;
1505 shift = 3;
1506 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1507 info->insn_type = dis_dref;
1508 info->data_size = 8;
1509 break;
1510 case 'U':
1511 nbits = 8;
1512 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1513 extu = 1;
1514 break;
1515 case 'k':
1516 nbits = 8;
1517 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1518 signedp = 1;
1519 break;
1520 case 'K':
1521 nbits = 8;
1522 shift = 3;
1523 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1524 signedp = 1;
1525 break;
1526 case 'p':
1527 nbits = 8;
1528 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1529 signedp = 1;
1530 pcrel = 1;
1531 branch = 1;
1532 info->insn_type = dis_condbranch;
1533 break;
1534 case 'q':
1535 nbits = 11;
1536 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1537 signedp = 1;
1538 pcrel = 1;
1539 branch = 1;
1540 info->insn_type = dis_branch;
1541 break;
1542 case 'A':
1543 nbits = 8;
1544 shift = 2;
1545 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1546 pcrel = 1;
1547 /* FIXME: This can be lw or la. We assume it is lw. */
1548 info->insn_type = dis_dref;
1549 info->data_size = 4;
1550 break;
1551 case 'B':
1552 nbits = 5;
1553 shift = 3;
1554 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1555 pcrel = 1;
1556 info->insn_type = dis_dref;
1557 info->data_size = 8;
1558 break;
1559 case 'E':
1560 nbits = 5;
1561 shift = 2;
1562 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1563 pcrel = 1;
1564 break;
1565 default:
1566 abort ();
1567 }
1568
1569 if (! use_extend)
1570 {
1571 if (signedp && immed >= (1 << (nbits - 1)))
1572 immed -= 1 << nbits;
1573 immed <<= shift;
1574 if ((type == '<' || type == '>' || type == '[' || type == ']')
1575 && immed == 0)
1576 immed = 8;
1577 }
1578 else
1579 {
1580 if (extbits == 16)
1581 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1582 else if (extbits == 15)
1583 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1584 else
1585 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1586 immed &= (1 << extbits) - 1;
1587 if (! extu && immed >= (1 << (extbits - 1)))
1588 immed -= 1 << extbits;
1589 }
1590
1591 if (! pcrel)
1592 (*info->fprintf_func) (info->stream, "%d", immed);
1593 else
1594 {
1595 bfd_vma baseaddr;
1596
1597 if (branch)
1598 {
1599 immed *= 2;
1600 baseaddr = memaddr + 2;
1601 }
1602 else if (use_extend)
1603 baseaddr = memaddr - 2;
1604 else
1605 {
1606 int status;
1607 bfd_byte buffer[2];
1608
1609 baseaddr = memaddr;
1610
1611 /* If this instruction is in the delay slot of a jr
1612 instruction, the base address is the address of the
1613 jr instruction. If it is in the delay slot of jalr
1614 instruction, the base address is the address of the
1615 jalr instruction. This test is unreliable: we have
1616 no way of knowing whether the previous word is
1617 instruction or data. */
1618 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1619 info);
1620 if (status == 0
1621 && (((info->endian == BFD_ENDIAN_BIG
1622 ? bfd_getb16 (buffer)
1623 : bfd_getl16 (buffer))
1624 & 0xf800) == 0x1800))
1625 baseaddr = memaddr - 4;
1626 else
1627 {
1628 status = (*info->read_memory_func) (memaddr - 2, buffer,
1629 2, info);
1630 if (status == 0
1631 && (((info->endian == BFD_ENDIAN_BIG
1632 ? bfd_getb16 (buffer)
1633 : bfd_getl16 (buffer))
1634 & 0xf81f) == 0xe800))
1635 baseaddr = memaddr - 2;
1636 }
1637 }
1638 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1639 if (pcrel && branch
1640 && info->flavour == bfd_target_unknown_flavour)
1641 /* For gdb disassembler, maintain odd address. */
1642 info->target |= 1;
1643 (*info->print_address_func) (info->target, info);
1644 }
1645 }
1646 break;
1647
1648 case 'a':
1649 {
1650 int jalx = l & 0x400;
1651
1652 if (! use_extend)
1653 extend = 0;
1654 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1655 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1656 /* For gdb disassembler, maintain odd address. */
1657 l |= 1;
1658 }
1659 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1660 (*info->print_address_func) (info->target, info);
1661 info->insn_type = dis_jsr;
1662 info->branch_delay_insns = 1;
1663 break;
1664
1665 case 'l':
1666 case 'L':
1667 {
1668 int need_comma, amask, smask;
1669
1670 need_comma = 0;
1671
1672 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1673
1674 amask = (l >> 3) & 7;
1675
1676 if (amask > 0 && amask < 5)
1677 {
1678 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1679 if (amask > 1)
1680 (*info->fprintf_func) (info->stream, "-%s",
1681 mips_gpr_names[amask + 3]);
1682 need_comma = 1;
1683 }
1684
1685 smask = (l >> 1) & 3;
1686 if (smask == 3)
1687 {
1688 (*info->fprintf_func) (info->stream, "%s??",
1689 need_comma ? "," : "");
1690 need_comma = 1;
1691 }
1692 else if (smask > 0)
1693 {
1694 (*info->fprintf_func) (info->stream, "%s%s",
1695 need_comma ? "," : "",
1696 mips_gpr_names[16]);
1697 if (smask > 1)
1698 (*info->fprintf_func) (info->stream, "-%s",
1699 mips_gpr_names[smask + 15]);
1700 need_comma = 1;
1701 }
1702
1703 if (l & 1)
1704 {
1705 (*info->fprintf_func) (info->stream, "%s%s",
1706 need_comma ? "," : "",
1707 mips_gpr_names[31]);
1708 need_comma = 1;
1709 }
1710
1711 if (amask == 5 || amask == 6)
1712 {
1713 (*info->fprintf_func) (info->stream, "%s$f0",
1714 need_comma ? "," : "");
1715 if (amask == 6)
1716 (*info->fprintf_func) (info->stream, "-$f1");
1717 }
1718 }
1719 break;
1720
1721 case 'm':
1722 case 'M':
1723 /* MIPS16e save/restore. */
1724 {
1725 int need_comma = 0;
1726 int amask, args, statics;
1727 int nsreg, smask;
1728 int framesz;
1729 int i, j;
1730
1731 l = l & 0x7f;
1732 if (use_extend)
1733 l |= extend << 16;
1734
1735 amask = (l >> 16) & 0xf;
1736 if (amask == MIPS16_ALL_ARGS)
1737 {
1738 args = 4;
1739 statics = 0;
1740 }
1741 else if (amask == MIPS16_ALL_STATICS)
1742 {
1743 args = 0;
1744 statics = 4;
1745 }
1746 else
1747 {
1748 args = amask >> 2;
1749 statics = amask & 3;
1750 }
1751
1752 if (args > 0) {
1753 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1754 if (args > 1)
1755 (*info->fprintf_func) (info->stream, "-%s",
1756 mips_gpr_names[4 + args - 1]);
1757 need_comma = 1;
1758 }
1759
1760 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1761 if (framesz == 0 && !use_extend)
1762 framesz = 128;
1763
1764 (*info->fprintf_func) (info->stream, "%s%d",
1765 need_comma ? "," : "",
1766 framesz);
1767
1768 if (l & 0x40) /* $ra */
1769 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1770
1771 nsreg = (l >> 24) & 0x7;
1772 smask = 0;
1773 if (l & 0x20) /* $s0 */
1774 smask |= 1 << 0;
1775 if (l & 0x10) /* $s1 */
1776 smask |= 1 << 1;
1777 if (nsreg > 0) /* $s2-$s8 */
1778 smask |= ((1 << nsreg) - 1) << 2;
1779
1780 /* Find first set static reg bit. */
1781 for (i = 0; i < 9; i++)
1782 {
1783 if (smask & (1 << i))
1784 {
1785 (*info->fprintf_func) (info->stream, ",%s",
1786 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1787 /* Skip over string of set bits. */
1788 for (j = i; smask & (2 << j); j++)
1789 continue;
1790 if (j > i)
1791 (*info->fprintf_func) (info->stream, "-%s",
1792 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1793 i = j + 1;
1794 }
1795 }
1796
1797 /* Statics $ax - $a3. */
1798 if (statics == 1)
1799 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1800 else if (statics > 0)
1801 (*info->fprintf_func) (info->stream, ",%s-%s",
1802 mips_gpr_names[7 - statics + 1],
1803 mips_gpr_names[7]);
1804 }
1805 break;
1806
1807 default:
1808 /* xgettext:c-format */
1809 (*info->fprintf_func)
1810 (info->stream,
1811 _("# internal disassembler error, unrecognised modifier (%c)"),
1812 type);
1813 abort ();
1814 }
1815 }
1816
1817 /* Disassemble mips16 instructions. */
1818
1819 static int
1820 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1821 {
1822 int status;
1823 bfd_byte buffer[2];
1824 int length;
1825 int insn;
1826 bfd_boolean use_extend;
1827 int extend = 0;
1828 const struct mips_opcode *op, *opend;
1829
1830 info->bytes_per_chunk = 2;
1831 info->display_endian = info->endian;
1832 info->insn_info_valid = 1;
1833 info->branch_delay_insns = 0;
1834 info->data_size = 0;
1835 info->insn_type = dis_nonbranch;
1836 info->target = 0;
1837 info->target2 = 0;
1838
1839 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1840 if (status != 0)
1841 {
1842 (*info->memory_error_func) (status, memaddr, info);
1843 return -1;
1844 }
1845
1846 length = 2;
1847
1848 if (info->endian == BFD_ENDIAN_BIG)
1849 insn = bfd_getb16 (buffer);
1850 else
1851 insn = bfd_getl16 (buffer);
1852
1853 /* Handle the extend opcode specially. */
1854 use_extend = FALSE;
1855 if ((insn & 0xf800) == 0xf000)
1856 {
1857 use_extend = TRUE;
1858 extend = insn & 0x7ff;
1859
1860 memaddr += 2;
1861
1862 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1863 if (status != 0)
1864 {
1865 (*info->fprintf_func) (info->stream, "extend 0x%x",
1866 (unsigned int) extend);
1867 (*info->memory_error_func) (status, memaddr, info);
1868 return -1;
1869 }
1870
1871 if (info->endian == BFD_ENDIAN_BIG)
1872 insn = bfd_getb16 (buffer);
1873 else
1874 insn = bfd_getl16 (buffer);
1875
1876 /* Check for an extend opcode followed by an extend opcode. */
1877 if ((insn & 0xf800) == 0xf000)
1878 {
1879 (*info->fprintf_func) (info->stream, "extend 0x%x",
1880 (unsigned int) extend);
1881 info->insn_type = dis_noninsn;
1882 return length;
1883 }
1884
1885 length += 2;
1886 }
1887
1888 /* FIXME: Should probably use a hash table on the major opcode here. */
1889
1890 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1891 for (op = mips16_opcodes; op < opend; op++)
1892 {
1893 if (op->pinfo != INSN_MACRO
1894 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1895 && (insn & op->mask) == op->match)
1896 {
1897 const char *s;
1898
1899 if (strchr (op->args, 'a') != NULL)
1900 {
1901 if (use_extend)
1902 {
1903 (*info->fprintf_func) (info->stream, "extend 0x%x",
1904 (unsigned int) extend);
1905 info->insn_type = dis_noninsn;
1906 return length - 2;
1907 }
1908
1909 use_extend = FALSE;
1910
1911 memaddr += 2;
1912
1913 status = (*info->read_memory_func) (memaddr, buffer, 2,
1914 info);
1915 if (status == 0)
1916 {
1917 use_extend = TRUE;
1918 if (info->endian == BFD_ENDIAN_BIG)
1919 extend = bfd_getb16 (buffer);
1920 else
1921 extend = bfd_getl16 (buffer);
1922 length += 2;
1923 }
1924 }
1925
1926 (*info->fprintf_func) (info->stream, "%s", op->name);
1927 if (op->args[0] != '\0')
1928 (*info->fprintf_func) (info->stream, "\t");
1929
1930 for (s = op->args; *s != '\0'; s++)
1931 {
1932 if (*s == ','
1933 && s[1] == 'w'
1934 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1935 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1936 {
1937 /* Skip the register and the comma. */
1938 ++s;
1939 continue;
1940 }
1941 if (*s == ','
1942 && s[1] == 'v'
1943 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1944 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1945 {
1946 /* Skip the register and the comma. */
1947 ++s;
1948 continue;
1949 }
1950 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1951 info);
1952 }
1953
1954 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1955 {
1956 info->branch_delay_insns = 1;
1957 if (info->insn_type != dis_jsr)
1958 info->insn_type = dis_branch;
1959 }
1960
1961 return length;
1962 }
1963 }
1964
1965 if (use_extend)
1966 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1967 (*info->fprintf_func) (info->stream, "0x%x", insn);
1968 info->insn_type = dis_noninsn;
1969
1970 return length;
1971 }
1972
1973 /* In an environment where we do not know the symbol type of the
1974 instruction we are forced to assume that the low order bit of the
1975 instructions' address may mark it as a mips16 instruction. If we
1976 are single stepping, or the pc is within the disassembled function,
1977 this works. Otherwise, we need a clue. Sometimes. */
1978
1979 static int
1980 _print_insn_mips (bfd_vma memaddr,
1981 struct disassemble_info *info,
1982 enum bfd_endian endianness)
1983 {
1984 bfd_byte buffer[INSNLEN];
1985 int status;
1986
1987 set_default_mips_dis_options (info);
1988 parse_mips_dis_options (info->disassembler_options);
1989
1990 #if 1
1991 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1992 /* Only a few tools will work this way. */
1993 if (memaddr & 0x01)
1994 return print_insn_mips16 (memaddr, info);
1995 #endif
1996
1997 #if SYMTAB_AVAILABLE
1998 if (info->mach == bfd_mach_mips16
1999 || (info->flavour == bfd_target_elf_flavour
2000 && info->symbols != NULL
2001 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
2002 == STO_MIPS16)))
2003 return print_insn_mips16 (memaddr, info);
2004 #endif
2005
2006 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2007 if (status == 0)
2008 {
2009 unsigned long insn;
2010
2011 if (endianness == BFD_ENDIAN_BIG)
2012 insn = (unsigned long) bfd_getb32 (buffer);
2013 else
2014 insn = (unsigned long) bfd_getl32 (buffer);
2015
2016 return print_insn_mips (memaddr, insn, info);
2017 }
2018 else
2019 {
2020 (*info->memory_error_func) (status, memaddr, info);
2021 return -1;
2022 }
2023 }
2024
2025 int
2026 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2027 {
2028 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2029 }
2030
2031 int
2032 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2033 {
2034 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2035 }
2036 \f
2037 void
2038 print_mips_disassembler_options (FILE *stream)
2039 {
2040 unsigned int i;
2041
2042 fprintf (stream, _("\n\
2043 The following MIPS specific disassembler options are supported for use\n\
2044 with the -M switch (multiple options should be separated by commas):\n"));
2045
2046 fprintf (stream, _("\n\
2047 gpr-names=ABI Print GPR names according to specified ABI.\n\
2048 Default: based on binary being disassembled.\n"));
2049
2050 fprintf (stream, _("\n\
2051 fpr-names=ABI Print FPR names according to specified ABI.\n\
2052 Default: numeric.\n"));
2053
2054 fprintf (stream, _("\n\
2055 cp0-names=ARCH Print CP0 register names according to\n\
2056 specified architecture.\n\
2057 Default: based on binary being disassembled.\n"));
2058
2059 fprintf (stream, _("\n\
2060 hwr-names=ARCH Print HWR names according to specified \n\
2061 architecture.\n\
2062 Default: based on binary being disassembled.\n"));
2063
2064 fprintf (stream, _("\n\
2065 reg-names=ABI Print GPR and FPR names according to\n\
2066 specified ABI.\n"));
2067
2068 fprintf (stream, _("\n\
2069 reg-names=ARCH Print CP0 register and HWR names according to\n\
2070 specified architecture.\n"));
2071
2072 fprintf (stream, _("\n\
2073 For the options above, the following values are supported for \"ABI\":\n\
2074 "));
2075 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2076 fprintf (stream, " %s", mips_abi_choices[i].name);
2077 fprintf (stream, _("\n"));
2078
2079 fprintf (stream, _("\n\
2080 For the options above, The following values are supported for \"ARCH\":\n\
2081 "));
2082 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2083 if (*mips_arch_choices[i].name != '\0')
2084 fprintf (stream, " %s", mips_arch_choices[i].name);
2085 fprintf (stream, _("\n"));
2086
2087 fprintf (stream, _("\n"));
2088 }