1 /* Assemble Matsushita MN10300 instructions.
2 Copyright (C) 1996 Free Software Foundation, Inc.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19 #include "opcode/mn10300.h"
21 /* Formats. Right now we don't use this. We probably will later for
22 the size of the instruction and other random stuff. */
34 /* Operands currently used. This is temporary. */
37 const struct mn10300_operand mn10300_operands
[] = {
41 #define DN0 (UNUSED+1)
42 {2, 0, MN10300_OPERAND_DREG
},
45 {2, 2, MN10300_OPERAND_DREG
},
48 {2, 0, MN10300_OPERAND_DREG
},
51 {2, 2, MN10300_OPERAND_DREG
},
54 {2, 0, MN10300_OPERAND_AREG
},
57 {2, 2, MN10300_OPERAND_AREG
},
60 {2, 0, MN10300_OPERAND_AREG
},
63 {2, 2, MN10300_OPERAND_AREG
},
66 {8, 0, MN10300_OPERAND_PROMOTE
},
68 #define IMM16 (IMM8+1)
69 {16, 0, MN10300_OPERAND_PROMOTE
},
71 #define IMM32 (IMM16+1)
75 {8, 0, MN10300_OPERAND_PROMOTE
},
78 {16, 0, MN10300_OPERAND_PROMOTE
},
84 {8, 0, MN10300_OPERAND_SP
},
87 {0, 0, MN10300_OPERAND_PSW
},
90 {0, 0, MN10300_OPERAND_MDR
},
93 {16, 0, MN10300_OPERAND_PROMOTE
},
95 #define ABS32 (ABS16+1)
99 {2, 0, MN10300_OPERAND_DREG
},
102 {8, 0, MN10300_OPERAND_SIGNED
| MN10300_OPERAND_PROMOTE
},
105 {16, 0, MN10300_OPERAND_SIGNED
| MN10300_OPERAND_PROMOTE
},
107 #define SD8N (SD16+1)
108 {8, 0, MN10300_OPERAND_SIGNED
},
110 #define SIMM8 (SD8N+1)
111 {8, 0, MN10300_OPERAND_SIGNED
| MN10300_OPERAND_PROMOTE
},
113 #define SIMM16 (SIMM8+1)
114 {16, 0, MN10300_OPERAND_SIGNED
| MN10300_OPERAND_PROMOTE
},
116 #define PAREN (SIMM16+1)
117 {0, 0, MN10300_OPERAND_PAREN
},
120 #define MEM(ADDR) PAREN, ADDR, PAREN
121 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
125 The format of the opcode table is:
127 NAME OPCODE MASK { OPERANDS }
129 NAME is the name of the instruction.
130 OPCODE is the instruction opcode.
131 MASK is the opcode mask; this is used to tell the disassembler
132 which bits in the actual opcode must match OPCODE.
133 OPERANDS is the list of operands.
135 The disassembler reads the table in order and prints the first
136 instruction which matches, so this table is sorted to put more
137 specific instructions before more general instructions. It is also
138 sorted by major opcode. */
140 const struct mn10300_opcode mn10300_opcodes
[] = {
141 { "mov", 0x8000, 0xf000, FMT_S1
, {SIMM8
, DN0
}},
142 { "mov", 0x80, 0xf0, FMT_S0
, {DM1
, DN0
}},
143 { "mov", 0xf1e0, 0xfff0, FMT_D0
, {DM1
, AN0
}},
144 { "mov", 0xf1d0, 0xfff0, FMT_D0
, {AM1
, DN0
}},
145 { "mov", 0x9000, 0xf000, FMT_S1
, {IMM8
, AN0
}},
146 { "mov", 0x90, 0xf0, FMT_S0
, {AM1
, AN0
}},
147 { "mov", 0x3c, 0xfc, FMT_S0
, {SP
, AN0
}},
148 { "mov", 0xf2f0, 0xfff3, FMT_D0
, {AM1
, SP
}},
149 { "mov", 0xf2e4, 0xfffc, FMT_D0
, {PSW
, DN0
}},
150 { "mov", 0xf2f3, 0xfff3, FMT_D0
, {DM1
, PSW
}},
151 { "mov", 0xf2e0, 0xfffc, FMT_D0
, {MDR
, DN0
}},
152 { "mov", 0xf2f2, 0xfff3, FMT_D0
, {DM1
, MDR
}},
153 { "mov", 0x70, 0xf0, FMT_S0
, {MEM(AM0
), DN1
}},
154 { "mov", 0xf80000, 0xfff000, FMT_D1
, {MEM2(SD8
, AM0
), DN1
}},
155 { "mov", 0xfa000000, 0xfff00000, FMT_D2
, {MEM2(SD16
, AM0
), DN1
}},
156 { "mov", 0xfc000000, 0xfff00000, FMT_D4
, {MEM2(D32
, AM0
), DN1
}},
157 { "mov", 0x5800, 0xfc00, FMT_S1
, {MEM2(D8
, SP
), DN0
}},
158 { "mov", 0xfab40000, 0xfffc0000, FMT_D2
, {MEM2(D16
, SP
), DN0
}},
159 { "mov", 0xfcb40000, 0xfffc0000, FMT_D4
, {MEM2(D32
, SP
), DN0
}},
160 { "mov", 0xf300, 0xffc0, FMT_D0
, {MEM2(DI
, AM0
), DN0
}},
161 { "mov", 0x300000, 0xfc0000, FMT_S2
, {MEM(ABS16
), DN0
}},
162 { "mov", 0xfca40000, 0xfffc0000, FMT_D4
, {MEM(ABS32
), DN0
}},
163 { "mov", 0xf000, 0xfff0, FMT_D0
, {MEM(AM0
), AN1
}},
164 { "mov", 0xf82000, 0xfff000, FMT_D1
, {MEM2(D8
, AM0
), AN1
}},
165 { "mov", 0xfa200000, 0xfff00000, FMT_D2
, {MEM2(D16
, AM0
), AN1
}},
166 { "mov", 0xfc200000, 0xfff00000, FMT_D4
, {MEM2(D32
, AM0
), AN1
}},
167 { "mov", 0x5c00, 0xfc00, FMT_S1
, {MEM2(D8
, SP
), AN0
}},
168 { "mov", 0xfab00000, 0xfffc0000, FMT_D2
, {MEM2(D16
, SP
), AN0
}},
169 { "mov", 0xfcb00000, 0xfffc0000, FMT_D4
, {MEM2(D32
, SP
), AN0
}},
170 { "mov", 0xf380, 0xffc0, FMT_D0
, {MEM2(DI
, AM0
), AN0
}},
171 { "mov", 0xfaa00000, 0xfffc0000, FMT_D2
, {MEM(ABS16
), AN0
}},
172 { "mov", 0xfca00000, 0xfffc0000, FMT_D4
, {MEM(ABS32
), AN0
}},
173 { "mov", 0xf8f000, 0xfffc00, FMT_D1
, {MEM2(SD8N
, AM0
), SP
}},
174 { "mov", 0x60, 0xf0, FMT_S0
, {DM1
, MEM(AN0
)}},
175 { "mov", 0xf81000, 0xfff000, FMT_D1
, {DM1
, MEM2(SD8
, AN0
)}},
176 { "mov", 0xfa100000, 0xfff00000, FMT_D2
, {DM1
, MEM2(SD16
, AN0
)}},
177 { "mov", 0xfc100000, 0xfff00000, FMT_D4
, {DM1
, MEM2(D32
, AN0
)}},
178 { "mov", 0x4200, 0xf300, FMT_S1
, {DM1
, MEM2(D8
, SP
)}},
179 { "mov", 0xfa910000, 0xfff30000, FMT_D2
, {DM1
, MEM2(D16
, SP
)}},
180 { "mov", 0xfc910000, 0xfff30000, FMT_D4
, {DM1
, MEM2(D32
, SP
)}},
181 { "mov", 0xf340, 0xffc0, FMT_D0
, {DM0
, MEM2(DI
, AN0
)}},
182 { "mov", 0x010000, 0xf30000, FMT_S2
, {DM1
, MEM(ABS16
)}},
183 { "mov", 0xfc810000, 0xfff30000, FMT_D4
, {DM1
, MEM(ABS32
)}},
184 { "mov", 0xf010, 0xfff0, FMT_D0
, {AM1
, MEM(AN0
)}},
185 { "mov", 0xf83000, 0xfff000, FMT_D1
, {AM1
, MEM2(SD8
, AN0
)}},
186 { "mov", 0xfa300000, 0xfff00000, FMT_D2
, {AM1
, MEM2(SD16
, AN0
)}},
187 { "mov", 0xfc300000, 0xfff00000, FMT_D4
, {AM1
, MEM2(D32
, AN0
)}},
188 { "mov", 0x4300, 0xf300, FMT_S1
, {AM1
, MEM2(D8
, SP
)}},
189 { "mov", 0xfa900000, 0xfff30000, FMT_D2
, {AM1
, MEM2(D16
, SP
)}},
190 { "mov", 0xfc900000, 0xfc930000, FMT_D4
, {AM1
, MEM2(D32
, SP
)}},
191 { "mov", 0xf3c0, 0xffc0, FMT_D0
, {AM0
, MEM2(DI
, AN0
)}},
192 { "mov", 0xfa800000, 0xfff30000, FMT_D2
, {AM1
, MEM(ABS16
)}},
193 { "mov", 0xfc800000, 0xfff30000, FMT_D4
, {AM1
, MEM(ABS32
)}},
194 { "mov", 0xf8f400, 0xfffc00, FMT_D1
, {SP
, MEM2(SD8N
, AN0
)}},
195 { "mov", 0x2c0000, 0xfc0000, FMT_S2
, {SIMM16
, DN0
}},
196 { "mov", 0xfcdc0000, 0xfffc0000, FMT_D4
, {IMM32
, DN0
}},
197 { "mov", 0x240000, 0xfc0000, FMT_S2
, {IMM16
, AN0
}},
198 { "mov", 0xfcdc0000, 0xfffc0000, FMT_D4
, {IMM32
, AN0
}},
200 { "movbu", 0xf040, 0xfff0, FMT_D0
, {MEM(AM0
), DN1
}},
201 { "movbu", 0xf84000, 0xfff000, FMT_D1
, {MEM2(SD8
, AM0
), DN1
}},
202 { "movbu", 0xfa400000, 0xfff00000, FMT_D2
, {MEM2(SD16
, AM0
), DN1
}},
203 { "movbu", 0xfc400000, 0xfff00000, FMT_D4
, {MEM2(D32
, AM0
), DN1
}},
204 { "movbu", 0xf8b800, 0xfffc00, FMT_D1
, {MEM2(D8
, SP
), DN0
}},
205 { "movbu", 0xfab80000, 0xfffc0000, FMT_D2
, {MEM2(D16
, SP
), DN0
}},
206 { "movbu", 0xfcb80000, 0xfffc0000, FMT_D4
, {MEM2(D32
, SP
), DN0
}},
207 { "movbu", 0xf400, 0xffc0, FMT_D0
, {MEM2(DI
, AM0
), DN0
}},
208 { "movbu", 0x340000, 0xfc0000, FMT_S2
, {MEM(ABS16
), DN0
}},
209 { "movbu", 0xfca80000, 0xfffc0000, FMT_D4
, {MEM(ABS32
), DN0
}},
210 { "movbu", 0xf050, 0xfff0, FMT_D0
, {DM1
, MEM(AN0
)}},
211 { "movbu", 0xf85000, 0xfff000, FMT_D1
, {DM1
, MEM2(SD8
, AN0
)}},
212 { "movbu", 0xfa500000, 0xfff00000, FMT_D2
, {DM1
, MEM2(SD16
, AN0
)}},
213 { "movbu", 0xfc500000, 0xfff00000, FMT_D4
, {DM1
, MEM2(D32
, AN0
)}},
214 { "movbu", 0xf89200, 0xfff300, FMT_D1
, {DM1
, MEM2(D8
, SP
)}},
215 { "movbu", 0xfa920000, 0xfff30000, FMT_D2
, {DM1
, MEM2(D16
, SP
)}},
216 { "movbu", 0xfc920000, 0xfff30000, FMT_D4
, {DM1
, MEM2(D32
, SP
)}},
217 { "movbu", 0xf440, 0xffc0, FMT_D0
, {DM0
, MEM2(DI
, AN0
)}},
218 { "movbu", 0x020000, 0xf30000, FMT_S2
, {DM1
, MEM(ABS16
)}},
219 { "movbu", 0xfc820000, 0xfff30000, FMT_D4
, {DM1
, MEM(ABS32
)}},
221 { "movhu", 0xf060, 0xfff0, FMT_D0
, {MEM(AM0
), DN1
}},
222 { "movhu", 0xf86000, 0xfff000, FMT_D1
, {MEM2(SD8
, AM0
), DN1
}},
223 { "movhu", 0xfa600000, 0xfff00000, FMT_D2
, {MEM2(SD16
, AM0
), DN1
}},
224 { "movhu", 0xfc600000, 0xfff00000, FMT_D4
, {MEM2(D32
, AM0
), DN1
}},
225 { "movhu", 0xf8bc00, 0xfffc00, FMT_D1
, {MEM2(D8
, SP
), DN0
}},
226 { "movhu", 0xfabc0000, 0xfffc0000, FMT_D2
, {MEM2(D16
, SP
), DN0
}},
227 { "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4
, {MEM2(D32
, SP
), DN0
}},
228 { "movhu", 0xf480, 0xffc0, FMT_D0
, {MEM2(DI
, AM0
), DN0
}},
229 { "movhu", 0xc80000, 0xfc0000, FMT_S2
, {MEM(ABS16
), DN0
}},
230 { "movhu", 0xfcac0000, 0xfffc0000, FMT_D4
, {MEM(ABS32
), DN0
}},
231 { "movhu", 0xf070, 0xfff0, FMT_D0
, {DM1
, MEM(AN0
)}},
232 { "movhu", 0xf87000, 0xfff000, FMT_D1
, {DM1
, MEM2(SD8
, AN0
)}},
233 { "movhu", 0xfa700000, 0xfff00000, FMT_D2
, {DM1
, MEM2(SD16
, AN0
)}},
234 { "movhu", 0xfc700000, 0xfff00000, FMT_D4
, {DM1
, MEM2(D32
, AN0
)}},
235 { "movhu", 0xf89300, 0xfff300, FMT_D1
, {DM1
, MEM2(D8
, SP
)}},
236 { "movhu", 0xfa930000, 0xfff30000, FMT_D2
, {DM1
, MEM2(D16
, SP
)}},
237 { "movhu", 0xfc930000, 0xfff30000, FMT_D4
, {DM1
, MEM2(D32
, SP
)}},
238 { "movhu", 0xf4c0, 0xffc0, FMT_D0
, {DM0
, MEM2(DI
, AN0
)}},
239 { "movhu", 0x030000, 0xf30000, FMT_S2
, {DM1
, MEM(ABS16
)}},
240 { "movhu", 0xfc830000, 0xfff30000, FMT_D4
, {DM1
, MEM(ABS32
)}},
242 { "ext", 0xf2d0, 0xfffc, FMT_D0
, {DN0
}},
243 { "extb", 0x10, 0xfc, FMT_S0
, {DN0
}},
244 { "extbu", 0x14, 0xfc, FMT_S0
, {DN0
}},
245 { "exth", 0x18, 0xfc, FMT_S0
, {DN0
}},
246 { "exthu", 0x1c, 0xfc, FMT_S0
, {DN0
}},
248 { "movm", 0xce00, 0xff00, FMT_S1
, {MEM(SP
), IMM8
}},
249 { "movm", 0xcf00, 0xff00, FMT_S1
, {IMM8
, MEM(SP
)}},
251 { "clr", 0x00, 0xf3, FMT_S0
, {DN1
}},
253 { "add", 0xe0, 0xf0, FMT_S0
, {DM1
, DN0
}},
254 { "add", 0xf160, 0xfff0, FMT_D0
, {DM1
, AN0
}},
255 { "add", 0xf150, 0xfff0, FMT_D0
, {AM1
, DN0
}},
256 { "add", 0xf170, 0xfff0, FMT_D0
, {AM1
, AN0
}},
257 { "add", 0x2800, 0xfc00, FMT_S1
, {SIMM8
, DN0
}},
258 { "add", 0xfac00000, 0xfffc0000, FMT_D2
, {SIMM16
, DN0
}},
259 { "add", 0xfcc00000, 0xfffc0000, FMT_D4
, {IMM32
, DN0
}},
260 { "add", 0x2000, 0xfc00, FMT_S1
, {SIMM8
, AN0
}},
261 { "add", 0xfad00000, 0xfffc0000, FMT_D2
, {SIMM16
, AN0
}},
262 { "add", 0xfcd00000, 0xfffc0000, FMT_D4
, {IMM32
, AN0
}},
263 { "add", 0xf8fe00, 0xffff00, FMT_D1
, {SIMM8
, SP
}},
264 { "add", 0xfafe0000, 0xfffc0000, FMT_D2
, {SIMM16
, SP
}},
265 { "add", 0xfcfe0000, 0xfff0000, FMT_D4
, {IMM32
, SP
}},
266 { "addc", 0xf140, 0xfff0, FMT_D0
, {DM1
, DN0
}},
268 { "sub", 0xf100, 0xfff0, FMT_D0
, {DM1
, DN0
}},
269 { "sub", 0xf120, 0xfff0, FMT_D0
, {DM1
, AN0
}},
270 { "sub", 0xf110, 0xfff0, FMT_D0
, {AM1
, DN0
}},
271 { "sub", 0xf130, 0xfff0, FMT_D0
, {AM1
, AN0
}},
272 { "sub", 0xfcc40000, 0xfffc0000, FMT_D4
, {IMM32
, DN0
}},
273 { "sub", 0xfcd40000, 0xfffc0000, FMT_D4
, {IMM32
, AN0
}},
274 { "subc", 0xf180, 0xfff0, FMT_D0
, {DM1
, DN0
}},
276 { "mul", 0xf240, 0xfff0, FMT_D0
, {DM1
, DN0
}},
277 { "mulu", 0xf250, 0xfff0, FMT_D0
, {DM1
, DN0
}},
279 { "div", 0xf260, 0xfff0, FMT_D0
, {DM1
, DN0
}},
280 { "divu", 0xf270, 0xfff0, FMT_D0
, {DM1
, DN0
}},
282 { "inc", 0x40, 0xf3, FMT_S0
, {DN1
}},
283 { "inc", 0x41, 0xf3, FMT_S0
, {AN1
}},
284 { "inc4", 0x50, 0xfc, FMT_S0
, {AN0
}},
286 { "cmp", 0xa000, 0xf000, FMT_S1
, {SIMM8
, DN0
}},
287 { "cmp", 0xa0, 0xf0, FMT_S0
, {DM1
, DN0
}},
288 { "cmp", 0xf1a0, 0xfff0, FMT_D0
, {DM1
, AN0
}},
289 { "cmp", 0xf190, 0xfff0, FMT_D0
, {AM1
, DN0
}},
290 { "cmp", 0xb000, 0xf000, FMT_S1
, {IMM8
, AN0
}},
291 { "cmp", 0xb0, 0xf0, FMT_S0
, {AM1
, AN0
}},
292 { "cmp", 0xfac80000, 0xfffc0000, FMT_D2
, {SIMM16
, DN0
}},
293 { "cmp", 0xfcc80000, 0xfffc0000, FMT_D4
, {IMM32
, DN0
}},
294 { "cmp", 0xfad80000, 0xfffc0000, FMT_D2
, {IMM16
, AN0
}},
295 { "cmp", 0xfcd80000, 0xfffc0000, FMT_D4
, {IMM32
, AN0
}},
297 { "and", 0xf200, 0xfff0, FMT_D0
, {DM1
, DN0
}},
298 { "and", 0xf8e000, 0xfffc00, FMT_D1
, {IMM8
, DN0
}},
299 { "and", 0xfae00000, 0xfffc0000, FMT_D2
, {IMM16
, DN0
}},
300 { "and", 0xfce00000, 0xfffc0000, FMT_D4
, {IMM32
, DN0
}},
301 { "and", 0xfafc0000, 0xfffc0000, FMT_D2
, {IMM16
, PSW
}},
302 { "or", 0xf210, 0xfff0, FMT_D0
, {DM1
, DN0
}},
303 { "or", 0xf8e400, 0xfffc00, FMT_D1
, {IMM8
, DN0
}},
304 { "or", 0xfae40000, 0xfffc0000, FMT_D2
, {IMM16
, DN0
}},
305 { "or", 0xfce40000, 0xfffc0000, FMT_D4
, {IMM32
, DN0
}},
306 { "or", 0xfafd0000, 0xfffc0000, FMT_D2
, {IMM16
, PSW
}},
307 { "xor", 0xf220, 0xfff0, FMT_D0
, {DM1
, DN0
}},
308 { "xor", 0xfae80000, 0xfffc0000, FMT_D2
, {IMM16
, DN0
}},
309 { "xor", 0xfce80000, 0xfffc0000, FMT_D4
, {IMM32
, DN0
}},
310 { "not", 0xf230, 0xfffc, FMT_D0
, {DN0
}},
312 { "btst", 0xf8ec00, 0xfffc00, FMT_D1
, {IMM8
, DN0
}},
313 { "btst", 0xfaec0000, 0xfffc0000, FMT_D2
, {IMM16
, DN0
}},
314 { "btst", 0xfcec0000, 0xfffc0000, FMT_D4
, {IMM32
, DN0
}},
315 { "btst", 0xfe020000, 0xffff0000, FMT_D5
, {IMM8
, MEM(ABS32
)}},
316 { "btst", 0xfaf80000, 0xfffc0000, FMT_D2
, {IMM8
, MEM2(SD8N
,AN0
)}},
317 { "bset", 0xf080, 0xfff0, FMT_D0
, {DM1
, MEM(AN0
)}},
318 { "bset", 0xfe000000, 0xffff0000, FMT_D5
, {IMM8
, MEM(ABS32
)}},
319 { "bset", 0xfaf00000, 0xfffc0000, FMT_D2
, {IMM8
, MEM2(SD8N
,AN0
)}},
320 { "bclr", 0xf090, 0xfff0, FMT_D0
, {DM1
, MEM(AN0
)}},
321 { "bclr", 0xfe010000, 0xffff0000, FMT_D5
, {IMM8
, MEM(ABS32
)}},
322 { "bclr", 0xfaf40000, 0xfffc0000, FMT_D2
, {IMM8
, MEM2(SD8N
,AN0
)}},
324 { "asr", 0xf2b0, 0xfff0, FMT_D0
, {DM1
, DN1
}},
325 { "asr", 0xf8c800, 0xfffc00, FMT_D1
, {IMM8
, DN0
}},
326 { "lsr", 0xf2a0, 0xfff0, FMT_D0
, {DM1
, DN1
}},
327 { "lsr", 0xf8c400, 0xfffc00, FMT_D1
, {IMM8
, DN0
}},
328 { "asl", 0xf290, 0xfff0, FMT_D0
, {DM1
, DN1
}},
329 { "asl", 0xf8c000, 0xfffc00, FMT_D1
, {IMM8
, DN0
}},
330 { "asl2", 0x54, 0xfc, FMT_S0
, {DN0
}},
331 { "ror", 0xf284, 0xfffc, FMT_D0
, {DN0
}},
332 { "rol", 0xf280, 0xfffc, FMT_D0
, {DN0
}},
334 { "beq", 0xc800, 0xff00, FMT_S1
, {SD8N
}},
335 { "bne", 0xc900, 0xff00, FMT_S1
, {SD8N
}},
336 { "bgt", 0xc100, 0xff00, FMT_S1
, {SD8N
}},
337 { "bge", 0xc200, 0xff00, FMT_S1
, {SD8N
}},
338 { "ble", 0xc300, 0xff00, FMT_S1
, {SD8N
}},
339 { "blt", 0xc000, 0xff00, FMT_S1
, {SD8N
}},
340 { "bhi", 0xc500, 0xff00, FMT_S1
, {SD8N
}},
341 { "bcc", 0xc600, 0xff00, FMT_S1
, {SD8N
}},
342 { "bls", 0xc700, 0xff00, FMT_S1
, {SD8N
}},
343 { "bcs", 0xc400, 0xff00, FMT_S1
, {SD8N
}},
344 { "bvc", 0xf8e800, 0xffff00, FMT_D1
, {SD8N
}},
345 { "bvs", 0xf8e900, 0xffff00, FMT_D1
, {SD8N
}},
346 { "bnc", 0xf8ea00, 0xffff00, FMT_D1
, {SD8N
}},
347 { "bns", 0xf8eb00, 0xffff00, FMT_D1
, {SD8N
}},
348 { "bra", 0xca00, 0xff00, FMT_S1
, {SD8N
}},
350 { "leq", 0xd8, 0xff, FMT_S0
, {UNUSED
}},
351 { "lne", 0xd9, 0xff, FMT_S0
, {UNUSED
}},
352 { "lgt", 0xd1, 0xff, FMT_S0
, {UNUSED
}},
353 { "lge", 0xd2, 0xff, FMT_S0
, {UNUSED
}},
354 { "lle", 0xd3, 0xff, FMT_S0
, {UNUSED
}},
355 { "llt", 0xd0, 0xff, FMT_S0
, {UNUSED
}},
356 { "lhi", 0xd5, 0xff, FMT_S0
, {UNUSED
}},
357 { "lcc", 0xd6, 0xff, FMT_S0
, {UNUSED
}},
358 { "lls", 0xd7, 0xff, FMT_S0
, {UNUSED
}},
359 { "lcs", 0xd4, 0xff, FMT_S0
, {UNUSED
}},
360 { "lra", 0xda, 0xff, FMT_S0
, {UNUSED
}},
361 { "lcc", 0xd6, 0xff, FMT_S0
, {UNUSED
}},
362 { "setlb", 0xdb, 0xff, FMT_S0
, {UNUSED
}},
364 { "jmp", 0xf0f4, 0xfffc, FMT_D0
, {AN0
}},
365 { "jmp", 0xcc0000, 0xff0000, FMT_S2
, {D16
}},
366 { "jmp", 0xdc0000, 0xff0000, FMT_S4
, {D32
}},
367 { "call", 0xcd000000, 0xff000000, FMT_S4
, {D16
,IMM8
,IMM8
}},
368 { "call", 0xdd000000, 0xff000000, FMT_S6
, {D32
,IMM8
,IMM8
}},
369 { "calls", 0xf0f0, 0xfffc, FMT_D0
, {AN0
}},
370 { "calls", 0xfaff0000, 0xffff0000, FMT_D2
, {D16
}},
371 { "calls", 0xfcff0000, 0xffff0000, FMT_D4
, {D32
}},
373 { "ret", 0xdf0000, 0xff00000, FMT_S2
, {IMM8
, IMM8
}},
374 { "retf", 0xde0000, 0xff00000, FMT_S2
, {IMM8
, IMM8
}},
375 { "rets", 0xf0fc, 0xffff, FMT_D0
, {UNUSED
}},
376 { "rti", 0xf0fd, 0xffff, FMT_D0
, {UNUSED
}},
377 { "trap", 0xf0fe, 0xffff, FMT_D0
, {UNUSED
}},
378 { "rtm", 0xf0ff, 0xffff, FMT_D0
, {UNUSED
}},
379 { "nop", 0xcb, 0xff, FMT_S0
, {UNUSED
}},
380 /* { "udf", 0, 0, {0}}, */
382 { "putx", 0xf500, 0xfff0, FMT_D0
, {DM0
}},
383 { "getx", 0xf6f0, 0xfff0, FMT_D0
, {DN0
}},
384 { "mulq", 0xf600, 0xfff0, FMT_D0
, {DM1
, DN0
}},
385 { "mulq", 0xf90000, 0xfffc00, FMT_D1
, {SIMM8
, DN0
}},
386 { "mulq", 0xfb000000, 0xfffc0000, FMT_D2
, {SIMM16
, DN0
}},
387 { "mulq", 0xfd000000, 0xfffc0000, FMT_D4
, {IMM32
, DN0
}},
388 { "mulqu", 0xf610, 0xfff0, FMT_D0
, {DM1
, DN0
}},
389 { "mulqu", 0xf90400, 0xfffc00, FMT_D1
, {SIMM8
, DN0
}},
390 { "mulqu", 0xfb040000, 0xfffc0000, FMT_D2
, {SIMM16
, DN0
}},
391 { "mulqu", 0xfd040000, 0xfffc0000, FMT_D4
, {IMM32
, DN0
}},
392 { "sat16", 0xf640, 0xfff0, FMT_D0
, {DM1
, DN0
}},
393 { "sat24", 0xf650, 0xfff0, FMT_D0
, {DM1
, DN0
}},
394 { "bsch", 0xf670, 0xfff0, FMT_D0
, {DM1
, DN0
}},
399 const int mn10300_num_opcodes
=
400 sizeof (mn10300_opcodes
) / sizeof (mn10300_opcodes
[0]);