1 /* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
28 #include "opcode/ppc.h"
30 /* This file provides several disassembler functions, all of which use
31 the disassembler interface defined in dis-asm.h. Several functions
32 are provided because this file handles disassembly for the PowerPC
33 in both big and little endian mode and also for the POWER (RS/6000)
35 static int print_insn_powerpc (bfd_vma
, struct disassemble_info
*, int,
40 /* Stash the result of parsing disassembler_options here. */
44 #define POWERPC_DIALECT(INFO) \
45 (((struct dis_private *) ((INFO)->private_data))->dialect)
53 struct ppc_mopt ppc_opts
[] = {
54 { "403", (PPC_OPCODE_PPC
| PPC_OPCODE_403
),
56 { "405", (PPC_OPCODE_PPC
| PPC_OPCODE_403
| PPC_OPCODE_405
),
58 { "440", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
59 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
61 { "464", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_440
62 | PPC_OPCODE_ISEL
| PPC_OPCODE_RFMCI
),
64 { "476", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_440
65 | PPC_OPCODE_476
| PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
),
67 { "601", (PPC_OPCODE_PPC
| PPC_OPCODE_601
),
69 { "603", (PPC_OPCODE_PPC
),
71 { "604", (PPC_OPCODE_PPC
),
73 { "620", (PPC_OPCODE_PPC
| PPC_OPCODE_64
),
75 { "7400", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
77 { "7410", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
79 { "7450", (PPC_OPCODE_PPC
| PPC_OPCODE_7450
| PPC_OPCODE_ALTIVEC
),
81 { "7455", (PPC_OPCODE_PPC
| PPC_OPCODE_ALTIVEC
),
83 { "750cl", (PPC_OPCODE_PPC
| PPC_OPCODE_750
| PPC_OPCODE_PPCPS
)
85 { "821", (PPC_OPCODE_PPC
| PPC_OPCODE_860
),
87 { "850", (PPC_OPCODE_PPC
| PPC_OPCODE_860
),
89 { "860", (PPC_OPCODE_PPC
| PPC_OPCODE_860
),
91 { "a2", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_POWER4
92 | PPC_OPCODE_POWER5
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_64
95 { "altivec", (PPC_OPCODE_PPC
),
96 PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
},
99 { "booke", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
),
101 { "booke32", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
),
103 { "cell", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
104 | PPC_OPCODE_CELL
| PPC_OPCODE_ALTIVEC
),
106 { "com", (PPC_OPCODE_COMMON
),
108 { "e300", (PPC_OPCODE_PPC
| PPC_OPCODE_E300
),
110 { "e500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
111 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
112 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
115 { "e500mc", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
116 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
117 | PPC_OPCODE_E500MC
),
119 { "e500mc64", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
120 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
121 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER5
122 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
124 { "e5500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
125 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
126 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
127 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
128 | PPC_OPCODE_POWER7
),
130 { "e6500", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_ISEL
131 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
132 | PPC_OPCODE_E500MC
| PPC_OPCODE_64
| PPC_OPCODE_ALTIVEC
133 | PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_E6500
| PPC_OPCODE_POWER4
134 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7
),
136 { "e500x2", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_SPE
137 | PPC_OPCODE_ISEL
| PPC_OPCODE_EFS
| PPC_OPCODE_BRLOCK
138 | PPC_OPCODE_PMR
| PPC_OPCODE_CACHELCK
| PPC_OPCODE_RFMCI
141 { "efs", (PPC_OPCODE_PPC
| PPC_OPCODE_EFS
),
143 { "power4", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
),
145 { "power5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
146 | PPC_OPCODE_POWER5
),
148 { "power6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
149 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
151 { "power7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
152 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
153 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
155 { "power8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
156 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
157 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_HTM
158 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_VSX
),
160 { "power9", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
161 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
162 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
163 | PPC_OPCODE_HTM
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
164 | PPC_OPCODE_VSX
| PPC_OPCODE_VSX3
),
166 { "ppc", (PPC_OPCODE_PPC
),
168 { "ppc32", (PPC_OPCODE_PPC
),
170 { "ppc64", (PPC_OPCODE_PPC
| PPC_OPCODE_64
),
172 { "ppc64bridge", (PPC_OPCODE_PPC
| PPC_OPCODE_64_BRIDGE
),
174 { "ppcps", (PPC_OPCODE_PPC
| PPC_OPCODE_PPCPS
),
176 { "pwr", (PPC_OPCODE_POWER
),
178 { "pwr2", (PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
),
180 { "pwr4", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
),
182 { "pwr5", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
183 | PPC_OPCODE_POWER5
),
185 { "pwr5x", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
186 | PPC_OPCODE_POWER5
),
188 { "pwr6", (PPC_OPCODE_PPC
| PPC_OPCODE_64
| PPC_OPCODE_POWER4
189 | PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC
),
191 { "pwr7", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
192 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
193 | PPC_OPCODE_POWER7
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_VSX
),
195 { "pwr8", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
196 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
197 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_HTM
198 | PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
| PPC_OPCODE_VSX
),
200 { "pwr9", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_64
201 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5
| PPC_OPCODE_POWER6
202 | PPC_OPCODE_POWER7
| PPC_OPCODE_POWER8
| PPC_OPCODE_POWER9
203 | PPC_OPCODE_HTM
| PPC_OPCODE_ALTIVEC
| PPC_OPCODE_ALTIVEC2
204 | PPC_OPCODE_VSX
| PPC_OPCODE_VSX3
),
206 { "pwrx", (PPC_OPCODE_POWER
| PPC_OPCODE_POWER2
),
208 { "spe", (PPC_OPCODE_PPC
| PPC_OPCODE_EFS
),
210 { "titan", (PPC_OPCODE_PPC
| PPC_OPCODE_BOOKE
| PPC_OPCODE_PMR
211 | PPC_OPCODE_RFMCI
| PPC_OPCODE_TITAN
),
213 { "vle", (PPC_OPCODE_PPC
| PPC_OPCODE_ISEL
| PPC_OPCODE_VLE
),
215 { "vsx", (PPC_OPCODE_PPC
),
216 PPC_OPCODE_VSX
| PPC_OPCODE_VSX3
},
217 { "htm", (PPC_OPCODE_PPC
),
221 /* Switch between Booke and VLE dialects for interlinked dumps. */
223 get_powerpc_dialect (struct disassemble_info
*info
)
225 ppc_cpu_t dialect
= 0;
227 dialect
= POWERPC_DIALECT (info
);
229 /* Disassemble according to the section headers flags for VLE-mode. */
230 if (dialect
& PPC_OPCODE_VLE
231 && info
->section
->owner
!= NULL
232 && bfd_get_flavour (info
->section
->owner
) == bfd_target_elf_flavour
233 && elf_object_id (info
->section
->owner
) == PPC32_ELF_DATA
234 && (elf_section_flags (info
->section
) & SHF_PPC_VLE
) != 0)
237 return dialect
& ~ PPC_OPCODE_VLE
;
240 /* Handle -m and -M options that set cpu type, and .machine arg. */
243 ppc_parse_cpu (ppc_cpu_t ppc_cpu
, ppc_cpu_t
*sticky
, const char *arg
)
247 for (i
= 0; i
< sizeof (ppc_opts
) / sizeof (ppc_opts
[0]); i
++)
248 if (strcmp (ppc_opts
[i
].opt
, arg
) == 0)
250 if (ppc_opts
[i
].sticky
)
252 *sticky
|= ppc_opts
[i
].sticky
;
253 if ((ppc_cpu
& ~*sticky
) != 0)
256 ppc_cpu
= ppc_opts
[i
].cpu
;
259 if (i
>= sizeof (ppc_opts
) / sizeof (ppc_opts
[0]))
266 /* Determine which set of machines to disassemble for. */
269 powerpc_init_dialect (struct disassemble_info
*info
)
271 ppc_cpu_t dialect
= 0;
272 ppc_cpu_t sticky
= 0;
274 struct dis_private
*priv
= calloc (sizeof (*priv
), 1);
281 case bfd_mach_ppc_403
:
282 case bfd_mach_ppc_403gc
:
283 dialect
= ppc_parse_cpu (dialect
, &sticky
, "403");
285 case bfd_mach_ppc_405
:
286 dialect
= ppc_parse_cpu (dialect
, &sticky
, "405");
288 case bfd_mach_ppc_601
:
289 dialect
= ppc_parse_cpu (dialect
, &sticky
, "601");
291 case bfd_mach_ppc_a35
:
292 case bfd_mach_ppc_rs64ii
:
293 case bfd_mach_ppc_rs64iii
:
294 dialect
= ppc_parse_cpu (dialect
, &sticky
, "pwr2") | PPC_OPCODE_64
;
296 case bfd_mach_ppc_e500
:
297 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500");
299 case bfd_mach_ppc_e500mc
:
300 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500mc");
302 case bfd_mach_ppc_e500mc64
:
303 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e500mc64");
305 case bfd_mach_ppc_e5500
:
306 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e5500");
308 case bfd_mach_ppc_e6500
:
309 dialect
= ppc_parse_cpu (dialect
, &sticky
, "e6500");
311 case bfd_mach_ppc_titan
:
312 dialect
= ppc_parse_cpu (dialect
, &sticky
, "titan");
314 case bfd_mach_ppc_vle
:
315 dialect
= ppc_parse_cpu (dialect
, &sticky
, "vle");
318 dialect
= ppc_parse_cpu (dialect
, &sticky
, "power9") | PPC_OPCODE_ANY
;
321 arg
= info
->disassembler_options
;
324 ppc_cpu_t new_cpu
= 0;
325 char *end
= strchr (arg
, ',');
330 if ((new_cpu
= ppc_parse_cpu (dialect
, &sticky
, arg
)) != 0)
332 else if (strcmp (arg
, "32") == 0)
333 dialect
&= ~(ppc_cpu_t
) PPC_OPCODE_64
;
334 else if (strcmp (arg
, "64") == 0)
335 dialect
|= PPC_OPCODE_64
;
337 fprintf (stderr
, _("warning: ignoring unknown -M%s option\n"), arg
);
344 info
->private_data
= priv
;
345 POWERPC_DIALECT(info
) = dialect
;
348 #define PPC_OPCD_SEGS 64
349 static unsigned short powerpc_opcd_indices
[PPC_OPCD_SEGS
+1];
350 #define VLE_OPCD_SEGS 32
351 static unsigned short vle_opcd_indices
[VLE_OPCD_SEGS
+1];
353 /* Calculate opcode table indices to speed up disassembly,
357 disassemble_init_powerpc (struct disassemble_info
*info
)
362 if (powerpc_opcd_indices
[PPC_OPCD_SEGS
] == 0)
365 i
= powerpc_num_opcodes
;
368 unsigned op
= PPC_OP (powerpc_opcodes
[i
].opcode
);
370 powerpc_opcd_indices
[op
] = i
;
373 last
= powerpc_num_opcodes
;
374 for (i
= PPC_OPCD_SEGS
; i
> 0; --i
)
376 if (powerpc_opcd_indices
[i
] == 0)
377 powerpc_opcd_indices
[i
] = last
;
378 last
= powerpc_opcd_indices
[i
];
384 unsigned op
= VLE_OP (vle_opcodes
[i
].opcode
, vle_opcodes
[i
].mask
);
385 unsigned seg
= VLE_OP_TO_SEG (op
);
387 vle_opcd_indices
[seg
] = i
;
390 last
= vle_num_opcodes
;
391 for (i
= VLE_OPCD_SEGS
; i
> 0; --i
)
393 if (vle_opcd_indices
[i
] == 0)
394 vle_opcd_indices
[i
] = last
;
395 last
= vle_opcd_indices
[i
];
399 if (info
->arch
== bfd_arch_powerpc
)
400 powerpc_init_dialect (info
);
403 /* Print a big endian PowerPC instruction. */
406 print_insn_big_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
408 return print_insn_powerpc (memaddr
, info
, 1, get_powerpc_dialect (info
));
411 /* Print a little endian PowerPC instruction. */
414 print_insn_little_powerpc (bfd_vma memaddr
, struct disassemble_info
*info
)
416 return print_insn_powerpc (memaddr
, info
, 0, get_powerpc_dialect (info
));
419 /* Print a POWER (RS/6000) instruction. */
422 print_insn_rs6000 (bfd_vma memaddr
, struct disassemble_info
*info
)
424 return print_insn_powerpc (memaddr
, info
, 1, PPC_OPCODE_POWER
);
427 /* Extract the operand value from the PowerPC or POWER instruction. */
430 operand_value_powerpc (const struct powerpc_operand
*operand
,
431 unsigned long insn
, ppc_cpu_t dialect
)
435 /* Extract the value from the instruction. */
436 if (operand
->extract
)
437 value
= (*operand
->extract
) (insn
, dialect
, &invalid
);
440 if (operand
->shift
>= 0)
441 value
= (insn
>> operand
->shift
) & operand
->bitm
;
443 value
= (insn
<< -operand
->shift
) & operand
->bitm
;
444 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
446 /* BITM is always some number of zeros followed by some
447 number of ones, followed by some number of zeros. */
448 unsigned long top
= operand
->bitm
;
449 /* top & -top gives the rightmost 1 bit, so this
450 fills in any trailing zeros. */
451 top
|= (top
& -top
) - 1;
453 value
= (value
^ top
) - top
;
460 /* Determine whether the optional operand(s) should be printed. */
463 skip_optional_operands (const unsigned char *opindex
,
464 unsigned long insn
, ppc_cpu_t dialect
)
466 const struct powerpc_operand
*operand
;
468 for (; *opindex
!= 0; opindex
++)
470 operand
= &powerpc_operands
[*opindex
];
471 if ((operand
->flags
& PPC_OPERAND_NEXT
) != 0
472 || ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0
473 && operand_value_powerpc (operand
, insn
, dialect
) !=
474 ppc_optional_operand_value (operand
)))
481 /* Find a match for INSN in the opcode table, given machine DIALECT.
482 A DIALECT of -1 is special, matching all machine opcode variations. */
484 static const struct powerpc_opcode
*
485 lookup_powerpc (unsigned long insn
, ppc_cpu_t dialect
)
487 const struct powerpc_opcode
*opcode
;
488 const struct powerpc_opcode
*opcode_end
;
491 /* Get the major opcode of the instruction. */
494 /* Find the first match in the opcode table for this major opcode. */
495 opcode_end
= powerpc_opcodes
+ powerpc_opcd_indices
[op
+ 1];
496 for (opcode
= powerpc_opcodes
+ powerpc_opcd_indices
[op
];
500 const unsigned char *opindex
;
501 const struct powerpc_operand
*operand
;
504 if ((insn
& opcode
->mask
) != opcode
->opcode
505 || (dialect
!= (ppc_cpu_t
) -1
506 && ((opcode
->flags
& dialect
) == 0
507 || (opcode
->deprecated
& dialect
) != 0)))
510 /* Check validity of operands. */
512 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
514 operand
= powerpc_operands
+ *opindex
;
515 if (operand
->extract
)
516 (*operand
->extract
) (insn
, dialect
, &invalid
);
527 /* Find a match for INSN in the VLE opcode table. */
529 static const struct powerpc_opcode
*
530 lookup_vle (unsigned long insn
)
532 const struct powerpc_opcode
*opcode
;
533 const struct powerpc_opcode
*opcode_end
;
537 if (op
>= 0x20 && op
<= 0x37)
539 /* This insn has a 4-bit opcode. */
542 seg
= VLE_OP_TO_SEG (op
);
544 /* Find the first match in the opcode table for this major opcode. */
545 opcode_end
= vle_opcodes
+ vle_opcd_indices
[seg
+ 1];
546 for (opcode
= vle_opcodes
+ vle_opcd_indices
[seg
];
550 unsigned long table_opcd
= opcode
->opcode
;
551 unsigned long table_mask
= opcode
->mask
;
552 bfd_boolean table_op_is_short
= PPC_OP_SE_VLE(table_mask
);
554 const unsigned char *opindex
;
555 const struct powerpc_operand
*operand
;
559 if (table_op_is_short
)
561 if ((insn2
& table_mask
) != table_opcd
)
564 /* Check validity of operands. */
566 for (opindex
= opcode
->operands
; *opindex
!= 0; ++opindex
)
568 operand
= powerpc_operands
+ *opindex
;
569 if (operand
->extract
)
570 (*operand
->extract
) (insn
, (ppc_cpu_t
)0, &invalid
);
581 /* Print a PowerPC or POWER instruction. */
584 print_insn_powerpc (bfd_vma memaddr
,
585 struct disassemble_info
*info
,
592 const struct powerpc_opcode
*opcode
;
593 bfd_boolean insn_is_short
;
595 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 4, info
);
598 /* The final instruction may be a 2-byte VLE insn. */
599 if ((dialect
& PPC_OPCODE_VLE
) != 0)
601 /* Clear buffer so unused bytes will not have garbage in them. */
602 buffer
[0] = buffer
[1] = buffer
[2] = buffer
[3] = 0;
603 status
= (*info
->read_memory_func
) (memaddr
, buffer
, 2, info
);
606 (*info
->memory_error_func
) (status
, memaddr
, info
);
612 (*info
->memory_error_func
) (status
, memaddr
, info
);
618 insn
= bfd_getb32 (buffer
);
620 insn
= bfd_getl32 (buffer
);
622 /* Get the major opcode of the insn. */
624 insn_is_short
= FALSE
;
625 if ((dialect
& PPC_OPCODE_VLE
) != 0)
627 opcode
= lookup_vle (insn
);
629 insn_is_short
= PPC_OP_SE_VLE(opcode
->mask
);
632 opcode
= lookup_powerpc (insn
, dialect
);
633 if (opcode
== NULL
&& (dialect
& PPC_OPCODE_ANY
) != 0)
634 opcode
= lookup_powerpc (insn
, (ppc_cpu_t
) -1);
638 const unsigned char *opindex
;
639 const struct powerpc_operand
*operand
;
644 if (opcode
->operands
[0] != 0)
645 (*info
->fprintf_func
) (info
->stream
, "%-7s ", opcode
->name
);
647 (*info
->fprintf_func
) (info
->stream
, "%s", opcode
->name
);
650 /* The operands will be fetched out of the 16-bit instruction. */
653 /* Now extract and print the operands. */
657 for (opindex
= opcode
->operands
; *opindex
!= 0; opindex
++)
661 operand
= powerpc_operands
+ *opindex
;
663 /* Operands that are marked FAKE are simply ignored. We
664 already made sure that the extract function considered
665 the instruction to be valid. */
666 if ((operand
->flags
& PPC_OPERAND_FAKE
) != 0)
669 /* If all of the optional operands have the value zero,
670 then don't print any of them. */
671 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0)
673 if (skip_optional
< 0)
674 skip_optional
= skip_optional_operands (opindex
, insn
,
680 value
= operand_value_powerpc (operand
, insn
, dialect
);
684 (*info
->fprintf_func
) (info
->stream
, ",");
688 /* Print the operand as directed by the flags. */
689 if ((operand
->flags
& PPC_OPERAND_GPR
) != 0
690 || ((operand
->flags
& PPC_OPERAND_GPR_0
) != 0 && value
!= 0))
691 (*info
->fprintf_func
) (info
->stream
, "r%ld", value
);
692 else if ((operand
->flags
& PPC_OPERAND_FPR
) != 0)
693 (*info
->fprintf_func
) (info
->stream
, "f%ld", value
);
694 else if ((operand
->flags
& PPC_OPERAND_VR
) != 0)
695 (*info
->fprintf_func
) (info
->stream
, "v%ld", value
);
696 else if ((operand
->flags
& PPC_OPERAND_VSR
) != 0)
697 (*info
->fprintf_func
) (info
->stream
, "vs%ld", value
);
698 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0)
699 (*info
->print_address_func
) (memaddr
+ value
, info
);
700 else if ((operand
->flags
& PPC_OPERAND_ABSOLUTE
) != 0)
701 (*info
->print_address_func
) ((bfd_vma
) value
& 0xffffffff, info
);
702 else if ((operand
->flags
& PPC_OPERAND_FSL
) != 0)
703 (*info
->fprintf_func
) (info
->stream
, "fsl%ld", value
);
704 else if ((operand
->flags
& PPC_OPERAND_FCR
) != 0)
705 (*info
->fprintf_func
) (info
->stream
, "fcr%ld", value
);
706 else if ((operand
->flags
& PPC_OPERAND_UDI
) != 0)
707 (*info
->fprintf_func
) (info
->stream
, "%ld", value
);
708 else if ((operand
->flags
& PPC_OPERAND_CR_REG
) != 0
709 && (((dialect
& PPC_OPCODE_PPC
) != 0)
710 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
711 (*info
->fprintf_func
) (info
->stream
, "cr%ld", value
);
712 else if (((operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
713 && (((dialect
& PPC_OPCODE_PPC
) != 0)
714 || ((dialect
& PPC_OPCODE_VLE
) != 0)))
716 static const char *cbnames
[4] = { "lt", "gt", "eq", "so" };
722 (*info
->fprintf_func
) (info
->stream
, "4*cr%d+", cr
);
724 (*info
->fprintf_func
) (info
->stream
, "%s", cbnames
[cc
]);
727 (*info
->fprintf_func
) (info
->stream
, "%d", (int) value
);
731 (*info
->fprintf_func
) (info
->stream
, ")");
735 if ((operand
->flags
& PPC_OPERAND_PARENS
) == 0)
739 (*info
->fprintf_func
) (info
->stream
, "(");
744 /* We have found and printed an instruction.
745 If it was a short VLE instruction we have more to do. */
752 /* Otherwise, return. */
756 /* We could not find a match. */
757 (*info
->fprintf_func
) (info
->stream
, ".long 0x%lx", insn
);
763 print_ppc_disassembler_options (FILE *stream
)
767 fprintf (stream
, _("\n\
768 The following PPC specific disassembler options are supported for use with\n\
771 for (col
= 0, i
= 0; i
< sizeof (ppc_opts
) / sizeof (ppc_opts
[0]); i
++)
773 col
+= fprintf (stream
, " %s,", ppc_opts
[i
].opt
);
776 fprintf (stream
, "\n");
780 fprintf (stream
, " 32, 64\n");