opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001
   3    Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 2, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21 02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
  42 static long extract_bat PARAMS ((unsigned long, int *));
  43 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
  44 static long extract_bba PARAMS ((unsigned long, int *));
  45 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
  46 static long extract_bd PARAMS ((unsigned long, int *));
  47 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
  48 static long extract_bdm PARAMS ((unsigned long, int *));
  49 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
  50 static long extract_bdp PARAMS ((unsigned long, int *));
  51 static int valid_bo PARAMS ((long));
  52 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
  53 static long extract_bo PARAMS ((unsigned long, int *));
  54 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
  55 static long extract_boe PARAMS ((unsigned long, int *));
  56 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
  57 static long extract_ds PARAMS ((unsigned long, int *));
  58 static unsigned long insert_de PARAMS ((unsigned long, long, const char **));
  59 static long extract_de PARAMS ((unsigned long, int *));
  60 static unsigned long insert_des PARAMS ((unsigned long, long, const char **));
  61 static long extract_des PARAMS ((unsigned long, int *));
  62 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
  63 static long extract_li PARAMS ((unsigned long, int *));
  64 static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
  65 static long extract_mbe PARAMS ((unsigned long, int *));
  66 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
  67 static long extract_mb6 PARAMS ((unsigned long, int *));
  68 static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
  69 static long extract_nb PARAMS ((unsigned long, int *));
  70 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
  71 static long extract_nsi PARAMS ((unsigned long, int *));
  72 static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
  73 static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
  74 static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
  75 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
  76 static long extract_rbs PARAMS ((unsigned long, int *));
  77 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
  78 static long extract_sh6 PARAMS ((unsigned long, int *));
  79 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
  80 static long extract_spr PARAMS ((unsigned long, int *));
  81 static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
  82 static long extract_tbr PARAMS ((unsigned long, int *));
  83 \f
  84 /* The operands table.
  85
  86    The fields are bits, shift, insert, extract, flags.
  87
  88    We used to put parens around the various additions, like the one
  89    for BA just below.  However, that caused trouble with feeble
  90    compilers with a limit on depth of a parenthesized expression, like
  91    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
  92    omit the parens, since the macros are never used in a context where
  93    the addition will be ambiguous.  */
  94
  95 const struct powerpc_operand powerpc_operands[] =
  96 {
  97   /* The zero index is used to indicate the end of the list of
  98      operands.  */
  99 #define UNUSED 0
 100   { 0, 0, 0, 0, 0 },
 101
 102   /* The BA field in an XL form instruction.  */
 103 #define BA UNUSED + 1
 104 #define BA_MASK (0x1f << 16)
 105   { 5, 16, 0, 0, PPC_OPERAND_CR },
 106
 107   /* The BA field in an XL form instruction when it must be the same
 108      as the BT field in the same instruction.  */
 109 #define BAT BA + 1
 110   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 111
 112   /* The BB field in an XL form instruction.  */
 113 #define BB BAT + 1
 114 #define BB_MASK (0x1f << 11)
 115   { 5, 11, 0, 0, PPC_OPERAND_CR },
 116
 117   /* The BB field in an XL form instruction when it must be the same
 118      as the BA field in the same instruction.  */
 119 #define BBA BB + 1
 120   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 121
 122   /* The BD field in a B form instruction.  The lower two bits are
 123      forced to zero.  */
 124 #define BD BBA + 1
 125   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 126
 127   /* The BD field in a B form instruction when absolute addressing is
 128      used.  */
 129 #define BDA BD + 1
 130   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 131
 132   /* The BD field in a B form instruction when the - modifier is used.
 133      This sets the y bit of the BO field appropriately.  */
 134 #define BDM BDA + 1
 135   { 16, 0, insert_bdm, extract_bdm,
 136       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 137
 138   /* The BD field in a B form instruction when the - modifier is used
 139      and absolute address is used.  */
 140 #define BDMA BDM + 1
 141   { 16, 0, insert_bdm, extract_bdm,
 142       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 143
 144   /* The BD field in a B form instruction when the + modifier is used.
 145      This sets the y bit of the BO field appropriately.  */
 146 #define BDP BDMA + 1
 147   { 16, 0, insert_bdp, extract_bdp,
 148       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 149
 150   /* The BD field in a B form instruction when the + modifier is used
 151      and absolute addressing is used.  */
 152 #define BDPA BDP + 1
 153   { 16, 0, insert_bdp, extract_bdp,
 154       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 155
 156   /* The BF field in an X or XL form instruction.  */
 157 #define BF BDPA + 1
 158   { 3, 23, 0, 0, PPC_OPERAND_CR },
 159
 160   /* An optional BF field.  This is used for comparison instructions,
 161      in which an omitted BF field is taken as zero.  */
 162 #define OBF BF + 1
 163   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 164
 165   /* The BFA field in an X or XL form instruction.  */
 166 #define BFA OBF + 1
 167   { 3, 18, 0, 0, PPC_OPERAND_CR },
 168
 169   /* The BI field in a B form or XL form instruction.  */
 170 #define BI BFA + 1
 171 #define BI_MASK (0x1f << 16)
 172   { 5, 16, 0, 0, PPC_OPERAND_CR },
 173
 174   /* The BO field in a B form instruction.  Certain values are
 175      illegal.  */
 176 #define BO BI + 1
 177 #define BO_MASK (0x1f << 21)
 178   { 5, 21, insert_bo, extract_bo, 0 },
 179
 180   /* The BO field in a B form instruction when the + or - modifier is
 181      used.  This is like the BO field, but it must be even.  */
 182 #define BOE BO + 1
 183   { 5, 21, insert_boe, extract_boe, 0 },
 184
 185   /* The BT field in an X or XL form instruction.  */
 186 #define BT BOE + 1
 187   { 5, 21, 0, 0, PPC_OPERAND_CR },
 188
 189   /* The condition register number portion of the BI field in a B form
 190      or XL form instruction.  This is used for the extended
 191      conditional branch mnemonics, which set the lower two bits of the
 192      BI field.  This field is optional.  */
 193 #define CR BT + 1
 194   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 195
 196   /* The CT field in an X form instruction.  */
 197 #define CT CR + 1
 198   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 199
 200   /* The D field in a D form instruction.  This is a displacement off
 201      a register, and implies that the next operand is a register in
 202      parentheses.  */
 203 #define D CT + 1
 204   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 205
 206   /* The DE field in a DE form instruction.  This is like D, but is 12
 207      bits only.  */
 208 #define DE D + 1
 209   { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
 210
 211   /* The DES field in a DES form instruction.  This is like DS, but is 14
 212      bits only (12 stored.)  */
 213 #define DES DE + 1
 214   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 215
 216   /* The DS field in a DS form instruction.  This is like D, but the
 217      lower two bits are forced to zero.  */
 218 #define DS DES + 1
 219   { 16, 0, insert_ds, extract_ds,
 220       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 221
 222   /* The E field in a wrteei instruction.  */
 223 #define E DS + 1
 224   { 1, 15, 0, 0, 0 },
 225
 226   /* The FL1 field in a POWER SC form instruction.  */
 227 #define FL1 E + 1
 228   { 4, 12, 0, 0, 0 },
 229
 230   /* The FL2 field in a POWER SC form instruction.  */
 231 #define FL2 FL1 + 1
 232   { 3, 2, 0, 0, 0 },
 233
 234   /* The FLM field in an XFL form instruction.  */
 235 #define FLM FL2 + 1
 236   { 8, 17, 0, 0, 0 },
 237
 238   /* The FRA field in an X or A form instruction.  */
 239 #define FRA FLM + 1
 240 #define FRA_MASK (0x1f << 16)
 241   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 242
 243   /* The FRB field in an X or A form instruction.  */
 244 #define FRB FRA + 1
 245 #define FRB_MASK (0x1f << 11)
 246   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 247
 248   /* The FRC field in an A form instruction.  */
 249 #define FRC FRB + 1
 250 #define FRC_MASK (0x1f << 6)
 251   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 252
 253   /* The FRS field in an X form instruction or the FRT field in a D, X
 254      or A form instruction.  */
 255 #define FRS FRC + 1
 256 #define FRT FRS
 257   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 258
 259   /* The FXM field in an XFX instruction.  */
 260 #define FXM FRS + 1
 261 #define FXM_MASK (0xff << 12)
 262   { 8, 12, 0, 0, 0 },
 263
 264   /* The L field in a D or X form instruction.  */
 265 #define L FXM + 1
 266   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 267
 268   /* The LEV field in a POWER SC form instruction.  */
 269 #define LEV L + 1
 270   { 7, 5, 0, 0, 0 },
 271
 272   /* The LI field in an I form instruction.  The lower two bits are
 273      forced to zero.  */
 274 #define LI LEV + 1
 275   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 276
 277   /* The LI field in an I form instruction when used as an absolute
 278      address.  */
 279 #define LIA LI + 1
 280   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 281
 282   /* The LS field in an X (sync) form instruction.  */
 283 #define LS LIA + 1
 284   { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 285
 286   /* The MB field in an M form instruction.  */
 287 #define MB LS + 1
 288 #define MB_MASK (0x1f << 6)
 289   { 5, 6, 0, 0, 0 },
 290
 291   /* The ME field in an M form instruction.  */
 292 #define ME MB + 1
 293 #define ME_MASK (0x1f << 1)
 294   { 5, 1, 0, 0, 0 },
 295
 296   /* The MB and ME fields in an M form instruction expressed a single
 297      operand which is a bitmask indicating which bits to select.  This
 298      is a two operand form using PPC_OPERAND_NEXT.  See the
 299      description in opcode/ppc.h for what this means.  */
 300 #define MBE ME + 1
 301   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 302   { 32, 0, insert_mbe, extract_mbe, 0 },
 303
 304   /* The MB or ME field in an MD or MDS form instruction.  The high
 305      bit is wrapped to the low end.  */
 306 #define MB6 MBE + 2
 307 #define ME6 MB6
 308 #define MB6_MASK (0x3f << 5)
 309   { 6, 5, insert_mb6, extract_mb6, 0 },
 310
 311   /* The MO field in an mbar instruction.  */
 312 #define MO MB6 + 1
 313   { 5, 21, 0, 0, 0 },
 314
 315   /* The NB field in an X form instruction.  The value 32 is stored as
 316      0.  */
 317 #define NB MO + 1
 318   { 6, 11, insert_nb, extract_nb, 0 },
 319
 320   /* The NSI field in a D form instruction.  This is the same as the
 321      SI field, only negated.  */
 322 #define NSI NB + 1
 323   { 16, 0, insert_nsi, extract_nsi,
 324       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 325
 326   /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
 327 #define RA NSI + 1
 328 #define RA_MASK (0x1f << 16)
 329   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 330
 331   /* The RA field in a D or X form instruction which is an updating
 332      load, which means that the RA field may not be zero and may not
 333      equal the RT field.  */
 334 #define RAL RA + 1
 335   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 336
 337   /* The RA field in an lmw instruction, which has special value
 338      restrictions.  */
 339 #define RAM RAL + 1
 340   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
 341
 342   /* The RA field in a D or X form instruction which is an updating
 343      store or an updating floating point load, which means that the RA
 344      field may not be zero.  */
 345 #define RAS RAM + 1
 346   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 347
 348   /* The RB field in an X, XO, M, or MDS form instruction.  */
 349 #define RB RAS + 1
 350 #define RB_MASK (0x1f << 11)
 351   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 352
 353   /* The RB field in an X form instruction when it must be the same as
 354      the RS field in the instruction.  This is used for extended
 355      mnemonics like mr.  */
 356 #define RBS RB + 1
 357   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 358
 359   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 360      instruction or the RT field in a D, DS, X, XFX or XO form
 361      instruction.  */
 362 #define RS RBS + 1
 363 #define RT RS
 364 #define RT_MASK (0x1f << 21)
 365   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 366
 367   /* The SH field in an X or M form instruction.  */
 368 #define SH RS + 1
 369 #define SH_MASK (0x1f << 11)
 370   { 5, 11, 0, 0, 0 },
 371
 372   /* The SH field in an MD form instruction.  This is split.  */
 373 #define SH6 SH + 1
 374 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 375   { 6, 1, insert_sh6, extract_sh6, 0 },
 376
 377   /* The SI field in a D form instruction.  */
 378 #define SI SH6 + 1
 379   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 380
 381   /* The SI field in a D form instruction when we accept a wide range
 382      of positive values.  */
 383 #define SISIGNOPT SI + 1
 384   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 385
 386   /* The SPR field in an XFX form instruction.  This is flipped--the
 387      lower 5 bits are stored in the upper 5 and vice- versa.  */
 388 #define SPR SISIGNOPT + 1
 389 #define SPR_MASK (0x3ff << 11)
 390   { 10, 11, insert_spr, extract_spr, 0 },
 391
 392   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 393 #define SPRBAT SPR + 1
 394 #define SPRBAT_MASK (0x3 << 17)
 395   { 2, 17, 0, 0, 0 },
 396
 397   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 398 #define SPRG SPRBAT + 1
 399 #define SPRG_MASK (0x3 << 16)
 400   { 2, 16, 0, 0, 0 },
 401
 402   /* The SR field in an X form instruction.  */
 403 #define SR SPRG + 1
 404   { 4, 16, 0, 0, 0 },
 405
 406   /* The STRM field in an X AltiVec form instruction.  */
 407 #define STRM SR + 1
 408 #define STRM_MASK (0x3 << 21)
 409   { 2, 21, 0, 0, 0 },
 410
 411   /* The SV field in a POWER SC form instruction.  */
 412 #define SV STRM + 1
 413   { 14, 2, 0, 0, 0 },
 414
 415   /* The TBR field in an XFX form instruction.  This is like the SPR
 416      field, but it is optional.  */
 417 #define TBR SV + 1
 418   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 419
 420   /* The TO field in a D or X form instruction.  */
 421 #define TO TBR + 1
 422 #define TO_MASK (0x1f << 21)
 423   { 5, 21, 0, 0, 0 },
 424
 425   /* The U field in an X form instruction.  */
 426 #define U TO + 1
 427   { 4, 12, 0, 0, 0 },
 428
 429   /* The UI field in a D form instruction.  */
 430 #define UI U + 1
 431   { 16, 0, 0, 0, 0 },
 432
 433   /* The VA field in a VA, VX or VXR form instruction. */
 434 #define VA UI + 1
 435 #define VA_MASK (0x1f << 16)
 436   { 5, 16, 0, 0, PPC_OPERAND_VR },
 437
 438   /* The VB field in a VA, VX or VXR form instruction. */
 439 #define VB VA + 1
 440 #define VB_MASK (0x1f << 11)
 441   { 5, 11, 0, 0, PPC_OPERAND_VR },
 442
 443   /* The VC field in a VA form instruction. */
 444 #define VC VB + 1
 445 #define VC_MASK (0x1f << 6)
 446   { 5, 6, 0, 0, PPC_OPERAND_VR },
 447
 448   /* The VD or VS field in a VA, VX, VXR or X form instruction. */
 449 #define VD VC + 1
 450 #define VS VD
 451 #define VD_MASK (0x1f << 21)
 452   { 5, 21, 0, 0, PPC_OPERAND_VR },
 453
 454   /* The SIMM field in a VX form instruction. */
 455 #define SIMM VD + 1
 456   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 457
 458   /* The UIMM field in a VX form instruction. */
 459 #define UIMM SIMM + 1
 460   { 5, 16, 0, 0, 0 },
 461
 462   /* The SHB field in a VA form instruction. */
 463 #define SHB UIMM + 1
 464   { 4, 6, 0, 0, 0 },
 465 };
 466
 467 /* The functions used to insert and extract complicated operands.  */
 468
 469 /* The BA field in an XL form instruction when it must be the same as
 470    the BT field in the same instruction.  This operand is marked FAKE.
 471    The insertion function just copies the BT field into the BA field,
 472    and the extraction function just checks that the fields are the
 473    same.  */
 474
 475 /*ARGSUSED*/
 476 static unsigned long
 477 insert_bat (insn, value, errmsg)
 478      unsigned long insn;
 479      long value ATTRIBUTE_UNUSED;
 480      const char **errmsg ATTRIBUTE_UNUSED;
 481 {
 482   return insn | (((insn >> 21) & 0x1f) << 16);
 483 }
 484
 485 static long
 486 extract_bat (insn, invalid)
 487      unsigned long insn;
 488      int *invalid;
 489 {
 490   if (invalid != (int *) NULL
 491       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 492     *invalid = 1;
 493   return 0;
 494 }
 495
 496 /* The BB field in an XL form instruction when it must be the same as
 497    the BA field in the same instruction.  This operand is marked FAKE.
 498    The insertion function just copies the BA field into the BB field,
 499    and the extraction function just checks that the fields are the
 500    same.  */
 501
 502 /*ARGSUSED*/
 503 static unsigned long
 504 insert_bba (insn, value, errmsg)
 505      unsigned long insn;
 506      long value ATTRIBUTE_UNUSED;
 507      const char **errmsg ATTRIBUTE_UNUSED;
 508 {
 509   return insn | (((insn >> 16) & 0x1f) << 11);
 510 }
 511
 512 static long
 513 extract_bba (insn, invalid)
 514      unsigned long insn;
 515      int *invalid;
 516 {
 517   if (invalid != (int *) NULL
 518       && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 519     *invalid = 1;
 520   return 0;
 521 }
 522
 523 /* The BD field in a B form instruction.  The lower two bits are
 524    forced to zero.  */
 525
 526 /*ARGSUSED*/
 527 static unsigned long
 528 insert_bd (insn, value, errmsg)
 529      unsigned long insn;
 530      long value;
 531      const char **errmsg ATTRIBUTE_UNUSED;
 532 {
 533   return insn | (value & 0xfffc);
 534 }
 535
 536 /*ARGSUSED*/
 537 static long
 538 extract_bd (insn, invalid)
 539      unsigned long insn;
 540      int *invalid ATTRIBUTE_UNUSED;
 541 {
 542   if ((insn & 0x8000) != 0)
 543     return (insn & 0xfffc) - 0x10000;
 544   else
 545     return insn & 0xfffc;
 546 }
 547
 548 /* The BD field in a B form instruction when the - modifier is used.
 549    This modifier means that the branch is not expected to be taken.
 550    We must set the y bit of the BO field to 1 if the offset is
 551    negative.  When extracting, we require that the y bit be 1 and that
 552    the offset be positive, since if the y bit is 0 we just want to
 553    print the normal form of the instruction.  */
 554
 555 /*ARGSUSED*/
 556 static unsigned long
 557 insert_bdm (insn, value, errmsg)
 558      unsigned long insn;
 559      long value;
 560      const char **errmsg ATTRIBUTE_UNUSED;
 561 {
 562   if ((value & 0x8000) != 0)
 563     insn |= 1 << 21;
 564   return insn | (value & 0xfffc);
 565 }
 566
 567 static long
 568 extract_bdm (insn, invalid)
 569      unsigned long insn;
 570      int *invalid;
 571 {
 572   if (invalid != (int *) NULL
 573       && ((insn & (1 << 21)) == 0
 574           || (insn & (1 << 15)) == 0))
 575     *invalid = 1;
 576   if ((insn & 0x8000) != 0)
 577     return (insn & 0xfffc) - 0x10000;
 578   else
 579     return insn & 0xfffc;
 580 }
 581
 582 /* The BD field in a B form instruction when the + modifier is used.
 583    This is like BDM, above, except that the branch is expected to be
 584    taken.  */
 585
 586 /*ARGSUSED*/
 587 static unsigned long
 588 insert_bdp (insn, value, errmsg)
 589      unsigned long insn;
 590      long value;
 591      const char **errmsg ATTRIBUTE_UNUSED;
 592 {
 593   if ((value & 0x8000) == 0)
 594     insn |= 1 << 21;
 595   return insn | (value & 0xfffc);
 596 }
 597
 598 static long
 599 extract_bdp (insn, invalid)
 600      unsigned long insn;
 601      int *invalid;
 602 {
 603   if (invalid != (int *) NULL
 604       && ((insn & (1 << 21)) == 0
 605           || (insn & (1 << 15)) != 0))
 606     *invalid = 1;
 607   if ((insn & 0x8000) != 0)
 608     return (insn & 0xfffc) - 0x10000;
 609   else
 610     return insn & 0xfffc;
 611 }
 612
 613 /* Check for legal values of a BO field.  */
 614
 615 static int
 616 valid_bo (value)
 617      long value;
 618 {
 619   /* Certain encodings have bits that are required to be zero.  These
 620      are (z must be zero, y may be anything):
 621          001zy
 622          011zy
 623          1z00y
 624          1z01y
 625          1z1zz
 626      */
 627   switch (value & 0x14)
 628     {
 629     default:
 630     case 0:
 631       return 1;
 632     case 0x4:
 633       return (value & 0x2) == 0;
 634     case 0x10:
 635       return (value & 0x8) == 0;
 636     case 0x14:
 637       return value == 0x14;
 638     }
 639 }
 640
 641 /* The BO field in a B form instruction.  Warn about attempts to set
 642    the field to an illegal value.  */
 643
 644 static unsigned long
 645 insert_bo (insn, value, errmsg)
 646      unsigned long insn;
 647      long value;
 648      const char **errmsg;
 649 {
 650   if (errmsg != (const char **) NULL
 651       && ! valid_bo (value))
 652     *errmsg = _("invalid conditional option");
 653   return insn | ((value & 0x1f) << 21);
 654 }
 655
 656 static long
 657 extract_bo (insn, invalid)
 658      unsigned long insn;
 659      int *invalid;
 660 {
 661   long value;
 662
 663   value = (insn >> 21) & 0x1f;
 664   if (invalid != (int *) NULL
 665       && ! valid_bo (value))
 666     *invalid = 1;
 667   return value;
 668 }
 669
 670 /* The BO field in a B form instruction when the + or - modifier is
 671    used.  This is like the BO field, but it must be even.  When
 672    extracting it, we force it to be even.  */
 673
 674 static unsigned long
 675 insert_boe (insn, value, errmsg)
 676      unsigned long insn;
 677      long value;
 678      const char **errmsg;
 679 {
 680   if (errmsg != (const char **) NULL)
 681     {
 682       if (! valid_bo (value))
 683         *errmsg = _("invalid conditional option");
 684       else if ((value & 1) != 0)
 685         *errmsg = _("attempt to set y bit when using + or - modifier");
 686     }
 687   return insn | ((value & 0x1f) << 21);
 688 }
 689
 690 static long
 691 extract_boe (insn, invalid)
 692      unsigned long insn;
 693      int *invalid;
 694 {
 695   long value;
 696
 697   value = (insn >> 21) & 0x1f;
 698   if (invalid != (int *) NULL
 699       && ! valid_bo (value))
 700     *invalid = 1;
 701   return value & 0x1e;
 702 }
 703
 704 /* The DS field in a DS form instruction.  This is like D, but the
 705    lower two bits are forced to zero.  */
 706
 707 /*ARGSUSED*/
 708 static unsigned long
 709 insert_ds (insn, value, errmsg)
 710      unsigned long insn;
 711      long value;
 712      const char **errmsg;
 713 {
 714   if ((value & 3) != 0 && errmsg != NULL)
 715     *errmsg = _("offset not a multiple of 4");
 716   return insn | (value & 0xfffc);
 717 }
 718
 719 /*ARGSUSED*/
 720 static long
 721 extract_ds (insn, invalid)
 722      unsigned long insn;
 723      int *invalid ATTRIBUTE_UNUSED;
 724 {
 725   if ((insn & 0x8000) != 0)
 726     return (insn & 0xfffc) - 0x10000;
 727   else
 728     return insn & 0xfffc;
 729 }
 730
 731 /* The DE field in a DE form instruction.  */
 732
 733 /*ARGSUSED*/
 734 static unsigned long
 735 insert_de (insn, value, errmsg)
 736      unsigned long insn;
 737      long value;
 738      const char **errmsg;
 739 {
 740   if ((value > 2047 || value < -2048) && errmsg != NULL)
 741     *errmsg = _("offset not between -2048 and 2047");
 742   return insn | ((value << 4) & 0xfff0);
 743 }
 744
 745 /*ARGSUSED*/
 746 static long
 747 extract_de (insn, invalid)
 748      unsigned long insn;
 749      int *invalid ATTRIBUTE_UNUSED;
 750 {
 751   return (insn & 0xfff0) >> 4;
 752 }
 753
 754 /* The DES field in a DES form instruction.  */
 755
 756 /*ARGSUSED*/
 757 static unsigned long
 758 insert_des (insn, value, errmsg)
 759      unsigned long insn;
 760      long value;
 761      const char **errmsg;
 762 {
 763   if ((value > 8191 || value < -8192) && errmsg != NULL)
 764     *errmsg = _("offset not between -8192 and 8191");
 765   else if ((value & 3) != 0 && errmsg != NULL)
 766     *errmsg = _("offset not a multiple of 4");
 767   return insn | ((value << 2) & 0xfff0);
 768 }
 769
 770 /*ARGSUSED*/
 771 static long
 772 extract_des (insn, invalid)
 773      unsigned long insn;
 774      int *invalid ATTRIBUTE_UNUSED;
 775 {
 776   if ((insn & 0x8000) != 0)
 777     return ((insn & 0xfff0) >> 2) - 0x4000;
 778   else
 779     return (insn & 0xfff0) >> 2;
 780 }
 781
 782 /* The LI field in an I form instruction.  The lower two bits are
 783    forced to zero.  */
 784
 785 /*ARGSUSED*/
 786 static unsigned long
 787 insert_li (insn, value, errmsg)
 788      unsigned long insn;
 789      long value;
 790      const char **errmsg;
 791 {
 792   if ((value & 3) != 0 && errmsg != (const char **) NULL)
 793     *errmsg = _("ignoring least significant bits in branch offset");
 794   return insn | (value & 0x3fffffc);
 795 }
 796
 797 /*ARGSUSED*/
 798 static long
 799 extract_li (insn, invalid)
 800      unsigned long insn;
 801      int *invalid ATTRIBUTE_UNUSED;
 802 {
 803   if ((insn & 0x2000000) != 0)
 804     return (insn & 0x3fffffc) - 0x4000000;
 805   else
 806     return insn & 0x3fffffc;
 807 }
 808
 809 /* The MB and ME fields in an M form instruction expressed as a single
 810    operand which is itself a bitmask.  The extraction function always
 811    marks it as invalid, since we never want to recognize an
 812    instruction which uses a field of this type.  */
 813
 814 static unsigned long
 815 insert_mbe (insn, value, errmsg)
 816      unsigned long insn;
 817      long value;
 818      const char **errmsg;
 819 {
 820   unsigned long uval, mask;
 821   int mb, me, mx, count, last;
 822
 823   uval = value;
 824
 825   if (uval == 0)
 826     {
 827       if (errmsg != (const char **) NULL)
 828         *errmsg = _("illegal bitmask");
 829       return insn;
 830     }
 831
 832   mb = 0;
 833   me = 32;
 834   if ((uval & 1) != 0)
 835     last = 1;
 836   else
 837     last = 0;
 838   count = 0;
 839
 840   /* mb: location of last 0->1 transition */
 841   /* me: location of last 1->0 transition */
 842   /* count: # transitions */
 843
 844   for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
 845     {
 846       if ((uval & mask) && !last)
 847         {
 848           ++count;
 849           mb = mx;
 850           last = 1;
 851         }
 852       else if (!(uval & mask) && last)
 853         {
 854           ++count;
 855           me = mx;
 856           last = 0;
 857         }
 858     }
 859   if (me == 0)
 860     me = 32;
 861
 862   if (count != 2 && (count != 0 || ! last))
 863     {
 864       if (errmsg != (const char **) NULL)
 865         *errmsg = _("illegal bitmask");
 866     }
 867
 868   return insn | (mb << 6) | ((me - 1) << 1);
 869 }
 870
 871 static long
 872 extract_mbe (insn, invalid)
 873      unsigned long insn;
 874      int *invalid;
 875 {
 876   long ret;
 877   int mb, me;
 878   int i;
 879
 880   if (invalid != (int *) NULL)
 881     *invalid = 1;
 882
 883   mb = (insn >> 6) & 0x1f;
 884   me = (insn >> 1) & 0x1f;
 885   if (mb < me + 1)
 886     {
 887       ret = 0;
 888       for (i = mb; i <= me; i++)
 889         ret |= (long) 1 << (31 - i);
 890     }
 891   else if (mb == me + 1)
 892     ret = ~0;
 893   else /* (mb > me + 1) */
 894     {
 895       ret = ~ (long) 0;
 896       for (i = me + 1; i < mb; i++)
 897         ret &= ~ ((long) 1 << (31 - i));
 898     }
 899   return ret;
 900 }
 901
 902 /* The MB or ME field in an MD or MDS form instruction.  The high bit
 903    is wrapped to the low end.  */
 904
 905 /*ARGSUSED*/
 906 static unsigned long
 907 insert_mb6 (insn, value, errmsg)
 908      unsigned long insn;
 909      long value;
 910      const char **errmsg ATTRIBUTE_UNUSED;
 911 {
 912   return insn | ((value & 0x1f) << 6) | (value & 0x20);
 913 }
 914
 915 /*ARGSUSED*/
 916 static long
 917 extract_mb6 (insn, invalid)
 918      unsigned long insn;
 919      int *invalid ATTRIBUTE_UNUSED;
 920 {
 921   return ((insn >> 6) & 0x1f) | (insn & 0x20);
 922 }
 923
 924 /* The NB field in an X form instruction.  The value 32 is stored as
 925    0.  */
 926
 927 static unsigned long
 928 insert_nb (insn, value, errmsg)
 929      unsigned long insn;
 930      long value;
 931      const char **errmsg;
 932 {
 933   if (value < 0 || value > 32)
 934     *errmsg = _("value out of range");
 935   if (value == 32)
 936     value = 0;
 937   return insn | ((value & 0x1f) << 11);
 938 }
 939
 940 /*ARGSUSED*/
 941 static long
 942 extract_nb (insn, invalid)
 943      unsigned long insn;
 944      int *invalid ATTRIBUTE_UNUSED;
 945 {
 946   long ret;
 947
 948   ret = (insn >> 11) & 0x1f;
 949   if (ret == 0)
 950     ret = 32;
 951   return ret;
 952 }
 953
 954 /* The NSI field in a D form instruction.  This is the same as the SI
 955    field, only negated.  The extraction function always marks it as
 956    invalid, since we never want to recognize an instruction which uses
 957    a field of this type.  */
 958
 959 /*ARGSUSED*/
 960 static unsigned long
 961 insert_nsi (insn, value, errmsg)
 962      unsigned long insn;
 963      long value;
 964      const char **errmsg ATTRIBUTE_UNUSED;
 965 {
 966   return insn | ((- value) & 0xffff);
 967 }
 968
 969 static long
 970 extract_nsi (insn, invalid)
 971      unsigned long insn;
 972      int *invalid;
 973 {
 974   if (invalid != (int *) NULL)
 975     *invalid = 1;
 976   if ((insn & 0x8000) != 0)
 977     return - ((long)(insn & 0xffff) - 0x10000);
 978   else
 979     return - (long)(insn & 0xffff);
 980 }
 981
 982 /* The RA field in a D or X form instruction which is an updating
 983    load, which means that the RA field may not be zero and may not
 984    equal the RT field.  */
 985
 986 static unsigned long
 987 insert_ral (insn, value, errmsg)
 988      unsigned long insn;
 989      long value;
 990      const char **errmsg;
 991 {
 992   if (value == 0
 993       || (unsigned long) value == ((insn >> 21) & 0x1f))
 994     *errmsg = "invalid register operand when updating";
 995   return insn | ((value & 0x1f) << 16);
 996 }
 997
 998 /* The RA field in an lmw instruction, which has special value
 999    restrictions.  */
1000
1001 static unsigned long
1002 insert_ram (insn, value, errmsg)
1003      unsigned long insn;
1004      long value;
1005      const char **errmsg;
1006 {
1007   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1008     *errmsg = _("index register in load range");
1009   return insn | ((value & 0x1f) << 16);
1010 }
1011
1012 /* The RA field in a D or X form instruction which is an updating
1013    store or an updating floating point load, which means that the RA
1014    field may not be zero.  */
1015
1016 static unsigned long
1017 insert_ras (insn, value, errmsg)
1018      unsigned long insn;
1019      long value;
1020      const char **errmsg;
1021 {
1022   if (value == 0)
1023     *errmsg = _("invalid register operand when updating");
1024   return insn | ((value & 0x1f) << 16);
1025 }
1026
1027 /* The RB field in an X form instruction when it must be the same as
1028    the RS field in the instruction.  This is used for extended
1029    mnemonics like mr.  This operand is marked FAKE.  The insertion
1030    function just copies the BT field into the BA field, and the
1031    extraction function just checks that the fields are the same.  */
1032
1033 /*ARGSUSED*/
1034 static unsigned long
1035 insert_rbs (insn, value, errmsg)
1036      unsigned long insn;
1037      long value ATTRIBUTE_UNUSED;
1038      const char **errmsg ATTRIBUTE_UNUSED;
1039 {
1040   return insn | (((insn >> 21) & 0x1f) << 11);
1041 }
1042
1043 static long
1044 extract_rbs (insn, invalid)
1045      unsigned long insn;
1046      int *invalid;
1047 {
1048   if (invalid != (int *) NULL
1049       && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1050     *invalid = 1;
1051   return 0;
1052 }
1053
1054 /* The SH field in an MD form instruction.  This is split.  */
1055
1056 /*ARGSUSED*/
1057 static unsigned long
1058 insert_sh6 (insn, value, errmsg)
1059      unsigned long insn;
1060      long value;
1061      const char **errmsg ATTRIBUTE_UNUSED;
1062 {
1063   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1064 }
1065
1066 /*ARGSUSED*/
1067 static long
1068 extract_sh6 (insn, invalid)
1069      unsigned long insn;
1070      int *invalid ATTRIBUTE_UNUSED;
1071 {
1072   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1073 }
1074
1075 /* The SPR field in an XFX form instruction.  This is flipped--the
1076    lower 5 bits are stored in the upper 5 and vice- versa.  */
1077
1078 static unsigned long
1079 insert_spr (insn, value, errmsg)
1080      unsigned long insn;
1081      long value;
1082      const char **errmsg ATTRIBUTE_UNUSED;
1083 {
1084   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1085 }
1086
1087 static long
1088 extract_spr (insn, invalid)
1089      unsigned long insn;
1090      int *invalid ATTRIBUTE_UNUSED;
1091 {
1092   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1093 }
1094
1095 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1096    is optional.  When TBR is omitted, it must be inserted as 268 (the
1097    magic number of the TB register).  These functions treat 0
1098    (indicating an omitted optional operand) as 268.  This means that
1099    ``mftb 4,0'' is not handled correctly.  This does not matter very
1100    much, since the architecture manual does not define mftb as
1101    accepting any values other than 268 or 269.  */
1102
1103 #define TB (268)
1104
1105 static unsigned long
1106 insert_tbr (insn, value, errmsg)
1107      unsigned long insn;
1108      long value;
1109      const char **errmsg ATTRIBUTE_UNUSED;
1110 {
1111   if (value == 0)
1112     value = TB;
1113   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1114 }
1115
1116 static long
1117 extract_tbr (insn, invalid)
1118      unsigned long insn;
1119      int *invalid ATTRIBUTE_UNUSED;
1120 {
1121   long ret;
1122
1123   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1124   if (ret == TB)
1125     ret = 0;
1126   return ret;
1127 }
1128 \f
1129 /* Macros used to form opcodes.  */
1130
1131 /* The main opcode.  */
1132 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1133 #define OP_MASK OP (0x3f)
1134
1135 /* The main opcode combined with a trap code in the TO field of a D
1136    form instruction.  Used for extended mnemonics for the trap
1137    instructions.  */
1138 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1139 #define OPTO_MASK (OP_MASK | TO_MASK)
1140
1141 /* The main opcode combined with a comparison size bit in the L field
1142    of a D form or X form instruction.  Used for extended mnemonics for
1143    the comparison instructions.  */
1144 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1145 #define OPL_MASK OPL (0x3f,1)
1146
1147 /* An A form instruction.  */
1148 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1149 #define A_MASK A (0x3f, 0x1f, 1)
1150
1151 /* An A_MASK with the FRB field fixed.  */
1152 #define AFRB_MASK (A_MASK | FRB_MASK)
1153
1154 /* An A_MASK with the FRC field fixed.  */
1155 #define AFRC_MASK (A_MASK | FRC_MASK)
1156
1157 /* An A_MASK with the FRA and FRC fields fixed.  */
1158 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1159
1160 /* A B form instruction.  */
1161 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1162 #define B_MASK B (0x3f, 1, 1)
1163
1164 /* A B form instruction setting the BO field.  */
1165 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1166 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1167
1168 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1169    matching a conditional branch regardless of the setting of the y
1170    bit.  */
1171 #define Y_MASK (((unsigned long)1) << 21)
1172 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1173
1174 /* A B form instruction setting the BO field and the condition bits of
1175    the BI field.  */
1176 #define BBOCB(op, bo, cb, aa, lk) \
1177   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1178 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1179
1180 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1181 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1182
1183 /* A BBOYCB_MASK in which the BI field is fixed.  */
1184 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1185
1186 /* The main opcode mask with the RA field clear.  */
1187 #define DRA_MASK (OP_MASK | RA_MASK)
1188
1189 /* A DS form instruction.  */
1190 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1191 #define DS_MASK DSO (0x3f, 3)
1192
1193 /* A DE form instruction.  */
1194 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1195 #define DE_MASK DEO (0x3e, 0xf)
1196
1197 /* An M form instruction.  */
1198 #define M(op, rc) (OP (op) | ((rc) & 1))
1199 #define M_MASK M (0x3f, 1)
1200
1201 /* An M form instruction with the ME field specified.  */
1202 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1203
1204 /* An M_MASK with the MB and ME fields fixed.  */
1205 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1206
1207 /* An M_MASK with the SH and ME fields fixed.  */
1208 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1209
1210 /* An MD form instruction.  */
1211 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1212 #define MD_MASK MD (0x3f, 0x7, 1)
1213
1214 /* An MD_MASK with the MB field fixed.  */
1215 #define MDMB_MASK (MD_MASK | MB6_MASK)
1216
1217 /* An MD_MASK with the SH field fixed.  */
1218 #define MDSH_MASK (MD_MASK | SH6_MASK)
1219
1220 /* An MDS form instruction.  */
1221 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1222 #define MDS_MASK MDS (0x3f, 0xf, 1)
1223
1224 /* An MDS_MASK with the MB field fixed.  */
1225 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1226
1227 /* An SC form instruction.  */
1228 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1229 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1230
1231 /* An VX form instruction. */
1232 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1233
1234 /* The mask for an VX form instruction. */
1235 #define VX_MASK VX(0x3f, 0x7ff)
1236
1237 /* An VA form instruction. */
1238 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1239
1240 /* The mask for an VA form instruction. */
1241 #define VXA_MASK VXA(0x3f, 0x3f)
1242
1243 /* An VXR form instruction. */
1244 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1245
1246 /* The mask for a VXR form instruction. */
1247 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1248
1249 /* An X form instruction.  */
1250 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1251
1252 /* An X form instruction with the RC bit specified.  */
1253 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1254
1255 /* The mask for an X form instruction.  */
1256 #define X_MASK XRC (0x3f, 0x3ff, 1)
1257
1258 /* An X_MASK with the RA field fixed.  */
1259 #define XRA_MASK (X_MASK | RA_MASK)
1260
1261 /* An X_MASK with the RB field fixed.  */
1262 #define XRB_MASK (X_MASK | RB_MASK)
1263
1264 /* An X_MASK with the RT field fixed.  */
1265 #define XRT_MASK (X_MASK | RT_MASK)
1266
1267 /* An X_MASK with the RA and RB fields fixed.  */
1268 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1269
1270 /* An X_MASK with the RT and RA fields fixed.  */
1271 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1272
1273 /* An X form comparison instruction.  */
1274 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1275
1276 /* The mask for an X form comparison instruction.  */
1277 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1278
1279 /* The mask for an X form comparison instruction with the L field
1280    fixed.  */
1281 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1282
1283 /* An X form trap instruction with the TO field specified.  */
1284 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1285 #define XTO_MASK (X_MASK | TO_MASK)
1286
1287 /* An X form tlb instruction with the SH field specified.  */
1288 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1289 #define XTLB_MASK (X_MASK | SH_MASK)
1290
1291 /* An X form sync instruction.  */
1292 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1293
1294 /* An X form sync instruction with everything filled in except the LS field.  */
1295 #define XSYNC_MASK (0xff9fffff)
1296
1297 /* An X form AltiVec dss instruction.  */
1298 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1299 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1300
1301 /* An XFL form instruction.  */
1302 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1303 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1304
1305 /* An XL form instruction with the LK field set to 0.  */
1306 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1307
1308 /* An XL form instruction which uses the LK field.  */
1309 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1310
1311 /* The mask for an XL form instruction.  */
1312 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1313
1314 /* An XL form instruction which explicitly sets the BO field.  */
1315 #define XLO(op, bo, xop, lk) \
1316   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1317 #define XLO_MASK (XL_MASK | BO_MASK)
1318
1319 /* An XL form instruction which explicitly sets the y bit of the BO
1320    field.  */
1321 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1322 #define XLYLK_MASK (XL_MASK | Y_MASK)
1323
1324 /* An XL form instruction which sets the BO field and the condition
1325    bits of the BI field.  */
1326 #define XLOCB(op, bo, cb, xop, lk) \
1327   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1328 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1329
1330 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1331 #define XLBB_MASK (XL_MASK | BB_MASK)
1332 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1333 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1334
1335 /* An XL_MASK with the BO and BB fields fixed.  */
1336 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1337
1338 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1339 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1340
1341 /* An XO form instruction.  */
1342 #define XO(op, xop, oe, rc) \
1343   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1344 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1345
1346 /* An XO_MASK with the RB field fixed.  */
1347 #define XORB_MASK (XO_MASK | RB_MASK)
1348
1349 /* An XS form instruction.  */
1350 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1351 #define XS_MASK XS (0x3f, 0x1ff, 1)
1352
1353 /* A mask for the FXM version of an XFX form instruction.  */
1354 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1355
1356 /* An XFX form instruction with the FXM field filled in.  */
1357 #define XFXM(op, xop, fxm) \
1358   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1359
1360 /* An XFX form instruction with the SPR field filled in.  */
1361 #define XSPR(op, xop, spr) \
1362   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1363 #define XSPR_MASK (X_MASK | SPR_MASK)
1364
1365 /* An XFX form instruction with the SPR field filled in except for the
1366    SPRBAT field.  */
1367 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1368
1369 /* An XFX form instruction with the SPR field filled in except for the
1370    SPRG field.  */
1371 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1372
1373 /* An X form instruction with everything filled in except the E field.  */
1374 #define XE_MASK (0xffff7fff)
1375
1376 /* The BO encodings used in extended conditional branch mnemonics.  */
1377 #define BODNZF  (0x0)
1378 #define BODNZFP (0x1)
1379 #define BODZF   (0x2)
1380 #define BODZFP  (0x3)
1381 #define BOF     (0x4)
1382 #define BOFP    (0x5)
1383 #define BODNZT  (0x8)
1384 #define BODNZTP (0x9)
1385 #define BODZT   (0xa)
1386 #define BODZTP  (0xb)
1387 #define BOT     (0xc)
1388 #define BOTP    (0xd)
1389 #define BODNZ   (0x10)
1390 #define BODNZP  (0x11)
1391 #define BODZ    (0x12)
1392 #define BODZP   (0x13)
1393 #define BOU     (0x14)
1394
1395 /* The BI condition bit encodings used in extended conditional branch
1396    mnemonics.  */
1397 #define CBLT    (0)
1398 #define CBGT    (1)
1399 #define CBEQ    (2)
1400 #define CBSO    (3)
1401
1402 /* The TO encodings used in extended trap mnemonics.  */
1403 #define TOLGT   (0x1)
1404 #define TOLLT   (0x2)
1405 #define TOEQ    (0x4)
1406 #define TOLGE   (0x5)
1407 #define TOLNL   (0x5)
1408 #define TOLLE   (0x6)
1409 #define TOLNG   (0x6)
1410 #define TOGT    (0x8)
1411 #define TOGE    (0xc)
1412 #define TONL    (0xc)
1413 #define TOLT    (0x10)
1414 #define TOLE    (0x14)
1415 #define TONG    (0x14)
1416 #define TONE    (0x18)
1417 #define TOU     (0x1f)
1418 \f
1419 /* Smaller names for the flags so each entry in the opcodes table will
1420    fit on a single line.  */
1421 #undef  PPC
1422 #define PPC     PPC_OPCODE_PPC | PPC_OPCODE_ANY
1423 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1424 #define PPC32   PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
1425 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_ANY
1426 #define PPCONLY PPC_OPCODE_PPC
1427 #define PPC403  PPC_OPCODE_403
1428 #define PPC405  PPC403
1429 #define PPC750  PPC
1430 #define PPC860  PPC
1431 #define PPCVEC  PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
1432 #define POWER   PPC_OPCODE_POWER | PPC_OPCODE_ANY
1433 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1434 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1435 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1436 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1437 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1438 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1439 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1440 #define MFDEC1  PPC_OPCODE_POWER
1441 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601
1442 #define BOOKE   PPC_OPCODE_BOOKE
1443 #define BOOKE64 PPC_OPCODE_BOOKE64
1444 \f
1445 /* The opcode table.
1446
1447    The format of the opcode table is:
1448
1449    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1450
1451    NAME is the name of the instruction.
1452    OPCODE is the instruction opcode.
1453    MASK is the opcode mask; this is used to tell the disassembler
1454      which bits in the actual opcode must match OPCODE.
1455    FLAGS are flags indicated what processors support the instruction.
1456    OPERANDS is the list of operands.
1457
1458    The disassembler reads the table in order and prints the first
1459    instruction which matches, so this table is sorted to put more
1460    specific instructions before more general instructions.  It is also
1461    sorted by major opcode.  */
1462
1463 const struct powerpc_opcode powerpc_opcodes[] = {
1464 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1465 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1466 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1467 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1468 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1469 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1470 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1471 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1472 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1473 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1474 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1475 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1476 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1477 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1478 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1479
1480 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1481 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1482 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1483 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1484 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1485 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1486 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1487 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1488 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1489 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1490 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1491 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1492 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1493 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1494 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1495 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1496 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1497 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1498 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1499 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1500 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1501 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1502 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1503 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1504 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1505 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1506 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1507 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1508 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1509 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1510
1511 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1512 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1513 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1514 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1515 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1516 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1517 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1518 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1519 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1520 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1521 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1522 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1523 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1524 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1525 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1526 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1527 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1528 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1529 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1530 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1531 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1532 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1533 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1534 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1535 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1536 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1537 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1538 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1539 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1540 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1541 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1542 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1543 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1544 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1545 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1546 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1547 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1548 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1549 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1550 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1551 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1552 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1553 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1554 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1555 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1556 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1557 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1558 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1559 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1560 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1561 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1562 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1563 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405,         { RT, RA, RB } },
1564 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405,         { RT, RA, RB } },
1565 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405,         { RT, RA, RB } },
1566 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405,         { RT, RA, RB } },
1567 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1568 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1569 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1570 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1571 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1572 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1573 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1574 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1575 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1576 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1577 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1578 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1579 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1580 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1581 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1582 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1583 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1584 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1585 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1586 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1587 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1588 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1589 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1590 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1591 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1592 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1593 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1594 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1595 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1596 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
1597 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1598 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1599 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1600 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1601 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1602 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1603 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1604 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1605 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1606 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1607 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1608 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1609 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1610 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1611 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1612 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1613 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1614 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1615 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1616 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1617 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1618 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1619 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1620 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1621 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1622 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1623 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1624 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1625 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1626 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1627 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1628 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1629 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1630 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1631 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1632 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1633 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1634 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1635 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1636 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1637 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1638 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1639 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1640 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1641 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1642 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1643 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1644 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1645 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1646 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1647 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1648 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1649 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1650 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1651 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1652 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1653 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1654 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1655 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1656 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1657 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1658 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1659 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1660 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1661 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1662 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1663 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1664 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1665 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1666 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1667 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1668 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1669 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1670 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1671 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1672 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1673 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1674 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1675 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1676 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1677 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1678 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1679 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1680 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1681 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1682 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1683 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1684 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1685 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1686 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1687 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1688 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1689 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1690 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1691 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1692 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1693 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1694 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1695 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1696 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1697 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1698 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1699 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
1700 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
1701 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
1702 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
1703 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
1704 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1705 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1706 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1707 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
1708 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1709 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1710 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1711 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
1712 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1713 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1714 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1715 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1716 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1717 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
1718 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
1719 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
1720 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1721 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1722 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1723 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1724 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1725 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1726 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1727 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1728 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1729 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1730 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1731 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1732 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1733 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1734 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1735 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1736 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1737 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1738 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1739 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1740 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1741 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1742 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1743 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1744 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1745 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
1746 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
1747 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
1748 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
1749 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
1750 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
1751 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1752
1753 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1754 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1755
1756 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1757 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1758
1759 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
1760
1761 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
1762 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
1763 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
1764 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
1765
1766 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
1767 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
1768 { "cmpli",   OP(10),    OP_MASK,        PPCONLY,        { BF, L, RA, UI } },
1769 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
1770
1771 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
1772 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
1773 { "cmpi",    OP(11),    OP_MASK,        PPCONLY,        { BF, L, RA, SI } },
1774 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
1775
1776 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1777 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1778 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1779
1780 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1781 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1782 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1783
1784 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
1785 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
1786 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1787 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA } },
1788 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1789 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
1790
1791 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
1792 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
1793 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
1794 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
1795 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1796
1797 { "bdnz-",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BDM } },
1798 { "bdnz+",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BDP } },
1799 { "bdnz",    BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BD } },
1800 { "bdn",     BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM,    { BD } },
1801 { "bdnzl-",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BDM } },
1802 { "bdnzl+",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BDP } },
1803 { "bdnzl",   BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BD } },
1804 { "bdnl",    BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM,    { BD } },
1805 { "bdnza-",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDMA } },
1806 { "bdnza+",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDPA } },
1807 { "bdnza",   BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDA } },
1808 { "bdna",    BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM,    { BDA } },
1809 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDMA } },
1810 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDPA } },
1811 { "bdnzla",  BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDA } },
1812 { "bdnla",   BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM,    { BDA } },
1813 { "bdz-",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPCCOM,    { BDM } },
1814 { "bdz+",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPCCOM,    { BDP } },
1815 { "bdz",     BBO(16,BODZ,0,0),  BBOYBI_MASK, COM,       { BD } },
1816 { "bdzl-",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPCCOM,    { BDM } },
1817 { "bdzl+",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPCCOM,    { BDP } },
1818 { "bdzl",    BBO(16,BODZ,0,1),  BBOYBI_MASK, COM,       { BD } },
1819 { "bdza-",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPCCOM,    { BDMA } },
1820 { "bdza+",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPCCOM,    { BDPA } },
1821 { "bdza",    BBO(16,BODZ,1,0),  BBOYBI_MASK, COM,       { BDA } },
1822 { "bdzla-",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPCCOM,    { BDMA } },
1823 { "bdzla+",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPCCOM,    { BDPA } },
1824 { "bdzla",   BBO(16,BODZ,1,1),  BBOYBI_MASK, COM,       { BDA } },
1825 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1826 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1827 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1828 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1829 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1830 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1831 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1832 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1833 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1834 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1835 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1836 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1837 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1838 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1839 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1840 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1841 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1842 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1843 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1844 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1845 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1846 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1847 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1848 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1849 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1850 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1851 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1852 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1853 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1854 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1855 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1856 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1857 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1858 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1859 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1860 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1861 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1862 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1863 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1864 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1865 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1866 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1867 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1868 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1869 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1870 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1871 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1872 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1873 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1874 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1875 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1876 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1877 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1878 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1879 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1880 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1881 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1882 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1883 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1884 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1885 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1886 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1887 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1888 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1889 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1890 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1891 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1892 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1893 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1894 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1895 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1896 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1897 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1898 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1899 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1900 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1901 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1902 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1903 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1904 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1905 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1906 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1907 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1908 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1909 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1910 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1911 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1912 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1913 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1914 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1915 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1916 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1917 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1918 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1919 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1920 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1921 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1922 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1923 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1924 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1925 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1926 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1927 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1928 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1929 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1930 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1931 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1932 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1933 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1934 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1935 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1936 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1937 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1938 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1939 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1940 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1941 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1942 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1943 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1944 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1945 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1946 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1947 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1948 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1949 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1950 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1951 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1952 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1953 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1954 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1955 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1956 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1957 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1958 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1959 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1960 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1961 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1962 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1963 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1964 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1965 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1966 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1967 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1968 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1969 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BDM } },
1970 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BDP } },
1971 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
1972 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BDM } },
1973 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BDP } },
1974 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
1975 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1976 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1977 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
1978 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1979 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1980 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
1981 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BDM } },
1982 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BDP } },
1983 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
1984 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BDM } },
1985 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BDP } },
1986 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
1987 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1988 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1989 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
1990 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1991 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1992 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
1993 { "bt-",     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BDM } },
1994 { "bt+",     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BDP } },
1995 { "bt",      BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BD } },
1996 { "bbt",     BBO(16,BOT,0,0), BBOY_MASK, PWRCOM,        { BI, BD } },
1997 { "btl-",    BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BDM } },
1998 { "btl+",    BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BDP } },
1999 { "btl",     BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BD } },
2000 { "bbtl",    BBO(16,BOT,0,1), BBOY_MASK, PWRCOM,        { BI, BD } },
2001 { "bta-",    BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDMA } },
2002 { "bta+",    BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDPA } },
2003 { "bta",     BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDA } },
2004 { "bbta",    BBO(16,BOT,1,0), BBOY_MASK, PWRCOM,        { BI, BDA } },
2005 { "btla-",   BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDMA } },
2006 { "btla+",   BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDPA } },
2007 { "btla",    BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDA } },
2008 { "bbtla",   BBO(16,BOT,1,1), BBOY_MASK, PWRCOM,        { BI, BDA } },
2009 { "bf-",     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BDM } },
2010 { "bf+",     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BDP } },
2011 { "bf",      BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BD } },
2012 { "bbf",     BBO(16,BOF,0,0), BBOY_MASK, PWRCOM,        { BI, BD } },
2013 { "bfl-",    BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BDM } },
2014 { "bfl+",    BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BDP } },
2015 { "bfl",     BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BD } },
2016 { "bbfl",    BBO(16,BOF,0,1), BBOY_MASK, PWRCOM,        { BI, BD } },
2017 { "bfa-",    BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDMA } },
2018 { "bfa+",    BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDPA } },
2019 { "bfa",     BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDA } },
2020 { "bbfa",    BBO(16,BOF,1,0), BBOY_MASK, PWRCOM,        { BI, BDA } },
2021 { "bfla-",   BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDMA } },
2022 { "bfla+",   BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDPA } },
2023 { "bfla",    BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDA } },
2024 { "bbfla",   BBO(16,BOF,1,1), BBOY_MASK, PWRCOM,        { BI, BDA } },
2025 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BDM } },
2026 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BDP } },
2027 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2028 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BDM } },
2029 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BDP } },
2030 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2031 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDMA } },
2032 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDPA } },
2033 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2034 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDMA } },
2035 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDPA } },
2036 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2037 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BDM } },
2038 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BDP } },
2039 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2040 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BDM } },
2041 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BDP } },
2042 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2043 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDMA } },
2044 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDPA } },
2045 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2046 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDMA } },
2047 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDPA } },
2048 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2049 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2050 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2051 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2052 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2053 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2054 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2055 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2056 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2057 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2058 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2059 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2060 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2061
2062 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
2063 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2064 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
2065 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2066 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2067
2068 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2069 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2070 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2071 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2072
2073 { "mcrf",    XL(19,0),  XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
2074
2075 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2076 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2077 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2078 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2079 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2080 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2081 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM,        { 0 } },
2082 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2083 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2084 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM,        { 0 } },
2085 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2086 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2087 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2088 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2089 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2090 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2091 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2092 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2093 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2094 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2095 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2096 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2097 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2098 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2099 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2100 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2101 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2102 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2103 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2104 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2105 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2106 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2107 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2108 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2109 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2110 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2111 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2112 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2113 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2114 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2115 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2116 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2117 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2118 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2119 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2120 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2121 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2122 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2123 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2124 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2125 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2126 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2127 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2128 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2129 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2130 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2131 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2132 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2133 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2134 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2135 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2136 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2137 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2138 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2139 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2140 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2141 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2142 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2143 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2144 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2145 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2146 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2147 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2148 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2149 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2150 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2151 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2152 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2153 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2154 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2155 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2156 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2157 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2158 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2159 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2160 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2161 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2162 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2163 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2164 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2165 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2166 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2167 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2168 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2169 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2170 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2171 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2172 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2173 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2174 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2175 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2176 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2177 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2178 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2179 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2180 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2181 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2182 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2183 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2184 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2185 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
2186 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2187 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2188 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2189 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
2190 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2191 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2192 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2193 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
2194 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2195 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2196 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2197 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
2198 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2199 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2200 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2201 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2202 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2203 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2204 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2205 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2206 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2207 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2208 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2209 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2210 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2211 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2212 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2213 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2214 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2215 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2216 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2217 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2218 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2219 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2220 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2221 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2222 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2223 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
2224 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
2225 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2226 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2227 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2228 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2229 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2230 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2231 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2232 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2233
2234 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2235
2236 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2237 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2238
2239 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2240 { "rfci",    XL(19,51), 0xffffffff,     PPC403,         { 0 } },
2241 { "rfci",    XL(19,51), 0xffffffff,     BOOKE,          { 0 } },
2242
2243 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2244
2245 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2246
2247 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2248 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2249
2250 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2251 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2252
2253 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2254
2255 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2256
2257 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2258 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2259
2260 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2261
2262 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2263 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2264
2265 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2266 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2267 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2268 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2269 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2270 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2271 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2272 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2273 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2274 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2275 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2276 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2277 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2278 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2279 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2280 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2281 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2282 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2283 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2284 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2285 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2286 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2287 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2288 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2289 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2290 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2291 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2292 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2293 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2294 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2295 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2296 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2297 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2298 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2299 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2300 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2301 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2302 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2303 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2304 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2305 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2306 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2307 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2308 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2309 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2310 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2311 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2312 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2313 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2314 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2315 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2316 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2317 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2318 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2319 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2320 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2321 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2322 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2323 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2324 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2325 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2326 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2327 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2328 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2329 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2330 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2331 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2332 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2333 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2334 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2335 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2336 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2337 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2338 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2339 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2340 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2341 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM,   { BI } },
2342 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2343 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2344 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM,   { BI } },
2345 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2346 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2347 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM,   { BI } },
2348 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2349 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2350 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM,   { BI } },
2351 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
2352 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2353 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2354 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
2355 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2356 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2357 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2358 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2359 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
2360 { "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
2361
2362 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2363 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2364
2365 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2366 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2367
2368 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
2369 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2370 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2371 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2372 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
2373 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2374 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2375 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2376
2377 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2378 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2379
2380 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
2381 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
2382 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
2383 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
2384
2385 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2386 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2387 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2388 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2389 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2390 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2391
2392 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
2393 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2394 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2395
2396 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2397 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2398
2399 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2400 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2401
2402 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2403 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2404
2405 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2406 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2407
2408 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2409 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2410
2411 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
2412 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
2413 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2414 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
2415 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
2416 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2417
2418 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2419 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2420
2421 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2422 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2423
2424 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2425 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2426
2427 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2428 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2429 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2430 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2431
2432 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2433 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2434
2435 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
2436 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
2437 { "cmp",     X(31,0),   XCMP_MASK,      PPCONLY,        { BF, L, RA, RB } },
2438 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
2439
2440 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
2441 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
2442 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
2443 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
2444 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
2445 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
2446 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
2447 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
2448 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
2449 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
2450 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
2451 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
2452 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
2453 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
2454 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
2455 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
2456 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
2457 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
2458 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
2459 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
2460 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
2461 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
2462 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
2463 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
2464 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
2465 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
2466 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
2467 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
2468 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
2469 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
2470 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
2471
2472 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2473 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2474 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
2475 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2476 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2477 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
2478 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2479 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2480 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
2481 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2482 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2483 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
2484
2485 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
2486 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
2487
2488 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2489 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2490 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2491 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2492 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2493 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2494 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2495 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2496
2497 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2498 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2499
2500 { "mfcr",    X(31,19),  XRARB_MASK,     COM,            { RT } },
2501
2502 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
2503
2504 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA, RB } },
2505
2506 { "icbt",    X(31,22),  X_MASK,         BOOKE,          { CT, RA, RB } },
2507
2508 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA, RB } },
2509 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2510
2511 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
2512 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
2513 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
2514 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
2515
2516 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
2517 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
2518 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
2519 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
2520
2521 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
2522 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
2523
2524 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
2525 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
2526
2527 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
2528 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
2529
2530 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
2531
2532 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA, RB } },
2533
2534 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
2535 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
2536 { "cmpl",    X(31,32),  XCMP_MASK,       PPCONLY,       { BF, L, RA, RB } },
2537 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
2538
2539 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2540 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
2541 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2542 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
2543 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
2544 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
2545 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
2546 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
2547
2548 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
2549
2550 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
2551
2552 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
2553 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2554
2555 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
2556
2557 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
2558
2559 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
2560 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
2561
2562 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
2563 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
2564
2565 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
2566 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
2567 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
2568 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
2569 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
2570 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
2571 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
2572 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
2573 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
2574 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
2575 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
2576 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
2577 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
2578 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
2579 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
2580
2581 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
2582 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
2583
2584 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2585 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2586
2587 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
2588
2589 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
2590
2591 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA, RB } },
2592
2593 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
2594
2595 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA, RB } },
2596
2597 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
2598
2599 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA, RB } },
2600
2601 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
2602 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
2603 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
2604 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
2605
2606 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2607 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2608 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2609 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2610
2611 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
2612
2613 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
2614
2615 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
2616
2617 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
2618 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
2619 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
2620 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
2621
2622 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA, RB } },
2623
2624 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
2625
2626 { "wrtee",   X(31,131), XRARB_MASK,     PPC403,         { RS } },
2627 { "wrtee",   X(31,131), XRARB_MASK,     BOOKE,          { RS } },
2628
2629 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2630 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2631 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2632 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2633 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2634 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2635 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2636 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2637
2638 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2639 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2640 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2641 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2642 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2643 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2644 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2645 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2646
2647 { "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM,      { RS }},
2648 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
2649
2650 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
2651
2652 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA, RB } },
2653
2654 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
2655
2656 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA, RB } },
2657 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
2658
2659 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
2660
2661 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA, RB } },
2662
2663 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
2664 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
2665
2666 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
2667 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
2668
2669 { "wrteei",  X(31,163), XE_MASK,        PPC403,         { E } },
2670 { "wrteei",  X(31,163), XE_MASK,        BOOKE,          { E } },
2671
2672 { "mtmsrd",  X(31,178), XRARB_MASK,     PPC64,          { RS } },
2673
2674 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
2675
2676 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
2677 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA, RB } },
2678
2679 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
2680 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
2681
2682 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
2683
2684 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2685 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2686 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2687 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2688 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2689 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2690 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2691 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2692
2693 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2694 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2695 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2696 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2697 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2698 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2699 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2700 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2701
2702 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
2703
2704 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA, RB } },
2705
2706 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA, RB } },
2707
2708 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
2709 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
2710
2711 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
2712 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
2713
2714 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA, RB } },
2715
2716 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2717 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2718 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2719 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2720 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2721 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2722 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2723 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2724
2725 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2726 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2727 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2728 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2729
2730 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2731 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2732 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2733 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2734 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2735 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2736 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2737 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2738
2739 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2740 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2741 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2742 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2743 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2744 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2745 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2746 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2747
2748 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
2749 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
2750
2751 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { CT, RA, RB } },
2752
2753 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
2754
2755 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
2756 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
2757
2758 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
2759
2760 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
2761
2762 { "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
2763
2764 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
2765
2766 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2767 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2768 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2769 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2770
2771 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2772 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2773 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2774 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2775 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2776 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2777 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2778 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2779
2780 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
2781
2782 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
2783 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
2784
2785 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { CT, RA, RB } },
2786
2787 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA, RB } },
2788
2789 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
2790 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
2791
2792 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
2793
2794 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA, RB } },
2795
2796 { "tlbie",   X(31,306), XRTRA_MASK,     PPC,            { RB } },
2797 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA, RB } },
2798
2799 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
2800
2801 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
2802
2803 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
2804 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
2805
2806 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
2807
2808 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403,        { RT } },
2809 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403,        { RT } },
2810 { "mfbr0",   XSPR(31,323,128), XSPR_MASK, PPC403,       { RT } },
2811 { "mfbr1",   XSPR(31,323,129), XSPR_MASK, PPC403,       { RT } },
2812 { "mfbr2",   XSPR(31,323,130), XSPR_MASK, PPC403,       { RT } },
2813 { "mfbr3",   XSPR(31,323,131), XSPR_MASK, PPC403,       { RT } },
2814 { "mfbr4",   XSPR(31,323,132), XSPR_MASK, PPC403,       { RT } },
2815 { "mfbr5",   XSPR(31,323,133), XSPR_MASK, PPC403,       { RT } },
2816 { "mfbr6",   XSPR(31,323,134), XSPR_MASK, PPC403,       { RT } },
2817 { "mfbr7",   XSPR(31,323,135), XSPR_MASK, PPC403,       { RT } },
2818 { "mfbear",  XSPR(31,323,144), XSPR_MASK, PPC403,       { RT } },
2819 { "mfbesr",  XSPR(31,323,145), XSPR_MASK, PPC403,       { RT } },
2820 { "mfiocr",  XSPR(31,323,160), XSPR_MASK, PPC403,       { RT } },
2821 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
2822 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
2823 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
2824 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
2825 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
2826 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
2827 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
2828 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
2829 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
2830 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
2831 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
2832 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
2833 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
2834 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
2835 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
2836 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
2837 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
2838 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
2839 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
2840 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
2841 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403,       { RT } },
2842 { "mfdcr",   X(31,323), X_MASK,         PPC403,         { RT, SPR } },
2843 { "mfdcr",   X(31,323), X_MASK,         BOOKE,          { RT, SPR } },
2844
2845 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2846 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2847 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2848 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2849
2850 { "mfmq",     XSPR(31,339,0),   XSPR_MASK, M601,        { RT } },
2851 { "mfxer",    XSPR(31,339,1),   XSPR_MASK, COM,         { RT } },
2852 { "mfrtcu",   XSPR(31,339,4),   XSPR_MASK, COM,         { RT } },
2853 { "mfrtcl",   XSPR(31,339,5),   XSPR_MASK, COM,         { RT } },
2854 { "mfdec",    XSPR(31,339,6),   XSPR_MASK, MFDEC1,      { RT } },
2855 { "mflr",     XSPR(31,339,8),   XSPR_MASK, COM,         { RT } },
2856 { "mfctr",    XSPR(31,339,9),   XSPR_MASK, COM,         { RT } },
2857 { "mftid",    XSPR(31,339,17),  XSPR_MASK, POWER,       { RT } },
2858 { "mfdsisr",  XSPR(31,339,18),  XSPR_MASK, COM,         { RT } },
2859 { "mfdar",    XSPR(31,339,19),  XSPR_MASK, COM,         { RT } },
2860 { "mfdec",    XSPR(31,339,22),  XSPR_MASK, MFDEC2,      { RT } },
2861 { "mfsdr0",   XSPR(31,339,24),  XSPR_MASK, POWER,       { RT } },
2862 { "mfsdr1",   XSPR(31,339,25),  XSPR_MASK, COM,         { RT } },
2863 { "mfsrr0",   XSPR(31,339,26),  XSPR_MASK, COM,         { RT } },
2864 { "mfsrr1",   XSPR(31,339,27),  XSPR_MASK, COM,         { RT } },
2865 { "mfcmpa",   XSPR(31,339,144), XSPR_MASK, PPC860,      { RT } },
2866 { "mfcmpb",   XSPR(31,339,145), XSPR_MASK, PPC860,      { RT } },
2867 { "mfcmpc",   XSPR(31,339,146), XSPR_MASK, PPC860,      { RT } },
2868 { "mfcmpd",   XSPR(31,339,147), XSPR_MASK, PPC860,      { RT } },
2869 { "mficr",    XSPR(31,339,148), XSPR_MASK, PPC860,      { RT } },
2870 { "mfder",    XSPR(31,339,149), XSPR_MASK, PPC860,      { RT } },
2871 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860,      { RT } },
2872 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860,      { RT } },
2873 { "mfcmpe",   XSPR(31,339,152), XSPR_MASK, PPC860,      { RT } },
2874 { "mfcmpf",   XSPR(31,339,153), XSPR_MASK, PPC860,      { RT } },
2875 { "mfcmpg",   XSPR(31,339,154), XSPR_MASK, PPC860,      { RT } },
2876 { "mfcmph",   XSPR(31,339,155), XSPR_MASK, PPC860,      { RT } },
2877 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860,      { RT } },
2878 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860,      { RT } },
2879 { "mfictrl",  XSPR(31,339,158), XSPR_MASK, PPC860,      { RT } },
2880 { "mfbar",    XSPR(31,339,159), XSPR_MASK, PPC860,      { RT } },
2881 { "mfsprg4",  XSPR(31,339,260), XSPR_MASK, PPC405,      { RT } },
2882 { "mfsprg5",  XSPR(31,339,261), XSPR_MASK, PPC405,      { RT } },
2883 { "mfsprg6",  XSPR(31,339,262), XSPR_MASK, PPC405,      { RT } },
2884 { "mfsprg7",  XSPR(31,339,263), XSPR_MASK, PPC405,      { RT } },
2885 { "mfsprg",   XSPR(31,339,272), XSPRG_MASK, PPC,        { RT, SPRG } },
2886 { "mfsprg0",  XSPR(31,339,272), XSPR_MASK, PPC,         { RT } },
2887 { "mfsprg1",  XSPR(31,339,273), XSPR_MASK, PPC,         { RT } },
2888 { "mfsprg2",  XSPR(31,339,274), XSPR_MASK, PPC,         { RT } },
2889 { "mfsprg3",  XSPR(31,339,275), XSPR_MASK, PPC,         { RT } },
2890 { "mfasr",    XSPR(31,339,280), XSPR_MASK, PPC64,       { RT } },
2891 { "mfear",    XSPR(31,339,282), XSPR_MASK, PPC,         { RT } },
2892 { "mfpvr",    XSPR(31,339,287), XSPR_MASK, PPC,         { RT } },
2893 { "mfibatu",  XSPR(31,339,528), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2894 { "mfibatl",  XSPR(31,339,529), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2895 { "mfdbatu",  XSPR(31,339,536), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2896 { "mfdbatl",  XSPR(31,339,537), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2897 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860,      { RT } },
2898 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860,      { RT } },
2899 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860,      { RT } },
2900 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860,      { RT } },
2901 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860,      { RT } },
2902 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860,      { RT } },
2903 { "mfdpdr",   XSPR(31,339,630), XSPR_MASK, PPC860,      { RT } },
2904 { "mfdpir",   XSPR(31,339,631), XSPR_MASK, PPC860,      { RT } },
2905 { "mfimmr",   XSPR(31,339,638), XSPR_MASK, PPC860,      { RT } },
2906 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860,      { RT } },
2907 { "mfmi_ap",  XSPR(31,339,786), XSPR_MASK, PPC860,      { RT } },
2908 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860,      { RT } },
2909 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860,      { RT } },
2910 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860,      { RT } },
2911 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860,      { RT } },
2912 { "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860,      { RT } },
2913 { "mfmd_ap",  XSPR(31,339,794), XSPR_MASK, PPC860,      { RT } },
2914 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860,      { RT } },
2915 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860,      { RT } },
2916 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860,      { RT } },
2917 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860,      { RT } },
2918 { "mfm_tw",   XSPR(31,339,799), XSPR_MASK, PPC860,      { RT } },
2919 { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860,     { RT } },
2920 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860,    { RT } },
2921 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860,    { RT } },
2922 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,    { RT } },
2923 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860,    { RT } },
2924 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860,    { RT } },
2925 { "mfzpr",      XSPR(31,339,944), XSPR_MASK, PPC403,    { RT } },
2926 { "mfpid",      XSPR(31,339,945), XSPR_MASK, PPC403,    { RT } },
2927 { "mfccr0",     XSPR(31,339,947), XSPR_MASK, PPC405,    { RT } },
2928 { "mficdbdr",   XSPR(31,339,979), XSPR_MASK, PPC403,    { RT } },
2929 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
2930 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
2931 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
2932 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
2933 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
2934 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
2935 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
2936 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
2937 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
2938 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
2939 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
2940 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
2941 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
2942 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
2943 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
2944 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
2945 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
2946 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
2947 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
2948 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
2949 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
2950 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
2951 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
2952 { "mfesr",   XSPR(31,339,980), XSPR_MASK, PPC403,       { RT } },
2953 { "mfdear",  XSPR(31,339,981), XSPR_MASK, PPC403,       { RT } },
2954 { "mfevpr",  XSPR(31,339,982), XSPR_MASK, PPC403,       { RT } },
2955 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403,       { RT } },
2956 { "mftsr",   XSPR(31,339,984), XSPR_MASK, PPC403,       { RT } },
2957 { "mftcr",   XSPR(31,339,986), XSPR_MASK, PPC403,       { RT } },
2958 { "mfpit",   XSPR(31,339,987), XSPR_MASK, PPC403,       { RT } },
2959 { "mftbhi",  XSPR(31,339,988), XSPR_MASK, PPC403,       { RT } },
2960 { "mftblo",  XSPR(31,339,989), XSPR_MASK, PPC403,       { RT } },
2961 { "mfsrr2",  XSPR(31,339,990), XSPR_MASK, PPC403,       { RT } },
2962 { "mfsrr3",  XSPR(31,339,991), XSPR_MASK, PPC403,       { RT } },
2963 { "mfdbsr",  XSPR(31,339,1008), XSPR_MASK, PPC403,      { RT } },
2964 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405,      { RT } },
2965 { "mfiac1",  XSPR(31,339,1012), XSPR_MASK, PPC403,      { RT } },
2966 { "mfiac2",  XSPR(31,339,1013), XSPR_MASK, PPC403,      { RT } },
2967 { "mfdac1",  XSPR(31,339,1014), XSPR_MASK, PPC403,      { RT } },
2968 { "mfdac2",  XSPR(31,339,1015), XSPR_MASK, PPC403,      { RT } },
2969 { "mfdccr",  XSPR(31,339,1018), XSPR_MASK, PPC403,      { RT } },
2970 { "mficcr",  XSPR(31,339,1019), XSPR_MASK, PPC403,      { RT } },
2971 { "mfpbl1",  XSPR(31,339,1020), XSPR_MASK, PPC403,      { RT } },
2972 { "mfpbu1",  XSPR(31,339,1021), XSPR_MASK, PPC403,      { RT } },
2973 { "mfpbl2",  XSPR(31,339,1022), XSPR_MASK, PPC403,      { RT } },
2974 { "mfpbu2",  XSPR(31,339,1023), XSPR_MASK, PPC403,      { RT } },
2975 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
2976 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
2977 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
2978 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
2979 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
2980 { "mfspr",   X(31,339), X_MASK,         COM,            { RT, SPR } },
2981
2982 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA, RB } },
2983
2984 { "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
2985 { "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
2986
2987 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA, RB } },
2988
2989 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA, RB } },
2990
2991 { "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
2992 { "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
2993
2994 { "dccci",   X(31,454), XRT_MASK,       PPC403,         { RA, RB } },
2995
2996 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
2997 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
2998 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
2999 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
3000
3001 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3002 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3003 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3004 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3005
3006 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
3007
3008 { "mftbl",   XSPR(31,371,268), XSPR_MASK, PPC,          { RT } },
3009 { "mftbu",   XSPR(31,371,269), XSPR_MASK, PPC,          { RT } },
3010 { "mftb",    X(31,371), X_MASK,         PPC,            { RT, TBR } },
3011
3012 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
3013
3014 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
3015
3016 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3017
3018 { "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
3019
3020 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3021 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3022
3023 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3024 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3025
3026 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3027
3028 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA, RB } },
3029
3030 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3031
3032 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3033
3034 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3035
3036 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3037
3038 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3039 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3040
3041 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3042 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3043
3044 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA, RB } },
3045
3046 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3047
3048 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3049
3050 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3051
3052 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3053
3054 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3055 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3056 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3057 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3058
3059 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403,        { RT } },
3060 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403,        { RT } },
3061 { "mtbr0",   XSPR(31,451,128), XSPR_MASK, PPC403,       { RT } },
3062 { "mtbr1",   XSPR(31,451,129), XSPR_MASK, PPC403,       { RT } },
3063 { "mtbr2",   XSPR(31,451,130), XSPR_MASK, PPC403,       { RT } },
3064 { "mtbr3",   XSPR(31,451,131), XSPR_MASK, PPC403,       { RT } },
3065 { "mtbr4",   XSPR(31,451,132), XSPR_MASK, PPC403,       { RT } },
3066 { "mtbr5",   XSPR(31,451,133), XSPR_MASK, PPC403,       { RT } },
3067 { "mtbr6",   XSPR(31,451,134), XSPR_MASK, PPC403,       { RT } },
3068 { "mtbr7",   XSPR(31,451,135), XSPR_MASK, PPC403,       { RT } },
3069 { "mtbear",  XSPR(31,451,144), XSPR_MASK, PPC403,       { RT } },
3070 { "mtbesr",  XSPR(31,451,145), XSPR_MASK, PPC403,       { RT } },
3071 { "mtiocr",  XSPR(31,451,160), XSPR_MASK, PPC403,       { RT } },
3072 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RT } },
3073 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RT } },
3074 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RT } },
3075 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RT } },
3076 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RT } },
3077 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RT } },
3078 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RT } },
3079 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RT } },
3080 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RT } },
3081 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RT } },
3082 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RT } },
3083 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RT } },
3084 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RT } },
3085 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RT } },
3086 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RT } },
3087 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RT } },
3088 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RT } },
3089 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RT } },
3090 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RT } },
3091 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RT } },
3092 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403,       { RT } },
3093 { "mtdcr",   X(31,451), X_MASK,         PPC403,         { SPR, RS } },
3094 { "mtdcr",   X(31,451), X_MASK,         BOOKE,          { SPR, RS } },
3095
3096 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3097 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3098
3099 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3100 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3101 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3102 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3103
3104 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3105 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3106
3107 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3108 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3109 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3110 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3111
3112 { "mtmq",    XSPR(31,467,0),   XSPR_MASK,    M601,      { RS } },
3113 { "mtxer",   XSPR(31,467,1),   XSPR_MASK,    COM,       { RS } },
3114 { "mtlr",    XSPR(31,467,8),   XSPR_MASK,    COM,       { RS } },
3115 { "mtctr",   XSPR(31,467,9),   XSPR_MASK,    COM,       { RS } },
3116 { "mttid",   XSPR(31,467,17),  XSPR_MASK,    POWER,     { RS } },
3117 { "mtdsisr", XSPR(31,467,18),  XSPR_MASK,    COM,       { RS } },
3118 { "mtdar",   XSPR(31,467,19),  XSPR_MASK,    COM,       { RS } },
3119 { "mtrtcu",  XSPR(31,467,20),  XSPR_MASK,    COM,       { RS } },
3120 { "mtrtcl",  XSPR(31,467,21),  XSPR_MASK,    COM,       { RS } },
3121 { "mtdec",   XSPR(31,467,22),  XSPR_MASK,    COM,       { RS } },
3122 { "mtsdr0",  XSPR(31,467,24),  XSPR_MASK,    POWER,     { RS } },
3123 { "mtsdr1",  XSPR(31,467,25),  XSPR_MASK,    COM,       { RS } },
3124 { "mtsrr0",  XSPR(31,467,26),  XSPR_MASK,    COM,       { RS } },
3125 { "mtsrr1",  XSPR(31,467,27),  XSPR_MASK,    COM,       { RS } },
3126 { "mtcmpa",   XSPR(31,467,144), XSPR_MASK, PPC860,      { RT } },
3127 { "mtcmpb",   XSPR(31,467,145), XSPR_MASK, PPC860,      { RT } },
3128 { "mtcmpc",   XSPR(31,467,146), XSPR_MASK, PPC860,      { RT } },
3129 { "mtcmpd",   XSPR(31,467,147), XSPR_MASK, PPC860,      { RT } },
3130 { "mticr",    XSPR(31,467,148), XSPR_MASK, PPC860,      { RT } },
3131 { "mtder",    XSPR(31,467,149), XSPR_MASK, PPC860,      { RT } },
3132 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860,      { RT } },
3133 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860,      { RT } },
3134 { "mtcmpe",   XSPR(31,467,152), XSPR_MASK, PPC860,      { RT } },
3135 { "mtcmpf",   XSPR(31,467,153), XSPR_MASK, PPC860,      { RT } },
3136 { "mtcmpg",   XSPR(31,467,154), XSPR_MASK, PPC860,      { RT } },
3137 { "mtcmph",   XSPR(31,467,155), XSPR_MASK, PPC860,      { RT } },
3138 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860,      { RT } },
3139 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860,      { RT } },
3140 { "mtictrl",  XSPR(31,467,158), XSPR_MASK, PPC860,      { RT } },
3141 { "mtbar",    XSPR(31,467,159), XSPR_MASK, PPC860,      { RT } },
3142 { "mtsprg",  XSPR(31,467,272), XSPRG_MASK,   PPC,       { SPRG, RS } },
3143 { "mtsprg0", XSPR(31,467,272), XSPR_MASK,    PPC,       { RT } },
3144 { "mtsprg1", XSPR(31,467,273), XSPR_MASK,    PPC,       { RT } },
3145 { "mtsprg2", XSPR(31,467,274), XSPR_MASK,    PPC,       { RT } },
3146 { "mtsprg3", XSPR(31,467,275), XSPR_MASK,    PPC,       { RT } },
3147 { "mtsprg4", XSPR(31,467,276), XSPR_MASK,    PPC405,    { RT } },
3148 { "mtsprg5", XSPR(31,467,277), XSPR_MASK,    PPC405,    { RT } },
3149 { "mtsprg6", XSPR(31,467,278), XSPR_MASK,    PPC405,    { RT } },
3150 { "mtsprg7", XSPR(31,467,279), XSPR_MASK,    PPC405,    { RT } },
3151 { "mtasr",   XSPR(31,467,280), XSPR_MASK,    PPC64,     { RS } },
3152 { "mtear",   XSPR(31,467,282), XSPR_MASK,    PPC,       { RS } },
3153 { "mttbl",   XSPR(31,467,284), XSPR_MASK,    PPC,       { RS } },
3154 { "mttbu",   XSPR(31,467,285), XSPR_MASK,    PPC,       { RS } },
3155 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3156 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3157 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3158 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
3159 { "mtzpr",   XSPR(31,467,944), XSPR_MASK, PPC403,       { RT } },
3160 { "mtpid",   XSPR(31,467,945), XSPR_MASK, PPC403,       { RT } },
3161 { "mtccr0",  XSPR(31,467,947), XSPR_MASK, PPC405,       { RT } },
3162 { "mtiac3",  XSPR(31,467,948), XSPR_MASK, PPC405,       { RT } },
3163 { "mtiac4",  XSPR(31,467,949), XSPR_MASK, PPC405,       { RT } },
3164 { "mtdvc1",  XSPR(31,467,950), XSPR_MASK, PPC405,       { RT } },
3165 { "mtdvc2",  XSPR(31,467,951), XSPR_MASK, PPC405,       { RT } },
3166 { "mtsgr",   XSPR(31,467,953), XSPR_MASK, PPC403,       { RT } },
3167 { "mtdcwr",  XSPR(31,467,954), XSPR_MASK, PPC403,       { RT } },
3168 { "mtsler",  XSPR(31,467,955), XSPR_MASK, PPC405,       { RT } },
3169 { "mtsu0r",  XSPR(31,467,956), XSPR_MASK, PPC405,       { RT } },
3170 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405,       { RT } },
3171 { "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403,       { RT } },
3172 { "mtesr",   XSPR(31,467,980), XSPR_MASK, PPC403,       { RT } },
3173 { "mtdear",  XSPR(31,467,981), XSPR_MASK, PPC403,       { RT } },
3174 { "mtevpr",  XSPR(31,467,982), XSPR_MASK, PPC403,       { RT } },
3175 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403,       { RT } },
3176 { "mttsr",   XSPR(31,467,984), XSPR_MASK, PPC403,       { RT } },
3177 { "mttcr",   XSPR(31,467,986), XSPR_MASK, PPC403,       { RT } },
3178 { "mtpit",   XSPR(31,467,987), XSPR_MASK, PPC403,       { RT } },
3179 { "mttbhi",  XSPR(31,467,988), XSPR_MASK, PPC403,       { RT } },
3180 { "mttblo",  XSPR(31,467,989), XSPR_MASK, PPC403,       { RT } },
3181 { "mtsrr2",  XSPR(31,467,990), XSPR_MASK, PPC403,       { RT } },
3182 { "mtsrr3",  XSPR(31,467,991), XSPR_MASK, PPC403,       { RT } },
3183 { "mtdbsr",  XSPR(31,467,1008), XSPR_MASK, PPC403,      { RT } },
3184 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405,      { RT } },
3185 { "mtiac1",  XSPR(31,467,1012), XSPR_MASK, PPC403,      { RT } },
3186 { "mtiac2",  XSPR(31,467,1013), XSPR_MASK, PPC403,      { RT } },
3187 { "mtdac1",  XSPR(31,467,1014), XSPR_MASK, PPC403,      { RT } },
3188 { "mtdac2",  XSPR(31,467,1015), XSPR_MASK, PPC403,      { RT } },
3189 { "mtdccr",  XSPR(31,467,1018), XSPR_MASK, PPC403,      { RT } },
3190 { "mticcr",  XSPR(31,467,1019), XSPR_MASK, PPC403,      { RT } },
3191 { "mtpbl1",  XSPR(31,467,1020), XSPR_MASK, PPC403,      { RT } },
3192 { "mtpbu1",  XSPR(31,467,1021), XSPR_MASK, PPC403,      { RT } },
3193 { "mtpbl2",  XSPR(31,467,1022), XSPR_MASK, PPC403,      { RT } },
3194 { "mtpbu2",  XSPR(31,467,1023), XSPR_MASK, PPC403,      { RT } },
3195 { "mtummcr0",   XSPR(31,467,936),  XSPR_MASK, PPC750,   { RT } },
3196 { "mtupmc1",    XSPR(31,467,937),  XSPR_MASK, PPC750,   { RT } },
3197 { "mtupmc2",    XSPR(31,467,938),  XSPR_MASK, PPC750,   { RT } },
3198 { "mtusia",     XSPR(31,467,939),  XSPR_MASK, PPC750,   { RT } },
3199 { "mtummcr1",   XSPR(31,467,940),  XSPR_MASK, PPC750,   { RT } },
3200 { "mtupmc3",    XSPR(31,467,941),  XSPR_MASK, PPC750,   { RT } },
3201 { "mtupmc4",    XSPR(31,467,942),  XSPR_MASK, PPC750,   { RT } },
3202 { "mtmmcr0",    XSPR(31,467,952),  XSPR_MASK, PPC750,   { RT } },
3203 { "mtpmc1",     XSPR(31,467,953),  XSPR_MASK, PPC750,   { RT } },
3204 { "mtpmc2",     XSPR(31,467,954),  XSPR_MASK, PPC750,   { RT } },
3205 { "mtsia",      XSPR(31,467,955),  XSPR_MASK, PPC750,   { RT } },
3206 { "mtmmcr1",    XSPR(31,467,956),  XSPR_MASK, PPC750,   { RT } },
3207 { "mtpmc3",     XSPR(31,467,957),  XSPR_MASK, PPC750,   { RT } },
3208 { "mtpmc4",     XSPR(31,467,958),  XSPR_MASK, PPC750,   { RT } },
3209 { "mtl2cr",     XSPR(31,467,1017), XSPR_MASK, PPC750,   { RT } },
3210 { "mtictc",     XSPR(31,467,1019), XSPR_MASK, PPC750,   { RT } },
3211 { "mtthrm1",    XSPR(31,467,1020), XSPR_MASK, PPC750,   { RT } },
3212 { "mtthrm2",    XSPR(31,467,1021), XSPR_MASK, PPC750,   { RT } },
3213 { "mtthrm3",    XSPR(31,467,1022), XSPR_MASK, PPC750,   { RT } },
3214 { "mtspr",   X(31,467),        X_MASK,       COM,       { SPR, RS } },
3215
3216 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
3217
3218 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
3219 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
3220
3221 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
3222
3223 { "dcread",  X(31,486), X_MASK,         PPC403,         { RT, RA, RB }},
3224
3225 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
3226 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3227 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
3228 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
3229 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3230 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
3231
3232 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3233 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3234 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3235 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3236
3237 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3238 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3239
3240 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3241 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3242 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3243 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3244
3245 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
3246
3247 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
3248
3249 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
3250
3251 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
3252
3253 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE,      { BF } },
3254
3255 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
3256
3257 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA, RB } },
3258 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
3259
3260 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA, RB } },
3261 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
3262
3263 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA, RB } },
3264
3265 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
3266 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
3267 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
3268 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
3269
3270 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
3271 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
3272
3273 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
3274 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
3275
3276 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
3277 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
3278
3279 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA, RB } },
3280
3281 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA, RB } },
3282
3283 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
3284
3285 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
3286
3287 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
3288
3289 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
3290
3291 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA, NB } },
3292 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA, NB } },
3293
3294 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPCONLY,      { 0 } },
3295 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
3296 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
3297 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
3298 { "msync",   X(31,598), 0xf80007fe,     BOOKE,          { 0 } },
3299
3300 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA, RB } },
3301
3302 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA, RB } },
3303
3304 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
3305
3306 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
3307
3308 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
3309
3310 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
3311
3312 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
3313
3314 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA, RB } },
3315 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA, RB } },
3316
3317 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA, RB } },
3318 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA, RB } },
3319
3320 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA, RB } },
3321
3322 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
3323 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
3324
3325 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
3326 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
3327
3328 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA, RB } },
3329
3330 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA, RB } },
3331
3332 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
3333
3334 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
3335 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
3336
3337 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
3338
3339 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA, NB } },
3340 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA, NB } },
3341
3342 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA, RB } },
3343
3344 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
3345 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
3346
3347 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
3348 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
3349
3350 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA, RB } },
3351
3352 { "dcba",    X(31,758), XRT_MASK,       PPC405,         { RA, RB } },
3353 { "dcba",    X(31,758), XRT_MASK,       BOOKE,          { RA, RB } },
3354
3355 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
3356
3357 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
3358 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
3359
3360 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
3361
3362 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
3363
3364 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
3365 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE,          { RA, RB } },
3366
3367 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA, RB } },
3368
3369 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
3370 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
3371 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
3372 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
3373
3374 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
3375 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
3376
3377 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA, RB } },
3378
3379 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA, RB } },
3380 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA, RB } },
3381
3382 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
3383
3384 { "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
3385 { "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { STRM } },
3386
3387 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
3388 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
3389 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
3390 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
3391
3392 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
3393
3394 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
3395 { "mbar",    X(31,854), 0xffffffff,     BOOKE,          { MO } },
3396
3397 { "tlbsx",   XRC(31,914,0), X_MASK,     PPC403,         { RT, RA, RB } },
3398 { "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403,         { RT, RA, RB } },
3399
3400 { "tlbsx",   XRC(31,914,0), X_MASK,     BOOKE,          { RA, RB } },
3401 { "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE,          { RA, RB } },
3402
3403 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
3404
3405 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA, RB } },
3406
3407 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
3408 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
3409
3410 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
3411 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
3412
3413 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
3414 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
3415 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
3416 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
3417
3418 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA, RB } },
3419
3420 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA, RB } },
3421
3422 { "tlbre",   X(31,946), X_MASK,         BOOKE,          { RT, RA, SH } },
3423
3424 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
3425 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
3426
3427 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
3428 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
3429
3430 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
3431 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
3432
3433 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3434
3435 { "iccci",   X(31,966), XRT_MASK,       PPC403,         { RA, RB } },
3436
3437 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
3438
3439 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
3440 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
3441 { "tlbwe",   X(31,978), X_MASK,         PPC403,         { RS, RA, SH } },
3442
3443 { "tlbwe",   X(31,978), X_MASK,         BOOKE,          { RT, RA, SH } },
3444
3445 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
3446
3447 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
3448
3449 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC,            { RA, RS } },
3450 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC,            { RA, RS } },
3451
3452 { "icread",  X(31,998), XRT_MASK,       PPC403,         { RA, RB } },
3453
3454 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
3455 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA, RB } },
3456
3457 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
3458
3459 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
3460 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
3461
3462 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
3463
3464 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
3465 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
3466 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
3467 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
3468 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
3469 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
3470 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
3471 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
3472 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
3473 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
3474 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
3475 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
3476
3477 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA } },
3478 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3479
3480 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
3481 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3482
3483 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA } },
3484
3485 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
3486
3487 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA } },
3488 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3489
3490 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
3491 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3492
3493 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA } },
3494
3495 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
3496
3497 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA } },
3498
3499 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
3500
3501 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA } },
3502
3503 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
3504
3505 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA } },
3506
3507 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
3508
3509 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
3510 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3511
3512 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA } },
3513 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3514
3515 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA } },
3516
3517 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
3518
3519 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA } },
3520
3521 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
3522
3523 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA } },
3524
3525 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
3526
3527 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA } },
3528
3529 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
3530
3531 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
3532
3533 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
3534
3535 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA } },
3536
3537 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
3538
3539 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA } },
3540
3541 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3542 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3543 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3544 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3545 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3546 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3547 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA } },
3548 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
3549 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA } },
3550 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
3551 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA } },
3552 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
3553 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA } },
3554 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
3555
3556 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3557 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3558
3559 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3560 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3561
3562 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3563 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3564
3565 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3566 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3567
3568 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3569 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3570
3571 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
3572 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
3573
3574 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3575 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3576
3577 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3578 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3579
3580 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3581 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3582
3583 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3584 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3585
3586 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
3587
3588 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
3589
3590 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA } },
3591
3592 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA } },
3593
3594 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA } },
3595
3596 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
3597
3598 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
3599 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
3600 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
3601 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
3602 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA } },
3603 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
3604 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
3605 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
3606 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
3607 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
3608
3609 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3610
3611 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
3612 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
3613
3614 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3615 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
3616 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3617 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
3618
3619 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3620 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
3621 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3622 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
3623
3624 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3625 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3626 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3627 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3628
3629 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3630 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3631 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3632 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3633
3634 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3635 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3636 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3637 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3638
3639 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
3640 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
3641
3642 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3643 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3644
3645 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
3646 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
3647 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
3648 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
3649
3650 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3651 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3652
3653 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3654 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3655 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3656 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3657
3658 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3659 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3660 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3661 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3662
3663 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3664 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3665 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3666 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3667
3668 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3669 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3670 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3671 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3672
3673 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3674
3675 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
3676 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
3677
3678 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
3679 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
3680
3681 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
3682
3683 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
3684 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
3685
3686 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
3687 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
3688
3689 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3690 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3691
3692 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
3693 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
3694
3695 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
3696 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
3697
3698 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
3699 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
3700
3701 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
3702 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
3703
3704 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3705 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3706
3707 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3708 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3709
3710 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3711 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3712
3713 };
3714
3715 const int powerpc_num_opcodes =
3716   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3717 \f
3718 /* The macro table.  This is only used by the assembler.  */
3719
3720 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3721    when x=0; 32-x when x is between 1 and 31; are negative if x is
3722    negative; and are 32 or more otherwise.  This is what you want
3723    when, for instance, you are emulating a right shift by a
3724    rotate-left-and-mask, because the underlying instructions support
3725    shifts of size 0 but not shifts of size 32.  By comparison, when
3726    extracting x bits from some word you want to use just 32-x, because
3727    the underlying instructions don't support extracting 0 bits but do
3728    support extracting the whole word (32 bits in this case).  */
3729
3730 const struct powerpc_macro powerpc_macros[] = {
3731 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
3732 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
3733 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
3734 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
3735 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
3736 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
3737 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
3738 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
3739 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
3740 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
3741 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
3742 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
3743 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
3744 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
3745 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
3746 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
3747
3748 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
3749 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
3750 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
3751 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
3752 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
3753 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
3754 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
3755 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
3756 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3757 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3758 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
3759 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
3760 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
3761 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
3762 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3763 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3764 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3765 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3766 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
3767 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
3768 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
3769 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
3770
3771 };
3772
3773 const int powerpc_num_macros =
3774   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);