opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
   3    2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
   4    Free Software Foundation, Inc.
   5    Written by Ian Lance Taylor, Cygnus Support
   6
   7    This file is part of the GNU opcodes library.
   8
   9    This library is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this file; see the file COPYING.  If not, write to the
  21    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "opcode/ppc.h"
  27 #include "opintl.h"
  28
  29 /* This file holds the PowerPC opcode table.  The opcode table
  30    includes almost all of the extended instruction mnemonics.  This
  31    permits the disassembler to use them, and simplifies the assembler
  32    logic, at the cost of increasing the table size.  The table is
  33    strictly constant data, so the compiler should be able to put it in
  34    the .text section.
  35
  36    This file also holds the operand table.  All knowledge about
  37    inserting operands into instructions and vice-versa is kept in this
  38    file.  */
  39 \f
  40 /* Local insertion and extraction functions.  */
  41
  42 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
  43 static long extract_arx (unsigned long, ppc_cpu_t, int *);
  44 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
  45 static long extract_ary (unsigned long, ppc_cpu_t, int *);
  46 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
  47 static long extract_bat (unsigned long, ppc_cpu_t, int *);
  48 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
  49 static long extract_bba (unsigned long, ppc_cpu_t, int *);
  50 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
  51 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
  52 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
  53 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
  54 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
  55 static long extract_bo (unsigned long, ppc_cpu_t, int *);
  56 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
  57 static long extract_boe (unsigned long, ppc_cpu_t, int *);
  58 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
  59 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
  60 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
  61 static long extract_li20 (unsigned long, ppc_cpu_t, int *);
  62 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
  63 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
  64 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
  65 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
  66 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
  67 static long extract_nb (unsigned long, ppc_cpu_t, int *);
  68 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
  69 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
  70 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
  71 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
  72 static long extract_oimm (unsigned long, ppc_cpu_t, int *);
  73 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
  74 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
  75 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
  76 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
  77 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
  78 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
  79 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
  80 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
  81 static long extract_rx (unsigned long, ppc_cpu_t, int *);
  82 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
  83 static long extract_ry (unsigned long, ppc_cpu_t, int *);
  84 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
  85 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
  86 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
  87 static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
  88 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
  89 static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
  90 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
  91 static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
  92 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
  93 static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
  94 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
  95 static long extract_spr (unsigned long, ppc_cpu_t, int *);
  96 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
  97 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
  98 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
  99 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
 100 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
 101 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
 102 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
 103 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
 104 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
 105 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
 106 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
 107 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
 108 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
 109 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
 110 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
 111 static long extract_dm (unsigned long, ppc_cpu_t, int *);
 112 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
 113 static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
 114 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
 115 static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
 116 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
 117 static long extract_vleui (unsigned long, ppc_cpu_t, int *);
 118 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
 119 static long extract_vleil (unsigned long, ppc_cpu_t, int *);
 120 \f
 121 /* The operands table.
 122
 123    The fields are bitm, shift, insert, extract, flags.
 124
 125    We used to put parens around the various additions, like the one
 126    for BA just below.  However, that caused trouble with feeble
 127    compilers with a limit on depth of a parenthesized expression, like
 128    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
 129    omit the parens, since the macros are never used in a context where
 130    the addition will be ambiguous.  */
 131
 132 const struct powerpc_operand powerpc_operands[] =
 133 {
 134   /* The zero index is used to indicate the end of the list of
 135      operands.  */
 136 #define UNUSED 0
 137   { 0, 0, NULL, NULL, 0 },
 138
 139   /* The BA field in an XL form instruction.  */
 140 #define BA UNUSED + 1
 141   /* The BI field in a B form or XL form instruction.  */
 142 #define BI BA
 143 #define BI_MASK (0x1f << 16)
 144   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
 145
 146   /* The BA field in an XL form instruction when it must be the same
 147      as the BT field in the same instruction.  */
 148 #define BAT BA + 1
 149   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 150
 151   /* The BB field in an XL form instruction.  */
 152 #define BB BAT + 1
 153 #define BB_MASK (0x1f << 11)
 154   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
 155
 156   /* The BB field in an XL form instruction when it must be the same
 157      as the BA field in the same instruction.  */
 158 #define BBA BB + 1
 159   /* The VB field in a VX form instruction when it must be the same
 160      as the VA field in the same instruction.  */
 161 #define VBA BBA
 162   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 163
 164   /* The BD field in a B form instruction.  The lower two bits are
 165      forced to zero.  */
 166 #define BD BBA + 1
 167   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 168
 169   /* The BD field in a B form instruction when absolute addressing is
 170      used.  */
 171 #define BDA BD + 1
 172   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 173
 174   /* The BD field in a B form instruction when the - modifier is used.
 175      This sets the y bit of the BO field appropriately.  */
 176 #define BDM BDA + 1
 177   { 0xfffc, 0, insert_bdm, extract_bdm,
 178       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 179
 180   /* The BD field in a B form instruction when the - modifier is used
 181      and absolute address is used.  */
 182 #define BDMA BDM + 1
 183   { 0xfffc, 0, insert_bdm, extract_bdm,
 184       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 185
 186   /* The BD field in a B form instruction when the + modifier is used.
 187      This sets the y bit of the BO field appropriately.  */
 188 #define BDP BDMA + 1
 189   { 0xfffc, 0, insert_bdp, extract_bdp,
 190       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 191
 192   /* The BD field in a B form instruction when the + modifier is used
 193      and absolute addressing is used.  */
 194 #define BDPA BDP + 1
 195   { 0xfffc, 0, insert_bdp, extract_bdp,
 196       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 197
 198   /* The BF field in an X or XL form instruction.  */
 199 #define BF BDPA + 1
 200   /* The CRFD field in an X form instruction.  */
 201 #define CRFD BF
 202   /* The CRD field in an XL form instruction.  */
 203 #define CRD BF
 204   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
 205
 206   /* The BF field in an X or XL form instruction.  */
 207 #define BFF BF + 1
 208   { 0x7, 23, NULL, NULL, 0 },
 209
 210   /* An optional BF field.  This is used for comparison instructions,
 211      in which an omitted BF field is taken as zero.  */
 212 #define OBF BFF + 1
 213   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 214
 215   /* The BFA field in an X or XL form instruction.  */
 216 #define BFA OBF + 1
 217   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
 218
 219   /* The BO field in a B form instruction.  Certain values are
 220      illegal.  */
 221 #define BO BFA + 1
 222 #define BO_MASK (0x1f << 21)
 223   { 0x1f, 21, insert_bo, extract_bo, 0 },
 224
 225   /* The BO field in a B form instruction when the + or - modifier is
 226      used.  This is like the BO field, but it must be even.  */
 227 #define BOE BO + 1
 228   { 0x1e, 21, insert_boe, extract_boe, 0 },
 229
 230 #define BH BOE + 1
 231   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 232
 233   /* The BT field in an X or XL form instruction.  */
 234 #define BT BH + 1
 235   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
 236
 237   /* The BI16 field in a BD8 form instruction.  */
 238 #define BI16 BT + 1
 239   { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
 240
 241   /* The BI32 field in a BD15 form instruction.  */
 242 #define BI32 BI16 + 1
 243   { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
 244
 245   /* The BO32 field in a BD15 form instruction.  */
 246 #define BO32 BI32 + 1
 247   { 0x3, 20, NULL, NULL, 0 },
 248
 249   /* The B8 field in a BD8 form instruction.  */
 250 #define B8 BO32 + 1
 251   { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 252
 253   /* The B15 field in a BD15 form instruction.  The lowest bit is
 254      forced to zero.  */
 255 #define B15 B8 + 1
 256   { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 257
 258   /* The B24 field in a BD24 form instruction.  The lowest bit is
 259      forced to zero.  */
 260 #define B24 B15 + 1
 261   { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 262
 263   /* The condition register number portion of the BI field in a B form
 264      or XL form instruction.  This is used for the extended
 265      conditional branch mnemonics, which set the lower two bits of the
 266      BI field.  This field is optional.  */
 267 #define CR B24 + 1
 268   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 269
 270   /* The CRB field in an X form instruction.  */
 271 #define CRB CR + 1
 272   /* The MB field in an M form instruction.  */
 273 #define MB CRB
 274 #define MB_MASK (0x1f << 6)
 275   { 0x1f, 6, NULL, NULL, 0 },
 276
 277   /* The CRD32 field in an XL form instruction.  */
 278 #define CRD32 CRB + 1
 279   { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
 280
 281   /* The CRFS field in an X form instruction.  */
 282 #define CRFS CRD32 + 1
 283   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
 284
 285 #define CRS CRFS + 1
 286   { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 287
 288   /* The CT field in an X form instruction.  */
 289 #define CT CRS + 1
 290   /* The MO field in an mbar instruction.  */
 291 #define MO CT
 292   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 293
 294   /* The D field in a D form instruction.  This is a displacement off
 295      a register, and implies that the next operand is a register in
 296      parentheses.  */
 297 #define D CT + 1
 298   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 299
 300   /* The D8 field in a D form instruction.  This is a displacement off
 301      a register, and implies that the next operand is a register in
 302      parentheses.  */
 303 #define D8 D + 1
 304   { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 305
 306   /* The DQ field in a DQ form instruction.  This is like D, but the
 307      lower four bits are forced to zero. */
 308 #define DQ D8 + 1
 309   { 0xfff0, 0, NULL, NULL,
 310     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 311
 312   /* The DS field in a DS form instruction.  This is like D, but the
 313      lower two bits are forced to zero.  */
 314 #define DS DQ + 1
 315   { 0xfffc, 0, NULL, NULL,
 316     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 317
 318   /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
 319 #define DUIS DS + 1
 320   { 0x3ff, 11, NULL, NULL, 0 },
 321
 322   /* The E field in a wrteei instruction.  */
 323   /* And the W bit in the pair singles instructions.  */
 324 #define E DUIS + 1
 325 #define PSW E
 326   { 0x1, 15, NULL, NULL, 0 },
 327
 328   /* The FL1 field in a POWER SC form instruction.  */
 329 #define FL1 E + 1
 330   /* The U field in an X form instruction.  */
 331 #define U FL1
 332   { 0xf, 12, NULL, NULL, 0 },
 333
 334   /* The FL2 field in a POWER SC form instruction.  */
 335 #define FL2 FL1 + 1
 336   { 0x7, 2, NULL, NULL, 0 },
 337
 338   /* The FLM field in an XFL form instruction.  */
 339 #define FLM FL2 + 1
 340   { 0xff, 17, NULL, NULL, 0 },
 341
 342   /* The FRA field in an X or A form instruction.  */
 343 #define FRA FLM + 1
 344 #define FRA_MASK (0x1f << 16)
 345   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
 346
 347   /* The FRAp field of DFP instructions.  */
 348 #define FRAp FRA + 1
 349   { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
 350
 351   /* The FRB field in an X or A form instruction.  */
 352 #define FRB FRAp + 1
 353 #define FRB_MASK (0x1f << 11)
 354   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
 355
 356   /* The FRBp field of DFP instructions.  */
 357 #define FRBp FRB + 1
 358   { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
 359
 360   /* The FRC field in an A form instruction.  */
 361 #define FRC FRBp + 1
 362 #define FRC_MASK (0x1f << 6)
 363   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
 364
 365   /* The FRS field in an X form instruction or the FRT field in a D, X
 366      or A form instruction.  */
 367 #define FRS FRC + 1
 368 #define FRT FRS
 369   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
 370
 371   /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
 372      instructions.  */
 373 #define FRSp FRS + 1
 374 #define FRTp FRSp
 375   { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
 376
 377   /* The FXM field in an XFX instruction.  */
 378 #define FXM FRSp + 1
 379   { 0xff, 12, insert_fxm, extract_fxm, 0 },
 380
 381   /* Power4 version for mfcr.  */
 382 #define FXM4 FXM + 1
 383   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 384
 385   /* The IMM20 field in an LI instruction.  */
 386 #define IMM20 FXM4 + 1
 387   { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
 388
 389   /* The L field in a D or X form instruction.  */
 390 #define L IMM20 + 1
 391   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 392
 393   /* The LEV field in a POWER SVC form instruction.  */
 394 #define SVC_LEV L + 1
 395   { 0x7f, 5, NULL, NULL, 0 },
 396
 397   /* The LEV field in an SC form instruction.  */
 398 #define LEV SVC_LEV + 1
 399   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
 400
 401   /* The LI field in an I form instruction.  The lower two bits are
 402      forced to zero.  */
 403 #define LI LEV + 1
 404   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 405
 406   /* The LI field in an I form instruction when used as an absolute
 407      address.  */
 408 #define LIA LI + 1
 409   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 410
 411   /* The LS or WC field in an X (sync or wait) form instruction.  */
 412 #define LS LIA + 1
 413 #define WC LS
 414   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 415
 416   /* The ME field in an M form instruction.  */
 417 #define ME LS + 1
 418 #define ME_MASK (0x1f << 1)
 419   { 0x1f, 1, NULL, NULL, 0 },
 420
 421   /* The MB and ME fields in an M form instruction expressed a single
 422      operand which is a bitmask indicating which bits to select.  This
 423      is a two operand form using PPC_OPERAND_NEXT.  See the
 424      description in opcode/ppc.h for what this means.  */
 425 #define MBE ME + 1
 426   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 427   { -1, 0, insert_mbe, extract_mbe, 0 },
 428
 429   /* The MB or ME field in an MD or MDS form instruction.  The high
 430      bit is wrapped to the low end.  */
 431 #define MB6 MBE + 2
 432 #define ME6 MB6
 433 #define MB6_MASK (0x3f << 5)
 434   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
 435
 436   /* The NB field in an X form instruction.  The value 32 is stored as
 437      0.  */
 438 #define NB MB6 + 1
 439   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
 440
 441   /* The NBI field in an lswi instruction, which has special value
 442      restrictions.  The value 32 is stored as 0.  */
 443 #define NBI NB + 1
 444   { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
 445
 446   /* The NSI field in a D form instruction.  This is the same as the
 447      SI field, only negated.  */
 448 #define NSI NBI + 1
 449   { 0xffff, 0, insert_nsi, extract_nsi,
 450       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 451
 452   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 453 #define RA NSI + 1
 454 #define RA_MASK (0x1f << 16)
 455   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
 456
 457   /* As above, but 0 in the RA field means zero, not r0.  */
 458 #define RA0 RA + 1
 459   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 460
 461   /* The RA field in the DQ form lq or an lswx instruction, which have special
 462      value restrictions.  */
 463 #define RAQ RA0 + 1
 464 #define RAX RAQ
 465   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 466
 467   /* The RA field in a D or X form instruction which is an updating
 468      load, which means that the RA field may not be zero and may not
 469      equal the RT field.  */
 470 #define RAL RAQ + 1
 471   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 472
 473   /* The RA field in an lmw instruction, which has special value
 474      restrictions.  */
 475 #define RAM RAL + 1
 476   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 477
 478   /* The RA field in a D or X form instruction which is an updating
 479      store or an updating floating point load, which means that the RA
 480      field may not be zero.  */
 481 #define RAS RAM + 1
 482   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 483
 484   /* The RA field of the tlbwe, dccci and iccci instructions,
 485      which are optional.  */
 486 #define RAOPT RAS + 1
 487   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 488
 489   /* The RB field in an X, XO, M, or MDS form instruction.  */
 490 #define RB RAOPT + 1
 491 #define RB_MASK (0x1f << 11)
 492   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
 493
 494   /* The RB field in an X form instruction when it must be the same as
 495      the RS field in the instruction.  This is used for extended
 496      mnemonics like mr.  */
 497 #define RBS RB + 1
 498   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 499
 500   /* The RB field in an lswx instruction, which has special value
 501      restrictions.  */
 502 #define RBX RBS + 1
 503   { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
 504
 505   /* The RB field of the dccci and iccci instructions, which are optional.  */
 506 #define RBOPT RBX + 1
 507   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 508
 509   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 510      instruction or the RT field in a D, DS, X, XFX or XO form
 511      instruction.  */
 512 #define RS RBOPT + 1
 513 #define RT RS
 514 #define RT_MASK (0x1f << 21)
 515 #define RD RS
 516   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 517
 518   /* The RS and RT fields of the DS form stq and DQ form lq instructions,
 519      which have special value restrictions.  */
 520 #define RSQ RS + 1
 521 #define RTQ RSQ
 522   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
 523
 524   /* The RS field of the tlbwe instruction, which is optional.  */
 525 #define RSO RSQ + 1
 526 #define RTO RSO
 527   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 528
 529   /* The RX field of the SE_RR form instruction.  */
 530 #define RX RSO + 1
 531   { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
 532
 533   /* The ARX field of the SE_RR form instruction.  */
 534 #define ARX RX + 1
 535   { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
 536
 537   /* The RY field of the SE_RR form instruction.  */
 538 #define RY ARX + 1
 539 #define RZ RY
 540   { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
 541
 542   /* The ARY field of the SE_RR form instruction.  */
 543 #define ARY RY + 1
 544   { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
 545
 546   /* The SCLSCI8 field in a D form instruction.  */
 547 #define SCLSCI8 ARY + 1
 548   { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
 549
 550   /* The SCLSCI8N field in a D form instruction.  This is the same as the
 551      SCLSCI8 field, only negated.  */
 552 #define SCLSCI8N SCLSCI8 + 1
 553   { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
 554       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 555
 556   /* The SD field of the SD4 form instruction.  */
 557 #define SE_SD SCLSCI8N + 1
 558   { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
 559
 560   /* The SD field of the SD4 form instruction, for halfword.  */
 561 #define SE_SDH SE_SD + 1
 562   { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
 563
 564   /* The SD field of the SD4 form instruction, for word.  */
 565 #define SE_SDW SE_SDH + 1
 566   { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
 567
 568   /* The SH field in an X or M form instruction.  */
 569 #define SH SE_SDW + 1
 570 #define SH_MASK (0x1f << 11)
 571   /* The other UIMM field in a EVX form instruction.  */
 572 #define EVUIMM SH
 573   { 0x1f, 11, NULL, NULL, 0 },
 574
 575   /* The SH field in an MD form instruction.  This is split.  */
 576 #define SH6 SH + 1
 577 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 578   { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
 579
 580   /* The SH field of the tlbwe instruction, which is optional.  */
 581 #define SHO SH6 + 1
 582   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 583
 584   /* The SI field in a D form instruction.  */
 585 #define SI SHO + 1
 586   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 587
 588   /* The SI field in a D form instruction when we accept a wide range
 589      of positive values.  */
 590 #define SISIGNOPT SI + 1
 591   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 592
 593   /* The SI8 field in a D form instruction.  */
 594 #define SI8 SISIGNOPT + 1
 595   { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 596
 597   /* The SPR field in an XFX form instruction.  This is flipped--the
 598      lower 5 bits are stored in the upper 5 and vice- versa.  */
 599 #define SPR SI8 + 1
 600 #define PMR SPR
 601 #define TMR SPR
 602 #define SPR_MASK (0x3ff << 11)
 603   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 604
 605   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 606 #define SPRBAT SPR + 1
 607 #define SPRBAT_MASK (0x3 << 17)
 608   { 0x3, 17, NULL, NULL, 0 },
 609
 610   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 611 #define SPRG SPRBAT + 1
 612   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
 613
 614   /* The SR field in an X form instruction.  */
 615 #define SR SPRG + 1
 616   /* The 4-bit UIMM field in a VX form instruction.  */
 617 #define UIMM4 SR
 618   { 0xf, 16, NULL, NULL, 0 },
 619
 620   /* The STRM field in an X AltiVec form instruction.  */
 621 #define STRM SR + 1
 622   /* The T field in a tlbilx form instruction.  */
 623 #define T STRM
 624   { 0x3, 21, NULL, NULL, 0 },
 625
 626   /* The ESYNC field in an X (sync) form instruction.  */
 627 #define ESYNC STRM + 1
 628   { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
 629
 630   /* The SV field in a POWER SC form instruction.  */
 631 #define SV ESYNC + 1
 632   { 0x3fff, 2, NULL, NULL, 0 },
 633
 634   /* The TBR field in an XFX form instruction.  This is like the SPR
 635      field, but it is optional.  */
 636 #define TBR SV + 1
 637   { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 638
 639   /* The TO field in a D or X form instruction.  */
 640 #define TO TBR + 1
 641 #define DUI TO
 642 #define TO_MASK (0x1f << 21)
 643   { 0x1f, 21, NULL, NULL, 0 },
 644
 645   /* The UI field in a D form instruction.  */
 646 #define UI TO + 1
 647   { 0xffff, 0, NULL, NULL, 0 },
 648
 649   /* The IMM field in an SE_IM5 instruction.  */
 650 #define UI5 UI + 1
 651   { 0x1f, 4, NULL, NULL, 0 },
 652
 653   /* The OIMM field in an SE_OIM5 instruction.  */
 654 #define OIMM5 UI5 + 1
 655   { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
 656
 657   /* The UI7 field in an SE_LI instruction.  */
 658 #define UI7 OIMM5 + 1
 659   { 0x7f, 4, NULL, NULL, 0 },
 660
 661   /* The VA field in a VA, VX or VXR form instruction.  */
 662 #define VA UI7 + 1
 663   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 664
 665   /* The VB field in a VA, VX or VXR form instruction.  */
 666 #define VB VA + 1
 667   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
 668
 669   /* The VC field in a VA form instruction.  */
 670 #define VC VB + 1
 671   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
 672
 673   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 674 #define VD VC + 1
 675 #define VS VD
 676   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
 677
 678   /* The SIMM field in a VX form instruction, and TE in Z form.  */
 679 #define SIMM VD + 1
 680 #define TE SIMM
 681   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 682
 683   /* The UIMM field in a VX form instruction.  */
 684 #define UIMM SIMM + 1
 685 #define DCTL UIMM
 686   { 0x1f, 16, NULL, NULL, 0 },
 687
 688   /* The 3-bit UIMM field in a VX form instruction.  */
 689 #define UIMM3 UIMM + 1
 690   { 0x7, 16, NULL, NULL, 0 },
 691
 692   /* The SHB field in a VA form instruction.  */
 693 #define SHB UIMM3 + 1
 694   { 0xf, 6, NULL, NULL, 0 },
 695
 696   /* The other UIMM field in a half word EVX form instruction.  */
 697 #define EVUIMM_2 SHB + 1
 698   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
 699
 700   /* The other UIMM field in a word EVX form instruction.  */
 701 #define EVUIMM_4 EVUIMM_2 + 1
 702   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
 703
 704   /* The other UIMM field in a double EVX form instruction.  */
 705 #define EVUIMM_8 EVUIMM_4 + 1
 706   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 707
 708   /* The WS field.  */
 709 #define WS EVUIMM_8 + 1
 710   { 0x7, 11, NULL, NULL, 0 },
 711
 712   /* PowerPC paired singles extensions.  */
 713   /* W bit in the pair singles instructions for x type instructions.  */
 714 #define PSWM WS + 1
 715   /* The BO16 field in a BD8 form instruction.  */
 716 #define BO16 PSWM
 717   {  0x1, 10, 0, 0, 0 },
 718
 719   /* IDX bits for quantization in the pair singles instructions.  */
 720 #define PSQ PSWM + 1
 721   {  0x7, 12, 0, 0, 0 },
 722
 723   /* IDX bits for quantization in the pair singles x-type instructions.  */
 724 #define PSQM PSQ + 1
 725   {  0x7, 7, 0, 0, 0 },
 726
 727   /* Smaller D field for quantization in the pair singles instructions.  */
 728 #define PSD PSQM + 1
 729   {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 730
 731 #define A_L PSD + 1
 732 #define W A_L
 733 #define MTMSRD_L W
 734   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 735
 736 #define RMC MTMSRD_L + 1
 737   { 0x3, 9, NULL, NULL, 0 },
 738
 739 #define R RMC + 1
 740   { 0x1, 16, NULL, NULL, 0 },
 741
 742 #define SP R + 1
 743   { 0x3, 19, NULL, NULL, 0 },
 744
 745 #define S SP + 1
 746   { 0x1, 20, NULL, NULL, 0 },
 747
 748   /* SH field starting at bit position 16.  */
 749 #define SH16 S + 1
 750   /* The DCM and DGM fields in a Z form instruction.  */
 751 #define DCM SH16
 752 #define DGM DCM
 753   { 0x3f, 10, NULL, NULL, 0 },
 754
 755   /* The EH field in larx instruction.  */
 756 #define EH SH16 + 1
 757   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 758
 759   /* The L field in an mtfsf or XFL form instruction.  */
 760 #define XFL_L EH + 1
 761   { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
 762
 763   /* Xilinx APU related masks and macros */
 764 #define FCRT XFL_L + 1
 765 #define FCRT_MASK (0x1f << 21)
 766   { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
 767
 768   /* Xilinx FSL related masks and macros */
 769 #define FSL FCRT + 1
 770 #define FSL_MASK (0x1f << 11)
 771   { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
 772
 773   /* Xilinx UDI related masks and macros */
 774 #define URT FSL + 1
 775   { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
 776
 777 #define URA URT + 1
 778   { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
 779
 780 #define URB URA + 1
 781   { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
 782
 783 #define URC URB + 1
 784   { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
 785
 786   /* The VLESIMM field in a D form instruction.  */
 787 #define VLESIMM URC + 1
 788   { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
 789       PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 790
 791   /* The VLENSIMM field in a D form instruction.  */
 792 #define VLENSIMM VLESIMM + 1
 793   { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
 794       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 795
 796   /* The VLEUIMM field in a D form instruction.  */
 797 #define VLEUIMM VLENSIMM + 1
 798   { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
 799
 800   /* The VLEUIMML field in a D form instruction.  */
 801 #define VLEUIMML VLEUIMM + 1
 802   { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
 803
 804   /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
 805 #define XS6 VLEUIMML + 1
 806 #define XT6 XS6
 807   { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
 808
 809   /* The XA field in an XX3 form instruction.  This is split.  */
 810 #define XA6 XT6 + 1
 811   { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
 812
 813   /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
 814 #define XB6 XA6 + 1
 815   { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
 816
 817   /* The XB field in an XX3 form instruction when it must be the same as
 818      the XA field in the instruction.  This is used in extended mnemonics
 819      like xvmovdp.  This is split.  */
 820 #define XB6S XB6 + 1
 821   { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
 822
 823   /* The XC field in an XX4 form instruction.  This is split.  */
 824 #define XC6 XB6S + 1
 825   { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
 826
 827   /* The DM or SHW field in an XX3 form instruction.  */
 828 #define DM XC6 + 1
 829 #define SHW DM
 830   { 0x3, 8, NULL, NULL, 0 },
 831
 832   /* The DM field in an extended mnemonic XX3 form instruction.  */
 833 #define DMEX DM + 1
 834   { 0x3, 8, insert_dm, extract_dm, 0 },
 835
 836   /* The UIM field in an XX2 form instruction.  */
 837 #define UIM DMEX + 1
 838   /* The 2-bit UIMM field in a VX form instruction.  */
 839 #define UIMM2 UIM
 840   { 0x3, 16, NULL, NULL, 0 },
 841
 842 #define ERAT_T UIM + 1
 843   { 0x7, 21, NULL, NULL, 0 },
 844 };
 845
 846 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 847                                            / sizeof (powerpc_operands[0]));
 848
 849 /* The functions used to insert and extract complicated operands.  */
 850
 851 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs.  */
 852
 853 static unsigned long
 854 insert_arx (unsigned long insn,
 855             long value,
 856             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 857             const char **errmsg ATTRIBUTE_UNUSED)
 858 {
 859   if (value >= 8 && value < 24)
 860     return insn | ((value - 8) & 0xf);
 861   else
 862     {
 863       *errmsg = _("invalid register");
 864       return 0;
 865     }
 866 }
 867
 868 static long
 869 extract_arx (unsigned long insn,
 870              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 871              int *invalid ATTRIBUTE_UNUSED)
 872 {
 873   return (insn & 0xf) + 8;
 874 }
 875
 876 static unsigned long
 877 insert_ary (unsigned long insn,
 878             long value,
 879             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 880             const char **errmsg ATTRIBUTE_UNUSED)
 881 {
 882   if (value >= 8 && value < 24)
 883     return insn | (((value - 8) & 0xf) << 4);
 884   else
 885     {
 886       *errmsg = _("invalid register");
 887       return 0;
 888     }
 889 }
 890
 891 static long
 892 extract_ary (unsigned long insn,
 893              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 894              int *invalid ATTRIBUTE_UNUSED)
 895 {
 896   return ((insn >> 4) & 0xf) + 8;
 897 }
 898
 899 static unsigned long
 900 insert_rx (unsigned long insn,
 901            long value,
 902            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 903            const char **errmsg)
 904 {
 905   if (value >= 0 && value < 8)
 906     return insn | value;
 907   else if (value >= 24 && value <= 31)
 908     return insn | (value - 16);
 909   else
 910     {
 911       *errmsg = _("invalid register");
 912       return 0;
 913     }
 914 }
 915
 916 static long
 917 extract_rx (unsigned long insn,
 918             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 919             int *invalid ATTRIBUTE_UNUSED)
 920 {
 921   int value = insn & 0xf;
 922   if (value >= 0 && value < 8)
 923     return value;
 924   else
 925     return value + 16;
 926 }
 927
 928 static unsigned long
 929 insert_ry (unsigned long insn,
 930            long value,
 931            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 932            const char **errmsg)
 933 {
 934   if (value >= 0 && value < 8)
 935     return insn | (value << 4);
 936   else if (value >= 24 && value <= 31)
 937     return insn | ((value - 16) << 4);
 938   else
 939     {
 940       *errmsg = _("invalid register");
 941       return 0;
 942     }
 943 }
 944
 945 static long
 946 extract_ry (unsigned long insn,
 947             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 948             int *invalid ATTRIBUTE_UNUSED)
 949 {
 950   int value = (insn >> 4) & 0xf;
 951   if (value >= 0 && value < 8)
 952     return value;
 953   else
 954     return value + 16;
 955 }
 956
 957 /* The BA field in an XL form instruction when it must be the same as
 958    the BT field in the same instruction.  This operand is marked FAKE.
 959    The insertion function just copies the BT field into the BA field,
 960    and the extraction function just checks that the fields are the
 961    same.  */
 962
 963 static unsigned long
 964 insert_bat (unsigned long insn,
 965             long value ATTRIBUTE_UNUSED,
 966             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 967             const char **errmsg ATTRIBUTE_UNUSED)
 968 {
 969   return insn | (((insn >> 21) & 0x1f) << 16);
 970 }
 971
 972 static long
 973 extract_bat (unsigned long insn,
 974              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 975              int *invalid)
 976 {
 977   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 978     *invalid = 1;
 979   return 0;
 980 }
 981
 982 /* The BB field in an XL form instruction when it must be the same as
 983    the BA field in the same instruction.  This operand is marked FAKE.
 984    The insertion function just copies the BA field into the BB field,
 985    and the extraction function just checks that the fields are the
 986    same.  */
 987
 988 static unsigned long
 989 insert_bba (unsigned long insn,
 990             long value ATTRIBUTE_UNUSED,
 991             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 992             const char **errmsg ATTRIBUTE_UNUSED)
 993 {
 994   return insn | (((insn >> 16) & 0x1f) << 11);
 995 }
 996
 997 static long
 998 extract_bba (unsigned long insn,
 999              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1000              int *invalid)
1001 {
1002   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1003     *invalid = 1;
1004   return 0;
1005 }
1006
1007 /* The BD field in a B form instruction when the - modifier is used.
1008    This modifier means that the branch is not expected to be taken.
1009    For chips built to versions of the architecture prior to version 2
1010    (ie. not Power4 compatible), we set the y bit of the BO field to 1
1011    if the offset is negative.  When extracting, we require that the y
1012    bit be 1 and that the offset be positive, since if the y bit is 0
1013    we just want to print the normal form of the instruction.
1014    Power4 compatible targets use two bits, "a", and "t", instead of
1015    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
1016    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
1017    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1018    for branch on CTR.  We only handle the taken/not-taken hint here.
1019    Note that we don't relax the conditions tested here when
1020    disassembling with -Many because insns using extract_bdm and
1021    extract_bdp always occur in pairs.  One or the other will always
1022    be valid.  */
1023
1024 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1025
1026 static unsigned long
1027 insert_bdm (unsigned long insn,
1028             long value,
1029             ppc_cpu_t dialect,
1030             const char **errmsg ATTRIBUTE_UNUSED)
1031 {
1032   if ((dialect & ISA_V2) == 0)
1033     {
1034       if ((value & 0x8000) != 0)
1035         insn |= 1 << 21;
1036     }
1037   else
1038     {
1039       if ((insn & (0x14 << 21)) == (0x04 << 21))
1040         insn |= 0x02 << 21;
1041       else if ((insn & (0x14 << 21)) == (0x10 << 21))
1042         insn |= 0x08 << 21;
1043     }
1044   return insn | (value & 0xfffc);
1045 }
1046
1047 static long
1048 extract_bdm (unsigned long insn,
1049              ppc_cpu_t dialect,
1050              int *invalid)
1051 {
1052   if ((dialect & ISA_V2) == 0)
1053     {
1054       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1055         *invalid = 1;
1056     }
1057   else
1058     {
1059       if ((insn & (0x17 << 21)) != (0x06 << 21)
1060           && (insn & (0x1d << 21)) != (0x18 << 21))
1061         *invalid = 1;
1062     }
1063
1064   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1065 }
1066
1067 /* The BD field in a B form instruction when the + modifier is used.
1068    This is like BDM, above, except that the branch is expected to be
1069    taken.  */
1070
1071 static unsigned long
1072 insert_bdp (unsigned long insn,
1073             long value,
1074             ppc_cpu_t dialect,
1075             const char **errmsg ATTRIBUTE_UNUSED)
1076 {
1077   if ((dialect & ISA_V2) == 0)
1078     {
1079       if ((value & 0x8000) == 0)
1080         insn |= 1 << 21;
1081     }
1082   else
1083     {
1084       if ((insn & (0x14 << 21)) == (0x04 << 21))
1085         insn |= 0x03 << 21;
1086       else if ((insn & (0x14 << 21)) == (0x10 << 21))
1087         insn |= 0x09 << 21;
1088     }
1089   return insn | (value & 0xfffc);
1090 }
1091
1092 static long
1093 extract_bdp (unsigned long insn,
1094              ppc_cpu_t dialect,
1095              int *invalid)
1096 {
1097   if ((dialect & ISA_V2) == 0)
1098     {
1099       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1100         *invalid = 1;
1101     }
1102   else
1103     {
1104       if ((insn & (0x17 << 21)) != (0x07 << 21)
1105           && (insn & (0x1d << 21)) != (0x19 << 21))
1106         *invalid = 1;
1107     }
1108
1109   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1110 }
1111
1112 static inline int
1113 valid_bo_pre_v2 (long value)
1114 {
1115   /* Certain encodings have bits that are required to be zero.
1116      These are (z must be zero, y may be anything):
1117          0000y
1118          0001y
1119          001zy
1120          0100y
1121          0101y
1122          011zy
1123          1z00y
1124          1z01y
1125          1z1zz
1126   */
1127   if ((value & 0x14) == 0)
1128     return 1;
1129   else if ((value & 0x14) == 0x4)
1130     return (value & 0x2) == 0;
1131   else if ((value & 0x14) == 0x10)
1132     return (value & 0x8) == 0;
1133   else
1134     return value == 0x14;
1135 }
1136
1137 static inline int
1138 valid_bo_post_v2 (long value)
1139 {
1140   /* Certain encodings have bits that are required to be zero.
1141      These are (z must be zero, a & t may be anything):
1142          0000z
1143          0001z
1144          001at
1145          0100z
1146          0101z
1147          011at
1148          1a00t
1149          1a01t
1150          1z1zz
1151   */
1152   if ((value & 0x14) == 0)
1153     return (value & 0x1) == 0;
1154   else if ((value & 0x14) == 0x14)
1155     return value == 0x14;
1156   else
1157     return 1;
1158 }
1159
1160 /* Check for legal values of a BO field.  */
1161
1162 static int
1163 valid_bo (long value, ppc_cpu_t dialect, int extract)
1164 {
1165   int valid_y = valid_bo_pre_v2 (value);
1166   int valid_at = valid_bo_post_v2 (value);
1167
1168   /* When disassembling with -Many, accept either encoding on the
1169      second pass through opcodes.  */
1170   if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1171     return valid_y || valid_at;
1172   if ((dialect & ISA_V2) == 0)
1173     return valid_y;
1174   else
1175     return valid_at;
1176 }
1177
1178 /* The BO field in a B form instruction.  Warn about attempts to set
1179    the field to an illegal value.  */
1180
1181 static unsigned long
1182 insert_bo (unsigned long insn,
1183            long value,
1184            ppc_cpu_t dialect,
1185            const char **errmsg)
1186 {
1187   if (!valid_bo (value, dialect, 0))
1188     *errmsg = _("invalid conditional option");
1189   else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1190     *errmsg = _("invalid counter access");
1191   return insn | ((value & 0x1f) << 21);
1192 }
1193
1194 static long
1195 extract_bo (unsigned long insn,
1196             ppc_cpu_t dialect,
1197             int *invalid)
1198 {
1199   long value;
1200
1201   value = (insn >> 21) & 0x1f;
1202   if (!valid_bo (value, dialect, 1))
1203     *invalid = 1;
1204   return value;
1205 }
1206
1207 /* The BO field in a B form instruction when the + or - modifier is
1208    used.  This is like the BO field, but it must be even.  When
1209    extracting it, we force it to be even.  */
1210
1211 static unsigned long
1212 insert_boe (unsigned long insn,
1213             long value,
1214             ppc_cpu_t dialect,
1215             const char **errmsg)
1216 {
1217   if (!valid_bo (value, dialect, 0))
1218     *errmsg = _("invalid conditional option");
1219   else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1220     *errmsg = _("invalid counter access");
1221   else if ((value & 1) != 0)
1222     *errmsg = _("attempt to set y bit when using + or - modifier");
1223
1224   return insn | ((value & 0x1f) << 21);
1225 }
1226
1227 static long
1228 extract_boe (unsigned long insn,
1229              ppc_cpu_t dialect,
1230              int *invalid)
1231 {
1232   long value;
1233
1234   value = (insn >> 21) & 0x1f;
1235   if (!valid_bo (value, dialect, 1))
1236     *invalid = 1;
1237   return value & 0x1e;
1238 }
1239
1240 /* FXM mask in mfcr and mtcrf instructions.  */
1241
1242 static unsigned long
1243 insert_fxm (unsigned long insn,
1244             long value,
1245             ppc_cpu_t dialect,
1246             const char **errmsg)
1247 {
1248   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1249      one bit of the mask field is set.  */
1250   if ((insn & (1 << 20)) != 0)
1251     {
1252       if (value == 0 || (value & -value) != value)
1253         {
1254           *errmsg = _("invalid mask field");
1255           value = 0;
1256         }
1257     }
1258
1259   /* If the optional field on mfcr is missing that means we want to use
1260      the old form of the instruction that moves the whole cr.  In that
1261      case we'll have VALUE zero.  There doesn't seem to be a way to
1262      distinguish this from the case where someone writes mfcr %r3,0.  */
1263   else if (value == 0)
1264     ;
1265
1266   /* If only one bit of the FXM field is set, we can use the new form
1267      of the instruction, which is faster.  Unlike the Power4 branch hint
1268      encoding, this is not backward compatible.  Do not generate the
1269      new form unless -mpower4 has been given, or -many and the two
1270      operand form of mfcr was used.  */
1271   else if ((value & -value) == value
1272            && ((dialect & PPC_OPCODE_POWER4) != 0
1273                || ((dialect & PPC_OPCODE_ANY) != 0
1274                    && (insn & (0x3ff << 1)) == 19 << 1)))
1275     insn |= 1 << 20;
1276
1277   /* Any other value on mfcr is an error.  */
1278   else if ((insn & (0x3ff << 1)) == 19 << 1)
1279     {
1280       *errmsg = _("ignoring invalid mfcr mask");
1281       value = 0;
1282     }
1283
1284   return insn | ((value & 0xff) << 12);
1285 }
1286
1287 static long
1288 extract_fxm (unsigned long insn,
1289              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1290              int *invalid)
1291 {
1292   long mask = (insn >> 12) & 0xff;
1293
1294   /* Is this a Power4 insn?  */
1295   if ((insn & (1 << 20)) != 0)
1296     {
1297       /* Exactly one bit of MASK should be set.  */
1298       if (mask == 0 || (mask & -mask) != mask)
1299         *invalid = 1;
1300     }
1301
1302   /* Check that non-power4 form of mfcr has a zero MASK.  */
1303   else if ((insn & (0x3ff << 1)) == 19 << 1)
1304     {
1305       if (mask != 0)
1306         *invalid = 1;
1307     }
1308
1309   return mask;
1310 }
1311
1312 static unsigned long
1313 insert_li20 (unsigned long insn,
1314              long value,
1315              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1316              const char **errmsg ATTRIBUTE_UNUSED)
1317 {
1318   return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1319 }
1320
1321 static long
1322 extract_li20 (unsigned long insn,
1323               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1324               int *invalid ATTRIBUTE_UNUSED)
1325 {
1326   long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1327
1328   return ext
1329          | (((insn >> 11) & 0xf) << 16)
1330          | (((insn >> 17) & 0xf) << 12)
1331          | (((insn >> 16) & 0x1) << 11)
1332          | (insn & 0x7ff);
1333 }
1334
1335 /* The LS field in a sync instruction that accepts 2 operands
1336    Values 2 and 3 are reserved,
1337      must be treated as 0 for future compatibility
1338    Values 0 and 1 can be accepted, if field ESYNC is zero
1339    Otherwise L = complement of ESYNC-bit2 (1<<18) */
1340
1341 static unsigned long
1342 insert_ls (unsigned long insn,
1343            long value,
1344            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1345            const char **errmsg ATTRIBUTE_UNUSED)
1346 {
1347   unsigned long ls;
1348
1349   ls = (insn >> 21) & 0x03;
1350   if (value == 0)
1351     {
1352       if (ls > 1)
1353         return insn & ~(0x3 << 21);
1354       return insn;
1355     }
1356   if ((value & 0x2) != 0)
1357     return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16);
1358   return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16);
1359 }
1360
1361 /* The MB and ME fields in an M form instruction expressed as a single
1362    operand which is itself a bitmask.  The extraction function always
1363    marks it as invalid, since we never want to recognize an
1364    instruction which uses a field of this type.  */
1365
1366 static unsigned long
1367 insert_mbe (unsigned long insn,
1368             long value,
1369             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1370             const char **errmsg)
1371 {
1372   unsigned long uval, mask;
1373   int mb, me, mx, count, last;
1374
1375   uval = value;
1376
1377   if (uval == 0)
1378     {
1379       *errmsg = _("illegal bitmask");
1380       return insn;
1381     }
1382
1383   mb = 0;
1384   me = 32;
1385   if ((uval & 1) != 0)
1386     last = 1;
1387   else
1388     last = 0;
1389   count = 0;
1390
1391   /* mb: location of last 0->1 transition */
1392   /* me: location of last 1->0 transition */
1393   /* count: # transitions */
1394
1395   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1396     {
1397       if ((uval & mask) && !last)
1398         {
1399           ++count;
1400           mb = mx;
1401           last = 1;
1402         }
1403       else if (!(uval & mask) && last)
1404         {
1405           ++count;
1406           me = mx;
1407           last = 0;
1408         }
1409     }
1410   if (me == 0)
1411     me = 32;
1412
1413   if (count != 2 && (count != 0 || ! last))
1414     *errmsg = _("illegal bitmask");
1415
1416   return insn | (mb << 6) | ((me - 1) << 1);
1417 }
1418
1419 static long
1420 extract_mbe (unsigned long insn,
1421              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1422              int *invalid)
1423 {
1424   long ret;
1425   int mb, me;
1426   int i;
1427
1428   *invalid = 1;
1429
1430   mb = (insn >> 6) & 0x1f;
1431   me = (insn >> 1) & 0x1f;
1432   if (mb < me + 1)
1433     {
1434       ret = 0;
1435       for (i = mb; i <= me; i++)
1436         ret |= 1L << (31 - i);
1437     }
1438   else if (mb == me + 1)
1439     ret = ~0;
1440   else /* (mb > me + 1) */
1441     {
1442       ret = ~0;
1443       for (i = me + 1; i < mb; i++)
1444         ret &= ~(1L << (31 - i));
1445     }
1446   return ret;
1447 }
1448
1449 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1450    is wrapped to the low end.  */
1451
1452 static unsigned long
1453 insert_mb6 (unsigned long insn,
1454             long value,
1455             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1456             const char **errmsg ATTRIBUTE_UNUSED)
1457 {
1458   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1459 }
1460
1461 static long
1462 extract_mb6 (unsigned long insn,
1463              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1464              int *invalid ATTRIBUTE_UNUSED)
1465 {
1466   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1467 }
1468
1469 /* The NB field in an X form instruction.  The value 32 is stored as
1470    0.  */
1471
1472 static long
1473 extract_nb (unsigned long insn,
1474             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1475             int *invalid ATTRIBUTE_UNUSED)
1476 {
1477   long ret;
1478
1479   ret = (insn >> 11) & 0x1f;
1480   if (ret == 0)
1481     ret = 32;
1482   return ret;
1483 }
1484
1485 /* The NB field in an lswi instruction, which has special value
1486    restrictions.  The value 32 is stored as 0.  */
1487
1488 static unsigned long
1489 insert_nbi (unsigned long insn,
1490             long value,
1491             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1492             const char **errmsg ATTRIBUTE_UNUSED)
1493 {
1494   long rtvalue = (insn & RT_MASK) >> 21;
1495   long ravalue = (insn & RA_MASK) >> 16;
1496
1497   if (value == 0)
1498     value = 32;
1499   if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1500                                                      : ravalue))
1501     *errmsg = _("address register in load range");
1502   return insn | ((value & 0x1f) << 11);
1503 }
1504
1505 /* The NSI field in a D form instruction.  This is the same as the SI
1506    field, only negated.  The extraction function always marks it as
1507    invalid, since we never want to recognize an instruction which uses
1508    a field of this type.  */
1509
1510 static unsigned long
1511 insert_nsi (unsigned long insn,
1512             long value,
1513             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1514             const char **errmsg ATTRIBUTE_UNUSED)
1515 {
1516   return insn | (-value & 0xffff);
1517 }
1518
1519 static long
1520 extract_nsi (unsigned long insn,
1521              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1522              int *invalid)
1523 {
1524   *invalid = 1;
1525   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1526 }
1527
1528 /* The RA field in a D or X form instruction which is an updating
1529    load, which means that the RA field may not be zero and may not
1530    equal the RT field.  */
1531
1532 static unsigned long
1533 insert_ral (unsigned long insn,
1534             long value,
1535             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1536             const char **errmsg)
1537 {
1538   if (value == 0
1539       || (unsigned long) value == ((insn >> 21) & 0x1f))
1540     *errmsg = "invalid register operand when updating";
1541   return insn | ((value & 0x1f) << 16);
1542 }
1543
1544 /* The RA field in an lmw instruction, which has special value
1545    restrictions.  */
1546
1547 static unsigned long
1548 insert_ram (unsigned long insn,
1549             long value,
1550             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1551             const char **errmsg)
1552 {
1553   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1554     *errmsg = _("index register in load range");
1555   return insn | ((value & 0x1f) << 16);
1556 }
1557
1558 /* The RA field in the DQ form lq or an lswx instruction, which have special
1559    value restrictions.  */
1560
1561 static unsigned long
1562 insert_raq (unsigned long insn,
1563             long value,
1564             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1565             const char **errmsg)
1566 {
1567   long rtvalue = (insn & RT_MASK) >> 21;
1568
1569   if (value == rtvalue)
1570     *errmsg = _("source and target register operands must be different");
1571   return insn | ((value & 0x1f) << 16);
1572 }
1573
1574 /* The RA field in a D or X form instruction which is an updating
1575    store or an updating floating point load, which means that the RA
1576    field may not be zero.  */
1577
1578 static unsigned long
1579 insert_ras (unsigned long insn,
1580             long value,
1581             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1582             const char **errmsg)
1583 {
1584   if (value == 0)
1585     *errmsg = _("invalid register operand when updating");
1586   return insn | ((value & 0x1f) << 16);
1587 }
1588
1589 /* The RB field in an X form instruction when it must be the same as
1590    the RS field in the instruction.  This is used for extended
1591    mnemonics like mr.  This operand is marked FAKE.  The insertion
1592    function just copies the BT field into the BA field, and the
1593    extraction function just checks that the fields are the same.  */
1594
1595 static unsigned long
1596 insert_rbs (unsigned long insn,
1597             long value ATTRIBUTE_UNUSED,
1598             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1599             const char **errmsg ATTRIBUTE_UNUSED)
1600 {
1601   return insn | (((insn >> 21) & 0x1f) << 11);
1602 }
1603
1604 static long
1605 extract_rbs (unsigned long insn,
1606              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1607              int *invalid)
1608 {
1609   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1610     *invalid = 1;
1611   return 0;
1612 }
1613
1614 /* The RB field in an lswx instruction, which has special value
1615    restrictions.  */
1616
1617 static unsigned long
1618 insert_rbx (unsigned long insn,
1619             long value,
1620             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1621             const char **errmsg)
1622 {
1623   long rtvalue = (insn & RT_MASK) >> 21;
1624
1625   if (value == rtvalue)
1626     *errmsg = _("source and target register operands must be different");
1627   return insn | ((value & 0x1f) << 11);
1628 }
1629
1630 /* The SCI8 field is made up of SCL and {U,N}I8 fields.  */
1631 static unsigned long
1632 insert_sci8 (unsigned long insn,
1633              long value,
1634              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1635              const char **errmsg)
1636 {
1637   unsigned int fill_scale = 0;
1638   unsigned long ui8 = value;
1639
1640   if ((ui8 & 0xffffff00) == 0)
1641     ;
1642   else if ((ui8 & 0xffffff00) == 0xffffff00)
1643     fill_scale = 0x400;
1644   else if ((ui8 & 0xffff00ff) == 0)
1645     {
1646       fill_scale = 1 << 8;
1647       ui8 >>= 8;
1648     }
1649   else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1650     {
1651       fill_scale = 0x400 | (1 << 8);
1652       ui8 >>= 8;
1653     }
1654   else if ((ui8 & 0xff00ffff) == 0)
1655     {
1656       fill_scale = 2 << 8;
1657       ui8 >>= 16;
1658     }
1659   else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1660     {
1661       fill_scale = 0x400 | (2 << 8);
1662       ui8 >>= 16;
1663     }
1664   else if ((ui8 & 0x00ffffff) == 0)
1665     {
1666       fill_scale = 3 << 8;
1667       ui8 >>= 24;
1668     }
1669   else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1670     {
1671       fill_scale = 0x400 | (3 << 8);
1672       ui8 >>= 24;
1673     }
1674   else
1675     {
1676       *errmsg = _("illegal immediate value");
1677       ui8 = 0;
1678     }
1679
1680   return insn | fill_scale | (ui8 & 0xff);
1681 }
1682
1683 static long
1684 extract_sci8 (unsigned long insn,
1685               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1686               int *invalid ATTRIBUTE_UNUSED)
1687 {
1688   int fill = insn & 0x400;
1689   int scale_factor = (insn & 0x300) >> 5;
1690   long value = (insn & 0xff) << scale_factor;
1691
1692   if (fill != 0)
1693     value |= ~((long) 0xff << scale_factor);
1694   return value;
1695 }
1696
1697 static unsigned long
1698 insert_sci8n (unsigned long insn,
1699               long value,
1700               ppc_cpu_t dialect,
1701               const char **errmsg)
1702 {
1703   return insert_sci8 (insn, -value, dialect, errmsg);
1704 }
1705
1706 static long
1707 extract_sci8n (unsigned long insn,
1708                ppc_cpu_t dialect,
1709                int *invalid)
1710 {
1711   return -extract_sci8 (insn, dialect, invalid);
1712 }
1713
1714 static unsigned long
1715 insert_sd4h (unsigned long insn,
1716              long value,
1717              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1718              const char **errmsg ATTRIBUTE_UNUSED)
1719 {
1720   return insn | ((value & 0x1e) << 7);
1721 }
1722
1723 static long
1724 extract_sd4h (unsigned long insn,
1725               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1726               int *invalid ATTRIBUTE_UNUSED)
1727 {
1728   return ((insn >> 8) & 0xf) << 1;
1729 }
1730
1731 static unsigned long
1732 insert_sd4w (unsigned long insn,
1733              long value,
1734              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1735              const char **errmsg ATTRIBUTE_UNUSED)
1736 {
1737   return insn | ((value & 0x3c) << 6);
1738 }
1739
1740 static long
1741 extract_sd4w (unsigned long insn,
1742               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1743               int *invalid ATTRIBUTE_UNUSED)
1744 {
1745   return ((insn >> 8) & 0xf) << 2;
1746 }
1747
1748 static unsigned long
1749 insert_oimm (unsigned long insn,
1750              long value,
1751              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1752              const char **errmsg ATTRIBUTE_UNUSED)
1753 {
1754   return insn | (((value - 1) & 0x1f) << 4);
1755 }
1756
1757 static long
1758 extract_oimm (unsigned long insn,
1759               ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1760               int *invalid ATTRIBUTE_UNUSED)
1761 {
1762   return ((insn >> 4) & 0x1f) + 1;
1763 }
1764
1765 /* The SH field in an MD form instruction.  This is split.  */
1766
1767 static unsigned long
1768 insert_sh6 (unsigned long insn,
1769             long value,
1770             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1771             const char **errmsg ATTRIBUTE_UNUSED)
1772 {
1773   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1774 }
1775
1776 static long
1777 extract_sh6 (unsigned long insn,
1778              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1779              int *invalid ATTRIBUTE_UNUSED)
1780 {
1781   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1782 }
1783
1784 /* The SPR field in an XFX form instruction.  This is flipped--the
1785    lower 5 bits are stored in the upper 5 and vice- versa.  */
1786
1787 static unsigned long
1788 insert_spr (unsigned long insn,
1789             long value,
1790             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1791             const char **errmsg ATTRIBUTE_UNUSED)
1792 {
1793   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1794 }
1795
1796 static long
1797 extract_spr (unsigned long insn,
1798              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1799              int *invalid ATTRIBUTE_UNUSED)
1800 {
1801   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1802 }
1803
1804 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1805 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
1806
1807 static unsigned long
1808 insert_sprg (unsigned long insn,
1809              long value,
1810              ppc_cpu_t dialect,
1811              const char **errmsg)
1812 {
1813   if (value > 7
1814       || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
1815     *errmsg = _("invalid sprg number");
1816
1817   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1818      user mode.  Anything else must use spr 272..279.  */
1819   if (value <= 3 || (insn & 0x100) != 0)
1820     value |= 0x10;
1821
1822   return insn | ((value & 0x17) << 16);
1823 }
1824
1825 static long
1826 extract_sprg (unsigned long insn,
1827               ppc_cpu_t dialect,
1828               int *invalid)
1829 {
1830   unsigned long val = (insn >> 16) & 0x1f;
1831
1832   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1833      If not BOOKE, 405 or VLE, then both use only 272..275.  */
1834   if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
1835       || (val - 0x10 > 7 && (insn & 0x100) != 0)
1836       || val <= 3
1837       || (val & 8) != 0)
1838     *invalid = 1;
1839   return val & 7;
1840 }
1841
1842 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1843    is optional.  When TBR is omitted, it must be inserted as 268 (the
1844    magic number of the TB register).  These functions treat 0
1845    (indicating an omitted optional operand) as 268.  This means that
1846    ``mftb 4,0'' is not handled correctly.  This does not matter very
1847    much, since the architecture manual does not define mftb as
1848    accepting any values other than 268 or 269.  */
1849
1850 #define TB (268)
1851
1852 static unsigned long
1853 insert_tbr (unsigned long insn,
1854             long value,
1855             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1856             const char **errmsg ATTRIBUTE_UNUSED)
1857 {
1858   if (value == 0)
1859     value = TB;
1860   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1861 }
1862
1863 static long
1864 extract_tbr (unsigned long insn,
1865              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1866              int *invalid ATTRIBUTE_UNUSED)
1867 {
1868   long ret;
1869
1870   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1871   if (ret == TB)
1872     ret = 0;
1873   return ret;
1874 }
1875
1876 /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
1877
1878 static unsigned long
1879 insert_xt6 (unsigned long insn,
1880             long value,
1881             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1882             const char **errmsg ATTRIBUTE_UNUSED)
1883 {
1884   return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1885 }
1886
1887 static long
1888 extract_xt6 (unsigned long insn,
1889              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1890              int *invalid ATTRIBUTE_UNUSED)
1891 {
1892   return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1893 }
1894
1895 /* The XA field in an XX3 form instruction.  This is split.  */
1896
1897 static unsigned long
1898 insert_xa6 (unsigned long insn,
1899             long value,
1900             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1901             const char **errmsg ATTRIBUTE_UNUSED)
1902 {
1903   return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1904 }
1905
1906 static long
1907 extract_xa6 (unsigned long insn,
1908              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1909              int *invalid ATTRIBUTE_UNUSED)
1910 {
1911   return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1912 }
1913
1914 /* The XB field in an XX3 form instruction.  This is split.  */
1915
1916 static unsigned long
1917 insert_xb6 (unsigned long insn,
1918             long value,
1919             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1920             const char **errmsg ATTRIBUTE_UNUSED)
1921 {
1922   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1923 }
1924
1925 static long
1926 extract_xb6 (unsigned long insn,
1927              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1928              int *invalid ATTRIBUTE_UNUSED)
1929 {
1930   return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1931 }
1932
1933 /* The XB field in an XX3 form instruction when it must be the same as
1934    the XA field in the instruction.  This is used for extended
1935    mnemonics like xvmovdp.  This operand is marked FAKE.  The insertion
1936    function just copies the XA field into the XB field, and the
1937    extraction function just checks that the fields are the same.  */
1938
1939 static unsigned long
1940 insert_xb6s (unsigned long insn,
1941             long value ATTRIBUTE_UNUSED,
1942             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1943             const char **errmsg ATTRIBUTE_UNUSED)
1944 {
1945   return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1946 }
1947
1948 static long
1949 extract_xb6s (unsigned long insn,
1950              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1951              int *invalid)
1952 {
1953   if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1954       || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1955     *invalid = 1;
1956   return 0;
1957 }
1958
1959 /* The XC field in an XX4 form instruction.  This is split.  */
1960
1961 static unsigned long
1962 insert_xc6 (unsigned long insn,
1963             long value,
1964             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1965             const char **errmsg ATTRIBUTE_UNUSED)
1966 {
1967   return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1968 }
1969
1970 static long
1971 extract_xc6 (unsigned long insn,
1972              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1973              int *invalid ATTRIBUTE_UNUSED)
1974 {
1975   return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
1976 }
1977
1978 static unsigned long
1979 insert_dm (unsigned long insn,
1980            long value,
1981            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1982            const char **errmsg)
1983 {
1984   if (value != 0 && value != 1)
1985     *errmsg = _("invalid constant");
1986   return insn | (((value) ? 3 : 0) << 8);
1987 }
1988
1989 static long
1990 extract_dm (unsigned long insn,
1991             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1992             int *invalid)
1993 {
1994   long value;
1995
1996   value = (insn >> 8) & 3;
1997   if (value != 0 && value != 3)
1998     *invalid = 1;
1999   return (value) ? 1 : 0;
2000 }
2001 /* The VLESIMM field in an I16A form instruction.  This is split.  */
2002
2003 static unsigned long
2004 insert_vlesi (unsigned long insn,
2005             long value,
2006             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2007             const char **errmsg ATTRIBUTE_UNUSED)
2008 {
2009   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2010 }
2011
2012 static long
2013 extract_vlesi (unsigned long insn,
2014              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2015              int *invalid ATTRIBUTE_UNUSED)
2016 {
2017   /* RWRW Because I don't know how to make int be 16 and long be 32 */
2018   /* I can't rely on casting an int to long to get sign extension. */
2019   long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2020   if (value & 0x8000)
2021     value |= 0xffff0000;
2022   return value;
2023 }
2024
2025 static unsigned long
2026 insert_vlensi (unsigned long insn,
2027             long value,
2028             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2029             const char **errmsg ATTRIBUTE_UNUSED)
2030 {
2031   value = -value;
2032   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2033 }
2034 static long
2035 extract_vlensi (unsigned long insn,
2036              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2037              int *invalid ATTRIBUTE_UNUSED)
2038 {
2039   long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2040   if (value & 0x8000)
2041     value |= 0xffff0000;
2042   *invalid = 1;
2043   return -value;
2044 }
2045
2046 /* The VLEUIMM field in an I16A form instruction.  This is split.  */
2047
2048 static unsigned long
2049 insert_vleui (unsigned long insn,
2050             long value,
2051             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2052             const char **errmsg ATTRIBUTE_UNUSED)
2053 {
2054   return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2055 }
2056
2057 static long
2058 extract_vleui (unsigned long insn,
2059              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2060              int *invalid ATTRIBUTE_UNUSED)
2061 {
2062   return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2063 }
2064
2065 /* The VLEUIMML field in an I16L form instruction.  This is split.  */
2066
2067 static unsigned long
2068 insert_vleil (unsigned long insn,
2069             long value,
2070             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2071             const char **errmsg ATTRIBUTE_UNUSED)
2072 {
2073   return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2074 }
2075
2076 static long
2077 extract_vleil (unsigned long insn,
2078              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2079              int *invalid ATTRIBUTE_UNUSED)
2080 {
2081   return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2082 }
2083
2084 \f
2085 /* Macros used to form opcodes.  */
2086
2087 /* The main opcode.  */
2088 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2089 #define OP_MASK OP (0x3f)
2090
2091 /* The main opcode combined with a trap code in the TO field of a D
2092    form instruction.  Used for extended mnemonics for the trap
2093    instructions.  */
2094 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2095 #define OPTO_MASK (OP_MASK | TO_MASK)
2096
2097 /* The main opcode combined with a comparison size bit in the L field
2098    of a D form or X form instruction.  Used for extended mnemonics for
2099    the comparison instructions.  */
2100 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2101 #define OPL_MASK OPL (0x3f,1)
2102
2103 /* The main opcode combined with an update code in D form instruction.
2104    Used for extended mnemonics for VLE memory instructions.  */
2105 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2106 #define OPVUP_MASK OPVUP (0x3f,  0xff)
2107
2108 /* An A form instruction.  */
2109 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2110 #define A_MASK A (0x3f, 0x1f, 1)
2111
2112 /* An A_MASK with the FRB field fixed.  */
2113 #define AFRB_MASK (A_MASK | FRB_MASK)
2114
2115 /* An A_MASK with the FRC field fixed.  */
2116 #define AFRC_MASK (A_MASK | FRC_MASK)
2117
2118 /* An A_MASK with the FRA and FRC fields fixed.  */
2119 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2120
2121 /* An AFRAFRC_MASK, but with L bit clear.  */
2122 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2123
2124 /* A B form instruction.  */
2125 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2126 #define B_MASK B (0x3f, 1, 1)
2127
2128 /* A BD8 form instruction.  This is a 16-bit instruction.  */
2129 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2130 #define BD8_MASK BD8 (0x3f, 1, 1)
2131
2132 /* Another BD8 form instruction.  This is a 16-bit instruction.  */
2133 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2134 #define BD8IO_MASK BD8IO (0x1f)
2135
2136 /* A BD8 form instruction for simplified mnemonics.  */
2137 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2138 /* A mask that excludes BO32 and BI32.  */
2139 #define EBD8IO1_MASK 0xf800
2140 /* A mask that includes BO32 and excludes BI32.  */
2141 #define EBD8IO2_MASK 0xfc00
2142 /* A mask that include BO32 AND BI32.  */
2143 #define EBD8IO3_MASK 0xff00
2144
2145 /* A BD15 form instruction.  */
2146 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2147 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2148
2149 /* A BD15 form instruction for extended conditional branch mnemonics.  */
2150 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2151 #define EBD15_MASK 0xfff00001
2152
2153 /* A BD15 form instruction for extended conditional branch mnemonics with BI.  */
2154 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2155                                     | (((aa) & 0xf) << 22) \
2156                                     | (((bo) & 0x3) << 20) \
2157                                     | (((bi) & 0x3) << 16) \
2158                                     | ((lk) & 1)
2159 #define EBD15BI_MASK  0xfff30001
2160
2161 /* A BD24 form instruction.  */
2162 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2163 #define BD24_MASK BD24 (0x3f, 1, 1)
2164
2165 /* A B form instruction setting the BO field.  */
2166 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2167 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2168
2169 /* A BBO_MASK with the y bit of the BO field removed.  This permits
2170    matching a conditional branch regardless of the setting of the y
2171    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
2172 #define Y_MASK   (((unsigned long) 1) << 21)
2173 #define AT1_MASK (((unsigned long) 3) << 21)
2174 #define AT2_MASK (((unsigned long) 9) << 21)
2175 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
2176 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2177
2178 /* A B form instruction setting the BO field and the condition bits of
2179    the BI field.  */
2180 #define BBOCB(op, bo, cb, aa, lk) \
2181   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2182 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2183
2184 /* A BBOCB_MASK with the y bit of the BO field removed.  */
2185 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2186 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2187 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2188
2189 /* A BBOYCB_MASK in which the BI field is fixed.  */
2190 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2191 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2192
2193 /* A VLE C form instruction.  */
2194 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2195 #define C_LK_MASK C_LK(0x7fff, 1)
2196 #define C(x) ((((unsigned long)(x)) & 0xffff))
2197 #define C_MASK C(0xffff)
2198
2199 /* An Context form instruction.  */
2200 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
2201 #define CTX_MASK CTX(0x3f, 0x7)
2202
2203 /* An User Context form instruction.  */
2204 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
2205 #define UCTX_MASK UCTX(0x3f, 0x1f)
2206
2207 /* The main opcode mask with the RA field clear.  */
2208 #define DRA_MASK (OP_MASK | RA_MASK)
2209
2210 /* A DS form instruction.  */
2211 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2212 #define DS_MASK DSO (0x3f, 3)
2213
2214 /* An EVSEL form instruction.  */
2215 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2216 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2217
2218 /* An IA16 form instruction.  */
2219 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2220 #define IA16_MASK IA16(0x3f, 0x1f)
2221
2222 /* An I16A form instruction.  */
2223 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2224 #define I16A_MASK I16A(0x3f, 0x1f)
2225
2226 /* An I16L form instruction.  */
2227 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2228 #define I16L_MASK I16L(0x3f, 0x1f)
2229
2230 /* An IM7 form instruction.  */
2231 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2232 #define IM7_MASK IM7(0x1f)
2233
2234 /* An M form instruction.  */
2235 #define M(op, rc) (OP (op) | ((rc) & 1))
2236 #define M_MASK M (0x3f, 1)
2237
2238 /* An LI20 form instruction.  */
2239 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2240 #define LI20_MASK LI20(0x3f, 0x1)
2241
2242 /* An M form instruction with the ME field specified.  */
2243 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2244
2245 /* An M_MASK with the MB and ME fields fixed.  */
2246 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2247
2248 /* An M_MASK with the SH and ME fields fixed.  */
2249 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2250
2251 /* An MD form instruction.  */
2252 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2253 #define MD_MASK MD (0x3f, 0x7, 1)
2254
2255 /* An MD_MASK with the MB field fixed.  */
2256 #define MDMB_MASK (MD_MASK | MB6_MASK)
2257
2258 /* An MD_MASK with the SH field fixed.  */
2259 #define MDSH_MASK (MD_MASK | SH6_MASK)
2260
2261 /* An MDS form instruction.  */
2262 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2263 #define MDS_MASK MDS (0x3f, 0xf, 1)
2264
2265 /* An MDS_MASK with the MB field fixed.  */
2266 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2267
2268 /* An SC form instruction.  */
2269 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2270 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2271
2272 /* An SCI8 form instruction.  */
2273 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2274 #define SCI8_MASK SCI8(0x3f, 0x1f)
2275
2276 /* An SCI8 form instruction.  */
2277 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2278 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2279
2280 /* An SD4 form instruction.  This is a 16-bit instruction.  */
2281 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2282 #define SD4_MASK SD4(0xf)
2283
2284 /* An SE_IM5 form instruction.  This is a 16-bit instruction.  */
2285 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2286 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2287
2288 /* An SE_R form instruction.  This is a 16-bit instruction.  */
2289 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2290 #define SE_R_MASK SE_R(0x3f, 0x3f)
2291
2292 /* An SE_RR form instruction.  This is a 16-bit instruction.  */
2293 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2294 #define SE_RR_MASK SE_RR(0x3f, 3)
2295
2296 /* A VX form instruction.  */
2297 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2298
2299 /* The mask for an VX form instruction.  */
2300 #define VX_MASK VX(0x3f, 0x7ff)
2301
2302 /* A VX_MASK with the VA field fixed.  */
2303 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2304
2305 /* A VX_MASK with the VB field fixed.  */
2306 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2307
2308 /* A VX_MASK with the VA and VB fields fixed.  */
2309 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2310
2311 /* A VX_MASK with the VD and VA fields fixed.  */
2312 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2313
2314 /* A VX_MASK with a UIMM4 field.  */
2315 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2316
2317 /* A VX_MASK with a UIMM3 field.  */
2318 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2319
2320 /* A VX_MASK with a UIMM2 field.  */
2321 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2322
2323 /* A VA form instruction.  */
2324 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2325
2326 /* The mask for an VA form instruction.  */
2327 #define VXA_MASK VXA(0x3f, 0x3f)
2328
2329 /* A VXA_MASK with a SHB field.  */
2330 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2331
2332 /* A VXR form instruction.  */
2333 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2334
2335 /* The mask for a VXR form instruction.  */
2336 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2337
2338 /* An X form instruction.  */
2339 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2340
2341 /* An EX form instruction.  */
2342 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2343
2344 /* The mask for an EX form instruction.  */
2345 #define EX_MASK EX (0x3f, 0x7ff)
2346
2347 /* An XX2 form instruction.  */
2348 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2349
2350 /* An XX3 form instruction.  */
2351 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2352
2353 /* An XX3 form instruction with the RC bit specified.  */
2354 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2355
2356 /* An XX4 form instruction.  */
2357 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2358
2359 /* A Z form instruction.  */
2360 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2361
2362 /* An X form instruction with the RC bit specified.  */
2363 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2364
2365 /* A Z form instruction with the RC bit specified.  */
2366 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2367
2368 /* The mask for an X form instruction.  */
2369 #define X_MASK XRC (0x3f, 0x3ff, 1)
2370
2371 /* An X form wait instruction with everything filled in except the WC field.  */
2372 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2373
2374 /* The mask for an XX1 form instruction.  */
2375 #define XX1_MASK X (0x3f, 0x3ff)
2376
2377 /* The mask for an XX2 form instruction.  */
2378 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2379
2380 /* The mask for an XX2 form instruction with the UIM bits specified.  */
2381 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2382
2383 /* The mask for an XX2 form instruction with the BF bits specified.  */
2384 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2385
2386 /* The mask for an XX3 form instruction.  */
2387 #define XX3_MASK XX3 (0x3f, 0xff)
2388
2389 /* The mask for an XX3 form instruction with the BF bits specified.  */
2390 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2391
2392 /* The mask for an XX3 form instruction with the DM or SHW bits specified.  */
2393 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2394 #define XX3SHW_MASK XX3DM_MASK
2395
2396 /* The mask for an XX4 form instruction.  */
2397 #define XX4_MASK XX4 (0x3f, 0x3)
2398
2399 /* An X form wait instruction with everything filled in except the WC field.  */
2400 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2401
2402 /* The mask for a Z form instruction.  */
2403 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2404 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2405
2406 /* An X_MASK with the RA field fixed.  */
2407 #define XRA_MASK (X_MASK | RA_MASK)
2408
2409 /* An XRA_MASK with the W field clear.  */
2410 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2411
2412 /* An X_MASK with the RB field fixed.  */
2413 #define XRB_MASK (X_MASK | RB_MASK)
2414
2415 /* An X_MASK with the RT field fixed.  */
2416 #define XRT_MASK (X_MASK | RT_MASK)
2417
2418 /* An XRT_MASK mask with the L bits clear.  */
2419 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2420
2421 /* An X_MASK with the RA and RB fields fixed.  */
2422 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2423
2424 /* An XRARB_MASK, but with the L bit clear.  */
2425 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2426
2427 /* An X_MASK with the RT and RA fields fixed.  */
2428 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2429
2430 /* An XRTRA_MASK, but with L bit clear.  */
2431 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2432
2433 /* An X form instruction with the L bit specified.  */
2434 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2435
2436 /* An X form instruction with the L bits specified.  */
2437 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2438
2439 /* An X form instruction with RT fields specified */
2440 #define XRT(op, xop, rt) (X ((op), (xop)) \
2441         | ((((unsigned long)(rt)) & 0x1f) << 21))
2442
2443 /* An X form instruction with RT and RA fields specified */
2444 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2445         | ((((unsigned long)(rt)) & 0x1f) << 21) \
2446         | ((((unsigned long)(ra)) & 0x1f) << 16))
2447
2448 /* The mask for an X form comparison instruction.  */
2449 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2450
2451 /* The mask for an X form comparison instruction with the L field
2452    fixed.  */
2453 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2454
2455 /* An X form trap instruction with the TO field specified.  */
2456 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2457 #define XTO_MASK (X_MASK | TO_MASK)
2458
2459 /* An X form tlb instruction with the SH field specified.  */
2460 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2461 #define XTLB_MASK (X_MASK | SH_MASK)
2462
2463 /* An X form sync instruction.  */
2464 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2465
2466 /* An X form sync instruction with everything filled in except the LS field.  */
2467 #define XSYNC_MASK (0xff9fffff)
2468
2469 /* An X form sync instruction with everything filled in except the L and E fields.  */
2470 #define XSYNCLE_MASK (0xff90ffff)
2471
2472 /* An X_MASK, but with the EH bit clear.  */
2473 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2474
2475 /* An X form AltiVec dss instruction.  */
2476 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2477 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2478
2479 /* An XFL form instruction.  */
2480 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2481 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2482
2483 /* An X form isel instruction.  */
2484 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2485 #define XISEL_MASK      XISEL(0x3f, 0x1f)
2486
2487 /* An XL form instruction with the LK field set to 0.  */
2488 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2489
2490 /* An XL form instruction which uses the LK field.  */
2491 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2492
2493 /* The mask for an XL form instruction.  */
2494 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2495
2496 /* An XL form instruction which explicitly sets the BO field.  */
2497 #define XLO(op, bo, xop, lk) \
2498   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2499 #define XLO_MASK (XL_MASK | BO_MASK)
2500
2501 /* An XL form instruction which explicitly sets the y bit of the BO
2502    field.  */
2503 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2504 #define XLYLK_MASK (XL_MASK | Y_MASK)
2505
2506 /* An XL form instruction which sets the BO field and the condition
2507    bits of the BI field.  */
2508 #define XLOCB(op, bo, cb, xop, lk) \
2509   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2510 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2511
2512 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
2513 #define XLBB_MASK (XL_MASK | BB_MASK)
2514 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2515 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2516
2517 /* A mask for branch instructions using the BH field.  */
2518 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2519
2520 /* An XL_MASK with the BO and BB fields fixed.  */
2521 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2522
2523 /* An XL_MASK with the BO, BI and BB fields fixed.  */
2524 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2525
2526 /* An X form mbar instruction with MO field.  */
2527 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2528
2529 /* An XO form instruction.  */
2530 #define XO(op, xop, oe, rc) \
2531   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2532 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2533
2534 /* An XO_MASK with the RB field fixed.  */
2535 #define XORB_MASK (XO_MASK | RB_MASK)
2536
2537 /* An XOPS form instruction for paired singles.  */
2538 #define XOPS(op, xop, rc) \
2539   (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2540 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2541
2542
2543 /* An XS form instruction.  */
2544 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2545 #define XS_MASK XS (0x3f, 0x1ff, 1)
2546
2547 /* A mask for the FXM version of an XFX form instruction.  */
2548 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2549
2550 /* An XFX form instruction with the FXM field filled in.  */
2551 #define XFXM(op, xop, fxm, p4) \
2552   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2553    | ((unsigned long)(p4) << 20))
2554
2555 /* An XFX form instruction with the SPR field filled in.  */
2556 #define XSPR(op, xop, spr) \
2557   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2558 #define XSPR_MASK (X_MASK | SPR_MASK)
2559
2560 /* An XFX form instruction with the SPR field filled in except for the
2561    SPRBAT field.  */
2562 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2563
2564 /* An XFX form instruction with the SPR field filled in except for the
2565    SPRG field.  */
2566 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2567
2568 /* An X form instruction with everything filled in except the E field.  */
2569 #define XE_MASK (0xffff7fff)
2570
2571 /* An X form user context instruction.  */
2572 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
2573 #define XUC_MASK      XUC(0x3f, 0x1f)
2574
2575 /* An XW form instruction.  */
2576 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2577 /* The mask for a G form instruction. rc not supported at present.  */
2578 #define XW_MASK XW (0x3f, 0x3f, 0)
2579
2580 /* An APU form instruction.  */
2581 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2582
2583 /* The mask for an APU form instruction.  */
2584 #define APU_MASK APU (0x3f, 0x3ff, 1)
2585 #define APU_RT_MASK (APU_MASK | RT_MASK)
2586 #define APU_RA_MASK (APU_MASK | RA_MASK)
2587
2588 /* The BO encodings used in extended conditional branch mnemonics.  */
2589 #define BODNZF  (0x0)
2590 #define BODNZFP (0x1)
2591 #define BODZF   (0x2)
2592 #define BODZFP  (0x3)
2593 #define BODNZT  (0x8)
2594 #define BODNZTP (0x9)
2595 #define BODZT   (0xa)
2596 #define BODZTP  (0xb)
2597
2598 #define BOF     (0x4)
2599 #define BOFP    (0x5)
2600 #define BOFM4   (0x6)
2601 #define BOFP4   (0x7)
2602 #define BOT     (0xc)
2603 #define BOTP    (0xd)
2604 #define BOTM4   (0xe)
2605 #define BOTP4   (0xf)
2606
2607 #define BODNZ   (0x10)
2608 #define BODNZP  (0x11)
2609 #define BODZ    (0x12)
2610 #define BODZP   (0x13)
2611 #define BODNZM4 (0x18)
2612 #define BODNZP4 (0x19)
2613 #define BODZM4  (0x1a)
2614 #define BODZP4  (0x1b)
2615
2616 #define BOU     (0x14)
2617
2618 /* The BO16 encodings used in extended VLE conditional branch mnemonics.  */
2619 #define BO16F   (0x0)
2620 #define BO16T   (0x1)
2621
2622 /* The BO32 encodings used in extended VLE conditional branch mnemonics.  */
2623 #define BO32F   (0x0)
2624 #define BO32T   (0x1)
2625 #define BO32DNZ (0x2)
2626 #define BO32DZ  (0x3)
2627
2628 /* The BI condition bit encodings used in extended conditional branch
2629    mnemonics.  */
2630 #define CBLT    (0)
2631 #define CBGT    (1)
2632 #define CBEQ    (2)
2633 #define CBSO    (3)
2634
2635 /* The TO encodings used in extended trap mnemonics.  */
2636 #define TOLGT   (0x1)
2637 #define TOLLT   (0x2)
2638 #define TOEQ    (0x4)
2639 #define TOLGE   (0x5)
2640 #define TOLNL   (0x5)
2641 #define TOLLE   (0x6)
2642 #define TOLNG   (0x6)
2643 #define TOGT    (0x8)
2644 #define TOGE    (0xc)
2645 #define TONL    (0xc)
2646 #define TOLT    (0x10)
2647 #define TOLE    (0x14)
2648 #define TONG    (0x14)
2649 #define TONE    (0x18)
2650 #define TOU     (0x1f)
2651 \f
2652 /* Smaller names for the flags so each entry in the opcodes table will
2653    fit on a single line.  */
2654 #define PPCNONE 0
2655 #undef  PPC
2656 #define PPC     PPC_OPCODE_PPC
2657 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2658 #define POWER4  PPC_OPCODE_POWER4
2659 #define POWER5  PPC_OPCODE_POWER5
2660 #define POWER6  PPC_OPCODE_POWER6
2661 #define POWER7  PPC_OPCODE_POWER7
2662 #define CELL    PPC_OPCODE_CELL
2663 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2664 #define NON32   (PPC_OPCODE_64 | PPC_OPCODE_POWER4      \
2665                  | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2666 #define PPC403  PPC_OPCODE_403
2667 #define PPC405  PPC_OPCODE_405
2668 #define PPC440  PPC_OPCODE_440
2669 #define PPC464  PPC440
2670 #define PPC476  PPC_OPCODE_476
2671 #define PPC750  PPC
2672 #define PPC7450 PPC
2673 #define PPC860  PPC
2674 #define PPCPS   PPC_OPCODE_PPCPS
2675 #define PPCVEC  PPC_OPCODE_ALTIVEC
2676 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
2677 #define PPCVSX  PPC_OPCODE_VSX
2678 #define POWER   PPC_OPCODE_POWER
2679 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2680 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2681 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2682 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2683 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
2684 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2685 #define MFDEC1  PPC_OPCODE_POWER
2686 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2687 #define BOOKE   PPC_OPCODE_BOOKE
2688 #define NO371   PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
2689 #define PPCE300 PPC_OPCODE_E300
2690 #define PPCSPE  PPC_OPCODE_SPE | PPC_OPCODE_VLE
2691 #define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
2692 #define PPCEFS  PPC_OPCODE_EFS | PPC_OPCODE_VLE
2693 #define PPCBRLK PPC_OPCODE_BRLOCK
2694 #define PPCPMR  PPC_OPCODE_PMR
2695 #define PPCTMR  PPC_OPCODE_TMR
2696 #define PPCCHLK PPC_OPCODE_CACHELCK
2697 #define PPCRFMCI        PPC_OPCODE_RFMCI
2698 #define E500MC  PPC_OPCODE_E500MC
2699 #define PPCA2   PPC_OPCODE_A2
2700 #define TITAN   PPC_OPCODE_TITAN
2701 #define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
2702 #define E500    PPC_OPCODE_E500
2703 #define E6500   PPC_OPCODE_E6500
2704 #define PPCVLE  PPC_OPCODE_VLE
2705 \f
2706 /* The opcode table.
2707
2708    The format of the opcode table is:
2709
2710    NAME         OPCODE          MASK         FLAGS      ANTI            {OPERANDS}
2711
2712    NAME is the name of the instruction.
2713    OPCODE is the instruction opcode.
2714    MASK is the opcode mask; this is used to tell the disassembler
2715      which bits in the actual opcode must match OPCODE.
2716    FLAGS are flags indicating which processors support the instruction.
2717    ANTI indicates which processors don't support the instruction.
2718    OPERANDS is the list of operands.
2719
2720    The disassembler reads the table in order and prints the first
2721    instruction which matches, so this table is sorted to put more
2722    specific instructions before more general instructions.
2723
2724    This table must be sorted by major opcode.  Please try to keep it
2725    vaguely sorted within major opcode too, except of course where
2726    constrained otherwise by disassembler operation.  */
2727
2728 const struct powerpc_opcode powerpc_opcodes[] = {
2729 {"attn",        X(0,256),       X_MASK,   POWER4|PPCA2, PPC476,         {0}},
2730 {"tdlgti",      OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2731 {"tdllti",      OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2732 {"tdeqi",       OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2733 {"tdlgei",      OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2734 {"tdlnli",      OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2735 {"tdllei",      OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2736 {"tdlngi",      OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2737 {"tdgti",       OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2738 {"tdgei",       OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2739 {"tdnli",       OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2740 {"tdlti",       OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2741 {"tdlei",       OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2742 {"tdngi",       OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2743 {"tdnei",       OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
2744 {"tdi",         OP(2),          OP_MASK,     PPC64,     PPCNONE,        {TO, RA, SI}},
2745
2746 {"twlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2747 {"tlgti",       OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2748 {"twllti",      OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2749 {"tllti",       OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2750 {"tweqi",       OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2751 {"teqi",        OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2752 {"twlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2753 {"tlgei",       OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2754 {"twlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2755 {"tlnli",       OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2756 {"twllei",      OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2757 {"tllei",       OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2758 {"twlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2759 {"tlngi",       OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2760 {"twgti",       OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2761 {"tgti",        OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2762 {"twgei",       OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2763 {"tgei",        OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2764 {"twnli",       OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2765 {"tnli",        OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2766 {"twlti",       OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2767 {"tlti",        OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2768 {"twlei",       OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2769 {"tlei",        OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2770 {"twngi",       OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2771 {"tngi",        OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2772 {"twnei",       OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2773 {"tnei",        OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2774 {"twi",         OP(3),          OP_MASK,     PPCCOM,    PPCNONE,        {TO, RA, SI}},
2775 {"ti",          OP(3),          OP_MASK,     PWRCOM,    PPCNONE,        {TO, RA, SI}},
2776
2777 {"ps_cmpu0",    X  (4,   0), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2778 {"vaddubm",     VX (4,   0),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2779 {"vmaxub",      VX (4,   2),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2780 {"vrlb",        VX (4,   4),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2781 {"vcmpequb",    VXR(4,   6,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2782 {"vmuloub",     VX (4,   8),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2783 {"vaddfp",      VX (4,  10),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2784 {"psq_lx",      XW (4,   6,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2785 {"vmrghb",      VX (4,  12),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2786 {"psq_stx",     XW (4,   7,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2787 {"vpkuhum",     VX (4,  14),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2788 {"mulhhwu",     XRC(4,   8,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2789 {"mulhhwu.",    XRC(4,   8,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2790 {"ps_sum0",     A  (4,  10,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2791 {"ps_sum0.",    A  (4,  10,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2792 {"ps_sum1",     A  (4,  11,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2793 {"ps_sum1.",    A  (4,  11,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2794 {"ps_muls0",    A  (4,  12,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2795 {"machhwu",     XO (4,  12,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2796 {"ps_muls0.",   A  (4,  12,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2797 {"machhwu.",    XO (4,  12,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2798 {"ps_muls1",    A  (4,  13,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2799 {"ps_muls1.",   A  (4,  13,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2800 {"ps_madds0",   A  (4,  14,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2801 {"ps_madds0.",  A  (4,  14,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2802 {"ps_madds1",   A  (4,  15,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2803 {"ps_madds1.",  A  (4,  15,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2804 {"vmhaddshs",   VXA(4,  32),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2805 {"vmhraddshs",  VXA(4,  33),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2806 {"vmladduhm",   VXA(4,  34),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2807 {"ps_div",      A  (4,  18,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2808 {"vmsumubm",    VXA(4,  36),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2809 {"ps_div.",     A  (4,  18,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2810 {"vmsummbm",    VXA(4,  37),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2811 {"vmsumuhm",    VXA(4,  38),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2812 {"vmsumuhs",    VXA(4,  39),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2813 {"ps_sub",      A  (4,  20,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2814 {"vmsumshm",    VXA(4,  40),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2815 {"ps_sub.",     A  (4,  20,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2816 {"vmsumshs",    VXA(4,  41),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2817 {"ps_add",      A  (4,  21,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2818 {"vsel",        VXA(4,  42),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2819 {"ps_add.",     A  (4,  21,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2820 {"vperm",       VXA(4,  43),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
2821 {"vsldoi",      VXA(4,  44),    VXASHB_MASK, PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, SHB}},
2822 {"ps_sel",      A  (4,  23,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2823 {"vmaddfp",     VXA(4,  46),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
2824 {"ps_sel.",     A  (4,  23,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2825 {"vnmsubfp",    VXA(4,  47),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
2826 {"ps_res",      A  (4,  24,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2827 {"ps_res.",     A  (4,  24,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2828 {"ps_mul",      A  (4,  25,0), AFRB_MASK,    PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2829 {"ps_mul.",     A  (4,  25,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2830 {"ps_rsqrte",   A  (4,  26,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2831 {"ps_rsqrte.",  A  (4,  26,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2832 {"ps_msub",     A  (4,  28,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2833 {"ps_msub.",    A  (4,  28,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2834 {"ps_madd",     A  (4,  29,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2835 {"ps_madd.",    A  (4,  29,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2836 {"ps_nmsub",    A  (4,  30,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2837 {"ps_nmsub.",   A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2838 {"ps_nmadd",    A  (4,  31,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2839 {"ps_nmadd.",   A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2840 {"ps_cmpo0",    X  (4,  32), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2841 {"vadduhm",     VX (4,  64),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2842 {"vmaxuh",      VX (4,  66),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2843 {"vrlh",        VX (4,  68),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2844 {"vcmpequh",    VXR(4,  70,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2845 {"vmulouh",     VX (4,  72),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2846 {"vsubfp",      VX (4,  74),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2847 {"psq_lux",     XW (4,  38,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2848 {"vmrghh",      VX (4,  76),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2849 {"psq_stux",    XW (4,  39,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2850 {"vpkuwum",     VX (4,  78),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2851 {"ps_neg",      XRC(4,  40,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2852 {"mulhhw",      XRC(4,  40,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2853 {"ps_neg.",     XRC(4,  40,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2854 {"mulhhw.",     XRC(4,  40,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2855 {"machhw",      XO (4,  44,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2856 {"machhw.",     XO (4,  44,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2857 {"nmachhw",     XO (4,  46,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2858 {"nmachhw.",    XO (4,  46,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2859 {"ps_cmpu1",    X  (4,  64), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2860 {"vadduwm",     VX (4,  128),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2861 {"vmaxuw",      VX (4,  130),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2862 {"vrlw",        VX (4,  132),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2863 {"vcmpequw",    VXR(4,  134,0), VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2864 {"vmrghw",      VX (4,  140),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2865 {"vpkuhus",     VX (4,  142),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2866 {"ps_mr",       XRC(4,  72,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2867 {"ps_mr.",      XRC(4,  72,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2868 {"machhwsu",    XO (4,  76,0,0),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
2869 {"machhwsu.",   XO (4,  76,0,1),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
2870 {"ps_cmpo1",    X  (4,  96), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2871 {"vcmpeqfp",    VXR(4, 198,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2872 {"vpkuwus",     VX (4, 206),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2873 {"machhws",     XO (4, 108,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2874 {"machhws.",    XO (4, 108,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2875 {"nmachhws",    XO (4, 110,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2876 {"nmachhws.",   XO (4, 110,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2877 {"vmaxsb",      VX (4, 258),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2878 {"vslb",        VX (4, 260),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2879 {"vmulosb",     VX (4, 264),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2880 {"vrefp",       VX (4, 266),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2881 {"vmrglb",      VX (4, 268),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2882 {"vpkshus",     VX (4, 270),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2883 {"ps_nabs",     XRC(4, 136,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2884 {"mulchwu",     XRC(4, 136,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2885 {"ps_nabs.",    XRC(4, 136,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2886 {"mulchwu.",    XRC(4, 136,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2887 {"macchwu",     XO (4, 140,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2888 {"macchwu.",    XO (4, 140,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2889 {"vmaxsh",      VX (4, 322),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2890 {"vslh",        VX (4, 324),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2891 {"vmulosh",     VX (4, 328),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2892 {"vrsqrtefp",   VX (4, 330),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2893 {"vmrglh",      VX (4, 332),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2894 {"vpkswus",     VX (4, 334),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2895 {"mulchw",      XRC(4, 168,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2896 {"mulchw.",     XRC(4, 168,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2897 {"macchw",      XO (4, 172,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2898 {"macchw.",     XO (4, 172,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2899 {"nmacchw",     XO (4, 174,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2900 {"nmacchw.",    XO (4, 174,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2901 {"vaddcuw",     VX (4, 384),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2902 {"vmaxsw",      VX (4, 386),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2903 {"vslw",        VX (4, 388),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2904 {"vexptefp",    VX (4, 394),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2905 {"vmrglw",      VX (4, 396),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2906 {"vpkshss",     VX (4, 398),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2907 {"macchwsu",    XO (4, 204,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2908 {"macchwsu.",   XO (4, 204,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2909 {"vsl",         VX (4, 452),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2910 {"vcmpgefp",    VXR(4, 454,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2911 {"vlogefp",     VX (4, 458),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2912 {"vpkswss",     VX (4, 462),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2913 {"macchws",     XO (4, 236,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2914 {"macchws.",    XO (4, 236,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2915 {"nmacchws",    XO (4, 238,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2916 {"nmacchws.",   XO (4, 238,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
2917 {"evaddw",      VX (4, 512),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2918 {"vaddubs",     VX (4, 512),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2919 {"evaddiw",     VX (4, 514),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB, UIMM}},
2920 {"vminub",      VX (4, 514),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2921 {"evsubfw",     VX (4, 516),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2922 {"evsubw",      VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, RA}},
2923 {"vsrb",        VX (4, 516),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2924 {"evsubifw",    VX (4, 518),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, UIMM, RB}},
2925 {"evsubiw",     VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
2926 {"vcmpgtub",    VXR(4, 518,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2927 {"evabs",       VX (4, 520),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2928 {"vmuleub",     VX (4, 520),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2929 {"evneg",       VX (4, 521),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2930 {"evextsb",     VX (4, 522),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2931 {"vrfin",       VX (4, 522),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2932 {"evextsh",     VX (4, 523),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2933 {"evrndw",      VX (4, 524),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2934 {"vspltb",      VX (4, 524),    VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM4}},
2935 {"evcntlzw",    VX (4, 525),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2936 {"evcntlsw",    VX (4, 526),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2937 {"vupkhsb",     VX (4, 526),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2938 {"brinc",       VX (4, 527),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2939 {"ps_abs",      XRC(4, 264,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2940 {"ps_abs.",     XRC(4, 264,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2941 {"evand",       VX (4, 529),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2942 {"evandc",      VX (4, 530),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2943 {"evxor",       VX (4, 534),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2944 {"evmr",        VX (4, 535),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, BBA}},
2945 {"evor",        VX (4, 535),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2946 {"evnor",       VX (4, 536),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2947 {"evnot",       VX (4, 536),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, BBA}},
2948 {"get",         APU(4, 268,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2949 {"eveqv",       VX (4, 537),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2950 {"evorc",       VX (4, 539),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2951 {"evnand",      VX (4, 542),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2952 {"evsrwu",      VX (4, 544),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2953 {"evsrws",      VX (4, 545),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2954 {"evsrwiu",     VX (4, 546),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
2955 {"evsrwis",     VX (4, 547),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
2956 {"evslw",       VX (4, 548),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2957 {"evslwi",      VX (4, 550),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
2958 {"evrlw",       VX (4, 552),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2959 {"evsplati",    VX (4, 553),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, SIMM}},
2960 {"evrlwi",      VX (4, 554),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
2961 {"evsplatfi",   VX (4, 555),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, SIMM}},
2962 {"evmergehi",   VX (4, 556),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2963 {"evmergelo",   VX (4, 557),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2964 {"evmergehilo", VX (4, 558),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2965 {"evmergelohi", VX (4, 559),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2966 {"evcmpgtu",    VX (4, 560),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2967 {"evcmpgts",    VX (4, 561),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2968 {"evcmpltu",    VX (4, 562),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2969 {"evcmplts",    VX (4, 563),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2970 {"evcmpeq",     VX (4, 564),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2971 {"cget",        APU(4, 284,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2972 {"vadduhs",     VX (4, 576),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2973 {"vminuh",      VX (4, 578),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2974 {"vsrh",        VX (4, 580),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2975 {"vcmpgtuh",    VXR(4, 582,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2976 {"vmuleuh",     VX (4, 584),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2977 {"vrfiz",       VX (4, 586),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2978 {"vsplth",      VX (4, 588),    VXUIMM3_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM3}},
2979 {"vupkhsh",     VX (4, 590),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2980 {"nget",        APU(4, 300,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2981 {"evsel",       EVSEL(4,79),    EVSEL_MASK,  PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB, CRFS}},
2982 {"ncget",       APU(4, 316,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2983 {"evfsadd",     VX (4, 640),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2984 {"vadduws",     VX (4, 640),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2985 {"evfssub",     VX (4, 641),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2986 {"vminuw",      VX (4, 642),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2987 {"evfsabs",     VX (4, 644),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2988 {"vsrw",        VX (4, 644),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2989 {"evfsnabs",    VX (4, 645),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2990 {"evfsneg",     VX (4, 646),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
2991 {"vcmpgtuw",    VXR(4, 646,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
2992 {"evfsmul",     VX (4, 648),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2993 {"evfsdiv",     VX (4, 649),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
2994 {"vrfip",       VX (4, 650),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
2995 {"evfscmpgt",   VX (4, 652),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2996 {"vspltw",      VX (4, 652),    VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM2}},
2997 {"evfscmplt",   VX (4, 653),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2998 {"evfscmpeq",   VX (4, 654),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
2999 {"vupklsb",     VX (4, 654),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3000 {"evfscfui",    VX (4, 656),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3001 {"evfscfsi",    VX (4, 657),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3002 {"evfscfuf",    VX (4, 658),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3003 {"evfscfsf",    VX (4, 659),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3004 {"evfsctui",    VX (4, 660),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3005 {"evfsctsi",    VX (4, 661),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3006 {"evfsctuf",    VX (4, 662),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3007 {"evfsctsf",    VX (4, 663),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3008 {"evfsctuiz",   VX (4, 664),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3009 {"put",         APU(4, 332,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3010 {"evfsctsiz",   VX (4, 666),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
3011 {"evfststgt",   VX (4, 668),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3012 {"evfststlt",   VX (4, 669),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3013 {"evfststeq",   VX (4, 670),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3014 {"cput",        APU(4, 348,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3015 {"efsadd",      VX (4, 704),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3016 {"efssub",      VX (4, 705),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3017 {"efsabs",      VX (4, 708),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3018 {"vsr",         VX (4, 708),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3019 {"efsnabs",     VX (4, 709),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3020 {"efsneg",      VX (4, 710),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3021 {"vcmpgtfp",    VXR(4, 710,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3022 {"efsmul",      VX (4, 712),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3023 {"efsdiv",      VX (4, 713),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3024 {"vrfim",       VX (4, 714),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3025 {"efscmpgt",    VX (4, 716),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3026 {"efscmplt",    VX (4, 717),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3027 {"efscmpeq",    VX (4, 718),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3028 {"vupklsh",     VX (4, 718),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3029 {"efscfd",      VX (4, 719),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3030 {"efscfui",     VX (4, 720),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3031 {"efscfsi",     VX (4, 721),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3032 {"efscfuf",     VX (4, 722),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3033 {"efscfsf",     VX (4, 723),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3034 {"efsctui",     VX (4, 724),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3035 {"efsctsi",     VX (4, 725),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3036 {"efsctuf",     VX (4, 726),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3037 {"efsctsf",     VX (4, 727),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3038 {"efsctuiz",    VX (4, 728),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3039 {"nput",        APU(4, 364,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3040 {"efsctsiz",    VX (4, 730),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3041 {"efststgt",    VX (4, 732),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3042 {"efststlt",    VX (4, 733),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3043 {"efststeq",    VX (4, 734),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3044 {"efdadd",      VX (4, 736),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3045 {"efdsub",      VX (4, 737),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3046 {"efdcfuid",    VX (4, 738),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3047 {"efdcfsid",    VX (4, 739),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3048 {"efdabs",      VX (4, 740),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3049 {"efdnabs",     VX (4, 741),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3050 {"efdneg",      VX (4, 742),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
3051 {"efdmul",      VX (4, 744),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3052 {"efddiv",      VX (4, 745),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
3053 {"efdctuidz",   VX (4, 746),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3054 {"efdctsidz",   VX (4, 747),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3055 {"efdcmpgt",    VX (4, 748),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3056 {"efdcmplt",    VX (4, 749),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3057 {"efdcmpeq",    VX (4, 750),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3058 {"efdcfs",      VX (4, 751),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3059 {"efdcfui",     VX (4, 752),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3060 {"efdcfsi",     VX (4, 753),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3061 {"efdcfuf",     VX (4, 754),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3062 {"efdcfsf",     VX (4, 755),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3063 {"efdctui",     VX (4, 756),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3064 {"efdctsi",     VX (4, 757),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3065 {"efdctuf",     VX (4, 758),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3066 {"efdctsf",     VX (4, 759),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3067 {"efdctuiz",    VX (4, 760),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3068 {"ncput",       APU(4, 380,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
3069 {"efdctsiz",    VX (4, 762),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
3070 {"efdtstgt",    VX (4, 764),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3071 {"efdtstlt",    VX (4, 765),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3072 {"efdtsteq",    VX (4, 766),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
3073 {"evlddx",      VX (4, 768),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3074 {"vaddsbs",     VX (4, 768),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3075 {"evldd",       VX (4, 769),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3076 {"evldwx",      VX (4, 770),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3077 {"vminsb",      VX (4, 770),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3078 {"evldw",       VX (4, 771),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3079 {"evldhx",      VX (4, 772),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3080 {"vsrab",       VX (4, 772),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3081 {"evldh",       VX (4, 773),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3082 {"vcmpgtsb",    VXR(4, 774,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3083 {"evlhhesplatx",VX (4, 776),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3084 {"vmulesb",     VX (4, 776),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3085 {"evlhhesplat", VX (4, 777),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3086 {"vcfux",       VX (4, 778),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3087 {"vcuxwfp",     VX (4, 778),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3088 {"evlhhousplatx",VX(4, 780),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3089 {"vspltisb",    VX (4, 780),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3090 {"evlhhousplat",VX (4, 781),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3091 {"evlhhossplatx",VX(4, 782),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3092 {"vpkpx",       VX (4, 782),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3093 {"evlhhossplat",VX (4, 783),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
3094 {"mullhwu",     XRC(4, 392,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3095 {"evlwhex",     VX (4, 784),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3096 {"mullhwu.",    XRC(4, 392,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3097 {"evlwhe",      VX (4, 785),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3098 {"evlwhoux",    VX (4, 788),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3099 {"evlwhou",     VX (4, 789),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3100 {"evlwhosx",    VX (4, 790),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3101 {"evlwhos",     VX (4, 791),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3102 {"maclhwu",     XO (4, 396,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3103 {"evlwwsplatx", VX (4, 792),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3104 {"maclhwu.",    XO (4, 396,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3105 {"evlwwsplat",  VX (4, 793),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3106 {"evlwhsplatx", VX (4, 796),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3107 {"evlwhsplat",  VX (4, 797),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3108 {"evstddx",     VX (4, 800),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3109 {"evstdd",      VX (4, 801),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3110 {"evstdwx",     VX (4, 802),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3111 {"evstdw",      VX (4, 803),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3112 {"evstdhx",     VX (4, 804),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3113 {"evstdh",      VX (4, 805),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
3114 {"evstwhex",    VX (4, 816),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3115 {"evstwhe",     VX (4, 817),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3116 {"evstwhox",    VX (4, 820),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3117 {"evstwho",     VX (4, 821),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3118 {"evstwwex",    VX (4, 824),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3119 {"evstwwe",     VX (4, 825),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3120 {"evstwwox",    VX (4, 828),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3121 {"evstwwo",     VX (4, 829),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
3122 {"vaddshs",     VX (4, 832),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3123 {"vminsh",      VX (4, 834),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3124 {"vsrah",       VX (4, 836),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3125 {"vcmpgtsh",    VXR(4, 838,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3126 {"vmulesh",     VX (4, 840),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3127 {"vcfsx",       VX (4, 842),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3128 {"vcsxwfp",     VX (4, 842),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3129 {"vspltish",    VX (4, 844),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3130 {"vupkhpx",     VX (4, 846),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3131 {"mullhw",      XRC(4, 424,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3132 {"mullhw.",     XRC(4, 424,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3133 {"maclhw",      XO (4, 428,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3134 {"maclhw.",     XO (4, 428,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3135 {"nmaclhw",     XO (4, 430,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3136 {"nmaclhw.",    XO (4, 430,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3137 {"vaddsws",     VX (4, 896),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3138 {"vminsw",      VX (4, 898),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3139 {"vsraw",       VX (4, 900),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3140 {"vcmpgtsw",    VXR(4, 902,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3141 {"vctuxs",      VX (4, 906),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3142 {"vcfpuxws",    VX (4, 906),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3143 {"vspltisw",    VX (4, 908),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
3144 {"maclhwsu",    XO (4, 460,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3145 {"maclhwsu.",   XO (4, 460,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3146 {"vcmpbfp",     VXR(4, 966,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3147 {"vctsxs",      VX (4, 970),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3148 {"vcfpsxws",    VX (4, 970),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
3149 {"vupklpx",     VX (4, 974),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
3150 {"maclhws",     XO (4, 492,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3151 {"maclhws.",    XO (4, 492,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3152 {"nmaclhws",    XO (4, 494,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3153 {"nmaclhws.",   XO (4, 494,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3154 {"vsububm",     VX (4,1024),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3155 {"vavgub",      VX (4,1026),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3156 {"vabsdub",     VX (4,1027),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3157 {"evmhessf",    VX (4,1027),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3158 {"vand",        VX (4,1028),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3159 {"vcmpequb.",   VXR(4,   6,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3160 {"udi0fcm.",    APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3161 {"udi0fcm",     APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3162 {"evmhossf",    VX (4,1031),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3163 {"evmheumi",    VX (4,1032),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3164 {"evmhesmi",    VX (4,1033),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3165 {"vmaxfp",      VX (4,1034),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3166 {"evmhesmf",    VX (4,1035),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3167 {"evmhoumi",    VX (4,1036),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3168 {"vslo",        VX (4,1036),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3169 {"evmhosmi",    VX (4,1037),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3170 {"evmhosmf",    VX (4,1039),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3171 {"machhwuo",    XO (4,  12,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3172 {"machhwuo.",   XO (4,  12,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3173 {"ps_merge00",  XOPS(4,528,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3174 {"ps_merge00.", XOPS(4,528,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3175 {"evmhessfa",   VX (4,1059),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3176 {"evmhossfa",   VX (4,1063),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3177 {"evmheumia",   VX (4,1064),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3178 {"evmhesmia",   VX (4,1065),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3179 {"evmhesmfa",   VX (4,1067),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3180 {"evmhoumia",   VX (4,1068),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3181 {"evmhosmia",   VX (4,1069),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3182 {"evmhosmfa",   VX (4,1071),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3183 {"vsubuhm",     VX (4,1088),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3184 {"vavguh",      VX (4,1090),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3185 {"vabsduh",     VX (4,1091),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3186 {"vandc",       VX (4,1092),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3187 {"vcmpequh.",   VXR(4,  70,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3188 {"udi1fcm.",    APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3189 {"udi1fcm",     APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3190 {"evmwhssf",    VX (4,1095),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3191 {"evmwlumi",    VX (4,1096),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3192 {"vminfp",      VX (4,1098),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3193 {"evmwhumi",    VX (4,1100),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3194 {"vsro",        VX (4,1100),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3195 {"evmwhsmi",    VX (4,1101),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3196 {"evmwhsmf",    VX (4,1103),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3197 {"evmwssf",     VX (4,1107),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3198 {"machhwo",     XO (4,  44,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3199 {"evmwumi",     VX (4,1112),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3200 {"machhwo.",    XO (4,  44,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3201 {"evmwsmi",     VX (4,1113),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3202 {"evmwsmf",     VX (4,1115),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3203 {"nmachhwo",    XO (4,  46,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3204 {"nmachhwo.",   XO (4,  46,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3205 {"ps_merge01",  XOPS(4,560,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3206 {"ps_merge01.", XOPS(4,560,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3207 {"evmwhssfa",   VX (4,1127),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3208 {"evmwlumia",   VX (4,1128),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3209 {"evmwhumia",   VX (4,1132),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3210 {"evmwhsmia",   VX (4,1133),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3211 {"evmwhsmfa",   VX (4,1135),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3212 {"evmwssfa",    VX (4,1139),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3213 {"evmwumia",    VX (4,1144),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3214 {"evmwsmia",    VX (4,1145),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3215 {"evmwsmfa",    VX (4,1147),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3216 {"vsubuwm",     VX (4,1152),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3217 {"vavguw",      VX (4,1154),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3218 {"vabsduw",     VX (4,1155),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
3219 {"vmr",         VX (4,1156),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VBA}},
3220 {"vor",         VX (4,1156),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3221 {"vcmpequw.",   VXR(4, 134,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3222 {"udi2fcm.",    APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3223 {"udi2fcm",     APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3224 {"machhwsuo",   XO (4,  76,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3225 {"machhwsuo.",  XO (4,  76,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3226 {"ps_merge10",  XOPS(4,592,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3227 {"ps_merge10.", XOPS(4,592,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3228 {"evaddusiaaw", VX (4,1216),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3229 {"evaddssiaaw", VX (4,1217),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3230 {"evsubfusiaaw",VX (4,1218),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3231 {"evsubfssiaaw",VX (4,1219),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3232 {"evmra",       VX (4,1220),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3233 {"vxor",        VX (4,1220),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3234 {"evdivws",     VX (4,1222),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3235 {"vcmpeqfp.",   VXR(4, 198,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3236 {"udi3fcm.",    APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3237 {"udi3fcm",     APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3238 {"evdivwu",     VX (4,1223),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3239 {"evaddumiaaw", VX (4,1224),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3240 {"evaddsmiaaw", VX (4,1225),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3241 {"evsubfumiaaw",VX (4,1226),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3242 {"evsubfsmiaaw",VX (4,1227),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
3243 {"machhwso",    XO (4, 108,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3244 {"machhwso.",   XO (4, 108,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3245 {"nmachhwso",   XO (4, 110,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3246 {"nmachhwso.",  XO (4, 110,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3247 {"ps_merge11",  XOPS(4,624,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3248 {"ps_merge11.", XOPS(4,624,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
3249 {"evmheusiaaw", VX (4,1280),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3250 {"evmhessiaaw", VX (4,1281),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3251 {"vavgsb",      VX (4,1282),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3252 {"evmhessfaaw", VX (4,1283),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3253 {"evmhousiaaw", VX (4,1284),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3254 {"vnot",        VX (4,1284),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VBA}},
3255 {"vnor",        VX (4,1284),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3256 {"evmhossiaaw", VX (4,1285),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3257 {"udi4fcm.",    APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3258 {"udi4fcm",     APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3259 {"evmhossfaaw", VX (4,1287),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3260 {"evmheumiaaw", VX (4,1288),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3261 {"evmhesmiaaw", VX (4,1289),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3262 {"evmhesmfaaw", VX (4,1291),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3263 {"evmhoumiaaw", VX (4,1292),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3264 {"evmhosmiaaw", VX (4,1293),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3265 {"evmhosmfaaw", VX (4,1295),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3266 {"macchwuo",    XO (4, 140,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3267 {"macchwuo.",   XO (4, 140,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3268 {"evmhegumiaa", VX (4,1320),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3269 {"evmhegsmiaa", VX (4,1321),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3270 {"evmhegsmfaa", VX (4,1323),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3271 {"evmhogumiaa", VX (4,1324),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3272 {"evmhogsmiaa", VX (4,1325),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3273 {"evmhogsmfaa", VX (4,1327),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3274 {"evmwlusiaaw", VX (4,1344),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3275 {"evmwlssiaaw", VX (4,1345),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3276 {"vavgsh",      VX (4,1346),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3277 {"udi5fcm.",    APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3278 {"udi5fcm",     APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3279 {"evmwlumiaaw", VX (4,1352),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3280 {"evmwlsmiaaw", VX (4,1353),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3281 {"evmwssfaa",   VX (4,1363),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3282 {"macchwo",     XO (4, 172,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3283 {"evmwumiaa",   VX (4,1368),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3284 {"macchwo.",    XO (4, 172,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3285 {"evmwsmiaa",   VX (4,1369),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3286 {"evmwsmfaa",   VX (4,1371),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3287 {"nmacchwo",    XO (4, 174,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3288 {"nmacchwo.",   XO (4, 174,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3289 {"evmheusianw", VX (4,1408),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3290 {"vsubcuw",     VX (4,1408),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3291 {"evmhessianw", VX (4,1409),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3292 {"vavgsw",      VX (4,1410),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3293 {"evmhessfanw", VX (4,1411),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3294 {"evmhousianw", VX (4,1412),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3295 {"evmhossianw", VX (4,1413),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3296 {"udi6fcm.",    APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3297 {"udi6fcm",     APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3298 {"evmhossfanw", VX (4,1415),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3299 {"evmheumianw", VX (4,1416),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3300 {"evmhesmianw", VX (4,1417),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3301 {"evmhesmfanw", VX (4,1419),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3302 {"evmhoumianw", VX (4,1420),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3303 {"evmhosmianw", VX (4,1421),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3304 {"evmhosmfanw", VX (4,1423),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3305 {"macchwsuo",   XO (4, 204,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3306 {"macchwsuo.",  XO (4, 204,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3307 {"evmhegumian", VX (4,1448),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3308 {"evmhegsmian", VX (4,1449),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3309 {"evmhegsmfan", VX (4,1451),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3310 {"evmhogumian", VX (4,1452),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3311 {"evmhogsmian", VX (4,1453),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3312 {"evmhogsmfan", VX (4,1455),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3313 {"evmwlusianw", VX (4,1472),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3314 {"evmwlssianw", VX (4,1473),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3315 {"vcmpgefp.",   VXR(4, 454,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3316 {"udi7fcm.",    APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3317 {"udi7fcm",     APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
3318 {"evmwlumianw", VX (4,1480),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3319 {"evmwlsmianw", VX (4,1481),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3320 {"evmwssfan",   VX (4,1491),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3321 {"macchwso",    XO (4, 236,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3322 {"evmwumian",   VX (4,1496),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3323 {"macchwso.",   XO (4, 236,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3324 {"evmwsmian",   VX (4,1497),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3325 {"evmwsmfan",   VX (4,1499),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
3326 {"nmacchwso",   XO (4, 238,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3327 {"nmacchwso.",  XO (4, 238,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3328 {"vsububs",     VX (4,1536),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3329 {"mfvscr",      VX (4,1540),    VXVAVB_MASK, PPCVEC|PPCVLE, PPCNONE,    {VD}},
3330 {"vcmpgtub.",   VXR(4, 518,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3331 {"udi8fcm.",    APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3332 {"udi8fcm",     APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3333 {"vsum4ubs",    VX (4,1544),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3334 {"vsubuhs",     VX (4,1600),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3335 {"mtvscr",      VX (4,1604),    VXVDVA_MASK, PPCVEC|PPCVLE, PPCNONE,    {VB}},
3336 {"vcmpgtuh.",   VXR(4, 582,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3337 {"vsum4shs",    VX (4,1608),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3338 {"udi9fcm.",    APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3339 {"udi9fcm",     APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3340 {"vsubuws",     VX (4,1664),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3341 {"vcmpgtuw.",   VXR(4, 646,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3342 {"udi10fcm.",   APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3343 {"udi10fcm",    APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3344 {"vsum2sws",    VX (4,1672),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3345 {"vcmpgtfp.",   VXR(4, 710,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3346 {"udi11fcm.",   APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3347 {"udi11fcm",    APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3348 {"vsubsbs",     VX (4,1792),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3349 {"vcmpgtsb.",   VXR(4, 774,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3350 {"udi12fcm.",   APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3351 {"udi12fcm",    APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3352 {"vsum4sbs",    VX (4,1800),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3353 {"maclhwuo",    XO (4, 396,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3354 {"maclhwuo.",   XO (4, 396,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3355 {"vsubshs",     VX (4,1856),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3356 {"vcmpgtsh.",   VXR(4, 838,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3357 {"udi13fcm.",   APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3358 {"udi13fcm",    APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3359 {"maclhwo",     XO (4, 428,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3360 {"maclhwo.",    XO (4, 428,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3361 {"nmaclhwo",    XO (4, 430,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3362 {"nmaclhwo.",   XO (4, 430,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3363 {"vsubsws",     VX (4,1920),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3364 {"vcmpgtsw.",   VXR(4, 902,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3365 {"udi14fcm.",   APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3366 {"udi14fcm",    APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3367 {"vsumsws",     VX (4,1928),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
3368 {"maclhwsuo",   XO (4, 460,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3369 {"maclhwsuo.",  XO (4, 460,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3370 {"vcmpbfp.",    VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
3371 {"udi15fcm.",   APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3372 {"udi15fcm",    APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
3373 {"maclhwso",    XO (4, 492,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3374 {"maclhwso.",   XO (4, 492,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3375 {"nmaclhwso",   XO (4, 494,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3376 {"nmaclhwso.",  XO (4, 494,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
3377 {"dcbz_l",      X  (4,1014),    XRT_MASK,    PPCPS,     PPCNONE,        {RA, RB}},
3378
3379 {"mulli",       OP(7),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3380 {"muli",        OP(7),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3381
3382 {"subfic",      OP(8),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3383 {"sfi",         OP(8),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3384
3385 {"dozi",        OP(9),          OP_MASK,     M601,      PPCNONE,        {RT, RA, SI}},
3386
3387 {"cmplwi",      OPL(10,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, UI}},
3388 {"cmpldi",      OPL(10,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, UI}},
3389 {"cmpli",       OP(10),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, UI}},
3390 {"cmpli",       OP(10),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, UI}},
3391
3392 {"cmpwi",       OPL(11,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, SI}},
3393 {"cmpdi",       OPL(11,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, SI}},
3394 {"cmpi",        OP(11),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, SI}},
3395 {"cmpi",        OP(11),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, SI}},
3396
3397 {"addic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3398 {"ai",          OP(12),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3399 {"subic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
3400
3401 {"addic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
3402 {"ai.",         OP(13),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
3403 {"subic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
3404
3405 {"li",          OP(14),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SI}},
3406 {"lil",         OP(14),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SI}},
3407 {"addi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SI}},
3408 {"cal",         OP(14),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
3409 {"subi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
3410 {"la",          OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
3411
3412 {"lis",         OP(15),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SISIGNOPT}},
3413 {"liu",         OP(15),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SISIGNOPT}},
3414 {"addis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
3415 {"cau",         OP(15),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
3416 {"subis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
3417
3418 {"bdnz-",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3419 {"bdnz+",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3420 {"bdnz",     BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
3421 {"bdn",      BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
3422 {"bdnzl-",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3423 {"bdnzl+",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3424 {"bdnzl",    BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
3425 {"bdnl",     BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
3426 {"bdnza-",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3427 {"bdnza+",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3428 {"bdnza",    BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
3429 {"bdna",     BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
3430 {"bdnzla-",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3431 {"bdnzla+",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3432 {"bdnzla",   BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
3433 {"bdnla",    BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
3434 {"bdz-",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3435 {"bdz+",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3436 {"bdz",      BBO(16,BODZ,0,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
3437 {"bdzl-",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
3438 {"bdzl+",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
3439 {"bdzl",     BBO(16,BODZ,0,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
3440 {"bdza-",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3441 {"bdza+",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3442 {"bdza",     BBO(16,BODZ,1,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
3443 {"bdzla-",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
3444 {"bdzla+",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
3445 {"bdzla",    BBO(16,BODZ,1,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
3446
3447 {"bge-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3448 {"bge+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3449 {"bge",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3450 {"bnl-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3451 {"bnl+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3452 {"bnl",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3453 {"bgel-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3454 {"bgel+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3455 {"bgel",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3456 {"bnll-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3457 {"bnll+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3458 {"bnll",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3459 {"bgea-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3460 {"bgea+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3461 {"bgea",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3462 {"bnla-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3463 {"bnla+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3464 {"bnla",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3465 {"bgela-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3466 {"bgela+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3467 {"bgela",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3468 {"bnlla-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3469 {"bnlla+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3470 {"bnlla",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3471 {"ble-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3472 {"ble+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3473 {"ble",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3474 {"bng-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3475 {"bng+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3476 {"bng",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3477 {"blel-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3478 {"blel+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3479 {"blel",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3480 {"bngl-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3481 {"bngl+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3482 {"bngl",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3483 {"blea-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3484 {"blea+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3485 {"blea",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3486 {"bnga-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3487 {"bnga+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3488 {"bnga",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3489 {"blela-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3490 {"blela+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3491 {"blela",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3492 {"bngla-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3493 {"bngla+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3494 {"bngla",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3495 {"bne-",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3496 {"bne+",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3497 {"bne",      BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3498 {"bnel-",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3499 {"bnel+",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3500 {"bnel",     BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3501 {"bnea-",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3502 {"bnea+",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3503 {"bnea",     BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3504 {"bnela-",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3505 {"bnela+",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3506 {"bnela",    BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3507 {"bns-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3508 {"bns+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3509 {"bns",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3510 {"bnu-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3511 {"bnu+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3512 {"bnu",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3513 {"bnsl-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3514 {"bnsl+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3515 {"bnsl",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3516 {"bnul-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3517 {"bnul+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3518 {"bnul",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3519 {"bnsa-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3520 {"bnsa+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3521 {"bnsa",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3522 {"bnua-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3523 {"bnua+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3524 {"bnua",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3525 {"bnsla-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3526 {"bnsla+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3527 {"bnsla",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3528 {"bnula-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3529 {"bnula+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3530 {"bnula",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3531
3532 {"blt-",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3533 {"blt+",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3534 {"blt",      BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3535 {"bltl-",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3536 {"bltl+",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3537 {"bltl",     BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3538 {"blta-",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3539 {"blta+",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3540 {"blta",     BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3541 {"bltla-",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3542 {"bltla+",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3543 {"bltla",    BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3544 {"bgt-",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3545 {"bgt+",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3546 {"bgt",      BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3547 {"bgtl-",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3548 {"bgtl+",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3549 {"bgtl",     BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3550 {"bgta-",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3551 {"bgta+",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3552 {"bgta",     BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3553 {"bgtla-",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3554 {"bgtla+",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3555 {"bgtla",    BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3556 {"beq-",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3557 {"beq+",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3558 {"beq",      BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3559 {"beql-",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3560 {"beql+",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3561 {"beql",     BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3562 {"beqa-",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3563 {"beqa+",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3564 {"beqa",     BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3565 {"beqla-",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3566 {"beqla+",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3567 {"beqla",    BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3568 {"bso-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3569 {"bso+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3570 {"bso",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3571 {"bun-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3572 {"bun+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3573 {"bun",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3574 {"bsol-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3575 {"bsol+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3576 {"bsol",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
3577 {"bunl-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
3578 {"bunl+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
3579 {"bunl",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
3580 {"bsoa-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3581 {"bsoa+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3582 {"bsoa",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3583 {"buna-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3584 {"buna+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3585 {"buna",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3586 {"bsola-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3587 {"bsola+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3588 {"bsola",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
3589 {"bunla-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
3590 {"bunla+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
3591 {"bunla",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
3592
3593 {"bdnzf-",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3594 {"bdnzf+",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3595 {"bdnzf",    BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3596 {"bdnzfl-",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3597 {"bdnzfl+",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3598 {"bdnzfl",   BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3599 {"bdnzfa-",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3600 {"bdnzfa+",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3601 {"bdnzfa",   BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3602 {"bdnzfla-", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3603 {"bdnzfla+", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3604 {"bdnzfla",  BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3605 {"bdzf-",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3606 {"bdzf+",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3607 {"bdzf",     BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3608 {"bdzfl-",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3609 {"bdzfl+",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3610 {"bdzfl",    BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3611 {"bdzfa-",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3612 {"bdzfa+",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3613 {"bdzfa",    BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3614 {"bdzfla-",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3615 {"bdzfla+",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3616 {"bdzfla",   BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3617
3618 {"bf-",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3619 {"bf+",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3620 {"bf",       BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3621 {"bbf",      BBO(16,BOF,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3622 {"bfl-",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3623 {"bfl+",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3624 {"bfl",      BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3625 {"bbfl",     BBO(16,BOF,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3626 {"bfa-",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3627 {"bfa+",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3628 {"bfa",      BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3629 {"bbfa",     BBO(16,BOF,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3630 {"bfla-",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3631 {"bfla+",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3632 {"bfla",     BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3633 {"bbfla",    BBO(16,BOF,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3634
3635 {"bdnzt-",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3636 {"bdnzt+",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3637 {"bdnzt",    BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3638 {"bdnztl-",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3639 {"bdnztl+",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3640 {"bdnztl",   BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3641 {"bdnzta-",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3642 {"bdnzta+",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3643 {"bdnzta",   BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3644 {"bdnztla-", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3645 {"bdnztla+", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3646 {"bdnztla",  BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3647 {"bdzt-",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3648 {"bdzt+",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3649 {"bdzt",     BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3650 {"bdztl-",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
3651 {"bdztl+",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
3652 {"bdztl",    BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
3653 {"bdzta-",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3654 {"bdzta+",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3655 {"bdzta",    BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3656 {"bdztla-",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
3657 {"bdztla+",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
3658 {"bdztla",   BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
3659
3660 {"bt-",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3661 {"bt+",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3662 {"bt",       BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3663 {"bbt",      BBO(16,BOT,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3664 {"btl-",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
3665 {"btl+",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
3666 {"btl",      BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
3667 {"bbtl",     BBO(16,BOT,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
3668 {"bta-",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3669 {"bta+",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3670 {"bta",      BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3671 {"bbta",     BBO(16,BOT,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3672 {"btla-",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
3673 {"btla+",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
3674 {"btla",     BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
3675 {"bbtla",    BBO(16,BOT,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
3676
3677 {"bc-",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
3678 {"bc+",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
3679 {"bc",          B(16,0,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
3680 {"bcl-",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
3681 {"bcl+",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
3682 {"bcl",         B(16,0,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
3683 {"bca-",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
3684 {"bca+",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
3685 {"bca",         B(16,1,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
3686 {"bcla-",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
3687 {"bcla+",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
3688 {"bcla",        B(16,1,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
3689
3690 {"svc",         SC(17,0,0),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
3691 {"svcl",        SC(17,0,1),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
3692 {"sc",          SC(17,1,0),     SC_MASK,     PPC,       PPCNONE,        {LEV}},
3693 {"svca",        SC(17,1,0),     SC_MASK,     PWRCOM,    PPCNONE,        {SV}},
3694 {"svcla",       SC(17,1,1),     SC_MASK,     POWER,     PPCNONE,        {SV}},
3695
3696 {"b",           B(18,0,0),      B_MASK,      COM,       PPCNONE,        {LI}},
3697 {"bl",          B(18,0,1),      B_MASK,      COM,       PPCNONE,        {LI}},
3698 {"ba",          B(18,1,0),      B_MASK,      COM,       PPCNONE,        {LIA}},
3699 {"bla",         B(18,1,1),      B_MASK,      COM,       PPCNONE,        {LIA}},
3700
3701 {"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
3702
3703 {"bdnzlr",   XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3704 {"bdnzlr-",  XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3705 {"bdnzlrl",  XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3706 {"bdnzlrl-", XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3707 {"bdnzlr+",  XLO(19,BODNZP,16,0),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3708 {"bdnzlrl+", XLO(19,BODNZP,16,1),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3709 {"bdzlr",    XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3710 {"bdzlr-",   XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3711 {"bdzlrl",   XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3712 {"bdzlrl-",  XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3713 {"bdzlr+",   XLO(19,BODZP,16,0),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3714 {"bdzlrl+",  XLO(19,BODZP,16,1),        XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
3715 {"blr",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3716 {"br",       XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
3717 {"blrl",     XLO(19,BOU,16,1),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
3718 {"brl",      XLO(19,BOU,16,1),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
3719 {"bdnzlr-",  XLO(19,BODNZM4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3720 {"bdnzlrl-", XLO(19,BODNZM4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3721 {"bdnzlr+",  XLO(19,BODNZP4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3722 {"bdnzlrl+", XLO(19,BODNZP4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3723 {"bdzlr-",   XLO(19,BODZM4,16,0),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3724 {"bdzlrl-",  XLO(19,BODZM4,16,1),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3725 {"bdzlr+",   XLO(19,BODZP4,16,0),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3726 {"bdzlrl+",  XLO(19,BODZP4,16,1),       XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
3727
3728 {"bgelr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3729 {"bgelr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3730 {"bger",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3731 {"bnllr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3732 {"bnllr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3733 {"bnlr",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3734 {"bgelrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3735 {"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3736 {"bgerl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3737 {"bnllrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3738 {"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3739 {"bnlrl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3740 {"blelr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3741 {"blelr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3742 {"bler",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3743 {"bnglr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3744 {"bnglr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3745 {"bngr",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3746 {"blelrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3747 {"blelrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3748 {"blerl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3749 {"bnglrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3750 {"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3751 {"bngrl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3752 {"bnelr",    XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3753 {"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3754 {"bner",     XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3755 {"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3756 {"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3757 {"bnerl",    XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3758 {"bnslr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3759 {"bnslr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3760 {"bnsr",     XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3761 {"bnulr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3762 {"bnulr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3763 {"bnslrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3764 {"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3765 {"bnsrl",    XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3766 {"bnulrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3767 {"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3768 {"bgelr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3769 {"bnllr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3770 {"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3771 {"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3772 {"blelr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3773 {"bnglr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3774 {"blelrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3775 {"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3776 {"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3777 {"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3778 {"bnslr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3779 {"bnulr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3780 {"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3781 {"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3782 {"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3783 {"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3784 {"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3785 {"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3786 {"blelr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3787 {"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3788 {"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3789 {"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3790 {"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3791 {"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3792 {"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3793 {"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3794 {"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3795 {"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3796 {"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3797 {"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3798 {"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3799 {"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3800 {"blelr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3801 {"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3802 {"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3803 {"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3804 {"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3805 {"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3806 {"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3807 {"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3808 {"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3809 {"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3810 {"bltlr",    XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3811 {"bltlr-",   XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3812 {"bltr",     XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3813 {"bltlrl",   XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3814 {"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3815 {"bltrl",    XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3816 {"bgtlr",    XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3817 {"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3818 {"bgtr",     XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3819 {"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3820 {"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3821 {"bgtrl",    XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3822 {"beqlr",    XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3823 {"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3824 {"beqr",     XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3825 {"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3826 {"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3827 {"beqrl",    XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3828 {"bsolr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3829 {"bsolr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3830 {"bsor",     XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3831 {"bunlr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3832 {"bunlr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3833 {"bsolrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3834 {"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3835 {"bsorl",    XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3836 {"bunlrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3837 {"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3838 {"bltlr+",   XLOCB(19,BOTP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3839 {"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3840 {"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3841 {"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3842 {"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3843 {"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3844 {"bsolr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3845 {"bunlr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3846 {"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3847 {"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3848 {"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3849 {"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3850 {"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3851 {"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3852 {"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3853 {"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3854 {"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3855 {"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3856 {"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3857 {"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3858 {"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3859 {"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3860 {"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3861 {"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3862 {"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3863 {"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3864 {"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3865 {"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3866 {"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3867 {"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
3868
3869 {"bdnzflr",  XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3870 {"bdnzflr-", XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3871 {"bdnzflrl", XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3872 {"bdnzflrl-",XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3873 {"bdnzflr+", XLO(19,BODNZFP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3874 {"bdnzflrl+",XLO(19,BODNZFP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3875 {"bdzflr",   XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3876 {"bdzflr-",  XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3877 {"bdzflrl",  XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3878 {"bdzflrl-", XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3879 {"bdzflr+",  XLO(19,BODZFP,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3880 {"bdzflrl+", XLO(19,BODZFP,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3881 {"bflr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3882 {"bflr-",    XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3883 {"bbfr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3884 {"bflrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3885 {"bflrl-",   XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3886 {"bbfrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3887 {"bflr+",    XLO(19,BOFP,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3888 {"bflrl+",   XLO(19,BOFP,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3889 {"bflr-",    XLO(19,BOFM4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3890 {"bflrl-",   XLO(19,BOFM4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3891 {"bflr+",    XLO(19,BOFP4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3892 {"bflrl+",   XLO(19,BOFP4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3893 {"bdnztlr",  XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3894 {"bdnztlr-", XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3895 {"bdnztlrl", XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3896 {"bdnztlrl-",XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3897 {"bdnztlr+", XLO(19,BODNZTP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3898 {"bdnztlrl+",XLO(19,BODNZTP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3899 {"bdztlr",   XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3900 {"bdztlr-",  XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3901 {"bdztlrl",  XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3902 {"bdztlrl-", XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3903 {"bdztlr+",  XLO(19,BODZTP,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3904 {"bdztlrl+", XLO(19,BODZTP,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3905 {"btlr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3906 {"btlr-",    XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3907 {"bbtr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3908 {"btlrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3909 {"btlrl-",   XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3910 {"bbtrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3911 {"btlr+",    XLO(19,BOTP,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3912 {"btlrl+",   XLO(19,BOTP,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
3913 {"btlr-",    XLO(19,BOTM4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3914 {"btlrl-",   XLO(19,BOTM4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3915 {"btlr+",    XLO(19,BOTP4,16,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3916 {"btlrl+",   XLO(19,BOTP4,16,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
3917
3918 {"bclr-",    XLYLK(19,16,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3919 {"bclrl-",   XLYLK(19,16,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3920 {"bclr+",    XLYLK(19,16,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3921 {"bclrl+",   XLYLK(19,16,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3922 {"bclr",     XLLK(19,16,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3923 {"bcr",      XLLK(19,16,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3924 {"bclrl",    XLLK(19,16,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3925 {"bcrl",     XLLK(19,16,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3926
3927 {"rfid",        XL(19,18),      0xffffffff,  PPC64,     PPCNONE,        {0}},
3928
3929 {"crnot",       XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3930 {"crnor",       XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3931 {"rfmci",       X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
3932
3933 {"rfdi",        XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
3934 {"rfi",         XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
3935 {"rfci",        XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
3936
3937 {"rfsvc",       XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
3938
3939 {"rfgi",        XL(19,102),   0xffffffff, E500MC|PPCA2, PPCNONE,        {0}},
3940
3941 {"crandc",      XL(19,129),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3942
3943 {"isync",       XL(19,150),     0xffffffff,  PPCCOM,    PPCNONE,        {0}},
3944 {"ics",         XL(19,150),     0xffffffff,  PWRCOM,    PPCNONE,        {0}},
3945
3946 {"crclr",       XL(19,193),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3947 {"crxor",       XL(19,193),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3948
3949 {"dnh",         X(19,198),      X_MASK,      E500MC,    PPCNONE,        {DUI, DUIS}},
3950
3951 {"crnand",      XL(19,225),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3952
3953 {"crand",       XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3954
3955 {"hrfid",       XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
3956
3957 {"crset",       XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3958 {"creqv",       XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3959
3960 {"doze",        XL(19,402),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3961
3962 {"crorc",       XL(19,417),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3963
3964 {"nap",         XL(19,434),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3965
3966 {"crmove",      XL(19,449),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3967 {"cror",        XL(19,449),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3968
3969 {"sleep",       XL(19,466),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3970 {"rvwinkle",    XL(19,498),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3971
3972 {"bctr",    XLO(19,BOU,528,0),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3973 {"bctrl",   XLO(19,BOU,528,1),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3974
3975 {"bgectr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3976 {"bgectr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3977 {"bnlctr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3978 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3979 {"bgectrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3980 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3981 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3982 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3983 {"blectr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3984 {"blectr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3985 {"bngctr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3986 {"bngctr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3987 {"blectrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3988 {"blectrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3989 {"bngctrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3990 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3991 {"bnectr",  XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3992 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3993 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3994 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3995 {"bnsctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3996 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3997 {"bnuctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3998 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
3999 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4000 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4001 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4002 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4003 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4004 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4005 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4006 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4007 {"blectr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4008 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4009 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4010 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4011 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4012 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4013 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4014 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4015 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4016 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4017 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4018 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4019 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4020 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4021 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4022 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4023 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4024 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4025 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4026 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4027 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4028 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4029 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4030 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4031 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4032 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4033 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4034 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4035 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4036 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4037 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4038 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4039 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4040 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4041 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4042 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4043 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4044 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4045 {"bltctr",  XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4046 {"bltctr-", XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4047 {"bltctrl", XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4048 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4049 {"bgtctr",  XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4050 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4051 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4052 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4053 {"beqctr",  XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4054 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4055 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4056 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4057 {"bsoctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4058 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4059 {"bunctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4060 {"bunctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4061 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4062 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4063 {"bunctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
4064 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4065 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4066 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4067 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4068 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4069 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4070 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4071 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4072 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4073 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4074 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
4075 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4076 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4077 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4078 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4079 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4080 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4081 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4082 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4083 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4084 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4085 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4086 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4087 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4088 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4089 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4090 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4091 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4092 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4093 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4094 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
4095
4096 {"bfctr",   XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4097 {"bfctr-",  XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4098 {"bfctrl",  XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4099 {"bfctrl-", XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4100 {"bfctr+",  XLO(19,BOFP,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4101 {"bfctrl+", XLO(19,BOFP,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4102 {"bfctr-",  XLO(19,BOFM4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4103 {"bfctrl-", XLO(19,BOFM4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4104 {"bfctr+",  XLO(19,BOFP4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4105 {"bfctrl+", XLO(19,BOFP4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4106 {"btctr",   XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4107 {"btctr-",  XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4108 {"btctrl",  XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
4109 {"btctrl-", XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4110 {"btctr+",  XLO(19,BOTP,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4111 {"btctrl+", XLO(19,BOTP,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
4112 {"btctr-",  XLO(19,BOTM4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4113 {"btctrl-", XLO(19,BOTM4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4114 {"btctr+",  XLO(19,BOTP4,528,0),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4115 {"btctrl+", XLO(19,BOTP4,528,1),        XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
4116
4117 {"bcctr-",  XLYLK(19,528,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4118 {"bcctrl-", XLYLK(19,528,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4119 {"bcctr+",  XLYLK(19,528,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4120 {"bcctrl+", XLYLK(19,528,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
4121 {"bcctr",   XLLK(19,528,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4122 {"bcc",     XLLK(19,528,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4123 {"bcctrl",  XLLK(19,528,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
4124 {"bccl",    XLLK(19,528,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
4125
4126 {"rlwimi",      M(20,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4127 {"rlimi",       M(20,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4128
4129 {"rlwimi.",     M(20,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4130 {"rlimi.",      M(20,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4131
4132 {"rotlwi",      MME(21,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
4133 {"clrlwi",      MME(21,31,0),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
4134 {"rlwinm",      M(21,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4135 {"rlinm",       M(21,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4136 {"rotlwi.",     MME(21,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
4137 {"clrlwi.",     MME(21,31,1),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
4138 {"rlwinm.",     M(21,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4139 {"rlinm.",      M(21,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
4140
4141 {"rlmi",        M(22,0),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
4142 {"rlmi.",       M(22,1),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
4143
4144 {"rotlw",       MME(23,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
4145 {"rlwnm",       M(23,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4146 {"rlnm",        M(23,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4147 {"rotlw.",      MME(23,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
4148 {"rlwnm.",      M(23,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4149 {"rlnm.",       M(23,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
4150
4151 {"nop",         OP(24),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
4152 {"ori",         OP(24),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4153 {"oril",        OP(24),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4154
4155 {"oris",        OP(25),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4156 {"oriu",        OP(25),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4157
4158 {"xnop",        OP(26),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
4159 {"xori",        OP(26),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4160 {"xoril",       OP(26),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4161
4162 {"xoris",       OP(27),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4163 {"xoriu",       OP(27),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4164
4165 {"andi.",       OP(28),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4166 {"andil.",      OP(28),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4167
4168 {"andis.",      OP(29),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
4169 {"andiu.",      OP(29),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
4170
4171 {"rotldi",      MD(30,0,0),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
4172 {"clrldi",      MD(30,0,0),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
4173 {"rldicl",      MD(30,0,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4174 {"rotldi.",     MD(30,0,1),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
4175 {"clrldi.",     MD(30,0,1),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
4176 {"rldicl.",     MD(30,0,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4177
4178 {"rldicr",      MD(30,1,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
4179 {"rldicr.",     MD(30,1,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
4180
4181 {"rldic",       MD(30,2,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4182 {"rldic.",      MD(30,2,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4183
4184 {"rldimi",      MD(30,3,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4185 {"rldimi.",     MD(30,3,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
4186
4187 {"rotld",       MDS(30,8,0),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
4188 {"rldcl",       MDS(30,8,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
4189 {"rotld.",      MDS(30,8,1),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
4190 {"rldcl.",      MDS(30,8,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
4191
4192 {"rldcr",       MDS(30,9,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
4193 {"rldcr.",      MDS(30,9,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
4194
4195 {"cmpw",        XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
4196 {"cmpd",        XOPL(31,0,1),   XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
4197 {"cmp",         X(31,0),        XCMP_MASK,   PPC|PPCVLE, PPCNONE,       {BF, L, RA, RB}},
4198 {"cmp",         X(31,0),        XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
4199
4200 {"twlgt",       XTO(31,4,TOLGT), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4201 {"tlgt",        XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4202 {"twllt",       XTO(31,4,TOLLT), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4203 {"tllt",        XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4204 {"tweq",        XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4205 {"teq",         XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4206 {"twlge",       XTO(31,4,TOLGE), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4207 {"tlge",        XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4208 {"twlnl",       XTO(31,4,TOLNL), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4209 {"tlnl",        XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4210 {"twlle",       XTO(31,4,TOLLE), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4211 {"tlle",        XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4212 {"twlng",       XTO(31,4,TOLNG), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4213 {"tlng",        XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4214 {"twgt",        XTO(31,4,TOGT),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4215 {"tgt",         XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4216 {"twge",        XTO(31,4,TOGE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4217 {"tge",         XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4218 {"twnl",        XTO(31,4,TONL),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4219 {"tnl",         XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4220 {"twlt",        XTO(31,4,TOLT),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4221 {"tlt",         XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4222 {"twle",        XTO(31,4,TOLE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4223 {"tle",         XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4224 {"twng",        XTO(31,4,TONG),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4225 {"tng",         XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4226 {"twne",        XTO(31,4,TONE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
4227 {"tne",         XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
4228 {"trap",        XTO(31,4,TOU),   0xffffffff, PPCCOM|PPCVLE, PPCNONE,    {0}},
4229 {"tw",          X(31,4),         X_MASK, PPCCOM|PPCVLE, PPCNONE,        {TO, RA, RB}},
4230 {"t",           X(31,4),         X_MASK,     PWRCOM,    PPCNONE,        {TO, RA, RB}},
4231
4232 {"lvsl",        X(31,6),        X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4233 {"lvebx",       X(31,7),        X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4234 {"lbfcmx",      APU(31,7,0),    APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4235
4236 {"subfc",       XO(31,8,0,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4237 {"sf",          XO(31,8,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4238 {"subc",        XO(31,8,0,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
4239 {"subfc.",      XO(31,8,0,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4240 {"sf.",         XO(31,8,0,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4241 {"subc.",       XO(31,8,0,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
4242
4243 {"mulhdu",      XO(31,9,0,0),   XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4244 {"mulhdu.",     XO(31,9,0,1),   XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4245
4246 {"addc",        XO(31,10,0,0),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4247 {"a",           XO(31,10,0,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4248 {"addc.",       XO(31,10,0,1),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4249 {"a.",          XO(31,10,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4250
4251 {"mulhwu",      XO(31,11,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4252 {"mulhwu.",     XO(31,11,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4253
4254 {"isellt",      X(31,15),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4255
4256 {"tlbilxlpid",  XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
4257 {"tlbilxpid",   XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
4258 {"tlbilxva",    XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {RA0, RB}},
4259 {"tlbilx",      X(31,18),       X_MASK,   E500MC|PPCA2, PPCNONE,        {T, RA0, RB}},
4260
4261 {"mfcr",        XFXM(31,19,0,0), XFXFXM_MASK, POWER4,   PPCNONE,        {RT, FXM4}},
4262 {"mfcr",        XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4,        {RT}},
4263 {"mfocrf",      XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE,      {RT, FXM}},
4264
4265 {"lwarx",       X(31,20),       XEH_MASK,    PPC|PPCVLE, PPCNONE,       {RT, RA0, RB, EH}},
4266
4267 {"ldx",         X(31,21),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB}},
4268
4269 {"icbt",        X(31,22),       X_MASK,      BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA0, RB}},
4270
4271 {"lwzx",        X(31,23),       X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RT, RA0, RB}},
4272 {"lx",          X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4273
4274 {"slw",         XRC(31,24,0),   X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RA, RS, RB}},
4275 {"sl",          XRC(31,24,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4276 {"slw.",        XRC(31,24,1),   X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RA, RS, RB}},
4277 {"sl.",         XRC(31,24,1),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4278
4279 {"cntlzw",      XRC(31,26,0),   XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
4280 {"cntlz",       XRC(31,26,0),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4281 {"cntlzw.",     XRC(31,26,1),   XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
4282 {"cntlz.",      XRC(31,26,1),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4283
4284 {"sld",         XRC(31,27,0),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4285 {"sld.",        XRC(31,27,1),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4286
4287 {"and",         XRC(31,28,0),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4288 {"and.",        XRC(31,28,1),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4289
4290 {"maskg",       XRC(31,29,0),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
4291 {"maskg.",      XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
4292
4293 {"ldepx",       X(31,29),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4294 {"lwepx",       X(31,31),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4295
4296 {"cmplw",       XOPL(31,32,0),  XCMPL_MASK,  PPCCOM|PPCVLE, PPCNONE,    {OBF, RA, RB}},
4297 {"cmpld",       XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
4298 {"cmpl",        X(31,32),       XCMP_MASK,   PPC|PPCVLE, PPCNONE,       {BF, L, RA, RB}},
4299 {"cmpl",        X(31,32),       XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
4300
4301 {"lvsr",        X(31,38),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4302 {"lvehx",       X(31,39),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4303 {"lhfcmx",      APU(31,39,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4304
4305 {"mviwsplt",    X(31,46),       X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
4306
4307 {"iselgt",      X(31,47),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4308
4309 {"lvewx",       X(31,71),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4310
4311 {"addg6s",      XO(31,74,0,0),  XO_MASK,     POWER6,    PPCNONE,        {RT, RA, RB}},
4312
4313 {"iseleq",      X(31,79),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
4314
4315 {"isel",        XISEL(31,15), XISEL_MASK, PPCISEL|TITAN|PPCVLE, PPCNONE, {RT, RA0, RB, CRB}},
4316
4317 {"subf",        XO(31,40,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4318 {"sub",         XO(31,40,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RB, RA}},
4319 {"subf.",       XO(31,40,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4320 {"sub.",        XO(31,40,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RB, RA}},
4321
4322 {"eratilx",     X(31,51),       X_MASK,      PPCA2,     PPCNONE,        {ERAT_T, RA, RB}},
4323
4324 {"lbarx",       X(31,52),       XEH_MASK,    POWER7|PPCVLE, PPCNONE,    {RT, RA0, RB, EH}},
4325
4326 {"ldux",        X(31,53),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RAL, RB}},
4327
4328 {"dcbst",       X(31,54),       XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
4329
4330 {"lwzux",       X(31,55),       X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RT, RAL, RB}},
4331 {"lux",         X(31,55),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4332
4333 {"cntlzd",      XRC(31,58,0),   XRB_MASK,    PPC64|PPCVLE, PPCNONE,     {RA, RS}},
4334 {"cntlzd.",     XRC(31,58,1),   XRB_MASK,    PPC64|PPCVLE, PPCNONE,     {RA, RS}},
4335
4336 {"andc",        XRC(31,60,0),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4337 {"andc.",       XRC(31,60,1),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4338
4339 {"waitrsv",     X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
4340 {"waitimpl",    X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
4341 {"wait",        X(31,62),       XWC_MASK,    POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
4342
4343 {"dcbstep",     XRT(31,63,0),   XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
4344
4345 {"tdlgt",       XTO(31,68,TOLGT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4346 {"tdllt",       XTO(31,68,TOLLT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4347 {"tdeq",        XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4348 {"tdlge",       XTO(31,68,TOLGE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4349 {"tdlnl",       XTO(31,68,TOLNL), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4350 {"tdlle",       XTO(31,68,TOLLE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4351 {"tdlng",       XTO(31,68,TOLNG), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4352 {"tdgt",        XTO(31,68,TOGT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4353 {"tdge",        XTO(31,68,TOGE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4354 {"tdnl",        XTO(31,68,TONL),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4355 {"tdlt",        XTO(31,68,TOLT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4356 {"tdle",        XTO(31,68,TOLE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4357 {"tdng",        XTO(31,68,TONG),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4358 {"tdne",        XTO(31,68,TONE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
4359 {"td",          X(31,68),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {TO, RA, RB}},
4360
4361 {"lwfcmx",      APU(31,71,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4362 {"mulhd",       XO(31,73,0,0),  XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4363 {"mulhd.",      XO(31,73,0,1),  XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4364
4365 {"mulhw",       XO(31,75,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4366 {"mulhw.",      XO(31,75,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
4367
4368 {"dlmzb",       XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
4369 {"dlmzb.",      XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
4370
4371 {"mtsrd",       X(31,82),  XRB_MASK|(1<<20), PPC64,     PPCNONE,        {SR, RS}},
4372
4373 {"mfmsr",       X(31,83),       XRARB_MASK,  COM|PPCVLE, PPCNONE,       {RT}},
4374
4375 {"ldarx",       X(31,84),       XEH_MASK,    PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB, EH}},
4376
4377 {"dcbfl",       XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA0, RB}},
4378 {"dcbf",        X(31,86),       XLRT_MASK,   PPC|PPCVLE, PPCNONE,       {RA0, RB, L}},
4379
4380 {"lbzx",        X(31,87),       X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
4381
4382 {"lbepx",       X(31,95),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4383
4384 {"dni",         XRC(31,97,1),   XRB_MASK,    E6500,     PPCNONE,        {DUI, DCTL}},
4385
4386 {"lvx",         X(31,103),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4387 {"lqfcmx",      APU(31,103,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4388
4389 {"neg",         XO(31,104,0,0), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
4390 {"neg.",        XO(31,104,0,1), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
4391
4392 {"mul",         XO(31,107,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4393 {"mul.",        XO(31,107,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4394
4395 {"mvidsplt",    X(31,110),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
4396
4397 {"mtsrdin",     X(31,114),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
4398
4399 {"lharx",       X(31,116),      XEH_MASK,    POWER7|PPCVLE, PPCNONE,    {RT, RA0, RB, EH}},
4400
4401 {"clf",         X(31,118),      XTO_MASK,    POWER,     PPCNONE,        {RA, RB}},
4402
4403 {"lbzux",       X(31,119),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
4404
4405 {"popcntb",     X(31,122),      XRB_MASK,    POWER5|PPCVLE, PPCNONE,    {RA, RS}},
4406
4407 {"not",         XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4408 {"nor",         XRC(31,124,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4409 {"not.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4410 {"nor.",        XRC(31,124,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4411
4412 {"dcbfep",      XRT(31,127,0),  XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
4413
4414 {"wrtee",       X(31,131),      XRARB_MASK,  PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
4415
4416 {"dcbtstls",    X(31,134),      X_MASK,      PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4417
4418 {"stvebx",      X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4419 {"stbfcmx",     APU(31,135,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4420
4421 {"subfe",       XO(31,136,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4422 {"sfe",         XO(31,136,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4423 {"subfe.",      XO(31,136,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4424 {"sfe.",        XO(31,136,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4425
4426 {"adde",        XO(31,138,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4427 {"ae",          XO(31,138,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4428 {"adde.",       XO(31,138,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4429 {"ae.",         XO(31,138,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4430
4431 {"dcbtstlse",   X(31,142),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
4432
4433 {"mtcr",        XFXM(31,144,0xff,0), XRARB_MASK, COM,   PPCNONE,        {RS}},
4434 {"mtcrf",       XFXM(31,144,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE,     {FXM, RS}},
4435 {"mtocrf",      XFXM(31,144,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE,     {FXM, RS}},
4436
4437 {"mtmsr",       X(31,146),      XRLARB_MASK, COM|PPCVLE, PPCNONE,       {RS, A_L}},
4438
4439 {"eratsx",      XRC(31,147,0),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4440 {"eratsx.",     XRC(31,147,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4441
4442 {"stdx",        X(31,149),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RA0, RB}},
4443
4444 {"stwcx.",      XRC(31,150,1),  X_MASK,      PPC|PPCVLE, PPCNONE,       {RS, RA0, RB}},
4445
4446 {"stwx",        X(31,151),      X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RS, RA0, RB}},
4447 {"stx",         X(31,151),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA, RB}},
4448
4449 {"slq",         XRC(31,152,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4450 {"slq.",        XRC(31,152,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4451
4452 {"sle",         XRC(31,153,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4453 {"sle.",        XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4454
4455 {"prtyw",       X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
4456
4457 {"stdepx",      X(31,157),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4458
4459 {"stwepx",      X(31,159),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4460
4461 {"wrteei",      X(31,163),      XE_MASK,     PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}},
4462
4463 {"dcbtls",      X(31,166),      X_MASK,      PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4464
4465 {"stvehx",      X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4466 {"sthfcmx",     APU(31,167,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4467
4468 {"dcbtlse",     X(31,174),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
4469
4470 {"mtmsrd",      X(31,178),      XRLARB_MASK, PPC64,     PPCNONE,        {RS, A_L}},
4471
4472 {"eratre",      X(31,179),      X_MASK,      PPCA2,     PPCNONE,        {RT, RA, WS}},
4473
4474 {"stdux",       X(31,181),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RAS, RB}},
4475
4476 {"wchkall",     X(31,182),      X_MASK,      PPCA2,     PPCNONE,        {OBF}},
4477
4478 {"stwux",       X(31,183),      X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RS, RAS, RB}},
4479 {"stux",        X(31,183),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4480
4481 {"sliq",        XRC(31,184,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4482 {"sliq.",       XRC(31,184,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4483
4484 {"prtyd",       X(31,186),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
4485
4486 {"icblq.",      XRC(31,198,1),  X_MASK,      E6500,     PPCNONE,        {CT, RA0, RB}},
4487
4488 {"stvewx",      X(31,199),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
4489 {"stwfcmx",     APU(31,199,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4490
4491 {"subfze",      XO(31,200,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4492 {"sfze",        XO(31,200,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4493 {"subfze.",     XO(31,200,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4494 {"sfze.",       XO(31,200,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4495
4496 {"addze",       XO(31,202,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4497 {"aze",         XO(31,202,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4498 {"addze.",      XO(31,202,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4499 {"aze.",        XO(31,202,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4500
4501 {"msgsnd",      XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
4502
4503 {"mtsr",        X(31,210), XRB_MASK|(1<<20), COM,       NON32,          {SR, RS}},
4504
4505 {"eratwe",      X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
4506
4507 {"ldawx.",      XRC(31,212,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
4508
4509 {"stdcx.",      XRC(31,214,1),  X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RA0, RB}},
4510
4511 {"stbx",        X(31,215),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RA0, RB}},
4512
4513 {"sllq",        XRC(31,216,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4514 {"sllq.",       XRC(31,216,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4515
4516 {"sleq",        XRC(31,217,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4517 {"sleq.",       XRC(31,217,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4518
4519 {"stbepx",      X(31,223),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4520
4521 {"icblc",       X(31,230),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4522
4523 {"stvx",        X(31,231),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VS, RA0, RB}},
4524 {"stqfcmx",     APU(31,231,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4525
4526 {"subfme",      XO(31,232,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4527 {"sfme",        XO(31,232,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4528 {"subfme.",     XO(31,232,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4529 {"sfme.",       XO(31,232,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4530
4531 {"mulld",       XO(31,233,0,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4532 {"mulld.",      XO(31,233,0,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
4533
4534 {"addme",       XO(31,234,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4535 {"ame",         XO(31,234,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4536 {"addme.",      XO(31,234,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
4537 {"ame.",        XO(31,234,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4538
4539 {"mullw",       XO(31,235,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4540 {"muls",        XO(31,235,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4541 {"mullw.",      XO(31,235,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4542 {"muls.",       XO(31,235,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4543
4544 {"icblce",      X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
4545 {"msgclr",      XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}},
4546 {"mtsrin",      X(31,242),      XRA_MASK,    PPC,       NON32,          {RS, RB}},
4547 {"mtsri",       X(31,242),      XRA_MASK,    POWER,     NON32,          {RS, RB}},
4548
4549 {"dcbtstt",     XRT(31,246,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA0, RB}},
4550 {"dcbtst",      X(31,246),      X_MASK,      POWER4,    PPCNONE,        {RA0, RB, CT}},
4551 {"dcbtst",      X(31,246),      X_MASK,      PPC|PPCVLE, POWER4,        {CT, RA0, RB}},
4552
4553 {"stbux",       X(31,247),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RAS, RB}},
4554
4555 {"slliq",       XRC(31,248,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4556 {"slliq.",      XRC(31,248,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4557
4558 {"bpermd",      X(31,252),      X_MASK,   POWER7|PPCA2, PPCNONE,        {RA, RS, RB}},
4559
4560 {"dcbtstep",    XRT(31,255,0),  X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4561
4562 {"mfdcrx",      X(31,259),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}},
4563 {"mfdcrx.",     XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
4564
4565 {"lvexbx",      X(31,261),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4566
4567 {"icbt",        X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
4568
4569 {"lvepxl",      X(31,263),      X_MASK,      PPCVEC2|PPCVLE, PPCNONE,   {VD, RA0, RB}},
4570
4571 {"ldfcmx",      APU(31,263,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4572 {"doz",         XO(31,264,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4573 {"doz.",        XO(31,264,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4574
4575 {"add",         XO(31,266,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4576 {"cax",         XO(31,266,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4577 {"add.",        XO(31,266,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
4578 {"cax.",        XO(31,266,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4579
4580 {"ehpriv",      X(31,270),      0xffffffff, E500MC|PPCA2|PPCVLE, PPCNONE, {0}},
4581
4582 {"tlbiel",      X(31,274),      XRTLRA_MASK, POWER4,    PPC476,         {RB, L}},
4583
4584 {"mfapidi",     X(31,275),      X_MASK,      BOOKE,     TITAN,          {RT, RA}},
4585
4586 {"lscbx",       XRC(31,277,0),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
4587 {"lscbx.",      XRC(31,277,1),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
4588
4589 {"dcbtt",       XRT(31,278,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA0, RB}},
4590 {"dcbt",        X(31,278),      X_MASK,      POWER4,    PPCNONE,        {RA0, RB, CT}},
4591 {"dcbt",        X(31,278),      X_MASK,      PPC|PPCVLE, POWER4,        {CT, RA0, RB}},
4592
4593 {"lhzx",        X(31,279),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
4594
4595 {"cdtbcd",      X(31,282),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
4596
4597 {"eqv",         XRC(31,284,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4598 {"eqv.",        XRC(31,284,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4599
4600 {"lhepx",       X(31,287),      X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4601
4602 {"mfdcrux",     X(31,291),      X_MASK,      PPC464|PPCVLE, PPCNONE,    {RS, RA}},
4603
4604 {"lvexhx",      X(31,293),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4605 {"lvepx",       X(31,295),      X_MASK,      PPCVEC2|PPCVLE, PPCNONE,   {VD, RA0, RB}},
4606
4607 {"tlbie",       X(31,306),      XRTLRA_MASK, PPC,       TITAN,          {RB, L}},
4608 {"tlbi",        X(31,306),      XRT_MASK,    POWER,     PPCNONE,        {RA0, RB}},
4609
4610 {"eciwx",       X(31,310),      X_MASK,      PPC,       TITAN,          {RT, RA0, RB}},
4611
4612 {"lhzux",       X(31,311),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
4613
4614 {"cbcdtd",      X(31,314),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
4615
4616 {"xor",         XRC(31,316,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4617 {"xor.",        XRC(31,316,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4618
4619 {"dcbtep",      XRT(31,319,0),  X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
4620
4621 {"mfexisr",     XSPR(31,323, 64), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4622 {"mfexier",     XSPR(31,323, 66), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4623 {"mfbr0",       XSPR(31,323,128), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4624 {"mfbr1",       XSPR(31,323,129), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4625 {"mfbr2",       XSPR(31,323,130), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4626 {"mfbr3",       XSPR(31,323,131), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4627 {"mfbr4",       XSPR(31,323,132), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4628 {"mfbr5",       XSPR(31,323,133), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4629 {"mfbr6",       XSPR(31,323,134), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4630 {"mfbr7",       XSPR(31,323,135), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4631 {"mfbear",      XSPR(31,323,144), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4632 {"mfbesr",      XSPR(31,323,145), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4633 {"mfiocr",      XSPR(31,323,160), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4634 {"mfdmacr0",    XSPR(31,323,192), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4635 {"mfdmact0",    XSPR(31,323,193), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4636 {"mfdmada0",    XSPR(31,323,194), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4637 {"mfdmasa0",    XSPR(31,323,195), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4638 {"mfdmacc0",    XSPR(31,323,196), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4639 {"mfdmacr1",    XSPR(31,323,200), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4640 {"mfdmact1",    XSPR(31,323,201), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4641 {"mfdmada1",    XSPR(31,323,202), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4642 {"mfdmasa1",    XSPR(31,323,203), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4643 {"mfdmacc1",    XSPR(31,323,204), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4644 {"mfdmacr2",    XSPR(31,323,208), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4645 {"mfdmact2",    XSPR(31,323,209), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4646 {"mfdmada2",    XSPR(31,323,210), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4647 {"mfdmasa2",    XSPR(31,323,211), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4648 {"mfdmacc2",    XSPR(31,323,212), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4649 {"mfdmacr3",    XSPR(31,323,216), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4650 {"mfdmact3",    XSPR(31,323,217), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4651 {"mfdmada3",    XSPR(31,323,218), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4652 {"mfdmasa3",    XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4653 {"mfdmacc3",    XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4654 {"mfdmasr",     XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4655 {"mfdcr",       X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RT, SPR}},
4656 {"mfdcr.",      XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
4657
4658 {"lvexwx",      X(31,325),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
4659
4660 {"dcread",      X(31,326),      X_MASK,  PPC476|TITAN,  PPCNONE,        {RT, RA0, RB}},
4661
4662 {"div",         XO(31,331,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4663 {"div.",        XO(31,331,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4664
4665 {"lxvdsx",      X(31,332),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
4666
4667 {"mfpmr",       X(31,334),      X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}},
4668 {"mftmr",       X(31,366),      X_MASK, PPCTMR|E6500,   PPCNONE,        {RT, TMR}},
4669
4670 {"mfmq",        XSPR(31,339,  0), XSPR_MASK, M601,      PPCNONE,        {RT}},
4671 {"mfxer",       XSPR(31,339,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
4672 {"mfrtcu",      XSPR(31,339,  4), XSPR_MASK, COM,       TITAN,          {RT}},
4673 {"mfrtcl",      XSPR(31,339,  5), XSPR_MASK, COM,       TITAN,          {RT}},
4674 {"mfdec",       XSPR(31,339,  6), XSPR_MASK, MFDEC1,    PPCNONE,        {RT}},
4675 {"mflr",        XSPR(31,339,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
4676 {"mfctr",       XSPR(31,339,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
4677 {"mftid",       XSPR(31,339, 17), XSPR_MASK, POWER,     PPCNONE,        {RT}},
4678 {"mfdsisr",     XSPR(31,339, 18), XSPR_MASK, COM,       TITAN,          {RT}},
4679 {"mfdar",       XSPR(31,339, 19), XSPR_MASK, COM,       TITAN,          {RT}},
4680 {"mfdec",       XSPR(31,339, 22), XSPR_MASK, MFDEC2,    MFDEC1,         {RT}},
4681 {"mfsdr0",      XSPR(31,339, 24), XSPR_MASK, POWER,     PPCNONE,        {RT}},
4682 {"mfsdr1",      XSPR(31,339, 25), XSPR_MASK, COM,       TITAN,          {RT}},
4683 {"mfsrr0",      XSPR(31,339, 26), XSPR_MASK, COM,       PPCNONE,        {RT}},
4684 {"mfsrr1",      XSPR(31,339, 27), XSPR_MASK, COM,       PPCNONE,        {RT}},
4685 {"mfcfar",      XSPR(31,339, 28), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
4686 {"mfpid",       XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4687 {"mfcsrr0",     XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4688 {"mfcsrr1",     XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4689 {"mfdear",      XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4690 {"mfesr",       XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4691 {"mfivpr",      XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4692 {"mfcmpa",      XSPR(31,339,144), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4693 {"mfcmpb",      XSPR(31,339,145), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4694 {"mfcmpc",      XSPR(31,339,146), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4695 {"mfcmpd",      XSPR(31,339,147), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4696 {"mficr",       XSPR(31,339,148), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4697 {"mfder",       XSPR(31,339,149), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4698 {"mfcounta",    XSPR(31,339,150), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4699 {"mfcountb",    XSPR(31,339,151), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4700 {"mfcmpe",      XSPR(31,339,152), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4701 {"mfcmpf",      XSPR(31,339,153), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4702 {"mfcmpg",      XSPR(31,339,154), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4703 {"mfcmph",      XSPR(31,339,155), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4704 {"mflctrl1",    XSPR(31,339,156), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4705 {"mflctrl2",    XSPR(31,339,157), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4706 {"mfictrl",     XSPR(31,339,158), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4707 {"mfbar",       XSPR(31,339,159), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4708 {"mfvrsave",    XSPR(31,339,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RT}},
4709 {"mfusprg0",    XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4710 {"mfsprg",      XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE,      {RT, SPRG}},
4711 {"mfsprg4",     XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4712 {"mfsprg5",     XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4713 {"mfsprg6",     XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4714 {"mfsprg7",     XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
4715 {"mftb",        XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4716 {"mftbl",       XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4717 {"mftbu",       XSPR(31,339,269), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4718 {"mfsprg0",     XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4719 {"mfsprg1",     XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4720 {"mfsprg2",     XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4721 {"mfsprg3",     XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4722 {"mfasr",       XSPR(31,339,280), XSPR_MASK, PPC64,     PPCNONE,        {RT}},
4723 {"mfear",       XSPR(31,339,282), XSPR_MASK, PPC,       TITAN,          {RT}},
4724 {"mfpir",       XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4725 {"mfpvr",       XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
4726 {"mfdbsr",      XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4727 {"mfdbcr0",     XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4728 {"mfdbcr1",     XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4729 {"mfdbcr2",     XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4730 {"mfiac1",      XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4731 {"mfiac2",      XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4732 {"mfiac3",      XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4733 {"mfiac4",      XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4734 {"mfdac1",      XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4735 {"mfdac2",      XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4736 {"mfdvc1",      XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4737 {"mfdvc2",      XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4738 {"mftsr",       XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4739 {"mftcr",       XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4740 {"mfivor0",     XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4741 {"mfivor1",     XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4742 {"mfivor2",     XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4743 {"mfivor3",     XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4744 {"mfivor4",     XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4745 {"mfivor5",     XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4746 {"mfivor6",     XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4747 {"mfivor7",     XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4748 {"mfivor8",     XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4749 {"mfivor9",     XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4750 {"mfivor10",    XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4751 {"mfivor11",    XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4752 {"mfivor12",    XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4753 {"mfivor13",    XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4754 {"mfivor14",    XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4755 {"mfivor15",    XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
4756 {"mfspefscr",   XSPR(31,339,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4757 {"mfbbear",     XSPR(31,339,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
4758 {"mfbbtar",     XSPR(31,339,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
4759 {"mfivor32",    XSPR(31,339,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4760 {"mfibatu",     XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4761 {"mfivor33",    XSPR(31,339,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4762 {"mfibatl",     XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4763 {"mfivor34",    XSPR(31,339,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
4764 {"mfivor35",    XSPR(31,339,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RT}},
4765 {"mfdbatu",     XSPR(31,339,536), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4766 {"mfdbatl",     XSPR(31,339,537), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
4767 {"mfic_cst",    XSPR(31,339,560), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4768 {"mfic_adr",    XSPR(31,339,561), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4769 {"mfic_dat",    XSPR(31,339,562), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4770 {"mfdc_cst",    XSPR(31,339,568), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4771 {"mfdc_adr",    XSPR(31,339,569), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4772 {"mfdc_dat",    XSPR(31,339,570), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4773 {"mfmcsrr0",    XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4774 {"mfmcsrr1",    XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4775 {"mfmcsr",      XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
4776 {"mfmcar",      XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  TITAN,          {RT}},
4777 {"mfdpdr",      XSPR(31,339,630), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4778 {"mfdpir",      XSPR(31,339,631), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4779 {"mfimmr",      XSPR(31,339,638), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4780 {"mfmi_ctr",    XSPR(31,339,784), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4781 {"mfmi_ap",     XSPR(31,339,786), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4782 {"mfmi_epn",    XSPR(31,339,787), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4783 {"mfmi_twc",    XSPR(31,339,789), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4784 {"mfmi_rpn",    XSPR(31,339,790), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4785 {"mfmd_ctr",    XSPR(31,339,792), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4786 {"mfm_casid",   XSPR(31,339,793), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4787 {"mfmd_ap",     XSPR(31,339,794), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4788 {"mfmd_epn",    XSPR(31,339,795), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4789 {"mfmd_twb",    XSPR(31,339,796), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4790 {"mfmd_twc",    XSPR(31,339,797), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4791 {"mfmd_rpn",    XSPR(31,339,798), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4792 {"mfm_tw",      XSPR(31,339,799), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4793 {"mfmi_dbcam",  XSPR(31,339,816), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4794 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4795 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4796 {"mfmd_dbcam",  XSPR(31,339,824), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4797 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4798 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4799 {"mfivndx",     XSPR(31,339,880), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4800 {"mfdvndx",     XSPR(31,339,881), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4801 {"mfivlim",     XSPR(31,339,882), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4802 {"mfdvlim",     XSPR(31,339,883), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4803 {"mfclcsr",     XSPR(31,339,884), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4804 {"mfccr1",      XSPR(31,339,888), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4805 {"mfppr",       XSPR(31,339,896), XSPR_MASK, POWER7,    PPCNONE,        {RT}},
4806 {"mfppr32",     XSPR(31,339,898), XSPR_MASK, POWER7,    PPCNONE,        {RT}},
4807 {"mfrstcfg",    XSPR(31,339,923), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4808 {"mfdcdbtrl",   XSPR(31,339,924), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4809 {"mfdcdbtrh",   XSPR(31,339,925), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4810 {"mficdbtr",    XSPR(31,339,927), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4811 {"mfummcr0",    XSPR(31,339,936), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4812 {"mfupmc1",     XSPR(31,339,937), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4813 {"mfupmc2",     XSPR(31,339,938), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4814 {"mfusia",      XSPR(31,339,939), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4815 {"mfummcr1",    XSPR(31,339,940), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4816 {"mfupmc3",     XSPR(31,339,941), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4817 {"mfupmc4",     XSPR(31,339,942), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4818 {"mfzpr",       XSPR(31,339,944), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4819 {"mfpid",       XSPR(31,339,945), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4820 {"mfmmucr",     XSPR(31,339,946), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4821 {"mfccr0",      XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RT}},
4822 {"mfiac3",      XSPR(31,339,948), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4823 {"mfiac4",      XSPR(31,339,949), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4824 {"mfdvc1",      XSPR(31,339,950), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4825 {"mfdvc2",      XSPR(31,339,951), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4826 {"mfmmcr0",     XSPR(31,339,952), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4827 {"mfpmc1",      XSPR(31,339,953), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4828 {"mfsgr",       XSPR(31,339,953), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4829 {"mfdcwr",      XSPR(31,339,954), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4830 {"mfpmc2",      XSPR(31,339,954), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4831 {"mfsia",       XSPR(31,339,955), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4832 {"mfsler",      XSPR(31,339,955), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4833 {"mfmmcr1",     XSPR(31,339,956), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4834 {"mfsu0r",      XSPR(31,339,956), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4835 {"mfdbcr1",     XSPR(31,339,957), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4836 {"mfpmc3",      XSPR(31,339,957), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4837 {"mfpmc4",      XSPR(31,339,958), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4838 {"mficdbdr",    XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE,     {RT}},
4839 {"mfesr",       XSPR(31,339,980), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4840 {"mfdear",      XSPR(31,339,981), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4841 {"mfevpr",      XSPR(31,339,982), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4842 {"mfcdbcr",     XSPR(31,339,983), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4843 {"mftsr",       XSPR(31,339,984), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4844 {"mftcr",       XSPR(31,339,986), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4845 {"mfpit",       XSPR(31,339,987), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4846 {"mftbhi",      XSPR(31,339,988), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4847 {"mftblo",      XSPR(31,339,989), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4848 {"mfsrr2",      XSPR(31,339,990), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4849 {"mfsrr3",      XSPR(31,339,991), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4850 {"mfdbsr",      XSPR(31,339,1008), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4851 {"mfdbcr0",     XSPR(31,339,1010), XSPR_MASK, PPC405,   PPCNONE,        {RT}},
4852 {"mfdbdr",      XSPR(31,339,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
4853 {"mfiac1",      XSPR(31,339,1012), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4854 {"mfiac2",      XSPR(31,339,1013), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4855 {"mfdac1",      XSPR(31,339,1014), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4856 {"mfdac2",      XSPR(31,339,1015), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4857 {"mfl2cr",      XSPR(31,339,1017), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4858 {"mfdccr",      XSPR(31,339,1018), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4859 {"mficcr",      XSPR(31,339,1019), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4860 {"mfictc",      XSPR(31,339,1019), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4861 {"mfpbl1",      XSPR(31,339,1020), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4862 {"mfthrm1",     XSPR(31,339,1020), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4863 {"mfpbu1",      XSPR(31,339,1021), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4864 {"mfthrm2",     XSPR(31,339,1021), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4865 {"mfpbl2",      XSPR(31,339,1022), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4866 {"mfthrm3",     XSPR(31,339,1022), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4867 {"mfpbu2",      XSPR(31,339,1023), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4868 {"mfspr",       X(31,339),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, SPR}},
4869
4870 {"lwax",        X(31,341),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB}},
4871
4872 {"dst",         XDSS(31,342,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4873
4874 {"lhax",        X(31,343),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
4875
4876 {"lvxl",        X(31,359),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
4877
4878 {"abs",         XO(31,360,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4879 {"abs.",        XO(31,360,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4880
4881 {"divs",        XO(31,363,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4882 {"divs.",       XO(31,363,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4883
4884 {"tlbia",       X(31,370),      0xffffffff,  PPC,       TITAN,          {0}},
4885
4886 {"mftbl",       XSPR(31,371,268), XSPR_MASK, PPC,       NO371,          {RT}},
4887 {"mftbu",       XSPR(31,371,269), XSPR_MASK, PPC,       NO371,          {RT}},
4888 {"mftb",        X(31,371),      X_MASK,      PPC|PPCA2, NO371|POWER7,   {RT, TBR}},
4889
4890 {"lwaux",       X(31,373),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RAL, RB}},
4891
4892 {"dstst",       XDSS(31,374,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4893
4894 {"lhaux",       X(31,375),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
4895
4896 {"popcntw",     X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
4897
4898 {"mtdcrx",      X(31,387),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RA, RS}},
4899 {"mtdcrx.",     XRC(31,387,1),  X_MASK,      PPCA2,     PPCNONE,        {RA, RS}},
4900
4901 {"stvexbx",     X(31,389),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
4902
4903 {"dcblc",       X(31,390),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
4904 {"stdfcmx",     APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4905
4906 {"divdeu",      XO(31,393,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4907 {"divdeu.",     XO(31,393,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4908 {"divweu",      XO(31,395,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4909 {"divweu.",     XO(31,395,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4910
4911 {"dcblce",      X(31,398),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
4912
4913 {"slbmte",      X(31,402),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
4914
4915 {"icswx",       XRC(31,406,0),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
4916 {"icswx.",      XRC(31,406,1),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
4917
4918 {"sthx",        X(31,407),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RA0, RB}},
4919
4920 {"orc",         XRC(31,412,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4921 {"orc.",        XRC(31,412,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4922
4923 {"sthepx",      X(31,415),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
4924
4925 {"mtdcrux",     X(31,419),      X_MASK,      PPC464|PPCVLE, PPCNONE,    {RA, RS}},
4926
4927 {"stvexhx",     X(31,421),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
4928
4929 {"dcblq.",      XRC(31,422,1),  X_MASK,      E6500,     PPCNONE,        {CT, RA0, RB}},
4930
4931 {"divde",       XO(31,425,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4932 {"divde.",      XO(31,425,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4933 {"divwe",       XO(31,427,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4934 {"divwe.",      XO(31,427,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
4935
4936 {"slbie",       X(31,434),      XRTRA_MASK,  PPC64,     PPCNONE,        {RB}},
4937
4938 {"ecowx",       X(31,438),      X_MASK,      PPC,       TITAN,          {RT, RA0, RB}},
4939
4940 {"sthux",       X(31,439),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RAS, RB}},
4941
4942 {"mdors",       0x7f9ce378,     0xffffffff,  E500MC,    PPCNONE,        {0}},
4943
4944 {"miso",        0x7f5ad378,     0xffffffff,  E6500,     PPCNONE,        {0}},
4945
4946 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
4947    "or rX,rX,rX", with rX being r27, r29 and r30 respectively.  */
4948 {"yield",       0x7f7bdb78,     0xffffffff,  POWER7,     PPCNONE,       {0}},
4949 {"mdoio",       0x7fbdeb78,     0xffffffff,  POWER7,     PPCNONE,       {0}},
4950 {"mdoom",       0x7fdef378,     0xffffffff,  POWER7,     PPCNONE,       {0}},
4951 {"mr",          XRC(31,444,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RBS}},
4952 {"or",          XRC(31,444,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4953 {"mr.",         XRC(31,444,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RBS}},
4954 {"or.",         XRC(31,444,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
4955
4956 {"mtexisr",     XSPR(31,451, 64), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4957 {"mtexier",     XSPR(31,451, 66), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4958 {"mtbr0",       XSPR(31,451,128), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4959 {"mtbr1",       XSPR(31,451,129), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4960 {"mtbr2",       XSPR(31,451,130), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4961 {"mtbr3",       XSPR(31,451,131), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4962 {"mtbr4",       XSPR(31,451,132), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4963 {"mtbr5",       XSPR(31,451,133), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4964 {"mtbr6",       XSPR(31,451,134), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4965 {"mtbr7",       XSPR(31,451,135), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4966 {"mtbear",      XSPR(31,451,144), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4967 {"mtbesr",      XSPR(31,451,145), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4968 {"mtiocr",      XSPR(31,451,160), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4969 {"mtdmacr0",    XSPR(31,451,192), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4970 {"mtdmact0",    XSPR(31,451,193), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4971 {"mtdmada0",    XSPR(31,451,194), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4972 {"mtdmasa0",    XSPR(31,451,195), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4973 {"mtdmacc0",    XSPR(31,451,196), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4974 {"mtdmacr1",    XSPR(31,451,200), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4975 {"mtdmact1",    XSPR(31,451,201), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4976 {"mtdmada1",    XSPR(31,451,202), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4977 {"mtdmasa1",    XSPR(31,451,203), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4978 {"mtdmacc1",    XSPR(31,451,204), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4979 {"mtdmacr2",    XSPR(31,451,208), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4980 {"mtdmact2",    XSPR(31,451,209), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4981 {"mtdmada2",    XSPR(31,451,210), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4982 {"mtdmasa2",    XSPR(31,451,211), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4983 {"mtdmacc2",    XSPR(31,451,212), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4984 {"mtdmacr3",    XSPR(31,451,216), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4985 {"mtdmact3",    XSPR(31,451,217), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4986 {"mtdmada3",    XSPR(31,451,218), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4987 {"mtdmasa3",    XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4988 {"mtdmacc3",    XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4989 {"mtdmasr",     XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4990 {"mtdcr",       X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {SPR, RS}},
4991 {"mtdcr.",      XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
4992
4993 {"stvexwx",     X(31,453),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
4994
4995 {"dccci",       X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
4996 {"dci",         X(31,454),      XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
4997
4998 {"divdu",       XO(31,457,0,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
4999 {"divdu.",      XO(31,457,0,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5000
5001 {"divwu",       XO(31,459,0,0), XO_MASK,  PPC|PPCVLE,   PPCNONE,        {RT, RA, RB}},
5002 {"divwu.",      XO(31,459,0,1), XO_MASK,  PPC|PPCVLE,   PPCNONE,        {RT, RA, RB}},
5003
5004 {"mtpmr",       X(31,462),      X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}},
5005 {"mttmr",       X(31,494),      X_MASK, PPCTMR|E6500,   PPCNONE,        {TMR, RS}},
5006
5007 {"mtmq",        XSPR(31,467,  0), XSPR_MASK, M601,      PPCNONE,        {RS}},
5008 {"mtxer",       XSPR(31,467,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5009 {"mtlr",        XSPR(31,467,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5010 {"mtctr",       XSPR(31,467,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5011 {"mttid",       XSPR(31,467, 17), XSPR_MASK, POWER,     PPCNONE,        {RS}},
5012 {"mtdsisr",     XSPR(31,467, 18), XSPR_MASK, COM,       TITAN,          {RS}},
5013 {"mtdar",       XSPR(31,467, 19), XSPR_MASK, COM,       TITAN,          {RS}},
5014 {"mtrtcu",      XSPR(31,467, 20), XSPR_MASK, COM,       TITAN,          {RS}},
5015 {"mtrtcl",      XSPR(31,467, 21), XSPR_MASK, COM,       TITAN,          {RS}},
5016 {"mtdec",       XSPR(31,467, 22), XSPR_MASK, COM,       PPCNONE,        {RS}},
5017 {"mtsdr0",      XSPR(31,467, 24), XSPR_MASK, POWER,     PPCNONE,        {RS}},
5018 {"mtsdr1",      XSPR(31,467, 25), XSPR_MASK, COM,       TITAN,          {RS}},
5019 {"mtsrr0",      XSPR(31,467, 26), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5020 {"mtsrr1",      XSPR(31,467, 27), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
5021 {"mtcfar",      XSPR(31,467, 28), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
5022 {"mtpid",       XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5023 {"mtdecar",     XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5024 {"mtcsrr0",     XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5025 {"mtcsrr1",     XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5026 {"mtdear",      XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5027 {"mtesr",       XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5028 {"mtivpr",      XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5029 {"mtcmpa",      XSPR(31,467,144), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5030 {"mtcmpb",      XSPR(31,467,145), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5031 {"mtcmpc",      XSPR(31,467,146), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5032 {"mtcmpd",      XSPR(31,467,147), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5033 {"mticr",       XSPR(31,467,148), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5034 {"mtder",       XSPR(31,467,149), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5035 {"mtcounta",    XSPR(31,467,150), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5036 {"mtcountb",    XSPR(31,467,151), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5037 {"mtcmpe",      XSPR(31,467,152), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5038 {"mtcmpf",      XSPR(31,467,153), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5039 {"mtcmpg",      XSPR(31,467,154), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5040 {"mtcmph",      XSPR(31,467,155), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5041 {"mtlctrl1",    XSPR(31,467,156), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5042 {"mtlctrl2",    XSPR(31,467,157), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5043 {"mtictrl",     XSPR(31,467,158), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5044 {"mtbar",       XSPR(31,467,159), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
5045 {"mtvrsave",    XSPR(31,467,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RS}},
5046 {"mtusprg0",    XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5047 {"mtsprg",      XSPR(31,467,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE,      {SPRG, RS}},
5048 {"mtsprg0",     XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5049 {"mtsprg1",     XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5050 {"mtsprg2",     XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5051 {"mtsprg3",     XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
5052 {"mtsprg4",     XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5053 {"mtsprg5",     XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5054 {"mtsprg6",     XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5055 {"mtsprg7",     XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
5056 {"mtasr",       XSPR(31,467,280), XSPR_MASK, PPC64,     PPCNONE,        {RS}},
5057 {"mtear",       XSPR(31,467,282), XSPR_MASK, PPC,       TITAN,          {RS}},
5058 {"mttbl",       XSPR(31,467,284), XSPR_MASK, PPC,       PPCNONE,        {RS}},
5059 {"mttbu",       XSPR(31,467,285), XSPR_MASK, PPC,       PPCNONE,        {RS}},
5060 {"mtdbsr",      XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5061 {"mtdbcr0",     XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5062 {"mtdbcr1",     XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5063 {"mtdbcr2",     XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5064 {"mtiac1",      XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5065 {"mtiac2",      XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5066 {"mtiac3",      XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5067 {"mtiac4",      XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5068 {"mtdac1",      XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5069 {"mtdac2",      XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5070 {"mtdvc1",      XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5071 {"mtdvc2",      XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5072 {"mttsr",       XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5073 {"mttcr",       XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5074 {"mtivor0",     XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5075 {"mtivor1",     XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5076 {"mtivor2",     XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5077 {"mtivor3",     XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5078 {"mtivor4",     XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5079 {"mtivor5",     XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5080 {"mtivor6",     XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5081 {"mtivor7",     XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5082 {"mtivor8",     XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5083 {"mtivor9",     XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5084 {"mtivor10",    XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5085 {"mtivor11",    XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5086 {"mtivor12",    XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5087 {"mtivor13",    XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5088 {"mtivor14",    XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5089 {"mtivor15",    XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
5090 {"mtspefscr",   XSPR(31,467,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5091 {"mtbbear",     XSPR(31,467,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
5092 {"mtbbtar",     XSPR(31,467,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
5093 {"mtivor32",    XSPR(31,467,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5094 {"mtibatu",     XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5095 {"mtivor33",    XSPR(31,467,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5096 {"mtibatl",     XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5097 {"mtivor34",    XSPR(31,467,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
5098 {"mtivor35",    XSPR(31,467,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RS}},
5099 {"mtdbatu",     XSPR(31,467,536), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5100 {"mtdbatl",     XSPR(31,467,537), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
5101 {"mtmcsrr0",    XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE,  {RS}},
5102 {"mtmcsrr1",    XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE,  {RS}},
5103 {"mtmcsr",      XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
5104 {"mtivndx",     XSPR(31,467,880), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5105 {"mtdvndx",     XSPR(31,467,881), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5106 {"mtivlim",     XSPR(31,467,882), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5107 {"mtdvlim",     XSPR(31,467,883), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5108 {"mtclcsr",     XSPR(31,467,884), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5109 {"mtccr1",      XSPR(31,467,888), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5110 {"mtppr",       XSPR(31,467,896), XSPR_MASK, POWER7,    PPCNONE,        {RS}},
5111 {"mtppr32",     XSPR(31,467,898), XSPR_MASK, POWER7,    PPCNONE,        {RS}},
5112 {"mtummcr0",    XSPR(31,467,936), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5113 {"mtupmc1",     XSPR(31,467,937), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5114 {"mtupmc2",     XSPR(31,467,938), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5115 {"mtusia",      XSPR(31,467,939), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5116 {"mtummcr1",    XSPR(31,467,940), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5117 {"mtupmc3",     XSPR(31,467,941), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5118 {"mtupmc4",     XSPR(31,467,942), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5119 {"mtzpr",       XSPR(31,467,944), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5120 {"mtpid",       XSPR(31,467,945), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5121 {"mtrmmucr",    XSPR(31,467,946), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
5122 {"mtccr0",      XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RS}},
5123 {"mtiac3",      XSPR(31,467,948), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5124 {"mtiac4",      XSPR(31,467,949), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5125 {"mtdvc1",      XSPR(31,467,950), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5126 {"mtdvc2",      XSPR(31,467,951), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5127 {"mtmmcr0",     XSPR(31,467,952), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5128 {"mtpmc1",      XSPR(31,467,953), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5129 {"mtsgr",       XSPR(31,467,953), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5130 {"mtdcwr",      XSPR(31,467,954), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5131 {"mtpmc2",      XSPR(31,467,954), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5132 {"mtsia",       XSPR(31,467,955), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5133 {"mtsler",      XSPR(31,467,955), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5134 {"mtmmcr1",     XSPR(31,467,956), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5135 {"mtsu0r",      XSPR(31,467,956), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5136 {"mtdbcr1",     XSPR(31,467,957), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
5137 {"mtpmc3",      XSPR(31,467,957), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5138 {"mtpmc4",      XSPR(31,467,958), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
5139 {"mticdbdr",    XSPR(31,467,979), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5140 {"mtesr",       XSPR(31,467,980), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5141 {"mtdear",      XSPR(31,467,981), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5142 {"mtevpr",      XSPR(31,467,982), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5143 {"mtcdbcr",     XSPR(31,467,983), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5144 {"mttsr",       XSPR(31,467,984), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5145 {"mttcr",       XSPR(31,467,986), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5146 {"mtpit",       XSPR(31,467,987), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5147 {"mttbhi",      XSPR(31,467,988), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5148 {"mttblo",      XSPR(31,467,989), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5149 {"mtsrr2",      XSPR(31,467,990), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5150 {"mtsrr3",      XSPR(31,467,991), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
5151 {"mtdbsr",      XSPR(31,467,1008), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5152 {"mtdbdr",      XSPR(31,467,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
5153 {"mtdbcr0",     XSPR(31,467,1010), XSPR_MASK, PPC405,   PPCNONE,        {RS}},
5154 {"mtiac1",      XSPR(31,467,1012), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5155 {"mtiac2",      XSPR(31,467,1013), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5156 {"mtdac1",      XSPR(31,467,1014), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5157 {"mtdac2",      XSPR(31,467,1015), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5158 {"mtl2cr",      XSPR(31,467,1017), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5159 {"mtdccr",      XSPR(31,467,1018), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5160 {"mticcr",      XSPR(31,467,1019), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5161 {"mtictc",      XSPR(31,467,1019), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5162 {"mtpbl1",      XSPR(31,467,1020), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5163 {"mtthrm1",     XSPR(31,467,1020), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5164 {"mtpbu1",      XSPR(31,467,1021), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5165 {"mtthrm2",     XSPR(31,467,1021), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5166 {"mtpbl2",      XSPR(31,467,1022), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5167 {"mtthrm3",     XSPR(31,467,1022), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
5168 {"mtpbu2",      XSPR(31,467,1023), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
5169 {"mtspr",       X(31,467),      X_MASK,      COM|PPCVLE, PPCNONE,       {SPR, RS}},
5170
5171 {"dcbi",        X(31,470),      XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
5172
5173 {"nand",        XRC(31,476,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5174 {"nand.",       XRC(31,476,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
5175
5176 {"dsn",         X(31,483),      XRT_MASK,    E500MC|PPCVLE, PPCNONE,    {RA, RB}},
5177
5178 {"dcread",      X(31,486),      X_MASK,  PPC403|PPC440|PPCVLE, PPCA2|PPC476, {RT, RA0, RB}},
5179
5180 {"icbtls",      X(31,486),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
5181
5182 {"stvxl",       X(31,487),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VS, RA0, RB}},
5183
5184 {"nabs",        XO(31,488,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5185 {"nabs.",       XO(31,488,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5186
5187 {"divd",        XO(31,489,0,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5188 {"divd.",       XO(31,489,0,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5189
5190 {"divw",        XO(31,491,0,0), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5191 {"divw.",       XO(31,491,0,1), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5192
5193 {"icbtlse",     X(31,494),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
5194
5195 {"slbia",       X(31,498),      0xffffffff,  PPC64,     PPCNONE,        {0}},
5196
5197 {"cli",         X(31,502),      XRB_MASK,    POWER,     PPCNONE,        {RT, RA}},
5198
5199 {"popcntd",     X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
5200
5201 {"cmpb",        X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
5202
5203 {"mcrxr",       X(31,512), XRARB_MASK|(3<<21), COM|PPCVLE, POWER7,      {BF}},
5204
5205 {"lbdx",        X(31,515),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5206
5207 {"bblels",      X(31,518),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
5208
5209 {"lvlx",        X(31,519),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5210 {"lbfcmux",     APU(31,519,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5211
5212 {"subfco",      XO(31,8,1,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5213 {"sfo",         XO(31,8,1,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5214 {"subco",       XO(31,8,1,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
5215 {"subfco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5216 {"sfo.",        XO(31,8,1,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5217 {"subco.",      XO(31,8,1,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
5218
5219 {"addco",       XO(31,10,1,0),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5220 {"ao",          XO(31,10,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5221 {"addco.",      XO(31,10,1,1),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5222 {"ao.",         XO(31,10,1,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5223
5224 {"clcs",        X(31,531),      XRB_MASK,    M601,      PPCNONE,        {RT, RA}},
5225
5226 {"ldbrx",       X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
5227
5228 {"lswx",        X(31,533),      X_MASK,  PPCCOM|PPCVLE, E500|E500MC,    {RT, RAX, RBX}},
5229 {"lsx",         X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
5230
5231 {"lwbrx",       X(31,534),      X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RT, RA0, RB}},
5232 {"lbrx",        X(31,534),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
5233
5234 {"lfsx",        X(31,535),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
5235
5236 {"srw",         XRC(31,536,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5237 {"sr",          XRC(31,536,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5238 {"srw.",        XRC(31,536,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5239 {"sr.",         XRC(31,536,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5240
5241 {"rrib",        XRC(31,537,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5242 {"rrib.",       XRC(31,537,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5243
5244 {"srd",         XRC(31,539,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5245 {"srd.",        XRC(31,539,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5246
5247 {"maskir",      XRC(31,541,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5248 {"maskir.",     XRC(31,541,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5249
5250 {"lhdx",        X(31,547),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5251
5252 {"lvtrx",       X(31,549),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5253
5254 {"bbelr",       X(31,550),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
5255
5256 {"lvrx",        X(31,551),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5257 {"lhfcmux",     APU(31,551,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5258
5259 {"subfo",       XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
5260 {"subo",        XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
5261 {"subfo.",      XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
5262 {"subo.",       XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
5263
5264 {"tlbsync",     X(31,566),      0xffffffff, PPC|PPCVLE, PPCNONE,        {0}},
5265
5266 {"lfsux",       X(31,567),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
5267
5268 {"lwdx",        X(31,579),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5269
5270 {"lvtlx",       X(31,581),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5271
5272 {"lwfcmux",     APU(31,583,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5273
5274 {"lxsdx",       X(31,588),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5275
5276 {"mfsr",        X(31,595), XRB_MASK|(1<<20), COM,       NON32,          {RT, SR}},
5277
5278 {"lswi",        X(31,597),      X_MASK,  PPCCOM|PPCVLE, E500|E500MC,    {RT, RAX, NBI}},
5279 {"lsi",         X(31,597),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA0, NB}},
5280
5281 {"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC,       E500,           {0}},
5282 {"ptesync",     XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
5283 {"sync",        X(31,598),      XSYNCLE_MASK,E6500,     PPCNONE,        {LS, ESYNC}},
5284 {"sync",        X(31,598),      XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476, {LS}},
5285 {"msync",       X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
5286 {"sync",        X(31,598),      0xffffffff, BOOKE|PPC476, E6500,        {0}},
5287 {"lwsync",      X(31,598),      0xffffffff, E500,       PPCNONE,        {0}},
5288 {"dcs",         X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
5289
5290 {"lfdx",        X(31,599),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
5291
5292 {"mffgpr",      XRC(31,607,0),  XRA_MASK,    POWER6,    POWER7,         {FRT, RB}},
5293 {"lfdepx",      X(31,607),      X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA0, RB}},
5294
5295 {"lddx",        X(31,611),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
5296
5297 {"lvswx",       X(31,613),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5298
5299 {"lqfcmux",     APU(31,615,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5300
5301 {"nego",        XO(31,104,1,0), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
5302 {"nego.",       XO(31,104,1,1), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
5303
5304 {"mulo",        XO(31,107,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5305 {"mulo.",       XO(31,107,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5306
5307 {"mfsri",       X(31,627),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
5308
5309 {"dclst",       X(31,630),      XRB_MASK,    M601,      PPCNONE,        {RS, RA}},
5310
5311 {"lfdux",       X(31,631),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
5312
5313 {"stbdx",       X(31,643),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5314
5315 {"stvlx",       X(31,647),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5316 {"stbfcmux",    APU(31,647,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5317
5318 {"subfeo",      XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5319 {"sfeo",        XO(31,136,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5320 {"subfeo.",     XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5321 {"sfeo.",       XO(31,136,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5322
5323 {"addeo",       XO(31,138,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5324 {"aeo",         XO(31,138,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5325 {"addeo.",      XO(31,138,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5326 {"aeo.",        XO(31,138,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5327
5328 {"mfsrin",      X(31,659),      XRA_MASK,    PPC,       NON32,          {RT, RB}},
5329
5330 {"stdbrx",      X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
5331
5332 {"stswx",       X(31,661),      X_MASK, PPCCOM|PPCVLE,  E500|E500MC,    {RS, RA0, RB}},
5333 {"stsx",        X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
5334
5335 {"stwbrx",      X(31,662),      X_MASK, PPCCOM|PPCVLE,  PPCNONE,        {RS, RA0, RB}},
5336 {"stbrx",       X(31,662),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
5337
5338 {"stfsx",       X(31,663),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
5339
5340 {"srq",         XRC(31,664,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5341 {"srq.",        XRC(31,664,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5342
5343 {"sre",         XRC(31,665,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5344 {"sre.",        XRC(31,665,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5345
5346 {"sthdx",       X(31,675),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5347
5348 {"stvfrx",      X(31,677),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5349
5350 {"stvrx",       X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5351 {"sthfcmux",    APU(31,679,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5352
5353 {"stbcx.",      XRC(31,694,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
5354
5355 {"stfsux",      X(31,695),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
5356
5357 {"sriq",        XRC(31,696,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5358 {"sriq.",       XRC(31,696,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5359
5360 {"stwdx",       X(31,707),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5361
5362 {"stvflx",      X(31,709),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5363
5364 {"stwfcmux",    APU(31,711,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5365
5366 {"stxsdx",      X(31,716),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5367
5368 {"subfzeo",     XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5369 {"sfzeo",       XO(31,200,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5370 {"subfzeo.",    XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5371 {"sfzeo.",      XO(31,200,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5372
5373 {"addzeo",      XO(31,202,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5374 {"azeo",        XO(31,202,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5375 {"addzeo.",     XO(31,202,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
5376 {"azeo.",       XO(31,202,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5377
5378 {"stswi",       X(31,725),      X_MASK, PPCCOM|PPCVLE,  E500|E500MC,    {RS, RA0, NB}},
5379 {"stsi",        X(31,725),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, NB}},
5380
5381 {"sthcx.",      XRC(31,726,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
5382
5383 {"stfdx",       X(31,727),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
5384
5385 {"srlq",        XRC(31,728,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5386 {"srlq.",       XRC(31,728,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5387
5388 {"sreq",        XRC(31,729,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5389 {"sreq.",       XRC(31,729,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5390
5391 {"mftgpr",      XRC(31,735,0),  XRA_MASK,    POWER6,    POWER7,         {RT, FRB}},
5392 {"stfdepx",     X(31,735),      X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE,   {FRS, RA0, RB}},
5393
5394 {"stddx",       X(31,739),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
5395
5396 {"stvswx",      X(31,741),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5397
5398 {"stqfcmux",    APU(31,743,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5399
5400 {"subfmeo",     XO(31,232,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
5401 {"sfmeo",       XO(31,232,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5402 {"subfmeo.",    XO(31,232,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
5403 {"sfmeo.",      XO(31,232,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5404
5405 {"mulldo",      XO(31,233,1,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5406 {"mulldo.",     XO(31,233,1,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5407
5408 {"addmeo",      XO(31,234,1,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5409 {"ameo",        XO(31,234,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5410 {"addmeo.",     XO(31,234,1,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
5411 {"ameo.",       XO(31,234,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
5412
5413 {"mullwo",      XO(31,235,1,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5414 {"mulso",       XO(31,235,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5415 {"mullwo.",     XO(31,235,1,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
5416 {"mulso.",      XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5417
5418 {"dcba",        X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
5419 {"dcbal",       XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA0, RB}},
5420
5421 {"stfdux",      X(31,759),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
5422
5423 {"srliq",       XRC(31,760,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5424 {"srliq.",      XRC(31,760,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5425
5426 {"lvsm",        X(31,773),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5427 {"stvepxl",     X(31,775),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5428 {"lvlxl",       X(31,775),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5429 {"ldfcmux",     APU(31,775,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5430
5431 {"dozo",        XO(31,264,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5432 {"dozo.",       XO(31,264,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5433
5434 {"addo",        XO(31,266,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5435 {"caxo",        XO(31,266,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5436 {"addo.",       XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
5437 {"caxo.",       XO(31,266,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
5438
5439 {"lxvw4x",      X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5440
5441 {"tlbivax",     X(31,786),      XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
5442
5443 {"lwzcix",      X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5444
5445 {"lhbrx",       X(31,790),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
5446
5447 {"lfdpx",       X(31,791),      X_MASK,      POWER6,    POWER7,         {FRTp, RA0, RB}},
5448 {"lfqx",        X(31,791),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
5449
5450 {"sraw",        XRC(31,792,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5451 {"sra",         XRC(31,792,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5452 {"sraw.",       XRC(31,792,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
5453 {"sra.",        XRC(31,792,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
5454
5455 {"srad",        XRC(31,794,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5456 {"srad.",       XRC(31,794,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
5457
5458 {"lfddx",       X(31,803),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {FRT, RA, RB}},
5459
5460 {"lvtrxl",      X(31,805),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5461 {"stvepx",      X(31,807),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5462 {"lvrxl",       X(31,807),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
5463
5464 {"rac",         X(31,818),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
5465
5466 {"erativax",    X(31,819),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA0, RB}},
5467
5468 {"lhzcix",      X(31,821),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5469
5470 {"dss",         XDSS(31,822,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {STRM}},
5471
5472 {"lfqux",       X(31,823),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
5473
5474 {"srawi",       XRC(31,824,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, SH}},
5475 {"srai",        XRC(31,824,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
5476 {"srawi.",      XRC(31,824,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, SH}},
5477 {"srai.",       XRC(31,824,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
5478
5479 {"sradi",       XS(31,413,0),   XS_MASK,     PPC64|PPCVLE, PPCNONE,     {RA, RS, SH6}},
5480 {"sradi.",      XS(31,413,1),   XS_MASK,     PPC64|PPCVLE, PPCNONE,     {RA, RS, SH6}},
5481
5482 {"lvtlxl",      X(31,837),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5483
5484 {"divo",        XO(31,331,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5485 {"divo.",       XO(31,331,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5486
5487 {"lxvd2x",      X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
5488
5489 {"tlbsrx.",     XRC(31,850,1),  XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
5490
5491 {"slbmfev",     X(31,851),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
5492
5493 {"lbzcix",      X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5494
5495 {"eieio",       X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
5496 {"mbar",        X(31,854),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {MO}},
5497 {"eieio",       XMBAR(31,854,1),0xffffffff,  E500,      PPCNONE,        {0}},
5498 {"eieio",       X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
5499
5500 {"lfiwax",      X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
5501
5502 {"lvswxl",      X(31,869),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
5503
5504 {"abso",        XO(31,360,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5505 {"abso.",       XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5506
5507 {"divso",       XO(31,363,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5508 {"divso.",      XO(31,363,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
5509
5510 {"ldcix",       X(31,885),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
5511
5512 {"lfiwzx",      X(31,887),      X_MASK,   POWER7|PPCA2, PPCNONE,        {FRT, RA0, RB}},
5513
5514 {"stvlxl",      X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5515 {"stdfcmux",    APU(31,903,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
5516
5517 {"divdeuo",     XO(31,393,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5518 {"divdeuo.",    XO(31,393,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5519 {"divweuo",     XO(31,395,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5520 {"divweuo.",    XO(31,395,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5521
5522 {"stxvw4x",     X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5523
5524 {"tlbsx",       XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
5525 {"tlbsx.",      XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
5526
5527 {"slbmfee",     X(31,915),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
5528
5529 {"stwcix",      X(31,917),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5530
5531 {"sthbrx",      X(31,918),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
5532
5533 {"stfdpx",      X(31,919),      X_MASK,      POWER6,    POWER7,         {FRSp, RA0, RB}},
5534 {"stfqx",       X(31,919),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA0, RB}},
5535
5536 {"sraq",        XRC(31,920,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5537 {"sraq.",       XRC(31,920,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5538
5539 {"srea",        XRC(31,921,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5540 {"srea.",       XRC(31,921,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
5541
5542 {"extsh",       XRC(31,922,0),  XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
5543 {"exts",        XRC(31,922,0),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
5544 {"extsh.",      XRC(31,922,1),  XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
5545 {"exts.",       XRC(31,922,1),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
5546
5547 {"stfddx",      X(31,931),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
5548
5549 {"stvfrxl",     X(31,933),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5550
5551 {"wclrone",     XOPL2(31,934,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
5552 {"wclrall",     X(31,934),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
5553 {"wclr",        X(31,934),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
5554
5555 {"stvrxl",      X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
5556
5557 {"divdeo",      XO(31,425,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5558 {"divdeo.",     XO(31,425,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5559 {"divweo",      XO(31,427,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5560 {"divweo.",     XO(31,427,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
5561
5562 {"tlbrehi",     XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
5563 {"tlbrelo",     XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
5564 {"tlbre",       X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
5565
5566 {"sthcix",      X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5567
5568 {"icswepx",     XRC(31,950,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
5569 {"icswepx.",    XRC(31,950,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
5570
5571 {"stfqux",      X(31,951),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
5572
5573 {"sraiq",       XRC(31,952,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5574 {"sraiq.",      XRC(31,952,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
5575
5576 {"extsb",       XRC(31,954,0),  XRB_MASK, PPC|PPCVLE,   PPCNONE,        {RA, RS}},
5577 {"extsb.",      XRC(31,954,1),  XRB_MASK, PPC|PPCVLE,   PPCNONE,        {RA, RS}},
5578
5579 {"stvflxl",     X(31,965),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5580
5581 {"iccci",       X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
5582 {"ici",         X(31,966),      XRARB_MASK,  PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
5583
5584 {"divduo",      XO(31,457,1,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5585 {"divduo.",     XO(31,457,1,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
5586
5587 {"divwuo",      XO(31,459,1,0), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5588 {"divwuo.",     XO(31,459,1,1), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
5589
5590 {"stxvd2x",     X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
5591
5592 {"tlbld",       X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
5593 {"tlbwehi",     XTLB(31,978,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
5594 {"tlbwelo",     XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
5595 {"tlbwe",       X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
5596
5597 {"stbcix",      X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5598
5599 {"icbi",        X(31,982),      XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
5600
5601 {"stfiwx",      X(31,983),      X_MASK,      PPC,       PPCEFS,         {FRS, RA0, RB}},
5602
5603 {"extsw",       XRC(31,986,0),  XRB_MASK, PPC64|PPCVLE, PPCNONE,        {RA, RS}},
5604 {"extsw.",      XRC(31,986,1),  XRB_MASK, PPC64|PPCVLE, PPCNONE,        {RA, RS}},
5605
5606 {"icbiep",      XRT(31,991,0),  XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
5607
5608 {"stvswxl",     X(31,997),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
5609
5610 {"icread",      X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA0, RB}},
5611
5612 {"nabso",       XO(31,488,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5613 {"nabso.",      XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
5614
5615 {"divdo",       XO(31,489,1,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5616 {"divdo.",      XO(31,489,1,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
5617
5618 {"divwo",       XO(31,491,1,0), XO_MASK,   PPC|PPCVLE,  PPCNONE,        {RT, RA, RB}},
5619 {"divwo.",      XO(31,491,1,1), XO_MASK,   PPC|PPCVLE,  PPCNONE,        {RT, RA, RB}},
5620
5621
5622 {"tlbli",       X(31,1010),     XRTRA_MASK,  PPC,       TITAN,          {RB}},
5623
5624 {"stdcix",      X(31,1013),     X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
5625
5626 {"dcbz",        X(31,1014),     XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
5627 {"dclz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA0, RB}},
5628
5629 {"dcbzep",      XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
5630
5631 {"dcbzl",       XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA0, RB}},
5632
5633 {"cctpl",       0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5634 {"cctpm",       0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
5635 {"cctph",       0x7c631b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5636
5637 {"dstt",        XDSS(31,342,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
5638 {"dststt",      XDSS(31,374,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
5639 {"dssall",      XDSS(31,822,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {0}},
5640
5641 {"db8cyc",      0x7f9ce378,     0xffffffff,  CELL,      PPCNONE,        {0}},
5642 {"db10cyc",     0x7fbdeb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5643 {"db12cyc",     0x7fdef378,     0xffffffff,  CELL,      PPCNONE,        {0}},
5644 {"db16cyc",     0x7ffffb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
5645
5646 {"lwz",         OP(32),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
5647 {"l",           OP(32),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
5648
5649 {"lwzu",        OP(33),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAL}},
5650 {"lu",          OP(33),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
5651
5652 {"lbz",         OP(34),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
5653
5654 {"lbzu",        OP(35),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
5655
5656 {"stw",         OP(36),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
5657 {"st",          OP(36),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
5658
5659 {"stwu",        OP(37),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RAS}},
5660 {"stu",         OP(37),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
5661
5662 {"stb",         OP(38),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
5663
5664 {"stbu",        OP(39),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
5665
5666 {"lhz",         OP(40),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
5667
5668 {"lhzu",        OP(41),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
5669
5670 {"lha",         OP(42),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
5671
5672 {"lhau",        OP(43),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
5673
5674 {"sth",         OP(44),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
5675
5676 {"sthu",        OP(45),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
5677
5678 {"lmw",         OP(46),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAM}},
5679 {"lm",          OP(46),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
5680
5681 {"stmw",        OP(47),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
5682 {"stm",         OP(47),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
5683
5684 {"lfs",         OP(48),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
5685
5686 {"lfsu",        OP(49),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
5687
5688 {"lfd",         OP(50),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
5689
5690 {"lfdu",        OP(51),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
5691
5692 {"stfs",        OP(52),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
5693
5694 {"stfsu",       OP(53),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
5695
5696 {"stfd",        OP(54),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
5697
5698 {"stfdu",       OP(55),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
5699
5700 {"lq",          OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
5701 {"psq_l",       OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
5702 {"lfq",         OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
5703
5704 {"lfdp",        OP(57),         OP_MASK,     POWER6,    POWER7,         {FRTp, DS, RA0}},
5705 {"psq_lu",      OP(57),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
5706 {"lfqu",        OP(57),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
5707
5708 {"ld",          DSO(58,0),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
5709 {"ldu",         DSO(58,1),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RAL}},
5710 {"lwa",         DSO(58,2),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
5711
5712 {"dadd",        XRC(59,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5713 {"dadd.",       XRC(59,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5714
5715 {"dqua",        ZRC(59,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
5716 {"dqua.",       ZRC(59,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
5717
5718 {"fdivs",       A(59,18,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5719 {"fdivs.",      A(59,18,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5720
5721 {"fsubs",       A(59,20,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5722 {"fsubs.",      A(59,20,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5723
5724 {"fadds",       A(59,21,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5725 {"fadds.",      A(59,21,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
5726
5727 {"fsqrts",      A(59,22,0),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
5728 {"fsqrts.",     A(59,22,1),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
5729
5730 {"fres",        A(59,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5731 {"fres",        A(59,24,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5732 {"fres.",       A(59,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5733 {"fres.",       A(59,24,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5734
5735 {"fmuls",       A(59,25,0),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
5736 {"fmuls.",      A(59,25,1),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
5737
5738 {"frsqrtes",    A(59,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5739 {"frsqrtes",    A(59,26,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5740 {"frsqrtes.",   A(59,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5741 {"frsqrtes.",   A(59,26,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5742
5743 {"fmsubs",      A(59,28,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5744 {"fmsubs.",     A(59,28,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5745
5746 {"fmadds",      A(59,29,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5747 {"fmadds.",     A(59,29,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5748
5749 {"fnmsubs",     A(59,30,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5750 {"fnmsubs.",    A(59,30,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5751
5752 {"fnmadds",     A(59,31,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5753 {"fnmadds.",    A(59,31,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
5754
5755 {"dmul",        XRC(59,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5756 {"dmul.",       XRC(59,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5757
5758 {"drrnd",       ZRC(59,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5759 {"drrnd.",      ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5760
5761 {"dscli",       ZRC(59,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5762 {"dscli.",      ZRC(59,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5763
5764 {"dquai",       ZRC(59,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
5765 {"dquai.",      ZRC(59,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
5766
5767 {"dscri",       ZRC(59,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5768 {"dscri.",      ZRC(59,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5769
5770 {"drintx",      ZRC(59,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5771 {"drintx.",     ZRC(59,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5772
5773 {"dcmpo",       X(59,130),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5774
5775 {"dtstex",      X(59,162),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5776 {"dtstdc",      Z(59,194),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DCM}},
5777 {"dtstdg",      Z(59,226),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DGM}},
5778
5779 {"drintn",      ZRC(59,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5780 {"drintn.",     ZRC(59,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5781
5782 {"dctdp",       XRC(59,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5783 {"dctdp.",      XRC(59,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5784
5785 {"dctfix",      XRC(59,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5786 {"dctfix.",     XRC(59,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5787
5788 {"ddedpd",      XRC(59,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5789 {"ddedpd.",     XRC(59,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5790
5791 {"dxex",        XRC(59,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5792 {"dxex.",       XRC(59,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5793
5794 {"dsub",        XRC(59,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5795 {"dsub.",       XRC(59,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5796
5797 {"ddiv",        XRC(59,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5798 {"ddiv.",       XRC(59,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5799
5800 {"dcmpu",       X(59,642),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5801
5802 {"dtstsf",      X(59,674),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
5803
5804 {"drsp",        XRC(59,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5805 {"drsp.",       XRC(59,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5806
5807 {"dcffix",      XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
5808 {"dcffix.",     XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
5809
5810 {"denbcd",      XRC(59,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5811 {"denbcd.",     XRC(59,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5812
5813 {"fcfids",      XRC(59,846,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5814 {"fcfids.",     XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5815
5816 {"diex",        XRC(59,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5817 {"diex.",       XRC(59,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5818
5819 {"fcfidus",     XRC(59,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5820 {"fcfidus.",    XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5821
5822 {"xxsldwi",     XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6, SHW}},
5823 {"xxsel",       XX4(60,3),      XX4_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6, XC6}},
5824 {"xxspltd",     XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6S, DMEX}},
5825 {"xxmrghd",     XX3(60,10),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5826 {"xxswapd",     XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5827 {"xxmrgld",     XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5828 {"xxpermdi",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6, DM}},
5829 {"xxmrghw",     XX3(60,18),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5830 {"xsadddp",     XX3(60,32),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5831 {"xsmaddadp",   XX3(60,33),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5832 {"xscmpudp",    XX3(60,35),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5833 {"xssubdp",     XX3(60,40),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5834 {"xsmaddmdp",   XX3(60,41),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5835 {"xscmpodp",    XX3(60,43),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5836 {"xsmuldp",     XX3(60,48),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5837 {"xsmsubadp",   XX3(60,49),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5838 {"xxmrglw",     XX3(60,50),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5839 {"xsdivdp",     XX3(60,56),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5840 {"xsmsubmdp",   XX3(60,57),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5841 {"xstdivdp",    XX3(60,61),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5842 {"xvaddsp",     XX3(60,64),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5843 {"xvmaddasp",   XX3(60,65),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5844 {"xvcmpeqsp",   XX3RC(60,67,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5845 {"xvcmpeqsp.",  XX3RC(60,67,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5846 {"xvsubsp",     XX3(60,72),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5847 {"xscvdpuxws",  XX2(60,72),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5848 {"xvmaddmsp",   XX3(60,73),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5849 {"xsrdpi",      XX2(60,73),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5850 {"xsrsqrtedp",  XX2(60,74),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5851 {"xssqrtdp",    XX2(60,75),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5852 {"xvcmpgtsp",   XX3RC(60,75,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5853 {"xvcmpgtsp.",  XX3RC(60,75,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5854 {"xvmulsp",     XX3(60,80),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5855 {"xvmsubasp",   XX3(60,81),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5856 {"xvcmpgesp",   XX3RC(60,83,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5857 {"xvcmpgesp.",  XX3RC(60,83,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5858 {"xvdivsp",     XX3(60,88),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5859 {"xscvdpsxws",  XX2(60,88),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5860 {"xvmsubmsp",   XX3(60,89),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5861 {"xsrdpiz",     XX2(60,89),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5862 {"xsredp",      XX2(60,90),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5863 {"xvtdivsp",    XX3(60,93),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5864 {"xvadddp",     XX3(60,96),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5865 {"xvmaddadp",   XX3(60,97),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5866 {"xvcmpeqdp",   XX3RC(60,99,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5867 {"xvcmpeqdp.",  XX3RC(60,99,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5868 {"xvsubdp",     XX3(60,104),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5869 {"xvmaddmdp",   XX3(60,105),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5870 {"xsrdpip",     XX2(60,105),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5871 {"xstsqrtdp",   XX2(60,106),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5872 {"xsrdpic",     XX2(60,107),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5873 {"xvcmpgtdp",   XX3RC(60,107,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5874 {"xvcmpgtdp.",  XX3RC(60,107,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5875 {"xvmuldp",     XX3(60,112),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5876 {"xvmsubadp",   XX3(60,113),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5877 {"xvcmpgedp",   XX3RC(60,115,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5878 {"xvcmpgedp.",  XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5879 {"xvdivdp",     XX3(60,120),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5880 {"xvmsubmdp",   XX3(60,121),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5881 {"xsrdpim",     XX2(60,121),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5882 {"xvtdivdp",    XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5883 {"xxland",      XX3(60,130),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5884 {"xvcvspuxws",  XX2(60,136),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5885 {"xvrspi",      XX2(60,137),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5886 {"xxlandc",     XX3(60,138),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5887 {"xvrsqrtesp",  XX2(60,138),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5888 {"xvsqrtsp",    XX2(60,139),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5889 {"xxlor",       XX3(60,146),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5890 {"xvcvspsxws",  XX2(60,152),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5891 {"xvrspiz",     XX2(60,153),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5892 {"xxlxor",      XX3(60,154),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5893 {"xvresp",      XX2(60,154),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5894 {"xsmaxdp",     XX3(60,160),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5895 {"xsnmaddadp",  XX3(60,161),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5896 {"xxlnor",      XX3(60,162),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5897 {"xxspltw",     XX2(60,164),    XX2UIM_MASK, PPCVSX,    PPCNONE,        {XT6, XB6, UIM}},
5898 {"xsmindp",     XX3(60,168),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5899 {"xvcvuxwsp",   XX2(60,168),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5900 {"xsnmaddmdp",  XX3(60,169),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5901 {"xvrspip",     XX2(60,169),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5902 {"xvtsqrtsp",   XX2(60,170),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5903 {"xvrspic",     XX2(60,171),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5904 {"xscpsgndp",   XX3(60,176),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5905 {"xsnmsubadp",  XX3(60,177),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5906 {"xvcvsxwsp",   XX2(60,184),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5907 {"xsnmsubmdp",  XX3(60,185),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5908 {"xvrspim",     XX2(60,185),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5909 {"xvmaxsp",     XX3(60,192),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5910 {"xvnmaddasp",  XX3(60,193),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5911 {"xvminsp",     XX3(60,200),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5912 {"xvcvdpuxws",  XX2(60,200),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5913 {"xvnmaddmsp",  XX3(60,201),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5914 {"xvrdpi",      XX2(60,201),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5915 {"xvrsqrtedp",  XX2(60,202),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5916 {"xvsqrtdp",    XX2(60,203),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5917 {"xvmovsp",     XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5918 {"xvcpsgnsp",   XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5919 {"xvnmsubasp",  XX3(60,209),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5920 {"xvcvdpsxws",  XX2(60,216),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5921 {"xvnmsubmsp",  XX3(60,217),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5922 {"xvrdpiz",     XX2(60,217),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5923 {"xvredp",      XX2(60,218),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5924 {"xvmaxdp",     XX3(60,224),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5925 {"xvnmaddadp",  XX3(60,225),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5926 {"xvmindp",     XX3(60,232),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5927 {"xvnmaddmdp",  XX3(60,233),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5928 {"xvcvuxwdp",   XX2(60,232),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5929 {"xvrdpip",     XX2(60,233),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5930 {"xvtsqrtdp",   XX2(60,234),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5931 {"xvrdpic",     XX2(60,235),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5932 {"xvmovdp",     XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5933 {"xvcpsgndp",   XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5934 {"xvnmsubadp",  XX3(60,241),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5935 {"xvcvsxwdp",   XX2(60,248),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5936 {"xvnmsubmdp",  XX3(60,249),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5937 {"xvrdpim",     XX2(60,249),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5938 {"xscvdpsp",    XX2(60,265),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5939 {"xscvdpuxds",  XX2(60,328),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5940 {"xscvspdp",    XX2(60,329),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5941 {"xscvdpsxds",  XX2(60,344),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5942 {"xsabsdp",     XX2(60,345),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5943 {"xscvuxddp",   XX2(60,360),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5944 {"xsnabsdp",    XX2(60,361),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5945 {"xscvsxddp",   XX2(60,376),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5946 {"xsnegdp",     XX2(60,377),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5947 {"xvcvspuxds",  XX2(60,392),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5948 {"xvcvdpsp",    XX2(60,393),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5949 {"xvcvspsxds",  XX2(60,408),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5950 {"xvabssp",     XX2(60,409),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5951 {"xvcvuxdsp",   XX2(60,424),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5952 {"xvnabssp",    XX2(60,425),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5953 {"xvcvsxdsp",   XX2(60,440),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5954 {"xvnegsp",     XX2(60,441),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5955 {"xvcvdpuxds",  XX2(60,456),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5956 {"xvcvspdp",    XX2(60,457),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5957 {"xvcvdpsxds",  XX2(60,472),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5958 {"xvabsdp",     XX2(60,473),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5959 {"xvcvuxddp",   XX2(60,488),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5960 {"xvnabsdp",    XX2(60,489),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5961 {"xvcvsxddp",   XX2(60,504),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5962 {"xvnegdp",     XX2(60,505),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5963
5964 {"psq_st",      OP(60),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5965 {"stfq",        OP(60),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5966
5967 {"stfdp",       OP(61),         OP_MASK,     POWER6,    POWER7,         {FRSp, DS, RA0}},
5968 {"psq_stu",     OP(61),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5969 {"stfqu",       OP(61),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5970
5971 {"std",         DSO(62,0),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
5972 {"stdu",        DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
5973 {"stq",         DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
5974
5975 {"fcmpu",       X(63,0),     X_MASK|(3<<21), COM,       PPCEFS,         {BF, FRA, FRB}},
5976
5977 {"daddq",       XRC(63,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5978 {"daddq.",      XRC(63,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
5979
5980 {"dquaq",       ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
5981 {"dquaq.",      ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
5982
5983 {"fcpsgn",      XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5984 {"fcpsgn.",     XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5985
5986 {"frsp",        XRC(63,12,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5987 {"frsp.",       XRC(63,12,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
5988
5989 {"fctiw",       XRC(63,14,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5990 {"fcir",        XRC(63,14,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5991 {"fctiw.",      XRC(63,14,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5992 {"fcir.",       XRC(63,14,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5993
5994 {"fctiwz",      XRC(63,15,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5995 {"fcirz",       XRC(63,15,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5996 {"fctiwz.",     XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
5997 {"fcirz.",      XRC(63,15,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
5998
5999 {"fdiv",        A(63,18,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6000 {"fd",          A(63,18,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6001 {"fdiv.",       A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6002 {"fd.",         A(63,18,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6003
6004 {"fsub",        A(63,20,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6005 {"fs",          A(63,20,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6006 {"fsub.",       A(63,20,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6007 {"fs.",         A(63,20,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6008
6009 {"fadd",        A(63,21,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6010 {"fa",          A(63,21,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6011 {"fadd.",       A(63,21,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
6012 {"fa.",         A(63,21,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
6013
6014 {"fsqrt",       A(63,22,0),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
6015 {"fsqrt.",      A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
6016
6017 {"fsel",        A(63,23,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6018 {"fsel.",       A(63,23,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
6019
6020 {"fre",         A(63,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6021 {"fre",         A(63,24,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
6022 {"fre.",        A(63,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6023 {"fre.",        A(63,24,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
6024
6025 {"fmul",        A(63,25,0),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
6026 {"fm",          A(63,25,0),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
6027 {"fmul.",       A(63,25,1),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
6028 {"fm.",         A(63,25,1),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
6029
6030 {"frsqrte",     A(63,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6031 {"frsqrte",     A(63,26,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
6032 {"frsqrte.",    A(63,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
6033 {"frsqrte.",    A(63,26,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
6034
6035 {"fmsub",       A(63,28,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6036 {"fms",         A(63,28,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6037 {"fmsub.",      A(63,28,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6038 {"fms.",        A(63,28,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6039
6040 {"fmadd",       A(63,29,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6041 {"fma",         A(63,29,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6042 {"fmadd.",      A(63,29,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6043 {"fma.",        A(63,29,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6044
6045 {"fnmsub",      A(63,30,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6046 {"fnms",        A(63,30,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6047 {"fnmsub.",     A(63,30,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6048 {"fnms.",       A(63,30,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6049
6050 {"fnmadd",      A(63,31,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6051 {"fnma",        A(63,31,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6052 {"fnmadd.",     A(63,31,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
6053 {"fnma.",       A(63,31,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
6054
6055 {"fcmpo",       X(63,32),    X_MASK|(3<<21), COM,       PPCEFS,         {BF, FRA, FRB}},
6056
6057 {"dmulq",       XRC(63,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6058 {"dmulq.",      XRC(63,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6059
6060 {"drrndq",      ZRC(63,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
6061 {"drrndq.",     ZRC(63,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
6062
6063 {"mtfsb1",      XRC(63,38,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6064 {"mtfsb1.",     XRC(63,38,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6065
6066 {"fneg",        XRC(63,40,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6067 {"fneg.",       XRC(63,40,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6068
6069 {"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
6070
6071 {"dscliq",      ZRC(63,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6072 {"dscliq.",     ZRC(63,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6073
6074 {"dquaiq",      ZRC(63,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
6075 {"dquaiq.",     ZRC(63,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
6076
6077 {"mtfsb0",      XRC(63,70,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6078 {"mtfsb0.",     XRC(63,70,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
6079
6080 {"fmr",         XRC(63,72,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6081 {"fmr.",        XRC(63,72,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6082
6083 {"dscriq",      ZRC(63,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6084 {"dscriq.",     ZRC(63,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
6085
6086 {"drintxq",     ZRC(63,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6087 {"drintxq.",    ZRC(63,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6088
6089 {"ftdiv",       X(63,128),   X_MASK|(3<<21), POWER7,    PPCNONE,        {BF, FRA, FRB}},
6090
6091 {"dcmpoq",      X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6092
6093 {"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
6094 {"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
6095 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
6096 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
6097
6098 {"fnabs",       XRC(63,136,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6099 {"fnabs.",      XRC(63,136,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6100
6101 {"fctiwu",      XRC(63,142,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6102 {"fctiwu.",     XRC(63,142,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6103 {"fctiwuz",     XRC(63,143,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6104 {"fctiwuz.",    XRC(63,143,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
6105
6106 {"ftsqrt",      X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE,    {BF, FRB}},
6107
6108 {"dtstexq",     X(63,162),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6109 {"dtstdcq",     Z(63,194),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DCM}},
6110 {"dtstdgq",     Z(63,226),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DGM}},
6111
6112 {"drintnq",     ZRC(63,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6113 {"drintnq.",    ZRC(63,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
6114
6115 {"dctqpq",      XRC(63,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6116 {"dctqpq.",     XRC(63,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6117
6118 {"fabs",        XRC(63,264,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6119 {"fabs.",       XRC(63,264,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
6120
6121 {"dctfixq",     XRC(63,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6122 {"dctfixq.",    XRC(63,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6123
6124 {"ddedpdq",     XRC(63,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
6125 {"ddedpdq.",    XRC(63,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
6126
6127 {"dxexq",       XRC(63,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6128 {"dxexq.",      XRC(63,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
6129
6130 {"frin",        XRC(63,392,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6131 {"frin.",       XRC(63,392,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6132 {"friz",        XRC(63,424,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6133 {"friz.",       XRC(63,424,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6134 {"frip",        XRC(63,456,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6135 {"frip.",       XRC(63,456,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6136 {"frim",        XRC(63,488,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6137 {"frim.",       XRC(63,488,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
6138
6139 {"dsubq",       XRC(63,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6140 {"dsubq.",      XRC(63,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6141
6142 {"ddivq",       XRC(63,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6143 {"ddivq.",      XRC(63,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
6144
6145 {"mffs",        XRC(63,583,0),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
6146 {"mffs.",       XRC(63,583,1),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
6147
6148 {"dcmpuq",      X(63,642),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
6149
6150 {"dtstsfq",     X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRBp}},
6151
6152 {"mtfsf",       XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
6153 {"mtfsf",       XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
6154 {"mtfsf.",      XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
6155 {"mtfsf.",      XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
6156
6157 {"drdpq",       XRC(63,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
6158 {"drdpq.",      XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
6159
6160 {"dcffixq",     XRC(63,802,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6161 {"dcffixq.",    XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
6162
6163 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6164 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6165 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6166 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6167
6168 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6169 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6170 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6171 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6172
6173 {"denbcdq",     XRC(63,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
6174 {"denbcdq.",    XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
6175
6176 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6177 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6178 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
6179 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
6180
6181 {"diexq",       XRC(63,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
6182 {"diexq.",      XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
6183
6184 {"fctidu",      XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6185 {"fctidu.",     XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6186
6187 {"fctiduz",     XRC(63,943,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6188 {"fctiduz.",    XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6189
6190 {"fcfidu",      XRC(63,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6191 {"fcfidu.",     XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
6192 };
6193
6194 const int powerpc_num_opcodes =
6195   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
6196 \f
6197 /* The VLE opcode table.
6198
6199    The format of this opcode table is the same as the main opcode table.  */
6200
6201 const struct powerpc_opcode vle_opcodes[] = {
6202
6203 {"se_illegal",  C(0),           C_MASK,         PPCVLE, PPCNONE,        {}},
6204 {"se_isync",    C(1),           C_MASK,         PPCVLE, PPCNONE,        {}},
6205 {"se_sc",       C(2),           C_MASK,         PPCVLE, PPCNONE,        {}},
6206 {"se_blr",      C_LK(2,0),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6207 {"se_blrl",     C_LK(2,1),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6208 {"se_bctr",     C_LK(3,0),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6209 {"se_bctrl",    C_LK(3,1),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
6210 {"se_rfi",      C(8),           C_MASK,         PPCVLE, PPCNONE,        {}},
6211 {"se_rfci",     C(9),           C_MASK,         PPCVLE, PPCNONE,        {}},
6212 {"se_rfdi",     C(10),          C_MASK,         PPCVLE, PPCNONE,        {}},
6213 {"se_rfmci",    C(11),          C_MASK,         PPCVLE, PPCNONE,        {}},
6214 {"se_not",      SE_R(0,2),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6215 {"se_neg",      SE_R(0,3),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6216 {"se_mflr",     SE_R(0,8),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6217 {"se_mtlr",     SE_R(0,9),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6218 {"se_mfctr",    SE_R(0,10),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6219 {"se_mtctr",    SE_R(0,11),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6220 {"se_extzb",    SE_R(0,12),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6221 {"se_extsb",    SE_R(0,13),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6222 {"se_extzh",    SE_R(0,14),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6223 {"se_extsh",    SE_R(0,15),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
6224 {"se_mr",       SE_RR(0,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6225 {"se_mtar",     SE_RR(0,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {ARX, RY}},
6226 {"se_mfar",     SE_RR(0,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, ARY}},
6227 {"se_add",      SE_RR(1,0),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6228 {"se_mullw",    SE_RR(1,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6229 {"se_sub",      SE_RR(1,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6230 {"se_subf",     SE_RR(1,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6231 {"se_cmp",      SE_RR(3,0),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6232 {"se_cmpl",     SE_RR(3,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6233 {"se_cmph",     SE_RR(3,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6234 {"se_cmphl",    SE_RR(3,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6235
6236 {"e_cmpi",      SCI8BF(6,0,21), SCI8BF_MASK,    PPCVLE, PPCNONE,        {CRD32, RA, SCLSCI8}},
6237 {"e_cmpli",     SCI8BF(6,1,21), SCI8BF_MASK,    PPCVLE, PPCNONE,        {CRD32, RA, SCLSCI8}},
6238 {"e_addi",      SCI8(6,16),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6239 {"e_subi",      SCI8(6,16),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
6240 {"e_addi.",     SCI8(6,17),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6241 {"e_addic",     SCI8(6,18),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6242 {"e_subic",     SCI8(6,18),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
6243 {"e_addic.",    SCI8(6,19),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6244 {"e_subic.",    SCI8(6,19),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
6245 {"e_mulli",     SCI8(6,20),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6246 {"e_subfic",    SCI8(6,22),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6247 {"e_subfic.",   SCI8(6,23),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
6248 {"e_andi",      SCI8(6,24),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6249 {"e_andi.",     SCI8(6,25),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6250 {"e_nop",       SCI8(6,26),     0xffffffff,     PPCVLE, PPCNONE,        {0}},
6251 {"e_ori",       SCI8(6,26),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6252 {"e_ori.",      SCI8(6,27),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6253 {"e_xori",      SCI8(6,28),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6254 {"e_xori.",     SCI8(6,29),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
6255 {"e_lbzu",      OPVUP(6,0),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6256 {"e_lhau",      OPVUP(6,3),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6257 {"e_lhzu",      OPVUP(6,1),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6258 {"e_lmw",       OPVUP(6,8),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6259 {"e_lwzu",      OPVUP(6,2),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6260 {"e_stbu",      OPVUP(6,4),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6261 {"e_sthu",      OPVUP(6,5),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6262 {"e_stwu",      OPVUP(6,6),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6263 {"e_stmw",      OPVUP(6,9),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
6264 {"e_add16i",    OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, RA, SI}},
6265 {"e_la",        OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6266 {"e_sub16i",    OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, RA, NSI}},
6267
6268 {"se_addi",     SE_IM5(8,0),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6269 {"se_cmpli",    SE_IM5(8,1),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6270 {"se_subi",     SE_IM5(9,0),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6271 {"se_subi.",    SE_IM5(9,1),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
6272 {"se_cmpi",     SE_IM5(10,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6273 {"se_bmaski",   SE_IM5(11,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6274 {"se_andi",     SE_IM5(11,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6275
6276 {"e_lbz",       OP(12),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6277 {"e_stb",       OP(13),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6278 {"e_lha",       OP(14),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6279
6280 {"se_srw",      SE_RR(16,0),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6281 {"se_sraw",     SE_RR(16,1),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6282 {"se_slw",      SE_RR(16,2),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6283 {"se_nop",      SE_RR(17,0),    0xffff,         PPCVLE, PPCNONE,        {0}},
6284 {"se_or",       SE_RR(17,0),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6285 {"se_andc",     SE_RR(17,1),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6286 {"se_and",      SE_RR(17,2),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6287 {"se_and.",     SE_RR(17,3),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
6288 {"se_li",       IM7(9),         IM7_MASK,       PPCVLE, PPCNONE,        {RX, UI7}},
6289
6290 {"e_lwz",       OP(20),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6291 {"e_stw",       OP(21),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6292 {"e_lhz",       OP(22),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6293 {"e_sth",       OP(23),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
6294
6295 {"se_bclri",    SE_IM5(24,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6296 {"se_bgeni",    SE_IM5(24,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6297 {"se_bseti",    SE_IM5(25,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6298 {"se_btsti",    SE_IM5(25,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6299 {"se_srwi",     SE_IM5(26,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6300 {"se_srawi",    SE_IM5(26,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6301 {"se_slwi",     SE_IM5(27,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
6302
6303 {"e_lis",       I16L(28,28),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6304 {"e_and2is.",   I16L(28,29),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6305 {"e_or2is",     I16L(28,26),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6306 {"e_and2i.",    I16L(28,25),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6307 {"e_or2i",      I16L(28,24),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
6308 {"e_cmphl16i",  IA16(28,23),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLEUIMM}},
6309 {"e_cmph16i",   IA16(28,22),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6310 {"e_cmpl16i",   I16A(28,21),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLEUIMM}},
6311 {"e_cmplwi",    I16A(28,21),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6312 {"e_mull2i",    I16A(28,20),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6313 {"e_cmp16i",    IA16(28,19),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6314 {"e_cmpwi",     IA16(28,19),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6315 {"e_sub2is",    I16A(28,18),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLENSIMM}},
6316 {"e_add2is",    I16A(28,18),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6317 {"e_sub2i.",    I16A(28,17),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLENSIMM}},
6318 {"e_add2i.",    I16A(28,17),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
6319 {"e_li",        LI20(28,0),     LI20_MASK,      PPCVLE, PPCNONE,        {RT, IMM20}},
6320 {"e_rlwimi",    M(29,0),        M_MASK,         PPCVLE, PPCNONE,        {RA, RS, SH, MB, ME}},
6321 {"e_rlwinm",    M(29,1),        M_MASK,         PPCVLE, PPCNONE,        {RA, RT, SH, MBE, ME}},
6322 {"e_b",         BD24(30,0,0),   BD24_MASK,      PPCVLE, PPCNONE,        {B24}},
6323 {"e_bl",        BD24(30,0,1),   BD24_MASK,      PPCVLE, PPCNONE,        {B24}},
6324 {"e_bdnz",      EBD15(30,8,BO32DNZ,0),  EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6325 {"e_bdnzl",     EBD15(30,8,BO32DNZ,1),  EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6326 {"e_bdz",       EBD15(30,8,BO32DZ,0),   EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6327 {"e_bdzl",      EBD15(30,8,BO32DZ,1),   EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
6328 {"e_bge",       EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6329 {"e_bgel",      EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6330 {"e_bnl",       EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6331 {"e_bnll",      EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6332 {"e_blt",       EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6333 {"e_bltl",      EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6334 {"e_bgt",       EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6335 {"e_bgtl",      EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6336 {"e_ble",       EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6337 {"e_blel",      EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6338 {"e_bng",       EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6339 {"e_bngl",      EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6340 {"e_bne",       EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6341 {"e_bnel",      EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6342 {"e_beq",       EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6343 {"e_beql",      EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6344 {"e_bso",       EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6345 {"e_bsol",      EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6346 {"e_bun",       EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6347 {"e_bunl",      EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6348 {"e_bns",       EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6349 {"e_bnsl",      EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6350 {"e_bnu",       EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6351 {"e_bnul",      EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
6352 {"e_bc",        BD15(30,8,0),   BD15_MASK,      PPCVLE, PPCNONE,        {BO32, BI32, B15}},
6353 {"e_bcl",       BD15(30,8,1),   BD15_MASK,      PPCVLE, PPCNONE,        {BO32, BI32, B15}},
6354
6355 {"e_bf",        EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6356 {"e_bfl",       EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6357 {"e_bt",        EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6358 {"e_btl",       EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
6359
6360 {"e_cmph",      X(31,14),       X_MASK,         PPCVLE, PPCNONE,        {CRD, RA, RB}},
6361 {"e_cmphl",     X(31,46),       X_MASK,         PPCVLE, PPCNONE,        {CRD, RA, RB}},
6362 {"e_crandc",    XL(31,129),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6363 {"e_crnand",    XL(31,225),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6364 {"e_crnot",     XL(31,33),      XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BBA}},
6365 {"e_crnor",     XL(31,33),      XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6366 {"e_crclr",     XL(31,193),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BAT, BBA}},
6367 {"e_crxor",     XL(31,193),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6368 {"e_mcrf",      XL(31,16),      XL_MASK,        PPCVLE, PPCNONE,        {CRD, CR}},
6369 {"e_slwi",      EX(31,112),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6370 {"e_slwi.",     EX(31,113),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6371
6372 {"e_crand",     XL(31,257),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6373
6374 {"e_rlw",       EX(31,560),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, RB}},
6375 {"e_rlw.",      EX(31,561),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, RB}},
6376
6377 {"e_crset",     XL(31,289),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BAT, BBA}},
6378 {"e_creqv",     XL(31,289),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6379
6380 {"e_rlwi",      EX(31,624),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6381 {"e_rlwi.",     EX(31,625),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6382
6383 {"e_crorc",     XL(31,417),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6384
6385 {"e_crmove",    XL(31,449),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BBA}},
6386 {"e_cror",      XL(31,449),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
6387
6388 {"mtmas1",      XSPR(31,467,625), XSPR_MASK,    PPCVLE, PPCNONE,        {RS}},
6389
6390 {"e_srwi",      EX(31,1136),    EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6391 {"e_srwi.",     EX(31,1137),    EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
6392
6393 {"se_lbz",      SD4(8),         SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SD, RX}},
6394
6395 {"se_stb",      SD4(9),         SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SD, RX}},
6396
6397 {"se_lhz",      SD4(10),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDH, RX}},
6398
6399 {"se_sth",      SD4(11),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDH, RX}},
6400
6401 {"se_lwz",      SD4(12),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDW, RX}},
6402
6403 {"se_stw",      SD4(13),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDW, RX}},
6404
6405 {"se_bge",      EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6406 {"se_bnl",      EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6407 {"se_ble",      EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6408 {"se_bng",      EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6409 {"se_bne",      EBD8IO(28,0,2), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6410 {"se_bns",      EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6411 {"se_bnu",      EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6412 {"se_bf",       EBD8IO(28,0,0), EBD8IO2_MASK,   PPCVLE, PPCNONE,        {BI16, B8}},
6413 {"se_blt",      EBD8IO(28,1,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6414 {"se_bgt",      EBD8IO(28,1,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6415 {"se_beq",      EBD8IO(28,1,2), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6416 {"se_bso",      EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6417 {"se_bun",      EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
6418 {"se_bt",       EBD8IO(28,1,0), EBD8IO2_MASK,   PPCVLE, PPCNONE,        {BI16, B8}},
6419 {"se_bc",       BD8IO(28),      BD8IO_MASK,     PPCVLE, PPCNONE,        {BO16, BI16, B8}},
6420 {"se_b",        BD8(58,0,0),    BD8_MASK,       PPCVLE, PPCNONE,        {B8}},
6421 {"se_bl",       BD8(58,0,1),    BD8_MASK,       PPCVLE, PPCNONE,        {B8}},
6422 };
6423
6424 const int vle_num_opcodes =
6425   sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
6426 \f
6427 /* The macro table.  This is only used by the assembler.  */
6428
6429 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
6430    when x=0; 32-x when x is between 1 and 31; are negative if x is
6431    negative; and are 32 or more otherwise.  This is what you want
6432    when, for instance, you are emulating a right shift by a
6433    rotate-left-and-mask, because the underlying instructions support
6434    shifts of size 0 but not shifts of size 32.  By comparison, when
6435    extracting x bits from some word you want to use just 32-x, because
6436    the underlying instructions don't support extracting 0 bits but do
6437    support extracting the whole word (32 bits in this case).  */
6438
6439 const struct powerpc_macro powerpc_macros[] = {
6440 {"extldi",   4, PPC64,  "rldicr %0,%1,%3,(%2)-1"},
6441 {"extldi.",  4, PPC64,  "rldicr. %0,%1,%3,(%2)-1"},
6442 {"extrdi",   4, PPC64,  "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6443 {"extrdi.",  4, PPC64,  "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
6444 {"insrdi",   4, PPC64,  "rldimi %0,%1,64-((%2)+(%3)),%3"},
6445 {"insrdi.",  4, PPC64,  "rldimi. %0,%1,64-((%2)+(%3)),%3"},
6446 {"rotrdi",   3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
6447 {"rotrdi.",  3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
6448 {"sldi",     3, PPC64,  "rldicr %0,%1,%2,63-(%2)"},
6449 {"sldi.",    3, PPC64,  "rldicr. %0,%1,%2,63-(%2)"},
6450 {"srdi",     3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
6451 {"srdi.",    3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
6452 {"clrrdi",   3, PPC64,  "rldicr %0,%1,0,63-(%2)"},
6453 {"clrrdi.",  3, PPC64,  "rldicr. %0,%1,0,63-(%2)"},
6454 {"clrlsldi", 4, PPC64,  "rldic %0,%1,%3,(%2)-(%3)"},
6455 {"clrlsldi.",4, PPC64,  "rldic. %0,%1,%3,(%2)-(%3)"},
6456
6457 {"extlwi",   4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
6458 {"extlwi.",  4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
6459 {"extrwi",   4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6460 {"extrwi.",  4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6461 {"inslwi",   4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6462 {"inslwi.",  4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6463 {"insrwi",   4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6464 {"insrwi.",  4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6465 {"rotrwi",   3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6466 {"rotrwi.",  3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6467 {"slwi",     3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
6468 {"sli",      3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
6469 {"slwi.",    3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
6470 {"sli.",     3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
6471 {"srwi",     3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6472 {"sri",      3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6473 {"srwi.",    3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6474 {"sri.",     3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6475 {"clrrwi",   3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
6476 {"clrrwi.",  3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
6477 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6478 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
6479
6480 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
6481 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
6482 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
6483 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
6484 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
6485 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
6486 {"e_slwi",   3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
6487 {"e_srwi",   3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
6488 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
6489 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
6490 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
6491 };
6492
6493 const int powerpc_num_macros =
6494   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);