1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2022 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "opcode/ppc.h"
27 /* This file holds the PowerPC opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
38 /* The functions used to insert and extract complicated operands. */
40 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
43 insert_arx (uint64_t insn
,
45 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
46 const char **errmsg ATTRIBUTE_UNUSED
)
49 if (value
< 0 || value
>= 16)
51 *errmsg
= _("invalid register");
58 extract_arx (uint64_t insn
,
59 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
60 int *invalid ATTRIBUTE_UNUSED
)
62 return (insn
& 0xf) + 8;
66 insert_ary (uint64_t insn
,
68 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
69 const char **errmsg ATTRIBUTE_UNUSED
)
72 if (value
< 0 || value
>= 16)
74 *errmsg
= _("invalid register");
77 return insn
| (value
<< 4);
81 extract_ary (uint64_t insn
,
82 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
83 int *invalid ATTRIBUTE_UNUSED
)
85 return ((insn
>> 4) & 0xf) + 8;
89 insert_rx (uint64_t insn
,
91 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
94 if (value
>= 0 && value
< 8)
96 else if (value
>= 24 && value
<= 31)
100 *errmsg
= _("invalid register");
107 extract_rx (uint64_t insn
,
108 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
109 int *invalid ATTRIBUTE_UNUSED
)
111 int64_t value
= insn
& 0xf;
112 if (value
>= 0 && value
< 8)
119 insert_ry (uint64_t insn
,
121 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
124 if (value
>= 0 && value
< 8)
126 else if (value
>= 24 && value
<= 31)
130 *errmsg
= _("invalid register");
133 return insn
| (value
<< 4);
137 extract_ry (uint64_t insn
,
138 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
139 int *invalid ATTRIBUTE_UNUSED
)
141 int64_t value
= (insn
>> 4) & 0xf;
142 if (value
>= 0 && value
< 8)
148 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
149 VRA and VRB fields in a VX form instruction when they must be the same.
150 This is used for extended mnemonics like crclr. The extraction function
151 enforces that the fields are the same. */
154 insert_bab (uint64_t insn
,
156 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
157 const char **errmsg ATTRIBUTE_UNUSED
)
160 return insn
| (value
<< 16) | (value
<< 11);
164 extract_bab (uint64_t insn
,
165 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
168 int64_t ba
= (insn
>> 16) & 0x1f;
169 int64_t bb
= (insn
>> 11) & 0x1f;
176 /* The BT, BA and BB fields in an XL form instruction when they must all be
177 the same. This is used for extended mnemonics like crclr. The extraction
178 function enforces that the fields are the same. */
181 insert_btab (uint64_t insn
,
187 return (value
<< 21) | insert_bab (insn
, value
, dialect
, errmsg
);
191 extract_btab (uint64_t insn
,
195 int64_t bt
= (insn
>> 21) & 0x1f;
196 int64_t bab
= extract_bab (insn
, dialect
, invalid
);
203 /* The BD field in a B form instruction when the - modifier is used.
204 This modifier means that the branch is not expected to be taken.
205 For chips built to versions of the architecture prior to version 2
206 (ie. not Power4 compatible), we set the y bit of the BO field to 1
207 if the offset is negative. When extracting, we require that the y
208 bit be 1 and that the offset be positive, since if the y bit is 0
209 we just want to print the normal form of the instruction.
210 Power4 compatible targets use two bits, "a", and "t", instead of
211 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
212 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
213 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
214 for branch on CTR. We only handle the taken/not-taken hint here.
215 Note that we don't relax the conditions tested here when
216 disassembling with -Many because insns using extract_bdm and
217 extract_bdp always occur in pairs. One or the other will always
220 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
223 insert_bdm (uint64_t insn
,
226 const char **errmsg ATTRIBUTE_UNUSED
)
228 if ((dialect
& ISA_V2
) == 0)
230 if ((value
& 0x8000) != 0)
235 if ((insn
& (0x14 << 21)) == (0x04 << 21))
237 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
240 return insn
| (value
& 0xfffc);
244 extract_bdm (uint64_t insn
,
248 if ((dialect
& ISA_V2
) == 0)
250 if (((insn
& (1 << 21)) == 0) != ((insn
& (1 << 15)) == 0))
255 if ((insn
& (0x17 << 21)) != (0x06 << 21)
256 && (insn
& (0x1d << 21)) != (0x18 << 21))
260 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
263 /* The BD field in a B form instruction when the + modifier is used.
264 This is like BDM, above, except that the branch is expected to be
268 insert_bdp (uint64_t insn
,
271 const char **errmsg ATTRIBUTE_UNUSED
)
273 if ((dialect
& ISA_V2
) == 0)
275 if ((value
& 0x8000) == 0)
280 if ((insn
& (0x14 << 21)) == (0x04 << 21))
282 else if ((insn
& (0x14 << 21)) == (0x10 << 21))
285 return insn
| (value
& 0xfffc);
289 extract_bdp (uint64_t insn
,
293 if ((dialect
& ISA_V2
) == 0)
295 if (((insn
& (1 << 21)) == 0) == ((insn
& (1 << 15)) == 0))
300 if ((insn
& (0x17 << 21)) != (0x07 << 21)
301 && (insn
& (0x1d << 21)) != (0x19 << 21))
305 return ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
309 valid_bo_pre_v2 (int64_t value
)
311 /* Certain encodings have bits that are required to be zero.
312 These are (z must be zero, y may be anything):
323 if ((value
& 0x14) == 0)
324 /* BO: 0000y, 0001y, 0100y, 0101y. */
326 else if ((value
& 0x14) == 0x4)
327 /* BO: 001zy, 011zy. */
328 return (value
& 0x2) == 0;
329 else if ((value
& 0x14) == 0x10)
330 /* BO: 1z00y, 1z01y. */
331 return (value
& 0x8) == 0;
334 return value
== 0x14;
338 valid_bo_post_v2 (int64_t value
)
340 /* Certain encodings have bits that are required to be zero.
341 These are (z must be zero, a & t may be anything):
352 if ((value
& 0x14) == 0)
353 /* BO: 0000z, 0001z, 0100z, 0101z. */
354 return (value
& 0x1) == 0;
355 else if ((value
& 0x14) == 0x14)
357 return value
== 0x14;
358 else if ((value
& 0x14) == 0x4)
359 /* BO: 001at, 011at, with "at" == 0b01 being reserved. */
360 return (value
& 0x3) != 1;
361 else if ((value
& 0x14) == 0x10)
362 /* BO: 1a00t, 1a01t, with "at" == 0b01 being reserved. */
363 return (value
& 0x9) != 1;
368 /* Check for legal values of a BO field. */
371 valid_bo (int64_t value
, ppc_cpu_t dialect
, int extract
)
373 int valid_y
= valid_bo_pre_v2 (value
);
374 int valid_at
= valid_bo_post_v2 (value
);
376 /* When disassembling with -Many, accept either encoding on the
377 second pass through opcodes. */
378 if (extract
&& dialect
== ~(ppc_cpu_t
) PPC_OPCODE_ANY
)
379 return valid_y
|| valid_at
;
380 if ((dialect
& ISA_V2
) == 0)
386 /* The BO field in a B form instruction. Warn about attempts to set
387 the field to an illegal value. */
390 insert_bo (uint64_t insn
,
395 if (!valid_bo (value
, dialect
, 0))
396 *errmsg
= _("invalid conditional option");
397 else if (PPC_OP (insn
) == 19
398 && (((insn
>> 1) & 0x3ff) == 528) && ! (value
& 4))
399 *errmsg
= _("invalid counter access");
400 return insn
| ((value
& 0x1f) << 21);
404 extract_bo (uint64_t insn
,
408 int64_t value
= (insn
>> 21) & 0x1f;
409 if (!valid_bo (value
, dialect
, 1))
414 /* For the given BO value, return a bit mask detailing which bits
415 define the branch hints. */
418 get_bo_hint_mask (int64_t bo
, ppc_cpu_t dialect
)
420 if ((dialect
& ISA_V2
) == 0)
422 if ((bo
& 0x14) != 0x14)
423 /* BO: 0000y, 0001y, 001zy, 0100y, 0101y, 011zy, 1z00y, 1z01y . */
431 if ((bo
& 0x14) == 0x4)
432 /* BO: 001at, 011at. */
434 else if ((bo
& 0x14) == 0x10)
435 /* BO: 1a00t, 1a01t. */
438 /* BO: 0000z, 0001z, 0100z, 0101z, 1z1zz. */
443 /* The BO field in a B form instruction when the + or - modifier is used. */
446 insert_boe (uint64_t insn
,
452 int64_t implied_hint
;
453 int64_t hint_mask
= get_bo_hint_mask (value
, dialect
);
456 implied_hint
= hint_mask
;
458 implied_hint
= hint_mask
& ~1;
460 /* The branch hint bit(s) in the BO field must either be zero or exactly
461 match the branch hint bits implied by the '+' or '-' modifier. */
462 if (implied_hint
== 0)
463 *errmsg
= _("BO value implies no branch hint, when using + or - modifier");
464 else if ((value
& hint_mask
) != 0
465 && (value
& hint_mask
) != implied_hint
)
467 if ((dialect
& ISA_V2
) == 0)
468 *errmsg
= _("attempt to set y bit when using + or - modifier");
470 *errmsg
= _("attempt to set 'at' bits when using + or - modifier");
473 value
|= implied_hint
;
475 return insert_bo (insn
, value
, dialect
, errmsg
);
479 extract_boe (uint64_t insn
,
484 int64_t value
= (insn
>> 21) & 0x1f;
485 int64_t implied_hint
;
486 int64_t hint_mask
= get_bo_hint_mask (value
, dialect
);
489 implied_hint
= hint_mask
;
491 implied_hint
= hint_mask
& ~1;
493 if (!valid_bo (value
, dialect
, 1)
495 || (value
& hint_mask
) != implied_hint
)
500 /* The BO field in a B form instruction when the - modifier is used. */
503 insert_bom (uint64_t insn
,
508 return insert_boe (insn
, value
, dialect
, errmsg
, 0);
512 extract_bom (uint64_t insn
,
516 return extract_boe (insn
, dialect
, invalid
, 0);
519 /* The BO field in a B form instruction when the + modifier is used. */
522 insert_bop (uint64_t insn
,
527 return insert_boe (insn
, value
, dialect
, errmsg
, 1);
531 extract_bop (uint64_t insn
,
535 return extract_boe (insn
, dialect
, invalid
, 1);
538 /* The DCMX field in a X form instruction when the field is split
539 into separate DC, DM and DX fields. */
542 insert_dcmxs (uint64_t insn
,
544 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
545 const char **errmsg ATTRIBUTE_UNUSED
)
548 | ((value
& 0x1f) << 16)
549 | ((value
& 0x20) >> 3)
554 extract_dcmxs (uint64_t insn
,
555 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
556 int *invalid ATTRIBUTE_UNUSED
)
558 return (insn
& 0x40) | ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
561 /* The DW field in a X form instruction when the field is split
562 into separate D and DX fields. */
565 insert_dw (uint64_t insn
,
567 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
568 const char **errmsg ATTRIBUTE_UNUSED
)
570 /* DW offsets must be in the range [-512, -8] and be a multiple of 8. */
573 || (value
& 0x7) != 0)
574 *errmsg
= _("invalid offset: must be in the range [-512, -8] "
575 "and be a multiple of 8");
577 return insn
| ((value
& 0xf8) << 18) | ((value
>> 8) & 1);
581 extract_dw (uint64_t insn
,
582 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
583 int *invalid ATTRIBUTE_UNUSED
)
585 int64_t dw
= ((insn
& 1) << 8) | ((insn
>> 18) & 0xf8);
589 /* The D field in a DX form instruction when the field is split
590 into separate D0, D1 and D2 fields. */
593 insert_dxd (uint64_t insn
,
595 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
596 const char **errmsg ATTRIBUTE_UNUSED
)
598 return insn
| (value
& 0xffc1) | ((value
& 0x3e) << 15);
602 extract_dxd (uint64_t insn
,
603 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
604 int *invalid ATTRIBUTE_UNUSED
)
606 uint64_t dxd
= (insn
& 0xffc1) | ((insn
>> 15) & 0x3e);
607 return (dxd
^ 0x8000) - 0x8000;
611 insert_dxdn (uint64_t insn
,
613 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
614 const char **errmsg ATTRIBUTE_UNUSED
)
616 return insert_dxd (insn
, -value
, dialect
, errmsg
);
620 extract_dxdn (uint64_t insn
,
621 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
624 return -extract_dxd (insn
, dialect
, invalid
);
627 /* The D field in a 64-bit D form prefix instruction when the field is split
628 into separate D0 and D1 fields. */
631 insert_d34 (uint64_t insn
,
633 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
634 const char **errmsg ATTRIBUTE_UNUSED
)
636 return insn
| ((value
& 0x3ffff0000ULL
) << 16) | (value
& 0xffff);
640 extract_d34 (uint64_t insn
,
641 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
642 int *invalid ATTRIBUTE_UNUSED
)
644 int64_t mask
= 1ULL << 33;
645 int64_t value
= ((insn
>> 16) & 0x3ffff0000ULL
) | (insn
& 0xffff);
646 value
= (value
^ mask
) - mask
;
650 /* The NSI34 field in an 8-byte D form prefix instruction. This is the same
651 as the SI34 field, only negated. The extraction function always marks it
652 as invalid, since we never want to recognize an instruction which uses
653 a field of this type. */
656 insert_nsi34 (uint64_t insn
,
661 return insert_d34 (insn
, -value
, dialect
, errmsg
);
665 extract_nsi34 (uint64_t insn
,
669 int64_t value
= extract_d34 (insn
, dialect
, invalid
);
674 /* The split IMM32 field in a vector splat insn. */
677 insert_imm32 (uint64_t insn
,
679 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
680 const char **errmsg ATTRIBUTE_UNUSED
)
682 return insn
| ((value
& 0xffff0000) << 16) | (value
& 0xffff);
686 extract_imm32 (uint64_t insn
,
687 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
688 int *invalid ATTRIBUTE_UNUSED
)
690 return (insn
& 0xffff) | ((insn
>> 16) & 0xffff0000);
693 /* The R field in an 8-byte prefix instruction when there are restrictions
694 between R's value and the RA value (ie, they cannot both be non zero). */
697 insert_pcrel (uint64_t insn
,
699 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
703 int64_t ra
= (insn
>> 16) & 0x1f;
704 if (ra
!= 0 && value
!= 0)
705 *errmsg
= _("invalid R operand");
707 return insn
| (value
<< 52);
711 extract_pcrel (uint64_t insn
,
712 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
715 /* If called with *invalid < 0 to return the value for missing
716 operands, *invalid will be the negative count of missing operands
717 including this one. Return a default value of 1 if the PRA0/PRAQ
718 operand was also omitted (ie. *invalid is -2). Return a default
719 value of 0 if the PRA0/PRAQ operand was not omitted
720 (ie. *invalid is -1). */
722 return ~ *invalid
& 1;
724 int64_t ra
= (insn
>> 16) & 0x1f;
725 int64_t pcrel
= (insn
>> 52) & 0x1;
726 if (ra
!= 0 && pcrel
!= 0)
732 /* Variant of extract_pcrel that sets invalid for R bit set. The idea
733 is to disassemble "paddi rt,0,offset,1" as "pla rt,offset". */
736 extract_pcrel0 (uint64_t insn
,
740 int64_t pcrel
= extract_pcrel (insn
, dialect
, invalid
);
746 /* FXM mask in mfcr and mtcrf instructions. */
749 insert_fxm (uint64_t insn
,
754 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
755 one bit of the mask field is set. */
756 if ((insn
& (1 << 20)) != 0)
758 if (value
== 0 || (value
& -value
) != value
)
760 *errmsg
= _("invalid mask field");
765 /* If only one bit of the FXM field is set, we can use the new form
766 of the instruction, which is faster. Unlike the Power4 branch hint
767 encoding, this is not backward compatible. Do not generate the
768 new form unless -mpower4 has been given, or -many and the two
769 operand form of mfcr was used. */
771 && (value
& -value
) == value
772 && ((dialect
& PPC_OPCODE_POWER4
) != 0
773 || ((dialect
& PPC_OPCODE_ANY
) != 0
774 && (insn
& (0x3ff << 1)) == 19 << 1)))
777 /* Any other value on mfcr is an error. */
778 else if ((insn
& (0x3ff << 1)) == 19 << 1)
780 /* A value of -1 means we used the one operand form of
781 mfcr which is valid. */
783 *errmsg
= _("invalid mfcr mask");
787 return insn
| ((value
& 0xff) << 12);
791 extract_fxm (uint64_t insn
,
792 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
795 /* Return a value of -1 for a missing optional operand, which is
796 used as a flag by insert_fxm. */
800 int64_t mask
= (insn
>> 12) & 0xff;
801 /* Is this a Power4 insn? */
802 if ((insn
& (1 << 20)) != 0)
804 /* Exactly one bit of MASK should be set. */
805 if (mask
== 0 || (mask
& -mask
) != mask
)
809 /* Check that non-power4 form of mfcr has a zero MASK. */
810 else if ((insn
& (0x3ff << 1)) == 19 << 1)
821 /* L field in the paste. instruction. */
824 insert_l1opt (uint64_t insn
,
826 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
827 const char **errmsg ATTRIBUTE_UNUSED
)
829 return insn
| ((value
& 1) << 21);
833 extract_l1opt (uint64_t insn
,
834 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
837 /* Return a value of 1 for a missing optional operand. */
841 return (insn
>> 21) & 1;
845 insert_li20 (uint64_t insn
,
847 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
848 const char **errmsg ATTRIBUTE_UNUSED
)
851 | ((value
& 0xf0000) >> 5)
852 | ((value
& 0x0f800) << 5)
857 extract_li20 (uint64_t insn
,
858 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
859 int *invalid ATTRIBUTE_UNUSED
)
861 return ((((insn
<< 5) & 0xf0000)
862 | ((insn
>> 5) & 0xf800)
863 | (insn
& 0x7ff)) ^ 0x80000) - 0x80000;
866 /* The 2-bit/3-bit L or 2-bit WC field in a SYNC, DCBF or WAIT instruction.
867 For SYNC, some L values are reserved:
868 * Values 6 and 7 are reserved on newer server cpus.
869 * Value 3 is reserved on all server cpus.
870 * Value 2 is reserved on all other cpus.
871 For DCBF, some L values are reserved:
872 * Values 2, 5 and 7 are reserved on all cpus.
873 For WAIT, some WC values are reserved:
874 * Value 3 is reserved on all server cpus.
875 * Values 1 and 2 are reserved on older server cpus. */
878 insert_ls (uint64_t insn
,
885 if (((insn
>> 1) & 0x3ff) == 598)
887 /* For SYNC, some L values are illegal. */
888 mask
= (dialect
& PPC_OPCODE_POWER10
) ? 0x7 : 0x3;
890 /* If the value is within range, check for other illegal values. */
891 if ((value
& mask
) == value
)
895 if (dialect
& PPC_OPCODE_POWER4
)
901 *errmsg
= _("illegal L operand value");
907 else if (((insn
>> 1) & 0x3ff) == 86)
909 /* For DCBF, some L values are illegal. */
910 mask
= (dialect
& PPC_OPCODE_POWER10
) ? 0x7 : 0x3;
912 /* If the value is within range, check for other illegal values. */
913 if ((value
& mask
) == value
)
919 *errmsg
= _("illegal L operand value");
927 /* For WAIT, some WC values are illegal. */
930 /* If the value is within range, check for other illegal values. */
931 if ((dialect
& PPC_OPCODE_A2
) == 0
932 && (dialect
& PPC_OPCODE_E500MC
) == 0
933 && (value
& mask
) == value
)
938 if (dialect
& PPC_OPCODE_POWER10
)
942 *errmsg
= _("illegal WC operand value");
949 return insn
| ((value
& mask
) << 21);
953 extract_ls (uint64_t insn
,
959 /* Missing optional operands have a value of zero. */
963 if (((insn
>> 1) & 0x3ff) == 598)
965 /* For SYNC, some L values are illegal. */
966 int64_t mask
= (dialect
& PPC_OPCODE_POWER10
) ? 0x7 : 0x3;
968 value
= (insn
>> 21) & mask
;
972 if (dialect
& PPC_OPCODE_POWER4
)
984 else if (((insn
>> 1) & 0x3ff) == 86)
986 /* For DCBF, some L values are illegal. */
987 int64_t mask
= (dialect
& PPC_OPCODE_POWER10
) ? 0x7 : 0x3;
989 value
= (insn
>> 21) & mask
;
1003 /* For WAIT, some WC values are illegal. */
1004 value
= (insn
>> 21) & 0x3;
1005 if ((dialect
& PPC_OPCODE_A2
) == 0
1006 && (dialect
& PPC_OPCODE_E500MC
) == 0)
1011 if (dialect
& PPC_OPCODE_POWER10
)
1025 /* The 4-bit E field in a sync instruction that accepts 2 operands.
1026 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1027 the complement of ESYNC-bit2. */
1030 insert_esync (uint64_t insn
,
1032 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1033 const char **errmsg
)
1035 uint64_t ls
= (insn
>> 21) & 0x03;
1038 && ((~value
>> 1) & 0x1) != ls
)
1039 *errmsg
= _("incompatible L operand value");
1041 return insn
| ((value
& 0xf) << 16);
1045 extract_esync (uint64_t insn
,
1046 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1049 /* Missing optional operands have a value of zero. */
1053 uint64_t ls
= (insn
>> 21) & 0x3;
1054 uint64_t value
= (insn
>> 16) & 0xf;
1056 && ((~value
>> 1) & 0x1) != ls
)
1061 /* The n operand of clrrwi, which sets the ME field to 31 - n. */
1064 insert_crwn (uint64_t insn
,
1066 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1067 const char **errmsg ATTRIBUTE_UNUSED
)
1069 return insn
| ((~value
& 0x1f) << 1);
1073 extract_crwn (uint64_t insn
,
1074 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1075 int *invalid ATTRIBUTE_UNUSED
)
1077 return ~(insn
>> 1) & 0x1f;
1080 /* The n operand of extlwi, which sets the ME field to n - 1. */
1083 insert_elwn (uint64_t insn
,
1085 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1086 const char **errmsg ATTRIBUTE_UNUSED
)
1088 return insn
| (((value
- 1) & 0x1f) << 1);
1092 extract_elwn (uint64_t insn
,
1093 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1094 int *invalid ATTRIBUTE_UNUSED
)
1096 return ((insn
>> 1) & 0x1f) + 1;
1099 /* The n operand of extrwi, sets MB = 32 - n. */
1102 insert_erwn (uint64_t insn
,
1104 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1105 const char **errmsg ATTRIBUTE_UNUSED
)
1107 return insn
| ((-value
& 0x1f) << 6);
1111 extract_erwn (uint64_t insn
,
1112 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1113 int *invalid ATTRIBUTE_UNUSED
)
1115 return (~(insn
>> 6) & 0x1f) + 1;
1118 /* The b operand of extrwi, sets SH = b + n. */
1121 insert_erwb (uint64_t insn
,
1124 const char **errmsg ATTRIBUTE_UNUSED
)
1126 int64_t n
= extract_erwn (insn
, dialect
, NULL
);
1127 return insn
| (((n
+ value
) & 0x1f) << 11);
1131 extract_erwb (uint64_t insn
,
1133 int *invalid ATTRIBUTE_UNUSED
)
1135 int64_t n
= extract_erwn (insn
, dialect
, NULL
);
1136 return ((insn
>> 11) - n
) & 0x1f;
1139 /* The n and b operands of clrlslwi. */
1142 insert_cslwn (uint64_t insn
,
1144 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1145 const char **errmsg ATTRIBUTE_UNUSED
)
1147 uint64_t mb
= 0x1f << 6;
1148 int64_t b
= (insn
>> 6) & 0x1f;
1149 return ((insn
& ~mb
) | ((value
& 0x1f) << 11) | (((b
- value
) & 0x1f) << 6)
1150 | ((~value
& 0x1f) << 1));
1154 extract_cslwb (uint64_t insn
,
1155 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1158 int64_t sh
= (insn
>> 11) & 0x1f;
1159 int64_t mb
= (insn
>> 6) & 0x1f;
1160 int64_t me
= (insn
>> 1) & 0x1f;
1163 return (mb
+ sh
) & 0x1f;
1166 /* The n and b operands of inslwi. */
1169 insert_ilwb (uint64_t insn
,
1171 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1172 const char **errmsg ATTRIBUTE_UNUSED
)
1174 uint64_t me
= 0x1f << 1;
1175 int64_t n
= (insn
>> 1) & 0x1f;
1176 return ((insn
& ~me
) | ((-value
& 0x1f) << 11) | ((value
& 0x1f) << 6)
1177 | (((value
+ n
- 1) & 0x1f) << 1));
1181 extract_ilwn (uint64_t insn
,
1182 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1185 int64_t sh
= (insn
>> 11) & 0x1f;
1186 int64_t mb
= (insn
>> 6) & 0x1f;
1187 int64_t me
= (insn
>> 1) & 0x1f;
1188 if (((sh
+ mb
) & 0x1f) != 0)
1190 return ((me
- mb
) & 0x1f) + 1;
1193 /* The n and b operands of insrwi. */
1196 insert_irwb (uint64_t insn
,
1198 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1199 const char **errmsg ATTRIBUTE_UNUSED
)
1201 uint64_t me
= 0x1f << 1;
1202 int64_t n
= (insn
>> 1) & 0x1f;
1203 return ((insn
& ~me
) | ((-(value
+ n
) & 0x1f) << 11) | ((value
& 0x1f) << 6)
1204 | (((value
+ n
- 1) & 0x1f) << 1));
1208 extract_irwn (uint64_t insn
,
1209 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1212 int64_t sh
= (insn
>> 11) & 0x1f;
1213 int64_t mb
= (insn
>> 6) & 0x1f;
1214 int64_t me
= (insn
>> 1) & 0x1f;
1215 if (((sh
+ me
+ 1) & 0x1f) != 0)
1217 return ((me
- mb
) & 0x1f) + 1;
1220 /* The MB and ME fields in an M form instruction expressed as a single
1221 operand which is itself a bitmask. The extraction function always
1222 marks it as invalid, since we never want to recognize an
1223 instruction which uses a field of this type. */
1226 insert_mbe (uint64_t insn
,
1228 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1229 const char **errmsg
)
1231 uint64_t uval
, mask
;
1232 long mb
, me
, mx
, count
, last
;
1238 *errmsg
= _("illegal bitmask");
1244 if ((uval
& 1) != 0)
1250 /* mb: location of last 0->1 transition */
1251 /* me: location of last 1->0 transition */
1252 /* count: # transitions */
1254 for (mx
= 0, mask
= (uint64_t) 1 << 31; mx
< 32; ++mx
, mask
>>= 1)
1256 if ((uval
& mask
) && !last
)
1262 else if (!(uval
& mask
) && last
)
1272 if (count
!= 2 && (count
!= 0 || ! last
))
1273 *errmsg
= _("illegal bitmask");
1275 return insn
| (mb
<< 6) | ((me
- 1) << 1);
1279 extract_mbe (uint64_t insn
,
1280 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1289 mb
= (insn
>> 6) & 0x1f;
1290 me
= (insn
>> 1) & 0x1f;
1294 for (i
= mb
; i
<= me
; i
++)
1295 ret
|= (uint64_t) 1 << (31 - i
);
1297 else if (mb
== me
+ 1)
1299 else /* (mb > me + 1) */
1302 for (i
= me
+ 1; i
< mb
; i
++)
1303 ret
&= ~((uint64_t) 1 << (31 - i
));
1308 /* The MB or ME field in an MD or MDS form instruction. The high bit
1309 is wrapped to the low end. */
1312 insert_mb6 (uint64_t insn
,
1314 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1315 const char **errmsg ATTRIBUTE_UNUSED
)
1317 return insn
| ((value
& 0x1f) << 6) | (value
& 0x20);
1321 extract_mb6 (uint64_t insn
,
1322 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1323 int *invalid ATTRIBUTE_UNUSED
)
1325 return ((insn
>> 6) & 0x1f) | (insn
& 0x20);
1328 /* The n operand of extrdi, which sets MB field. */
1331 insert_erdn (uint64_t insn
,
1334 const char **errmsg
)
1336 return insert_mb6 (insn
, -value
, dialect
, errmsg
);
1340 extract_erdn (uint64_t insn
,
1344 return (~extract_mb6 (insn
, dialect
, invalid
) & 63) + 1;
1347 /* The n operand of extldi, which sets ME field. */
1350 insert_eldn (uint64_t insn
,
1353 const char **errmsg
)
1355 return insert_mb6 (insn
, value
- 1, dialect
, errmsg
);
1359 extract_eldn (uint64_t insn
,
1363 return extract_mb6 (insn
, dialect
, invalid
) + 1;
1366 /* The n operand of clrrdi, which set ME field. */
1369 insert_crdn (uint64_t insn
,
1372 const char **errmsg
)
1374 return insert_mb6 (insn
, 63 - value
, dialect
, errmsg
);
1378 extract_crdn (uint64_t insn
,
1382 return 63 - extract_mb6 (insn
, dialect
, invalid
);
1385 /* The NB field in an X form instruction. The value 32 is stored as
1389 extract_nb (uint64_t insn
,
1390 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1391 int *invalid ATTRIBUTE_UNUSED
)
1395 ret
= (insn
>> 11) & 0x1f;
1401 /* The NB field in an lswi instruction, which has special value
1402 restrictions. The value 32 is stored as 0. */
1405 insert_nbi (uint64_t insn
,
1407 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1408 const char **errmsg ATTRIBUTE_UNUSED
)
1410 int64_t rtvalue
= (insn
>> 21) & 0x1f;
1411 int64_t ravalue
= (insn
>> 16) & 0x1f;
1415 if (rtvalue
+ (value
+ 3) / 4 > (rtvalue
> ravalue
? ravalue
+ 32
1417 *errmsg
= _("address register in load range");
1418 return insn
| ((value
& 0x1f) << 11);
1421 /* The NSI field in a D form instruction. This is the same as the SI
1422 field, only negated. The extraction function always marks it as
1423 invalid, since we never want to recognize an instruction which uses
1424 a field of this type. */
1427 insert_nsi (uint64_t insn
,
1429 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1430 const char **errmsg ATTRIBUTE_UNUSED
)
1432 return insn
| (-value
& 0xffff);
1436 extract_nsi (uint64_t insn
,
1437 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1441 return -(((insn
& 0xffff) ^ 0x8000) - 0x8000);
1444 /* The 2-bit SC field in a SYNC or PL field in a WAIT instruction.
1445 For WAIT, some PL values are reserved:
1446 * Values 1, 2 and 3 are reserved. */
1449 insert_pl (uint64_t insn
,
1451 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1452 const char **errmsg
)
1454 /* For WAIT, some PL values are illegal. */
1455 if (((insn
>> 1) & 0x3ff) == 30
1457 *errmsg
= _("illegal PL operand value");
1458 return insn
| ((value
& 0x3) << 16);
1462 extract_pl (uint64_t insn
,
1463 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1466 /* Missing optional operands have a value of zero. */
1470 uint64_t value
= (insn
>> 16) & 0x3;
1472 /* For WAIT, some PL values are illegal. */
1473 if (((insn
>> 1) & 0x3ff) == 30
1479 /* The RA field in a D or X form instruction which is an updating
1480 load, which means that the RA field may not be zero and may not
1481 equal the RT field. */
1484 insert_ral (uint64_t insn
,
1486 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1487 const char **errmsg
)
1490 || (uint64_t) value
== ((insn
>> 21) & 0x1f))
1491 *errmsg
= "invalid register operand when updating";
1492 return insn
| ((value
& 0x1f) << 16);
1496 extract_ral (uint64_t insn
,
1497 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1500 int64_t rtvalue
= (insn
>> 21) & 0x1f;
1501 int64_t ravalue
= (insn
>> 16) & 0x1f;
1503 if (rtvalue
== ravalue
|| ravalue
== 0)
1508 /* The RA field in an lmw instruction, which has special value
1512 insert_ram (uint64_t insn
,
1514 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1515 const char **errmsg
)
1517 if ((uint64_t) value
>= ((insn
>> 21) & 0x1f))
1518 *errmsg
= _("index register in load range");
1519 return insn
| ((value
& 0x1f) << 16);
1523 extract_ram (uint64_t insn
,
1524 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1527 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
1528 uint64_t ravalue
= (insn
>> 16) & 0x1f;
1530 if (ravalue
>= rtvalue
)
1535 /* The RA field in the DQ form lq or an lswx instruction, which have special
1536 value restrictions. */
1539 insert_raq (uint64_t insn
,
1541 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1542 const char **errmsg
)
1544 int64_t rtvalue
= (insn
>> 21) & 0x1f;
1546 if (value
== rtvalue
)
1547 *errmsg
= _("source and target register operands must be different");
1548 return insn
| ((value
& 0x1f) << 16);
1552 extract_raq (uint64_t insn
,
1553 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1556 /* Missing optional operands have a value of zero. */
1560 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
1561 uint64_t ravalue
= (insn
>> 16) & 0x1f;
1562 if (ravalue
== rtvalue
)
1567 /* The RA field in a D or X form instruction which is an updating
1568 store or an updating floating point load, which means that the RA
1569 field may not be zero. */
1572 insert_ras (uint64_t insn
,
1574 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1575 const char **errmsg
)
1578 *errmsg
= _("invalid register operand when updating");
1579 return insn
| ((value
& 0x1f) << 16);
1583 extract_ras (uint64_t insn
,
1584 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1587 uint64_t ravalue
= (insn
>> 16) & 0x1f;
1594 /* The RS and RB fields in an X form instruction when they must be the same.
1595 This is used for extended mnemonics like mr. The extraction function
1596 enforces that the fields are the same. */
1599 insert_rsb (uint64_t insn
,
1601 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1602 const char **errmsg ATTRIBUTE_UNUSED
)
1605 return insn
| (value
<< 21) | (value
<< 11);
1609 extract_rsb (uint64_t insn
,
1610 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1613 int64_t rs
= (insn
>> 21) & 0x1f;
1614 int64_t rb
= (insn
>> 11) & 0x1f;
1621 /* The RB field in an lswx instruction, which has special value
1625 insert_rbx (uint64_t insn
,
1627 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1628 const char **errmsg
)
1630 int64_t rtvalue
= (insn
>> 21) & 0x1f;
1632 if (value
== rtvalue
)
1633 *errmsg
= _("source and target register operands must be different");
1634 return insn
| ((value
& 0x1f) << 11);
1638 extract_rbx (uint64_t insn
,
1639 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1642 uint64_t rtvalue
= (insn
>> 21) & 0x1f;
1643 uint64_t rbvalue
= (insn
>> 11) & 0x1f;
1645 if (rbvalue
== rtvalue
)
1650 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1652 insert_sci8 (uint64_t insn
,
1654 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1655 const char **errmsg
)
1657 uint64_t fill_scale
= 0;
1658 uint64_t ui8
= value
;
1660 if ((ui8
& 0xffffff00) == 0)
1662 else if ((ui8
& 0xffffff00) == 0xffffff00)
1664 else if ((ui8
& 0xffff00ff) == 0)
1666 fill_scale
= 1 << 8;
1669 else if ((ui8
& 0xffff00ff) == 0xffff00ff)
1671 fill_scale
= 0x400 | (1 << 8);
1674 else if ((ui8
& 0xff00ffff) == 0)
1676 fill_scale
= 2 << 8;
1679 else if ((ui8
& 0xff00ffff) == 0xff00ffff)
1681 fill_scale
= 0x400 | (2 << 8);
1684 else if ((ui8
& 0x00ffffff) == 0)
1686 fill_scale
= 3 << 8;
1689 else if ((ui8
& 0x00ffffff) == 0x00ffffff)
1691 fill_scale
= 0x400 | (3 << 8);
1696 *errmsg
= _("illegal immediate value");
1700 return insn
| fill_scale
| (ui8
& 0xff);
1704 extract_sci8 (uint64_t insn
,
1705 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1706 int *invalid ATTRIBUTE_UNUSED
)
1708 int64_t fill
= insn
& 0x400;
1709 int64_t scale_factor
= (insn
& 0x300) >> 5;
1710 int64_t value
= (insn
& 0xff) << scale_factor
;
1713 value
|= ~((int64_t) 0xff << scale_factor
);
1718 insert_sci8n (uint64_t insn
,
1721 const char **errmsg
)
1723 return insert_sci8 (insn
, -value
, dialect
, errmsg
);
1727 extract_sci8n (uint64_t insn
,
1731 return -extract_sci8 (insn
, dialect
, invalid
);
1735 insert_oimm (uint64_t insn
,
1737 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1738 const char **errmsg ATTRIBUTE_UNUSED
)
1740 return insn
| (((value
- 1) & 0x1f) << 4);
1744 extract_oimm (uint64_t insn
,
1745 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1746 int *invalid ATTRIBUTE_UNUSED
)
1748 return ((insn
>> 4) & 0x1f) + 1;
1751 /* The n operand of rotrwi, sets SH = 32 - n. */
1754 insert_rrwn (uint64_t insn
,
1756 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1757 const char **errmsg ATTRIBUTE_UNUSED
)
1759 return insn
| ((-value
& 0x1f) << 11);
1763 extract_rrwn (uint64_t insn
,
1764 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1765 int *invalid ATTRIBUTE_UNUSED
)
1767 return 31 & -(insn
>> 11);
1770 /* The n operand of slwi, sets SH = n and ME = 31 - n. */
1773 insert_slwn (uint64_t insn
,
1775 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1776 const char **errmsg ATTRIBUTE_UNUSED
)
1778 return insn
| ((value
& 0x1f) << 11) | ((~value
& 0x1f) << 1);
1782 extract_slwn (uint64_t insn
,
1783 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1786 int64_t sh
= (insn
>> 11) & 0x1f;
1787 int64_t nme
= ~(insn
>> 1) & 0x1f;
1793 /* The n operand of srwi, sets SH = 32 - n and MB = n. */
1796 insert_srwn (uint64_t insn
,
1798 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1799 const char **errmsg ATTRIBUTE_UNUSED
)
1801 return insn
| ((-value
& 0x1f) << 11) | ((value
& 0x1f) << 6);
1805 extract_srwn (uint64_t insn
,
1806 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1809 int64_t nsh
= -(insn
>> 11) & 0x1f;
1810 int64_t mb
= (insn
>> 6) & 0x1f;
1816 /* The SH field in an MD form instruction. This is split. */
1819 insert_sh6 (uint64_t insn
,
1821 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1822 const char **errmsg ATTRIBUTE_UNUSED
)
1824 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
1828 extract_sh6 (uint64_t insn
,
1829 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1830 int *invalid ATTRIBUTE_UNUSED
)
1832 return ((insn
>> 11) & 0x1f) | ((insn
<< 4) & 0x20);
1835 /* The n operand of rotrdi, which writes to SH field. */
1838 insert_rrdn (uint64_t insn
,
1841 const char **errmsg
)
1843 return insert_sh6 (insn
, -value
, dialect
, errmsg
);
1847 extract_rrdn (uint64_t insn
,
1851 return -extract_sh6 (insn
, dialect
, invalid
) & 63;
1854 /* The n operand of sldi, which writes to SH and ME fields. */
1857 insert_sldn (uint64_t insn
,
1860 const char **errmsg
)
1862 insn
= insert_sh6 (insn
, value
, dialect
, errmsg
);
1863 return insert_crdn (insn
, value
, dialect
, errmsg
);
1867 extract_sldn (uint64_t insn
,
1871 int64_t sh
= extract_sh6 (insn
, dialect
, invalid
);
1872 int64_t me
= extract_crdn (insn
, dialect
, invalid
);
1878 /* The n operand of srdi, which writes to SH and MB fields. */
1881 insert_srdn (uint64_t insn
,
1884 const char **errmsg
)
1886 insn
= insert_rrdn (insn
, value
, dialect
, errmsg
);
1887 return insert_mb6 (insn
, value
, dialect
, errmsg
);
1891 extract_srdn (uint64_t insn
,
1895 int64_t sh
= extract_rrdn (insn
, dialect
, invalid
);
1896 int64_t mb
= extract_mb6 (insn
, dialect
, invalid
);
1902 /* The b operand of extrdi, which sets SH field. */
1905 insert_erdb (uint64_t insn
,
1908 const char **errmsg
)
1910 int64_t n
= extract_erdn (insn
, dialect
, NULL
);
1911 return insert_sh6 (insn
, value
+ n
, dialect
, errmsg
);
1915 extract_erdb (uint64_t insn
,
1919 int64_t sh
= extract_sh6 (insn
, dialect
, invalid
);
1920 int64_t n
= extract_erdn (insn
, dialect
, invalid
);
1921 return (sh
- n
) & 63;
1924 /* The b and n operands of clrlsldi. */
1927 insert_csldn (uint64_t insn
,
1930 const char **errmsg
)
1932 uint64_t mb6
= 0x3f << 5;
1933 int64_t b
= extract_mb6 (insn
, dialect
, NULL
);
1934 insn
= insert_mb6 (insn
& ~mb6
, b
- value
, dialect
, errmsg
);
1935 return insert_sh6 (insn
, value
, dialect
, errmsg
);
1939 extract_csldb (uint64_t insn
,
1943 int64_t sh
= extract_sh6 (insn
, dialect
, invalid
);
1944 int64_t mb
= extract_mb6 (insn
, dialect
, invalid
);
1945 return (mb
+ sh
) & 63;
1948 /* The b and n operands of insrdi. */
1951 insert_irdb (uint64_t insn
,
1954 const char **errmsg
)
1956 uint64_t sh6
= (0x1f << 11) | 2;
1957 int64_t n
= extract_sh6 (insn
, dialect
, NULL
);
1958 insn
= insert_sh6 (insn
& ~sh6
, -(value
+ n
), dialect
, errmsg
);
1959 return insert_mb6 (insn
, value
, dialect
, errmsg
);
1963 extract_irdn (uint64_t insn
,
1967 int64_t sh
= extract_sh6 (insn
, dialect
, invalid
);
1968 int64_t mb
= extract_mb6 (insn
, dialect
, invalid
);
1969 return (~(mb
+ sh
) & 63) + 1;
1972 /* The SPR field in an XFX form instruction. This is flipped--the
1973 lower 5 bits are stored in the upper 5 and vice- versa. */
1976 insert_spr (uint64_t insn
,
1978 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1979 const char **errmsg ATTRIBUTE_UNUSED
)
1981 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
1985 extract_spr (uint64_t insn
,
1986 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
1987 int *invalid ATTRIBUTE_UNUSED
)
1989 return ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
1992 /* Some dialects have 8 [DI]BAT registers instead of the standard 4. */
1993 #define ALLOW8_BAT (PPC_OPCODE_750)
1996 insert_sprbat (uint64_t insn
,
1999 const char **errmsg
)
2001 if ((uint64_t) value
> 7
2002 || ((uint64_t) value
> 3 && (dialect
& ALLOW8_BAT
) == 0))
2003 *errmsg
= _("invalid bat number");
2005 /* If this is [di]bat4..7 then use spr 560..575, otherwise 528..543. */
2006 if ((uint64_t) value
> 3)
2007 value
= ((value
& 3) << 6) | 1;
2011 return insn
| (value
<< 11);
2015 extract_sprbat (uint64_t insn
,
2019 uint64_t val
= (insn
>> 17) & 0x3;
2021 val
= val
+ ((insn
>> 9) & 0x4);
2022 if (val
> 3 && (dialect
& ALLOW8_BAT
) == 0)
2027 /* Some dialects have 8 SPRG registers instead of the standard 4. */
2028 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
2031 insert_sprg (uint64_t insn
,
2034 const char **errmsg
)
2036 if ((uint64_t) value
> 7
2037 || ((uint64_t) value
> 3 && (dialect
& ALLOW8_SPRG
) == 0))
2038 *errmsg
= _("invalid sprg number");
2040 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2041 user mode. Anything else must use spr 272..279. */
2042 if ((uint64_t) value
<= 3 || (insn
& 0x100) != 0)
2045 return insn
| ((value
& 0x17) << 16);
2049 extract_sprg (uint64_t insn
,
2053 uint64_t val
= (insn
>> 16) & 0x1f;
2055 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
2056 If not BOOKE, 405 or VLE, then both use only 272..275. */
2057 if ((val
- 0x10 > 3 && (dialect
& ALLOW8_SPRG
) == 0)
2058 || (val
- 0x10 > 7 && (insn
& 0x100) != 0)
2065 /* The TBR field in an XFX instruction. This is just like SPR, but it
2069 insert_tbr (uint64_t insn
,
2071 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2072 const char **errmsg
)
2074 if (value
!= 268 && value
!= 269)
2075 *errmsg
= _("invalid tbr number");
2076 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x3e0) << 6);
2080 extract_tbr (uint64_t insn
,
2081 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2084 /* Missing optional operands have a value of 268. */
2088 int64_t ret
= ((insn
>> 16) & 0x1f) | ((insn
>> 6) & 0x3e0);
2089 if (ret
!= 268 && ret
!= 269)
2094 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2097 insert_xt6 (uint64_t insn
,
2099 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2100 const char **errmsg ATTRIBUTE_UNUSED
)
2102 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 5);
2106 extract_xt6 (uint64_t insn
,
2107 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2108 int *invalid ATTRIBUTE_UNUSED
)
2110 return ((insn
<< 5) & 0x20) | ((insn
>> 21) & 0x1f);
2113 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
2115 insert_xtq6 (uint64_t insn
,
2117 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2118 const char **errmsg ATTRIBUTE_UNUSED
)
2120 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) >> 2);
2124 extract_xtq6 (uint64_t insn
,
2125 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2126 int *invalid ATTRIBUTE_UNUSED
)
2128 return ((insn
<< 2) & 0x20) | ((insn
>> 21) & 0x1f);
2131 /* The XA field in an XX3 form instruction. This is split. */
2134 insert_xa6 (uint64_t insn
,
2136 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2137 const char **errmsg ATTRIBUTE_UNUSED
)
2139 return insn
| ((value
& 0x1f) << 16) | ((value
& 0x20) >> 3);
2143 extract_xa6 (uint64_t insn
,
2144 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2145 int *invalid ATTRIBUTE_UNUSED
)
2147 return ((insn
<< 3) & 0x20) | ((insn
>> 16) & 0x1f);
2150 /* The XA field in an MMA XX3 form instruction. This is split
2151 and must not overlap with the ACC operand. */
2154 insert_xa6a (uint64_t insn
,
2157 const char **errmsg
)
2159 int64_t acc
= (insn
>> 23) & 0x7;
2160 if ((value
>> 2) == acc
)
2161 *errmsg
= _("VSR overlaps ACC operand");
2162 return insert_xa6 (insn
, value
, dialect
, errmsg
);
2166 extract_xa6a (uint64_t insn
,
2170 int64_t acc
= (insn
>> 23) & 0x7;
2171 int64_t value
= extract_xa6 (insn
, dialect
, invalid
);
2172 if ((value
>> 2) == acc
)
2177 /* The XB field in an XX3 form instruction. This is split. */
2180 insert_xb6 (uint64_t insn
,
2182 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2183 const char **errmsg ATTRIBUTE_UNUSED
)
2185 return insn
| ((value
& 0x1f) << 11) | ((value
& 0x20) >> 4);
2189 extract_xb6 (uint64_t insn
,
2190 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2191 int *invalid ATTRIBUTE_UNUSED
)
2193 return ((insn
<< 4) & 0x20) | ((insn
>> 11) & 0x1f);
2196 /* The XB field in an MMA XX3 form instruction. This is split
2197 and must not overlap with the ACC operand. */
2200 insert_xb6a (uint64_t insn
,
2203 const char **errmsg
)
2205 int64_t acc
= (insn
>> 23) & 0x7;
2206 if ((value
>> 2) == acc
)
2207 *errmsg
= _("VSR overlaps ACC operand");
2208 return insert_xb6 (insn
, value
, dialect
, errmsg
);
2212 extract_xb6a (uint64_t insn
,
2216 int64_t acc
= (insn
>> 23) & 0x7;
2217 int64_t value
= extract_xb6 (insn
, dialect
, invalid
);
2218 if ((value
>> 2) == acc
)
2223 /* The XA and XB fields in an XX3 form instruction when they must be the same.
2224 This is used for extended mnemonics like xvmovdp. The extraction function
2225 enforces that the fields are the same. */
2228 insert_xab6 (uint64_t insn
,
2231 const char **errmsg
)
2233 return insert_xa6 (insn
, value
, dialect
, errmsg
)
2234 | insert_xb6 (insn
, value
, dialect
, errmsg
);
2238 extract_xab6 (uint64_t insn
,
2242 int64_t xa6
= extract_xa6 (insn
, dialect
, invalid
);
2243 int64_t xb6
= extract_xb6 (insn
, dialect
, invalid
);
2250 /* The XC field in an XX4 form instruction. This is split. */
2253 insert_xc6 (uint64_t insn
,
2255 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2256 const char **errmsg ATTRIBUTE_UNUSED
)
2258 return insn
| ((value
& 0x1f) << 6) | ((value
& 0x20) >> 2);
2262 extract_xc6 (uint64_t insn
,
2263 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2264 int *invalid ATTRIBUTE_UNUSED
)
2266 return ((insn
<< 2) & 0x20) | ((insn
>> 6) & 0x1f);
2269 /* The split XTp field in a vector paired insn. */
2272 insert_xtp (uint64_t insn
,
2274 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2275 const char **errmsg ATTRIBUTE_UNUSED
)
2277 return insn
| ((value
& 0x1e) << 21) | ((value
& 0x20) << (21 - 5));
2281 extract_xtp (uint64_t insn
,
2282 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2283 int *invalid ATTRIBUTE_UNUSED
)
2285 return ((insn
>> (21 - 5)) & 0x20) | ((insn
>> 21) & 0x1e);
2288 /* The split XT field in a vector splat insn. */
2291 insert_xts (uint64_t insn
,
2293 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2294 const char **errmsg ATTRIBUTE_UNUSED
)
2296 return insn
| ((value
& 0x1f) << 21) | ((value
& 0x20) << (16 - 5));
2300 extract_xts (uint64_t insn
,
2301 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2302 int *invalid ATTRIBUTE_UNUSED
)
2304 return ((insn
>> (16 - 5)) & 0x20) | ((insn
>> 21) & 0x1f);
2308 insert_dm (uint64_t insn
,
2310 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2311 const char **errmsg
)
2313 if (value
!= 0 && value
!= 1)
2314 *errmsg
= _("invalid constant");
2315 return insn
| (((value
) ? 3 : 0) << 8);
2319 extract_dm (uint64_t insn
,
2320 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2323 int64_t value
= (insn
>> 8) & 3;
2324 if (value
!= 0 && value
!= 3)
2326 return (value
) ? 1 : 0;
2329 /* The VLESIMM field in an I16A form instruction. This is split. */
2332 insert_vlesi (uint64_t insn
,
2334 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2335 const char **errmsg ATTRIBUTE_UNUSED
)
2337 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2341 extract_vlesi (uint64_t insn
,
2342 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2343 int *invalid ATTRIBUTE_UNUSED
)
2345 int64_t value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2346 value
= (value
^ 0x8000) - 0x8000;
2351 insert_vlensi (uint64_t insn
,
2353 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2354 const char **errmsg ATTRIBUTE_UNUSED
)
2357 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2360 extract_vlensi (uint64_t insn
,
2361 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2364 int64_t value
= ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2365 value
= (value
^ 0x8000) - 0x8000;
2366 /* Don't use for disassembly. */
2371 /* The VLEUIMM field in an I16A form instruction. This is split. */
2374 insert_vleui (uint64_t insn
,
2376 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2377 const char **errmsg ATTRIBUTE_UNUSED
)
2379 return insn
| ((value
& 0xf800) << 10) | (value
& 0x7ff);
2383 extract_vleui (uint64_t insn
,
2384 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2385 int *invalid ATTRIBUTE_UNUSED
)
2387 return ((insn
>> 10) & 0xf800) | (insn
& 0x7ff);
2390 /* The VLEUIMML field in an I16L form instruction. This is split. */
2393 insert_vleil (uint64_t insn
,
2395 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2396 const char **errmsg ATTRIBUTE_UNUSED
)
2398 return insn
| ((value
& 0xf800) << 5) | (value
& 0x7ff);
2402 extract_vleil (uint64_t insn
,
2403 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2404 int *invalid ATTRIBUTE_UNUSED
)
2406 return ((insn
>> 5) & 0xf800) | (insn
& 0x7ff);
2410 insert_evuimm1_ex0 (uint64_t insn
,
2412 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2413 const char **errmsg
)
2415 if (value
<= 0 || value
> 0x1f)
2416 *errmsg
= _("UIMM = 00000 is illegal");
2417 return insn
| ((value
& 0x1f) << 11);
2421 extract_evuimm1_ex0 (uint64_t insn
,
2422 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2425 int64_t value
= ((insn
>> 11) & 0x1f);
2433 insert_evuimm2_ex0 (uint64_t insn
,
2435 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2436 const char **errmsg
)
2438 if (value
<= 0 || value
> 0x3e)
2439 *errmsg
= _("UIMM = 00000 is illegal");
2440 return insn
| ((value
& 0x3e) << 10);
2444 extract_evuimm2_ex0 (uint64_t insn
,
2445 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2448 int64_t value
= ((insn
>> 10) & 0x3e);
2456 insert_evuimm4_ex0 (uint64_t insn
,
2458 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2459 const char **errmsg
)
2461 if (value
<= 0 || value
> 0x7c)
2462 *errmsg
= _("UIMM = 00000 is illegal");
2463 return insn
| ((value
& 0x7c) << 9);
2467 extract_evuimm4_ex0 (uint64_t insn
,
2468 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2471 int64_t value
= ((insn
>> 9) & 0x7c);
2479 insert_evuimm8_ex0 (uint64_t insn
,
2481 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2482 const char **errmsg
)
2484 if (value
<= 0 || value
> 0xf8)
2485 *errmsg
= _("UIMM = 00000 is illegal");
2486 return insn
| ((value
& 0xf8) << 8);
2490 extract_evuimm8_ex0 (uint64_t insn
,
2491 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2494 int64_t value
= ((insn
>> 8) & 0xf8);
2502 insert_evuimm_lt8 (uint64_t insn
,
2504 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2505 const char **errmsg
)
2507 if (value
< 0 || value
> 7)
2508 *errmsg
= _("UIMM values >7 are illegal");
2509 return insn
| ((value
& 0x7) << 11);
2513 extract_evuimm_lt8 (uint64_t insn
,
2514 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2517 int64_t value
= ((insn
>> 11) & 0x1f);
2525 insert_evuimm_lt16 (uint64_t insn
,
2527 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2528 const char **errmsg
)
2530 if (value
< 0 || value
> 15)
2531 *errmsg
= _("UIMM values >15 are illegal");
2532 return insn
| ((value
& 0xf) << 11);
2536 extract_evuimm_lt16 (uint64_t insn
,
2537 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2540 int64_t value
= ((insn
>> 11) & 0x1f);
2548 insert_rD_rS_even (uint64_t insn
,
2550 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2551 const char **errmsg
)
2553 if ((value
& 0x1) != 0)
2554 *errmsg
= _("GPR odd is illegal");
2555 return insn
| ((value
& 0x1e) << 21);
2559 extract_rD_rS_even (uint64_t insn
,
2560 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2563 int64_t value
= ((insn
>> 21) & 0x1f);
2564 if ((value
& 0x1) != 0)
2571 insert_off_lsp (uint64_t insn
,
2573 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2574 const char **errmsg
)
2576 if (value
<= 0 || value
> 0x3)
2577 *errmsg
= _("invalid offset");
2578 return insn
| (value
& 0x3);
2582 extract_off_lsp (uint64_t insn
,
2583 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2586 int64_t value
= (insn
& 0x3);
2594 insert_off_spe2 (uint64_t insn
,
2596 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2597 const char **errmsg
)
2599 if (value
<= 0 || value
> 0x7)
2600 *errmsg
= _("invalid offset");
2601 return insn
| (value
& 0x7);
2605 extract_off_spe2 (uint64_t insn
,
2606 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2609 int64_t value
= (insn
& 0x7);
2617 insert_Ddd (uint64_t insn
,
2619 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2620 const char **errmsg
)
2622 if (value
< 0 || value
> 0x7)
2623 *errmsg
= _("invalid Ddd value");
2624 return insn
| ((value
& 0x3) << 11) | ((value
& 0x4) >> 2);
2628 extract_Ddd (uint64_t insn
,
2629 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2630 int *invalid ATTRIBUTE_UNUSED
)
2632 return ((insn
>> 11) & 0x3) | ((insn
<< 2) & 0x4);
2636 insert_sxl (uint64_t insn
,
2638 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2639 const char **errmsg ATTRIBUTE_UNUSED
)
2641 return insn
| ((value
& 0x1) << 11);
2645 extract_sxl (uint64_t insn
,
2646 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2649 /* Missing optional operands have a value of one. */
2652 return (insn
>> 11) & 0x1;
2655 /* The list of embedded processors that use the embedded operand ordering
2656 for the 3 operand dcbt and dcbtst instructions. */
2657 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
2660 /* ISA 2.03 and later specify extended mnemonics dcbtct, dcbtds, and
2661 dcbtstct, dcbtstds with a note saying these should be used in new
2662 programs rather than the base mnemonics "so that it can be coded
2663 with TH as the last operand for all categories". For that reason
2664 the extended mnemonics are enabled in the assembler for the
2665 embedded processors, but not for the disassembler so as to display
2666 the embedded dcbt or dcbtst expected form with TH first for
2667 embedded programmers. */
2670 insert_thct (uint64_t insn
,
2672 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2673 const char **errmsg
)
2675 if ((uint64_t) value
> 7)
2676 *errmsg
= _("invalid TH value");
2677 return insn
| ((value
& 7) << 21);
2681 extract_thct (uint64_t insn
,
2685 /* Missing optional operands have a value of 0. */
2689 int64_t value
= (insn
>> 21) & 0x1f;
2690 if (value
> 7 || (dialect
& DCBT_EO
) != 0)
2697 insert_thds (uint64_t insn
,
2699 ppc_cpu_t dialect ATTRIBUTE_UNUSED
,
2700 const char **errmsg
)
2702 if (value
< 8 || value
> 15)
2703 *errmsg
= _("invalid TH value");
2704 return insn
| ((value
& 0x1f) << 21);
2708 extract_thds (uint64_t insn
,
2712 /* Missing optional operands have a value of 8. */
2716 int64_t value
= (insn
>> 21) & 0x1f;
2717 if (value
< 8 || value
> 15 || (dialect
& DCBT_EO
) != 0)
2723 /* The operands table.
2725 The fields are bitm, shift, insert, extract, flags.
2727 We used to put parens around the various additions, like the one
2728 for BA just below. However, that caused trouble with feeble
2729 compilers with a limit on depth of a parenthesized expression, like
2730 (reportedly) the compiler in Microsoft Developer Studio 5. So we
2731 omit the parens, since the macros are never used in a context where
2732 the addition will be ambiguous. */
2734 const struct powerpc_operand powerpc_operands
[] =
2736 /* The zero index is used to indicate the end of the list of
2739 { 0, 0, NULL
, NULL
, 0 },
2741 /* The BA field in an XL form instruction. */
2742 #define BA UNUSED + 1
2743 /* The BI field in a B form or XL form instruction. */
2745 #define BI_MASK (0x1f << 16)
2746 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2748 /* The BT, BA and BB fields in a XL form instruction when they must all
2751 { 0x1f, 21, insert_btab
, extract_btab
, PPC_OPERAND_CR_BIT
},
2753 /* The BB field in an XL form instruction. */
2755 #define BB_MASK (0x1f << 11)
2756 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2758 /* The BA and BB fields in a XL form instruction when they must be
2761 { 0x1f, 16, insert_bab
, extract_bab
, PPC_OPERAND_CR_BIT
},
2763 /* The VRA and VRB fields in a VX form instruction when they must be the same.
2764 This is used for extended mnemonics like vmr. */
2766 { 0x1f, 16, insert_bab
, extract_bab
, PPC_OPERAND_VR
},
2768 /* The RA and RB fields in a VX form instruction when they must be the same.
2769 This is used for extended mnemonics like evmr. */
2771 { 0x1f, 16, insert_bab
, extract_bab
, PPC_OPERAND_GPR
},
2774 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2776 /* The BD field in a B form instruction. The lower two bits are
2779 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2781 /* The BD field in a B form instruction when absolute addressing is
2784 { 0xfffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
2786 /* The BD field in a B form instruction when the - modifier is used.
2787 This sets the y bit of the BO field appropriately. */
2789 { 0xfffc, 0, insert_bdm
, extract_bdm
,
2790 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2792 /* The BD field in a B form instruction when the - modifier is used
2793 and absolute address is used. */
2794 #define BDMA BDM + 1
2795 { 0xfffc, 0, insert_bdm
, extract_bdm
,
2796 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
2798 /* The BD field in a B form instruction when the + modifier is used.
2799 This sets the y bit of the BO field appropriately. */
2800 #define BDP BDMA + 1
2801 { 0xfffc, 0, insert_bdp
, extract_bdp
,
2802 PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2804 /* The BD field in a B form instruction when the + modifier is used
2805 and absolute addressing is used. */
2806 #define BDPA BDP + 1
2807 { 0xfffc, 0, insert_bdp
, extract_bdp
,
2808 PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
2810 /* The BF field in an X or XL form instruction. */
2812 /* The CRFD field in an X form instruction. */
2814 /* The CRD field in an XL form instruction. */
2816 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
},
2818 /* The BF field in an X or XL form instruction. */
2820 { 0x7, 23, NULL
, NULL
, 0 },
2822 /* The ACC field in a VSX ACC 8LS:D-form instruction. */
2824 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_ACC
},
2826 /* An optional BF field. This is used for comparison instructions,
2827 in which an omitted BF field is taken as zero. */
2829 { 0x7, 23, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
2831 /* The BFA field in an X or XL form instruction. */
2833 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
},
2835 /* The BO field in a B form instruction. Certain values are
2838 #define BO_MASK (0x1f << 21)
2839 { 0x1f, 21, insert_bo
, extract_bo
, 0 },
2841 /* The BO field in a B form instruction when the - modifier is used. */
2843 { 0x1f, 21, insert_bom
, extract_bom
, 0 },
2845 /* The BO field in a B form instruction when the + modifier is used. */
2847 { 0x1f, 21, insert_bop
, extract_bop
, 0 },
2849 /* The RM field in an X form instruction. */
2852 { 0x3, 11, NULL
, NULL
, 0 },
2855 { 0x3, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2857 /* The BT field in an X or XL form instruction. */
2859 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2861 /* The BT field in a mtfsb0 or mtfsb1 instruction. */
2863 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_CR_BIT
| PPC_OPERAND_CR_REG
},
2865 /* The BI16 field in a BD8 form instruction. */
2866 #define BI16 BTF + 1
2867 { 0x3, 8, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2869 /* The BI32 field in a BD15 form instruction. */
2870 #define BI32 BI16 + 1
2871 { 0xf, 16, NULL
, NULL
, PPC_OPERAND_CR_BIT
},
2873 /* The BO32 field in a BD15 form instruction. */
2874 #define BO32 BI32 + 1
2875 { 0x3, 20, NULL
, NULL
, 0 },
2877 /* The B8 field in a BD8 form instruction. */
2879 { 0x1fe, -1, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2881 /* The B15 field in a BD15 form instruction. The lowest bit is
2884 { 0xfffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2886 /* The B24 field in a BD24 form instruction. The lowest bit is
2889 { 0x1fffffe, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
2891 /* The condition register number portion of the BI field in a B form
2892 or XL form instruction. This is used for the extended
2893 conditional branch mnemonics, which set the lower two bits of the
2894 BI field. This field is optional. */
2896 { 0x7, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
2898 /* The CRB field in an X form instruction. */
2900 /* The MB field in an M form instruction. */
2902 #define MB_MASK (0x1f << 6)
2903 { 0x1f, 6, NULL
, NULL
, 0 },
2905 /* The CRD32 field in an XL form instruction. */
2906 #define CRD32 CRB + 1
2907 { 0x3, 21, NULL
, NULL
, PPC_OPERAND_CR_REG
},
2909 /* The CRFS field in an X form instruction. */
2910 #define CRFS CRD32 + 1
2911 { 0x7, 0, NULL
, NULL
, PPC_OPERAND_CR_REG
},
2913 #define CRS CRFS + 1
2914 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_CR_REG
| PPC_OPERAND_OPTIONAL
},
2916 /* The CT field in an X form instruction. */
2918 /* The MO field in an mbar instruction. */
2920 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
2922 /* The TH field in dcbtct. */
2924 { 0x1f, 21, insert_thct
, extract_thct
, PPC_OPERAND_OPTIONAL
},
2926 /* The TH field in dcbtds. */
2927 #define THDS THCT + 1
2928 { 0x1f, 21, insert_thds
, extract_thds
, PPC_OPERAND_OPTIONAL
},
2930 /* The D field in a D form instruction. This is a displacement off
2931 a register, and implies that the next operand is a register in
2934 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
2936 /* The D8 field in a D form instruction. This is a displacement off
2937 a register, and implies that the next operand is a register in
2940 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
2942 /* The DCMX field in an X form instruction. */
2944 { 0x7f, 16, NULL
, NULL
, 0 },
2946 /* The split DCMX field in an X form instruction. */
2947 #define DCMXS DCMX + 1
2948 { 0x7f, PPC_OPSHIFT_INV
, insert_dcmxs
, extract_dcmxs
, 0 },
2950 /* The DQ field in a DQ form instruction. This is like D, but the
2951 lower four bits are forced to zero. */
2952 #define DQ DCMXS + 1
2953 { 0xfff0, 0, NULL
, NULL
,
2954 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DQ
},
2956 /* The DS field in a DS form instruction. This is like D, but the
2957 lower two bits are forced to zero. */
2959 { 0xfffc, 0, NULL
, NULL
,
2960 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
| PPC_OPERAND_DS
},
2962 /* The D field in an 8-byte D form prefix instruction. This is a displacement
2963 off a register, and implies that the next operand is a register in
2966 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV
, insert_d34
, extract_d34
,
2967 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
2969 /* The SI field in an 8-byte D form prefix instruction. */
2970 #define SI34 D34 + 1
2971 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV
, insert_d34
, extract_d34
, PPC_OPERAND_SIGNED
},
2973 /* The NSI field in an 8-byte D form prefix instruction. This is the
2974 same as the SI34 field, only negated. */
2975 #define NSI34 SI34 + 1
2976 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV
, insert_nsi34
, extract_nsi34
,
2977 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
2979 /* The IMM32 field in a vector splat immediate prefix instruction. */
2980 #define IMM32 NSI34 + 1
2981 { 0xffffffff, PPC_OPSHIFT_INV
, insert_imm32
, extract_imm32
, 0},
2983 /* The UIM field in a vector permute extended prefix instruction. */
2984 #define UIM3 IMM32 + 1
2985 { 0x7, 32, NULL
, NULL
, 0},
2987 /* The UIM field in a vector eval prefix instruction. */
2988 #define UIM8 UIM3 + 1
2989 { 0xff, 32, NULL
, NULL
, 0},
2991 /* The IX field in xxsplti32dx. */
2993 { 0x1, 17, NULL
, NULL
, 0 },
2995 /* The PMSK field in GER rank 8 prefix instructions. */
2996 #define PMSK8 IX + 1
2997 { 0xff, 40, NULL
, NULL
, 0 },
2999 /* The PMSK field in GER rank 4 prefix instructions. */
3000 #define PMSK4 PMSK8 + 1
3001 { 0xf, 44, NULL
, NULL
, 0 },
3003 /* The PMSK field in GER rank 2 prefix instructions. */
3004 #define PMSK2 PMSK4 + 1
3005 { 0x3, 46, NULL
, NULL
, 0 },
3007 /* The XMSK field in GER prefix instructions. */
3008 #define XMSK PMSK2 + 1
3009 { 0xf, 36, NULL
, NULL
, 0 },
3011 /* The YMSK field in GER prefix instructions. */
3012 #define YMSK XMSK + 1
3013 { 0xf, 32, NULL
, NULL
, 0 },
3015 /* The YMSK field in 64-bit GER prefix instructions. */
3016 #define YMSK2 YMSK + 1
3017 { 0x3, 34, NULL
, NULL
, 0 },
3019 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
3020 unsigned imediate */
3021 #define DUIS YMSK2 + 1
3023 { 0x3ff, 11, NULL
, NULL
, 0 },
3025 /* The split DW field in a X form instruction. */
3027 { -1, PPC_OPSHIFT_INV
, insert_dw
, extract_dw
,
3028 PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
3030 /* The split D field in a DX form instruction. */
3032 { 0xffff, PPC_OPSHIFT_INV
, insert_dxd
, extract_dxd
,
3033 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
3035 /* The split ND field in a DX form instruction.
3036 This is the same as the DX field, only negated. */
3037 #define NDXD DXD + 1
3038 { 0xffff, PPC_OPSHIFT_INV
, insert_dxdn
, extract_dxdn
,
3039 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
3041 /* The E field in a wrteei instruction. */
3042 /* And the W bit in the pair singles instructions. */
3043 /* And the ST field in a VX form instruction. */
3047 { 0x1, 15, NULL
, NULL
, 0 },
3049 /* The FL1 field in a POWER SC form instruction. */
3051 /* The U field in an X form instruction. */
3053 { 0xf, 12, NULL
, NULL
, 0 },
3055 /* The FL2 field in a POWER SC form instruction. */
3057 { 0x7, 2, NULL
, NULL
, 0 },
3059 /* The FLM field in an XFL form instruction. */
3061 { 0xff, 17, NULL
, NULL
, 0 },
3063 /* The FRA field in an X or A form instruction. */
3065 #define FRA_MASK (0x1f << 16)
3066 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
3068 /* The FRAp field of DFP instructions. */
3069 #define FRAp FRA + 1
3070 { 0x1e, 16, NULL
, NULL
, PPC_OPERAND_FPR
},
3072 /* The FRB field in an X or A form instruction. */
3073 #define FRB FRAp + 1
3074 #define FRB_MASK (0x1f << 11)
3075 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
3077 /* The FRBp field of DFP instructions. */
3078 #define FRBp FRB + 1
3079 { 0x1e, 11, NULL
, NULL
, PPC_OPERAND_FPR
},
3081 /* The FRC field in an A form instruction. */
3082 #define FRC FRBp + 1
3083 #define FRC_MASK (0x1f << 6)
3084 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_FPR
},
3086 /* The FRS field in an X form instruction or the FRT field in a D, X
3087 or A form instruction. */
3090 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
3092 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
3094 #define FRSp FRS + 1
3096 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_FPR
},
3098 /* The FXM field in an XFX instruction. */
3099 #define FXM FRSp + 1
3100 { 0xff, 12, insert_fxm
, extract_fxm
, 0 },
3102 /* Power4 version for mfcr. */
3103 #define FXM4 FXM + 1
3104 { 0xff, 12, insert_fxm
, extract_fxm
, PPC_OPERAND_OPTIONAL
},
3106 /* The IMM20 field in an LI instruction. */
3107 #define IMM20 FXM4 + 1
3108 { 0xfffff, PPC_OPSHIFT_INV
, insert_li20
, extract_li20
, PPC_OPERAND_SIGNED
},
3110 /* The L field in a D or X form instruction. */
3112 { 0x1, 21, NULL
, NULL
, 0 },
3114 /* The optional L field in tlbie and tlbiel instructions. */
3116 /* The R field in a HTM X form instruction. */
3118 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
3120 /* The optional L field in the paste. instruction. This is similar to LOPT
3121 above, but with a default value of 1. */
3122 #define L1OPT LOPT + 1
3123 { 0x1, 21, insert_l1opt
, extract_l1opt
, PPC_OPERAND_OPTIONAL
},
3125 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
3126 #define L32OPT L1OPT + 1
3127 { 0x1, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_OPTIONAL32
},
3129 /* The 2-bit L or WC field in an X (sync, dcbf or wait) form instruction. */
3130 #define L2OPT L32OPT + 1
3133 { 0x3, 21, insert_ls
, extract_ls
, PPC_OPERAND_OPTIONAL
},
3135 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
3136 #define SVC_LEV L2OPT + 1
3137 { 0x7f, 5, NULL
, NULL
, 0 },
3139 /* The LEV field in an SC form instruction. */
3140 #define LEV SVC_LEV + 1
3141 { 0x7f, 5, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
3143 /* The LI field in an I form instruction. The lower two bits are
3146 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_RELATIVE
| PPC_OPERAND_SIGNED
},
3148 /* The LI field in an I form instruction when used as an absolute
3151 { 0x3fffffc, 0, NULL
, NULL
, PPC_OPERAND_ABSOLUTE
| PPC_OPERAND_SIGNED
},
3153 /* The 3-bit L field in a sync or dcbf instruction. */
3156 { 0x7, 21, insert_ls
, extract_ls
, PPC_OPERAND_OPTIONAL
},
3158 /* The ME field in an M form instruction. */
3160 #define ME_MASK (0x1f << 1)
3161 { 0x1f, 1, NULL
, NULL
, 0 },
3164 { 0x1f, 1, insert_crwn
, extract_crwn
, 0 },
3166 #define ELWn CRWn + 1
3167 { 0x1f, 1, insert_elwn
, extract_elwn
, PPC_OPERAND_PLUS1
},
3169 #define ERWn ELWn + 1
3170 { 0x1f, 6, insert_erwn
, extract_erwn
, 0 },
3172 #define ERWb ERWn + 1
3173 { 0x1f, 11, insert_erwb
, extract_erwb
, 0 },
3175 #define CSLWb ERWb + 1
3176 { 0x1f, 6, NULL
, extract_cslwb
, 0 },
3178 #define CSLWn CSLWb + 1
3179 { 0x1f, 11, insert_cslwn
, NULL
, 0 },
3181 #define ILWn CSLWn + 1
3182 { 0x1f, 1, NULL
, extract_ilwn
, PPC_OPERAND_PLUS1
},
3184 #define ILWb ILWn + 1
3185 { 0x1f, 6, insert_ilwb
, NULL
, 0 },
3187 #define IRWn ILWb + 1
3188 { 0x1f, 1, NULL
, extract_irwn
, PPC_OPERAND_PLUS1
},
3190 #define IRWb IRWn + 1
3191 { 0x1f, 6, insert_irwb
, NULL
, 0 },
3193 /* The MB and ME fields in an M form instruction expressed a single
3194 operand which is a bitmask indicating which bits to select. This
3195 is a two operand form using PPC_OPERAND_NEXT. See the
3196 description in opcode/ppc.h for what this means. */
3197 #define MBE IRWb + 1
3198 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_OPTIONAL
| PPC_OPERAND_NEXT
},
3199 { -1, 0, insert_mbe
, extract_mbe
, 0 },
3201 /* The MB or ME field in an MD or MDS form instruction. The high
3202 bit is wrapped to the low end. */
3205 #define MB6_MASK (0x3f << 5)
3206 { 0x3f, 5, insert_mb6
, extract_mb6
, 0 },
3208 #define ELDn MB6 + 1
3209 { 0x3f, 5, insert_eldn
, extract_eldn
, PPC_OPERAND_PLUS1
},
3211 #define ERDn ELDn + 1
3212 { 0x3f, 5, insert_erdn
, extract_erdn
, 0 },
3214 #define CRDn ERDn + 1
3215 { 0x3f, 5, insert_crdn
, extract_crdn
, 0 },
3217 /* The NB field in an X form instruction. The value 32 is stored as
3220 { 0x1f, 11, NULL
, extract_nb
, PPC_OPERAND_PLUS1
},
3222 /* The NBI field in an lswi instruction, which has special value
3223 restrictions. The value 32 is stored as 0. */
3225 { 0x1f, 11, insert_nbi
, extract_nb
, PPC_OPERAND_PLUS1
},
3227 /* The NSI field in a D form instruction. This is the same as the
3228 SI field, only negated. */
3230 { 0xffff, 0, insert_nsi
, extract_nsi
,
3231 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
3233 /* The NSI field in a D form instruction when we accept a wide range
3234 of positive values. */
3235 #define NSISIGNOPT NSI + 1
3236 { 0xffff, 0, insert_nsi
, extract_nsi
,
3237 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
3239 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
3240 #define RA NSISIGNOPT + 1
3241 #define RA_MASK (0x1f << 16)
3242 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
},
3244 /* As above, but 0 in the RA field means zero, not r0. */
3246 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
},
3248 /* Similar to above, but optional. */
3249 #define PRA0 RA0 + 1
3250 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR_0
| PPC_OPERAND_OPTIONAL
},
3252 /* The RA field in the DQ form lq or an lswx instruction, which have
3253 special value restrictions. */
3254 #define RAQ PRA0 + 1
3256 { 0x1f, 16, insert_raq
, extract_raq
, PPC_OPERAND_GPR_0
},
3258 /* Similar to above, but optional. */
3259 #define PRAQ RAQ + 1
3260 { 0x1f, 16, insert_raq
, extract_raq
,
3261 PPC_OPERAND_GPR_0
| PPC_OPERAND_OPTIONAL
},
3263 /* The R field in an 8-byte D, DS, DQ or X form prefix instruction. */
3264 #define PCREL PRAQ + 1
3265 #define PCREL_MASK (1ULL << 52)
3266 { 0x1, 52, insert_pcrel
, extract_pcrel
, PPC_OPERAND_OPTIONAL
},
3268 #define PCREL0 PCREL + 1
3269 { 0x1, 52, insert_pcrel
, extract_pcrel0
, PPC_OPERAND_OPTIONAL
},
3271 /* The RA field in a D or X form instruction which is an updating
3272 load, which means that the RA field may not be zero and may not
3273 equal the RT field. */
3274 #define RAL PCREL0 + 1
3275 { 0x1f, 16, insert_ral
, extract_ral
, PPC_OPERAND_GPR_0
},
3277 /* The RA field in an lmw instruction, which has special value
3280 { 0x1f, 16, insert_ram
, extract_ram
, PPC_OPERAND_GPR_0
},
3282 /* The RA field in a D or X form instruction which is an updating
3283 store or an updating floating point load, which means that the RA
3284 field may not be zero. */
3286 { 0x1f, 16, insert_ras
, extract_ras
, PPC_OPERAND_GPR_0
},
3288 /* The RA field of the tlbwe, dccci and iccci instructions,
3289 which are optional. */
3290 #define RAOPT RAS + 1
3291 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
3293 /* The RB field in an X, XO, M, or MDS form instruction. */
3294 #define RB RAOPT + 1
3295 #define RB_MASK (0x1f << 11)
3296 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
},
3298 /* The RS and RB fields in an X form instruction when they must be the same.
3299 This is used for extended mnemonics like mr. */
3301 { 0x1f, 11, insert_rsb
, extract_rsb
, PPC_OPERAND_GPR
},
3303 /* The RB field in an lswx instruction, which has special value
3306 { 0x1f, 11, insert_rbx
, extract_rbx
, PPC_OPERAND_GPR
},
3308 /* The RB field of the dccci and iccci instructions, which are optional. */
3309 #define RBOPT RBX + 1
3310 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
3312 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
3313 #define RC RBOPT + 1
3314 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_GPR
},
3316 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
3317 instruction or the RT field in a D, DS, X, XFX or XO form
3321 #define RT_MASK (0x1f << 21)
3323 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
3325 #define RD_EVEN RS + 1
3326 #define RS_EVEN RD_EVEN
3327 { 0x1f, 21, insert_rD_rS_even
, extract_rD_rS_even
, PPC_OPERAND_GPR
},
3329 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
3330 which have special value restrictions. */
3331 #define RSQ RS_EVEN + 1
3333 #define Q_MASK (1 << 21)
3334 { 0x1e, 21, NULL
, NULL
, PPC_OPERAND_GPR
},
3336 /* The RS field of the tlbwe instruction, which is optional. */
3339 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_GPR
| PPC_OPERAND_OPTIONAL
},
3341 /* The RX field of the SE_RR form instruction. */
3343 { 0x1f, PPC_OPSHIFT_INV
, insert_rx
, extract_rx
, PPC_OPERAND_GPR
},
3345 /* The ARX field of the SE_RR form instruction. */
3347 { 0x1f, PPC_OPSHIFT_INV
, insert_arx
, extract_arx
, PPC_OPERAND_GPR
},
3349 /* The RY field of the SE_RR form instruction. */
3352 { 0x1f, PPC_OPSHIFT_INV
, insert_ry
, extract_ry
, PPC_OPERAND_GPR
},
3354 /* The ARY field of the SE_RR form instruction. */
3356 { 0x1f, PPC_OPSHIFT_INV
, insert_ary
, extract_ary
, PPC_OPERAND_GPR
},
3358 /* The SCLSCI8 field in a D form instruction. */
3359 #define SCLSCI8 ARY + 1
3360 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8
, extract_sci8
, 0 },
3362 /* The SCLSCI8N field in a D form instruction. This is the same as the
3363 SCLSCI8 field, only negated. */
3364 #define SCLSCI8N SCLSCI8 + 1
3365 { 0xffffffff, PPC_OPSHIFT_INV
, insert_sci8n
, extract_sci8n
,
3366 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
},
3368 /* The SD field of the SD4 form instruction. */
3369 #define SE_SD SCLSCI8N + 1
3370 { 0xf, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
3372 /* The SD field of the SD4 form instruction, for halfword. */
3373 #define SE_SDH SE_SD + 1
3374 { 0x1e, 7, NULL
, NULL
, PPC_OPERAND_PARENS
},
3376 /* The SD field of the SD4 form instruction, for word. */
3377 #define SE_SDW SE_SDH + 1
3378 { 0x3c, 6, NULL
, NULL
, PPC_OPERAND_PARENS
},
3380 /* The SH field in an X or M form instruction. */
3381 #define SH SE_SDW + 1
3382 #define SH_MASK (0x1f << 11)
3383 /* The other UIMM field in a EVX form instruction. */
3385 /* The FC field in an atomic X form instruction. */
3388 { 0x1f, 11, NULL
, NULL
, 0 },
3391 { 0x1f, 11, insert_rrwn
, extract_rrwn
, 0 },
3393 #define SLWn RRWn + 1
3394 { 0x1f, 11, insert_slwn
, extract_slwn
, 0 },
3396 #define SRWn SLWn + 1
3397 { 0x1f, 11, insert_srwn
, extract_srwn
, 0 },
3399 #define EVUIMM_LT8 SRWn + 1
3400 { 0x1f, 11, insert_evuimm_lt8
, extract_evuimm_lt8
, 0 },
3402 #define EVUIMM_LT16 EVUIMM_LT8 + 1
3403 { 0x1f, 11, insert_evuimm_lt16
, extract_evuimm_lt16
, 0 },
3405 /* The SI field in a HTM X form instruction. */
3406 #define HTM_SI EVUIMM_LT16 + 1
3407 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_SIGNED
},
3409 /* The SH field in an MD form instruction. This is split. */
3410 #define SH6 HTM_SI + 1
3411 #define SH6_MASK ((0x1f << 11) | (1 << 1))
3412 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_sh6
, 0 },
3414 #define RRDn SH6 + 1
3415 { 0x3f, PPC_OPSHIFT_INV
, insert_rrdn
, extract_rrdn
, 0 },
3417 #define SLDn RRDn + 1
3418 { 0x3f, PPC_OPSHIFT_INV
, insert_sldn
, extract_sldn
, 0 },
3420 #define SRDn SLDn + 1
3421 { 0x3f, PPC_OPSHIFT_INV
, insert_srdn
, extract_srdn
, 0 },
3423 #define ERDb SRDn + 1
3424 { 0x3f, PPC_OPSHIFT_INV
, insert_erdb
, extract_erdb
, 0 },
3426 #define CSLDn ERDb + 1
3427 { 0x3f, PPC_OPSHIFT_SH6
, insert_csldn
, extract_sh6
, 0 },
3429 #define CSLDb CSLDn + 1
3430 { 0x3f, 5, insert_mb6
, extract_csldb
, 0 },
3432 #define IRDn CSLDb + 1
3433 { 0x3f, PPC_OPSHIFT_INV
, insert_sh6
, extract_irdn
, PPC_OPERAND_PLUS1
},
3435 #define IRDb IRDn + 1
3436 { 0x3f, 5, insert_irdb
, extract_mb6
, 0 },
3438 /* The SH field of some variants of the tlbre and tlbwe
3439 instructions, and the ELEV field of the e_sc instruction. */
3440 #define SHO IRDb + 1
3442 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
3444 /* The SI field in a D form instruction. */
3446 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
3448 /* The SI field in a D form instruction when we accept a wide range
3449 of positive values. */
3450 #define SISIGNOPT SI + 1
3451 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
3453 /* The SI8 field in a D form instruction. */
3454 #define SI8 SISIGNOPT + 1
3455 { 0xff, 0, NULL
, NULL
, PPC_OPERAND_SIGNED
},
3457 /* The SPR field in an XFX form instruction. This is flipped--the
3458 lower 5 bits are stored in the upper 5 and vice- versa. */
3462 #define SPR_MASK (0x3ff << 11)
3463 { 0x3ff, 11, insert_spr
, extract_spr
, PPC_OPERAND_SPR
},
3465 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
3466 #define SPRBAT SPR + 1
3467 #define SPRBAT_MASK (0xc1 << 11)
3468 { 0x7, PPC_OPSHIFT_INV
, insert_sprbat
, extract_sprbat
, PPC_OPERAND_SPR
},
3470 /* The GQR index number in an XFX form m[ft]gqr instruction. */
3471 #define SPRGQR SPRBAT + 1
3472 #define SPRGQR_MASK (0x7 << 16)
3473 { 0x7, 16, NULL
, NULL
, PPC_OPERAND_GQR
},
3475 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
3476 #define SPRG SPRGQR + 1
3477 { 0x1f, 16, insert_sprg
, extract_sprg
, PPC_OPERAND_SPR
},
3479 /* The SR field in an X form instruction. */
3481 /* The 4-bit UIMM field in a VX form instruction. */
3483 { 0xf, 16, NULL
, NULL
, 0 },
3485 /* The STRM field in an X AltiVec form instruction. */
3487 /* The T field in a tlbilx form instruction. */
3489 /* The L field in wclr instructions. */
3491 { 0x3, 21, NULL
, NULL
, 0 },
3493 /* The ESYNC field in an X (sync) form instruction. */
3494 #define ESYNC STRM + 1
3495 { 0xf, 16, insert_esync
, extract_esync
, PPC_OPERAND_OPTIONAL
},
3497 /* The SV field in a POWER SC form instruction. */
3498 #define SV ESYNC + 1
3499 { 0x3fff, 2, NULL
, NULL
, 0 },
3501 /* The TBR field in an XFX form instruction. This is like the SPR
3502 field, but it is optional. */
3504 { 0x3ff, 11, insert_tbr
, extract_tbr
,
3505 PPC_OPERAND_SPR
| PPC_OPERAND_OPTIONAL
},
3507 /* The TO field in a D or X form instruction. */
3510 #define TO_MASK (0x1f << 21)
3511 { 0x1f, 21, NULL
, NULL
, 0 },
3513 /* The UI field in a D form instruction. */
3515 { 0xffff, 0, NULL
, NULL
, 0 },
3517 #define UISIGNOPT UI + 1
3518 { 0xffff, 0, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
3520 /* The IMM field in an SE_IM5 instruction. */
3521 #define UI5 UISIGNOPT + 1
3522 { 0x1f, 4, NULL
, NULL
, 0 },
3524 /* The OIMM field in an SE_OIM5 instruction. */
3525 #define OIMM5 UI5 + 1
3526 { 0x1f, 4, insert_oimm
, extract_oimm
, PPC_OPERAND_PLUS1
},
3528 /* The UI7 field in an SE_LI instruction. */
3529 #define UI7 OIMM5 + 1
3530 { 0x7f, 4, NULL
, NULL
, 0 },
3532 /* The VA field in a VA, VX or VXR form instruction. */
3534 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_VR
},
3536 /* The VB field in a VA, VX or VXR form instruction. */
3538 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_VR
},
3540 /* The VC field in a VA form instruction. */
3542 { 0x1f, 6, NULL
, NULL
, PPC_OPERAND_VR
},
3544 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
3547 { 0x1f, 21, NULL
, NULL
, PPC_OPERAND_VR
},
3549 /* The SIMM field in a VX form instruction, and TE in Z form. */
3552 { 0x1f, 16, NULL
, NULL
, PPC_OPERAND_SIGNED
},
3554 /* The UIMM field in a VX form instruction. */
3555 #define UIMM SIMM + 1
3557 { 0x1f, 16, NULL
, NULL
, 0 },
3559 /* The 3-bit UIMM field in a VX form instruction. */
3560 #define UIMM3 UIMM + 1
3561 { 0x7, 16, NULL
, NULL
, 0 },
3563 /* The 6-bit UIM field in a X form instruction. */
3564 #define UIM6 UIMM3 + 1
3565 { 0x3f, 16, NULL
, NULL
, 0 },
3567 /* The SIX field in a VX form instruction. */
3568 #define SIX UIM6 + 1
3570 { 0xf, 11, NULL
, NULL
, 0 },
3572 /* The PS field in a VX form instruction. */
3574 { 0x1, 9, NULL
, NULL
, 0 },
3576 /* The SH field in a vector shift double by bit immediate instruction. */
3578 { 0x7, 6, NULL
, NULL
, 0 },
3580 /* The SHB field in a VA form instruction. */
3582 { 0xf, 6, NULL
, NULL
, 0 },
3584 /* The other UIMM field in a half word EVX form instruction. */
3585 #define EVUIMM_1 SHB + 1
3586 { 0x1f, 11, NULL
, NULL
, PPC_OPERAND_PARENS
},
3588 #define EVUIMM_1_EX0 EVUIMM_1 + 1
3589 { 0x1f, 11, insert_evuimm1_ex0
, extract_evuimm1_ex0
, PPC_OPERAND_PARENS
},
3591 #define EVUIMM_2 EVUIMM_1_EX0 + 1
3592 { 0x3e, 10, NULL
, NULL
, PPC_OPERAND_PARENS
},
3594 #define EVUIMM_2_EX0 EVUIMM_2 + 1
3595 { 0x3e, 10, insert_evuimm2_ex0
, extract_evuimm2_ex0
, PPC_OPERAND_PARENS
},
3597 /* The other UIMM field in a word EVX form instruction. */
3598 #define EVUIMM_4 EVUIMM_2_EX0 + 1
3599 { 0x7c, 9, NULL
, NULL
, PPC_OPERAND_PARENS
},
3601 #define EVUIMM_4_EX0 EVUIMM_4 + 1
3602 { 0x7c, 9, insert_evuimm4_ex0
, extract_evuimm4_ex0
, PPC_OPERAND_PARENS
},
3604 /* The other UIMM field in a double EVX form instruction. */
3605 #define EVUIMM_8 EVUIMM_4_EX0 + 1
3606 { 0xf8, 8, NULL
, NULL
, PPC_OPERAND_PARENS
},
3608 #define EVUIMM_8_EX0 EVUIMM_8 + 1
3609 { 0xf8, 8, insert_evuimm8_ex0
, extract_evuimm8_ex0
, PPC_OPERAND_PARENS
},
3611 /* The WS or DRM field in an X form instruction. */
3612 #define WS EVUIMM_8_EX0 + 1
3614 /* The NNN field in a VX form instruction for SPE2 */
3616 { 0x7, 11, NULL
, NULL
, 0 },
3618 /* PowerPC paired singles extensions. */
3619 /* W bit in the pair singles instructions for x type instructions. */
3621 /* The BO16 field in a BD8 form instruction. */
3623 { 0x1, 10, 0, 0, 0 },
3625 /* IDX bits for quantization in the pair singles instructions. */
3626 #define PSQ PSWM + 1
3627 { 0x7, 12, 0, 0, PPC_OPERAND_GQR
},
3629 /* IDX bits for quantization in the pair singles x-type instructions. */
3630 #define PSQM PSQ + 1
3631 { 0x7, 7, 0, 0, PPC_OPERAND_GQR
},
3633 /* Smaller D field for quantization in the pair singles instructions. */
3634 #define PSD PSQM + 1
3635 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS
| PPC_OPERAND_SIGNED
},
3637 /* The L field in an mtmsrd or A form instruction or R or W in an
3642 { 0x1, 16, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
3644 /* The RMC or CY field in a Z23 form instruction. */
3647 { 0x3, 9, NULL
, NULL
, 0 },
3651 { 0x1, 16, NULL
, NULL
, 0 },
3654 { 0x3, 18, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
3657 { 0x1, 17, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
3660 { 0x3, 19, NULL
, NULL
, 0 },
3663 { 0x1, 20, NULL
, NULL
, 0 },
3665 /* The S field in a XL form instruction. */
3667 { 0x1, 11, insert_sxl
, extract_sxl
, PPC_OPERAND_OPTIONAL
},
3669 /* SH field starting at bit position 16. */
3670 #define SH16 SXL + 1
3671 /* The DCM and DGM fields in a Z form instruction. */
3674 { 0x3f, 10, NULL
, NULL
, 0 },
3676 /* The EH field in larx instruction. */
3678 { 0x1, 0, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
3680 /* The L field in an mtfsf or XFL form instruction. */
3681 /* The A field in a HTM X form instruction. */
3682 #define XFL_L EH + 1
3684 { 0x1, 25, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
3686 /* Xilinx APU related masks and macros */
3687 #define FCRT XFL_L + 1
3688 #define FCRT_MASK (0x1f << 21)
3689 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR
},
3691 /* Xilinx FSL related masks and macros */
3692 #define FSL FCRT + 1
3693 #define FSL_MASK (0x1f << 11)
3694 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL
},
3696 /* Xilinx UDI related masks and macros */
3698 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI
},
3701 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI
},
3704 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI
},
3707 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI
},
3709 /* The VLESIMM field in a D form instruction. */
3710 #define VLESIMM URC + 1
3711 { 0xffff, PPC_OPSHIFT_INV
, insert_vlesi
, extract_vlesi
,
3712 PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
3714 /* The VLENSIMM field in a D form instruction. */
3715 #define VLENSIMM VLESIMM + 1
3716 { 0xffff, PPC_OPSHIFT_INV
, insert_vlensi
, extract_vlensi
,
3717 PPC_OPERAND_NEGATIVE
| PPC_OPERAND_SIGNED
| PPC_OPERAND_SIGNOPT
},
3719 /* The VLEUIMM field in a D form instruction. */
3720 #define VLEUIMM VLENSIMM + 1
3721 { 0xffff, PPC_OPSHIFT_INV
, insert_vleui
, extract_vleui
, 0 },
3723 /* The VLEUIMML field in a D form instruction. */
3724 #define VLEUIMML VLEUIMM + 1
3725 { 0xffff, PPC_OPSHIFT_INV
, insert_vleil
, extract_vleil
, 0 },
3727 /* The XT and XS fields in an XX1 or XX3 form instruction. This is
3729 #define XS6 VLEUIMML + 1
3731 { 0x3f, PPC_OPSHIFT_INV
, insert_xt6
, extract_xt6
, PPC_OPERAND_VSR
},
3733 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
3734 #define XSQ6 XT6 + 1
3736 { 0x3f, PPC_OPSHIFT_INV
, insert_xtq6
, extract_xtq6
, PPC_OPERAND_VSR
},
3738 /* The split XTp field in a vector paired instruction. */
3739 #define XTP XSQ6 + 1
3740 { 0x3e, PPC_OPSHIFT_INV
, insert_xtp
, extract_xtp
, PPC_OPERAND_VSR
},
3743 { 0x3f, PPC_OPSHIFT_INV
, insert_xts
, extract_xts
, PPC_OPERAND_VSR
},
3745 /* The XT field in a plxv instruction. Runs into the OP field. */
3746 #define XTOP XTS + 1
3747 { 0x3f, 21, NULL
, NULL
, PPC_OPERAND_VSR
},
3749 /* The XA field in an XX3 form instruction. This is split. */
3750 #define XA6 XTOP + 1
3751 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6
, extract_xa6
, PPC_OPERAND_VSR
},
3753 /* The XA field in an MMA XX3 form instruction. This is split and
3754 must not overlap with the ACC operand. */
3755 #define XA6a XA6 + 1
3756 { 0x3f, PPC_OPSHIFT_INV
, insert_xa6a
, extract_xa6a
, PPC_OPERAND_VSR
},
3758 /* The XAp field in an MMA XX3 form instruction. This is split.
3759 This is like XA6a, but must be even. */
3760 #define XA6ap XA6a + 1
3761 { 0x3e, PPC_OPSHIFT_INV
, insert_xa6a
, extract_xa6a
, PPC_OPERAND_VSR
},
3763 /* The XB field in an XX2 or XX3 form instruction. This is split. */
3764 #define XB6 XA6ap + 1
3765 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6
, extract_xb6
, PPC_OPERAND_VSR
},
3767 /* The XB field in an XX3 form instruction. This is split and
3768 must not overlap with the ACC operand. */
3769 #define XB6a XB6 + 1
3770 { 0x3f, PPC_OPSHIFT_INV
, insert_xb6a
, extract_xb6a
, PPC_OPERAND_VSR
},
3772 /* The XA and XB fields in an XX3 form instruction when they must be the same.
3773 This is used in extended mnemonics like xvmovdp. This is split. */
3774 #define XAB6 XB6a + 1
3775 { 0x3f, PPC_OPSHIFT_INV
, insert_xab6
, extract_xab6
, PPC_OPERAND_VSR
},
3777 /* The XC field in an XX4 form instruction. This is split. */
3778 #define XC6 XAB6 + 1
3779 { 0x3f, PPC_OPSHIFT_INV
, insert_xc6
, extract_xc6
, PPC_OPERAND_VSR
},
3781 /* The DM or SHW field in an XX3 form instruction. */
3784 { 0x3, 8, NULL
, NULL
, 0 },
3786 /* The DM field in an extended mnemonic XX3 form instruction. */
3788 { 0x3, 8, insert_dm
, extract_dm
, 0 },
3790 /* The UIM field in an XX2 form instruction. */
3791 #define UIM DMEX + 1
3792 /* The 2-bit UIMM field in a VX form instruction. */
3794 /* The 2-bit L field in a darn instruction. */
3796 { 0x3, 16, NULL
, NULL
, 0 },
3798 #define ERAT_T UIM + 1
3799 { 0x7, 21, NULL
, NULL
, 0 },
3801 #define IH ERAT_T + 1
3802 { 0x7, 21, NULL
, NULL
, PPC_OPERAND_OPTIONAL
},
3804 /* The 2-bit SC or PL field in an X form instruction. */
3807 { 0x3, 16, insert_pl
, extract_pl
, PPC_OPERAND_OPTIONAL
},
3809 /* The 8-bit IMM8 field in a XX1 form instruction. */
3810 #define IMM8 SC2 + 1
3811 { 0xff, 11, NULL
, NULL
, PPC_OPERAND_SIGNOPT
},
3813 #define VX_OFF IMM8 + 1
3814 { 0x3, 0, insert_off_lsp
, extract_off_lsp
, 0 },
3816 #define VX_OFF_SPE2 VX_OFF + 1
3817 { 0x7, 0, insert_off_spe2
, extract_off_spe2
, 0 },
3819 #define BBB VX_OFF_SPE2 + 1
3820 { 0x7, 13, NULL
, NULL
, 0 },
3823 #define VX_MASK_DDD (VX_MASK & ~0x1)
3824 { 0x7, PPC_OPSHIFT_INV
, insert_Ddd
, extract_Ddd
, 0 },
3827 { 0x3, 13, NULL
, NULL
, 0 },
3830 const unsigned int num_powerpc_operands
= (sizeof (powerpc_operands
)
3831 / sizeof (powerpc_operands
[0]));
3833 /* Macros used to form opcodes. */
3835 /* The main opcode. */
3836 #define OP(x) ((((uint64_t)(x)) & 0x3f) << 26)
3837 #define OP_MASK OP (0x3f)
3839 /* The prefix opcode. */
3840 #define PREFIX_OP (1ULL << 58)
3842 /* The 2-bit prefix form. */
3843 #define PREFIX_FORM(x) ((x & 3ULL) << 56)
3845 #define SUFFIX_MASK ((1ULL << 32) - 1)
3846 #define PREFIX_MASK (SUFFIX_MASK << 32)
3848 /* Prefix insn, eight byte load/store form 8LS. */
3849 #define P8LS (PREFIX_OP | PREFIX_FORM (0))
3851 /* Prefix insn, eight byte register to register form 8RR. */
3852 #define P8RR (PREFIX_OP | PREFIX_FORM (1))
3854 /* Prefix insn, modified load/store form MLS. */
3855 #define PMLS (PREFIX_OP | PREFIX_FORM (2))
3857 /* Prefix insn, modified register to register form MRR. */
3858 #define PMRR (PREFIX_OP | PREFIX_FORM (3))
3860 /* Prefix insn, modified masked immediate register to register form MMIRR. */
3861 #define PMMIRR (PREFIX_OP | PREFIX_FORM (3) | (9ULL << 52))
3863 /* An 8-byte D form prefix instruction. */
3864 #define P_D_MASK (((-1ULL << 50) & ~PCREL_MASK) | OP_MASK)
3866 /* The same as P_D_MASK, but with the RA and PCREL fields specified. */
3867 #define P_DRAPCREL_MASK (P_D_MASK | PCREL_MASK | RA_MASK)
3869 /* Mask for prefix X form instructions. */
3870 #define P_X_MASK (PREFIX_MASK | X_MASK)
3871 #define P_XX1_MASK (PREFIX_MASK | XX1_MASK)
3873 /* Mask for prefix vector permute insns. */
3874 #define P_XX4_MASK (PREFIX_MASK | XX4_MASK)
3875 #define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32))
3876 #define P_U8XX4_MASK (P_XX4_MASK & ~(0xffULL << 32))
3878 /* MMIRR:XX3-form 8-byte outer product instructions. */
3879 #define P_GER_MASK ((-1ULL << 40) | XX3_MASK | (3 << 21) | 1)
3880 #define P_GER2_MASK (P_GER_MASK & ~(3ULL << 46))
3881 #define P_GER4_MASK (P_GER_MASK & ~(15ULL << 44))
3882 #define P_GER8_MASK (P_GER_MASK & ~(255ULL << 40))
3883 #define P_GER64_MASK (P_GER_MASK | (3ULL << 32))
3885 /* Vector splat immediate op. */
3886 #define VSOP(op, xop) (OP (op) | (xop << 17))
3887 #define P_VS_MASK ((-1ULL << 48) | VSOP (0x3f, 0xf))
3888 #define P_VSI_MASK ((-1ULL << 48) | VSOP (0x3f, 0xe))
3890 /* The main opcode combined with a trap code in the TO field of a D
3891 form instruction. Used for extended mnemonics for the trap
3893 #define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21))
3894 #define OPTO_MASK (OP_MASK | TO_MASK)
3896 /* The main opcode combined with a comparison size bit in the L field
3897 of a D form or X form instruction. Used for extended mnemonics for
3898 the comparison instructions. */
3899 #define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21))
3900 #define OPL_MASK OPL (0x3f,1)
3902 /* The main opcode combined with an update code in D form instruction.
3903 Used for extended mnemonics for VLE memory instructions. */
3904 #define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8))
3905 #define OPVUP_MASK OPVUP (0x3f, 0xff)
3907 /* The main opcode combined with an update code and the RT fields
3908 specified in D form instruction. Used for VLE volatile context
3909 save/restore instructions. */
3910 #define OPVUPRT(x,vup,rt) \
3912 | ((((uint64_t)(rt)) & 0x1f) << 21))
3913 #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
3915 /* An A form instruction. */
3916 #define A(op, xop, rc) \
3918 | ((((uint64_t)(xop)) & 0x1f) << 1) \
3919 | (((uint64_t)(rc)) & 1))
3920 #define A_MASK A (0x3f, 0x1f, 1)
3922 /* An A_MASK with the FRB field fixed. */
3923 #define AFRB_MASK (A_MASK | FRB_MASK)
3925 /* An A_MASK with the FRC field fixed. */
3926 #define AFRC_MASK (A_MASK | FRC_MASK)
3928 /* An A_MASK with the FRA and FRC fields fixed. */
3929 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
3931 /* An AFRAFRC_MASK, but with L bit clear. */
3932 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16))
3934 /* A B form instruction. */
3935 #define B(op, aa, lk) \
3937 | ((((uint64_t)(aa)) & 1) << 1) \
3939 #define B_MASK B (0x3f, 1, 1)
3941 /* A BD8 form instruction. This is a 16-bit instruction. */
3942 #define BD8(op, aa, lk) \
3943 (((((uint64_t)(op)) & 0x3f) << 10) \
3944 | (((aa) & 1) << 9) \
3945 | (((lk) & 1) << 8))
3946 #define BD8_MASK BD8 (0x3f, 1, 1)
3948 /* Another BD8 form instruction. This is a 16-bit instruction. */
3949 #define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11)
3950 #define BD8IO_MASK BD8IO (0x1f)
3952 /* A BD8 form instruction for simplified mnemonics. */
3953 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
3954 /* A mask that excludes BO32 and BI32. */
3955 #define EBD8IO1_MASK 0xf800
3956 /* A mask that includes BO32 and excludes BI32. */
3957 #define EBD8IO2_MASK 0xfc00
3958 /* A mask that include BO32 AND BI32. */
3959 #define EBD8IO3_MASK 0xff00
3961 /* A BD15 form instruction. */
3962 #define BD15(op, aa, lk) \
3964 | ((((uint64_t)(aa)) & 0xf) << 22) \
3966 #define BD15_MASK BD15 (0x3f, 0xf, 1)
3968 /* A BD15 form instruction for extended conditional branch mnemonics. */
3969 #define EBD15(op, aa, bo, lk) \
3970 (((op) & 0x3fu) << 26) \
3971 | (((aa) & 0xf) << 22) \
3972 | (((bo) & 0x3) << 20) \
3974 #define EBD15_MASK 0xfff00001
3976 /* A BD15 form instruction for extended conditional branch mnemonics
3978 #define EBD15BI(op, aa, bo, bi, lk) \
3979 ((((op) & 0x3fu) << 26) \
3980 | (((aa) & 0xf) << 22) \
3981 | (((bo) & 0x3) << 20) \
3982 | (((bi) & 0x3) << 16) \
3985 #define EBD15BI_MASK 0xfff30001
3987 /* A BD24 form instruction. */
3988 #define BD24(op, aa, lk) \
3990 | ((((uint64_t)(aa)) & 1) << 25) \
3992 #define BD24_MASK BD24 (0x3f, 1, 1)
3994 /* A B form instruction setting the BO field. */
3995 #define BBO(op, bo, aa, lk) \
3996 (B ((op), (aa), (lk)) \
3997 | ((((uint64_t)(bo)) & 0x1f) << 21))
3998 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
4000 /* A BBO_MASK with the y bit of the BO field removed. This permits
4001 matching a conditional branch regardless of the setting of the y
4002 bit. Similarly for the 'at' bits used for power4 branch hints. */
4003 #define Y_MASK (((uint64_t) 1) << 21)
4004 #define AT1_MASK (((uint64_t) 3) << 21)
4005 #define AT2_MASK (((uint64_t) 9) << 21)
4006 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
4007 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
4009 /* A B form instruction setting the BO field and the condition bits of
4011 #define BBOCB(op, bo, cb, aa, lk) \
4012 (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16))
4013 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
4015 /* A BBOCB_MASK with the y bit of the BO field removed. */
4016 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
4017 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
4018 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
4020 /* A BBOYCB_MASK in which the BI field is fixed. */
4021 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
4022 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
4024 /* A VLE C form instruction. */
4025 #define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1))
4026 #define C_LK_MASK C_LK(0x7fff, 1)
4027 #define C(x) ((((uint64_t)(x)) & 0xffff))
4028 #define C_MASK C(0xffff)
4030 /* An Context form instruction. */
4031 #define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7))
4032 #define CTX_MASK CTX(0x3f, 0x7)
4034 /* An User Context form instruction. */
4035 #define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
4036 #define UCTX_MASK UCTX(0x3f, 0x1f)
4038 /* The main opcode mask with the RA field clear. */
4039 #define DRA_MASK (OP_MASK | RA_MASK)
4041 /* A DQ form VSX instruction. */
4042 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
4043 #define DQX_MASK DQX (0x3f, 7)
4045 /* A DQ form VSX vector paired instruction. */
4046 #define DQXP(op, xop) (OP (op) | ((xop) & 0xf))
4047 #define DQXP_MASK DQXP (0x3f, 0xf)
4049 /* A DS form instruction. */
4050 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
4051 #define DS_MASK DSO (0x3f, 3)
4053 /* An DX form instruction. */
4054 #define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
4055 #define DX_MASK DX (0x3f, 0x1f)
4056 /* An DX form instruction with the D bits specified. */
4057 #define NODX_MASK (DX_MASK | 0x1fffc1)
4059 /* An EVSEL form instruction. */
4060 #define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3)
4061 #define EVSEL_MASK EVSEL(0x3f, 0xff)
4063 /* An IA16 form instruction. */
4064 #define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
4065 #define IA16_MASK IA16(0x3f, 0x1f)
4067 /* An I16A form instruction. */
4068 #define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
4069 #define I16A_MASK I16A(0x3f, 0x1f)
4071 /* An I16L form instruction. */
4072 #define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
4073 #define I16L_MASK I16L(0x3f, 0x1f)
4075 /* An IM7 form instruction. */
4076 #define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11)
4077 #define IM7_MASK IM7(0x1f)
4079 /* An M form instruction. */
4080 #define M(op, rc) (OP (op) | ((rc) & 1))
4081 #define M_MASK M (0x3f, 1)
4083 /* An LI20 form instruction. */
4084 #define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15)
4085 #define LI20_MASK LI20(0x3f, 0x1)
4087 /* An M form instruction with the ME field specified. */
4088 #define MME(op, me, rc) \
4090 | ((((uint64_t)(me)) & 0x1f) << 1))
4092 /* An M_MASK with the MB field fixed. */
4093 #define MMB_MASK (M_MASK | MB_MASK)
4095 /* An M_MASK with the ME field fixed. */
4096 #define MME_MASK (M_MASK | ME_MASK)
4098 /* An M_MASK with the MB and ME fields fixed. */
4099 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
4101 /* An M_MASK with the SH and ME fields fixed. */
4102 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
4104 /* An M_MASK with the SH and MB fields fixed. */
4105 #define MSHMB_MASK (M_MASK | SH_MASK | MB_MASK)
4107 /* An MD form instruction. */
4108 #define MD(op, xop, rc) \
4110 | ((((uint64_t)(xop)) & 0x7) << 2) \
4112 #define MD_MASK MD (0x3f, 0x7, 1)
4114 /* An MD_MASK with the MB field fixed. */
4115 #define MDMB_MASK (MD_MASK | MB6_MASK)
4117 /* An MD_MASK with the SH field fixed. */
4118 #define MDSH_MASK (MD_MASK | SH6_MASK)
4120 /* An MDS form instruction. */
4121 #define MDS(op, xop, rc) \
4123 | ((((uint64_t)(xop)) & 0xf) << 1) \
4125 #define MDS_MASK MDS (0x3f, 0xf, 1)
4127 /* An MDS_MASK with the MB field fixed. */
4128 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
4130 /* An SC form instruction. */
4131 #define SC(op, sa, lk) \
4133 | ((((uint64_t)(sa)) & 1) << 1) \
4137 | (((uint64_t) 0x3ff) << 16) \
4138 | (((uint64_t) 1) << 1) \
4141 /* An SCI8 form instruction. */
4142 #define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11))
4143 #define SCI8_MASK SCI8(0x3f, 0x1f)
4145 /* An SCI8 form instruction. */
4146 #define SCI8BF(op, fop, xop) \
4148 | ((((uint64_t)(xop)) & 0x1f) << 11) \
4149 | (((fop) & 7) << 23))
4150 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
4152 /* An SD4 form instruction. This is a 16-bit instruction. */
4153 #define SD4(op) ((((uint64_t)(op)) & 0xf) << 12)
4154 #define SD4_MASK SD4(0xf)
4156 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
4157 #define SE_IM5(op, xop) \
4158 (((((uint64_t)(op)) & 0x3f) << 10) \
4159 | (((xop) & 0x1) << 9))
4160 #define SE_IM5_MASK SE_IM5(0x3f, 1)
4162 /* An SE_R form instruction. This is a 16-bit instruction. */
4163 #define SE_R(op, xop) \
4164 (((((uint64_t)(op)) & 0x3f) << 10) \
4165 | (((xop) & 0x3f) << 4))
4166 #define SE_R_MASK SE_R(0x3f, 0x3f)
4168 /* An SE_RR form instruction. This is a 16-bit instruction. */
4169 #define SE_RR(op, xop) \
4170 (((((uint64_t)(op)) & 0x3f) << 10) \
4171 | (((xop) & 0x3) << 8))
4172 #define SE_RR_MASK SE_RR(0x3f, 3)
4174 /* A VX form instruction. */
4175 #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
4177 /* The mask for an VX form instruction. */
4178 #define VX_MASK VX(0x3f, 0x7ff)
4180 /* A VX LSP form instruction. */
4181 #define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff))
4183 /* The mask for an VX LSP form instruction. */
4184 #define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
4185 #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
4187 /* Additional format of VX SPE2 form instruction. */
4188 #define VX_RA_CONST(op, xop, bits11_15) \
4190 | (((uint64_t)(bits11_15) & 0x1f) << 16) \
4191 | (((uint64_t)(xop)) & 0x7ff))
4192 #define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f)
4194 #define VX_RB_CONST(op, xop, bits16_20) \
4196 | (((uint64_t)(bits16_20) & 0x1f) << 11) \
4197 | (((uint64_t)(xop)) & 0x7ff))
4198 #define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f)
4200 #define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8)
4202 #define VX_SPE_CRFD(op, xop, bits9_10) \
4204 | (((uint64_t)(bits9_10) & 0x3) << 21) \
4205 | (((uint64_t)(xop)) & 0x7ff))
4206 #define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3)
4208 #define VX_SPE2_CLR(op, xop, bit16) \
4210 | (((uint64_t)(bit16) & 0x1) << 15) \
4211 | (((uint64_t)(xop)) & 0x7ff))
4212 #define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1)
4214 #define VX_SPE2_SPLATB(op, xop, bits19_20) \
4216 | (((uint64_t)(bits19_20) & 0x3) << 11) \
4217 | (((uint64_t)(xop)) & 0x7ff))
4218 #define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3)
4220 #define VX_SPE2_OCTET(op, xop, bits16_17) \
4222 | (((uint64_t)(bits16_17) & 0x3) << 14) \
4223 | (((uint64_t)(xop)) & 0x7ff))
4224 #define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7)
4226 #define VX_SPE2_DDHH(op, xop, bit16) \
4228 | (((uint64_t)(bit16) & 0x1) << 15) \
4229 | (((uint64_t)(xop)) & 0x7ff))
4230 #define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1)
4232 #define VX_SPE2_HH(op, xop, bit16, bits19_20) \
4234 | (((uint64_t)(bit16) & 0x1) << 15) \
4235 | (((uint64_t)(bits19_20) & 0x3) << 11) \
4236 | (((uint64_t)(xop)) & 0x7ff))
4237 #define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3)
4239 #define VX_SPE2_EVMAR(op, xop) \
4241 | ((uint64_t)(0x1) << 11) \
4242 | (((uint64_t)(xop)) & 0x7ff))
4243 #define VX_SPE2_EVMAR_MASK \
4244 (VX_SPE2_EVMAR(0x3f, 0x7ff) \
4245 | ((uint64_t)(0x1) << 11))
4247 /* A VX_MASK with the VA field fixed. */
4248 #define VXVA_MASK (VX_MASK | (0x1f << 16))
4250 /* A VX_MASK with the VB field fixed. */
4251 #define VXVB_MASK (VX_MASK | (0x1f << 11))
4253 /* A VX_MASK with the VA and VB fields fixed. */
4254 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
4256 /* A VX_MASK with the VD and VA fields fixed. */
4257 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
4259 /* A VX_MASK with a UIMM4 field. */
4260 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
4262 /* A VX_MASK with a UIMM3 field. */
4263 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
4265 /* A VX_MASK with a UIMM2 field. */
4266 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
4268 /* A VX_MASK with a PS field. */
4269 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
4271 /* A VX_MASK with the VA field fixed with a PS field. */
4272 #define VXVAPS_MASK (VXVA_MASK & ~(0x1 << 9))
4274 /* A VX_MASK with the VA field fixed with a MP field. */
4275 #define VXVAM_MASK (VXVA_MASK & ~(0x1 << 16))
4277 /* A VX_MASK for instructions using a BF field. */
4278 #define VXBF_MASK (VX_MASK | (3 << 21))
4280 /* A VX_MASK for instructions with an RC field. */
4281 #define VXRC_MASK (VX_MASK & ~(0x1f << 6))
4283 /* A VX_MASK for instructions with a SH field. */
4284 #define VXSH_MASK (VX_MASK & ~(0x7 << 6))
4286 /* A VA form instruction. */
4287 #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f))
4289 /* The mask for an VA form instruction. */
4290 #define VXA_MASK VXA(0x3f, 0x3f)
4292 /* A VXA_MASK with a SHB field. */
4293 #define VXASHB_MASK (VXA_MASK | (1 << 10))
4295 /* A VXR form instruction. */
4296 #define VXR(op, xop, rc) \
4298 | (((uint64_t)(rc) & 1) << 10) \
4299 | (((uint64_t)(xop)) & 0x3ff))
4301 /* The mask for a VXR form instruction. */
4302 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
4304 /* A VX form instruction with a VA tertiary opcode. */
4305 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
4307 #define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
4308 #define VXASH_MASK VXASH (0x3f, 0x1f)
4310 /* An X form instruction. */
4311 #define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
4313 /* A X form instruction for Quad-Precision FP Instructions. */
4314 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
4316 /* An EX form instruction. */
4317 #define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
4319 /* The mask for an EX form instruction. */
4320 #define EX_MASK EX (0x3f, 0x7ff)
4322 /* An XX2 form instruction. */
4323 #define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2))
4325 /* A XX2 form instruction with the VA bits specified. */
4326 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
4328 /* An XX3 form instruction. */
4329 #define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3))
4331 /* An XX3 form instruction with the RC bit specified. */
4332 #define XX3RC(op, xop, rc) \
4334 | (((uint64_t)(rc) & 1) << 10) \
4335 | ((((uint64_t)(xop)) & 0x7f) << 3))
4337 /* An XX4 form instruction. */
4338 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
4340 /* A Z form instruction. */
4341 #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1))
4343 /* An X form instruction with the RC bit specified. */
4344 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
4346 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
4347 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
4349 /* An X form instruction with the RA bits specified as two ops. */
4350 #define XMMF(op, xop, mop0, mop1) \
4352 | ((mop0) & 3) << 19 \
4353 | ((mop1) & 7) << 16)
4355 /* A Z form instruction with the RC bit specified. */
4356 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
4358 /* The mask for an X form instruction. */
4359 #define X_MASK XRC (0x3f, 0x3ff, 1)
4361 /* The mask for an X form instruction with the BF bits specified. */
4362 #define XBF_MASK (X_MASK | (3 << 21))
4364 /* An X form instruction without the RC field specified. */
4365 #define XRC_MASK XRC (0x3f, 0x3ff, 0)
4367 /* An X form wait instruction with everything filled in except the WC
4369 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
4371 /* An X form wait instruction with everything filled in except the WC
4373 #define XWCPL_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | (3 << 18) | RB_MASK)
4375 /* The mask for an XX1 form instruction. */
4376 #define XX1_MASK X (0x3f, 0x3ff)
4378 /* An XX1_MASK with the RB field fixed. */
4379 #define XX1RB_MASK (XX1_MASK | RB_MASK)
4381 /* The mask for an XX2 form instruction. */
4382 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
4384 /* The mask for an XX2 form instruction with the UIM bits specified. */
4385 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
4387 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */
4388 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
4390 /* The mask for an XX2 form instruction with the BF bits specified. */
4391 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
4393 /* The mask for an XX2 form instruction with the BF and DCMX bits
4395 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
4397 /* The mask for an XX2 form instruction with a split DCMX bits
4399 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
4401 /* The mask for an XX3 form instruction. */
4402 #define XX3_MASK XX3 (0x3f, 0xff)
4404 /* The mask for an XX3 form instruction with the BF bits specified. */
4405 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
4407 /* The mask for an XX3 form instruction with the DM or SHW bits
4409 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
4410 #define XX3SHW_MASK XX3DM_MASK
4412 /* The mask for an XX4 form instruction. */
4413 #define XX4_MASK XX4 (0x3f, 0x3)
4415 /* An X form wait instruction with everything filled in except the WC
4417 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
4419 /* The mask for an XMMF form instruction. */
4420 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
4422 /* The mask for a Z form instruction. */
4423 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
4424 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4426 /* An X_MASK with the RA/VA field fixed. */
4427 #define XRA_MASK (X_MASK | RA_MASK)
4428 #define XVA_MASK XRA_MASK
4430 /* An XRA_MASK with the A_L/W field clear. */
4431 #define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16))
4432 #define XRLA_MASK XWRA_MASK
4434 /* An X_MASK with the RB field fixed. */
4435 #define XRB_MASK (X_MASK | RB_MASK)
4437 /* An X_MASK with the RT field fixed. */
4438 #define XRT_MASK (X_MASK | RT_MASK)
4440 /* An XRT_MASK mask with the 2 L bits clear. */
4441 #define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21))
4443 /* An XRT_MASK mask with the 3 L bits clear. */
4444 #define XL3RT_MASK (XRT_MASK & ~((uint64_t) 0x7 << 21))
4446 /* An X_MASK with the RA and RB fields fixed. */
4447 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
4449 /* An XBF_MASK with the RA and RB fields fixed. */
4450 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
4452 /* An XRARB_MASK, but with the L bit clear. */
4453 #define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16))
4455 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */
4456 #define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16))
4458 /* An X_MASK with the RT and RA fields fixed. */
4459 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
4461 /* An X_MASK with the RT and RB fields fixed. */
4462 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
4464 /* An XRTRA_MASK, but with L bit clear. */
4465 #define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21))
4467 /* An X_MASK with the RT, RA and RB fields fixed. */
4468 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
4470 /* An XRTRARB_MASK, but with L bit clear. */
4471 #define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21))
4473 /* An XRTRARB_MASK, but with A bit clear. */
4474 #define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25))
4476 /* An XRTRARB_MASK, but with BF bits clear. */
4477 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23))
4479 /* An X form instruction with the L bit specified. */
4480 #define XOPL(op, xop, l) \
4482 | ((((uint64_t)(l)) & 1) << 21))
4484 /* An X form instruction with the 2 L bits specified. */
4485 #define XOPL2(op, xop, l) \
4487 | ((((uint64_t)(l)) & 3) << 21))
4489 /* An X form instruction with the 3 L bits specified. */
4490 #define XOPL3(op, xop, l) \
4492 | ((((uint64_t)(l)) & 7) << 21))
4494 /* An X form instruction with the WC and PL bits specified. */
4495 #define XWCPL(op, xop, wc, pl) \
4496 (XOPL3 ((op), (xop), (wc)) \
4497 | ((((uint64_t)(pl)) & 3) << 16))
4499 /* An X form instruction with the L bit and RC bit specified. */
4500 #define XRCL(op, xop, l, rc) \
4501 (XRC ((op), (xop), (rc)) \
4502 | ((((uint64_t)(l)) & 1) << 21))
4504 /* An X form instruction with RT fields specified */
4505 #define XRT(op, xop, rt) \
4507 | ((((uint64_t)(rt)) & 0x1f) << 21))
4509 /* An X form instruction with RT and RA fields specified */
4510 #define XRTRA(op, xop, rt, ra) \
4512 | ((((uint64_t)(rt)) & 0x1f) << 21) \
4513 | ((((uint64_t)(ra)) & 0x1f) << 16))
4515 /* The mask for an X form comparison instruction. */
4516 #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22))
4518 /* The mask for an X form comparison instruction with the L field
4520 #define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21))
4522 /* An X form trap instruction with the TO field specified. */
4523 #define XTO(op, xop, to) \
4525 | ((((uint64_t)(to)) & 0x1f) << 21))
4526 #define XTO_MASK (X_MASK | TO_MASK)
4528 /* An X form tlb instruction with the SH field specified. */
4529 #define XTLB(op, xop, sh) \
4531 | ((((uint64_t)(sh)) & 0x1f) << 11))
4532 #define XTLB_MASK (X_MASK | SH_MASK)
4534 /* An X form sync instruction. */
4535 #define XSYNC(op, xop, l) \
4537 | ((((uint64_t)(l)) & 3) << 21))
4539 /* An X form sync instruction with everything filled in except the LS
4541 #define XSYNC_MASK (0xff9fffff)
4543 /* An X form sync instruction with everything filled in except the L
4545 #define XSYNCLE_MASK (0xff90ffff)
4547 /* An X form sync instruction. */
4548 #define XSYNCLS(op, xop, l, s) \
4550 | ((((uint64_t)(l)) & 7) << 21) \
4551 | ((((uint64_t)(s)) & 3) << 16))
4553 /* An X form sync instruction with everything filled in except the
4555 #define XSYNCLS_MASK (0xff1cffff)
4557 /* An X_MASK, but with the EH bit clear. */
4558 #define XEH_MASK (X_MASK & ~((uint64_t )1))
4560 /* An X form AltiVec dss instruction. */
4561 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25))
4562 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
4564 /* An XFL form instruction. */
4565 #define XFL(op, xop, rc) \
4567 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
4568 | (((uint64_t)(rc)) & 1))
4569 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
4571 /* An X form isel instruction. */
4572 #define XISEL(op, xop, cr) (OP (op) | ((xop) << 1) | ((cr) << 6))
4573 #define XISEL_MASK XISEL(0x3f, 0x1f, 0)
4575 /* An XL form instruction with the LK field set to 0. */
4576 #define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
4578 /* An XL form instruction which uses the LK field. */
4579 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
4581 /* The mask for an XL form instruction. */
4582 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
4584 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
4585 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
4587 /* An XL form instruction which explicitly sets the BO field. */
4588 #define XLO(op, bo, xop, lk) \
4589 (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21))
4590 #define XLO_MASK (XL_MASK | BO_MASK)
4592 /* An XL form instruction which sets the BO field and the condition
4593 bits of the BI field. */
4594 #define XLOCB(op, bo, cb, xop, lk) \
4595 (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16))
4597 /* An XL_MASK with the BB field fixed. */
4598 #define XLBB_MASK (XL_MASK | BB_MASK)
4600 /* A mask for branch instructions using the BH field. */
4601 #define XLBH_MASK (XL_MASK | (BB_MASK & ~(3 << 11)))
4603 /* An XLBH_MASK with the BO field fixed. */
4604 #define XLBOBB_MASK (XLBH_MASK | BO_MASK)
4606 /* An XLBH_MASK with the BO and BI fields fixed. */
4607 #define XLBOBIBB_MASK (XLBOBB_MASK | BI_MASK)
4609 /* An XLBH_MASK with the BO and condition bits of the BI fields fixed. */
4610 #define XLBOCBBB_MASK (XLBOBB_MASK | (3 << 16))
4612 /* An X form mbar instruction with MO field. */
4613 #define XMBAR(op, xop, mo) \
4615 | ((((uint64_t)(mo)) & 1) << 21))
4617 /* An XO form instruction. */
4618 #define XO(op, xop, oe, rc) \
4620 | ((((uint64_t)(xop)) & 0x1ff) << 1) \
4621 | ((((uint64_t)(oe)) & 1) << 10) \
4622 | (((unsigned long)(rc)) & 1))
4623 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
4625 /* An XO_MASK with the RB field fixed. */
4626 #define XORB_MASK (XO_MASK | RB_MASK)
4628 /* An XOPS form instruction for paired singles. */
4629 #define XOPS(op, xop, rc) \
4631 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
4632 | (((uint64_t)(rc)) & 1))
4633 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
4636 /* An XS form instruction. */
4637 #define XS(op, xop, rc) \
4639 | ((((uint64_t)(xop)) & 0x1ff) << 2) \
4640 | (((uint64_t)(rc)) & 1))
4641 #define XS_MASK XS (0x3f, 0x1ff, 1)
4643 /* A mask for the FXM version of an XFX form instruction. */
4644 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
4646 /* An XFX form instruction with the FXM field filled in. */
4647 #define XFXM(op, xop, fxm, p4) \
4649 | ((((uint64_t)(fxm)) & 0xff) << 12) \
4650 | ((uint64_t)(p4) << 20))
4652 /* An XFX form instruction with the SPR field filled in. */
4653 #define XSPR(op, xop, spr) \
4655 | ((((uint64_t)(spr)) & 0x1f) << 16) \
4656 | ((((uint64_t)(spr)) & 0x3e0) << 6))
4657 #define XSPR_MASK (X_MASK | SPR_MASK)
4659 /* An XFX form instruction with the SPR field filled in except for the
4661 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
4663 /* An XFX form instruction with the SPR field filled in except for the
4665 #define XSPRGQR_MASK (XSPR_MASK &~ SPRGQR_MASK)
4667 /* An XFX form instruction with the SPR field filled in except for the
4669 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
4671 /* An X form instruction with everything filled in except the E field. */
4672 #define XE_MASK (0xffff7fff)
4674 /* An X form user context instruction. */
4675 #define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
4676 #define XUC_MASK XUC(0x3f, 0x1f)
4678 /* An XW form instruction. */
4679 #define XW(op, xop, rc) \
4681 | ((((uint64_t)(xop)) & 0x3f) << 1) \
4683 /* The mask for a G form instruction. rc not supported at present. */
4684 #define XW_MASK XW (0x3f, 0x3f, 0)
4686 /* An APU form instruction. */
4687 #define APU(op, xop, rc) \
4689 | (((uint64_t)(xop)) & 0x3ff) << 1 \
4692 /* The mask for an APU form instruction. */
4693 #define APU_MASK APU (0x3f, 0x3ff, 1)
4694 #define APU_RT_MASK (APU_MASK | RT_MASK)
4695 #define APU_RA_MASK (APU_MASK | RA_MASK)
4697 /* The BO encodings used in extended conditional branch mnemonics. */
4698 #define BODNZF (0x0)
4699 #define BODNZFP (0x1)
4701 #define BODZFP (0x3)
4702 #define BODNZT (0x8)
4703 #define BODNZTP (0x9)
4705 #define BODZTP (0xb)
4716 #define BODNZ (0x10)
4717 #define BODNZP (0x11)
4719 #define BODZP (0x13)
4720 #define BODNZM4 (0x18)
4721 #define BODNZP4 (0x19)
4722 #define BODZM4 (0x1a)
4723 #define BODZP4 (0x1b)
4727 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
4731 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
4734 #define BO32DNZ (0x2)
4735 #define BO32DZ (0x3)
4737 /* The BI condition bit encodings used in extended conditional branch
4744 /* The TO encodings used in extended trap mnemonics. */
4761 /* Smaller names for the flags so each entry in the opcodes table will
4762 fit on a single line. */
4764 #define PPC PPC_OPCODE_PPC
4765 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
4766 #define POWER4 PPC_OPCODE_POWER4
4767 #define POWER5 PPC_OPCODE_POWER5
4768 #define POWER6 PPC_OPCODE_POWER6
4769 #define POWER7 PPC_OPCODE_POWER7
4770 #define POWER8 PPC_OPCODE_POWER8
4771 #define POWER9 PPC_OPCODE_POWER9
4772 #define POWER10 PPC_OPCODE_POWER10
4773 #define CELL PPC_OPCODE_CELL
4774 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
4775 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
4776 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
4777 #define PPC403 PPC_OPCODE_403
4778 #define PPC405 PPC_OPCODE_405
4779 #define PPC440 PPC_OPCODE_440
4780 #define PPC464 PPC440
4781 #define PPC476 PPC_OPCODE_476
4782 #define PPC750 PPC_OPCODE_750
4783 #define GEKKO PPC_OPCODE_750
4784 #define BROADWAY PPC_OPCODE_750
4785 #define PPC7450 PPC_OPCODE_7450
4786 #define PPC860 PPC_OPCODE_860
4787 #define PPCPS PPC_OPCODE_PPCPS
4788 #define PPCVEC PPC_OPCODE_ALTIVEC
4789 #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500)
4790 #define PPCVEC3 PPC_OPCODE_POWER9
4791 #define PPCVSX PPC_OPCODE_VSX
4792 #define PPCVSX2 PPC_OPCODE_POWER8
4793 #define PPCVSX3 PPC_OPCODE_POWER9
4794 #define PPCVSX4 PPC_OPCODE_POWER10
4795 #define POWER PPC_OPCODE_POWER
4796 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
4797 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
4798 #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \
4799 | PPC_OPCODE_COMMON)
4800 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
4801 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
4802 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
4803 #define MFDEC1 PPC_OPCODE_POWER
4804 #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \
4806 #define BOOKE PPC_OPCODE_BOOKE
4807 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
4808 #define PPCE300 PPC_OPCODE_E300
4809 #define PPCSPE PPC_OPCODE_SPE
4810 #define PPCSPE2 PPC_OPCODE_SPE2
4811 #define PPCISEL PPC_OPCODE_ISEL
4812 #define PPCEFS PPC_OPCODE_EFS
4813 #define PPCEFS2 PPC_OPCODE_EFS2
4814 #define PPCBRLK PPC_OPCODE_BRLOCK
4815 #define PPCPMR PPC_OPCODE_PMR
4816 #define PPCTMR PPC_OPCODE_TMR
4817 #define PPCCHLK PPC_OPCODE_CACHELCK
4818 #define PPCRFMCI PPC_OPCODE_RFMCI
4819 #define E500MC PPC_OPCODE_E500MC
4820 #define PPCA2 PPC_OPCODE_A2
4821 #define TITAN PPC_OPCODE_TITAN
4822 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
4823 #define E500 PPC_OPCODE_E500
4824 #define E6500 PPC_OPCODE_E6500
4825 #define PPCVLE PPC_OPCODE_VLE
4826 #define PPCHTM PPC_OPCODE_POWER8
4827 #define E200Z4 PPC_OPCODE_E200Z4
4828 #define PPCLSP PPC_OPCODE_LSP
4829 /* Used to mark extended mnemonic in deprecated field so that -Mraw
4830 won't use this variant in disassembly. */
4831 #define EXT PPC_OPCODE_RAW
4833 /* The opcode table.
4835 The format of the opcode table is:
4837 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
4839 NAME is the name of the instruction.
4840 OPCODE is the instruction opcode.
4841 MASK is the opcode mask; this is used to tell the disassembler
4842 which bits in the actual opcode must match OPCODE.
4843 FLAGS are flags indicating which processors support the instruction.
4844 ANTI indicates which processors don't support the instruction.
4845 OPERANDS is the list of operands.
4847 The disassembler reads the table in order and prints the first
4848 instruction which matches, so this table is sorted to put more
4849 specific instructions before more general instructions.
4851 This table must be sorted by major opcode. Please try to keep it
4852 vaguely sorted within major opcode too, except of course where
4853 constrained otherwise by disassembler operation. */
4855 const struct powerpc_opcode powerpc_opcodes
[] = {
4856 {"attn", X(0,256), X_MASK
, POWER4
|PPCA2
, PPC476
|PPCVLE
, {0}},
4857 {"tdlgti", OPTO(2,TOLGT
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4858 {"tdllti", OPTO(2,TOLLT
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4859 {"tdeqi", OPTO(2,TOEQ
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4860 {"tdlgei", OPTO(2,TOLGE
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4861 {"tdlnli", OPTO(2,TOLNL
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4862 {"tdllei", OPTO(2,TOLLE
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4863 {"tdlngi", OPTO(2,TOLNG
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4864 {"tdgti", OPTO(2,TOGT
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4865 {"tdgei", OPTO(2,TOGE
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4866 {"tdnli", OPTO(2,TONL
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4867 {"tdlti", OPTO(2,TOLT
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4868 {"tdlei", OPTO(2,TOLE
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4869 {"tdngi", OPTO(2,TONG
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4870 {"tdnei", OPTO(2,TONE
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4871 {"tdui", OPTO(2,TOU
), OPTO_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, SI
}},
4872 {"tdi", OP(2), OP_MASK
, PPC64
, PPCVLE
, {TO
, RA
, SI
}},
4874 {"twlgti", OPTO(3,TOLGT
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4875 {"tlgti", OPTO(3,TOLGT
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4876 {"twllti", OPTO(3,TOLLT
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4877 {"tllti", OPTO(3,TOLLT
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4878 {"tweqi", OPTO(3,TOEQ
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4879 {"teqi", OPTO(3,TOEQ
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4880 {"twlgei", OPTO(3,TOLGE
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4881 {"tlgei", OPTO(3,TOLGE
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4882 {"twlnli", OPTO(3,TOLNL
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4883 {"tlnli", OPTO(3,TOLNL
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4884 {"twllei", OPTO(3,TOLLE
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4885 {"tllei", OPTO(3,TOLLE
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4886 {"twlngi", OPTO(3,TOLNG
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4887 {"tlngi", OPTO(3,TOLNG
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4888 {"twgti", OPTO(3,TOGT
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4889 {"tgti", OPTO(3,TOGT
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4890 {"twgei", OPTO(3,TOGE
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4891 {"tgei", OPTO(3,TOGE
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4892 {"twnli", OPTO(3,TONL
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4893 {"tnli", OPTO(3,TONL
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4894 {"twlti", OPTO(3,TOLT
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4895 {"tlti", OPTO(3,TOLT
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4896 {"twlei", OPTO(3,TOLE
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4897 {"tlei", OPTO(3,TOLE
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4898 {"twngi", OPTO(3,TONG
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4899 {"tngi", OPTO(3,TONG
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4900 {"twnei", OPTO(3,TONE
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4901 {"tnei", OPTO(3,TONE
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4902 {"twui", OPTO(3,TOU
), OPTO_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4903 {"tui", OPTO(3,TOU
), OPTO_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, SI
}},
4904 {"twi", OP(3), OP_MASK
, PPCCOM
, PPCVLE
, {TO
, RA
, SI
}},
4905 {"ti", OP(3), OP_MASK
, PWRCOM
, PPCVLE
, {TO
, RA
, SI
}},
4907 {"ps_cmpu0", X (4, 0), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
4908 {"vaddubm", VX (4, 0), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4909 {"vmul10cuq", VX (4, 1), VXVB_MASK
, PPCVEC3
, 0, {VD
, VA
}},
4910 {"vmaxub", VX (4, 2), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4911 {"vrlb", VX (4, 4), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4912 {"vrlq", VX (4, 5), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4913 {"vcmpequb", VXR(4, 6,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4914 {"vcmpneb", VXR(4, 7,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
4915 {"vmuloub", VX (4, 8), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4916 {"vaddfp", VX (4, 10), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4917 {"vdivuq", VX (4, 11), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
4918 {"psq_lx", XW (4, 6,0), XW_MASK
, PPCPS
, 0, {FRT
,RA
,RB
,PSWM
,PSQM
}},
4919 {"vmrghb", VX (4, 12), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4920 {"vstribl", VXVA(4,13,0), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
4921 {"vstribr", VXVA(4,13,1), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
4922 {"vstrihl", VXVA(4,13,2), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
4923 {"vstrihr", VXVA(4,13,3), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
4924 {"psq_stx", XW (4, 7,0), XW_MASK
, PPCPS
, 0, {FRS
,RA
,RB
,PSWM
,PSQM
}},
4925 {"vpkuhum", VX (4, 14), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
4926 {"vinsbvlx", VX (4, 15), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
4927 {"mulhhwu", XRC(4, 8,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4928 {"mulhhwu.", XRC(4, 8,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4929 {"mtvsrbmi", DX (4,10), DX_MASK
, POWER10
, 0, {VD
, DXD
}},
4930 {"ps_sum0", A (4, 10,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4931 {"ps_sum0.", A (4, 10,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4932 {"vsldbi", VX (4, 22), VXSH_MASK
, POWER10
, 0, {VD
, VA
, VB
, SH3
}},
4933 {"ps_sum1", A (4, 11,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4934 {"ps_sum1.", A (4, 11,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4935 {"vextdubvlx", VX (4, 24), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4936 {"ps_muls0", A (4, 12,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4937 {"machhwu", XO (4, 12,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4938 {"vextdubvrx", VX (4, 25), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4939 {"ps_muls0.", A (4, 12,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4940 {"machhwu.", XO (4, 12,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
4941 {"vextduhvlx", VX (4, 26), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4942 {"ps_muls1", A (4, 13,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4943 {"vextduhvrx", VX (4, 27), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4944 {"ps_muls1.", A (4, 13,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4945 {"vextduwvlx", VX (4, 28), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4946 {"ps_madds0", A (4, 14,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4947 {"vextduwvrx", VX (4, 29), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4948 {"ps_madds0.", A (4, 14,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4949 {"vextddvlx", VX (4, 30), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4950 {"ps_madds1", A (4, 15,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4951 {"vextddvrx", VX (4, 31), VXRC_MASK
, POWER10
, 0, {VD
, VA
, VB
, RC
}},
4952 {"ps_madds1.", A (4, 15,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4953 {"vmhaddshs", VXA(4, 32), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4954 {"vmhraddshs", VXA(4, 33), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4955 {"vmladduhm", VXA(4, 34), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4956 {"vmsumudm", VXA(4, 35), VXA_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, VC
}},
4957 {"ps_div", A (4, 18,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4958 {"vmsumcud", VXA(4, 23), VXA_MASK
, POWER10
, 0, {VD
, VA
, VB
, VC
}},
4959 {"vmsumubm", VXA(4, 36), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4960 {"ps_div.", A (4, 18,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4961 {"vmsummbm", VXA(4, 37), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4962 {"vmsumuhm", VXA(4, 38), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4963 {"vmsumuhs", VXA(4, 39), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4964 {"ps_sub", A (4, 20,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4965 {"vmsumshm", VXA(4, 40), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4966 {"ps_sub.", A (4, 20,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4967 {"vmsumshs", VXA(4, 41), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4968 {"ps_add", A (4, 21,0), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4969 {"vsel", VXA(4, 42), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4970 {"ps_add.", A (4, 21,1), AFRC_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
4971 {"vperm", VXA(4, 43), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, VC
}},
4972 {"vsldoi", VXA(4, 44), VXASHB_MASK
, PPCVEC
, 0, {VD
, VA
, VB
, SHB
}},
4973 {"vpermxor", VXA(4, 45), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
4974 {"ps_sel", A (4, 23,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4975 {"vmaddfp", VXA(4, 46), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VC
, VB
}},
4976 {"ps_sel.", A (4, 23,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4977 {"vnmsubfp", VXA(4, 47), VXA_MASK
, PPCVEC
, 0, {VD
, VA
, VC
, VB
}},
4978 {"ps_res", A (4, 24,0), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4979 {"maddhd", VXA(4, 48), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
4980 {"ps_res.", A (4, 24,1), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4981 {"maddhdu", VXA(4, 49), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
4982 {"ps_mul", A (4, 25,0), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4983 {"ps_mul.", A (4, 25,1), AFRB_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
}},
4984 {"maddld", VXA(4, 51), VXA_MASK
, POWER9
, 0, {RT
, RA
, RB
, RC
}},
4985 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4986 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK
, PPCPS
, 0, {FRT
, FRB
}},
4987 {"ps_msub", A (4, 28,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4988 {"ps_msub.", A (4, 28,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4989 {"ps_madd", A (4, 29,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4990 {"ps_madd.", A (4, 29,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4991 {"vpermr", VXA(4, 59), VXA_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, VC
}},
4992 {"ps_nmsub", A (4, 30,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4993 {"vaddeuqm", VXA(4, 60), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
4994 {"ps_nmsub.", A (4, 30,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4995 {"vaddecuq", VXA(4, 61), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
4996 {"ps_nmadd", A (4, 31,0), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4997 {"vsubeuqm", VXA(4, 62), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
4998 {"ps_nmadd.", A (4, 31,1), A_MASK
, PPCPS
, 0, {FRT
, FRA
, FRC
, FRB
}},
4999 {"vsubecuq", VXA(4, 63), VXA_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, VC
}},
5000 {"ps_cmpo0", X (4, 32), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
5001 {"vadduhm", VX (4, 64), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5002 {"vmul10ecuq", VX (4, 65), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5003 {"vmaxuh", VX (4, 66), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5004 {"vrlh", VX (4, 68), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5005 {"vrlqmi", VX (4, 69), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5006 {"vcmpequh", VXR(4, 70,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5007 {"vcmpneh", VXR(4, 71,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5008 {"vmulouh", VX (4, 72), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5009 {"vsubfp", VX (4, 74), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5010 {"psq_lux", XW (4, 38,0), XW_MASK
, PPCPS
, 0, {FRT
,RA
,RB
,PSWM
,PSQM
}},
5011 {"vmrghh", VX (4, 76), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5012 {"psq_stux", XW (4, 39,0), XW_MASK
, PPCPS
, 0, {FRS
,RA
,RB
,PSWM
,PSQM
}},
5013 {"vpkuwum", VX (4, 78), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5014 {"vinshvlx", VX (4, 79), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
5015 {"ps_neg", XRC(4, 40,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
5016 {"mulhhw", XRC(4, 40,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5017 {"ps_neg.", XRC(4, 40,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
5018 {"mulhhw.", XRC(4, 40,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5019 {"machhw", XO (4, 44,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5020 {"machhw.", XO (4, 44,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5021 {"nmachhw", XO (4, 46,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5022 {"nmachhw.", XO (4, 46,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5023 {"ps_cmpu1", X (4, 64), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
5024 {"vadduwm", VX (4, 128), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5025 {"vmaxuw", VX (4, 130), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5026 {"vrlw", VX (4, 132), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5027 {"vrlwmi", VX (4, 133), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5028 {"vcmpequw", VXR(4, 134,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5029 {"vcmpnew", VXR(4, 135,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5030 {"vmulouw", VX (4, 136), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5031 {"vmuluwm", VX (4, 137), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5032 {"vdivuw", VX (4, 139), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5033 {"vmrghw", VX (4, 140), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5034 {"vpkuhus", VX (4, 142), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5035 {"vinswvlx", VX (4, 143), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
5036 {"ps_mr", XRC(4, 72,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
5037 {"ps_mr.", XRC(4, 72,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
5038 {"machhwsu", XO (4, 76,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5039 {"machhwsu.", XO (4, 76,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5040 {"ps_cmpo1", X (4, 96), XBF_MASK
, PPCPS
, 0, {BF
, FRA
, FRB
}},
5041 {"vaddudm", VX (4, 192), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5042 {"vmaxud", VX (4, 194), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5043 {"vrld", VX (4, 196), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5044 {"vrldmi", VX (4, 197), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5045 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5046 {"vcmpequd", VXR(4, 199,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5047 {"vmuloud", VX (4, 200), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5048 {"vdivud", VX (4, 203), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5049 {"vpkuwus", VX (4, 206), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5050 {"vinsw", VX (4, 207), VXUIMM4_MASK
, POWER10
, 0, {VD
, RB
, UIMM4
}},
5051 {"machhws", XO (4, 108,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5052 {"machhws.", XO (4, 108,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5053 {"nmachhws", XO (4, 110,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5054 {"nmachhws.", XO (4, 110,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5055 {"vadduqm", VX (4, 256), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5056 {"vcmpuq", VX (4, 257), VXBF_MASK
, POWER10
, 0, {BF
, VA
, VB
}},
5057 {"vmaxsb", VX (4, 258), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5058 {"vslb", VX (4, 260), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5059 {"vslq", VX (4, 261), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5060 {"vcmpnezb", VXR(4, 263,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5061 {"vmulosb", VX (4, 264), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5062 {"vrefp", VX (4, 266), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5063 {"vdivsq", VX (4, 267), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5064 {"vmrglb", VX (4, 268), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5065 {"vpkshus", VX (4, 270), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5066 {"vinsbvrx", VX (4, 271), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
5067 {"ps_nabs", XRC(4, 136,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
5068 {"mulchwu", XRC(4, 136,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5069 {"ps_nabs.", XRC(4, 136,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
5070 {"mulchwu.", XRC(4, 136,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5071 {"macchwu", XO (4, 140,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5072 {"macchwu.", XO (4, 140,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5073 {"vaddcuq", VX (4, 320), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5074 {"vcmpsq", VX (4, 321), VXBF_MASK
, POWER10
, 0, {BF
, VA
, VB
}},
5075 {"vmaxsh", VX (4, 322), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5076 {"vslh", VX (4, 324), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5077 {"vrlqnm", VX (4, 325), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5078 {"vcmpnezh", VXR(4, 327,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5079 {"vmulosh", VX (4, 328), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5080 {"vrsqrtefp", VX (4, 330), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5081 {"vmrglh", VX (4, 332), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5082 {"vpkswus", VX (4, 334), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5083 {"vinshvrx", VX (4, 335), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
5084 {"mulchw", XRC(4, 168,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5085 {"mulchw.", XRC(4, 168,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5086 {"macchw", XO (4, 172,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5087 {"macchw.", XO (4, 172,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5088 {"nmacchw", XO (4, 174,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5089 {"nmacchw.", XO (4, 174,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5090 {"vaddcuw", VX (4, 384), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5091 {"vmaxsw", VX (4, 386), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5092 {"vslw", VX (4, 388), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5093 {"vrlwnm", VX (4, 389), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5094 {"vcmpnezw", VXR(4, 391,0), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5095 {"vmulosw", VX (4, 392), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5096 {"vexptefp", VX (4, 394), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5097 {"vdivsw", VX (4, 395), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5098 {"vmrglw", VX (4, 396), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5099 {"vclrlb", VX (4, 397), VX_MASK
, POWER10
, 0, {VD
, VA
, RB
}},
5100 {"vpkshss", VX (4, 398), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5101 {"vinswvrx", VX (4, 399), VX_MASK
, POWER10
, 0, {VD
, RA
, VB
}},
5102 {"macchwsu", XO (4, 204,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5103 {"macchwsu.", XO (4, 204,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5104 {"vmaxsd", VX (4, 450), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5105 {"vsl", VX (4, 452), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5106 {"vrldnm", VX (4, 453), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5107 {"vcmpgefp", VXR(4, 454,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5108 {"vcmpequq", VXR(4, 455,0), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5109 {"vmulosd", VX (4, 456), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5110 {"vmulld", VX (4, 457), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5111 {"vlogefp", VX (4, 458), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5112 {"vdivsd", VX (4, 459), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5113 {"vclrrb", VX (4, 461), VX_MASK
, POWER10
, 0, {VD
, VA
, RB
}},
5114 {"vpkswss", VX (4, 462), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5115 {"vinsd", VX (4, 463), VXUIMM4_MASK
, POWER10
, 0, {VD
, RB
, UIMM4
}},
5116 {"macchws", XO (4, 236,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5117 {"macchws.", XO (4, 236,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5118 {"nmacchws", XO (4, 238,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5119 {"nmacchws.", XO (4, 238,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5120 {"evaddw", VX (4, 512), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5121 {"vaddubs", VX (4, 512), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5122 {"vmul10uq", VX (4, 513), VXVB_MASK
, PPCVEC3
, 0, {VD
, VA
}},
5123 {"evaddiw", VX (4, 514), VX_MASK
, PPCSPE
, 0, {RS
, RB
, UIMM
}},
5124 {"vminub", VX (4, 514), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5125 {"evsubfw", VX (4, 516), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5126 {"evsubw", VX (4, 516), VX_MASK
, PPCSPE
, 0, {RS
, RB
, RA
}},
5127 {"vsrb", VX (4, 516), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5128 {"vsrq", VX (4, 517), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5129 {"evsubifw", VX (4, 518), VX_MASK
, PPCSPE
, 0, {RS
, UIMM
, RB
}},
5130 {"evsubiw", VX (4, 518), VX_MASK
, PPCSPE
, 0, {RS
, RB
, UIMM
}},
5131 {"vcmpgtub", VXR(4, 518,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5132 {"evabs", VX (4, 520), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5133 {"vmuleub", VX (4, 520), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5134 {"evneg", VX (4, 521), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5135 {"evextsb", VX (4, 522), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5136 {"vrfin", VX (4, 522), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5137 {"vdiveuq", VX (4, 523), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5138 {"evextsh", VX (4, 523), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5139 {"evrndw", VX (4, 524), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5140 {"vspltb", VX (4, 524), VXUIMM4_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM4
}},
5141 {"vextractub", VX (4, 525), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
5142 {"evcntlzw", VX (4, 525), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5143 {"evcntlsw", VX (4, 526), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5144 {"vupkhsb", VX (4, 526), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5145 {"vinsblx", VX (4, 527), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
5146 {"brinc", VX (4, 527), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5147 {"ps_abs", XRC(4, 264,0), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
5148 {"ps_abs.", XRC(4, 264,1), XRA_MASK
, PPCPS
, 0, {FRT
, FRB
}},
5149 {"evand", VX (4, 529), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5150 {"evandc", VX (4, 530), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5151 {"vsrdbi", VX (4, 534), VXSH_MASK
, POWER10
, 0, {VD
, VA
, VB
, SH3
}},
5152 {"evxor", VX (4, 534), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5153 {"evmr", VX (4, 535), VX_MASK
, PPCSPE
, EXT
, {RS
, RAB
}},
5154 {"evor", VX (4, 535), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5155 {"evnot", VX (4, 536), VX_MASK
, PPCSPE
, EXT
, {RS
, RAB
}},
5156 {"evnor", VX (4, 536), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5157 {"get", APU(4, 268,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
5158 {"eveqv", VX (4, 537), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5159 {"evorc", VX (4, 539), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5160 {"evnand", VX (4, 542), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5161 {"evsrwu", VX (4, 544), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5162 {"evsrws", VX (4, 545), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5163 {"evsrwiu", VX (4, 546), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
5164 {"evsrwis", VX (4, 547), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
5165 {"evslw", VX (4, 548), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5166 {"evslwi", VX (4, 550), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
5167 {"evrlw", VX (4, 552), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5168 {"evsplati", VX (4, 553), VX_MASK
, PPCSPE
, 0, {RS
, SIMM
}},
5169 {"evrlwi", VX (4, 554), VX_MASK
, PPCSPE
, 0, {RS
, RA
, EVUIMM
}},
5170 {"evsplatfi", VX (4, 555), VX_MASK
, PPCSPE
, 0, {RS
, SIMM
}},
5171 {"evmergehi", VX (4, 556), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5172 {"evmergelo", VX (4, 557), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5173 {"evmergehilo", VX (4, 558), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5174 {"evmergelohi", VX (4, 559), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5175 {"evcmpgtu", VX (4, 560), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5176 {"evcmpgts", VX (4, 561), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5177 {"evcmpltu", VX (4, 562), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5178 {"evcmplts", VX (4, 563), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5179 {"evcmpeq", VX (4, 564), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5180 {"cget", APU(4, 284,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
5181 {"vadduhs", VX (4, 576), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5182 {"vmul10euq", VX (4, 577), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5183 {"vminuh", VX (4, 578), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5184 {"vsrh", VX (4, 580), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5185 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5186 {"vmuleuh", VX (4, 584), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5187 {"vrfiz", VX (4, 586), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5188 {"vsplth", VX (4, 588), VXUIMM3_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM3
}},
5189 {"vextractuh", VX (4, 589), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
5190 {"vupkhsh", VX (4, 590), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5191 {"vinshlx", VX (4, 591), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
5192 {"nget", APU(4, 300,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
5193 {"evsel", EVSEL(4,79), EVSEL_MASK
, PPCSPE
, 0, {RS
, RA
, RB
, CRFS
}},
5194 {"ncget", APU(4, 316,0), APU_RA_MASK
, PPC405
, 0, {RT
, FSL
}},
5195 {"evfsadd", VX (4, 640), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5196 {"vadduws", VX (4, 640), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5197 {"evfssub", VX (4, 641), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5198 {"evfsmadd", VX (4, 642), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5199 {"vminuw", VX (4, 642), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5200 {"evfsmsub", VX (4, 643), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5201 {"evfsabs", VX (4, 644), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5202 {"vsrw", VX (4, 644), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5203 {"evfsnabs", VX (4, 645), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5204 {"evfsneg", VX (4, 646), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5205 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5206 {"vcmpgtuq", VXR(4, 647,0), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5207 {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK
, PPCEFS2
, 0, {RD
, RA
}},
5208 {"vmuleuw", VX (4, 648), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5209 {"evfsmul", VX (4, 648), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5210 {"vmulhuw", VX (4, 649), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5211 {"evfsdiv", VX (4, 649), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5212 {"evfsnmadd", VX (4, 650), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5213 {"vrfip", VX (4, 650), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5214 {"vdiveuw", VX (4, 651), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5215 {"evfsnmsub", VX (4, 651), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5216 {"evfscmpgt", VX (4, 652), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5217 {"vspltw", VX (4, 652), VXUIMM2_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM2
}},
5218 {"vextractuw", VX (4, 653), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
5219 {"evfscmplt", VX (4, 653), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5220 {"evfscmpeq", VX (4, 654), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5221 {"vupklsb", VX (4, 654), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5222 {"vinswlx", VX (4, 655), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
5223 {"evfscfui", VX (4, 656), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
5224 {"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
5225 {"evfscfsi", VX (4, 657), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
5226 {"evfscfuf", VX (4, 658), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
5227 {"evfscfsf", VX (4, 659), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
5228 {"evfsctui", VX (4, 660), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
5229 {"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
5230 {"evfsctsi", VX (4, 661), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
5231 {"evfsctuf", VX (4, 662), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
5232 {"evfsctsf", VX (4, 663), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
5233 {"evfsctuiz", VX (4, 664), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
5234 {"put", APU(4, 332,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
5235 {"evfsctsiz", VX (4, 666), VX_MASK
, PPCSPE
, 0, {RS
, RB
}},
5236 {"evfststgt", VX (4, 668), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5237 {"evfststlt", VX (4, 669), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5238 {"evfststeq", VX (4, 670), VX_MASK
, PPCSPE
, 0, {CRFD
, RA
, RB
}},
5239 {"evfsmax", VX (4, 672), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5240 {"evfsmin", VX (4, 673), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5241 {"evfsaddsub", VX (4, 674), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5242 {"evfssubadd", VX (4, 675), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5243 {"evfssum", VX (4, 676), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5244 {"evfsdiff", VX (4, 677), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5245 {"evfssumdiff", VX (4, 678), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5246 {"evfsdiffsum", VX (4, 679), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5247 {"evfsaddx", VX (4, 680), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5248 {"evfssubx", VX (4, 681), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5249 {"evfsaddsubx", VX (4, 682), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5250 {"evfssubaddx", VX (4, 683), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5251 {"evfsmulx", VX (4, 684), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5252 {"evfsmule", VX (4, 686), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5253 {"evfsmulo", VX (4, 687), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5254 {"efsmax", VX (4, 688), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5255 {"efsmin", VX (4, 689), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5256 {"efdmax", VX (4, 696), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5257 {"cput", APU(4, 348,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
5258 {"efdmin", VX (4, 697), VX_MASK
, PPCEFS2
, 0, {RD
, RA
, RB
}},
5259 {"efsadd", VX (4, 704), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5260 {"evsadd", VX (4, 704), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5261 {"efssub", VX (4, 705), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5262 {"evssub", VX (4, 705), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5263 {"efsmadd", VX (4, 706), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
5264 {"vminud", VX (4, 706), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5265 {"efsmsub", VX (4, 707), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
5266 {"efsabs", VX (4, 708), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
5267 {"evsabs", VX (4, 708), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
5268 {"vsr", VX (4, 708), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5269 {"efsnabs", VX (4, 709), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
5270 {"evsnabs", VX (4, 709), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
5271 {"efsneg", VX (4, 710), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
5272 {"evsneg", VX (4, 710), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
5273 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5274 {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK
,PPCEFS2
, 0, {RD
, RA
}},
5275 {"vcmpgtud", VXR(4, 711,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5276 {"vmuleud", VX (4, 712), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5277 {"efsmul", VX (4, 712), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5278 {"evsmul", VX (4, 712), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5279 {"vmulhud", VX (4, 713), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5280 {"efsdiv", VX (4, 713), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5281 {"evsdiv", VX (4, 713), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5282 {"efsnmadd", VX (4, 714), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
5283 {"vrfim", VX (4, 714), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5284 {"vdiveud", VX (4, 715), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5285 {"efsnmsub", VX (4, 715), VX_MASK
, PPCEFS2
, 0, {RS
, RA
, RB
}},
5286 {"efscmpgt", VX (4, 716), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5287 {"evscmpgt", VX (4, 716), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5288 {"vextractd", VX (4, 717), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
5289 {"efscmplt", VX (4, 717), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5290 {"evsgmplt", VX (4, 717), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5291 {"efscmpeq", VX (4, 718), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5292 {"evsgmpeq", VX (4, 718), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5293 {"vupklsh", VX (4, 718), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5294 {"vinsdlx", VX (4, 719), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
5295 {"efscfd", VX (4, 719), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5296 {"efscfui", VX (4, 720), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5297 {"evscfui", VX (4, 720), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5298 {"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
5299 {"efscfsi", VX (4, 721), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5300 {"evscfsi", VX (4, 721), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5301 {"efscfuf", VX (4, 722), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5302 {"evscfuf", VX (4, 722), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5303 {"efscfsf", VX (4, 723), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5304 {"evscfsf", VX (4, 723), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5305 {"efsctui", VX (4, 724), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5306 {"evsctui", VX (4, 724), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5307 {"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
5308 {"efsctsi", VX (4, 725), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5309 {"evsctsi", VX (4, 725), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5310 {"efsctuf", VX (4, 726), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5311 {"evsctuf", VX (4, 726), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5312 {"efsctsf", VX (4, 727), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5313 {"evsctsf", VX (4, 727), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5314 {"efsctuiz", VX (4, 728), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5315 {"evsctuiz", VX (4, 728), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5316 {"nput", APU(4, 364,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
5317 {"efsctsiz", VX (4, 730), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5318 {"evsctsiz", VX (4, 730), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5319 {"efststgt", VX (4, 732), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5320 {"evststgt", VX (4, 732), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5321 {"efststlt", VX (4, 733), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5322 {"evststlt", VX (4, 733), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5323 {"efststeq", VX (4, 734), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5324 {"evststeq", VX (4, 734), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5325 {"efdadd", VX (4, 736), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5326 {"efdsub", VX (4, 737), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5327 {"efdmadd", VX (4, 738), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
5328 {"efdcfuid", VX (4, 738), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
5329 {"efdmsub", VX (4, 739), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
5330 {"efdcfsid", VX (4, 739), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
5331 {"efdabs", VX (4, 740), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
5332 {"efdnabs", VX (4, 741), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
5333 {"efdneg", VX (4, 742), VX_MASK
, PPCEFS
, 0, {RS
, RA
}},
5334 {"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK
, PPCEFS2
, 0, {RD
, RA
}},
5335 {"efdmul", VX (4, 744), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5336 {"efddiv", VX (4, 745), VX_MASK
, PPCEFS
, 0, {RS
, RA
, RB
}},
5337 {"efdnmadd", VX (4, 746), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
5338 {"efdctuidz", VX (4, 746), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
5339 {"efdnmsub", VX (4, 747), VX_MASK
, PPCEFS2
, E500
|E500MC
, {RD
, RA
, RB
}},
5340 {"efdctsidz", VX (4, 747), VX_MASK
, E500
|E500MC
,0, {RS
, RB
}},
5341 {"efdcmpgt", VX (4, 748), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5342 {"efdcmplt", VX (4, 749), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5343 {"efdcmpeq", VX (4, 750), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5344 {"efdcfs", VX (4, 751), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5345 {"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
5346 {"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
5347 {"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
5348 {"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
5349 {"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
5350 {"efdcfuf", VX (4, 754), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5351 {"efdcfsf", VX (4, 755), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5352 {"efdctui", VX (4, 756), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5353 {"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK
, PPCEFS2
, 0, {RD
, RB
}},
5354 {"efdctsi", VX (4, 757), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5355 {"efdctuf", VX (4, 758), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5356 {"efdctsf", VX (4, 759), VX_MASK
, PPCEFS
, 0, {RS
, RB
}},
5357 {"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
5358 {"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
5359 {"ncput", APU(4, 380,0), APU_RT_MASK
, PPC405
, 0, {RA
, FSL
}},
5360 {"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK
, PPCEFS
, 0, {RS
, RB
}},
5361 {"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK
, PPCEFS
, E500
|E500MC
, {RS
, RB
}},
5362 {"efdtstgt", VX (4, 764), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5363 {"efdtstlt", VX (4, 765), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5364 {"efdtsteq", VX (4, 766), VX_MASK
, PPCEFS
, 0, {CRFD
, RA
, RB
}},
5365 {"evlddx", VX (4, 768), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5366 {"vaddsbs", VX (4, 768), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5367 {"evldd", VX (4, 769), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
5368 {"evldwx", VX (4, 770), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5369 {"vminsb", VX (4, 770), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5370 {"evldw", VX (4, 771), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
5371 {"evldhx", VX (4, 772), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5372 {"vsrab", VX (4, 772), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5373 {"vsraq", VX (4, 773), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5374 {"evldh", VX (4, 773), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
5375 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5376 {"evlhhesplatx",VX (4, 776), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5377 {"vmulesb", VX (4, 776), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5378 {"evlhhesplat", VX (4, 777), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
5379 {"vcfux", VX (4, 778), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
5380 {"vcuxwfp", VX (4, 778), VX_MASK
, PPCVEC
, EXT
, {VD
, VB
, UIMM
}},
5381 {"vdivesq", VX (4, 779), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5382 {"evlhhousplatx",VX(4, 780), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5383 {"vspltisb", VX (4, 780), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
5384 {"vinsertb", VX (4, 781), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
5385 {"evlhhousplat",VX (4, 781), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
5386 {"evlhhossplatx",VX(4, 782), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5387 {"vpkpx", VX (4, 782), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5388 {"vinsbrx", VX (4, 783), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
5389 {"evlhhossplat",VX (4, 783), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_2
, RA
}},
5390 {"mullhwu", XRC(4, 392,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5391 {"evlwhex", VX (4, 784), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5392 {"mullhwu.", XRC(4, 392,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5393 {"evlwhe", VX (4, 785), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
5394 {"evlwhoux", VX (4, 788), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5395 {"evlwhou", VX (4, 789), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
5396 {"evlwhosx", VX (4, 790), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5397 {"evlwhos", VX (4, 791), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
5398 {"maclhwu", XO (4, 396,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5399 {"evlwwsplatx", VX (4, 792), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5400 {"maclhwu.", XO (4, 396,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5401 {"evlwwsplat", VX (4, 793), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
5402 {"evlwhsplatx", VX (4, 796), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5403 {"evlwhsplat", VX (4, 797), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
5404 {"evstddx", VX (4, 800), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5405 {"evstdd", VX (4, 801), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
5406 {"evstdwx", VX (4, 802), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5407 {"evstdw", VX (4, 803), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
5408 {"evstdhx", VX (4, 804), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5409 {"evstdh", VX (4, 805), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_8
, RA
}},
5410 {"evstwhex", VX (4, 816), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5411 {"evstwhe", VX (4, 817), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
5412 {"evstwhox", VX (4, 820), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5413 {"evstwho", VX (4, 821), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
5414 {"evstwwex", VX (4, 824), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5415 {"evstwwe", VX (4, 825), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
5416 {"evstwwox", VX (4, 828), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5417 {"evstwwo", VX (4, 829), VX_MASK
, PPCSPE
, 0, {RS
, EVUIMM_4
, RA
}},
5418 {"vaddshs", VX (4, 832), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5419 {"bcdcpsgn.", VX (4, 833), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5420 {"vminsh", VX (4, 834), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5421 {"vsrah", VX (4, 836), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5422 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5423 {"vmulesh", VX (4, 840), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5424 {"vcfsx", VX (4, 842), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
5425 {"vcsxwfp", VX (4, 842), VX_MASK
, PPCVEC
, EXT
, {VD
, VB
, UIMM
}},
5426 {"vspltish", VX (4, 844), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
5427 {"vinserth", VX (4, 845), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
5428 {"vupkhpx", VX (4, 846), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5429 {"vinshrx", VX (4, 847), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
5430 {"mullhw", XRC(4, 424,0), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5431 {"mullhw.", XRC(4, 424,1), X_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5432 {"maclhw", XO (4, 428,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5433 {"maclhw.", XO (4, 428,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5434 {"nmaclhw", XO (4, 430,0,0),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5435 {"nmaclhw.", XO (4, 430,0,1),XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5436 {"vaddsws", VX (4, 896), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5437 {"vminsw", VX (4, 898), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5438 {"vsraw", VX (4, 900), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5439 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5440 {"vcmpgtsq", VXR(4, 903,0), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5441 {"vmulesw", VX (4, 904), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5442 {"vmulhsw", VX (4, 905), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5443 {"vctuxs", VX (4, 906), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
5444 {"vcfpuxws", VX (4, 906), VX_MASK
, PPCVEC
, EXT
, {VD
, VB
, UIMM
}},
5445 {"vdivesw", VX (4, 907), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5446 {"vspltisw", VX (4, 908), VXVB_MASK
, PPCVEC
, 0, {VD
, SIMM
}},
5447 {"vinsertw", VX (4, 909), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
5448 {"vinswrx", VX (4, 911), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
5449 {"maclhwsu", XO (4, 460,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5450 {"maclhwsu.", XO (4, 460,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5451 {"vminsd", VX (4, 962), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5452 {"vsrad", VX (4, 964), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5453 {"vcmpbfp", VXR(4, 966,0), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5454 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5455 {"vmulesd", VX (4, 968), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5456 {"vmulhsd", VX (4, 969), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5457 {"vctsxs", VX (4, 970), VX_MASK
, PPCVEC
, 0, {VD
, VB
, UIMM
}},
5458 {"vcfpsxws", VX (4, 970), VX_MASK
, PPCVEC
, EXT
, {VD
, VB
, UIMM
}},
5459 {"vdivesd", VX (4, 971), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5460 {"vinsertd", VX (4, 973), VXUIMM4_MASK
, PPCVEC3
, 0, {VD
, VB
, UIMM4
}},
5461 {"vupklpx", VX (4, 974), VXVA_MASK
, PPCVEC
, 0, {VD
, VB
}},
5462 {"vinsdrx", VX (4, 975), VX_MASK
, POWER10
, 0, {VD
, RA
, RB
}},
5463 {"maclhws", XO (4, 492,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5464 {"maclhws.", XO (4, 492,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5465 {"nmaclhws", XO (4, 494,0,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5466 {"nmaclhws.", XO (4, 494,0,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5467 {"vsububm", VX (4,1024), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5468 {"bcdadd.", VX (4,1025), VXPS_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, PS
}},
5469 {"vavgub", VX (4,1026), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5470 {"vabsdub", VX (4,1027), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5471 {"evmhessf", VX (4,1027), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5472 {"vand", VX (4,1028), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5473 {"vcmpequb.", VXR(4, 6,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5474 {"vcmpneb.", VXR(4, 7,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5475 {"udi0fcm.", APU(4, 515,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5476 {"udi0fcm", APU(4, 515,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5477 {"evmhossf", VX (4,1031), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5478 {"vpmsumb", VX (4,1032), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5479 {"evmheumi", VX (4,1032), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5480 {"evmhesmi", VX (4,1033), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5481 {"vmaxfp", VX (4,1034), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5482 {"evmhesmf", VX (4,1035), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5483 {"evmhoumi", VX (4,1036), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5484 {"vslo", VX (4,1036), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5485 {"vstribl.", VXVA(4,1037,0), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
5486 {"vstribr.", VXVA(4,1037,1), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
5487 {"vstrihl.", VXVA(4,1037,2), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
5488 {"vstrihr.", VXVA(4,1037,3), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
5489 {"evmhosmi", VX (4,1037), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5490 {"evmhosmf", VX (4,1039), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5491 {"machhwuo", XO (4, 12,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5492 {"machhwuo.", XO (4, 12,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5493 {"ps_merge00", XOPS(4,528,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
5494 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
5495 {"evmhessfa", VX (4,1059), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5496 {"evmhossfa", VX (4,1063), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5497 {"evmheumia", VX (4,1064), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5498 {"evmhesmia", VX (4,1065), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5499 {"evmhesmfa", VX (4,1067), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5500 {"evmhoumia", VX (4,1068), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5501 {"evmhosmia", VX (4,1069), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5502 {"evmhosmfa", VX (4,1071), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5503 {"vsubuhm", VX (4,1088), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5504 {"bcdsub.", VX (4,1089), VXPS_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
, PS
}},
5505 {"vavguh", VX (4,1090), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5506 {"evmwlssf", VX (4,1091), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5507 {"vabsduh", VX (4,1091), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5508 {"vandc", VX (4,1092), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5509 {"vcmpequh.", VXR(4, 70,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5510 {"udi1fcm.", APU(4, 547,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5511 {"udi1fcm", APU(4, 547,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5512 {"vcmpneh.", VXR(4, 71,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5513 {"evmwhssf", VX (4,1095), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5514 {"vpmsumh", VX (4,1096), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5515 {"evmwlumi", VX (4,1096), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5516 {"vminfp", VX (4,1098), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5517 {"evmwlsmf", VX (4,1099), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5518 {"evmwhumi", VX (4,1100), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5519 {"vsro", VX (4,1100), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5520 {"evmwhsmi", VX (4,1101), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5521 {"vpkudum", VX (4,1102), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5522 {"evmwhsmf", VX (4,1103), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5523 {"evmwssf", VX (4,1107), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5524 {"machhwo", XO (4, 44,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5525 {"evmwumi", VX (4,1112), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5526 {"machhwo.", XO (4, 44,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5527 {"evmwsmi", VX (4,1113), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5528 {"evmwsmf", VX (4,1115), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5529 {"nmachhwo", XO (4, 46,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5530 {"nmachhwo.", XO (4, 46,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5531 {"ps_merge01", XOPS(4,560,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
5532 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
5533 {"evmwlssfa", VX (4,1123), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5534 {"evmwhssfa", VX (4,1127), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5535 {"evmwlumia", VX (4,1128), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5536 {"evmwlsmfa", VX (4,1131), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5537 {"evmwhumia", VX (4,1132), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5538 {"evmwhsmia", VX (4,1133), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5539 {"evmwhsmfa", VX (4,1135), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5540 {"evmwssfa", VX (4,1139), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5541 {"evmwumia", VX (4,1144), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5542 {"evmwsmia", VX (4,1145), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5543 {"evmwsmfa", VX (4,1147), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5544 {"vsubuwm", VX (4,1152), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5545 {"bcdus.", VX (4,1153), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5546 {"vavguw", VX (4,1154), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5547 {"vabsduw", VX (4,1155), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5548 {"vmr", VX (4,1156), VX_MASK
, PPCVEC
, EXT
, {VD
, VAB
}},
5549 {"vor", VX (4,1156), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5550 {"vcmpnew.", VXR(4, 135,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5551 {"vpmsumw", VX (4,1160), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5552 {"vcmpequw.", VXR(4, 134,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5553 {"udi2fcm.", APU(4, 579,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5554 {"udi2fcm", APU(4, 579,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5555 {"machhwsuo", XO (4, 76,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5556 {"machhwsuo.", XO (4, 76,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5557 {"ps_merge10", XOPS(4,592,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
5558 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
5559 {"vsubudm", VX (4,1216), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5560 {"evaddusiaaw", VX (4,1216), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5561 {"bcds.", VX (4,1217), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
5562 {"evaddssiaaw", VX (4,1217), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5563 {"evsubfusiaaw",VX (4,1218), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5564 {"evsubfssiaaw",VX (4,1219), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5565 {"evmra", VX (4,1220), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5566 {"vxor", VX (4,1220), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5567 {"evdivws", VX (4,1222), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5568 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5569 {"udi3fcm.", APU(4, 611,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5570 {"vcmpequd.", VXR(4, 199,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5571 {"udi3fcm", APU(4, 611,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5572 {"evdivwu", VX (4,1223), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5573 {"vpmsumd", VX (4,1224), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5574 {"evaddumiaaw", VX (4,1224), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5575 {"evaddsmiaaw", VX (4,1225), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5576 {"evsubfumiaaw",VX (4,1226), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5577 {"evsubfsmiaaw",VX (4,1227), VX_MASK
, PPCSPE
, 0, {RS
, RA
}},
5578 {"vgnb", VX (4,1228), VX_MASK
, POWER10
, 0, {RT
, VB
, UIMM3
}},
5579 {"vpkudus", VX (4,1230), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5580 {"machhwso", XO (4, 108,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5581 {"machhwso.", XO (4, 108,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5582 {"nmachhwso", XO (4, 110,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5583 {"nmachhwso.", XO (4, 110,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5584 {"ps_merge11", XOPS(4,624,0), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
5585 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK
, PPCPS
, 0, {FRT
, FRA
, FRB
}},
5586 {"vsubuqm", VX (4,1280), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5587 {"evmheusiaaw", VX (4,1280), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5588 {"bcdtrunc.", VX (4,1281), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
5589 {"evmhessiaaw", VX (4,1281), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5590 {"vavgsb", VX (4,1282), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5591 {"evmhessfaaw", VX (4,1283), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5592 {"evmhousiaaw", VX (4,1284), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5593 {"vnot", VX (4,1284), VX_MASK
, PPCVEC
, EXT
, {VD
, VAB
}},
5594 {"vnor", VX (4,1284), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5595 {"evmhossiaaw", VX (4,1285), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5596 {"udi4fcm.", APU(4, 643,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5597 {"udi4fcm", APU(4, 643,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5598 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5599 {"evmhossfaaw", VX (4,1287), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5600 {"evmheumiaaw", VX (4,1288), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5601 {"vcipher", VX (4,1288), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5602 {"vcipherlast", VX (4,1289), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5603 {"evmhesmiaaw", VX (4,1289), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5604 {"evmhesmfaaw", VX (4,1291), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5605 {"vgbbd", VX (4,1292), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5606 {"evmhoumiaaw", VX (4,1292), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5607 {"evmhosmiaaw", VX (4,1293), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5608 {"evmhosmfaaw", VX (4,1295), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5609 {"macchwuo", XO (4, 140,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5610 {"macchwuo.", XO (4, 140,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5611 {"evmhegumiaa", VX (4,1320), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5612 {"evmhegsmiaa", VX (4,1321), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5613 {"evmhegsmfaa", VX (4,1323), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5614 {"evmhogumiaa", VX (4,1324), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5615 {"evmhogsmiaa", VX (4,1325), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5616 {"evmhogsmfaa", VX (4,1327), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5617 {"vsubcuq", VX (4,1344), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5618 {"evmwlusiaaw", VX (4,1344), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5619 {"bcdutrunc.", VX (4,1345), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5620 {"evmwlssiaaw", VX (4,1345), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5621 {"vavgsh", VX (4,1346), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5622 {"evmwlssfaaw", VX (4,1347), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5623 {"evmwhusiaa", VX (4,1348), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5624 {"vorc", VX (4,1348), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5625 {"evmwhssmaa", VX (4,1349), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5626 {"udi5fcm.", APU(4, 675,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5627 {"udi5fcm", APU(4, 675,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5628 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5629 {"evmwhssfaa", VX (4,1351), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5630 {"vncipher", VX (4,1352), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5631 {"evmwlumiaaw", VX (4,1352), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5632 {"vncipherlast",VX (4,1353), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5633 {"evmwlsmiaaw", VX (4,1353), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5634 {"evmwlsmfaaw", VX (4,1355), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5635 {"evmwhumiaa", VX (4,1356), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5636 {"vbpermq", VX (4,1356), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5637 {"vcfuged", VX (4,1357), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5638 {"evmwhsmiaa", VX (4,1357), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5639 {"vpksdus", VX (4,1358), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5640 {"evmwhsmfaa", VX (4,1359), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5641 {"evmwssfaa", VX (4,1363), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5642 {"macchwo", XO (4, 172,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5643 {"evmwumiaa", VX (4,1368), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5644 {"macchwo.", XO (4, 172,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5645 {"evmwsmiaa", VX (4,1369), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5646 {"evmwsmfaa", VX (4,1371), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5647 {"nmacchwo", XO (4, 174,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5648 {"nmacchwo.", XO (4, 174,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5649 {"evmwhgumiaa", VX (4,1380), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5650 {"evmwhgsmiaa", VX (4,1381), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5651 {"evmwhgssfaa", VX (4,1383), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5652 {"evmwhgsmfaa", VX (4,1391), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5653 {"evmheusianw", VX (4,1408), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5654 {"vsubcuw", VX (4,1408), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5655 {"evmhessianw", VX (4,1409), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5656 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5657 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
5658 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
5659 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5660 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
5661 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
5662 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK
, PPCVEC3
, 0, {VD
, VB
, PS
}},
5663 {"vavgsw", VX (4,1410), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5664 {"evmhessfanw", VX (4,1411), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5665 {"vnand", VX (4,1412), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5666 {"evmhousianw", VX (4,1412), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5667 {"evmhossianw", VX (4,1413), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5668 {"udi6fcm.", APU(4, 707,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5669 {"udi6fcm", APU(4, 707,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5670 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5671 {"evmhossfanw", VX (4,1415), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5672 {"evmheumianw", VX (4,1416), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5673 {"evmhesmianw", VX (4,1417), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5674 {"evmhesmfanw", VX (4,1419), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5675 {"evmhoumianw", VX (4,1420), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5676 {"vpextd", VX (4,1421), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5677 {"evmhosmianw", VX (4,1421), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5678 {"evmhosmfanw", VX (4,1423), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5679 {"macchwsuo", XO (4, 204,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5680 {"macchwsuo.", XO (4, 204,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5681 {"evmhegumian", VX (4,1448), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5682 {"evmhegsmian", VX (4,1449), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5683 {"evmhegsmfan", VX (4,1451), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5684 {"evmhogumian", VX (4,1452), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5685 {"evmhogsmian", VX (4,1453), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5686 {"evmhogsmfan", VX (4,1455), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5687 {"evmwlusianw", VX (4,1472), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5688 {"bcdsr.", VX (4,1473), VXPS_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
, PS
}},
5689 {"evmwlssianw", VX (4,1473), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5690 {"evmwlssfanw", VX (4,1475), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5691 {"evmwhusian", VX (4,1476), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5692 {"vsld", VX (4,1476), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5693 {"evmwhssian", VX (4,1477), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5694 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5695 {"udi7fcm.", APU(4, 739,0), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5696 {"udi7fcm", APU(4, 739,1), APU_MASK
, PPC405
|PPC440
, 0, {URT
, URA
, URB
}},
5697 {"vcmpequq.", VXR(4, 455,1), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5698 {"evmwhssfan", VX (4,1479), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5699 {"vsbox", VX (4,1480), VXVB_MASK
, PPCVEC2
, 0, {VD
, VA
}},
5700 {"evmwlumianw", VX (4,1480), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5701 {"evmwlsmianw", VX (4,1481), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5702 {"evmwlsmfanw", VX (4,1483), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5703 {"evmwhumian", VX (4,1484), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5704 {"vbpermd", VX (4,1484), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5705 {"vpdepd", VX (4,1485), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5706 {"evmwhsmian", VX (4,1485), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5707 {"vpksdss", VX (4,1486), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5708 {"evmwhsmfan", VX (4,1487), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5709 {"evmwssfan", VX (4,1491), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5710 {"macchwso", XO (4, 236,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5711 {"evmwumian", VX (4,1496), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5712 {"macchwso.", XO (4, 236,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5713 {"evmwsmian", VX (4,1497), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5714 {"evmwsmfan", VX (4,1499), VX_MASK
, PPCSPE
, 0, {RS
, RA
, RB
}},
5715 {"evmwhgumian", VX (4,1508), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5716 {"evmwhgsmian", VX (4,1509), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5717 {"evmwhgssfan", VX (4,1511), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5718 {"evmwhgsmfan", VX (4,1519), VX_MASK
, PPCSPE
, 0, {RD
, RA
, RB
}},
5719 {"nmacchwso", XO (4, 238,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5720 {"nmacchwso.", XO (4, 238,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5721 {"vsububs", VX (4,1536), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5722 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK
, PPCVEC3
, 0, {RT
, VB
}},
5723 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK
, PPCVEC3
, 0, {RT
, VB
}},
5724 {"vnegw", VXVA(4,1538,6), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5725 {"vnegd", VXVA(4,1538,7), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5726 {"vprtybw", VXVA(4,1538,8), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5727 {"vprtybd", VXVA(4,1538,9), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5728 {"vprtybq", VXVA(4,1538,10), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5729 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5730 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5731 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5732 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5733 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5734 {"vextsd2q", VXVA(4,1538,27), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
5735 {"vctzb", VXVA(4,1538,28), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5736 {"vctzh", VXVA(4,1538,29), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5737 {"vctzw", VXVA(4,1538,30), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5738 {"vctzd", VXVA(4,1538,31), VXVA_MASK
, PPCVEC3
, 0, {VD
, VB
}},
5739 {"mfvscr", VX (4,1540), VXVAVB_MASK
, PPCVEC
, 0, {VD
}},
5740 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5741 {"udi8fcm.", APU(4, 771,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5742 {"udi8fcm", APU(4, 771,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5743 {"vsum4ubs", VX (4,1544), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5744 {"vmoduq", VX (4,1547), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5745 {"vextublx", VX (4,1549), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
5746 {"vsubuhs", VX (4,1600), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5748 {"vexpandbm", VXVA(4,1602,0), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
5749 {"vexpandhm", VXVA(4,1602,1), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
5750 {"vexpandwm", VXVA(4,1602,2), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
5751 {"vexpanddm", VXVA(4,1602,3), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
5752 {"vexpandqm", VXVA(4,1602,4), VXVA_MASK
, POWER10
, 0, {VD
, VB
}},
5753 {"vextractbm", VXVA(4,1602,8), VXVA_MASK
, POWER10
, 0, {RT
, VB
}},
5754 {"vextracthm", VXVA(4,1602,9), VXVA_MASK
, POWER10
, 0, {RT
, VB
}},
5755 {"vextractwm", VXVA(4,1602,10), VXVA_MASK
, POWER10
, 0, {RT
, VB
}},
5756 {"vextractdm", VXVA(4,1602,11), VXVA_MASK
, POWER10
, 0, {RT
, VB
}},
5757 {"vextractqm", VXVA(4,1602,12), VXVA_MASK
, POWER10
, 0, {RT
, VB
}},
5758 {"mtvsrbm", VXVA(4,1602,16), VXVA_MASK
, POWER10
, 0, {VD
, RB
}},
5759 {"mtvsrhm", VXVA(4,1602,17), VXVA_MASK
, POWER10
, 0, {VD
, RB
}},
5760 {"mtvsrwm", VXVA(4,1602,18), VXVA_MASK
, POWER10
, 0, {VD
, RB
}},
5761 {"mtvsrdm", VXVA(4,1602,19), VXVA_MASK
, POWER10
, 0, {VD
, RB
}},
5762 {"mtvsrqm", VXVA(4,1602,20), VXVA_MASK
, POWER10
, 0, {VD
, RB
}},
5763 {"vcntmbb", VXVA(4,1602,24), VXVAM_MASK
, POWER10
, 0, {RT
, VB
, MP
}},
5764 {"vcntmbh", VXVA(4,1602,26), VXVAM_MASK
, POWER10
, 0, {RT
, VB
, MP
}},
5765 {"vcntmbw", VXVA(4,1602,28), VXVAM_MASK
, POWER10
, 0, {RT
, VB
, MP
}},
5766 {"vcntmbd", VXVA(4,1602,30), VXVAM_MASK
, POWER10
, 0, {RT
, VB
, MP
}},
5768 {"mtvscr", VX (4,1604), VXVDVA_MASK
, PPCVEC
, 0, {VB
}},
5769 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5770 {"vsum4shs", VX (4,1608), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5771 {"udi9fcm.", APU(4, 804,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5772 {"udi9fcm", APU(4, 804,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5773 {"vextuhlx", VX (4,1613), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
5774 {"vupkhsw", VX (4,1614), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5775 {"vsubuws", VX (4,1664), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5776 {"vshasigmaw", VX (4,1666), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, ST
, SIX
}},
5777 {"veqv", VX (4,1668), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5778 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5779 {"udi10fcm.", APU(4, 835,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5780 {"vcmpgtuq.", VXR(4, 647,1), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5781 {"udi10fcm", APU(4, 835,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5782 {"vsum2sws", VX (4,1672), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5783 {"vmoduw", VX (4,1675), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5784 {"vmrgow", VX (4,1676), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5785 {"vextuwlx", VX (4,1677), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
5786 {"vshasigmad", VX (4,1730), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, ST
, SIX
}},
5787 {"vsrd", VX (4,1732), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5788 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5789 {"udi11fcm.", APU(4, 867,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5790 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5791 {"udi11fcm", APU(4, 867,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5792 {"vmodud", VX (4,1739), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5793 {"vupklsw", VX (4,1742), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5794 {"vsubsbs", VX (4,1792), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5795 {"vclzb", VX (4,1794), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5796 {"vpopcntb", VX (4,1795), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5797 {"vsrv", VX (4,1796), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5798 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5799 {"udi12fcm.", APU(4, 899,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5800 {"udi12fcm", APU(4, 899,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5801 {"vsum4sbs", VX (4,1800), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5802 {"vmodsq", VX (4,1803), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5803 {"vextubrx", VX (4,1805), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
5804 {"maclhwuo", XO (4, 396,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5805 {"maclhwuo.", XO (4, 396,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5806 {"vsubshs", VX (4,1856), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5807 {"vclzh", VX (4,1858), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5808 {"vpopcnth", VX (4,1859), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5809 {"vslv", VX (4,1860), VX_MASK
, PPCVEC3
, 0, {VD
, VA
, VB
}},
5810 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5811 {"vextuhrx", VX (4,1869), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
5812 {"udi13fcm.", APU(4, 931,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5813 {"udi13fcm", APU(4, 931,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5814 {"maclhwo", XO (4, 428,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5815 {"maclhwo.", XO (4, 428,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5816 {"nmaclhwo", XO (4, 430,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5817 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5818 {"vsubsws", VX (4,1920), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5819 {"vclzw", VX (4,1922), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5820 {"vpopcntw", VX (4,1923), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5821 {"vclzdm", VX (4,1924), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5822 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5823 {"udi14fcm.", APU(4, 963,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5824 {"vcmpgtsq.", VXR(4, 903,1), VXR_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5825 {"udi14fcm", APU(4, 963,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5826 {"vsumsws", VX (4,1928), VX_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5827 {"vmodsw", VX (4,1931), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5828 {"vmrgew", VX (4,1932), VX_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5829 {"vextuwrx", VX (4,1933), VX_MASK
, PPCVEC3
, 0, {RT
, RA
, VB
}},
5830 {"maclhwsuo", XO (4, 460,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5831 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5832 {"vclzd", VX (4,1986), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5833 {"vpopcntd", VX (4,1987), VXVA_MASK
, PPCVEC2
, 0, {VD
, VB
}},
5834 {"vctzdm", VX (4,1988), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5835 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK
, PPCVEC
, 0, {VD
, VA
, VB
}},
5836 {"udi15fcm.", APU(4, 995,0), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5837 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK
, PPCVEC2
, 0, {VD
, VA
, VB
}},
5838 {"udi15fcm", APU(4, 995,1), APU_MASK
, PPC440
, 0, {URT
, URA
, URB
}},
5839 {"vmodsd", VX (4,1995), VX_MASK
, POWER10
, 0, {VD
, VA
, VB
}},
5840 {"maclhwso", XO (4, 492,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5841 {"maclhwso.", XO (4, 492,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5842 {"nmaclhwso", XO (4, 494,1,0), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5843 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK
, MULHW
, 0, {RT
, RA
, RB
}},
5844 {"dcbz_l", X (4,1014), XRT_MASK
, PPCPS
, 0, {RA
, RB
}},
5846 {"lxvp", DQXP(6,0), DQXP_MASK
, POWER10
, PPCVLE
, {XTP
, DQ
, RA0
}},
5847 {"stxvp", DQXP(6,1), DQXP_MASK
, POWER10
, PPCVLE
, {XTP
, DQ
, RA0
}},
5849 {"mulli", OP(7), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
5850 {"muli", OP(7), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
5852 {"subfic", OP(8), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
5853 {"sfi", OP(8), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
5855 {"dozi", OP(9), OP_MASK
, M601
, PPCVLE
, {RT
, RA
, SI
}},
5857 {"cmplwi", OPL(10,0), OPL_MASK
, PPCCOM
, PPCVLE
|EXT
, {OBF
, RA
, UISIGNOPT
}},
5858 {"cmpldi", OPL(10,1), OPL_MASK
, PPC64
, PPCVLE
|EXT
, {OBF
, RA
, UISIGNOPT
}},
5859 {"cmpli", OP(10), OP_MASK
, PPC
, PPCVLE
, {BF
, L32OPT
, RA
, UISIGNOPT
}},
5860 {"cmpli", OP(10), OP_MASK
, PWRCOM
, PPC
|PPCVLE
, {BF
, RA
, UISIGNOPT
}},
5862 {"cmpwi", OPL(11,0), OPL_MASK
, PPCCOM
, PPCVLE
|EXT
, {OBF
, RA
, SI
}},
5863 {"cmpdi", OPL(11,1), OPL_MASK
, PPC64
, PPCVLE
|EXT
, {OBF
, RA
, SI
}},
5864 {"cmpi", OP(11), OP_MASK
, PPC
, PPCVLE
, {BF
, L32OPT
, RA
, SI
}},
5865 {"cmpi", OP(11), OP_MASK
, PWRCOM
, PPC
|PPCVLE
, {BF
, RA
, SI
}},
5867 {"addic", OP(12), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
5868 {"ai", OP(12), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
5869 {"subic", OP(12), OP_MASK
, PPCCOM
, PPCVLE
|EXT
, {RT
, RA
, NSI
}},
5871 {"addic.", OP(13), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA
, SI
}},
5872 {"ai.", OP(13), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA
, SI
}},
5873 {"subic.", OP(13), OP_MASK
, PPCCOM
, PPCVLE
|EXT
, {RT
, RA
, NSI
}},
5875 {"li", OP(14), DRA_MASK
, PPCCOM
, PPCVLE
|EXT
, {RT
, SI
}},
5876 {"lil", OP(14), DRA_MASK
, PWRCOM
, PPCVLE
|EXT
, {RT
, SI
}},
5877 {"addi", OP(14), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, SI
}},
5878 {"cal", OP(14), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
5879 {"subi", OP(14), OP_MASK
, PPCCOM
, PPCVLE
|EXT
, {RT
, RA0
, NSI
}},
5880 {"la", OP(14), OP_MASK
, PPCCOM
, PPCVLE
|EXT
, {RT
, D
, RA0
}},
5882 {"lis", OP(15), DRA_MASK
, PPCCOM
, PPCVLE
|EXT
, {RT
, SISIGNOPT
}},
5883 {"liu", OP(15), DRA_MASK
, PWRCOM
, PPCVLE
|EXT
, {RT
, SISIGNOPT
}},
5884 {"addis", OP(15), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, RA0
, SISIGNOPT
}},
5885 {"cau", OP(15), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, RA0
, SISIGNOPT
}},
5886 {"subis", OP(15), OP_MASK
, PPCCOM
, PPCVLE
|EXT
, {RT
, RA0
, NSISIGNOPT
}},
5888 {"bdnz-", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDM
}},
5889 {"bdnz+", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDP
}},
5890 {"bdnz", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BD
}},
5891 {"bdn", BBO(16,BODNZ
,0,0), BBOATBI_MASK
, PWRCOM
, PPCVLE
|EXT
, {BD
}},
5892 {"bdnzl-", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDM
}},
5893 {"bdnzl+", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDP
}},
5894 {"bdnzl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BD
}},
5895 {"bdnl", BBO(16,BODNZ
,0,1), BBOATBI_MASK
, PWRCOM
, PPCVLE
|EXT
, {BD
}},
5896 {"bdnza-", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDMA
}},
5897 {"bdnza+", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDPA
}},
5898 {"bdnza", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDA
}},
5899 {"bdna", BBO(16,BODNZ
,1,0), BBOATBI_MASK
, PWRCOM
, PPCVLE
|EXT
, {BDA
}},
5900 {"bdnzla-", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDMA
}},
5901 {"bdnzla+", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDPA
}},
5902 {"bdnzla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDA
}},
5903 {"bdnla", BBO(16,BODNZ
,1,1), BBOATBI_MASK
, PWRCOM
, PPCVLE
|EXT
, {BDA
}},
5904 {"bdz-", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDM
}},
5905 {"bdz+", BBO(16,BODZ
,0,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDP
}},
5906 {"bdz", BBO(16,BODZ
,0,0), BBOATBI_MASK
, COM
, PPCVLE
|EXT
, {BD
}},
5907 {"bdzl-", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDM
}},
5908 {"bdzl+", BBO(16,BODZ
,0,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDP
}},
5909 {"bdzl", BBO(16,BODZ
,0,1), BBOATBI_MASK
, COM
, PPCVLE
|EXT
, {BD
}},
5910 {"bdza-", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDMA
}},
5911 {"bdza+", BBO(16,BODZ
,1,0), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDPA
}},
5912 {"bdza", BBO(16,BODZ
,1,0), BBOATBI_MASK
, COM
, PPCVLE
|EXT
, {BDA
}},
5913 {"bdzla-", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDMA
}},
5914 {"bdzla+", BBO(16,BODZ
,1,1), BBOATBI_MASK
, PPCCOM
, PPCVLE
|EXT
, {BDPA
}},
5915 {"bdzla", BBO(16,BODZ
,1,1), BBOATBI_MASK
, COM
, PPCVLE
|EXT
, {BDA
}},
5917 {"bge-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5918 {"bge+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5919 {"bge", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5920 {"bnl-", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5921 {"bnl+", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5922 {"bnl", BBOCB(16,BOF
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5923 {"bgel-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5924 {"bgel+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5925 {"bgel", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5926 {"bnll-", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5927 {"bnll+", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5928 {"bnll", BBOCB(16,BOF
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5929 {"bgea-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5930 {"bgea+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5931 {"bgea", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5932 {"bnla-", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5933 {"bnla+", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5934 {"bnla", BBOCB(16,BOF
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5935 {"bgela-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5936 {"bgela+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5937 {"bgela", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5938 {"bnlla-", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5939 {"bnlla+", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5940 {"bnlla", BBOCB(16,BOF
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5941 {"ble-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5942 {"ble+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5943 {"ble", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5944 {"bng-", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5945 {"bng+", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5946 {"bng", BBOCB(16,BOF
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5947 {"blel-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5948 {"blel+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5949 {"blel", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5950 {"bngl-", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5951 {"bngl+", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5952 {"bngl", BBOCB(16,BOF
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5953 {"blea-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5954 {"blea+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5955 {"blea", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5956 {"bnga-", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5957 {"bnga+", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5958 {"bnga", BBOCB(16,BOF
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5959 {"blela-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5960 {"blela+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5961 {"blela", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5962 {"bngla-", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5963 {"bngla+", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5964 {"bngla", BBOCB(16,BOF
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5965 {"bne-", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5966 {"bne+", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5967 {"bne", BBOCB(16,BOF
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5968 {"bnel-", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5969 {"bnel+", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5970 {"bnel", BBOCB(16,BOF
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5971 {"bnea-", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5972 {"bnea+", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5973 {"bnea", BBOCB(16,BOF
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5974 {"bnela-", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5975 {"bnela+", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5976 {"bnela", BBOCB(16,BOF
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5977 {"bns-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5978 {"bns+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5979 {"bns", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5980 {"bnu-", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5981 {"bnu+", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5982 {"bnu", BBOCB(16,BOF
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BD
}},
5983 {"bnsl-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5984 {"bnsl+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5985 {"bnsl", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
5986 {"bnul-", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
5987 {"bnul+", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
5988 {"bnul", BBOCB(16,BOF
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BD
}},
5989 {"bnsa-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5990 {"bnsa+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5991 {"bnsa", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5992 {"bnua-", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5993 {"bnua+", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5994 {"bnua", BBOCB(16,BOF
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDA
}},
5995 {"bnsla-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5996 {"bnsla+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
5997 {"bnsla", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
5998 {"bnula-", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
5999 {"bnula+", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6000 {"bnula", BBOCB(16,BOF
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDA
}},
6002 {"blt-", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
6003 {"blt+", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
6004 {"blt", BBOCB(16,BOT
,CBLT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
6005 {"bltl-", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
6006 {"bltl+", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
6007 {"bltl", BBOCB(16,BOT
,CBLT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
6008 {"blta-", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
6009 {"blta+", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6010 {"blta", BBOCB(16,BOT
,CBLT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
6011 {"bltla-", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
6012 {"bltla+", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6013 {"bltla", BBOCB(16,BOT
,CBLT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
6014 {"bgt-", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
6015 {"bgt+", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
6016 {"bgt", BBOCB(16,BOT
,CBGT
,0,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
6017 {"bgtl-", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
6018 {"bgtl+", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
6019 {"bgtl", BBOCB(16,BOT
,CBGT
,0,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
6020 {"bgta-", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
6021 {"bgta+", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6022 {"bgta", BBOCB(16,BOT
,CBGT
,1,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
6023 {"bgtla-", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
6024 {"bgtla+", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6025 {"bgtla", BBOCB(16,BOT
,CBGT
,1,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
6026 {"beq-", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
6027 {"beq+", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
6028 {"beq", BBOCB(16,BOT
,CBEQ
,0,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
6029 {"beql-", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
6030 {"beql+", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
6031 {"beql", BBOCB(16,BOT
,CBEQ
,0,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
6032 {"beqa-", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
6033 {"beqa+", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6034 {"beqa", BBOCB(16,BOT
,CBEQ
,1,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
6035 {"beqla-", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
6036 {"beqla+", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6037 {"beqla", BBOCB(16,BOT
,CBEQ
,1,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
6038 {"bso-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
6039 {"bso+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
6040 {"bso", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
6041 {"bun-", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
6042 {"bun+", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
6043 {"bun", BBOCB(16,BOT
,CBSO
,0,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BD
}},
6044 {"bsol-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
6045 {"bsol+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
6046 {"bsol", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BD
}},
6047 {"bunl-", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDM
}},
6048 {"bunl+", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDP
}},
6049 {"bunl", BBOCB(16,BOT
,CBSO
,0,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BD
}},
6050 {"bsoa-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
6051 {"bsoa+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6052 {"bsoa", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
6053 {"buna-", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
6054 {"buna+", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6055 {"buna", BBOCB(16,BOT
,CBSO
,1,0), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDA
}},
6056 {"bsola-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
6057 {"bsola+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6058 {"bsola", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, COM
, PPCVLE
|EXT
, {CR
, BDA
}},
6059 {"bunla-", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDMA
}},
6060 {"bunla+", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDPA
}},
6061 {"bunla", BBOCB(16,BOT
,CBSO
,1,1), BBOATCB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BDA
}},
6063 {"bdnzf-", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDM
}},
6064 {"bdnzf+", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDP
}},
6065 {"bdnzf", BBO(16,BODNZF
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6066 {"bdnzfl-", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDM
}},
6067 {"bdnzfl+", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDP
}},
6068 {"bdnzfl", BBO(16,BODNZF
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6069 {"bdnzfa-", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDMA
}},
6070 {"bdnzfa+", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDPA
}},
6071 {"bdnzfa", BBO(16,BODNZF
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6072 {"bdnzfla-", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDMA
}},
6073 {"bdnzfla+", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDPA
}},
6074 {"bdnzfla", BBO(16,BODNZF
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6075 {"bdzf-", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDM
}},
6076 {"bdzf+", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDP
}},
6077 {"bdzf", BBO(16,BODZF
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6078 {"bdzfl-", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDM
}},
6079 {"bdzfl+", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDP
}},
6080 {"bdzfl", BBO(16,BODZF
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6081 {"bdzfa-", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDMA
}},
6082 {"bdzfa+", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDPA
}},
6083 {"bdzfa", BBO(16,BODZF
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6084 {"bdzfla-", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDMA
}},
6085 {"bdzfla+", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDPA
}},
6086 {"bdzfla", BBO(16,BODZF
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6088 {"bf-", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDM
}},
6089 {"bf+", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDP
}},
6090 {"bf", BBO(16,BOF
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6091 {"bbf", BBO(16,BOF
,0,0), BBOAT_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6092 {"bfl-", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDM
}},
6093 {"bfl+", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDP
}},
6094 {"bfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6095 {"bbfl", BBO(16,BOF
,0,1), BBOAT_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6096 {"bfa-", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDMA
}},
6097 {"bfa+", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDPA
}},
6098 {"bfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6099 {"bbfa", BBO(16,BOF
,1,0), BBOAT_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6100 {"bfla-", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDMA
}},
6101 {"bfla+", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDPA
}},
6102 {"bfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6103 {"bbfla", BBO(16,BOF
,1,1), BBOAT_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6105 {"bdnzt-", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDM
}},
6106 {"bdnzt+", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDP
}},
6107 {"bdnzt", BBO(16,BODNZT
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6108 {"bdnztl-", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDM
}},
6109 {"bdnztl+", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDP
}},
6110 {"bdnztl", BBO(16,BODNZT
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6111 {"bdnzta-", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDMA
}},
6112 {"bdnzta+", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDPA
}},
6113 {"bdnzta", BBO(16,BODNZT
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6114 {"bdnztla-", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDMA
}},
6115 {"bdnztla+", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDPA
}},
6116 {"bdnztla", BBO(16,BODNZT
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6117 {"bdzt-", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDM
}},
6118 {"bdzt+", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDP
}},
6119 {"bdzt", BBO(16,BODZT
,0,0), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6120 {"bdztl-", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDM
}},
6121 {"bdztl+", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDP
}},
6122 {"bdztl", BBO(16,BODZT
,0,1), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6123 {"bdzta-", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDMA
}},
6124 {"bdzta+", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDPA
}},
6125 {"bdzta", BBO(16,BODZT
,1,0), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6126 {"bdztla-", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDMA
}},
6127 {"bdztla+", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BDPA
}},
6128 {"bdztla", BBO(16,BODZT
,1,1), BBOY_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6130 {"bt-", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDM
}},
6131 {"bt+", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDP
}},
6132 {"bt", BBO(16,BOT
,0,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6133 {"bbt", BBO(16,BOT
,0,0), BBOAT_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6134 {"btl-", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDM
}},
6135 {"btl+", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDP
}},
6136 {"btl", BBO(16,BOT
,0,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6137 {"bbtl", BBO(16,BOT
,0,1), BBOAT_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BD
}},
6138 {"bta-", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDMA
}},
6139 {"bta+", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDPA
}},
6140 {"bta", BBO(16,BOT
,1,0), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6141 {"bbta", BBO(16,BOT
,1,0), BBOAT_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6142 {"btla-", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDMA
}},
6143 {"btla+", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDPA
}},
6144 {"btla", BBO(16,BOT
,1,1), BBOAT_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6145 {"bbtla", BBO(16,BOT
,1,1), BBOAT_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BDA
}},
6147 {"bc-", B(16,0,0), B_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOM
, BI
, BDM
}},
6148 {"bc+", B(16,0,0), B_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOP
, BI
, BDP
}},
6149 {"bc", B(16,0,0), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BD
}},
6150 {"bcl-", B(16,0,1), B_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOM
, BI
, BDM
}},
6151 {"bcl+", B(16,0,1), B_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOP
, BI
, BDP
}},
6152 {"bcl", B(16,0,1), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BD
}},
6153 {"bca-", B(16,1,0), B_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOM
, BI
, BDMA
}},
6154 {"bca+", B(16,1,0), B_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOP
, BI
, BDPA
}},
6155 {"bca", B(16,1,0), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BDA
}},
6156 {"bcla-", B(16,1,1), B_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOM
, BI
, BDMA
}},
6157 {"bcla+", B(16,1,1), B_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOP
, BI
, BDPA
}},
6158 {"bcla", B(16,1,1), B_MASK
, COM
, PPCVLE
, {BO
, BI
, BDA
}},
6160 {"svc", SC(17,0,0), SC_MASK
, POWER
, PPCVLE
, {SVC_LEV
, FL1
, FL2
}},
6161 {"scv", SC(17,0,1), SC_MASK
, POWER9
, PPCVLE
, {SVC_LEV
}},
6162 {"svcl", SC(17,0,1), SC_MASK
, POWER
, PPCVLE
, {SVC_LEV
, FL1
, FL2
}},
6163 {"sc", SC(17,1,0), SC_MASK
, PPC
, PPCVLE
, {LEV
}},
6164 {"svca", SC(17,1,0), SC_MASK
, PWRCOM
, PPCVLE
, {SV
}},
6165 {"svcla", SC(17,1,1), SC_MASK
, POWER
, PPCVLE
, {SV
}},
6167 {"b", B(18,0,0), B_MASK
, COM
, PPCVLE
, {LI
}},
6168 {"bl", B(18,0,1), B_MASK
, COM
, PPCVLE
, {LI
}},
6169 {"ba", B(18,1,0), B_MASK
, COM
, PPCVLE
, {LIA
}},
6170 {"bla", B(18,1,1), B_MASK
, COM
, PPCVLE
, {LIA
}},
6172 {"mcrf", XL(19,0), XLBB_MASK
|(3<<21)|(3<<16), COM
, PPCVLE
, {BF
, BFA
}},
6174 {"lnia", DX(19,2), NODX_MASK
, POWER9
, PPCVLE
|EXT
, {RT
}},
6175 {"addpcis", DX(19,2), DX_MASK
, POWER9
, PPCVLE
, {RT
, DXD
}},
6176 {"subpcis", DX(19,2), DX_MASK
, POWER9
, PPCVLE
|EXT
, {RT
, NDXD
}},
6178 {"bdnzlr-", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BH
}},
6179 {"bdnzlr+", XLO(19,BODNZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BH
}},
6180 {"bdnzlr", XLO(19,BODNZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BH
}},
6181 {"bdnzlrl-", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BH
}},
6182 {"bdnzlrl+", XLO(19,BODNZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BH
}},
6183 {"bdnzlrl", XLO(19,BODNZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BH
}},
6184 {"bdzlr-", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BH
}},
6185 {"bdzlr+", XLO(19,BODZP
,16,0), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BH
}},
6186 {"bdzlr", XLO(19,BODZ
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BH
}},
6187 {"bdzlrl-", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BH
}},
6188 {"bdzlrl+", XLO(19,BODZP
,16,1), XLBOBIBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BH
}},
6189 {"bdzlrl", XLO(19,BODZ
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BH
}},
6190 {"blr", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BH
}},
6191 {"br", XLO(19,BOU
,16,0), XLBOBIBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {BH
}},
6192 {"blrl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BH
}},
6193 {"brl", XLO(19,BOU
,16,1), XLBOBIBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {BH
}},
6194 {"bdnzlr-", XLO(19,BODNZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BH
}},
6195 {"bdnzlrl-", XLO(19,BODNZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BH
}},
6196 {"bdnzlr+", XLO(19,BODNZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BH
}},
6197 {"bdnzlrl+", XLO(19,BODNZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BH
}},
6198 {"bdzlr-", XLO(19,BODZM4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BH
}},
6199 {"bdzlrl-", XLO(19,BODZM4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BH
}},
6200 {"bdzlr+", XLO(19,BODZP4
,16,0), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BH
}},
6201 {"bdzlrl+", XLO(19,BODZP4
,16,1), XLBOBIBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BH
}},
6203 {"bgelr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6204 {"bgelr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6205 {"bgelr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6206 {"bger", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6207 {"bnllr-", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6208 {"bnllr+", XLOCB(19,BOFP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6209 {"bnllr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6210 {"bnlr", XLOCB(19,BOF
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6211 {"bgelrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6212 {"bgelrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6213 {"bgelrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6214 {"bgerl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6215 {"bnllrl-", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6216 {"bnllrl+", XLOCB(19,BOFP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6217 {"bnllrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6218 {"bnlrl", XLOCB(19,BOF
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6219 {"blelr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6220 {"blelr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6221 {"blelr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6222 {"bler", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6223 {"bnglr-", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6224 {"bnglr+", XLOCB(19,BOFP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6225 {"bnglr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6226 {"bngr", XLOCB(19,BOF
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6227 {"blelrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6228 {"blelrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6229 {"blelrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6230 {"blerl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6231 {"bnglrl-", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6232 {"bnglrl+", XLOCB(19,BOFP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6233 {"bnglrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6234 {"bngrl", XLOCB(19,BOF
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6235 {"bnelr-", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6236 {"bnelr+", XLOCB(19,BOFP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6237 {"bnelr", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6238 {"bner", XLOCB(19,BOF
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6239 {"bnelrl-", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6240 {"bnelrl+", XLOCB(19,BOFP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6241 {"bnelrl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6242 {"bnerl", XLOCB(19,BOF
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6243 {"bnslr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6244 {"bnslr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6245 {"bnslr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6246 {"bnsr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6247 {"bnulr-", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6248 {"bnulr+", XLOCB(19,BOFP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6249 {"bnulr", XLOCB(19,BOF
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6250 {"bnslrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6251 {"bnslrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6252 {"bnslrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6253 {"bnsrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6254 {"bnulrl-", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6255 {"bnulrl+", XLOCB(19,BOFP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6256 {"bnulrl", XLOCB(19,BOF
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6257 {"bgelr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6258 {"bnllr-", XLOCB(19,BOFM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6259 {"bgelrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6260 {"bnllrl-", XLOCB(19,BOFM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6261 {"blelr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6262 {"bnglr-", XLOCB(19,BOFM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6263 {"blelrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6264 {"bnglrl-", XLOCB(19,BOFM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6265 {"bnelr-", XLOCB(19,BOFM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6266 {"bnelrl-", XLOCB(19,BOFM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6267 {"bnslr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6268 {"bnulr-", XLOCB(19,BOFM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6269 {"bnslrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6270 {"bnulrl-", XLOCB(19,BOFM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6271 {"bgelr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6272 {"bnllr+", XLOCB(19,BOFP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6273 {"bgelrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6274 {"bnllrl+", XLOCB(19,BOFP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6275 {"blelr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6276 {"bnglr+", XLOCB(19,BOFP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6277 {"blelrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6278 {"bnglrl+", XLOCB(19,BOFP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6279 {"bnelr+", XLOCB(19,BOFP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6280 {"bnelrl+", XLOCB(19,BOFP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6281 {"bnslr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6282 {"bnulr+", XLOCB(19,BOFP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6283 {"bnslrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6284 {"bnulrl+", XLOCB(19,BOFP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6285 {"bltlr-", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6286 {"bltlr+", XLOCB(19,BOTP
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6287 {"bltlr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6288 {"bltr", XLOCB(19,BOT
,CBLT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6289 {"bltlrl-", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6290 {"bltlrl+", XLOCB(19,BOTP
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6291 {"bltlrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6292 {"bltrl", XLOCB(19,BOT
,CBLT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6293 {"bgtlr-", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6294 {"bgtlr+", XLOCB(19,BOTP
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6295 {"bgtlr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6296 {"bgtr", XLOCB(19,BOT
,CBGT
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6297 {"bgtlrl-", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6298 {"bgtlrl+", XLOCB(19,BOTP
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6299 {"bgtlrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6300 {"bgtrl", XLOCB(19,BOT
,CBGT
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6301 {"beqlr-", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6302 {"beqlr+", XLOCB(19,BOTP
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6303 {"beqlr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6304 {"beqr", XLOCB(19,BOT
,CBEQ
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6305 {"beqlrl-", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6306 {"beqlrl+", XLOCB(19,BOTP
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6307 {"beqlrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6308 {"beqrl", XLOCB(19,BOT
,CBEQ
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6309 {"bsolr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6310 {"bsolr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6311 {"bsolr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6312 {"bsor", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6313 {"bunlr-", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6314 {"bunlr+", XLOCB(19,BOTP
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6315 {"bunlr", XLOCB(19,BOT
,CBSO
,16,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6316 {"bsolrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6317 {"bsolrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6318 {"bsolrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6319 {"bsorl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6320 {"bunlrl-", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6321 {"bunlrl+", XLOCB(19,BOTP
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6322 {"bunlrl", XLOCB(19,BOT
,CBSO
,16,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6323 {"bltlr-", XLOCB(19,BOTM4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6324 {"bltlrl-", XLOCB(19,BOTM4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6325 {"bgtlr-", XLOCB(19,BOTM4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6326 {"bgtlrl-", XLOCB(19,BOTM4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6327 {"beqlr-", XLOCB(19,BOTM4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6328 {"beqlrl-", XLOCB(19,BOTM4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6329 {"bsolr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6330 {"bunlr-", XLOCB(19,BOTM4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6331 {"bsolrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6332 {"bunlrl-", XLOCB(19,BOTM4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6333 {"bltlr+", XLOCB(19,BOTP4
,CBLT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6334 {"bltlrl+", XLOCB(19,BOTP4
,CBLT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6335 {"bgtlr+", XLOCB(19,BOTP4
,CBGT
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6336 {"bgtlrl+", XLOCB(19,BOTP4
,CBGT
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6337 {"beqlr+", XLOCB(19,BOTP4
,CBEQ
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6338 {"beqlrl+", XLOCB(19,BOTP4
,CBEQ
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6339 {"bsolr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6340 {"bunlr+", XLOCB(19,BOTP4
,CBSO
,16,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6341 {"bsolrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6342 {"bunlrl+", XLOCB(19,BOTP4
,CBSO
,16,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6344 {"bdnzflr-", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6345 {"bdnzflr+", XLO(19,BODNZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6346 {"bdnzflr", XLO(19,BODNZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6347 {"bdnzflrl-",XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6348 {"bdnzflrl+",XLO(19,BODNZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6349 {"bdnzflrl", XLO(19,BODNZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6350 {"bdzflr-", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6351 {"bdzflr+", XLO(19,BODZFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6352 {"bdzflr", XLO(19,BODZF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6353 {"bdzflrl-", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6354 {"bdzflrl+", XLO(19,BODZFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6355 {"bdzflrl", XLO(19,BODZF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6356 {"bflr-", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6357 {"bflr+", XLO(19,BOFP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6358 {"bflr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6359 {"bbfr", XLO(19,BOF
,16,0), XLBOBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6360 {"bflrl-", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6361 {"bflrl+", XLO(19,BOFP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6362 {"bflrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6363 {"bbfrl", XLO(19,BOF
,16,1), XLBOBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6364 {"bflr-", XLO(19,BOFM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6365 {"bflrl-", XLO(19,BOFM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6366 {"bflr+", XLO(19,BOFP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6367 {"bflrl+", XLO(19,BOFP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6368 {"bdnztlr-", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6369 {"bdnztlr+", XLO(19,BODNZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6370 {"bdnztlr", XLO(19,BODNZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6371 {"bdnztlrl-", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6372 {"bdnztlrl+", XLO(19,BODNZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6373 {"bdnztlrl", XLO(19,BODNZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6374 {"bdztlr-", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6375 {"bdztlr+", XLO(19,BODZTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6376 {"bdztlr", XLO(19,BODZT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6377 {"bdztlrl-", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6378 {"bdztlrl+", XLO(19,BODZTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6379 {"bdztlrl", XLO(19,BODZT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6380 {"btlr-", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6381 {"btlr+", XLO(19,BOTP
,16,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6382 {"btlr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6383 {"bbtr", XLO(19,BOT
,16,0), XLBOBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6384 {"btlrl-", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6385 {"btlrl+", XLO(19,BOTP
,16,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6386 {"btlrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6387 {"bbtrl", XLO(19,BOT
,16,1), XLBOBB_MASK
, PWRCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6388 {"btlr-", XLO(19,BOTM4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6389 {"btlrl-", XLO(19,BOTM4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6390 {"btlr+", XLO(19,BOTP4
,16,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6391 {"btlrl+", XLO(19,BOTP4
,16,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6393 {"bclr-", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOM
, BI
, BH
}},
6394 {"bclr+", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOP
, BI
, BH
}},
6395 {"bclr", XLLK(19,16,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
6396 {"bcr", XLLK(19,16,0), XLBH_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
, BH
}},
6397 {"bclrl-", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOM
, BI
, BH
}},
6398 {"bclrl+", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOP
, BI
, BH
}},
6399 {"bclrl", XLLK(19,16,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
6400 {"bcrl", XLLK(19,16,1), XLBH_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
, BH
}},
6402 {"rfid", XL(19,18), 0xffffffff, PPC64
, PPCVLE
, {0}},
6404 {"crnot", XL(19,33), XL_MASK
, PPCCOM
, PPCVLE
|EXT
, {BT
, BAB
}},
6405 {"crnor", XL(19,33), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
6407 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI
|PPCA2
|PPC476
, PPCVLE
, {0}},
6408 {"rfdi", XL(19,39), 0xffffffff, E500MC
, PPCVLE
, {0}},
6409 {"rfi", XL(19,50), 0xffffffff, COM
, PPCVLE
, {0}},
6410 {"rfci", XL(19,51), 0xffffffff, PPC403
|BOOKE
|PPCE300
|PPCA2
|PPC476
, PPCVLE
, {0}},
6412 {"rfscv", XL(19,82), 0xffffffff, POWER9
, PPCVLE
, {0}},
6413 {"rfsvc", XL(19,82), 0xffffffff, POWER
, PPCVLE
, {0}},
6415 {"rfgi", XL(19,102), 0xffffffff, E500MC
|PPCA2
, PPCVLE
, {0}},
6417 {"crandc", XL(19,129), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
6419 {"rfebb", XL(19,146), XLS_MASK
, POWER8
, PPCVLE
, {SXL
}},
6421 {"isync", XL(19,150), 0xffffffff, PPCCOM
, PPCVLE
, {0}},
6422 {"ics", XL(19,150), 0xffffffff, PWRCOM
, PPCVLE
, {0}},
6424 {"crclr", XL(19,193), XL_MASK
, PPCCOM
, PPCVLE
|EXT
, {BTAB
}},
6425 {"crxor", XL(19,193), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
6427 {"dnh", X(19,198), X_MASK
, E500MC
, PPCVLE
, {DUI
, DUIS
}},
6429 {"crnand", XL(19,225), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
6431 {"crand", XL(19,257), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
6433 {"hrfid", XL(19,274), 0xffffffff, POWER5
|CELL
, PPC476
|PPCVLE
, {0}},
6435 {"crset", XL(19,289), XL_MASK
, PPCCOM
, PPCVLE
|EXT
, {BTAB
}},
6436 {"creqv", XL(19,289), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
6438 {"urfid", XL(19,306), 0xffffffff, POWER9
, PPCVLE
, {0}},
6439 {"stop", XL(19,370), 0xffffffff, POWER9
, PPCVLE
, {0}},
6441 {"doze", XL(19,402), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
6443 {"crorc", XL(19,417), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
6445 {"nap", XL(19,434), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
6447 {"crmove", XL(19,449), XL_MASK
, PPCCOM
, PPCVLE
|EXT
, {BT
, BAB
}},
6448 {"cror", XL(19,449), XL_MASK
, COM
, PPCVLE
, {BT
, BA
, BB
}},
6450 {"sleep", XL(19,466), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
6451 {"rvwinkle", XL(19,498), 0xffffffff, POWER6
, POWER9
|PPCVLE
, {0}},
6453 {"bctr", XLO(19,BOU
,528,0), XLBOBIBB_MASK
, COM
, PPCVLE
|EXT
, {BH
}},
6454 {"bctrl", XLO(19,BOU
,528,1), XLBOBIBB_MASK
, COM
, PPCVLE
|EXT
, {BH
}},
6455 {"bgectr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6456 {"bgectr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6457 {"bgectr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6458 {"bnlctr-", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6459 {"bnlctr+", XLOCB(19,BOFP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6460 {"bnlctr", XLOCB(19,BOF
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6461 {"bgectrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6462 {"bgectrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6463 {"bgectrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6464 {"bnlctrl-",XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6465 {"bnlctrl+",XLOCB(19,BOFP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6466 {"bnlctrl", XLOCB(19,BOF
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6467 {"blectr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6468 {"blectr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6469 {"blectr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6470 {"bngctr-", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6471 {"bngctr+", XLOCB(19,BOFP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6472 {"bngctr", XLOCB(19,BOF
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6473 {"blectrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6474 {"blectrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6475 {"blectrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6476 {"bngctrl-",XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6477 {"bngctrl+",XLOCB(19,BOFP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6478 {"bngctrl", XLOCB(19,BOF
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6479 {"bnectr-", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6480 {"bnectr+", XLOCB(19,BOFP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6481 {"bnectr", XLOCB(19,BOF
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6482 {"bnectrl-",XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6483 {"bnectrl+",XLOCB(19,BOFP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6484 {"bnectrl", XLOCB(19,BOF
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6485 {"bnsctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6486 {"bnsctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6487 {"bnsctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6488 {"bnuctr-", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6489 {"bnuctr+", XLOCB(19,BOFP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6490 {"bnuctr", XLOCB(19,BOF
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6491 {"bnsctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6492 {"bnsctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6493 {"bnsctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6494 {"bnuctrl-",XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6495 {"bnuctrl+",XLOCB(19,BOFP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6496 {"bnuctrl", XLOCB(19,BOF
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6497 {"bgectr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6498 {"bnlctr-", XLOCB(19,BOFM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6499 {"bgectrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6500 {"bnlctrl-",XLOCB(19,BOFM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6501 {"blectr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6502 {"bngctr-", XLOCB(19,BOFM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6503 {"blectrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6504 {"bngctrl-",XLOCB(19,BOFM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6505 {"bnectr-", XLOCB(19,BOFM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6506 {"bnectrl-",XLOCB(19,BOFM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6507 {"bnsctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6508 {"bnuctr-", XLOCB(19,BOFM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6509 {"bnsctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6510 {"bnuctrl-",XLOCB(19,BOFM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6511 {"bgectr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6512 {"bnlctr+", XLOCB(19,BOFP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6513 {"bgectrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6514 {"bnlctrl+",XLOCB(19,BOFP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6515 {"blectr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6516 {"bngctr+", XLOCB(19,BOFP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6517 {"blectrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6518 {"bngctrl+",XLOCB(19,BOFP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6519 {"bnectr+", XLOCB(19,BOFP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6520 {"bnectrl+",XLOCB(19,BOFP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6521 {"bnsctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6522 {"bnuctr+", XLOCB(19,BOFP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6523 {"bnsctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6524 {"bnuctrl+",XLOCB(19,BOFP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6525 {"bltctr-", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6526 {"bltctr+", XLOCB(19,BOTP
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6527 {"bltctr", XLOCB(19,BOT
,CBLT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6528 {"bltctrl-",XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6529 {"bltctrl+",XLOCB(19,BOTP
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6530 {"bltctrl", XLOCB(19,BOT
,CBLT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6531 {"bgtctr-", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6532 {"bgtctr+", XLOCB(19,BOTP
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6533 {"bgtctr", XLOCB(19,BOT
,CBGT
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6534 {"bgtctrl-",XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6535 {"bgtctrl+",XLOCB(19,BOTP
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6536 {"bgtctrl", XLOCB(19,BOT
,CBGT
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6537 {"beqctr-", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6538 {"beqctr+", XLOCB(19,BOTP
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6539 {"beqctr", XLOCB(19,BOT
,CBEQ
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6540 {"beqctrl-",XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6541 {"beqctrl+",XLOCB(19,BOTP
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6542 {"beqctrl", XLOCB(19,BOT
,CBEQ
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6543 {"bsoctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6544 {"bsoctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6545 {"bsoctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6546 {"bunctr-", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6547 {"bunctr+", XLOCB(19,BOTP
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6548 {"bunctr", XLOCB(19,BOT
,CBSO
,528,0), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6549 {"bsoctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6550 {"bsoctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6551 {"bsoctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6552 {"bunctrl-",XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6553 {"bunctrl+",XLOCB(19,BOTP
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {CR
, BH
}},
6554 {"bunctrl", XLOCB(19,BOT
,CBSO
,528,1), XLBOCBBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {CR
, BH
}},
6555 {"bltctr-", XLOCB(19,BOTM4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6556 {"bltctrl-",XLOCB(19,BOTM4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6557 {"bgtctr-", XLOCB(19,BOTM4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6558 {"bgtctrl-",XLOCB(19,BOTM4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6559 {"beqctr-", XLOCB(19,BOTM4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6560 {"beqctrl-",XLOCB(19,BOTM4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6561 {"bsoctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6562 {"bunctr-", XLOCB(19,BOTM4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6563 {"bsoctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6564 {"bunctrl-",XLOCB(19,BOTM4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6565 {"bltctr+", XLOCB(19,BOTP4
,CBLT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6566 {"bltctrl+",XLOCB(19,BOTP4
,CBLT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6567 {"bgtctr+", XLOCB(19,BOTP4
,CBGT
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6568 {"bgtctrl+",XLOCB(19,BOTP4
,CBGT
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6569 {"beqctr+", XLOCB(19,BOTP4
,CBEQ
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6570 {"beqctrl+",XLOCB(19,BOTP4
,CBEQ
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6571 {"bsoctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6572 {"bunctr+", XLOCB(19,BOTP4
,CBSO
,528,0), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6573 {"bsoctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6574 {"bunctrl+",XLOCB(19,BOTP4
,CBSO
,528,1), XLBOCBBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {CR
, BH
}},
6576 {"bfctr-", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6577 {"bfctr+", XLO(19,BOFP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6578 {"bfctr", XLO(19,BOF
,528,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6579 {"bfctrl-", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6580 {"bfctrl+", XLO(19,BOFP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6581 {"bfctrl", XLO(19,BOF
,528,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6582 {"bfctr-", XLO(19,BOFM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6583 {"bfctrl-", XLO(19,BOFM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6584 {"bfctr+", XLO(19,BOFP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6585 {"bfctrl+", XLO(19,BOFP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6586 {"btctr-", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6587 {"btctr+", XLO(19,BOTP
,528,0), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6588 {"btctr", XLO(19,BOT
,528,0), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6589 {"btctrl-", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6590 {"btctrl+", XLO(19,BOTP
,528,1), XLBOBB_MASK
, PPCCOM
, ISA_V2
|PPCVLE
|EXT
, {BI
, BH
}},
6591 {"btctrl", XLO(19,BOT
,528,1), XLBOBB_MASK
, PPCCOM
, PPCVLE
|EXT
, {BI
, BH
}},
6592 {"btctr-", XLO(19,BOTM4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6593 {"btctrl-", XLO(19,BOTM4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6594 {"btctr+", XLO(19,BOTP4
,528,0), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6595 {"btctrl+", XLO(19,BOTP4
,528,1), XLBOBB_MASK
, ISA_V2
, PPCVLE
|EXT
, {BI
, BH
}},
6597 {"bcctr-", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOM
, BI
, BH
}},
6598 {"bcctr+", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOP
, BI
, BH
}},
6599 {"bcctr", XLLK(19,528,0), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
6600 {"bcc", XLLK(19,528,0), XLBH_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
, BH
}},
6601 {"bcctrl-", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOM
, BI
, BH
}},
6602 {"bcctrl+", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCVLE
|EXT
, {BOP
, BI
, BH
}},
6603 {"bcctrl", XLLK(19,528,1), XLBH_MASK
, PPCCOM
, PPCVLE
, {BO
, BI
, BH
}},
6604 {"bccl", XLLK(19,528,1), XLBH_MASK
, PWRCOM
, PPCVLE
, {BO
, BI
, BH
}},
6606 {"bdnztar", XLO(19,BODNZ
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6607 {"bdnztarl", XLO(19,BODNZ
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6608 {"bdztar", XLO(19,BODZ
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6609 {"bdztarl", XLO(19,BODZ
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6610 {"btar", XLO(19,BOU
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6611 {"btarl", XLO(19,BOU
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6612 {"bdnztar-", XLO(19,BODNZM4
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6613 {"bdnztarl-", XLO(19,BODNZM4
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6614 {"bdnztar+", XLO(19,BODNZP4
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6615 {"bdnztarl+", XLO(19,BODNZP4
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6616 {"bdztar-", XLO(19,BODZM4
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6617 {"bdztarl-", XLO(19,BODZM4
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6618 {"bdztar+", XLO(19,BODZP4
,560,0), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6619 {"bdztarl+", XLO(19,BODZP4
,560,1), XLBOBIBB_MASK
, POWER8
, PPCVLE
|EXT
, {BH
}},
6621 {"bgetar", XLOCB(19,BOF
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6622 {"bnltar", XLOCB(19,BOF
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6623 {"bgetarl", XLOCB(19,BOF
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6624 {"bnltarl", XLOCB(19,BOF
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6625 {"bletar", XLOCB(19,BOF
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6626 {"bngtar", XLOCB(19,BOF
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6627 {"bletarl", XLOCB(19,BOF
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6628 {"bngtarl", XLOCB(19,BOF
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6629 {"bnetar", XLOCB(19,BOF
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6630 {"bnetarl", XLOCB(19,BOF
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6631 {"bnstar", XLOCB(19,BOF
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6632 {"bnutar", XLOCB(19,BOF
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6633 {"bnstarl", XLOCB(19,BOF
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6634 {"bnutarl", XLOCB(19,BOF
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6635 {"bgetar-", XLOCB(19,BOFM4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6636 {"bnltar-", XLOCB(19,BOFM4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6637 {"bgetarl-",XLOCB(19,BOFM4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6638 {"bnltarl-",XLOCB(19,BOFM4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6639 {"bletar-", XLOCB(19,BOFM4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6640 {"bngtar-", XLOCB(19,BOFM4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6641 {"bletarl-",XLOCB(19,BOFM4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6642 {"bngtarl-",XLOCB(19,BOFM4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6643 {"bnetar-", XLOCB(19,BOFM4
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6644 {"bnetarl-",XLOCB(19,BOFM4
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6645 {"bnstar-", XLOCB(19,BOFM4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6646 {"bnutar-", XLOCB(19,BOFM4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6647 {"bnstarl-",XLOCB(19,BOFM4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6648 {"bnutarl-",XLOCB(19,BOFM4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6649 {"bgetar+", XLOCB(19,BOFP4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6650 {"bnltar+", XLOCB(19,BOFP4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6651 {"bgetarl+",XLOCB(19,BOFP4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6652 {"bnltarl+",XLOCB(19,BOFP4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6653 {"bletar+", XLOCB(19,BOFP4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6654 {"bngtar+", XLOCB(19,BOFP4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6655 {"bletarl+",XLOCB(19,BOFP4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6656 {"bngtarl+",XLOCB(19,BOFP4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6657 {"bnetar+", XLOCB(19,BOFP4
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6658 {"bnetarl+",XLOCB(19,BOFP4
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6659 {"bnstar+", XLOCB(19,BOFP4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6660 {"bnutar+", XLOCB(19,BOFP4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6661 {"bnstarl+",XLOCB(19,BOFP4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6662 {"bnutarl+",XLOCB(19,BOFP4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6663 {"blttar", XLOCB(19,BOT
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6664 {"blttarl", XLOCB(19,BOT
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6665 {"bgttar", XLOCB(19,BOT
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6666 {"bgttarl", XLOCB(19,BOT
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6667 {"beqtar", XLOCB(19,BOT
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6668 {"beqtarl", XLOCB(19,BOT
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6669 {"bsotar", XLOCB(19,BOT
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6670 {"buntar", XLOCB(19,BOT
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6671 {"bsotarl", XLOCB(19,BOT
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6672 {"buntarl", XLOCB(19,BOT
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6673 {"blttar-", XLOCB(19,BOTM4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6674 {"blttarl-",XLOCB(19,BOTM4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6675 {"bgttar-", XLOCB(19,BOTM4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6676 {"bgttarl-",XLOCB(19,BOTM4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6677 {"beqtar-", XLOCB(19,BOTM4
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6678 {"beqtarl-",XLOCB(19,BOTM4
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6679 {"bsotar-", XLOCB(19,BOTM4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6680 {"buntar-", XLOCB(19,BOTM4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6681 {"bsotarl-",XLOCB(19,BOTM4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6682 {"buntarl-",XLOCB(19,BOTM4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6683 {"blttar+", XLOCB(19,BOTP4
,CBLT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6684 {"blttarl+",XLOCB(19,BOTP4
,CBLT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6685 {"bgttar+", XLOCB(19,BOTP4
,CBGT
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6686 {"bgttarl+",XLOCB(19,BOTP4
,CBGT
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6687 {"beqtar+", XLOCB(19,BOTP4
,CBEQ
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6688 {"beqtarl+",XLOCB(19,BOTP4
,CBEQ
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6689 {"bsotar+", XLOCB(19,BOTP4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6690 {"buntar+", XLOCB(19,BOTP4
,CBSO
,560,0), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6691 {"bsotarl+",XLOCB(19,BOTP4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6692 {"buntarl+",XLOCB(19,BOTP4
,CBSO
,560,1), XLBOCBBB_MASK
, POWER8
, PPCVLE
|EXT
, {CR
, BH
}},
6694 {"bdnzftar", XLO(19,BODNZF
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6695 {"bdnzftarl", XLO(19,BODNZF
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6696 {"bdzftar", XLO(19,BODZF
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6697 {"bdzftarl", XLO(19,BODZF
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6699 {"bftar", XLO(19,BOF
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6700 {"bftarl", XLO(19,BOF
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6701 {"bftar-", XLO(19,BOFM4
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6702 {"bftarl-", XLO(19,BOFM4
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6703 {"bftar+", XLO(19,BOFP4
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6704 {"bftarl+", XLO(19,BOFP4
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6706 {"bdnzttar", XLO(19,BODNZT
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6707 {"bdnzttarl", XLO(19,BODNZT
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6708 {"bdzttar", XLO(19,BODZT
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6709 {"bdzttarl", XLO(19,BODZT
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6711 {"bttar", XLO(19,BOT
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6712 {"bttarl", XLO(19,BOT
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6713 {"bttar-", XLO(19,BOTM4
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6714 {"bttarl-", XLO(19,BOTM4
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6715 {"bttar+", XLO(19,BOTP4
,560,0), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6716 {"bttarl+", XLO(19,BOTP4
,560,1), XLBOBB_MASK
, POWER8
, PPCVLE
|EXT
, {BI
, BH
}},
6718 {"bctar-", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCVLE
|EXT
, {BOM
, BI
, BH
}},
6719 {"bctar+", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCVLE
|EXT
, {BOP
, BI
, BH
}},
6720 {"bctar", XLLK(19,560,0), XLBH_MASK
, POWER8
, PPCVLE
, {BO
, BI
, BH
}},
6721 {"bctarl-", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCVLE
|EXT
, {BOM
, BI
, BH
}},
6722 {"bctarl+", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCVLE
|EXT
, {BOP
, BI
, BH
}},
6723 {"bctarl", XLLK(19,560,1), XLBH_MASK
, POWER8
, PPCVLE
, {BO
, BI
, BH
}},
6725 {"rlwimi", M(20,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
6726 {"inslwi", M(20,0), M_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, ILWn
, ILWb
}},
6727 {"insrwi", M(20,0), M_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, IRWn
, IRWb
}},
6728 {"rlimi", M(20,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
6730 {"rlwimi.", M(20,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
6731 {"inslwi.", M(20,1), M_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, ILWn
, ILWb
}},
6732 {"insrwi.", M(20,1), M_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, IRWn
, IRWb
}},
6733 {"rlimi.", M(20,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
6735 {"rotlwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, SH
}},
6736 {"rotrwi", MME(21,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, RRWn
}},
6737 {"clrlwi", MME(21,31,0), MSHME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, MB
}},
6738 {"clrrwi", M(21,0), MSHMB_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, CRWn
}},
6739 {"slwi", M(21,0), MMB_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, SLWn
}},
6740 {"srwi", MME(21,31,0), MME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, SRWn
}},
6741 {"rlwinm", M(21,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
6742 {"extlwi", M(21,0), MMB_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, ELWn
, SH
}},
6743 {"extrwi", MME(21,31,0), MME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, ERWn
, ERWb
}},
6744 {"clrlslwi", M(21,0), M_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, CSLWb
, CSLWn
}},
6745 {"sli", M(21,0), MMB_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, RS
, SLWn
}},
6746 {"sri", MME(21,31,0), MME_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, RS
, SRWn
}},
6747 {"rlinm", M(21,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
6748 {"rotlwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, SH
}},
6749 {"rotrwi.", MME(21,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, RRWn
}},
6750 {"clrlwi.", MME(21,31,1), MSHME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, MB
}},
6751 {"clrrwi.", M(21,1), MSHMB_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, CRWn
}},
6752 {"slwi.", M(21,1), MMB_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, SLWn
}},
6753 {"srwi.", MME(21,31,1), MME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, SRWn
}},
6754 {"rlwinm.", M(21,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
6755 {"extlwi.", M(21,1), MMB_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, ELWn
, SH
}},
6756 {"extrwi.", MME(21,31,1), MME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, ERWn
, ERWb
}},
6757 {"clrlslwi.", M(21,1), M_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, CSLWb
, CSLWn
}},
6758 {"sli.", M(21,1), MMB_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, RS
, SLWn
}},
6759 {"sri.", MME(21,31,1), MME_MASK
, PWRCOM
, PPCVLE
|EXT
, {RA
, RS
, SRWn
}},
6760 {"rlinm.", M(21,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, SH
, MBE
, ME
}},
6762 {"rlmi", M(22,0), M_MASK
, M601
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
6763 {"rlmi.", M(22,1), M_MASK
, M601
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
6765 {"rotlw", MME(23,31,0), MMBME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, RB
}},
6766 {"rlwnm", M(23,0), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
6767 {"rlnm", M(23,0), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
6768 {"rotlw.", MME(23,31,1), MMBME_MASK
, PPCCOM
, PPCVLE
|EXT
, {RA
, RS
, RB
}},
6769 {"rlwnm.", M(23,1), M_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
6770 {"rlnm.", M(23,1), M_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, RB
, MBE
, ME
}},
6772 {"nop", OP(24), 0xffffffff, PPCCOM
, PPCVLE
|EXT
, {0}},
6773 {"exser", 0x63ff0000, 0xffffffff, POWER9
, PPCVLE
|EXT
, {0}},
6774 {"ori", OP(24), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
6775 {"oril", OP(24), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
6777 {"oris", OP(25), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
6778 {"oriu", OP(25), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
6780 {"xnop", OP(26), 0xffffffff, PPCCOM
, PPCVLE
|EXT
, {0}},
6781 {"xori", OP(26), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
6782 {"xoril", OP(26), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
6784 {"xoris", OP(27), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
6785 {"xoriu", OP(27), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
6787 {"andi.", OP(28), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
6788 {"andil.", OP(28), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
6790 {"andis.", OP(29), OP_MASK
, PPCCOM
, PPCVLE
, {RA
, RS
, UI
}},
6791 {"andiu.", OP(29), OP_MASK
, PWRCOM
, PPCVLE
, {RA
, RS
, UI
}},
6793 {"rotldi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, SH6
}},
6794 {"rotrdi", MD(30,0,0), MDMB_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, RRDn
}},
6795 {"clrldi", MD(30,0,0), MDSH_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, MB6
}},
6796 {"srdi", MD(30,0,0), MD_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, SRDn
}},
6797 {"rldicl", MD(30,0,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
6798 {"extrdi", MD(30,0,0), MD_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, ERDn
, ERDb
}},
6799 {"rotldi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, SH6
}},
6800 {"rotrdi.", MD(30,0,1), MDMB_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, RRDn
}},
6801 {"clrldi.", MD(30,0,1), MDSH_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, MB6
}},
6802 {"srdi.", MD(30,0,1), MD_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, SRDn
}},
6803 {"rldicl.", MD(30,0,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
6804 {"extrdi.", MD(30,0,1), MD_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, ERDn
, ERDb
}},
6806 {"clrrdi", MD(30,1,0), MDSH_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, CRDn
}},
6807 {"sldi", MD(30,1,0), MD_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, SLDn
}},
6808 {"rldicr", MD(30,1,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, ME6
}},
6809 {"extldi", MD(30,1,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, ELDn
, SH6
}},
6810 {"clrrdi.", MD(30,1,1), MDSH_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, CRDn
}},
6811 {"sldi.", MD(30,1,1), MD_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, SLDn
}},
6812 {"rldicr.", MD(30,1,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, ME6
}},
6813 {"extldi.", MD(30,1,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, ELDn
, SH6
}},
6815 {"rldic", MD(30,2,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
6816 {"clrlsldi", MD(30,2,0), MD_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, CSLDb
, CSLDn
}},
6817 {"rldic.", MD(30,2,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
6818 {"clrlsldi.", MD(30,2,1), MD_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, CSLDb
, CSLDn
}},
6820 {"rldimi", MD(30,3,0), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
6821 {"insrdi", MD(30,3,0), MD_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, IRDn
, IRDb
}},
6822 {"rldimi.", MD(30,3,1), MD_MASK
, PPC64
, PPCVLE
, {RA
, RS
, SH6
, MB6
}},
6823 {"insrdi.", MD(30,3,1), MD_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, IRDn
, IRDb
}},
6825 {"rotld", MDS(30,8,0), MDSMB_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, RB
}},
6826 {"rldcl", MDS(30,8,0), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, MB6
}},
6827 {"rotld.", MDS(30,8,1), MDSMB_MASK
, PPC64
, PPCVLE
|EXT
, {RA
, RS
, RB
}},
6828 {"rldcl.", MDS(30,8,1), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, MB6
}},
6830 {"rldcr", MDS(30,9,0), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, ME6
}},
6831 {"rldcr.", MDS(30,9,1), MDS_MASK
, PPC64
, PPCVLE
, {RA
, RS
, RB
, ME6
}},
6833 {"cmpw", XOPL(31,0,0), XCMPL_MASK
, PPCCOM
, EXT
, {OBF
, RA
, RB
}},
6834 {"cmpd", XOPL(31,0,1), XCMPL_MASK
, PPC64
, EXT
, {OBF
, RA
, RB
}},
6835 {"cmp", X(31,0), XCMP_MASK
, PPC
, 0, {BF
, L32OPT
, RA
, RB
}},
6836 {"cmp", X(31,0), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
6838 {"twlgt", XTO(31,4,TOLGT
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6839 {"tlgt", XTO(31,4,TOLGT
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6840 {"twllt", XTO(31,4,TOLLT
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6841 {"tllt", XTO(31,4,TOLLT
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6842 {"tweq", XTO(31,4,TOEQ
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6843 {"teq", XTO(31,4,TOEQ
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6844 {"twlge", XTO(31,4,TOLGE
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6845 {"tlge", XTO(31,4,TOLGE
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6846 {"twlnl", XTO(31,4,TOLNL
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6847 {"tlnl", XTO(31,4,TOLNL
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6848 {"twlle", XTO(31,4,TOLLE
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6849 {"tlle", XTO(31,4,TOLLE
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6850 {"twlng", XTO(31,4,TOLNG
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6851 {"tlng", XTO(31,4,TOLNG
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6852 {"twgt", XTO(31,4,TOGT
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6853 {"tgt", XTO(31,4,TOGT
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6854 {"twge", XTO(31,4,TOGE
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6855 {"tge", XTO(31,4,TOGE
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6856 {"twnl", XTO(31,4,TONL
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6857 {"tnl", XTO(31,4,TONL
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6858 {"twlt", XTO(31,4,TOLT
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6859 {"tlt", XTO(31,4,TOLT
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6860 {"twle", XTO(31,4,TOLE
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6861 {"tle", XTO(31,4,TOLE
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6862 {"twng", XTO(31,4,TONG
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6863 {"tng", XTO(31,4,TONG
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6864 {"twne", XTO(31,4,TONE
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6865 {"tne", XTO(31,4,TONE
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6866 {"trap", XTO(31,4,TOU
), 0xffffffff, PPCCOM
, EXT
, {0}},
6867 {"twu", XTO(31,4,TOU
), XTO_MASK
, PPCCOM
, EXT
, {RA
, RB
}},
6868 {"tu", XTO(31,4,TOU
), XTO_MASK
, PWRCOM
, EXT
, {RA
, RB
}},
6869 {"tw", X(31,4), X_MASK
, PPCCOM
, 0, {TO
, RA
, RB
}},
6870 {"t", X(31,4), X_MASK
, PWRCOM
, 0, {TO
, RA
, RB
}},
6872 {"lvsl", X(31,6), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6873 {"lvebx", X(31,7), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6874 {"lbfcmx", APU(31,7,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6876 {"subfc", XO(31,8,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6877 {"sf", XO(31,8,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6878 {"subc", XO(31,8,0,0), XO_MASK
, PPCCOM
, EXT
, {RT
, RB
, RA
}},
6879 {"subfc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6880 {"sf.", XO(31,8,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6881 {"subc.", XO(31,8,0,1), XO_MASK
, PPCCOM
, EXT
, {RT
, RB
, RA
}},
6883 {"mulhdu", XO(31,9,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6884 {"mulhdu.", XO(31,9,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
6886 {"addc", XO(31,10,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6887 {"a", XO(31,10,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6888 {"addc.", XO(31,10,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
6889 {"a.", XO(31,10,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6891 {"mulhwu", XO(31,11,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6892 {"mulhwu.", XO(31,11,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6894 {"lxsiwzx", X(31,12), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
6896 {"lxvrbx", X(31,13), XX1_MASK
, POWER10
, 0, {XT6
, RA0
, RB
}},
6898 {"isellt", XISEL(31,15,0), X_MASK
, PPCISEL
, EXT
, {RT
, RA0
, RB
}},
6899 {"iselgt", XISEL(31,15,1), X_MASK
, PPCISEL
, EXT
, {RT
, RA0
, RB
}},
6900 {"iseleq", XISEL(31,15,2), X_MASK
, PPCISEL
, EXT
, {RT
, RA0
, RB
}},
6901 {"isel", XISEL(31,15,0), XISEL_MASK
, PPCISEL
|TITAN
, 0, {RT
, RA0
, RB
, BC
}},
6903 {"tlbilxlpid", XTO(31,18,0), XTO_MASK
, E500MC
|PPCA2
, 0, {0}},
6904 {"tlbilxpid", XTO(31,18,1), XTO_MASK
, E500MC
|PPCA2
, 0, {0}},
6905 {"tlbilxva", XTO(31,18,3), XTO_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
6906 {"tlbilx", X(31,18), X_MASK
, E500MC
|PPCA2
, 0, {T
, RA0
, RB
}},
6908 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK
, COM
, 0, {RT
, FXM4
}},
6909 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK
, COM
, 0, {RT
, FXM
}},
6911 {"lwarx", X(31,20), XEH_MASK
, PPC
, 0, {RT
, RA0
, RB
, EH
}},
6913 {"ldx", X(31,21), X_MASK
, PPC64
, 0, {RT
, RA0
, RB
}},
6915 {"icbt", X(31,22), X_MASK
, POWER5
|BOOKE
|PPCE300
, 0, {CT
, RA0
, RB
}},
6917 {"lwzx", X(31,23), X_MASK
, PPCCOM
, 0, {RT
, RA0
, RB
}},
6918 {"lx", X(31,23), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6920 {"slw", XRC(31,24,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6921 {"sl", XRC(31,24,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6922 {"slw.", XRC(31,24,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
6923 {"sl.", XRC(31,24,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
6925 {"cntlzw", XRC(31,26,0), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
6926 {"cntlz", XRC(31,26,0), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
6927 {"cntlzw.", XRC(31,26,1), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
6928 {"cntlz.", XRC(31,26,1), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
6930 {"sld", XRC(31,27,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6931 {"sld.", XRC(31,27,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
6933 {"and", XRC(31,28,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6934 {"and.", XRC(31,28,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6936 {"maskg", XRC(31,29,0), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
6937 {"maskg.", XRC(31,29,1), X_MASK
, M601
, PPCA2
, {RA
, RS
, RB
}},
6939 {"ldepx", X(31,29), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
6941 {"waitasec", X(31,30), XRTRARB_MASK
, POWER8
, POWER9
, {0}},
6942 {"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10
, EXT
, {0}},
6943 {"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10
, EXT
, {0}},
6944 {"wait", X(31,30), XWCPL_MASK
, POWER10
, 0, {WC
, PL
}},
6945 {"wait", X(31,30), XWC_MASK
, POWER9
, POWER10
, {WC
}},
6947 {"lwepx", X(31,31), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
6949 {"cmplw", XOPL(31,32,0), XCMPL_MASK
, PPCCOM
, EXT
, {OBF
, RA
, RB
}},
6950 {"cmpld", XOPL(31,32,1), XCMPL_MASK
, PPC64
, EXT
, {OBF
, RA
, RB
}},
6951 {"cmpl", X(31,32), XCMP_MASK
, PPC
, 0, {BF
, L32OPT
, RA
, RB
}},
6952 {"cmpl", X(31,32), XCMPL_MASK
, PWRCOM
, PPC
, {BF
, RA
, RB
}},
6954 {"lvsr", X(31,38), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6955 {"lvehx", X(31,39), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6956 {"lhfcmx", APU(31,39,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
6958 {"lxvrhx", X(31,45), XX1_MASK
, POWER10
, 0, {XT6
, RA0
, RB
}},
6960 {"mviwsplt", X(31,46), X_MASK
, E6500
, 0, {VD
, RA
, RB
}},
6962 {"lvewx", X(31,71), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
6964 {"addg6s", XO(31,74,0,0), XO_MASK
, POWER6
, 0, {RT
, RA
, RB
}},
6966 {"lxsiwax", X(31,76), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
6968 {"lxvrwx", X(31,77), XX1_MASK
, POWER10
, 0, {XT6
, RA0
, RB
}},
6970 {"subf", XO(31,40,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6971 {"sub", XO(31,40,0,0), XO_MASK
, PPC
, EXT
, {RT
, RB
, RA
}},
6972 {"subf.", XO(31,40,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
6973 {"sub.", XO(31,40,0,1), XO_MASK
, PPC
, EXT
, {RT
, RB
, RA
}},
6975 {"mffprd", X(31,51), XX1RB_MASK
|1, PPCVSX2
, EXT
, {RA
, FRS
}},
6976 {"mfvrd", X(31,51)|1, XX1RB_MASK
|1, PPCVSX2
, EXT
, {RA
, VS
}},
6977 {"mfvsrd", X(31,51), XX1RB_MASK
, PPCVSX2
, 0, {RA
, XS6
}},
6978 {"eratilx", X(31,51), X_MASK
, PPCA2
, 0, {ERAT_T
, RA
, RB
}},
6980 {"lbarx", X(31,52), XEH_MASK
, POWER8
|E6500
, 0, {RT
, RA0
, RB
, EH
}},
6982 {"ldux", X(31,53), X_MASK
, PPC64
, 0, {RT
, RAL
, RB
}},
6984 {"dcbst", X(31,54), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
6986 {"lwzux", X(31,55), X_MASK
, PPCCOM
, 0, {RT
, RAL
, RB
}},
6987 {"lux", X(31,55), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
6989 {"cntlzd", XRC(31,58,0), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
6990 {"cntlzd.", XRC(31,58,1), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
6992 {"cntlzdm", X(31,59), X_MASK
, POWER10
, 0, {RA
, RS
, RB
}},
6994 {"andc", XRC(31,60,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6995 {"andc.", XRC(31,60,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
6997 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC
|PPCA2
, EXT
, {0}},
6998 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC
|PPCA2
, EXT
, {0}},
6999 {"wait", X(31,62), XWC_MASK
, E500MC
|PPCA2
, 0, {WC
}},
7001 {"dcbstep", XRT(31,63,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
7003 {"tdlgt", XTO(31,68,TOLGT
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7004 {"tdllt", XTO(31,68,TOLLT
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7005 {"tdeq", XTO(31,68,TOEQ
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7006 {"tdlge", XTO(31,68,TOLGE
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7007 {"tdlnl", XTO(31,68,TOLNL
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7008 {"tdlle", XTO(31,68,TOLLE
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7009 {"tdlng", XTO(31,68,TOLNG
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7010 {"tdgt", XTO(31,68,TOGT
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7011 {"tdge", XTO(31,68,TOGE
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7012 {"tdnl", XTO(31,68,TONL
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7013 {"tdlt", XTO(31,68,TOLT
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7014 {"tdle", XTO(31,68,TOLE
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7015 {"tdng", XTO(31,68,TONG
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7016 {"tdne", XTO(31,68,TONE
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7017 {"tdu", XTO(31,68,TOU
), XTO_MASK
, PPC64
, EXT
, {RA
, RB
}},
7018 {"td", X(31,68), X_MASK
, PPC64
, 0, {TO
, RA
, RB
}},
7020 {"lwfcmx", APU(31,71,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7021 {"mulhd", XO(31,73,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7022 {"mulhd.", XO(31,73,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7024 {"mulhw", XO(31,75,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7025 {"mulhw.", XO(31,75,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7027 {"msgsndu", XRTRA(31,78,0,0), XRTRA_MASK
, POWER9
, 0, {RB
}},
7028 {"dlmzb", XRC(31,78,0), X_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA
, RS
, RB
}},
7029 {"dlmzb.", XRC(31,78,1), X_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA
, RS
, RB
}},
7031 {"mtsrd", X(31,82), XRB_MASK
|(1<<20), PPC64
, 0, {SR
, RS
}},
7033 {"mfmsr", X(31,83), XRARB_MASK
, COM
, 0, {RT
}},
7035 {"ldarx", X(31,84), XEH_MASK
, PPC64
, 0, {RT
, RA0
, RB
, EH
}},
7037 {"dcbfl", XOPL(31,86,1), XRT_MASK
, POWER5
, PPC476
|EXT
, {RA0
, RB
}},
7038 {"dcbflp", XOPL2(31,86,3), XRT_MASK
, POWER9
, PPC476
|EXT
, {RA0
, RB
}},
7039 {"dcbfps", XOPL3(31,86,4), XRT_MASK
, POWER10
, PPC476
|EXT
, {RA0
, RB
}},
7040 {"dcbstps", XOPL3(31,86,6), XRT_MASK
, POWER10
, PPC476
|EXT
, {RA0
, RB
}},
7041 {"dcbf", X(31,86), XL3RT_MASK
, POWER10
, PPC476
, {RA0
, RB
, L3OPT
}},
7042 {"dcbf", X(31,86), XLRT_MASK
, PPC
, POWER10
, {RA0
, RB
, L2OPT
}},
7044 {"lbzx", X(31,87), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
7046 {"lbepx", X(31,95), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
7048 {"dni", XRC(31,97,1), XRB_MASK
, E6500
, 0, {DUI
, DCTL
}},
7050 {"lvx", X(31,103), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
7051 {"lqfcmx", APU(31,103,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7053 {"neg", XO(31,104,0,0), XORB_MASK
, COM
, 0, {RT
, RA
}},
7054 {"neg.", XO(31,104,0,1), XORB_MASK
, COM
, 0, {RT
, RA
}},
7056 {"mul", XO(31,107,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7057 {"mul.", XO(31,107,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7059 {"lxvrdx", X(31,109), XX1_MASK
, POWER10
, 0, {XT6
, RA0
, RB
}},
7061 {"msgclru", XRTRA(31,110,0,0), XRTRA_MASK
, POWER9
, 0, {RB
}},
7062 {"mvidsplt", X(31,110), X_MASK
, E6500
, 0, {VD
, RA
, RB
}},
7064 {"mtsrdin", X(31,114), XRA_MASK
, PPC64
, 0, {RS
, RB
}},
7066 {"mffprwz", X(31,115), XX1RB_MASK
|1, PPCVSX2
, EXT
, {RA
, FRS
}},
7067 {"mfvrwz", X(31,115)|1, XX1RB_MASK
|1, PPCVSX2
, EXT
, {RA
, VS
}},
7068 {"mfvsrwz", X(31,115), XX1RB_MASK
, PPCVSX2
, 0, {RA
, XS6
}},
7070 {"lharx", X(31,116), XEH_MASK
, POWER8
|E6500
, 0, {RT
, RA0
, RB
, EH
}},
7072 {"clf", X(31,118), XTO_MASK
, POWER
, 0, {RA
, RB
}},
7074 {"lbzux", X(31,119), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
7076 {"popcntb", X(31,122), XRB_MASK
, POWER5
, 0, {RA
, RS
}},
7078 {"not", XRC(31,124,0), X_MASK
, COM
, EXT
, {RA
, RSB
}},
7079 {"nor", XRC(31,124,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7080 {"not.", XRC(31,124,1), X_MASK
, COM
, EXT
, {RA
, RSB
}},
7081 {"nor.", XRC(31,124,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7083 {"dcbfep", XRT(31,127,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
7085 {"setb", X(31,128), XRB_MASK
|(3<<16), POWER9
, 0, {RT
, BFA
}},
7087 {"wrtee", X(31,131), XRARB_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RS
}},
7089 {"dcbtstls", X(31,134), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
7091 {"stvebx", X(31,135), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
7092 {"stbfcmx", APU(31,135,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7094 {"subfe", XO(31,136,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7095 {"sfe", XO(31,136,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7096 {"subfe.", XO(31,136,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7097 {"sfe.", XO(31,136,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7099 {"adde", XO(31,138,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7100 {"ae", XO(31,138,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7101 {"adde.", XO(31,138,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7102 {"ae.", XO(31,138,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7104 {"stxsiwx", X(31,140), XX1_MASK
, PPCVSX2
, 0, {XS6
, RA0
, RB
}},
7106 {"stxvrbx", X(31,141), XX1_MASK
, POWER10
, 0, {XT6
, RA0
, RB
}},
7108 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK
, POWER8
, 0, {RB
}},
7109 {"dcbtstlse", X(31,142), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
7111 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK
, COM
, EXT
, {RS
}},
7112 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK
, COM
, 0, {FXM
, RS
}},
7113 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK
, COM
, 0, {FXM
, RS
}},
7115 {"mtmsr", X(31,146), XRLARB_MASK
, COM
, 0, {RS
, A_L
}},
7117 {"mtsle", X(31,147), XRTLRARB_MASK
, POWER8
, 0, {L
}},
7118 {"eratsx", XRC(31,147,0), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
7119 {"eratsx.", XRC(31,147,1), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
7121 {"stdx", X(31,149), X_MASK
, PPC64
, 0, {RS
, RA0
, RB
}},
7123 {"stwcx.", XRC(31,150,1), X_MASK
, PPC
, 0, {RS
, RA0
, RB
}},
7125 {"stwx", X(31,151), X_MASK
, PPCCOM
, 0, {RS
, RA0
, RB
}},
7126 {"stx", X(31,151), X_MASK
, PWRCOM
, 0, {RS
, RA
, RB
}},
7128 {"slq", XRC(31,152,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7129 {"slq.", XRC(31,152,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7131 {"sle", XRC(31,153,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7132 {"sle.", XRC(31,153,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7134 {"prtyw", X(31,154), XRB_MASK
, POWER6
|PPCA2
|PPC476
, 0, {RA
, RS
}},
7136 {"brw", X(31,155), XRB_MASK
, POWER10
, 0, {RA
, RS
}},
7137 {"pdepd", X(31,156), X_MASK
, POWER10
, 0, {RA
, RS
, RB
}},
7139 {"stdepx", X(31,157), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
7141 {"stwepx", X(31,159), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
7143 {"wrteei", X(31,163), XE_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {E
}},
7145 {"dcbtls", X(31,166), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
7147 {"stvehx", X(31,167), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
7148 {"sthfcmx", APU(31,167,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7150 {"addex", ZRC(31,170,0), Z2_MASK
, POWER9
, 0, {RT
, RA
, RB
, CY
}},
7152 {"stxvrhx", X(31,173), XX1_MASK
, POWER10
, 0, {XT6
, RA0
, RB
}},
7154 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK
, POWER8
, 0, {RB
}},
7155 {"dcbtlse", X(31,174), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA0
, RB
}},
7157 {"xxmfacc", XVA(31,177,0), XRARB_MASK
|3<<21, POWER10
, 0, {ACC
}},
7158 {"xxmtacc", XVA(31,177,1), XRARB_MASK
|3<<21, POWER10
, 0, {ACC
}},
7159 {"xxsetaccz", XVA(31,177,3), XRARB_MASK
|3<<21, POWER10
, 0, {ACC
}},
7161 {"mtmsrd", X(31,178), XRLARB_MASK
, PPC64
, 0, {RS
, A_L
}},
7163 {"mtfprd", X(31,179), XX1RB_MASK
|1, PPCVSX2
, EXT
, {FRT
, RA
}},
7164 {"mtvrd", X(31,179)|1, XX1RB_MASK
|1, PPCVSX2
, EXT
, {VD
, RA
}},
7165 {"mtvsrd", X(31,179), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
7166 {"eratre", X(31,179), X_MASK
, PPCA2
, 0, {RT
, RA
, WS
}},
7168 {"stdux", X(31,181), X_MASK
, PPC64
, 0, {RS
, RAS
, RB
}},
7170 {"stqcx.", XRC(31,182,1), X_MASK
|Q_MASK
, POWER8
, 0, {RSQ
, RA0
, RB
}},
7171 {"wchkall", X(31,182), X_MASK
, PPCA2
, 0, {OBF
}},
7173 {"stwux", X(31,183), X_MASK
, PPCCOM
, 0, {RS
, RAS
, RB
}},
7174 {"stux", X(31,183), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
7176 {"sliq", XRC(31,184,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
7177 {"sliq.", XRC(31,184,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
7179 {"prtyd", X(31,186), XRB_MASK
, POWER6
|PPCA2
, 0, {RA
, RS
}},
7181 {"brd", X(31,187), XRB_MASK
, POWER10
, 0, {RA
, RS
}},
7182 {"pextd", X(31,188), X_MASK
, POWER10
, 0, {RA
, RS
, RB
}},
7184 {"cmprb", X(31,192), XCMP_MASK
, POWER9
, 0, {BF
, L
, RA
, RB
}},
7186 {"icblq.", XRC(31,198,1), X_MASK
, E6500
, 0, {CT
, RA0
, RB
}},
7188 {"stvewx", X(31,199), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
7189 {"stwfcmx", APU(31,199,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7191 {"subfze", XO(31,200,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7192 {"sfze", XO(31,200,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7193 {"subfze.", XO(31,200,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7194 {"sfze.", XO(31,200,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7196 {"addze", XO(31,202,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7197 {"aze", XO(31,202,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7198 {"addze.", XO(31,202,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7199 {"aze.", XO(31,202,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7201 {"stxvrwx", X(31,205), XX1_MASK
, POWER10
, 0, {XT6
, RA0
, RB
}},
7203 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
, 0, {RB
}},
7205 {"mtsr", X(31,210), XRB_MASK
|(1<<20), COM
, NON32
, {SR
, RS
}},
7207 {"mtfprwa", X(31,211), XX1RB_MASK
|1, PPCVSX2
, EXT
, {FRT
, RA
}},
7208 {"mtvrwa", X(31,211)|1, XX1RB_MASK
|1, PPCVSX2
, EXT
, {VD
, RA
}},
7209 {"mtvsrwa", X(31,211), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
7210 {"eratwe", X(31,211), X_MASK
, PPCA2
, 0, {RS
, RA
, WS
}},
7212 {"ldawx.", XRC(31,212,1), X_MASK
, PPCA2
, 0, {RT
, RA0
, RB
}},
7214 {"stdcx.", XRC(31,214,1), X_MASK
, PPC64
, 0, {RS
, RA0
, RB
}},
7216 {"stbx", X(31,215), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
7218 {"sllq", XRC(31,216,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7219 {"sllq.", XRC(31,216,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7221 {"sleq", XRC(31,217,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7222 {"sleq.", XRC(31,217,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
7224 {"brh", X(31,219), XRB_MASK
, POWER10
, 0, {RA
, RS
}},
7225 {"cfuged", X(31,220), X_MASK
, POWER10
, 0, {RA
, RS
, RB
}},
7227 {"stbepx", X(31,223), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
7229 {"cmpeqb", X(31,224), XCMPL_MASK
, POWER9
, 0, {BF
, RA
, RB
}},
7231 {"icblc", X(31,230), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
7233 {"stvx", X(31,231), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
7234 {"stqfcmx", APU(31,231,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7236 {"subfme", XO(31,232,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7237 {"sfme", XO(31,232,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7238 {"subfme.", XO(31,232,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7239 {"sfme.", XO(31,232,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7241 {"mulld", XO(31,233,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7242 {"mulld.", XO(31,233,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7244 {"addme", XO(31,234,0,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7245 {"ame", XO(31,234,0,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7246 {"addme.", XO(31,234,0,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
7247 {"ame.", XO(31,234,0,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
7249 {"mullw", XO(31,235,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7250 {"muls", XO(31,235,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7251 {"mullw.", XO(31,235,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7252 {"muls.", XO(31,235,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7254 {"stxvrdx", X(31,237), XX1_MASK
, POWER10
, 0, {XT6
, RA0
, RB
}},
7256 {"icblce", X(31,238), X_MASK
, PPCCHLK
, E500MC
|PPCA2
, {CT
, RA
, RB
}},
7257 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK
, E500MC
|PPCA2
|POWER8
, 0, {RB
}},
7258 {"mtsrin", X(31,242), XRA_MASK
, PPC
, NON32
, {RS
, RB
}},
7259 {"mtsri", X(31,242), XRA_MASK
, POWER
, NON32
, {RS
, RB
}},
7261 {"mtfprwz", X(31,243), XX1RB_MASK
|1, PPCVSX2
, EXT
, {FRT
, RA
}},
7262 {"mtvrwz", X(31,243)|1, XX1RB_MASK
|1, PPCVSX2
, EXT
, {VD
, RA
}},
7263 {"mtvsrwz", X(31,243), XX1RB_MASK
, PPCVSX2
, 0, {XT6
, RA
}},
7265 {"dcbtstt", XRT(31,246,0x10), XRT_MASK
, POWER7
, EXT
, {RA0
, RB
}},
7266 {"dcbtstct", X(31,246), X_MASK
, POWER4
, EXT
, {RA0
, RB
, THCT
}},
7267 {"dcbtstds", X(31,246), X_MASK
, POWER4
, EXT
, {RA0
, RB
, THDS
}},
7268 {"dcbtst", X(31,246), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
7269 {"dcbtst", X(31,246), X_MASK
, DCBT_EO
, 0, {CT
, RA0
, RB
}},
7270 {"dcbtst", X(31,246), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
7272 {"stbux", X(31,247), X_MASK
, COM
, 0, {RS
, RAS
, RB
}},
7274 {"slliq", XRC(31,248,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
7275 {"slliq.", XRC(31,248,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
7277 {"bpermd", X(31,252), X_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
, RB
}},
7279 {"dcbtstep", XRT(31,255,0), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
7281 {"mfdcrx", X(31,259), X_MASK
, BOOKE
|PPCA2
|PPC476
, TITAN
, {RS
, RA
}},
7282 {"mfdcrx.", XRC(31,259,1), X_MASK
, PPCA2
, 0, {RS
, RA
}},
7284 {"lvexbx", X(31,261), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7286 {"icbt", X(31,262), XRT_MASK
, PPC403
, 0, {RA
, RB
}},
7288 {"lvepxl", X(31,263), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7289 {"ldfcmx", APU(31,263,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7291 {"doz", XO(31,264,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7292 {"doz.", XO(31,264,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7294 {"modud", X(31,265), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
7296 {"add", XO(31,266,0,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7297 {"cax", XO(31,266,0,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7298 {"add.", XO(31,266,0,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
7299 {"cax.", XO(31,266,0,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
7301 {"moduw", X(31,267), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
7303 {"lxvx", X(31,268), XX1_MASK
|1<<6, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
7304 {"lxvl", X(31,269), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
7306 {"ehpriv", X(31,270), 0xffffffff, E500MC
|PPCA2
, 0, {0}},
7308 {"tlbiel", X(31,274), X_MASK
|1<<20,POWER9
, 0, {RB
, RSO
, RIC
, PRS
, X_R
}},
7309 {"tlbiel", X(31,274), XRTLRA_MASK
, POWER4
, POWER9
|PPC476
, {RB
, LOPT
}},
7311 {"mfapidi", X(31,275), X_MASK
, BOOKE
, E500
|TITAN
, {RT
, RA
}},
7313 {"lqarx", X(31,276), XEH_MASK
|Q_MASK
, POWER8
, 0, {RTQ
, RAX
, RBX
, EH
}},
7315 {"lscbx", XRC(31,277,0), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
7316 {"lscbx.", XRC(31,277,1), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
7318 {"dcbtt", XRT(31,278,0x10), XRT_MASK
, POWER7
, EXT
, {RA0
, RB
}},
7319 {"dcbna", XRT(31,278,0x11), XRT_MASK
, POWER10
, EXT
, {RA0
, RB
}},
7320 {"dcbtct", X(31,278), X_MASK
, POWER4
, EXT
, {RA0
, RB
, THCT
}},
7321 {"dcbtds", X(31,278), X_MASK
, POWER4
, EXT
, {RA0
, RB
, THDS
}},
7322 {"dcbt", X(31,278), X_MASK
, POWER4
, DCBT_EO
, {RA0
, RB
, CT
}},
7323 {"dcbt", X(31,278), X_MASK
, DCBT_EO
, 0, {CT
, RA0
, RB
}},
7324 {"dcbt", X(31,278), X_MASK
, PPC
, POWER4
|DCBT_EO
, {RA0
, RB
}},
7326 {"lhzx", X(31,279), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
7328 {"cdtbcd", X(31,282), XRB_MASK
, POWER6
, 0, {RA
, RS
}},
7330 {"eqv", XRC(31,284,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7331 {"eqv.", XRC(31,284,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7333 {"lhepx", X(31,287), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
7335 {"mfdcrux", X(31,291), X_MASK
, PPC464
|PPC476
, 0, {RS
, RA
}},
7337 {"lvexhx", X(31,293), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7338 {"lvepx", X(31,295), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7340 {"lxvll", X(31,301), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
7342 {"mfbhrbe", X(31,302), X_MASK
, POWER8
, 0, {RT
, BHRBE
}},
7344 {"tlbie", X(31,306), X_MASK
|1<<20,POWER9
, TITAN
, {RB
, RS
, RIC
, PRS
, X_R
}},
7345 {"tlbie", X(31,306), XRA_MASK
, POWER7
, POWER9
|TITAN
, {RB
, RS
}},
7346 {"tlbie", X(31,306), XRTLRA_MASK
, PPC
, E500
|POWER7
|TITAN
, {RB
, LOPT
}},
7347 {"tlbi", X(31,306), XRT_MASK
, POWER
, 0, {RA0
, RB
}},
7349 {"mfvsrld", X(31,307), XX1RB_MASK
, PPCVSX3
, 0, {RA
, XS6
}},
7351 {"eciwx", X(31,310), X_MASK
, PPC
, E500
|TITAN
, {RT
, RA0
, RB
}},
7353 {"lhzux", X(31,311), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
7355 {"cbcdtd", X(31,314), XRB_MASK
, POWER6
, 0, {RA
, RS
}},
7357 {"xor", XRC(31,316,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7358 {"xor.", XRC(31,316,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7360 {"dcbtep", XRT(31,319,0), X_MASK
, E500MC
|PPCA2
, 0, {RT
, RA0
, RB
}},
7362 {"mfexisr", XSPR(31,323, 64), XSPR_MASK
, PPC403
, 0, {RT
}},
7363 {"mfexier", XSPR(31,323, 66), XSPR_MASK
, PPC403
, 0, {RT
}},
7364 {"mfbr0", XSPR(31,323,128), XSPR_MASK
, PPC403
, 0, {RT
}},
7365 {"mfbr1", XSPR(31,323,129), XSPR_MASK
, PPC403
, 0, {RT
}},
7366 {"mfbr2", XSPR(31,323,130), XSPR_MASK
, PPC403
, 0, {RT
}},
7367 {"mfbr3", XSPR(31,323,131), XSPR_MASK
, PPC403
, 0, {RT
}},
7368 {"mfbr4", XSPR(31,323,132), XSPR_MASK
, PPC403
, 0, {RT
}},
7369 {"mfbr5", XSPR(31,323,133), XSPR_MASK
, PPC403
, 0, {RT
}},
7370 {"mfbr6", XSPR(31,323,134), XSPR_MASK
, PPC403
, 0, {RT
}},
7371 {"mfbr7", XSPR(31,323,135), XSPR_MASK
, PPC403
, 0, {RT
}},
7372 {"mfbear", XSPR(31,323,144), XSPR_MASK
, PPC403
, 0, {RT
}},
7373 {"mfbesr", XSPR(31,323,145), XSPR_MASK
, PPC403
, 0, {RT
}},
7374 {"mfiocr", XSPR(31,323,160), XSPR_MASK
, PPC403
, 0, {RT
}},
7375 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK
, PPC403
, 0, {RT
}},
7376 {"mfdmact0", XSPR(31,323,193), XSPR_MASK
, PPC403
, 0, {RT
}},
7377 {"mfdmada0", XSPR(31,323,194), XSPR_MASK
, PPC403
, 0, {RT
}},
7378 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK
, PPC403
, 0, {RT
}},
7379 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK
, PPC403
, 0, {RT
}},
7380 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK
, PPC403
, 0, {RT
}},
7381 {"mfdmact1", XSPR(31,323,201), XSPR_MASK
, PPC403
, 0, {RT
}},
7382 {"mfdmada1", XSPR(31,323,202), XSPR_MASK
, PPC403
, 0, {RT
}},
7383 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK
, PPC403
, 0, {RT
}},
7384 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK
, PPC403
, 0, {RT
}},
7385 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK
, PPC403
, 0, {RT
}},
7386 {"mfdmact2", XSPR(31,323,209), XSPR_MASK
, PPC403
, 0, {RT
}},
7387 {"mfdmada2", XSPR(31,323,210), XSPR_MASK
, PPC403
, 0, {RT
}},
7388 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK
, PPC403
, 0, {RT
}},
7389 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK
, PPC403
, 0, {RT
}},
7390 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK
, PPC403
, 0, {RT
}},
7391 {"mfdmact3", XSPR(31,323,217), XSPR_MASK
, PPC403
, 0, {RT
}},
7392 {"mfdmada3", XSPR(31,323,218), XSPR_MASK
, PPC403
, 0, {RT
}},
7393 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK
, PPC403
, 0, {RT
}},
7394 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK
, PPC403
, 0, {RT
}},
7395 {"mfdmasr", XSPR(31,323,224), XSPR_MASK
, PPC403
, 0, {RT
}},
7396 {"mfdcr", X(31,323), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, E500
|TITAN
, {RT
, SPR
}},
7397 {"mfdcr.", XRC(31,323,1), X_MASK
, PPCA2
, 0, {RT
, SPR
}},
7399 {"lvexwx", X(31,325), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
7401 {"dcread", X(31,326), X_MASK
, PPC476
|TITAN
, 0, {RT
, RA0
, RB
}},
7403 {"div", XO(31,331,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7404 {"div.", XO(31,331,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7406 {"lxvdsx", X(31,332), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
7408 {"lxvpx", X(31,333), XX1_MASK
, POWER10
, 0, {XTP
, RA0
, RB
}},
7410 {"mfpmr", X(31,334), X_MASK
, PPCPMR
|PPCE300
, 0, {RT
, PMR
}},
7411 {"mftmr", X(31,366), X_MASK
, PPCTMR
, 0, {RT
, TMR
}},
7413 {"slbsync", X(31,338), 0xffffffff, POWER9
, 0, {0}},
7415 {"mfmq", XSPR(31,339, 0), XSPR_MASK
, M601
, EXT
, {RT
}},
7416 {"mfxer", XSPR(31,339, 1), XSPR_MASK
, COM
, EXT
, {RT
}},
7417 {"mfudscr", XSPR(31,339, 3), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7418 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK
, COM
, TITAN
|EXT
, {RT
}},
7419 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK
, COM
, TITAN
|EXT
, {RT
}},
7420 {"mfdec", XSPR(31,339, 6), XSPR_MASK
, MFDEC1
, EXT
, {RT
}},
7421 {"mflr", XSPR(31,339, 8), XSPR_MASK
, COM
, EXT
, {RT
}},
7422 {"mfctr", XSPR(31,339, 9), XSPR_MASK
, COM
, EXT
, {RT
}},
7423 {"mfuamr", XSPR(31,339, 13), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7424 {"mfdscr", XSPR(31,339, 17), XSPR_MASK
, POWER6
, EXT
, {RT
}},
7425 {"mftid", XSPR(31,339, 17), XSPR_MASK
, POWER
, EXT
, {RT
}},
7426 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK
, COM
, TITAN
|EXT
, {RT
}},
7427 {"mfdar", XSPR(31,339, 19), XSPR_MASK
, COM
, TITAN
|EXT
, {RT
}},
7428 {"mfdec", XSPR(31,339, 22), XSPR_MASK
, MFDEC2
, MFDEC1
|EXT
, {RT
}},
7429 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK
, POWER
, EXT
, {RT
}},
7430 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK
, COM
, TITAN
|EXT
, {RT
}},
7431 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK
, COM
, EXT
, {RT
}},
7432 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK
, COM
, EXT
, {RT
}},
7433 {"mfcfar", XSPR(31,339, 28), XSPR_MASK
, POWER6
, EXT
, {RT
}},
7434 {"mfamr", XSPR(31,339, 29), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7435 {"mfpidr", XSPR(31,339, 48), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7436 {"mfpid", XSPR(31,339, 48), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7437 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7438 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7439 {"mfiamr", XSPR(31,339, 61), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7440 {"mfdear", XSPR(31,339, 61), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7441 {"mfesr", XSPR(31,339, 62), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7442 {"mfivpr", XSPR(31,339, 63), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7443 {"mfctrl", XSPR(31,339,136), XSPR_MASK
, POWER4
, EXT
, {RT
}},
7444 {"mfcmpa", XSPR(31,339,144), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7445 {"mfcmpb", XSPR(31,339,145), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7446 {"mfcmpc", XSPR(31,339,146), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7447 {"mfcmpd", XSPR(31,339,147), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7448 {"mficr", XSPR(31,339,148), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7449 {"mfder", XSPR(31,339,149), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7450 {"mfcounta", XSPR(31,339,150), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7451 {"mfcountb", XSPR(31,339,151), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7452 {"mfcmpe", XSPR(31,339,152), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7453 {"mffscr", XSPR(31,339,153), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7454 {"mfcmpf", XSPR(31,339,153), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7455 {"mfcmpg", XSPR(31,339,154), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7456 {"mfcmph", XSPR(31,339,155), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7457 {"mflctrl1", XSPR(31,339,156), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7458 {"mfuamor", XSPR(31,339,157), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7459 {"mflctrl2", XSPR(31,339,157), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7460 {"mfictrl", XSPR(31,339,158), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7461 {"mfpspb", XSPR(31,339,159), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7462 {"mfbar", XSPR(31,339,159), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7463 {"mfdpdes", XSPR(31,339,176), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7464 {"mfdawr0", XSPR(31,339,180), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7465 {"mfdawr1", XSPR(31,339,181), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7466 {"mfrpr", XSPR(31,339,186), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7467 {"mfciabr", XSPR(31,339,187), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7468 {"mfdawrx0", XSPR(31,339,188), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7469 {"mfdawrx1", XSPR(31,339,189), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7470 {"mfhfscr", XSPR(31,339,190), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7471 {"mfvrsave", XSPR(31,339,256), XSPR_MASK
, PPCVEC
, EXT
, {RT
}},
7472 {"mfusprg0", XSPR(31,339,256), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7473 {"mfsprg", XSPR(31,339,256), XSPRG_MASK
, PPC
, EXT
, {RT
, SPRG
}},
7474 {"mfusprg3", XSPR(31,339,259), XSPR_MASK
, POWER10
, EXT
, {RT
}},
7475 {"mfsprg4", XSPR(31,339,260), XSPR_MASK
, PPC405
|BOOKE
, EXT
, {RT
}},
7476 {"mfsprg5", XSPR(31,339,261), XSPR_MASK
, PPC405
|BOOKE
, EXT
, {RT
}},
7477 {"mfsprg6", XSPR(31,339,262), XSPR_MASK
, PPC405
|BOOKE
, EXT
, {RT
}},
7478 {"mfsprg7", XSPR(31,339,263), XSPR_MASK
, PPC405
|BOOKE
, EXT
, {RT
}},
7479 {"mftbu", XSPR(31,339,269), XSPR_MASK
, POWER4
|BOOKE
, EXT
, {RT
}},
7480 {"mftb", X(31,339), X_MASK
, POWER4
|BOOKE
, EXT
, {RT
, TBR
}},
7481 {"mftbl", XSPR(31,339,268), XSPR_MASK
, POWER4
|BOOKE
, EXT
, {RT
}},
7482 {"mfsprg0", XSPR(31,339,272), XSPR_MASK
, PPC
, EXT
, {RT
}},
7483 {"mfsprg1", XSPR(31,339,273), XSPR_MASK
, PPC
, EXT
, {RT
}},
7484 {"mfsprg2", XSPR(31,339,274), XSPR_MASK
, PPC
, EXT
, {RT
}},
7485 {"mfsprg3", XSPR(31,339,275), XSPR_MASK
, PPC
, EXT
, {RT
}},
7486 {"mfasr", XSPR(31,339,280), XSPR_MASK
, PPC64
, EXT
, {RT
}},
7487 {"mfear", XSPR(31,339,282), XSPR_MASK
, PPC
, TITAN
|EXT
, {RT
}},
7488 {"mfpir", XSPR(31,339,286), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7489 {"mfpvr", XSPR(31,339,287), XSPR_MASK
, PPC
, EXT
, {RT
}},
7490 {"mfhsprg0", XSPR(31,339,304), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7491 {"mfdbsr", XSPR(31,339,304), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7492 {"mfhsprg1", XSPR(31,339,305), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7493 {"mfhdisr", XSPR(31,339,306), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7494 {"mfhdar", XSPR(31,339,307), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7495 {"mfspurr", XSPR(31,339,308), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7496 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7497 {"mfpurr", XSPR(31,339,309), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7498 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7499 {"mfhdec", XSPR(31,339,310), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7500 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7501 {"mfiac1", XSPR(31,339,312), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7502 {"mfhrmor", XSPR(31,339,313), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7503 {"mfiac2", XSPR(31,339,313), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7504 {"mfhsrr0", XSPR(31,339,314), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7505 {"mfiac3", XSPR(31,339,314), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7506 {"mfhsrr1", XSPR(31,339,315), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7507 {"mfiac4", XSPR(31,339,315), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7508 {"mfdac1", XSPR(31,339,316), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7509 {"mfdac2", XSPR(31,339,317), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7510 {"mflpcr", XSPR(31,339,318), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7511 {"mfdvc1", XSPR(31,339,318), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7512 {"mflpidr", XSPR(31,339,319), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7513 {"mfdvc2", XSPR(31,339,319), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7514 {"mfhmer", XSPR(31,339,336), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7515 {"mftsr", XSPR(31,339,336), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7516 {"mfhmeer", XSPR(31,339,337), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7517 {"mfpcr", XSPR(31,339,338), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7518 {"mfheir", XSPR(31,339,339), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7519 {"mftcr", XSPR(31,339,340), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7520 {"mfamor", XSPR(31,339,349), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7521 {"mfivor0", XSPR(31,339,400), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7522 {"mfivor1", XSPR(31,339,401), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7523 {"mfivor2", XSPR(31,339,402), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7524 {"mfivor3", XSPR(31,339,403), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7525 {"mfivor4", XSPR(31,339,404), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7526 {"mfivor5", XSPR(31,339,405), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7527 {"mfivor6", XSPR(31,339,406), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7528 {"mfivor7", XSPR(31,339,407), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7529 {"mfivor8", XSPR(31,339,408), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7530 {"mfivor9", XSPR(31,339,409), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7531 {"mfivor10", XSPR(31,339,410), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7532 {"mfivor11", XSPR(31,339,411), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7533 {"mfivor12", XSPR(31,339,412), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7534 {"mfivor13", XSPR(31,339,413), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7535 {"mfivor14", XSPR(31,339,414), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7536 {"mfivor15", XSPR(31,339,415), XSPR_MASK
, BOOKE
, EXT
, {RT
}},
7537 {"mftir", XSPR(31,339,446), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7538 {"mfptcr", XSPR(31,339,464), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7539 {"mfusprg0", XSPR(31,339,496), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7540 {"mfusprg1", XSPR(31,339,497), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7541 {"mfurmor", XSPR(31,339,505), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7542 {"mfusrr0", XSPR(31,339,506), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7543 {"mfusrr1", XSPR(31,339,507), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7544 {"mfsmfctrl", XSPR(31,339,511), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7545 {"mfspefscr", XSPR(31,339,512), XSPR_MASK
, PPCSPE
, EXT
, {RT
}},
7546 {"mfbbear", XSPR(31,339,513), XSPR_MASK
, PPCBRLK
, EXT
, {RT
}},
7547 {"mfbbtar", XSPR(31,339,514), XSPR_MASK
, PPCBRLK
, EXT
, {RT
}},
7548 {"mfivor32", XSPR(31,339,528), XSPR_MASK
, PPCSPE
|E6500
, EXT
, {RT
}},
7549 {"mfivor33", XSPR(31,339,529), XSPR_MASK
, PPCSPE
|E6500
, EXT
, {RT
}},
7550 {"mfivor34", XSPR(31,339,530), XSPR_MASK
, PPCSPE
, EXT
, {RT
}},
7551 {"mfivor35", XSPR(31,339,531), XSPR_MASK
, PPCPMR
, EXT
, {RT
}},
7552 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK
, PPC
, TITAN
|EXT
, {RT
, SPRBAT
}},
7553 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK
, PPC
, TITAN
|EXT
, {RT
, SPRBAT
}},
7554 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK
, PPC
, TITAN
|EXT
, {RT
, SPRBAT
}},
7555 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK
, PPC
, TITAN
|EXT
, {RT
, SPRBAT
}},
7556 {"mfic_cst", XSPR(31,339,560), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7557 {"mfic_adr", XSPR(31,339,561), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7558 {"mfic_dat", XSPR(31,339,562), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7559 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7560 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7561 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7562 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK
, PPCRFMCI
, EXT
, {RT
}},
7563 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK
, PPCRFMCI
, EXT
, {RT
}},
7564 {"mfmcsr", XSPR(31,339,572), XSPR_MASK
, PPCRFMCI
, EXT
, {RT
}},
7565 {"mfmcar", XSPR(31,339,573), XSPR_MASK
, PPCRFMCI
, TITAN
|EXT
, {RT
}},
7566 {"mfdpdr", XSPR(31,339,630), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7567 {"mfdpir", XSPR(31,339,631), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7568 {"mfimmr", XSPR(31,339,638), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7569 {"mfusier2", XSPR(31,339,736), XSPR_MASK
, POWER10
, EXT
, {RT
}},
7570 {"mfsier2", XSPR(31,339,736), XSPR_MASK
, POWER10
, EXT
, {RT
}},
7571 {"mfusier3", XSPR(31,339,737), XSPR_MASK
, POWER10
, EXT
, {RT
}},
7572 {"mfsier3", XSPR(31,339,737), XSPR_MASK
, POWER10
, EXT
, {RT
}},
7573 {"mfummcr3", XSPR(31,339,738), XSPR_MASK
, POWER10
, EXT
, {RT
}},
7574 {"mfmmcr3", XSPR(31,339,738), XSPR_MASK
, POWER10
, EXT
, {RT
}},
7575 {"mfusier", XSPR(31,339,768), XSPR_MASK
, POWER10
, EXT
, {RT
}},
7576 {"mfsier", XSPR(31,339,768), XSPR_MASK
, POWER10
, EXT
, {RT
}},
7577 {"mfummcr2", XSPR(31,339,769), XSPR_MASK
, POWER9
, EXT
, {RT
}},
7578 {"mfmmcr2", XSPR(31,339,769), XSPR_MASK
, POWER9
, EXT
, {RT
}},
7579 {"mfummcra", XSPR(31,339,770), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7580 {"mfmmcra", XSPR(31,339,770), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7581 {"mfupmc1", XSPR(31,339,771), XSPR_MASK
, POWER9
, EXT
, {RT
}},
7582 {"mfpmc1", XSPR(31,339,771), XSPR_MASK
, POWER7
, EXT
, {RT
}},
7583 {"mfupmc2", XSPR(31,339,772), XSPR_MASK
, POWER9
, EXT
, {RT
}},
7584 {"mfpmc2", XSPR(31,339,772), XSPR_MASK
, POWER7
, EXT
, {RT
}},
7585 {"mfupmc3", XSPR(31,339,773), XSPR_MASK
, POWER9
, EXT
, {RT
}},
7586 {"mfpmc3", XSPR(31,339,773), XSPR_MASK
, POWER7
, EXT
, {RT
}},
7587 {"mfupmc4", XSPR(31,339,774), XSPR_MASK
, POWER9
, EXT
, {RT
}},
7588 {"mfpmc4", XSPR(31,339,774), XSPR_MASK
, POWER7
, EXT
, {RT
}},
7589 {"mfupmc5", XSPR(31,339,775), XSPR_MASK
, POWER9
, EXT
, {RT
}},
7590 {"mfpmc5", XSPR(31,339,775), XSPR_MASK
, POWER7
, EXT
, {RT
}},
7591 {"mfupmc6", XSPR(31,339,776), XSPR_MASK
, POWER9
, EXT
, {RT
}},
7592 {"mfpmc6", XSPR(31,339,776), XSPR_MASK
, POWER7
, EXT
, {RT
}},
7593 {"mfummcr0", XSPR(31,339,779), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7594 {"mfmmcr0", XSPR(31,339,779), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7595 {"mfusiar", XSPR(31,339,780), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7596 {"mfsiar", XSPR(31,339,780), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7597 {"mfusdar", XSPR(31,339,781), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7598 {"mfsdar", XSPR(31,339,781), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7599 {"mfummcr1", XSPR(31,339,782), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7600 {"mfmmcr1", XSPR(31,339,782), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7601 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7602 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7603 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7604 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7605 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7606 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7607 {"mfm_casid", XSPR(31,339,793), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7608 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7609 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7610 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7611 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7612 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7613 {"mfm_tw", XSPR(31,339,799), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7614 {"mfbescrs", XSPR(31,339,800), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7615 {"mfbescrsu", XSPR(31,339,801), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7616 {"mfbescrr", XSPR(31,339,802), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7617 {"mfbescrru", XSPR(31,339,803), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7618 {"mfebbhr", XSPR(31,339,804), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7619 {"mfebbrr", XSPR(31,339,805), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7620 {"mfbescr", XSPR(31,339,806), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7621 {"mftar", XSPR(31,339,815), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7622 {"mfasdr", XSPR(31,339,816), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7623 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7624 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7625 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7626 {"mfpsscr", XSPR(31,339,823), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7627 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7628 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7629 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK
, PPC860
, EXT
, {RT
}},
7630 {"mfic", XSPR(31,339,848), XSPR_MASK
, POWER8
, EXT
, {RS
}},
7631 {"mfvtb", XSPR(31,339,849), XSPR_MASK
, POWER8
, EXT
, {RS
}},
7632 {"mfhpsscr", XSPR(31,339,855), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7633 {"mfivndx", XSPR(31,339,880), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7634 {"mfdvndx", XSPR(31,339,881), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7635 {"mfivlim", XSPR(31,339,882), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7636 {"mfdvlim", XSPR(31,339,883), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7637 {"mfclcsr", XSPR(31,339,884), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7638 {"mfccr1", XSPR(31,339,888), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7639 {"mfppr", XSPR(31,339,896), XSPR_MASK
, POWER5
, EXT
, {RT
}},
7640 {"mfppr32", XSPR(31,339,898), XSPR_MASK
, POWER5
, EXT
, {RT
}},
7641 {"mfgqr", XSPR(31,339,912), XSPRGQR_MASK
, PPCPS
, EXT
, {RT
, SPRGQR
}},
7642 {"mfhid2", XSPR(31,339,920), XSPR_MASK
, GEKKO
, EXT
, {RT
}},
7643 {"mfwpar", XSPR(31,339,921), XSPR_MASK
, GEKKO
, EXT
, {RT
}},
7644 {"mfdmau", XSPR(31,339,922), XSPR_MASK
, GEKKO
, EXT
, {RT
}},
7645 {"mfdmal", XSPR(31,339,923), XSPR_MASK
, GEKKO
, EXT
, {RT
}},
7646 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7647 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7648 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7649 {"mficdbtr", XSPR(31,339,927), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7650 {"mfummcr0", XSPR(31,339,936), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7651 {"mfupmc1", XSPR(31,339,937), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7652 {"mfupmc2", XSPR(31,339,938), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7653 {"mfusia", XSPR(31,339,939), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7654 {"mfummcr1", XSPR(31,339,940), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7655 {"mfupmc3", XSPR(31,339,941), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7656 {"mfupmc4", XSPR(31,339,942), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7657 {"mfzpr", XSPR(31,339,944), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7658 {"mfpid", XSPR(31,339,945), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7659 {"mfmmucr", XSPR(31,339,946), XSPR_MASK
, TITAN
, EXT
, {RT
}},
7660 {"mfccr0", XSPR(31,339,947), XSPR_MASK
, PPC405
|TITAN
, EXT
, {RT
}},
7661 {"mfiac3", XSPR(31,339,948), XSPR_MASK
, PPC405
, EXT
, {RT
}},
7662 {"mfiac4", XSPR(31,339,949), XSPR_MASK
, PPC405
, EXT
, {RT
}},
7663 {"mfdvc1", XSPR(31,339,950), XSPR_MASK
, PPC405
, EXT
, {RT
}},
7664 {"mfdvc2", XSPR(31,339,951), XSPR_MASK
, PPC405
, EXT
, {RT
}},
7665 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7666 {"mfpmc1", XSPR(31,339,953), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7667 {"mfsgr", XSPR(31,339,953), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7668 {"mfdcwr", XSPR(31,339,954), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7669 {"mfpmc2", XSPR(31,339,954), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7670 {"mfsia", XSPR(31,339,955), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7671 {"mfsler", XSPR(31,339,955), XSPR_MASK
, PPC405
, EXT
, {RT
}},
7672 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7673 {"mfsu0r", XSPR(31,339,956), XSPR_MASK
, PPC405
, EXT
, {RT
}},
7674 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK
, PPC405
, EXT
, {RT
}},
7675 {"mfpmc3", XSPR(31,339,957), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7676 {"mfpmc4", XSPR(31,339,958), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7677 {"mficdbdr", XSPR(31,339,979), XSPR_MASK
, PPC403
|TITAN
, EXT
, {RT
}},
7678 {"mfesr", XSPR(31,339,980), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7679 {"mfdear", XSPR(31,339,981), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7680 {"mfevpr", XSPR(31,339,982), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7681 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7682 {"mftsr", XSPR(31,339,984), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7683 {"mftcr", XSPR(31,339,986), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7684 {"mfpit", XSPR(31,339,987), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7685 {"mftbhi", XSPR(31,339,988), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7686 {"mftblo", XSPR(31,339,989), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7687 {"mfsrr2", XSPR(31,339,990), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7688 {"mfsrr3", XSPR(31,339,991), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7689 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7690 {"mfhid0", XSPR(31,339,1008), XSPR_MASK
, GEKKO
, EXT
, {RT
}},
7691 {"mfhid1", XSPR(31,339,1009), XSPR_MASK
, GEKKO
, EXT
, {RT
}},
7692 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK
, PPC405
, EXT
, {RT
}},
7693 {"mfiabr", XSPR(31,339,1010), XSPR_MASK
, GEKKO
, EXT
, {RT
}},
7694 {"mfhid4", XSPR(31,339,1011), XSPR_MASK
, BROADWAY
, EXT
, {RT
}},
7695 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK
, TITAN
, EXT
, {RS
}},
7696 {"mfiac1", XSPR(31,339,1012), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7697 {"mfiac2", XSPR(31,339,1013), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7698 {"mfdabr", XSPR(31,339,1013), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7699 {"mfdac1", XSPR(31,339,1014), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7700 {"mfdac2", XSPR(31,339,1015), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7701 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7702 {"mfdccr", XSPR(31,339,1018), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7703 {"mficcr", XSPR(31,339,1019), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7704 {"mfictc", XSPR(31,339,1019), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7705 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7706 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7707 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7708 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7709 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7710 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK
, PPC750
, EXT
, {RT
}},
7711 {"mfpir", XSPR(31,339,1023), XSPR_MASK
, POWER10
, EXT
, {RT
}},
7712 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK
, PPC403
, EXT
, {RT
}},
7713 {"mfspr", X(31,339), X_MASK
, COM
, 0, {RT
, SPR
}},
7715 {"lwax", X(31,341), X_MASK
, PPC64
, 0, {RT
, RA0
, RB
}},
7717 {"dst", XDSS(31,342,0), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
7718 {"dstt", XDSS(31,342,1), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
7720 {"lhax", X(31,343), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
7722 {"lvxl", X(31,359), X_MASK
, PPCVEC
, 0, {VD
, RA0
, RB
}},
7724 {"abs", XO(31,360,0,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
7725 {"abs.", XO(31,360,0,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
7727 {"divs", XO(31,363,0,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7728 {"divs.", XO(31,363,0,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
7730 {"lxvwsx", X(31,364), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
7732 {"tlbia", X(31,370), 0xffffffff, PPC
, E500
|TITAN
, {0}},
7734 {"mftbu", XSPR(31,371,269), XSPR_MASK
, PPC
, NO371
|POWER4
|EXT
, {RT
}},
7735 {"mftb", X(31,371), X_MASK
, PPC
, NO371
|POWER4
, {RT
, TBR
}},
7736 {"mftbl", XSPR(31,371,268), XSPR_MASK
, PPC
, NO371
|POWER4
|EXT
, {RT
}},
7738 {"lwaux", X(31,373), X_MASK
, PPC64
, 0, {RT
, RAL
, RB
}},
7740 {"dstst", XDSS(31,374,0), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
7741 {"dststt", XDSS(31,374,1), XDSS_MASK
, PPCVEC
, 0, {RA
, RB
, STRM
}},
7743 {"lhaux", X(31,375), X_MASK
, COM
, 0, {RT
, RAL
, RB
}},
7745 {"popcntw", X(31,378), XRB_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
}},
7747 {"setbc", X(31,384), XRB_MASK
, POWER10
, 0, {RT
, BI
}},
7749 {"mtdcrx", X(31,387), X_MASK
, BOOKE
|PPCA2
|PPC476
, TITAN
, {RA
, RS
}},
7750 {"mtdcrx.", XRC(31,387,1), X_MASK
, PPCA2
, 0, {RA
, RS
}},
7752 {"stvexbx", X(31,389), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7754 {"dcblc", X(31,390), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
7755 {"stdfcmx", APU(31,391,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
7757 {"divdeu", XO(31,393,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7758 {"divdeu.", XO(31,393,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7759 {"divweu", XO(31,395,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7760 {"divweu.", XO(31,395,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7762 {"stxvx", X(31,396), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
7763 {"stxvl", X(31,397), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
7765 {"dcblce", X(31,398), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
7767 {"slbmte", X(31,402), XRA_MASK
, PPC64
, 0, {RS
, RB
}},
7769 {"mtvsrws", X(31,403), XX1RB_MASK
, PPCVSX3
, 0, {XT6
, RA
}},
7771 {"pbt.", XRC(31,404,1), X_MASK
, POWER8
, 0, {RS
, RA0
, RB
}},
7773 {"icswx", XRC(31,406,0), X_MASK
, POWER7
|PPCA2
, 0, {RS
, RA
, RB
}},
7774 {"icswx.", XRC(31,406,1), X_MASK
, POWER7
|PPCA2
, 0, {RS
, RA
, RB
}},
7776 {"sthx", X(31,407), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
7778 {"orc", XRC(31,412,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7779 {"orc.", XRC(31,412,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7781 {"sthepx", X(31,415), X_MASK
, E500MC
|PPCA2
, 0, {RS
, RA0
, RB
}},
7783 {"setbcr", X(31,416), XRB_MASK
, POWER10
, 0, {RT
, BI
}},
7785 {"mtdcrux", X(31,419), X_MASK
, PPC464
|PPC476
, 0, {RA
, RS
}},
7787 {"stvexhx", X(31,421), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7789 {"dcblq.", XRC(31,422,1), X_MASK
, E6500
, 0, {CT
, RA0
, RB
}},
7791 {"divde", XO(31,425,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7792 {"divde.", XO(31,425,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7793 {"divwe", XO(31,427,0,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7794 {"divwe.", XO(31,427,0,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
7796 {"stxvll", X(31,429), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
7798 {"clrbhrb", X(31,430), 0xffffffff, POWER8
, 0, {0}},
7800 {"slbie", X(31,434), XRTRA_MASK
, PPC64
, 0, {RB
}},
7802 {"mtvsrdd", X(31,435), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
7804 {"ecowx", X(31,438), X_MASK
, PPC
, E500
|TITAN
, {RT
, RA0
, RB
}},
7806 {"sthux", X(31,439), X_MASK
, COM
, 0, {RS
, RAS
, RB
}},
7809 {"cctpl", 0x7c210b78, 0xffffffff, CELL
, EXT
, {0}},
7811 {"cctpm", 0x7c421378, 0xffffffff, CELL
, EXT
, {0}},
7813 {"cctph", 0x7c631b78, 0xffffffff, CELL
, EXT
, {0}},
7815 {"miso", 0x7f5ad378, 0xffffffff, POWER8
|E6500
, EXT
, {0}},
7817 {"yield", 0x7f7bdb78, 0xffffffff, POWER7
, EXT
, {0}},
7819 {"mdors", 0x7f9ce378, 0xffffffff, E500MC
, EXT
, {0}},
7820 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL
, EXT
, {0}},
7822 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7
, EXT
, {0}},
7823 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL
, EXT
, {0}},
7825 {"mdoom", 0x7fdef378, 0xffffffff, POWER7
, EXT
, {0}},
7826 {"db12cyc", 0x7fdef378, 0xffffffff, CELL
, EXT
, {0}},
7828 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL
, EXT
, {0}},
7830 {"mr", XRC(31,444,0), X_MASK
, COM
, EXT
, {RA
, RSB
}},
7831 {"or", XRC(31,444,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7832 {"mr.", XRC(31,444,1), X_MASK
, COM
, EXT
, {RA
, RSB
}},
7833 {"or.", XRC(31,444,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
7835 {"setnbc", X(31,448), XRB_MASK
, POWER10
, 0, {RT
, BI
}},
7837 {"mtexisr", XSPR(31,451, 64), XSPR_MASK
, PPC403
, 0, {RS
}},
7838 {"mtexier", XSPR(31,451, 66), XSPR_MASK
, PPC403
, 0, {RS
}},
7839 {"mtbr0", XSPR(31,451,128), XSPR_MASK
, PPC403
, 0, {RS
}},
7840 {"mtbr1", XSPR(31,451,129), XSPR_MASK
, PPC403
, 0, {RS
}},
7841 {"mtbr2", XSPR(31,451,130), XSPR_MASK
, PPC403
, 0, {RS
}},
7842 {"mtbr3", XSPR(31,451,131), XSPR_MASK
, PPC403
, 0, {RS
}},
7843 {"mtbr4", XSPR(31,451,132), XSPR_MASK
, PPC403
, 0, {RS
}},
7844 {"mtbr5", XSPR(31,451,133), XSPR_MASK
, PPC403
, 0, {RS
}},
7845 {"mtbr6", XSPR(31,451,134), XSPR_MASK
, PPC403
, 0, {RS
}},
7846 {"mtbr7", XSPR(31,451,135), XSPR_MASK
, PPC403
, 0, {RS
}},
7847 {"mtbear", XSPR(31,451,144), XSPR_MASK
, PPC403
, 0, {RS
}},
7848 {"mtbesr", XSPR(31,451,145), XSPR_MASK
, PPC403
, 0, {RS
}},
7849 {"mtiocr", XSPR(31,451,160), XSPR_MASK
, PPC403
, 0, {RS
}},
7850 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK
, PPC403
, 0, {RS
}},
7851 {"mtdmact0", XSPR(31,451,193), XSPR_MASK
, PPC403
, 0, {RS
}},
7852 {"mtdmada0", XSPR(31,451,194), XSPR_MASK
, PPC403
, 0, {RS
}},
7853 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK
, PPC403
, 0, {RS
}},
7854 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK
, PPC403
, 0, {RS
}},
7855 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK
, PPC403
, 0, {RS
}},
7856 {"mtdmact1", XSPR(31,451,201), XSPR_MASK
, PPC403
, 0, {RS
}},
7857 {"mtdmada1", XSPR(31,451,202), XSPR_MASK
, PPC403
, 0, {RS
}},
7858 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK
, PPC403
, 0, {RS
}},
7859 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK
, PPC403
, 0, {RS
}},
7860 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK
, PPC403
, 0, {RS
}},
7861 {"mtdmact2", XSPR(31,451,209), XSPR_MASK
, PPC403
, 0, {RS
}},
7862 {"mtdmada2", XSPR(31,451,210), XSPR_MASK
, PPC403
, 0, {RS
}},
7863 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK
, PPC403
, 0, {RS
}},
7864 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK
, PPC403
, 0, {RS
}},
7865 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK
, PPC403
, 0, {RS
}},
7866 {"mtdmact3", XSPR(31,451,217), XSPR_MASK
, PPC403
, 0, {RS
}},
7867 {"mtdmada3", XSPR(31,451,218), XSPR_MASK
, PPC403
, 0, {RS
}},
7868 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK
, PPC403
, 0, {RS
}},
7869 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK
, PPC403
, 0, {RS
}},
7870 {"mtdmasr", XSPR(31,451,224), XSPR_MASK
, PPC403
, 0, {RS
}},
7871 {"mtdcr", X(31,451), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, E500
|TITAN
, {SPR
, RS
}},
7872 {"mtdcr.", XRC(31,451,1), X_MASK
, PPCA2
, 0, {SPR
, RS
}},
7874 {"stvexwx", X(31,453), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
7876 {"dccci", X(31,454), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCA2
, 0, {RAOPT
, RBOPT
}},
7877 {"dci", X(31,454), XRARB_MASK
, PPCA2
|PPC476
, 0, {CT
}},
7879 {"divdu", XO(31,457,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7880 {"divdu.", XO(31,457,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
7882 {"divwu", XO(31,459,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7883 {"divwu.", XO(31,459,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
7885 {"stxvpx", X(31,461), XX1_MASK
, POWER10
, 0, {XTP
, RA0
, RB
}},
7887 {"mtpmr", X(31,462), X_MASK
, PPCPMR
|PPCE300
, 0, {PMR
, RS
}},
7888 {"mttmr", X(31,494), X_MASK
, PPCTMR
, 0, {TMR
, RS
}},
7890 {"slbieg", X(31,466), XRA_MASK
, POWER9
, 0, {RS
, RB
}},
7892 {"mtmq", XSPR(31,467, 0), XSPR_MASK
, M601
, EXT
, {RS
}},
7893 {"mtxer", XSPR(31,467, 1), XSPR_MASK
, COM
, EXT
, {RS
}},
7894 {"mtudscr", XSPR(31,467, 3), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7895 {"mtlr", XSPR(31,467, 8), XSPR_MASK
, COM
, EXT
, {RS
}},
7896 {"mtctr", XSPR(31,467, 9), XSPR_MASK
, COM
, EXT
, {RS
}},
7897 {"mtuamr", XSPR(31,467, 13), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7898 {"mtdscr", XSPR(31,467, 17), XSPR_MASK
, POWER6
, EXT
, {RS
}},
7899 {"mttid", XSPR(31,467, 17), XSPR_MASK
, POWER
, EXT
, {RS
}},
7900 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK
, COM
, TITAN
|EXT
, {RS
}},
7901 {"mtdar", XSPR(31,467, 19), XSPR_MASK
, COM
, TITAN
|EXT
, {RS
}},
7902 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK
, COM
, TITAN
|EXT
, {RS
}},
7903 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK
, COM
, TITAN
|EXT
, {RS
}},
7904 {"mtdec", XSPR(31,467, 22), XSPR_MASK
, COM
, EXT
, {RS
}},
7905 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK
, POWER
, EXT
, {RS
}},
7906 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK
, COM
, TITAN
|EXT
, {RS
}},
7907 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK
, COM
, EXT
, {RS
}},
7908 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK
, COM
, EXT
, {RS
}},
7909 {"mtcfar", XSPR(31,467, 28), XSPR_MASK
, POWER6
, EXT
, {RS
}},
7910 {"mtamr", XSPR(31,467, 29), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7911 {"mtpidr", XSPR(31,467, 48), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7912 {"mtpid", XSPR(31,467, 48), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7913 {"mtdecar", XSPR(31,467, 54), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7914 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7915 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7916 {"mtiamr", XSPR(31,467, 61), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7917 {"mtdear", XSPR(31,467, 61), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7918 {"mtesr", XSPR(31,467, 62), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7919 {"mtivpr", XSPR(31,467, 63), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7920 {"mttfhar", XSPR(31,467,128), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7921 {"mttfiar", XSPR(31,467,129), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7922 {"mttexasr", XSPR(31,467,130), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7923 {"mttexasru", XSPR(31,467,131), XSPR_MASK
, POWER9
, EXT
, {RS
}},
7924 {"mtcmpa", XSPR(31,467,144), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7925 {"mtcmpb", XSPR(31,467,145), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7926 {"mtcmpc", XSPR(31,467,146), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7927 {"mtcmpd", XSPR(31,467,147), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7928 {"mticr", XSPR(31,467,148), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7929 {"mtder", XSPR(31,467,149), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7930 {"mtcounta", XSPR(31,467,150), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7931 {"mtcountb", XSPR(31,467,151), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7932 {"mtctrl", XSPR(31,467,152), XSPR_MASK
, POWER4
, EXT
, {RS
}},
7933 {"mtcmpe", XSPR(31,467,152), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7934 {"mtfscr", XSPR(31,467,153), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7935 {"mtcmpf", XSPR(31,467,153), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7936 {"mtcmpg", XSPR(31,467,154), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7937 {"mtcmph", XSPR(31,467,155), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7938 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7939 {"mtuamor", XSPR(31,467,157), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7940 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7941 {"mtictrl", XSPR(31,467,158), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7942 {"mtpspb", XSPR(31,467,159), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7943 {"mtbar", XSPR(31,467,159), XSPR_MASK
, PPC860
, EXT
, {RS
}},
7944 {"mtdpdes", XSPR(31,467,176), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7945 {"mtdawr0", XSPR(31,467,180), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7946 {"mtdawr1", XSPR(31,467,181), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7947 {"mtrpr", XSPR(31,467,186), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7948 {"mtciabr", XSPR(31,467,187), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7949 {"mtdawrx0", XSPR(31,467,188), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7950 {"mtdawrx1", XSPR(31,467,189), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7951 {"mthfscr", XSPR(31,467,190), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7952 {"mtvrsave", XSPR(31,467,256), XSPR_MASK
, PPCVEC
, EXT
, {RS
}},
7953 {"mtusprg0", XSPR(31,467,256), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7954 {"mtsprg", XSPR(31,467,256), XSPRG_MASK
, PPC
, EXT
, {SPRG
, RS
}},
7955 {"mtsprg0", XSPR(31,467,272), XSPR_MASK
, PPC
, EXT
, {RS
}},
7956 {"mtsprg1", XSPR(31,467,273), XSPR_MASK
, PPC
, EXT
, {RS
}},
7957 {"mtsprg2", XSPR(31,467,274), XSPR_MASK
, PPC
, EXT
, {RS
}},
7958 {"mtsprg3", XSPR(31,467,275), XSPR_MASK
, PPC
, EXT
, {RS
}},
7959 {"mtsprg4", XSPR(31,467,276), XSPR_MASK
, PPC405
|BOOKE
, EXT
, {RS
}},
7960 {"mtsprg5", XSPR(31,467,277), XSPR_MASK
, PPC405
|BOOKE
, EXT
, {RS
}},
7961 {"mtsprg6", XSPR(31,467,278), XSPR_MASK
, PPC405
|BOOKE
, EXT
, {RS
}},
7962 {"mtsprg7", XSPR(31,467,279), XSPR_MASK
, PPC405
|BOOKE
, EXT
, {RS
}},
7963 {"mtasr", XSPR(31,467,280), XSPR_MASK
, PPC64
, EXT
, {RS
}},
7964 {"mtear", XSPR(31,467,282), XSPR_MASK
, PPC
, TITAN
|EXT
, {RS
}},
7965 {"mttbl", XSPR(31,467,284), XSPR_MASK
, PPC
, EXT
, {RS
}},
7966 {"mttbu", XSPR(31,467,285), XSPR_MASK
, PPC
, EXT
, {RS
}},
7967 {"mttbu40", XSPR(31,467,286), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7968 {"mthsprg0", XSPR(31,467,304), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7969 {"mtdbsr", XSPR(31,467,304), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7970 {"mthsprg1", XSPR(31,467,305), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7971 {"mthdisr", XSPR(31,467,306), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7972 {"mthdar", XSPR(31,467,307), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7973 {"mtspurr", XSPR(31,467,308), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7974 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7975 {"mtpurr", XSPR(31,467,309), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7976 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7977 {"mthdec", XSPR(31,467,310), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7978 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7979 {"mtiac1", XSPR(31,467,312), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7980 {"mthrmor", XSPR(31,467,313), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7981 {"mtiac2", XSPR(31,467,313), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7982 {"mthsrr0", XSPR(31,467,314), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7983 {"mtiac3", XSPR(31,467,314), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7984 {"mthsrr1", XSPR(31,467,315), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7985 {"mtiac4", XSPR(31,467,315), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7986 {"mtdac1", XSPR(31,467,316), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7987 {"mtdac2", XSPR(31,467,317), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7988 {"mtlpcr", XSPR(31,467,318), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7989 {"mtdvc1", XSPR(31,467,318), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7990 {"mtlpidr", XSPR(31,467,319), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7991 {"mtdvc2", XSPR(31,467,319), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7992 {"mthmer", XSPR(31,467,336), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7993 {"mttsr", XSPR(31,467,336), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7994 {"mthmeer", XSPR(31,467,337), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7995 {"mtpcr", XSPR(31,467,338), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7996 {"mtheir", XSPR(31,467,339), XSPR_MASK
, POWER10
, EXT
, {RS
}},
7997 {"mttcr", XSPR(31,467,340), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
7998 {"mtamor", XSPR(31,467,349), XSPR_MASK
, POWER7
, EXT
, {RS
}},
7999 {"mtivor0", XSPR(31,467,400), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8000 {"mtivor1", XSPR(31,467,401), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8001 {"mtivor2", XSPR(31,467,402), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8002 {"mtivor3", XSPR(31,467,403), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8003 {"mtivor4", XSPR(31,467,404), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8004 {"mtivor5", XSPR(31,467,405), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8005 {"mtivor6", XSPR(31,467,406), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8006 {"mtivor7", XSPR(31,467,407), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8007 {"mtivor8", XSPR(31,467,408), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8008 {"mtivor9", XSPR(31,467,409), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8009 {"mtivor10", XSPR(31,467,410), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8010 {"mtivor11", XSPR(31,467,411), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8011 {"mtivor12", XSPR(31,467,412), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8012 {"mtivor13", XSPR(31,467,413), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8013 {"mtivor14", XSPR(31,467,414), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8014 {"mtivor15", XSPR(31,467,415), XSPR_MASK
, BOOKE
, EXT
, {RS
}},
8015 {"mtptcr", XSPR(31,467,464), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8016 {"mtusprg0", XSPR(31,467,496), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8017 {"mtusprg1", XSPR(31,467,497), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8018 {"mturmor", XSPR(31,467,505), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8019 {"mtusrr0", XSPR(31,467,506), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8020 {"mtusrr1", XSPR(31,467,507), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8021 {"mtsmfctrl", XSPR(31,467,511), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8022 {"mtspefscr", XSPR(31,467,512), XSPR_MASK
, PPCSPE
, EXT
, {RS
}},
8023 {"mtbbear", XSPR(31,467,513), XSPR_MASK
, PPCBRLK
, EXT
, {RS
}},
8024 {"mtbbtar", XSPR(31,467,514), XSPR_MASK
, PPCBRLK
, EXT
, {RS
}},
8025 {"mtivor32", XSPR(31,467,528), XSPR_MASK
, PPCSPE
|E6500
, EXT
, {RS
}},
8026 {"mtivor33", XSPR(31,467,529), XSPR_MASK
, PPCSPE
|E6500
, EXT
, {RS
}},
8027 {"mtivor34", XSPR(31,467,530), XSPR_MASK
, PPCSPE
, EXT
, {RS
}},
8028 {"mtivor35", XSPR(31,467,531), XSPR_MASK
, PPCPMR
, EXT
, {RS
}},
8029 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK
, PPC
, TITAN
|EXT
, {SPRBAT
, RS
}},
8030 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK
, PPC
, TITAN
|EXT
, {SPRBAT
, RS
}},
8031 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK
, PPC
, TITAN
|EXT
, {SPRBAT
, RS
}},
8032 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK
, PPC
, TITAN
|EXT
, {SPRBAT
, RS
}},
8033 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK
, PPCRFMCI
, EXT
, {RS
}},
8034 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK
, PPCRFMCI
, EXT
, {RS
}},
8035 {"mtmcsr", XSPR(31,467,572), XSPR_MASK
, PPCRFMCI
, EXT
, {RS
}},
8036 {"mtsier2", XSPR(31,467,752), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8037 {"mtsier3", XSPR(31,467,753), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8038 {"mtmmcr3", XSPR(31,467,754), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8039 {"mtummcr2", XSPR(31,467,769), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8040 {"mtmmcr2", XSPR(31,467,769), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8041 {"mtummcra", XSPR(31,467,770), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8042 {"mtupmc1", XSPR(31,467,771), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8043 {"mtupmc2", XSPR(31,467,772), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8044 {"mtupmc3", XSPR(31,467,773), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8045 {"mtupmc4", XSPR(31,467,774), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8046 {"mtupmc5", XSPR(31,467,775), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8047 {"mtupmc6", XSPR(31,467,776), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8048 {"mtummcr0", XSPR(31,467,779), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8049 {"mtsier", XSPR(31,467,784), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8050 {"mtmmcra", XSPR(31,467,786), XSPR_MASK
, POWER7
, EXT
, {RS
}},
8051 {"mtpmc1", XSPR(31,467,787), XSPR_MASK
, POWER7
, EXT
, {RS
}},
8052 {"mtpmc2", XSPR(31,467,788), XSPR_MASK
, POWER7
, EXT
, {RS
}},
8053 {"mtpmc3", XSPR(31,467,789), XSPR_MASK
, POWER7
, EXT
, {RS
}},
8054 {"mtpmc4", XSPR(31,467,790), XSPR_MASK
, POWER7
, EXT
, {RS
}},
8055 {"mtpmc5", XSPR(31,467,791), XSPR_MASK
, POWER7
, EXT
, {RS
}},
8056 {"mtpmc6", XSPR(31,467,792), XSPR_MASK
, POWER7
, EXT
, {RS
}},
8057 {"mtmmcr0", XSPR(31,467,795), XSPR_MASK
, POWER7
, EXT
, {RS
}},
8058 {"mtsiar", XSPR(31,467,796), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8059 {"mtsdar", XSPR(31,467,797), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8060 {"mtmmcr1", XSPR(31,467,798), XSPR_MASK
, POWER7
, EXT
, {RS
}},
8061 {"mtbescrs", XSPR(31,467,800), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8062 {"mtbescrsu", XSPR(31,467,801), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8063 {"mtbescrr", XSPR(31,467,802), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8064 {"mtbescrru", XSPR(31,467,803), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8065 {"mtebbhr", XSPR(31,467,804), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8066 {"mtebbrr", XSPR(31,467,805), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8067 {"mtbescr", XSPR(31,467,806), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8068 {"mttar", XSPR(31,467,815), XSPR_MASK
, POWER9
, EXT
, {RS
}},
8069 {"mtasdr", XSPR(31,467,816), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8070 {"mtpsscr", XSPR(31,467,823), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8071 {"mtic", XSPR(31,467,848), XSPR_MASK
, POWER8
, EXT
, {RS
}},
8072 {"mtvtb", XSPR(31,467,849), XSPR_MASK
, POWER8
, EXT
, {RS
}},
8073 {"mthpsscr", XSPR(31,467,855), XSPR_MASK
, POWER10
, EXT
, {RS
}},
8074 {"mtivndx", XSPR(31,467,880), XSPR_MASK
, TITAN
, EXT
, {RS
}},
8075 {"mtdvndx", XSPR(31,467,881), XSPR_MASK
, TITAN
, EXT
, {RS
}},
8076 {"mtivlim", XSPR(31,467,882), XSPR_MASK
, TITAN
, EXT
, {RS
}},
8077 {"mtdvlim", XSPR(31,467,883), XSPR_MASK
, TITAN
, EXT
, {RS
}},
8078 {"mtclcsr", XSPR(31,467,884), XSPR_MASK
, TITAN
, EXT
, {RS
}},
8079 {"mtccr1", XSPR(31,467,888), XSPR_MASK
, TITAN
, EXT
, {RS
}},
8080 {"mtppr", XSPR(31,467,896), XSPR_MASK
, POWER5
, EXT
, {RS
}},
8081 {"mtppr32", XSPR(31,467,898), XSPR_MASK
, POWER5
, EXT
, {RS
}},
8082 {"mtgqr", XSPR(31,467,912), XSPRGQR_MASK
, PPCPS
, EXT
, {SPRGQR
, RS
}},
8083 {"mthid2", XSPR(31,467,920), XSPR_MASK
, GEKKO
, EXT
, {RS
}},
8084 {"mtwpar", XSPR(31,467,921), XSPR_MASK
, GEKKO
, EXT
, {RS
}},
8085 {"mtdmau", XSPR(31,467,922), XSPR_MASK
, GEKKO
, EXT
, {RS
}},
8086 {"mtdmal", XSPR(31,467,923), XSPR_MASK
, GEKKO
, EXT
, {RS
}},
8087 {"mtummcr0", XSPR(31,467,936), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8088 {"mtupmc1", XSPR(31,467,937), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8089 {"mtupmc2", XSPR(31,467,938), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8090 {"mtusia", XSPR(31,467,939), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8091 {"mtummcr1", XSPR(31,467,940), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8092 {"mtupmc3", XSPR(31,467,941), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8093 {"mtupmc4", XSPR(31,467,942), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8094 {"mtzpr", XSPR(31,467,944), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8095 {"mtpid", XSPR(31,467,945), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8096 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK
, TITAN
, EXT
, {RS
}},
8097 {"mtccr0", XSPR(31,467,947), XSPR_MASK
, PPC405
|TITAN
, EXT
, {RS
}},
8098 {"mtiac3", XSPR(31,467,948), XSPR_MASK
, PPC405
, EXT
, {RS
}},
8099 {"mtiac4", XSPR(31,467,949), XSPR_MASK
, PPC405
, EXT
, {RS
}},
8100 {"mtdvc1", XSPR(31,467,950), XSPR_MASK
, PPC405
, EXT
, {RS
}},
8101 {"mtdvc2", XSPR(31,467,951), XSPR_MASK
, PPC405
, EXT
, {RS
}},
8102 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8103 {"mtpmc1", XSPR(31,467,953), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8104 {"mtsgr", XSPR(31,467,953), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8105 {"mtdcwr", XSPR(31,467,954), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8106 {"mtpmc2", XSPR(31,467,954), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8107 {"mtsia", XSPR(31,467,955), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8108 {"mtsler", XSPR(31,467,955), XSPR_MASK
, PPC405
, EXT
, {RS
}},
8109 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8110 {"mtsu0r", XSPR(31,467,956), XSPR_MASK
, PPC405
, EXT
, {RS
}},
8111 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK
, PPC405
, EXT
, {RS
}},
8112 {"mtpmc3", XSPR(31,467,957), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8113 {"mtpmc4", XSPR(31,467,958), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8114 {"mticdbdr", XSPR(31,467,979), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8115 {"mtesr", XSPR(31,467,980), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8116 {"mtdear", XSPR(31,467,981), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8117 {"mtevpr", XSPR(31,467,982), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8118 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8119 {"mttsr", XSPR(31,467,984), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8120 {"mttcr", XSPR(31,467,986), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8121 {"mtpit", XSPR(31,467,987), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8122 {"mttbhi", XSPR(31,467,988), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8123 {"mttblo", XSPR(31,467,989), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8124 {"mtsrr2", XSPR(31,467,990), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8125 {"mtsrr3", XSPR(31,467,991), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8126 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8127 {"mthid0", XSPR(31,467,1008), XSPR_MASK
, GEKKO
, EXT
, {RS
}},
8128 {"mthid1", XSPR(31,467,1009), XSPR_MASK
, GEKKO
, EXT
, {RS
}},
8129 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK
, PPC405
, EXT
, {RS
}},
8130 {"mtiabr", XSPR(31,467,1010), XSPR_MASK
, GEKKO
, EXT
, {RS
}},
8131 {"mthid4", XSPR(31,467,1011), XSPR_MASK
, BROADWAY
, EXT
, {RS
}},
8132 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK
, TITAN
, EXT
, {RS
}},
8133 {"mtiac1", XSPR(31,467,1012), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8134 {"mtiac2", XSPR(31,467,1013), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8135 {"mtdabr", XSPR(31,467,1013), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8136 {"mtdac1", XSPR(31,467,1014), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8137 {"mtdac2", XSPR(31,467,1015), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8138 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8139 {"mtdccr", XSPR(31,467,1018), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8140 {"mticcr", XSPR(31,467,1019), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8141 {"mtictc", XSPR(31,467,1019), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8142 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8143 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8144 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8145 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8146 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8147 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK
, PPC750
, EXT
, {RS
}},
8148 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK
, PPC403
, EXT
, {RS
}},
8149 {"mtspr", X(31,467), X_MASK
, COM
, 0, {SPR
, RS
}},
8151 {"dcbi", X(31,470), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
8153 {"nand", XRC(31,476,0), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
8154 {"nand.", XRC(31,476,1), X_MASK
, COM
, 0, {RA
, RS
, RB
}},
8156 {"setnbcr", X(31,480), XRB_MASK
, POWER10
, 0, {RT
, BI
}},
8158 {"dsn", X(31,483), XRT_MASK
, E500MC
, 0, {RA
, RB
}},
8160 {"dcread", X(31,486), X_MASK
, PPC403
|PPC440
, PPCA2
, {RT
, RA0
, RB
}},
8162 {"icbtls", X(31,486), X_MASK
, PPCCHLK
|PPC476
|TITAN
, 0, {CT
, RA0
, RB
}},
8164 {"stvxl", X(31,487), X_MASK
, PPCVEC
, 0, {VS
, RA0
, RB
}},
8166 {"nabs", XO(31,488,0,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
8167 {"nabs.", XO(31,488,0,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
8169 {"divd", XO(31,489,0,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
8170 {"divd.", XO(31,489,0,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
8172 {"divw", XO(31,491,0,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
8173 {"divw.", XO(31,491,0,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
8175 {"icbtlse", X(31,494), X_MASK
, PPCCHLK
, E500MC
, {CT
, RA
, RB
}},
8177 {"slbia", X(31,498), 0xff1fffff, POWER6
, 0, {IH
}},
8178 {"slbia", X(31,498), 0xffffffff, PPC64
, POWER6
, {0}},
8180 {"cli", X(31,502), XRB_MASK
, POWER
, 0, {RT
, RA
}},
8182 {"popcntd", X(31,506), XRB_MASK
, POWER7
|PPCA2
, 0, {RA
, RS
}},
8184 {"cmpb", X(31,508), X_MASK
, POWER6
|PPCA2
|PPC476
, 0, {RA
, RS
, RB
}},
8186 {"mcrxr", X(31,512), XBFRARB_MASK
, COM
, POWER7
, {BF
}},
8188 {"lbdcbx", X(31,514), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
8189 {"lbdx", X(31,515), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
8191 {"bblels", X(31,518), X_MASK
, PPCBRLK
, 0, {0}},
8193 {"lvlx", X(31,519), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
8194 {"lbfcmux", APU(31,519,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
8196 {"subfco", XO(31,8,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8197 {"sfo", XO(31,8,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8198 {"subco", XO(31,8,1,0), XO_MASK
, PPCCOM
, EXT
, {RT
, RB
, RA
}},
8199 {"subfco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8200 {"sfo.", XO(31,8,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8201 {"subco.", XO(31,8,1,1), XO_MASK
, PPCCOM
, EXT
, {RT
, RB
, RA
}},
8203 {"addco", XO(31,10,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8204 {"ao", XO(31,10,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8205 {"addco.", XO(31,10,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8206 {"ao.", XO(31,10,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8208 {"lxsspx", X(31,524), XX1_MASK
, PPCVSX2
, 0, {XT6
, RA0
, RB
}},
8210 {"clcs", X(31,531), XRB_MASK
, M601
, 0, {RT
, RA
}},
8212 {"ldbrx", X(31,532), X_MASK
, CELL
|POWER7
|PPCA2
, 0, {RT
, RA0
, RB
}},
8214 {"lswx", X(31,533), X_MASK
, PPCCOM
, E500
|E500MC
, {RT
, RAX
, RBX
}},
8215 {"lsx", X(31,533), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8217 {"lwbrx", X(31,534), X_MASK
, PPCCOM
, 0, {RT
, RA0
, RB
}},
8218 {"lbrx", X(31,534), X_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8220 {"lfsx", X(31,535), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
8222 {"srw", XRC(31,536,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
8223 {"sr", XRC(31,536,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
8224 {"srw.", XRC(31,536,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
8225 {"sr.", XRC(31,536,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
8227 {"rrib", XRC(31,537,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8228 {"rrib.", XRC(31,537,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8230 {"cnttzw", XRC(31,538,0), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
8231 {"cnttzw.", XRC(31,538,1), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
8233 {"srd", XRC(31,539,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
8234 {"srd.", XRC(31,539,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
8236 {"maskir", XRC(31,541,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8237 {"maskir.", XRC(31,541,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8239 {"lhdcbx", X(31,546), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
8240 {"lhdx", X(31,547), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
8242 {"lvtrx", X(31,549), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
8244 {"bbelr", X(31,550), X_MASK
, PPCBRLK
, 0, {0}},
8246 {"lvrx", X(31,551), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
8247 {"lhfcmux", APU(31,551,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
8249 {"subfo", XO(31,40,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
8250 {"subo", XO(31,40,1,0), XO_MASK
, PPC
, EXT
, {RT
, RB
, RA
}},
8251 {"subfo.", XO(31,40,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
8252 {"subo.", XO(31,40,1,1), XO_MASK
, PPC
, EXT
, {RT
, RB
, RA
}},
8254 {"tlbsync", X(31,566), 0xffffffff, PPC
, 0, {0}},
8256 {"lfsux", X(31,567), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
8258 {"cnttzd", XRC(31,570,0), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
8259 {"cnttzd.", XRC(31,570,1), XRB_MASK
, POWER9
, 0, {RA
, RS
}},
8261 {"cnttzdm", X(31,571), X_MASK
, POWER10
, 0, {RA
, RS
, RB
}},
8263 {"mcrxrx", X(31,576), XBFRARB_MASK
, POWER9
, 0, {BF
}},
8265 {"lwdcbx", X(31,578), X_MASK
, E200Z4
, 0, {RT
, RA
, RB
}},
8266 {"lwdx", X(31,579), X_MASK
, E500MC
|E200Z4
, 0, {RT
, RA
, RB
}},
8268 {"lvtlx", X(31,581), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
8270 {"lwat", X(31,582), X_MASK
, POWER9
, 0, {RT
, RA0
, FC
}},
8272 {"lwfcmux", APU(31,583,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
8274 {"lxsdx", X(31,588), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
8276 {"mfsr", X(31,595), XRB_MASK
|(1<<20), COM
, NON32
, {RT
, SR
}},
8278 {"lswi", X(31,597), X_MASK
, PPCCOM
, E500
|E500MC
, {RT
, RAX
, NBI
}},
8279 {"lsi", X(31,597), X_MASK
, PWRCOM
, 0, {RT
, RA0
, NB
}},
8281 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4
, BOOKE
|PPC476
|EXT
, {0}},
8282 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC
, E500
|EXT
, {0}},
8283 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64
, EXT
, {0}},
8284 {"phwsync", XSYNCLS(31,598,4,0), 0xffffffff, POWER10
, EXT
, {0}},
8285 {"plwsync", XSYNCLS(31,598,5,0), 0xffffffff, POWER10
, EXT
, {0}},
8286 {"stncisync", XSYNCLS(31,598,1,1), 0xffffffff, POWER10
, EXT
, {0}},
8287 {"stcisync", XSYNCLS(31,598,0,2), 0xffffffff, POWER10
, EXT
, {0}},
8288 {"stsync", XSYNCLS(31,598,0,3), 0xffffffff, POWER10
, EXT
, {0}},
8289 {"sync", X(31,598), XSYNCLS_MASK
, POWER10
, BOOKE
|PPC476
, {LS3
, SC2
}},
8290 {"sync", X(31,598), XSYNCLE_MASK
, E6500
, 0, {LS
, ESYNC
}},
8291 {"sync", X(31,598), XSYNC_MASK
, PPCCOM
, POWER10
|BOOKE
|PPC476
, {LS
}},
8292 {"msync", X(31,598), 0xffffffff, BOOKE
|PPCA2
|PPC476
, 0, {0}},
8293 {"sync", X(31,598), 0xffffffff, BOOKE
|PPC476
, E6500
, {0}},
8294 {"lwsync", X(31,598), 0xffffffff, E500
, 0, {0}},
8295 {"dcs", X(31,598), 0xffffffff, PWRCOM
, 0, {0}},
8297 {"lfdx", X(31,599), X_MASK
, COM
, PPCEFS
, {FRT
, RA0
, RB
}},
8299 {"mffgpr", XRC(31,607,0), XRA_MASK
, POWER6
, POWER7
, {FRT
, RB
}},
8300 {"lfdepx", X(31,607), X_MASK
, E500MC
|PPCA2
, 0, {FRT
, RA0
, RB
}},
8302 {"lddx", X(31,611), X_MASK
, E500MC
, 0, {RT
, RA
, RB
}},
8304 {"lvswx", X(31,613), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
8306 {"ldat", X(31,614), X_MASK
, POWER9
, 0, {RT
, RA0
, FC
}},
8308 {"lqfcmux", APU(31,615,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
8310 {"nego", XO(31,104,1,0), XORB_MASK
, COM
, 0, {RT
, RA
}},
8311 {"nego.", XO(31,104,1,1), XORB_MASK
, COM
, 0, {RT
, RA
}},
8313 {"mulo", XO(31,107,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
8314 {"mulo.", XO(31,107,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
8316 {"mfsri", X(31,627), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
8318 {"dclst", X(31,630), XRB_MASK
, M601
, 0, {RS
, RA
}},
8320 {"lfdux", X(31,631), X_MASK
, COM
, PPCEFS
, {FRT
, RAS
, RB
}},
8322 {"stbdcbx", X(31,642), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
8323 {"stbdx", X(31,643), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
8325 {"stvlx", X(31,647), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
8326 {"stbfcmux", APU(31,647,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
8328 {"stxsspx", X(31,652), XX1_MASK
, PPCVSX2
, 0, {XS6
, RA0
, RB
}},
8330 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK
, PPCHTM
, 0, {HTM_R
}},
8332 {"subfeo", XO(31,136,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8333 {"sfeo", XO(31,136,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8334 {"subfeo.", XO(31,136,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8335 {"sfeo.", XO(31,136,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8337 {"addeo", XO(31,138,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8338 {"aeo", XO(31,138,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8339 {"addeo.", XO(31,138,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8340 {"aeo.", XO(31,138,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8342 {"hashstp", X(31,658), XRC_MASK
, POWER8
, 0, {RB
, DW
, RA0
}},
8344 {"mfsrin", X(31,659), XRA_MASK
, PPC
, NON32
, {RT
, RB
}},
8346 {"stdbrx", X(31,660), X_MASK
, CELL
|POWER7
|PPCA2
, 0, {RS
, RA0
, RB
}},
8348 {"stswx", X(31,661), X_MASK
, PPCCOM
, E500
|E500MC
, {RS
, RA0
, RB
}},
8349 {"stsx", X(31,661), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
8351 {"stwbrx", X(31,662), X_MASK
, PPCCOM
, 0, {RS
, RA0
, RB
}},
8352 {"stbrx", X(31,662), X_MASK
, PWRCOM
, 0, {RS
, RA0
, RB
}},
8354 {"stfsx", X(31,663), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
8356 {"srq", XRC(31,664,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8357 {"srq.", XRC(31,664,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8359 {"sre", XRC(31,665,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8360 {"sre.", XRC(31,665,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8362 {"sthdcbx", X(31,674), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
8363 {"sthdx", X(31,675), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
8365 {"stvfrx", X(31,677), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
8367 {"stvrx", X(31,679), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
8368 {"sthfcmux", APU(31,679,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
8370 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK
, PPCHTM
, 0, {0}},
8371 {"tend.", XRC(31,686,1), XRTARARB_MASK
, PPCHTM
, 0, {HTM_A
}},
8373 {"hashchkp", X(31,690), XRC_MASK
, POWER8
, 0, {RB
, DW
, RA0
}},
8375 {"stbcx.", XRC(31,694,1), X_MASK
, POWER8
|E6500
, 0, {RS
, RA0
, RB
}},
8377 {"stfsux", X(31,695), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
8379 {"sriq", XRC(31,696,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
8380 {"sriq.", XRC(31,696,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
8382 {"stwdcbx", X(31,706), X_MASK
, E200Z4
, 0, {RS
, RA
, RB
}},
8383 {"stwdx", X(31,707), X_MASK
, E500MC
|E200Z4
, 0, {RS
, RA
, RB
}},
8385 {"stvflx", X(31,709), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
8387 {"stwat", X(31,710), X_MASK
, POWER9
, 0, {RS
, RA0
, FC
}},
8389 {"stwfcmux", APU(31,711,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
8391 {"stxsdx", X(31,716), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
8393 {"tcheck", X(31,718), XRTBFRARB_MASK
, PPCHTM
, 0, {BF
}},
8395 {"subfzeo", XO(31,200,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
8396 {"sfzeo", XO(31,200,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
8397 {"subfzeo.", XO(31,200,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
8398 {"sfzeo.", XO(31,200,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
8400 {"addzeo", XO(31,202,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
8401 {"azeo", XO(31,202,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
8402 {"addzeo.", XO(31,202,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
8403 {"azeo.", XO(31,202,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
8405 {"hashst", X(31,722), XRC_MASK
, POWER8
, 0, {RB
, DW
, RA0
}},
8407 {"stswi", X(31,725), X_MASK
, PPCCOM
, E500
|E500MC
, {RS
, RA0
, NB
}},
8408 {"stsi", X(31,725), X_MASK
, PWRCOM
, 0, {RS
, RA0
, NB
}},
8410 {"sthcx.", XRC(31,726,1), X_MASK
, POWER8
|E6500
, 0, {RS
, RA0
, RB
}},
8412 {"stfdx", X(31,727), X_MASK
, COM
, PPCEFS
, {FRS
, RA0
, RB
}},
8414 {"srlq", XRC(31,728,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8415 {"srlq.", XRC(31,728,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8417 {"sreq", XRC(31,729,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8418 {"sreq.", XRC(31,729,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8420 {"mftgpr", XRC(31,735,0), XRA_MASK
, POWER6
, POWER7
, {RT
, FRB
}},
8421 {"stfdepx", X(31,735), X_MASK
, E500MC
|PPCA2
, 0, {FRS
, RA0
, RB
}},
8423 {"stddx", X(31,739), X_MASK
, E500MC
, 0, {RS
, RA
, RB
}},
8425 {"stvswx", X(31,741), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
8427 {"stdat", X(31,742), X_MASK
, POWER9
, 0, {RS
, RA0
, FC
}},
8429 {"stqfcmux", APU(31,743,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
8431 {"subfmeo", XO(31,232,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
8432 {"sfmeo", XO(31,232,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
8433 {"subfmeo.", XO(31,232,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
8434 {"sfmeo.", XO(31,232,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
8436 {"mulldo", XO(31,233,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
8437 {"mulldo.", XO(31,233,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
8439 {"addmeo", XO(31,234,1,0), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
8440 {"ameo", XO(31,234,1,0), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
8441 {"addmeo.", XO(31,234,1,1), XORB_MASK
, PPCCOM
, 0, {RT
, RA
}},
8442 {"ameo.", XO(31,234,1,1), XORB_MASK
, PWRCOM
, 0, {RT
, RA
}},
8444 {"mullwo", XO(31,235,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8445 {"mulso", XO(31,235,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8446 {"mullwo.", XO(31,235,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8447 {"mulso.", XO(31,235,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8449 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK
,PPCHTM
, EXT
, {0}},
8450 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK
,PPCHTM
, EXT
, {0}},
8451 {"tsr.", XRC(31,750,1), XRTLRARB_MASK
,PPCHTM
, 0, {L
}},
8453 {"hashchk", X(31,754), XRC_MASK
, POWER8
, 0, {RB
, DW
, RA0
}},
8455 {"darn", X(31,755), XLRAND_MASK
, POWER9
, 0, {RT
, LRAND
}},
8457 {"dcba", X(31,758), XRT_MASK
, PPC405
|PPC7450
|BOOKE
|PPCA2
|PPC476
, 0, {RA0
, RB
}},
8458 {"dcbal", XOPL(31,758,1), XRT_MASK
, E500MC
, 0, {RA0
, RB
}},
8460 {"stfdux", X(31,759), X_MASK
, COM
, PPCEFS
, {FRS
, RAS
, RB
}},
8462 {"srliq", XRC(31,760,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
8463 {"srliq.", XRC(31,760,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
8465 {"lvsm", X(31,773), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
8467 {"copy", XOPL(31,774,1), XRT_MASK
, POWER9
, 0, {RA0
, RB
}},
8469 {"stvepxl", X(31,775), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
8470 {"lvlxl", X(31,775), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
8471 {"ldfcmux", APU(31,775,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
8473 {"dozo", XO(31,264,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
8474 {"dozo.", XO(31,264,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
8476 {"addo", XO(31,266,1,0), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8477 {"caxo", XO(31,266,1,0), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8478 {"addo.", XO(31,266,1,1), XO_MASK
, PPCCOM
, 0, {RT
, RA
, RB
}},
8479 {"caxo.", XO(31,266,1,1), XO_MASK
, PWRCOM
, 0, {RT
, RA
, RB
}},
8481 {"modsd", X(31,777), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
8482 {"modsw", X(31,779), X_MASK
, POWER9
, 0, {RT
, RA
, RB
}},
8484 {"lxvw4x", X(31,780), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
8485 {"lxsibzx", X(31,781), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
8487 {"tabortwc.", XRC(31,782,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, RB
}},
8489 {"tlbivax", X(31,786), XRT_MASK
, BOOKE
|PPCA2
|PPC476
, 0, {RA0
, RB
}},
8491 {"lwzcix", X(31,789), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
8493 {"lhbrx", X(31,790), X_MASK
, COM
, 0, {RT
, RA0
, RB
}},
8495 {"lfdpx", X(31,791), X_MASK
|Q_MASK
, POWER6
, POWER7
, {FRTp
, RA0
, RB
}},
8496 {"lfqx", X(31,791), X_MASK
, POWER2
, 0, {FRT
, RA
, RB
}},
8498 {"sraw", XRC(31,792,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
8499 {"sra", XRC(31,792,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
8500 {"sraw.", XRC(31,792,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, RB
}},
8501 {"sra.", XRC(31,792,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, RB
}},
8503 {"srad", XRC(31,794,0), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
8504 {"srad.", XRC(31,794,1), X_MASK
, PPC64
, 0, {RA
, RS
, RB
}},
8506 {"evlddepx", VX (31, 1598), VX_MASK
, PPCSPE
, 0, {RT
, RA
, RB
}},
8507 {"lfddx", X(31,803), X_MASK
, E500MC
, 0, {FRT
, RA
, RB
}},
8509 {"lvtrxl", X(31,805), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
8510 {"stvepx", X(31,807), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
8511 {"lvrxl", X(31,807), X_MASK
, CELL
, 0, {VD
, RA0
, RB
}},
8513 {"lxvh8x", X(31,812), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
8514 {"lxsihzx", X(31,813), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
8516 {"tabortdc.", XRC(31,814,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, RB
}},
8518 {"rac", X(31,818), X_MASK
, M601
, 0, {RT
, RA
, RB
}},
8520 {"erativax", X(31,819), X_MASK
, PPCA2
, 0, {RS
, RA0
, RB
}},
8522 {"lhzcix", X(31,821), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
8524 {"dss", XDSS(31,822,0), XDSS_MASK
, PPCVEC
, 0, {STRM
}},
8525 {"dssall", XDSS(31,822,1), XDSS_MASK
, PPCVEC
, 0, {0}},
8527 {"lfqux", X(31,823), X_MASK
, POWER2
, 0, {FRT
, RA
, RB
}},
8529 {"srawi", XRC(31,824,0), X_MASK
, PPCCOM
, 0, {RA
, RS
, SH
}},
8530 {"srai", XRC(31,824,0), X_MASK
, PWRCOM
, 0, {RA
, RS
, SH
}},
8531 {"srawi.", XRC(31,824,1), X_MASK
, PPCCOM
, 0, {RA
, RS
, SH
}},
8532 {"srai.", XRC(31,824,1), X_MASK
, PWRCOM
, 0, {RA
, RS
, SH
}},
8534 {"sradi", XS(31,413,0), XS_MASK
, PPC64
, 0, {RA
, RS
, SH6
}},
8535 {"sradi.", XS(31,413,1), XS_MASK
, PPC64
, 0, {RA
, RS
, SH6
}},
8537 {"lvtlxl", X(31,837), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
8539 {"cpabort", X(31,838), XRTRARB_MASK
,POWER9
, 0, {0}},
8541 {"divo", XO(31,331,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
8542 {"divo.", XO(31,331,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
8544 {"lxvd2x", X(31,844), XX1_MASK
, PPCVSX
, 0, {XT6
, RA0
, RB
}},
8545 {"lxvx", X(31,844), XX1_MASK
, POWER8
, POWER9
|PPCVSX3
, {XT6
, RA0
, RB
}},
8547 {"tabortwci.", XRC(31,846,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, HTM_SI
}},
8549 {"tlbsrx.", XRC(31,850,1), XRT_MASK
, PPCA2
, 0, {RA0
, RB
}},
8551 {"slbiag", X(31,850), XRLARB_MASK
, POWER10
, 0, {RS
, A_L
}},
8552 {"slbiag", X(31,850), XRARB_MASK
, POWER9
, POWER10
, {RS
}},
8554 {"slbmfev", X(31,851), XRLA_MASK
, POWER9
, 0, {RT
, RB
, A_L
}},
8555 {"slbmfev", X(31,851), XRA_MASK
, PPC64
, POWER9
, {RT
, RB
}},
8557 {"lbzcix", X(31,853), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
8559 {"eieio", X(31,854), 0xffffffff, PPC
, BOOKE
|PPCA2
|PPC476
, {0}},
8560 {"mbar", X(31,854), X_MASK
, BOOKE
|PPCA2
|PPC476
, 0, {MO
}},
8561 {"eieio", XMBAR(31,854,1),0xffffffff, E500
, 0, {0}},
8562 {"eieio", X(31,854), 0xffffffff, PPCA2
|PPC476
, 0, {0}},
8564 {"lfiwax", X(31,855), X_MASK
, POWER6
|PPCA2
|PPC476
, 0, {FRT
, RA0
, RB
}},
8566 {"lvswxl", X(31,869), X_MASK
, E6500
, 0, {VD
, RA0
, RB
}},
8568 {"abso", XO(31,360,1,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
8569 {"abso.", XO(31,360,1,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
8571 {"divso", XO(31,363,1,0), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
8572 {"divso.", XO(31,363,1,1), XO_MASK
, M601
, 0, {RT
, RA
, RB
}},
8574 {"lxvb16x", X(31,876), XX1_MASK
, PPCVSX3
, 0, {XT6
, RA0
, RB
}},
8576 {"tabortdci.", XRC(31,878,1), X_MASK
, PPCHTM
, 0, {TO
, RA
, HTM_SI
}},
8578 {"rmieg", X(31,882), XRTRA_MASK
, POWER9
, 0, {RB
}},
8580 {"ldcix", X(31,885), X_MASK
, POWER6
, 0, {RT
, RA0
, RB
}},
8582 {"msgsync", X(31,886), 0xffffffff, POWER9
, 0, {0}},
8584 {"lfiwzx", X(31,887), X_MASK
, POWER7
|PPCA2
, 0, {FRT
, RA0
, RB
}},
8586 {"extswsli", XS(31,445,0), XS_MASK
, POWER9
, 0, {RA
, RS
, SH6
}},
8587 {"extswsli.", XS(31,445,1), XS_MASK
, POWER9
, 0, {RA
, RS
, SH6
}},
8589 {"paste.", XRC(31,902,1), XLRT_MASK
, POWER10
, 0, {RA0
, RB
, L1OPT
}},
8590 {"paste.", XRCL(31,902,1,1),XRT_MASK
, POWER9
, POWER10
, {RA0
, RB
}},
8592 {"stvlxl", X(31,903), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
8593 {"stdfcmux", APU(31,903,0), APU_MASK
, PPC405
, 0, {FCRT
, RA
, RB
}},
8595 {"divdeuo", XO(31,393,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
8596 {"divdeuo.", XO(31,393,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
8597 {"divweuo", XO(31,395,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
8598 {"divweuo.", XO(31,395,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
8600 {"stxvw4x", X(31,908), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
8601 {"stxsibx", X(31,909), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
8603 {"tabort.", XRC(31,910,1), XRTRB_MASK
, PPCHTM
, 0, {RA
}},
8605 {"tlbsx", XRC(31,914,0), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RTO
, RA0
, RB
}},
8606 {"tlbsx.", XRC(31,914,1), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RTO
, RA0
, RB
}},
8608 {"slbmfee", X(31,915), XRLA_MASK
, POWER9
, 0, {RT
, RB
, A_L
}},
8609 {"slbmfee", X(31,915), XRA_MASK
, PPC64
, POWER9
, {RT
, RB
}},
8611 {"stwcix", X(31,917), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
8613 {"sthbrx", X(31,918), X_MASK
, COM
, 0, {RS
, RA0
, RB
}},
8615 {"stfdpx", X(31,919), X_MASK
|Q_MASK
, POWER6
, POWER7
, {FRSp
, RA0
, RB
}},
8616 {"stfqx", X(31,919), X_MASK
, POWER2
, 0, {FRS
, RA0
, RB
}},
8618 {"sraq", XRC(31,920,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8619 {"sraq.", XRC(31,920,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8621 {"srea", XRC(31,921,0), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8622 {"srea.", XRC(31,921,1), X_MASK
, M601
, 0, {RA
, RS
, RB
}},
8624 {"extsh", XRC(31,922,0), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
8625 {"exts", XRC(31,922,0), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
8626 {"extsh.", XRC(31,922,1), XRB_MASK
, PPCCOM
, 0, {RA
, RS
}},
8627 {"exts.", XRC(31,922,1), XRB_MASK
, PWRCOM
, 0, {RA
, RS
}},
8629 {"evstddepx", VX (31, 1854), VX_MASK
, PPCSPE
, 0, {RT
, RA
, RB
}},
8630 {"stfddx", X(31,931), X_MASK
, E500MC
, 0, {FRS
, RA
, RB
}},
8632 {"stvfrxl", X(31,933), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
8634 {"wclrone", XOPL2(31,934,2),XRT_MASK
, PPCA2
, EXT
, {RA0
, RB
}},
8635 {"wclrall", X(31,934), XRARB_MASK
, PPCA2
, EXT
, {L2
}},
8636 {"wclr", X(31,934), X_MASK
, PPCA2
, 0, {L2
, RA0
, RB
}},
8638 {"stvrxl", X(31,935), X_MASK
, CELL
, 0, {VS
, RA0
, RB
}},
8640 {"divdeo", XO(31,425,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
8641 {"divdeo.", XO(31,425,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
8642 {"divweo", XO(31,427,1,0), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
8643 {"divweo.", XO(31,427,1,1), XO_MASK
, POWER7
|PPCA2
, 0, {RT
, RA
, RB
}},
8645 {"stxvh8x", X(31,940), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
8646 {"stxsihx", X(31,941), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
8648 {"treclaim.", XRC(31,942,1), XRTRB_MASK
, PPCHTM
, 0, {RA
}},
8650 {"tlbrehi", XTLB(31,946,0), XTLB_MASK
, PPC403
, PPCA2
|EXT
, {RT
, RA
}},
8651 {"tlbrelo", XTLB(31,946,1), XTLB_MASK
, PPC403
, PPCA2
|EXT
, {RT
, RA
}},
8652 {"tlbre", X(31,946), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RSO
, RAOPT
, SHO
}},
8654 {"sthcix", X(31,949), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
8656 {"icswepx", XRC(31,950,0), X_MASK
, PPCA2
, 0, {RS
, RA
, RB
}},
8657 {"icswepx.", XRC(31,950,1), X_MASK
, PPCA2
, 0, {RS
, RA
, RB
}},
8659 {"stfqux", X(31,951), X_MASK
, POWER2
, 0, {FRS
, RA
, RB
}},
8661 {"sraiq", XRC(31,952,0), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
8662 {"sraiq.", XRC(31,952,1), X_MASK
, M601
, 0, {RA
, RS
, SH
}},
8664 {"extsb", XRC(31,954,0), XRB_MASK
, PPC
, 0, {RA
, RS
}},
8665 {"extsb.", XRC(31,954,1), XRB_MASK
, PPC
, 0, {RA
, RS
}},
8667 {"stvflxl", X(31,965), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
8669 {"iccci", X(31,966), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
|PPCA2
, 0, {RAOPT
, RBOPT
}},
8670 {"ici", X(31,966), XRARB_MASK
, PPCA2
|PPC476
, 0, {CT
}},
8672 {"divduo", XO(31,457,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
8673 {"divduo.", XO(31,457,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
8675 {"divwuo", XO(31,459,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
8676 {"divwuo.", XO(31,459,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
8678 {"stxvd2x", X(31,972), XX1_MASK
, PPCVSX
, 0, {XS6
, RA0
, RB
}},
8679 {"stxvx", X(31,972), XX1_MASK
, POWER8
, POWER9
|PPCVSX3
, {XS6
, RA0
, RB
}},
8681 {"tlbld", X(31,978), XRTRA_MASK
, PPC
, PPC403
|BOOKE
|PPCA2
|PPC476
, {RB
}},
8682 {"tlbwehi", XTLB(31,978,0), XTLB_MASK
, PPC403
, EXT
, {RT
, RA
}},
8683 {"tlbwelo", XTLB(31,978,1), XTLB_MASK
, PPC403
, EXT
, {RT
, RA
}},
8684 {"tlbwe", X(31,978), X_MASK
, PPC403
|BOOKE
|PPCA2
|PPC476
, 0, {RSO
, RAOPT
, SHO
}},
8686 {"slbfee.", XRC(31,979,1), XRA_MASK
, POWER6
, 0, {RT
, RB
}},
8688 {"stbcix", X(31,981), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
8690 {"icbi", X(31,982), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
8692 {"stfiwx", X(31,983), X_MASK
, PPC
, PPCEFS
, {FRS
, RA0
, RB
}},
8694 {"extsw", XRC(31,986,0), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
8695 {"extsw.", XRC(31,986,1), XRB_MASK
, PPC64
, 0, {RA
, RS
}},
8697 {"icbiep", XRT(31,991,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
8699 {"stvswxl", X(31,997), X_MASK
, E6500
, 0, {VS
, RA0
, RB
}},
8701 {"icread", X(31,998), XRT_MASK
, PPC403
|PPC440
|PPC476
|TITAN
, 0, {RA0
, RB
}},
8703 {"nabso", XO(31,488,1,0), XORB_MASK
, M601
, 0, {RT
, RA
}},
8704 {"nabso.", XO(31,488,1,1), XORB_MASK
, M601
, 0, {RT
, RA
}},
8706 {"divdo", XO(31,489,1,0), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
8707 {"divdo.", XO(31,489,1,1), XO_MASK
, PPC64
, 0, {RT
, RA
, RB
}},
8709 {"divwo", XO(31,491,1,0), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
8710 {"divwo.", XO(31,491,1,1), XO_MASK
, PPC
, 0, {RT
, RA
, RB
}},
8712 {"stxvb16x", X(31,1004), XX1_MASK
, PPCVSX3
, 0, {XS6
, RA0
, RB
}},
8714 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK
,PPCHTM
, 0, {0}},
8716 {"tlbli", X(31,1010), XRTRA_MASK
, PPC
, TITAN
, {RB
}},
8718 {"stdcix", X(31,1013), X_MASK
, POWER6
, 0, {RS
, RA0
, RB
}},
8720 {"dcbz", X(31,1014), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
8721 {"dclz", X(31,1014), XRT_MASK
, PPC
, 0, {RA0
, RB
}},
8722 {"dcbzl", XOPL(31,1014,1), XRT_MASK
, POWER4
|E500MC
, PPC476
, {RA0
, RB
}},
8724 {"dcbzep", XRT(31,1023,0), XRT_MASK
, E500MC
|PPCA2
, 0, {RA0
, RB
}},
8726 {"lwz", OP(32), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RA0
}},
8727 {"l", OP(32), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
8729 {"lwzu", OP(33), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RAL
}},
8730 {"lu", OP(33), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
8732 {"lbz", OP(34), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
8734 {"lbzu", OP(35), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
8736 {"stw", OP(36), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RA0
}},
8737 {"st", OP(36), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
8739 {"stwu", OP(37), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RAS
}},
8740 {"stu", OP(37), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
8742 {"stb", OP(38), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RA0
}},
8744 {"stbu", OP(39), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RAS
}},
8746 {"lhz", OP(40), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
8748 {"lhzu", OP(41), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
8750 {"lha", OP(42), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RA0
}},
8752 {"lhau", OP(43), OP_MASK
, COM
, PPCVLE
, {RT
, D
, RAL
}},
8754 {"sth", OP(44), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RA0
}},
8756 {"sthu", OP(45), OP_MASK
, COM
, PPCVLE
, {RS
, D
, RAS
}},
8758 {"lmw", OP(46), OP_MASK
, PPCCOM
, PPCVLE
, {RT
, D
, RAM
}},
8759 {"lm", OP(46), OP_MASK
, PWRCOM
, PPCVLE
, {RT
, D
, RA0
}},
8761 {"stmw", OP(47), OP_MASK
, PPCCOM
, PPCVLE
, {RS
, D
, RA0
}},
8762 {"stm", OP(47), OP_MASK
, PWRCOM
, PPCVLE
, {RS
, D
, RA0
}},
8764 {"lfs", OP(48), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RA0
}},
8766 {"lfsu", OP(49), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RAS
}},
8768 {"lfd", OP(50), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RA0
}},
8770 {"lfdu", OP(51), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, D
, RAS
}},
8772 {"stfs", OP(52), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RA0
}},
8774 {"stfsu", OP(53), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RAS
}},
8776 {"stfd", OP(54), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RA0
}},
8778 {"stfdu", OP(55), OP_MASK
, COM
, PPCEFS
|PPCVLE
, {FRS
, D
, RAS
}},
8780 {"lq", OP(56), OP_MASK
|Q_MASK
, POWER4
, PPC476
|PPCVLE
, {RTQ
, DQ
, RAQ
}},
8781 {"psq_l", OP(56), OP_MASK
, PPCPS
, PPCVLE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
8782 {"lfq", OP(56), OP_MASK
, POWER2
, PPCVLE
, {FRT
, D
, RA0
}},
8784 {"lxsd", DSO(57,2), DS_MASK
, PPCVSX3
, PPCVLE
, {VD
, DS
, RA0
}},
8785 {"lxssp", DSO(57,3), DS_MASK
, PPCVSX3
, PPCVLE
, {VD
, DS
, RA0
}},
8786 {"lfdp", OP(57), OP_MASK
|Q_MASK
, POWER6
, POWER7
|PPCVLE
, {FRTp
, DS
, RA0
}},
8787 {"psq_lu", OP(57), OP_MASK
, PPCPS
, PPCVLE
, {FRT
,PSD
,RA
,PSW
,PSQ
}},
8788 {"lfqu", OP(57), OP_MASK
, POWER2
, PPCVLE
, {FRT
, D
, RA0
}},
8790 {"ld", DSO(58,0), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RA0
}},
8791 {"ldu", DSO(58,1), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RAL
}},
8792 {"lwa", DSO(58,2), DS_MASK
, PPC64
, PPCVLE
, {RT
, DS
, RA0
}},
8794 {"dadd", XRC(59,2,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
8795 {"dadd.", XRC(59,2,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
8797 {"dqua", ZRC(59,3,0), Z2_MASK
, POWER6
, PPCVLE
, {FRT
,FRA
,FRB
,RMC
}},
8798 {"dqua.", ZRC(59,3,1), Z2_MASK
, POWER6
, PPCVLE
, {FRT
,FRA
,FRB
,RMC
}},
8800 {"xvi8ger4pp", XX3(59,2), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8801 {"xvi8ger4", XX3(59,3), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8803 {"fdivs", A(59,18,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8804 {"fdivs.", A(59,18,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8806 {"fsubs", A(59,20,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8807 {"fsubs.", A(59,20,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8809 {"fadds", A(59,21,0), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8810 {"fadds.", A(59,21,1), AFRC_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
8812 {"fsqrts", A(59,22,0), AFRAFRC_MASK
, PPC
, TITAN
|PPCVLE
, {FRT
, FRB
}},
8813 {"fsqrts.", A(59,22,1), AFRAFRC_MASK
, PPC
, TITAN
|PPCVLE
, {FRT
, FRB
}},
8815 {"fres", A(59,24,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8816 {"fres", A(59,24,0), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
8817 {"fres.", A(59,24,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8818 {"fres.", A(59,24,1), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
8820 {"fmuls", A(59,25,0), AFRB_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
8821 {"fmuls.", A(59,25,1), AFRB_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
8823 {"frsqrtes", A(59,26,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8824 {"frsqrtes", A(59,26,0), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
8825 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8826 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
8828 {"fmsubs", A(59,28,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8829 {"fmsubs.", A(59,28,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8831 {"fmadds", A(59,29,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8832 {"fmadds.", A(59,29,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8834 {"fnmsubs", A(59,30,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8835 {"fnmsubs.", A(59,30,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8837 {"fnmadds", A(59,31,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8838 {"fnmadds.", A(59,31,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
8840 {"dmul", XRC(59,34,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
8841 {"dmul.", XRC(59,34,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
8843 {"drrnd", ZRC(59,35,0), Z2_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
, RMC
}},
8844 {"drrnd.", ZRC(59,35,1), Z2_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
, RMC
}},
8846 {"dscli", ZRC(59,66,0), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
8847 {"dscli.", ZRC(59,66,1), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
8849 {"dquai", ZRC(59,67,0), Z2_MASK
, POWER6
, PPCVLE
, {TE
, FRT
,FRB
,RMC
}},
8850 {"dquai.", ZRC(59,67,1), Z2_MASK
, POWER6
, PPCVLE
, {TE
, FRT
,FRB
,RMC
}},
8852 {"xvf16ger2pp", XX3(59,18), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8853 {"xvf16ger2", XX3(59,19), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8855 {"dscri", ZRC(59,98,0), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
8856 {"dscri.", ZRC(59,98,1), Z_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, SH16
}},
8858 {"drintx", ZRC(59,99,0), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
8859 {"drintx.", ZRC(59,99,1), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
8861 {"xvf32gerpp", XX3(59,26), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8862 {"xvf32ger", XX3(59,27), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8864 {"dcmpo", X(59,130), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
8866 {"xvi4ger8pp", XX3(59,34), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8867 {"xvi4ger8", XX3(59,35), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8869 {"dtstex", X(59,162), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
8871 {"xvi16ger2spp", XX3(59,42), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8872 {"xvi16ger2s", XX3(59,43), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8874 {"dtstdc", Z(59,194), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, DCM
}},
8876 {"xvbf16ger2pp",XX3(59,50), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8877 {"xvbf16ger2", XX3(59,51), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8879 {"dtstdg", Z(59,226), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, DGM
}},
8881 {"drintn", ZRC(59,227,0), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
8882 {"drintn.", ZRC(59,227,1), Z2_MASK
, POWER6
, PPCVLE
, {R
, FRT
, FRB
, RMC
}},
8884 {"xvf64gerpp", XX3(59,58), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6ap
, XB6a
}},
8885 {"xvf64ger", XX3(59,59), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6ap
, XB6a
}},
8887 {"dctdp", XRC(59,258,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
8888 {"dctdp.", XRC(59,258,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
8890 {"dctfix", XRC(59,290,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
8891 {"dctfix.", XRC(59,290,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
8893 {"ddedpd", XRC(59,322,0), X_MASK
, POWER6
, PPCVLE
, {SP
, FRT
, FRB
}},
8894 {"ddedpd.", XRC(59,322,1), X_MASK
, POWER6
, PPCVLE
, {SP
, FRT
, FRB
}},
8896 {"xvi16ger2", XX3(59,75), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8898 {"xvf16ger2np", XX3(59,82), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8900 {"dxex", XRC(59,354,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
8901 {"dxex.", XRC(59,354,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
8903 {"xvf32gernp", XX3(59,90), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8905 {"xvi8ger4spp", XX3(59,99), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8907 {"xvi16ger2pp", XX3(59,107), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8909 {"xvbf16ger2np",XX3(59,114), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8911 {"xvf64gernp", XX3(59,122), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6ap
, XB6a
}},
8913 {"dsub", XRC(59,514,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
8914 {"dsub.", XRC(59,514,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
8916 {"ddiv", XRC(59,546,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
8917 {"ddiv.", XRC(59,546,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
8919 {"xvf16ger2pn", XX3(59,146), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8921 {"xvf32gerpn", XX3(59,154), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8923 {"dcmpu", X(59,642), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
8925 {"dtstsf", X(59,674), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRB
}},
8926 {"dtstsfi", X(59,675), X_MASK
|1<<22,POWER9
, PPCVLE
, {BF
, UIM6
, FRB
}},
8928 {"xvbf16ger2pn",XX3(59,178), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8930 {"xvf64gerpn", XX3(59,186), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6ap
, XB6a
}},
8932 {"drsp", XRC(59,770,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
8933 {"drsp.", XRC(59,770,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRB
}},
8935 {"dcffix", XRC(59,802,0), X_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8936 {"dcffix.", XRC(59,802,1), X_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
8938 {"denbcd", XRC(59,834,0), X_MASK
, POWER6
, PPCVLE
, {S
, FRT
, FRB
}},
8939 {"denbcd.", XRC(59,834,1), X_MASK
, POWER6
, PPCVLE
, {S
, FRT
, FRB
}},
8941 {"xvf16ger2nn", XX3(59,210), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8943 {"fcfids", XRC(59,846,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
8944 {"fcfids.", XRC(59,846,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
8946 {"diex", XRC(59,866,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
8947 {"diex.", XRC(59,866,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRA
, FRB
}},
8949 {"xvf32gernn", XX3(59,218), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8951 {"xvbf16ger2nn",XX3(59,242), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6a
, XB6a
}},
8953 {"fcfidus", XRC(59,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
8954 {"fcfidus.", XRC(59,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
8956 {"xvf64gernn", XX3(59,250), XX3_MASK
|3<<21, POWER10
, PPCVLE
, {ACC
, XA6ap
, XB6a
}},
8958 {"xsaddsp", XX3(60,0), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8959 {"xsmaddasp", XX3(60,1), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8960 {"xxsldwi", XX3(60,2), XX3SHW_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, SHW
}},
8961 {"xscmpeqdp", XX3(60,3), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
8962 {"xsrsqrtesp", XX2(60,10), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
8963 {"xssqrtsp", XX2(60,11), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
8964 {"xxsel", XX4(60,3), XX4_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, XC6
}},
8965 {"xssubsp", XX3(60,8), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8966 {"xsmaddmsp", XX3(60,9), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8967 {"xxspltd", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCVLE
|EXT
, {XT6
, XAB6
, DMEX
}},
8968 {"xxmrghd", XX3(60,10), XX3_MASK
, PPCVSX
, PPCVLE
|EXT
, {XT6
, XA6
, XB6
}},
8969 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK
, PPCVSX
, PPCVLE
|EXT
, {XT6
, XAB6
}},
8970 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK
, PPCVSX
, PPCVLE
|EXT
, {XT6
, XA6
, XB6
}},
8971 {"xxpermdi", XX3(60,10), XX3DM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
, DM
}},
8972 {"xscmpgtdp", XX3(60,11), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
8973 {"xsresp", XX2(60,26), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
8974 {"xsmulsp", XX3(60,16), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8975 {"xsmsubasp", XX3(60,17), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8976 {"xxmrghw", XX3(60,18), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8977 {"xscmpgedp", XX3(60,19), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
8978 {"xsdivsp", XX3(60,24), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8979 {"xsmsubmsp", XX3(60,25), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
8980 {"xxperm", XX3(60,26), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
8981 {"xsadddp", XX3(60,32), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8982 {"xsmaddadp", XX3(60,33), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8983 {"xscmpudp", XX3(60,35), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
8984 {"xscvdpuxws", XX2(60,72), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8985 {"xsrdpi", XX2(60,73), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8986 {"xsrsqrtedp", XX2(60,74), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8987 {"xssqrtdp", XX2(60,75), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8988 {"xssubdp", XX3(60,40), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8989 {"xsmaddmdp", XX3(60,41), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8990 {"xscmpodp", XX3(60,43), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
8991 {"xscvdpsxws", XX2(60,88), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8992 {"xsrdpiz", XX2(60,89), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8993 {"xsredp", XX2(60,90), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8994 {"xsmuldp", XX3(60,48), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8995 {"xsmsubadp", XX3(60,49), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8996 {"xxmrglw", XX3(60,50), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
8997 {"xsrdpip", XX2(60,105), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
8998 {"xstsqrtdp", XX2(60,106), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
8999 {"xsrdpic", XX2(60,107), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9000 {"xsdivdp", XX3(60,56), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9001 {"xsmsubmdp", XX3(60,57), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9002 {"xxpermr", XX3(60,58), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
9003 {"xscmpexpdp", XX3(60,59), XX3BF_MASK
, PPCVSX3
, PPCVLE
, {BF
, XA6
, XB6
}},
9004 {"xsrdpim", XX2(60,121), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9005 {"xstdivdp", XX3(60,61), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
9006 {"xvaddsp", XX3(60,64), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9007 {"xvmaddasp", XX3(60,65), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9008 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9009 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9010 {"xvcvspuxws", XX2(60,136), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9011 {"xvrspi", XX2(60,137), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9012 {"xvrsqrtesp", XX2(60,138), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9013 {"xvsqrtsp", XX2(60,139), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9014 {"xvsubsp", XX3(60,72), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9015 {"xvmaddmsp", XX3(60,73), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9016 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9017 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9018 {"xvcvspsxws", XX2(60,152), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9019 {"xvrspiz", XX2(60,153), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9020 {"xvresp", XX2(60,154), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9021 {"xvmulsp", XX3(60,80), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9022 {"xvmsubasp", XX3(60,81), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9023 {"xxspltw", XX2(60,164), XX2UIM_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
, UIM
}},
9024 {"xxextractuw", XX2(60,165), XX2UIM4_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, UIMM4
}},
9025 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9026 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9027 {"xvcvuxwsp", XX2(60,168), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9028 {"xvrspip", XX2(60,169), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9029 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
9030 {"xvrspic", XX2(60,171), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9031 {"xvdivsp", XX3(60,88), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9032 {"xvmsubmsp", XX3(60,89), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9033 {"xxspltib", X(60,360), XX1_MASK
|3<<19, PPCVSX3
, PPCVLE
, {XT6
, IMM8
}},
9034 {"lxvkq", XVA(60,360,31), XVA_MASK
&~1, POWER10
, PPCVLE
, {XT6
, UIM5
}},
9035 {"xxinsertw", XX2(60,181), XX2UIM4_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, UIMM4
}},
9036 {"xvcvsxwsp", XX2(60,184), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9037 {"xvrspim", XX2(60,185), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9038 {"xvtdivsp", XX3(60,93), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
9039 {"xvadddp", XX3(60,96), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9040 {"xvmaddadp", XX3(60,97), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9041 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9042 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9043 {"xvcvdpuxws", XX2(60,200), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9044 {"xvrdpi", XX2(60,201), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9045 {"xvrsqrtedp", XX2(60,202), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9046 {"xvsqrtdp", XX2(60,203), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9047 {"xvsubdp", XX3(60,104), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9048 {"xvmaddmdp", XX3(60,105), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9049 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9050 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9051 {"xvcvdpsxws", XX2(60,216), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9052 {"xvrdpiz", XX2(60,217), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9053 {"xvredp", XX2(60,218), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9054 {"xvmuldp", XX3(60,112), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9055 {"xvmsubadp", XX3(60,113), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9056 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9057 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9058 {"xvcvuxwdp", XX2(60,232), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9059 {"xvrdpip", XX2(60,233), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9060 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XB6
}},
9061 {"xvrdpic", XX2(60,235), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9062 {"xvdivdp", XX3(60,120), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9063 {"xvmsubmdp", XX3(60,121), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9064 {"xvcvsxwdp", XX2(60,248), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9065 {"xvrdpim", XX2(60,249), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9066 {"xvtdivdp", XX3(60,125), XX3BF_MASK
, PPCVSX
, PPCVLE
, {BF
, XA6
, XB6
}},
9067 {"xsmaxcdp", XX3(60,128), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
9068 {"xsnmaddasp", XX3(60,129), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
9069 {"xxland", XX3(60,130), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9070 {"xscvdpsp", XX2(60,265), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9071 {"xscvdpspn", XX2(60,267), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
9072 {"xsmincdp", XX3(60,136), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
9073 {"xsnmaddmsp", XX3(60,137), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
9074 {"xxlandc", XX3(60,138), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9075 {"xsrsp", XX2(60,281), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
9076 {"xsmaxjdp", XX3(60,144), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
9077 {"xsnmsubasp", XX3(60,145), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
9078 {"xxmr", XX3(60,146), XX3_MASK
, PPCVSX
, PPCVLE
|EXT
, {XT6
, XAB6
}},
9079 {"xxlor", XX3(60,146), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9080 {"xscvuxdsp", XX2(60,296), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
9081 {"xststdcsp", XX2(60,298), XX2BFD_MASK
, PPCVSX3
, PPCVLE
, {BF
, XB6
, DCMX
}},
9082 {"xsminjdp", XX3(60,152), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
9083 {"xsnmsubmsp", XX3(60,153), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
9084 {"xxlxor", XX3(60,154), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9085 {"xscvsxdsp", XX2(60,312), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
9086 {"xsmaxdp", XX3(60,160), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9087 {"xsnmaddadp", XX3(60,161), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9088 {"xxlnot", XX3(60,162), XX3_MASK
, PPCVSX
, PPCVLE
|EXT
, {XT6
, XAB6
}},
9089 {"xxlnor", XX3(60,162), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9090 {"xscvdpuxds", XX2(60,328), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9091 {"xscvspdp", XX2(60,329), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9092 {"xscvspdpn", XX2(60,331), XX2_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XB6
}},
9093 {"xsmindp", XX3(60,168), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9094 {"xsnmaddmdp", XX3(60,169), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9095 {"xxlorc", XX3(60,170), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
9096 {"xscvdpsxds", XX2(60,344), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9097 {"xsabsdp", XX2(60,345), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9098 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK
|1, PPCVSX3
, PPCVLE
, {RT
, XB6
}},
9099 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK
|1, PPCVSX3
, PPCVLE
, {RT
, XB6
}},
9100 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9101 {"xscvdphp", XX2VA(60,347,17),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9102 {"xscpsgndp", XX3(60,176), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9103 {"xsnmsubadp", XX3(60,177), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9104 {"xxlnand", XX3(60,178), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
9105 {"xscvuxddp", XX2(60,360), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9106 {"xsnabsdp", XX2(60,361), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9107 {"xststdcdp", XX2(60,362), XX2BFD_MASK
, PPCVSX3
, PPCVLE
, {BF
, XB6
, DCMX
}},
9108 {"xsnmsubmdp", XX3(60,185), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9109 {"xxleqv", XX3(60,186), XX3_MASK
, PPCVSX2
, PPCVLE
, {XT6
, XA6
, XB6
}},
9110 {"xscvsxddp", XX2(60,376), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9111 {"xsnegdp", XX2(60,377), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9112 {"xvmaxsp", XX3(60,192), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9113 {"xvnmaddasp", XX3(60,193), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9114 {"xvcvspuxds", XX2(60,392), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9115 {"xvcvdpsp", XX2(60,393), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9116 {"xvminsp", XX3(60,200), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9117 {"xvnmaddmsp", XX3(60,201), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9118 {"xvcvspsxds", XX2(60,408), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9119 {"xvabssp", XX2(60,409), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9120 {"xvmovsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCVLE
|EXT
, {XT6
, XAB6
}},
9121 {"xvcpsgnsp", XX3(60,208), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9122 {"xvnmsubasp", XX3(60,209), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9123 {"xvcvuxdsp", XX2(60,424), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9124 {"xvnabssp", XX2(60,425), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9125 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, DCMXS
}},
9126 {"xviexpsp", XX3(60,216), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
9127 {"xvnmsubmsp", XX3(60,217), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9128 {"xvcvsxdsp", XX2(60,440), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9129 {"xvnegsp", XX2(60,441), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9130 {"xvmaxdp", XX3(60,224), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9131 {"xvnmaddadp", XX3(60,225), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9132 {"xvcvdpuxds", XX2(60,456), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9133 {"xvcvspdp", XX2(60,457), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9134 {"xxgenpcvbm", X(60,916), XX1_MASK
, POWER10
, PPCVLE
, {XT6
, VB
, UIMM
}},
9135 {"xxgenpcvhm", X(60,917), XX1_MASK
, POWER10
, PPCVLE
, {XT6
, VB
, UIMM
}},
9136 {"xsiexpdp", X(60,918), XX1_MASK
, PPCVSX3
, PPCVLE
, {XT6
, RA
, RB
}},
9137 {"xvmindp", XX3(60,232), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9138 {"xvnmaddmdp", XX3(60,233), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9139 {"xvcvdpsxds", XX2(60,472), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9140 {"xvabsdp", XX2(60,473), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9141 {"xxgenpcvwm", X(60,948), XX1_MASK
, POWER10
, PPCVLE
, {XT6
, VB
, UIMM
}},
9142 {"xxgenpcvdm", X(60,949), XX1_MASK
, POWER10
, PPCVLE
, {XT6
, VB
, UIMM
}},
9143 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9144 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9145 {"xvtlsbb", XX2VA(60,475,2),XX2BF_MASK
, POWER10
, PPCVLE
, {BF
, XB6
}},
9146 {"xxbrh", XX2VA(60,475,7),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9147 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9148 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9149 {"xxbrw", XX2VA(60,475,15),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9150 {"xvcvbf16spn", XX2VA(60,475,16),XX2_MASK
, PPCVSX4
, PPCVLE
, {XT6
, XB6
}},
9151 {"xvcvspbf16", XX2VA(60,475,17),XX2_MASK
, PPCVSX4
, PPCVLE
, {XT6
, XB6
}},
9152 {"xxbrd", XX2VA(60,475,23),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9153 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9154 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9155 {"xxbrq", XX2VA(60,475,31),XX2_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
}},
9156 {"xvmovdp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCVLE
|EXT
, {XT6
, XAB6
}},
9157 {"xvcpsgndp", XX3(60,240), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9158 {"xvnmsubadp", XX3(60,241), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9159 {"xvcvuxddp", XX2(60,488), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9160 {"xvnabsdp", XX2(60,489), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9161 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XB6
, DCMXS
}},
9162 {"xviexpdp", XX3(60,248), XX3_MASK
, PPCVSX3
, PPCVLE
, {XT6
, XA6
, XB6
}},
9163 {"xvnmsubmdp", XX3(60,249), XX3_MASK
, PPCVSX
, PPCVLE
, {XT6
, XA6
, XB6
}},
9164 {"xvcvsxddp", XX2(60,504), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9165 {"xvnegdp", XX2(60,505), XX2_MASK
, PPCVSX
, PPCVLE
, {XT6
, XB6
}},
9167 {"psq_st", OP(60), OP_MASK
, PPCPS
, PPCVLE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
9168 {"stfq", OP(60), OP_MASK
, POWER2
, PPCVLE
, {FRS
, D
, RA
}},
9170 {"lxv", DQX(61,1), DQX_MASK
, PPCVSX3
, PPCVLE
, {XTQ6
, DQ
, RA0
}},
9171 {"stxv", DQX(61,5), DQX_MASK
, PPCVSX3
, PPCVLE
, {XSQ6
, DQ
, RA0
}},
9172 {"stxsd", DSO(61,2), DS_MASK
, PPCVSX3
, PPCVLE
, {VS
, DS
, RA0
}},
9173 {"stxssp", DSO(61,3), DS_MASK
, PPCVSX3
, PPCVLE
, {VS
, DS
, RA0
}},
9174 {"stfdp", OP(61), OP_MASK
|Q_MASK
, POWER6
, POWER7
|PPCVLE
, {FRSp
, DS
, RA0
}},
9175 {"psq_stu", OP(61), OP_MASK
, PPCPS
, PPCVLE
, {FRS
,PSD
,RA
,PSW
,PSQ
}},
9176 {"stfqu", OP(61), OP_MASK
, POWER2
, PPCVLE
, {FRS
, D
, RA
}},
9178 {"std", DSO(62,0), DS_MASK
, PPC64
, PPCVLE
, {RS
, DS
, RA0
}},
9179 {"stdu", DSO(62,1), DS_MASK
, PPC64
, PPCVLE
, {RS
, DS
, RAS
}},
9180 {"stq", DSO(62,2), DS_MASK
|Q_MASK
, POWER4
, PPC476
|PPCVLE
, {RSQ
, DS
, RA0
}},
9182 {"fcmpu", X(63,0), XBF_MASK
, COM
, PPCEFS
|PPCVLE
, {BF
, FRA
, FRB
}},
9184 {"daddq", XRC(63,2,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
9185 {"daddq.", XRC(63,2,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
9187 {"dquaq", ZRC(63,3,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
, RMC
}},
9188 {"dquaq.", ZRC(63,3,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
, RMC
}},
9190 {"xsaddqp", XRC(63,4,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9191 {"xsaddqpo", XRC(63,4,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9193 {"xsrqpi", ZRC(63,5,0), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
9194 {"xsrqpix", ZRC(63,5,1), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
9196 {"fcpsgn", XRC(63,8,0), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FRT
, FRA
, FRB
}},
9197 {"fcpsgn.", XRC(63,8,1), X_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FRT
, FRA
, FRB
}},
9199 {"frsp", XRC(63,12,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9200 {"frsp.", XRC(63,12,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9202 {"fctiw", XRC(63,14,0), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9203 {"fcir", XRC(63,14,0), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
9204 {"fctiw.", XRC(63,14,1), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9205 {"fcir.", XRC(63,14,1), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
9207 {"fctiwz", XRC(63,15,0), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9208 {"fcirz", XRC(63,15,0), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
9209 {"fctiwz.", XRC(63,15,1), XRA_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9210 {"fcirz.", XRC(63,15,1), XRA_MASK
, PWR2COM
, PPCVLE
, {FRT
, FRB
}},
9212 {"fdiv", A(63,18,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
9213 {"fd", A(63,18,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
9214 {"fdiv.", A(63,18,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
9215 {"fd.", A(63,18,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
9217 {"fsub", A(63,20,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
9218 {"fs", A(63,20,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
9219 {"fsub.", A(63,20,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
9220 {"fs.", A(63,20,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
9222 {"fadd", A(63,21,0), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
9223 {"fa", A(63,21,0), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
9224 {"fadd.", A(63,21,1), AFRC_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRB
}},
9225 {"fa.", A(63,21,1), AFRC_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRB
}},
9227 {"fsqrt", A(63,22,0), AFRAFRC_MASK
, PPCPWR2
, TITAN
|PPCVLE
, {FRT
, FRB
}},
9228 {"fsqrt.", A(63,22,1), AFRAFRC_MASK
, PPCPWR2
, TITAN
|PPCVLE
, {FRT
, FRB
}},
9230 {"fsel", A(63,23,0), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9231 {"fsel.", A(63,23,1), A_MASK
, PPC
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9233 {"fre", A(63,24,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
9234 {"fre", A(63,24,0), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
9235 {"fre.", A(63,24,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
9236 {"fre.", A(63,24,1), AFRALFRC_MASK
, POWER5
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
9238 {"fmul", A(63,25,0), AFRB_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
9239 {"fm", A(63,25,0), AFRB_MASK
, PWRCOM
, PPCVLE
|PPCVLE
, {FRT
, FRA
, FRC
}},
9240 {"fmul.", A(63,25,1), AFRB_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
}},
9241 {"fm.", A(63,25,1), AFRB_MASK
, PWRCOM
, PPCVLE
|PPCVLE
, {FRT
, FRA
, FRC
}},
9243 {"frsqrte", A(63,26,0), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
9244 {"frsqrte", A(63,26,0), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
9245 {"frsqrte.", A(63,26,1), AFRAFRC_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
9246 {"frsqrte.", A(63,26,1), AFRALFRC_MASK
, PPC
, POWER7
|PPCVLE
, {FRT
, FRB
, A_L
}},
9248 {"fmsub", A(63,28,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9249 {"fms", A(63,28,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9250 {"fmsub.", A(63,28,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9251 {"fms.", A(63,28,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9253 {"fmadd", A(63,29,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9254 {"fma", A(63,29,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9255 {"fmadd.", A(63,29,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9256 {"fma.", A(63,29,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9258 {"fnmsub", A(63,30,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9259 {"fnms", A(63,30,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9260 {"fnmsub.", A(63,30,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9261 {"fnms.", A(63,30,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9263 {"fnmadd", A(63,31,0), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9264 {"fnma", A(63,31,0), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9265 {"fnmadd.", A(63,31,1), A_MASK
, PPCCOM
, PPCEFS
|PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9266 {"fnma.", A(63,31,1), A_MASK
, PWRCOM
, PPCVLE
, {FRT
, FRA
, FRC
, FRB
}},
9268 {"fcmpo", X(63,32), XBF_MASK
, COM
, PPCEFS
|PPCVLE
, {BF
, FRA
, FRB
}},
9270 {"dmulq", XRC(63,34,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
9271 {"dmulq.", XRC(63,34,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
9273 {"drrndq", ZRC(63,35,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
, RMC
}},
9274 {"drrndq.", ZRC(63,35,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
, RMC
}},
9276 {"xsmulqp", XRC(63,36,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9277 {"xsmulqpo", XRC(63,36,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9279 {"xsrqpxp", Z(63,37), Z2_MASK
, PPCVSX3
, PPCVLE
, {R
, VD
, VB
, RMC
}},
9281 {"mtfsb1", XRC(63,38,0), XRARB_MASK
, COM
, PPCVLE
, {BTF
}},
9282 {"mtfsb1.", XRC(63,38,1), XRARB_MASK
, COM
, PPCVLE
, {BTF
}},
9284 {"fneg", XRC(63,40,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9285 {"fneg.", XRC(63,40,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9287 {"mcrfs", X(63,64), XRB_MASK
|(3<<21)|(3<<16), COM
, PPCVLE
, {BF
, BFA
}},
9289 {"dscliq", ZRC(63,66,0), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
9290 {"dscliq.", ZRC(63,66,1), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
9292 {"dquaiq", ZRC(63,67,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {TE
, FRTp
, FRBp
, RMC
}},
9293 {"dquaiq.", ZRC(63,67,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {TE
, FRTp
, FRBp
, RMC
}},
9295 {"xscmpeqqp", X(63,68), X_MASK
, POWER10
, PPCVLE
, {VD
, VA
, VB
}},
9297 {"mtfsb0", XRC(63,70,0), XRARB_MASK
, COM
, PPCVLE
, {BTF
}},
9298 {"mtfsb0.", XRC(63,70,1), XRARB_MASK
, COM
, PPCVLE
, {BTF
}},
9300 {"fmr", XRC(63,72,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9301 {"fmr.", XRC(63,72,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9303 {"dscriq", ZRC(63,98,0), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
9304 {"dscriq.", ZRC(63,98,1), Z_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, SH16
}},
9306 {"drintxq", ZRC(63,99,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
9307 {"drintxq.", ZRC(63,99,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
9309 {"xscpsgnqp", X(63,100), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9311 {"ftdiv", X(63,128), XBF_MASK
, POWER7
, PPCVLE
, {BF
, FRA
, FRB
}},
9313 {"dcmpoq", X(63,130), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
9315 {"xscmpoqp", X(63,132), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
9317 {"mtfsfi", XRC(63,134,0), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCVLE
, {BFF
, U
, W
}},
9318 {"mtfsfi", XRC(63,134,0), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
|PPCVLE
, {BFF
, U
}},
9319 {"mtfsfi.", XRC(63,134,1), XWRA_MASK
|(3<<21)|(1<<11), POWER6
|PPCA2
|PPC476
, PPCVLE
, {BFF
, U
, W
}},
9320 {"mtfsfi.", XRC(63,134,1), XRA_MASK
|(3<<21)|(1<<11), COM
, POWER6
|PPCA2
|PPC476
|PPCVLE
, {BFF
, U
}},
9322 {"fnabs", XRC(63,136,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9323 {"fnabs.", XRC(63,136,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9325 {"fctiwu", XRC(63,142,0), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
9326 {"fctiwu.", XRC(63,142,1), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
9327 {"fctiwuz", XRC(63,143,0), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
9328 {"fctiwuz.", XRC(63,143,1), XRA_MASK
, POWER7
, PPCVLE
, {FRT
, FRB
}},
9330 {"ftsqrt", X(63,160), XBF_MASK
|FRA_MASK
, POWER7
, PPCVLE
, {BF
, FRB
}},
9332 {"dtstexq", X(63,162), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
9334 {"xscmpexpqp", X(63,164), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
9336 {"dtstdcq", Z(63,194), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, DCM
}},
9338 {"xscmpgeqp", X(63,196), X_MASK
, POWER10
, PPCVLE
, {VD
, VA
, VB
}},
9340 {"dtstdgq", Z(63,226), Z_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, DGM
}},
9342 {"drintnq", ZRC(63,227,0), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
9343 {"drintnq.", ZRC(63,227,1), Z2_MASK
|Q_MASK
, POWER6
, PPCVLE
, {R
, FRTp
, FRBp
, RMC
}},
9345 {"xscmpgtqp", X(63,228), X_MASK
, POWER10
, PPCVLE
, {VD
, VA
, VB
}},
9347 {"dctqpq", XRC(63,258,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
9348 {"dctqpq.", XRC(63,258,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
9350 {"fabs", XRC(63,264,0), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9351 {"fabs.", XRC(63,264,1), XRA_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
, FRB
}},
9353 {"dctfixq", XRC(63,290,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
9354 {"dctfixq.", XRC(63,290,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
9356 {"ddedpdq", XRC(63,322,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {SP
, FRTp
, FRBp
}},
9357 {"ddedpdq.", XRC(63,322,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {SP
, FRTp
, FRBp
}},
9359 {"dxexq", XRC(63,354,0), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
9360 {"dxexq.", XRC(63,354,1), X_MASK
, POWER6
, PPCVLE
, {FRT
, FRBp
}},
9362 {"xsmaddqp", XRC(63,388,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9363 {"xsmaddqpo", XRC(63,388,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9365 {"frin", XRC(63,392,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
9366 {"frin.", XRC(63,392,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
9368 {"xsmsubqp", XRC(63,420,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9369 {"xsmsubqpo", XRC(63,420,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9371 {"friz", XRC(63,424,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
9372 {"friz.", XRC(63,424,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
9374 {"xsnmaddqp", XRC(63,452,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9375 {"xsnmaddqpo", XRC(63,452,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9377 {"frip", XRC(63,456,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
9378 {"frip.", XRC(63,456,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
9380 {"xsnmsubqp", XRC(63,484,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9381 {"xsnmsubqpo", XRC(63,484,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9383 {"frim", XRC(63,488,0), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
9384 {"frim.", XRC(63,488,1), XRA_MASK
, POWER5
, PPCVLE
, {FRT
, FRB
}},
9386 {"dsubq", XRC(63,514,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
9387 {"dsubq.", XRC(63,514,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
9389 {"xssubqp", XRC(63,516,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9390 {"xssubqpo", XRC(63,516,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9392 {"ddivq", XRC(63,546,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
9393 {"ddivq.", XRC(63,546,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRAp
, FRBp
}},
9395 {"xsdivqp", XRC(63,548,0), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9396 {"xsdivqpo", XRC(63,548,1), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9398 {"mffs", XRC(63,583,0), XRARB_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
}},
9399 {"mffs.", XRC(63,583,1), XRARB_MASK
, COM
, PPCEFS
|PPCVLE
, {FRT
}},
9401 {"mffsce", XMMF(63,583,0,1), XMMF_MASK
|RB_MASK
, POWER9
, PPCVLE
, {FRT
}},
9402 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK
, POWER9
, PPCVLE
, {FRT
, FRB
}},
9403 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK
|(3<<14), POWER9
, PPCVLE
, {FRT
, DRM
}},
9404 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK
, POWER9
, PPCVLE
, {FRT
, FRB
}},
9405 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK
|(7<<13), POWER9
, PPCVLE
, {FRT
, RM
}},
9406 {"mffsl", XMMF(63,583,3,0), XMMF_MASK
|RB_MASK
, POWER9
, PPCVLE
, {FRT
}},
9408 {"dcmpuq", X(63,642), X_MASK
, POWER6
, PPCVLE
, {BF
, FRAp
, FRBp
}},
9410 {"xscmpuqp", X(63,644), XBF_MASK
, PPCVSX3
, PPCVLE
, {BF
, VA
, VB
}},
9412 {"dtstsfq", X(63,674), X_MASK
, POWER6
, PPCVLE
, {BF
, FRA
, FRBp
}},
9413 {"dtstsfiq", X(63,675), X_MASK
|1<<22,POWER9
, PPCVLE
, {BF
, UIM6
, FRBp
}},
9415 {"xsmaxcqp", X(63,676), X_MASK
, POWER10
, PPCVLE
, {VD
, VA
, VB
}},
9417 {"xststdcqp", X(63,708), X_MASK
, PPCVSX3
, PPCVLE
, {BF
, VB
, DCMX
}},
9419 {"mtfsf", XFL(63,711,0), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FLM
, FRB
, XFL_L
, W
}},
9420 {"mtfsf", XFL(63,711,0), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
|PPCVLE
, {FLM
, FRB
}},
9421 {"mtfsf.", XFL(63,711,1), XFL_MASK
, POWER6
|PPCA2
|PPC476
, PPCVLE
, {FLM
, FRB
, XFL_L
, W
}},
9422 {"mtfsf.", XFL(63,711,1), XFL_MASK
, COM
, POWER6
|PPCA2
|PPC476
|PPCEFS
|PPCVLE
, {FLM
, FRB
}},
9424 {"xsmincqp", X(63,740), X_MASK
, POWER10
, PPCVLE
, {VD
, VA
, VB
}},
9426 {"drdpq", XRC(63,770,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRBp
}},
9427 {"drdpq.", XRC(63,770,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRBp
}},
9429 {"dcffixq", XRC(63,802,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
9430 {"dcffixq.", XRC(63,802,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRB
}},
9432 {"xsabsqp", XVA(63,804,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9433 {"xsxexpqp", XVA(63,804,2), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9434 {"xsnabsqp", XVA(63,804,8), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9435 {"xsnegqp", XVA(63,804,16), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9436 {"xsxsigqp", XVA(63,804,18), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9437 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9438 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9440 {"fctid", XRC(63,814,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
9441 {"fctid", XRC(63,814,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
9442 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
9443 {"fctid.", XRC(63,814,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
9445 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
9446 {"fctidz", XRC(63,815,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
9447 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
9448 {"fctidz.", XRC(63,815,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
9450 {"denbcdq", XRC(63,834,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {S
, FRTp
, FRBp
}},
9451 {"denbcdq.", XRC(63,834,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {S
, FRTp
, FRBp
}},
9453 {"xscvqpuqz", XVA(63,836,0), XVA_MASK
, POWER10
, PPCVLE
, {VD
, VB
}},
9454 {"xscvqpuwz", XVA(63,836,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9455 {"xscvudqp", XVA(63,836,2), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9456 {"xscvuqqp", XVA(63,836,3), XVA_MASK
, POWER10
, PPCVLE
, {VD
, VB
}},
9457 {"xscvqpsqz", XVA(63,836,8), XVA_MASK
, POWER10
, PPCVLE
, {VD
, VB
}},
9458 {"xscvqpswz", XVA(63,836,9), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9459 {"xscvsdqp", XVA(63,836,10), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9460 {"xscvsqqp", XVA(63,836,11), XVA_MASK
, POWER10
, PPCVLE
, {VD
, VB
}},
9461 {"xscvqpudz", XVA(63,836,17), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9462 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9463 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9464 {"xscvdpqp", XVA(63,836,22), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9465 {"xscvqpsdz", XVA(63,836,25), XVA_MASK
, PPCVSX3
, PPCVLE
, {VD
, VB
}},
9467 {"fmrgow", X(63,838), X_MASK
, PPCVSX2
, PPCVLE
, {FRT
, FRA
, FRB
}},
9469 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
9470 {"fcfid", XRC(63,846,0), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
9471 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC64
, PPCVLE
, {FRT
, FRB
}},
9472 {"fcfid.", XRC(63,846,1), XRA_MASK
, PPC476
, PPCVLE
, {FRT
, FRB
}},
9474 {"diexq", XRC(63,866,0), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
}},
9475 {"diexq.", XRC(63,866,1), X_MASK
|Q_MASK
, POWER6
, PPCVLE
, {FRTp
, FRA
, FRBp
}},
9477 {"xsiexpqp", X(63,868), X_MASK
, PPCVSX3
, PPCVLE
, {VD
, VA
, VB
}},
9479 {"fctidu", XRC(63,942,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
9480 {"fctidu.", XRC(63,942,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
9482 {"fctiduz", XRC(63,943,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
9483 {"fctiduz.", XRC(63,943,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
9485 {"fmrgew", X(63,966), X_MASK
, PPCVSX2
, PPCVLE
, {FRT
, FRA
, FRB
}},
9487 {"fcfidu", XRC(63,974,0), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
9488 {"fcfidu.", XRC(63,974,1), XRA_MASK
, POWER7
|PPCA2
, PPCVLE
, {FRT
, FRB
}},
9490 {"dcffixqq", XVA(63,994,0), XVA_MASK
, POWER10
, PPCVLE
, {FRTp
, VB
}},
9491 {"dctfixqq", XVA(63,994,1), XVA_MASK
, POWER10
, PPCVLE
, {VD
, FRBp
}},
9494 const unsigned int powerpc_num_opcodes
=
9495 sizeof (powerpc_opcodes
) / sizeof (powerpc_opcodes
[0]);
9497 /* The opcode table for 8-byte prefix instructions.
9499 The format of this opcode table is the same as the main opcode table. */
9501 const struct powerpc_opcode prefix_opcodes
[] = {
9502 {"pnop", PMRR
, PREFIX_MASK
, POWER10
, 0, {0}},
9503 {"pli", PMLS
|OP(14), P_DRAPCREL_MASK
, POWER10
, EXT
, {RT
, SI34
}},
9504 {"paddi", PMLS
|OP(14), P_D_MASK
, POWER10
, 0, {RT
, RA0
, SI34
, PCREL0
}},
9505 {"psubi", PMLS
|OP(14), P_D_MASK
, POWER10
, EXT
, {RT
, RA0
, NSI34
, PCREL0
}},
9506 {"pla", PMLS
|OP(14), P_D_MASK
, POWER10
, EXT
, {RT
, D34
, PRA0
, PCREL
}},
9507 {"xxsplti32dx", P8RR
|VSOP(32,0), P_VSI_MASK
, POWER10
, 0, {XTS
, IX
, IMM32
}},
9508 {"xxspltidp", P8RR
|VSOP(32,2), P_VS_MASK
, POWER10
, 0, {XTS
, IMM32
}},
9509 {"xxspltiw", P8RR
|VSOP(32,3), P_VS_MASK
, POWER10
, 0, {XTS
, IMM32
}},
9510 {"plwz", PMLS
|OP(32), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
9511 {"xxblendvb", P8RR
|XX4(33,0), P_XX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
}},
9512 {"xxblendvh", P8RR
|XX4(33,1), P_XX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
}},
9513 {"xxblendvw", P8RR
|XX4(33,2), P_XX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
}},
9514 {"xxblendvd", P8RR
|XX4(33,3), P_XX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
}},
9515 {"xxpermx", P8RR
|XX4(34,0), P_UXX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
, UIM3
}},
9516 {"xxeval", P8RR
|XX4(34,1), P_U8XX4_MASK
, POWER10
, 0, {XT6
, XA6
, XB6
, XC6
, UIM8
}},
9517 {"plbz", PMLS
|OP(34), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
9518 {"pstw", PMLS
|OP(36), P_D_MASK
, POWER10
, 0, {RS
, D34
, PRA0
, PCREL
}},
9519 {"pstb", PMLS
|OP(38), P_D_MASK
, POWER10
, 0, {RS
, D34
, PRA0
, PCREL
}},
9520 {"plhz", PMLS
|OP(40), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
9521 {"plwa", P8LS
|OP(41), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
9522 {"plxsd", P8LS
|OP(42), P_D_MASK
, POWER10
, 0, {VD
, D34
, PRA0
, PCREL
}},
9523 {"plha", PMLS
|OP(42), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
9524 {"plxssp", P8LS
|OP(43), P_D_MASK
, POWER10
, 0, {VD
, D34
, PRA0
, PCREL
}},
9525 {"psth", PMLS
|OP(44), P_D_MASK
, POWER10
, 0, {RS
, D34
, PRA0
, PCREL
}},
9526 {"pstxsd", P8LS
|OP(46), P_D_MASK
, POWER10
, 0, {VS
, D34
, PRA0
, PCREL
}},
9527 {"pstxssp", P8LS
|OP(47), P_D_MASK
, POWER10
, 0, {VS
, D34
, PRA0
, PCREL
}},
9528 {"plfs", PMLS
|OP(48), P_D_MASK
, POWER10
, 0, {FRT
, D34
, PRA0
, PCREL
}},
9529 {"plxv", P8LS
|OP(50), P_D_MASK
&~OP(1), POWER10
, 0, {XTOP
, D34
, PRA0
, PCREL
}},
9530 {"plfd", PMLS
|OP(50), P_D_MASK
, POWER10
, 0, {FRT
, D34
, PRA0
, PCREL
}},
9531 {"pstfs", PMLS
|OP(52), P_D_MASK
, POWER10
, 0, {FRS
, D34
, PRA0
, PCREL
}},
9532 {"pstxv", P8LS
|OP(54), P_D_MASK
&~OP(1), POWER10
, 0, {XTOP
, D34
, PRA0
, PCREL
}},
9533 {"pstfd", PMLS
|OP(54), P_D_MASK
, POWER10
, 0, {FRS
, D34
, PRA0
, PCREL
}},
9534 {"plq", P8LS
|OP(56), P_D_MASK
, POWER10
, 0, {RTQ
, D34
, PRAQ
, PCREL
}},
9535 {"pld", P8LS
|OP(57), P_D_MASK
, POWER10
, 0, {RT
, D34
, PRA0
, PCREL
}},
9536 {"plxvp", P8LS
|OP(58), P_D_MASK
, POWER10
, 0, {XTP
, D34
, PRA0
, PCREL
}},
9537 {"pmxvi8ger4pp", PMMIRR
|XX3(59,2), P_GER4_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK4
}},
9538 {"pmxvi8ger4", PMMIRR
|XX3(59,3), P_GER4_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK4
}},
9539 {"pmxvf16ger2pp", PMMIRR
|XX3(59,18), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9540 {"pmxvf16ger2", PMMIRR
|XX3(59,19), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9541 {"pmxvf32gerpp", PMMIRR
|XX3(59,26), P_GER_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
}},
9542 {"pmxvf32ger", PMMIRR
|XX3(59,27), P_GER_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
}},
9543 {"pmxvi4ger8pp", PMMIRR
|XX3(59,34), P_GER8_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK8
}},
9544 {"pmxvi4ger8", PMMIRR
|XX3(59,35), P_GER8_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK8
}},
9545 {"pmxvi16ger2spp",PMMIRR
|XX3(59,42), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9546 {"pmxvi16ger2s", PMMIRR
|XX3(59,43), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9547 {"pmxvbf16ger2pp",PMMIRR
|XX3(59,50), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9548 {"pmxvbf16ger2", PMMIRR
|XX3(59,51), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9549 {"pmxvf64gerpp", PMMIRR
|XX3(59,58), P_GER64_MASK
, POWER10
, 0, {ACC
, XA6ap
, XB6a
, XMSK
, YMSK2
}},
9550 {"pmxvf64ger", PMMIRR
|XX3(59,59), P_GER64_MASK
, POWER10
, 0, {ACC
, XA6ap
, XB6a
, XMSK
, YMSK2
}},
9551 {"pmxvi16ger2", PMMIRR
|XX3(59,75), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9552 {"pmxvf16ger2np", PMMIRR
|XX3(59,82), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9553 {"pmxvf32gernp", PMMIRR
|XX3(59,90), P_GER_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
}},
9554 {"pmxvi8ger4spp", PMMIRR
|XX3(59,99), P_GER4_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK4
}},
9555 {"pmxvi16ger2pp", PMMIRR
|XX3(59,107), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9556 {"pmxvbf16ger2np",PMMIRR
|XX3(59,114), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9557 {"pmxvf64gernp", PMMIRR
|XX3(59,122), P_GER64_MASK
, POWER10
, 0, {ACC
, XA6ap
, XB6a
, XMSK
, YMSK2
}},
9558 {"pmxvf16ger2pn", PMMIRR
|XX3(59,146), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9559 {"pmxvf32gerpn", PMMIRR
|XX3(59,154), P_GER_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
}},
9560 {"pmxvbf16ger2pn",PMMIRR
|XX3(59,178), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9561 {"pmxvf64gerpn", PMMIRR
|XX3(59,186), P_GER64_MASK
, POWER10
, 0, {ACC
, XA6ap
, XB6a
, XMSK
, YMSK2
}},
9562 {"pmxvf16ger2nn", PMMIRR
|XX3(59,210), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9563 {"pmxvf32gernn", PMMIRR
|XX3(59,218), P_GER_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
}},
9564 {"pmxvbf16ger2nn",PMMIRR
|XX3(59,242), P_GER2_MASK
, POWER10
, 0, {ACC
, XA6a
, XB6a
, XMSK
, YMSK
, PMSK2
}},
9565 {"pmxvf64gernn", PMMIRR
|XX3(59,250), P_GER64_MASK
, POWER10
, 0, {ACC
, XA6ap
, XB6a
, XMSK
, YMSK2
}},
9566 {"pstq", P8LS
|OP(60), P_D_MASK
, POWER10
, 0, {RSQ
, D34
, PRA0
, PCREL
}},
9567 {"pstd", P8LS
|OP(61), P_D_MASK
, POWER10
, 0, {RS
, D34
, PRA0
, PCREL
}},
9568 {"pstxvp", P8LS
|OP(62), P_D_MASK
, POWER10
, 0, {XTP
, D34
, PRA0
, PCREL
}},
9571 const unsigned int prefix_num_opcodes
=
9572 sizeof (prefix_opcodes
) / sizeof (prefix_opcodes
[0]);
9574 /* The VLE opcode table.
9576 The format of this opcode table is the same as the main opcode table. */
9578 const struct powerpc_opcode vle_opcodes
[] = {
9579 {"se_illegal", C(0), C_MASK
, PPCVLE
, 0, {}},
9580 {"se_isync", C(1), C_MASK
, PPCVLE
, 0, {}},
9581 {"se_sc", C(2), C_MASK
, PPCVLE
, 0, {}},
9582 {"se_blr", C_LK(2,0), C_LK_MASK
, PPCVLE
, 0, {}},
9583 {"se_blrl", C_LK(2,1), C_LK_MASK
, PPCVLE
, 0, {}},
9584 {"se_bctr", C_LK(3,0), C_LK_MASK
, PPCVLE
, 0, {}},
9585 {"se_bctrl", C_LK(3,1), C_LK_MASK
, PPCVLE
, 0, {}},
9586 {"se_rfi", C(8), C_MASK
, PPCVLE
, 0, {}},
9587 {"se_rfci", C(9), C_MASK
, PPCVLE
, 0, {}},
9588 {"se_rfdi", C(10), C_MASK
, PPCVLE
, 0, {}},
9589 {"se_rfmci", C(11), C_MASK
, PPCRFMCI
|PPCVLE
, 0, {}},
9590 {"se_rfgi", C(12), C_MASK
, PPCVLE
, 0, {}},
9591 {"se_not", SE_R(0,2), SE_R_MASK
, PPCVLE
, 0, {RX
}},
9592 {"se_neg", SE_R(0,3), SE_R_MASK
, PPCVLE
, 0, {RX
}},
9593 {"se_mflr", SE_R(0,8), SE_R_MASK
, PPCVLE
, 0, {RX
}},
9594 {"se_mtlr", SE_R(0,9), SE_R_MASK
, PPCVLE
, 0, {RX
}},
9595 {"se_mfctr", SE_R(0,10), SE_R_MASK
, PPCVLE
, 0, {RX
}},
9596 {"se_mtctr", SE_R(0,11), SE_R_MASK
, PPCVLE
, 0, {RX
}},
9597 {"se_extzb", SE_R(0,12), SE_R_MASK
, PPCVLE
, 0, {RX
}},
9598 {"se_extsb", SE_R(0,13), SE_R_MASK
, PPCVLE
, 0, {RX
}},
9599 {"se_extzh", SE_R(0,14), SE_R_MASK
, PPCVLE
, 0, {RX
}},
9600 {"se_extsh", SE_R(0,15), SE_R_MASK
, PPCVLE
, 0, {RX
}},
9601 {"se_mr", SE_RR(0,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9602 {"se_mtar", SE_RR(0,2), SE_RR_MASK
, PPCVLE
, 0, {ARX
, RY
}},
9603 {"se_mfar", SE_RR(0,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, ARY
}},
9604 {"se_add", SE_RR(1,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9605 {"se_mullw", SE_RR(1,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9606 {"se_sub", SE_RR(1,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9607 {"se_subf", SE_RR(1,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9608 {"se_cmp", SE_RR(3,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9609 {"se_cmpl", SE_RR(3,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9610 {"se_cmph", SE_RR(3,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9611 {"se_cmphl", SE_RR(3,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
9613 /* by major opcode */
9614 {"zvaddih", VX(4, 0x200), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
9615 {"zvsubifh", VX(4, 0x201), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
9616 {"zvaddh", VX(4, 0x204), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9617 {"zvsubfh", VX(4, 0x205), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9618 {"zvaddsubfh", VX(4, 0x206), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9619 {"zvsubfaddh", VX(4, 0x207), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9620 {"zvaddhx", VX(4, 0x20C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9621 {"zvsubfhx", VX(4, 0x20D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9622 {"zvaddsubfhx", VX(4, 0x20E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9623 {"zvsubfaddhx", VX(4, 0x20F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9624 {"zaddwus", VX(4, 0x210), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9625 {"zsubfwus", VX(4, 0x211), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9626 {"zaddwss", VX(4, 0x212), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9627 {"zsubfwss", VX(4, 0x213), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9628 {"zvaddhus", VX(4, 0x214), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9629 {"zvsubfhus", VX(4, 0x215), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9630 {"zvaddhss", VX(4, 0x216), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9631 {"zvsubfhss", VX(4, 0x217), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9632 {"zvaddsubfhss", VX(4, 0x21A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9633 {"zvsubfaddhss", VX(4, 0x21B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9634 {"zvaddhxss", VX(4, 0x21C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9635 {"zvsubfhxss", VX(4, 0x21D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9636 {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9637 {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9638 {"zaddheuw", VX(4, 0x220), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9639 {"zsubfheuw", VX(4, 0x221), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9640 {"zaddhesw", VX(4, 0x222), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9641 {"zsubfhesw", VX(4, 0x223), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9642 {"zaddhouw", VX(4, 0x224), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9643 {"zsubfhouw", VX(4, 0x225), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9644 {"zaddhosw", VX(4, 0x226), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9645 {"zsubfhosw", VX(4, 0x227), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9646 {"zvmergehih", VX(4, 0x22C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9647 {"zvmergeloh", VX(4, 0x22D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9648 {"zvmergehiloh", VX(4, 0x22E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9649 {"zvmergelohih", VX(4, 0x22F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9650 {"zvcmpgthu", VX(4, 0x230), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
9651 {"zvcmpgths", VX(4, 0x230), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
9652 {"zvcmplthu", VX(4, 0x231), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
9653 {"zvcmplths", VX(4, 0x231), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
9654 {"zvcmpeqh", VX(4, 0x232), VX_MASK
, PPCLSP
, 0, {CRFD
, RA
, RB
}},
9655 {"zpkswgshfrs", VX(4, 0x238), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9656 {"zpkswgswfrs", VX(4, 0x239), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9657 {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9658 {"zvpkswshfrs", VX(4, 0x23B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9659 {"zvpkswuhs", VX(4, 0x23C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9660 {"zvpkswshs", VX(4, 0x23D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9661 {"zvpkuwuhs", VX(4, 0x23E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9662 {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, SIMM
}},
9663 {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, SIMM
}},
9664 {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9665 {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9666 {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9667 {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9668 {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9669 {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9670 {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9671 {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9672 {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9673 {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9674 {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9675 {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9676 {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9677 {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9678 {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9679 {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9680 {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9681 {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9682 {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9683 {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9684 {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9685 {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK
, PPCLSP
, 0, {RD
, RA
}},
9686 {"zsatsduw", VX(4, 0x260), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9687 {"zsatsdsw", VX(4, 0x261), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9688 {"zsatuduw", VX(4, 0x262), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9689 {"zvselh", VX(4, 0x264), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9690 {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK
, PPCLSP
, 0, {RD
, RA
, RB
, VX_OFF
}},
9691 {"zbrminc", VX(4, 0x268), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9692 {"zcircinc", VX(4, 0x269), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9693 {"zdivwsf", VX(4, 0x26B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9694 {"zvsrhu", VX(4, 0x270), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9695 {"zvsrhs", VX(4, 0x271), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9696 {"zvsrhiu", VX(4, 0x272), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
9697 {"zvsrhis", VX(4, 0x273), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
9698 {"zvslh", VX(4, 0x274), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9699 {"zvrlh", VX(4, 0x275), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9700 {"zvslhi", VX(4, 0x276), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
9701 {"zvrlhi", VX(4, 0x277), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
9702 {"zvslhus", VX(4, 0x278), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9703 {"zvslhss", VX(4, 0x279), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9704 {"zvslhius", VX(4, 0x27A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
9705 {"zvslhiss", VX(4, 0x27B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM_LT16
}},
9706 {"zslwus", VX(4, 0x27C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9707 {"zslwss", VX(4, 0x27D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9708 {"zslwius", VX(4, 0x27E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
9709 {"zslwiss", VX(4, 0x27F), VX_MASK
, PPCLSP
, 0, {RD
, RA
, EVUIMM
}},
9710 {"zaddwgui", VX(4, 0x460), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9711 {"zsubfwgui", VX(4, 0x461), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9712 {"zaddd", VX(4, 0x462), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9713 {"zsubfd", VX(4, 0x463), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9714 {"zvaddsubfw", VX(4, 0x464), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9715 {"zvsubfaddw", VX(4, 0x465), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9716 {"zvaddw", VX(4, 0x466), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9717 {"zvsubfw", VX(4, 0x467), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9718 {"zaddwgsi", VX(4, 0x468), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9719 {"zsubfwgsi", VX(4, 0x469), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9720 {"zadddss", VX(4, 0x46A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9721 {"zsubfdss", VX(4, 0x46B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9722 {"zvaddsubfwss", VX(4, 0x46C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9723 {"zvsubfaddwss", VX(4, 0x46D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9724 {"zvaddwss", VX(4, 0x46E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9725 {"zvsubfwss", VX(4, 0x46F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9726 {"zaddwgsf", VX(4, 0x470), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9727 {"zsubfwgsf", VX(4, 0x471), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9728 {"zadddus", VX(4, 0x472), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9729 {"zsubfdus", VX(4, 0x473), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9730 {"zvaddwus", VX(4, 0x476), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9731 {"zvsubfwus", VX(4, 0x477), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9732 {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
9733 {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
9734 {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
9735 {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
9736 {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
}},
9737 {"zvdotphgwasmf", VX(4, 0x488), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9738 {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9739 {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9740 {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9741 {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9742 {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9743 {"zvmhulgwsmf", VX(4, 0x490), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9744 {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9745 {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9746 {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9747 {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9748 {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9749 {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9750 {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9751 {"zmhegwsmf", VX(4, 0x498), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9752 {"zmhegwsmfr", VX(4, 0x499), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9753 {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9754 {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9755 {"zmhegwsmfan", VX(4, 0x49C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9756 {"zmhegwsmfran", VX(4, 0x49D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9757 {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9758 {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9759 {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9760 {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9761 {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9762 {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9763 {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9764 {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9765 {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9766 {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9767 {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9768 {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9769 {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9770 {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9771 {"zmheogwsmf", VX(4, 0x4B8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9772 {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9773 {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9774 {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9775 {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9776 {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9777 {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9778 {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9779 {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9780 {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9781 {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9782 {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9783 {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9784 {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9785 {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9786 {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9787 {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9788 {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9789 {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9790 {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9791 {"zmhogwsmf", VX(4, 0x4D8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9792 {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9793 {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9794 {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9795 {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9796 {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
9797 {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9798 {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9799 {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9800 {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9801 {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9802 {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9803 {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9804 {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9805 {"zmhegui", VX(4, 0x500), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9806 {"zvdotphgaui", VX(4, 0x501), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9807 {"zmheguiaa", VX(4, 0x502), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9808 {"zvdotphgauiaa", VX(4, 0x503), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9809 {"zmheguian", VX(4, 0x504), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9810 {"zvdotphgauian", VX(4, 0x505), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9811 {"zmhegsi", VX(4, 0x508), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9812 {"zvdotphgasi", VX(4, 0x509), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9813 {"zmhegsiaa", VX(4, 0x50A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9814 {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9815 {"zmhegsian", VX(4, 0x50C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9816 {"zvdotphgasian", VX(4, 0x50D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9817 {"zmhegsui", VX(4, 0x510), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9818 {"zvdotphgasui", VX(4, 0x511), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9819 {"zmhegsuiaa", VX(4, 0x512), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9820 {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9821 {"zmhegsuian", VX(4, 0x514), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9822 {"zvdotphgasuian", VX(4, 0x515), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9823 {"zmhegsmf", VX(4, 0x518), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9824 {"zvdotphgasmf", VX(4, 0x519), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9825 {"zmhegsmfaa", VX(4, 0x51A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9826 {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9827 {"zmhegsmfan", VX(4, 0x51C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9828 {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9829 {"zmheogui", VX(4, 0x520), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9830 {"zvdotphxgaui", VX(4, 0x521), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9831 {"zmheoguiaa", VX(4, 0x522), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9832 {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9833 {"zmheoguian", VX(4, 0x524), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9834 {"zvdotphxgauian", VX(4, 0x525), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9835 {"zmheogsi", VX(4, 0x528), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9836 {"zvdotphxgasi", VX(4, 0x529), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9837 {"zmheogsiaa", VX(4, 0x52A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9838 {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9839 {"zmheogsian", VX(4, 0x52C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9840 {"zvdotphxgasian", VX(4, 0x52D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9841 {"zmheogsui", VX(4, 0x530), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9842 {"zvdotphxgasui", VX(4, 0x531), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9843 {"zmheogsuiaa", VX(4, 0x532), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9844 {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9845 {"zmheogsuian", VX(4, 0x534), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9846 {"zvdotphxgasuian", VX(4, 0x535), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9847 {"zmheogsmf", VX(4, 0x538), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9848 {"zvdotphxgasmf", VX(4, 0x539), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9849 {"zmheogsmfaa", VX(4, 0x53A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9850 {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9851 {"zmheogsmfan", VX(4, 0x53C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9852 {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9853 {"zmhogui", VX(4, 0x540), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9854 {"zvdotphgsui", VX(4, 0x541), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9855 {"zmhoguiaa", VX(4, 0x542), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9856 {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9857 {"zmhoguian", VX(4, 0x544), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9858 {"zvdotphgsuian", VX(4, 0x545), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9859 {"zmhogsi", VX(4, 0x548), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9860 {"zvdotphgssi", VX(4, 0x549), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9861 {"zmhogsiaa", VX(4, 0x54A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9862 {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9863 {"zmhogsian", VX(4, 0x54C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9864 {"zvdotphgssian", VX(4, 0x54D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9865 {"zmhogsui", VX(4, 0x550), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9866 {"zvdotphgssui", VX(4, 0x551), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9867 {"zmhogsuiaa", VX(4, 0x552), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9868 {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9869 {"zmhogsuian", VX(4, 0x554), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9870 {"zvdotphgssuian", VX(4, 0x555), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9871 {"zmhogsmf", VX(4, 0x558), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9872 {"zvdotphgssmf", VX(4, 0x559), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9873 {"zmhogsmfaa", VX(4, 0x55A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9874 {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9875 {"zmhogsmfan", VX(4, 0x55C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9876 {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9877 {"zmwgui", VX(4, 0x560), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9878 {"zmwguiaa", VX(4, 0x562), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9879 {"zmwguiaas", VX(4, 0x563), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9880 {"zmwguian", VX(4, 0x564), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9881 {"zmwguians", VX(4, 0x565), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9882 {"zmwgsi", VX(4, 0x568), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9883 {"zmwgsiaa", VX(4, 0x56A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9884 {"zmwgsiaas", VX(4, 0x56B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9885 {"zmwgsian", VX(4, 0x56C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9886 {"zmwgsians", VX(4, 0x56D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9887 {"zmwgsui", VX(4, 0x570), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9888 {"zmwgsuiaa", VX(4, 0x572), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9889 {"zmwgsuiaas", VX(4, 0x573), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9890 {"zmwgsuian", VX(4, 0x574), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9891 {"zmwgsuians", VX(4, 0x575), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9892 {"zmwgsmf", VX(4, 0x578), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9893 {"zmwgsmfr", VX(4, 0x579), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9894 {"zmwgsmfaa", VX(4, 0x57A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9895 {"zmwgsmfraa", VX(4, 0x57B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9896 {"zmwgsmfan", VX(4, 0x57C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9897 {"zmwgsmfran", VX(4, 0x57D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9898 {"zvmhului", VX(4, 0x580), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9899 {"zvmhuluiaa", VX(4, 0x582), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9900 {"zvmhuluiaas", VX(4, 0x583), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9901 {"zvmhuluian", VX(4, 0x584), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9902 {"zvmhuluians", VX(4, 0x585), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9903 {"zvmhuluianp", VX(4, 0x586), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9904 {"zvmhuluianps", VX(4, 0x587), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9905 {"zvmhulsi", VX(4, 0x588), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9906 {"zvmhulsiaa", VX(4, 0x58A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9907 {"zvmhulsiaas", VX(4, 0x58B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9908 {"zvmhulsian", VX(4, 0x58C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9909 {"zvmhulsians", VX(4, 0x58D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9910 {"zvmhulsianp", VX(4, 0x58E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9911 {"zvmhulsianps", VX(4, 0x58F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9912 {"zvmhulsui", VX(4, 0x590), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9913 {"zvmhulsuiaa", VX(4, 0x592), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9914 {"zvmhulsuiaas", VX(4, 0x593), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9915 {"zvmhulsuian", VX(4, 0x594), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9916 {"zvmhulsuians", VX(4, 0x595), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9917 {"zvmhulsuianp", VX(4, 0x596), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9918 {"zvmhulsuianps", VX(4, 0x597), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9919 {"zvmhulsf", VX(4, 0x598), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9920 {"zvmhulsfr", VX(4, 0x599), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9921 {"zvmhulsfaas", VX(4, 0x59A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9922 {"zvmhulsfraas", VX(4, 0x59B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9923 {"zvmhulsfans", VX(4, 0x59C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9924 {"zvmhulsfrans", VX(4, 0x59D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9925 {"zvmhulsfanps", VX(4, 0x59E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9926 {"zvmhulsfranps", VX(4, 0x59F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9927 {"zvmhllui", VX(4, 0x5A0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9928 {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9929 {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9930 {"zvmhlluian", VX(4, 0x5A4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9931 {"zvmhlluians", VX(4, 0x5A5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9932 {"zvmhlluianp", VX(4, 0x5A6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9933 {"zvmhlluianps", VX(4, 0x5A7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9934 {"zvmhllsi", VX(4, 0x5A8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9935 {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9936 {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9937 {"zvmhllsian", VX(4, 0x5AC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9938 {"zvmhllsians", VX(4, 0x5AD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9939 {"zvmhllsianp", VX(4, 0x5AE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9940 {"zvmhllsianps", VX(4, 0x5AF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9941 {"zvmhllsui", VX(4, 0x5B0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9942 {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9943 {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9944 {"zvmhllsuian", VX(4, 0x5B4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9945 {"zvmhllsuians", VX(4, 0x5B5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9946 {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9947 {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9948 {"zvmhllsf", VX(4, 0x5B8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9949 {"zvmhllsfr", VX(4, 0x5B9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9950 {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9951 {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9952 {"zvmhllsfans", VX(4, 0x5BC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9953 {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9954 {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9955 {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9956 {"zvmhuuui", VX(4, 0x5C0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9957 {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9958 {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9959 {"zvmhuuuian", VX(4, 0x5C4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9960 {"zvmhuuuians", VX(4, 0x5C5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9961 {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9962 {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9963 {"zvmhuusi", VX(4, 0x5C8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9964 {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9965 {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9966 {"zvmhuusian", VX(4, 0x5CC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9967 {"zvmhuusians", VX(4, 0x5CD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9968 {"zvmhuusianp", VX(4, 0x5CE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9969 {"zvmhuusianps", VX(4, 0x5CF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9970 {"zvmhuusui", VX(4, 0x5D0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9971 {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9972 {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9973 {"zvmhuusuian", VX(4, 0x5D4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9974 {"zvmhuusuians", VX(4, 0x5D5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9975 {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9976 {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9977 {"zvmhuusf", VX(4, 0x5D8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9978 {"zvmhuusfr", VX(4, 0x5D9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9979 {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9980 {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9981 {"zvmhuusfans", VX(4, 0x5DC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9982 {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9983 {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9984 {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9985 {"zvmhxlui", VX(4, 0x5E0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9986 {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9987 {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9988 {"zvmhxluian", VX(4, 0x5E4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9989 {"zvmhxluians", VX(4, 0x5E5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9990 {"zvmhxluianp", VX(4, 0x5E6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9991 {"zvmhxluianps", VX(4, 0x5E7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9992 {"zvmhxlsi", VX(4, 0x5E8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9993 {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9994 {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9995 {"zvmhxlsian", VX(4, 0x5EC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9996 {"zvmhxlsians", VX(4, 0x5ED), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9997 {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9998 {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
9999 {"zvmhxlsui", VX(4, 0x5F0), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10000 {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10001 {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10002 {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10003 {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10004 {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10005 {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10006 {"zvmhxlsf", VX(4, 0x5F8), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10007 {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10008 {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10009 {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10010 {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10011 {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10012 {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10013 {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10014 {"zmheui", VX(4, 0x600), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10015 {"zmheuiaa", VX(4, 0x602), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10016 {"zmheuiaas", VX(4, 0x603), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10017 {"zmheuian", VX(4, 0x604), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10018 {"zmheuians", VX(4, 0x605), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10019 {"zmhesi", VX(4, 0x608), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10020 {"zmhesiaa", VX(4, 0x60A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10021 {"zmhesiaas", VX(4, 0x60B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10022 {"zmhesian", VX(4, 0x60C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10023 {"zmhesians", VX(4, 0x60D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10024 {"zmhesui", VX(4, 0x610), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10025 {"zmhesuiaa", VX(4, 0x612), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10026 {"zmhesuiaas", VX(4, 0x613), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10027 {"zmhesuian", VX(4, 0x614), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10028 {"zmhesuians", VX(4, 0x615), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10029 {"zmhesf", VX(4, 0x618), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10030 {"zmhesfr", VX(4, 0x619), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10031 {"zmhesfaas", VX(4, 0x61A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10032 {"zmhesfraas", VX(4, 0x61B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10033 {"zmhesfans", VX(4, 0x61C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10034 {"zmhesfrans", VX(4, 0x61D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10035 {"zmheoui", VX(4, 0x620), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10036 {"zmheouiaa", VX(4, 0x622), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10037 {"zmheouiaas", VX(4, 0x623), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10038 {"zmheouian", VX(4, 0x624), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10039 {"zmheouians", VX(4, 0x625), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10040 {"zmheosi", VX(4, 0x628), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10041 {"zmheosiaa", VX(4, 0x62A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10042 {"zmheosiaas", VX(4, 0x62B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10043 {"zmheosian", VX(4, 0x62C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10044 {"zmheosians", VX(4, 0x62D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10045 {"zmheosui", VX(4, 0x630), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10046 {"zmheosuiaa", VX(4, 0x632), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10047 {"zmheosuiaas", VX(4, 0x633), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10048 {"zmheosuian", VX(4, 0x634), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10049 {"zmheosuians", VX(4, 0x635), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10050 {"zmheosf", VX(4, 0x638), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10051 {"zmheosfr", VX(4, 0x639), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10052 {"zmheosfaas", VX(4, 0x63A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10053 {"zmheosfraas", VX(4, 0x63B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10054 {"zmheosfans", VX(4, 0x63C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10055 {"zmheosfrans", VX(4, 0x63D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10056 {"zmhoui", VX(4, 0x640), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10057 {"zmhouiaa", VX(4, 0x642), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10058 {"zmhouiaas", VX(4, 0x643), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10059 {"zmhouian", VX(4, 0x644), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10060 {"zmhouians", VX(4, 0x645), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10061 {"zmhosi", VX(4, 0x648), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10062 {"zmhosiaa", VX(4, 0x64A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10063 {"zmhosiaas", VX(4, 0x64B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10064 {"zmhosian", VX(4, 0x64C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10065 {"zmhosians", VX(4, 0x64D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10066 {"zmhosui", VX(4, 0x650), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10067 {"zmhosuiaa", VX(4, 0x652), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10068 {"zmhosuiaas", VX(4, 0x653), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10069 {"zmhosuian", VX(4, 0x654), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10070 {"zmhosuians", VX(4, 0x655), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10071 {"zmhosf", VX(4, 0x658), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10072 {"zmhosfr", VX(4, 0x659), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10073 {"zmhosfaas", VX(4, 0x65A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10074 {"zmhosfraas", VX(4, 0x65B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10075 {"zmhosfans", VX(4, 0x65C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10076 {"zmhosfrans", VX(4, 0x65D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10077 {"zvmhuih", VX(4, 0x660), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10078 {"zvmhuihs", VX(4, 0x661), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10079 {"zvmhuiaah", VX(4, 0x662), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10080 {"zvmhuiaahs", VX(4, 0x663), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10081 {"zvmhuianh", VX(4, 0x664), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10082 {"zvmhuianhs", VX(4, 0x665), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10083 {"zvmhsihs", VX(4, 0x669), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10084 {"zvmhsiaahs", VX(4, 0x66B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10085 {"zvmhsianhs", VX(4, 0x66D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10086 {"zvmhsuihs", VX(4, 0x671), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10087 {"zvmhsuiaahs", VX(4, 0x673), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10088 {"zvmhsuianhs", VX(4, 0x675), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10089 {"zvmhsfh", VX(4, 0x678), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10090 {"zvmhsfrh", VX(4, 0x679), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10091 {"zvmhsfaahs", VX(4, 0x67A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10092 {"zvmhsfraahs", VX(4, 0x67B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10093 {"zvmhsfanhs", VX(4, 0x67C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10094 {"zvmhsfranhs", VX(4, 0x67D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10095 {"zvdotphaui", VX(4, 0x680), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10096 {"zvdotphauis", VX(4, 0x681), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10097 {"zvdotphauiaa", VX(4, 0x682), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10098 {"zvdotphauiaas", VX(4, 0x683), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10099 {"zvdotphauian", VX(4, 0x684), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10100 {"zvdotphauians", VX(4, 0x685), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10101 {"zvdotphasi", VX(4, 0x688), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10102 {"zvdotphasis", VX(4, 0x689), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10103 {"zvdotphasiaa", VX(4, 0x68A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10104 {"zvdotphasiaas", VX(4, 0x68B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10105 {"zvdotphasian", VX(4, 0x68C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10106 {"zvdotphasians", VX(4, 0x68D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10107 {"zvdotphasui", VX(4, 0x690), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10108 {"zvdotphasuis", VX(4, 0x691), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10109 {"zvdotphasuiaa", VX(4, 0x692), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10110 {"zvdotphasuiaas", VX(4, 0x693), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10111 {"zvdotphasuian", VX(4, 0x694), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10112 {"zvdotphasuians", VX(4, 0x695), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10113 {"zvdotphasfs", VX(4, 0x698), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10114 {"zvdotphasfrs", VX(4, 0x699), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10115 {"zvdotphasfaas", VX(4, 0x69A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10116 {"zvdotphasfraas", VX(4, 0x69B), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10117 {"zvdotphasfans", VX(4, 0x69C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10118 {"zvdotphasfrans", VX(4, 0x69D), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10119 {"zvdotphxaui", VX(4, 0x6A0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10120 {"zvdotphxauis", VX(4, 0x6A1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10121 {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10122 {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10123 {"zvdotphxauian", VX(4, 0x6A4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10124 {"zvdotphxauians", VX(4, 0x6A5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10125 {"zvdotphxasi", VX(4, 0x6A8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10126 {"zvdotphxasis", VX(4, 0x6A9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10127 {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10128 {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10129 {"zvdotphxasian", VX(4, 0x6AC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10130 {"zvdotphxasians", VX(4, 0x6AD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10131 {"zvdotphxasui", VX(4, 0x6B0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10132 {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10133 {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10134 {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10135 {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10136 {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10137 {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10138 {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10139 {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10140 {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10141 {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10142 {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10143 {"zvdotphsui", VX(4, 0x6C0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10144 {"zvdotphsuis", VX(4, 0x6C1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10145 {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10146 {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10147 {"zvdotphsuian", VX(4, 0x6C4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10148 {"zvdotphsuians", VX(4, 0x6C5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10149 {"zvdotphssi", VX(4, 0x6C8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10150 {"zvdotphssis", VX(4, 0x6C9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10151 {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10152 {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10153 {"zvdotphssian", VX(4, 0x6CC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10154 {"zvdotphssians", VX(4, 0x6CD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10155 {"zvdotphssui", VX(4, 0x6D0), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10156 {"zvdotphssuis", VX(4, 0x6D1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10157 {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10158 {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10159 {"zvdotphssuian", VX(4, 0x6D4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10160 {"zvdotphssuians", VX(4, 0x6D5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10161 {"zvdotphssfs", VX(4, 0x6D8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10162 {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10163 {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10164 {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10165 {"zvdotphssfans", VX(4, 0x6DC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10166 {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10167 {"zmwluis", VX(4, 0x6E1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10168 {"zmwluiaa", VX(4, 0x6E2), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10169 {"zmwluiaas", VX(4, 0x6E3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10170 {"zmwluian", VX(4, 0x6E4), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10171 {"zmwluians", VX(4, 0x6E5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10172 {"zmwlsis", VX(4, 0x6E9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10173 {"zmwlsiaas", VX(4, 0x6EB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10174 {"zmwlsians", VX(4, 0x6ED), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10175 {"zmwlsuis", VX(4, 0x6F1), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10176 {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10177 {"zmwlsuians", VX(4, 0x6F5), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10178 {"zmwsf", VX(4, 0x6F8), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10179 {"zmwsfr", VX(4, 0x6F9), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10180 {"zmwsfaas", VX(4, 0x6FA), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10181 {"zmwsfraas", VX(4, 0x6FB), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10182 {"zmwsfans", VX(4, 0x6FC), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10183 {"zmwsfrans", VX(4, 0x6FD), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10184 {"zlddx", VX(4, 0x300), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10185 {"zldd", VX(4, 0x301), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
10186 {"zldwx", VX(4, 0x302), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10187 {"zldw", VX(4, 0x303), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
10188 {"zldhx", VX(4, 0x304), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10189 {"zldh", VX(4, 0x305), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8
, RA
}},
10190 {"zlwgsfdx", VX(4, 0x308), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10191 {"zlwgsfd", VX(4, 0x309), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
10192 {"zlwwosdx", VX(4, 0x30A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10193 {"zlwwosd", VX(4, 0x30B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
10194 {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10195 {"zlwhsplatwd", VX(4, 0x30D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
10196 {"zlwhsplatdx", VX(4, 0x30E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10197 {"zlwhsplatd", VX(4, 0x30F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
10198 {"zlwhgwsfdx", VX(4, 0x310), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10199 {"zlwhgwsfd", VX(4, 0x311), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
10200 {"zlwhedx", VX(4, 0x312), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10201 {"zlwhed", VX(4, 0x313), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
10202 {"zlwhosdx", VX(4, 0x314), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10203 {"zlwhosd", VX(4, 0x315), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
10204 {"zlwhoudx", VX(4, 0x316), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10205 {"zlwhoud", VX(4, 0x317), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4
, RA
}},
10206 {"zlwhx", VX(4, 0x318), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10207 {"zlwh", VX(4, 0x319), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4
, RA
}},
10208 {"zlwwx", VX(4, 0x31A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10209 {"zlww", VX(4, 0x31B), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4
, RA
}},
10210 {"zlhgwsfx", VX(4, 0x31C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10211 {"zlhgwsf", VX(4, 0x31D), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
10212 {"zlhhsplatx", VX(4, 0x31E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10213 {"zlhhsplat", VX(4, 0x31F), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
10214 {"zstddx", VX(4, 0x320), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
10215 {"zstdd", VX(4, 0x321), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
10216 {"zstdwx", VX(4, 0x322), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
10217 {"zstdw", VX(4, 0x323), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
10218 {"zstdhx", VX(4, 0x324), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
10219 {"zstdh", VX(4, 0x325), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8
, RA
}},
10220 {"zstwhedx", VX(4, 0x328), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
10221 {"zstwhed", VX(4, 0x329), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4
, RA
}},
10222 {"zstwhodx", VX(4, 0x32A), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
10223 {"zstwhod", VX(4, 0x32B), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4
, RA
}},
10224 {"zlhhex", VX(4, 0x330), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10225 {"zlhhe", VX(4, 0x331), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
10226 {"zlhhosx", VX(4, 0x332), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10227 {"zlhhos", VX(4, 0x333), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
10228 {"zlhhoux", VX(4, 0x334), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10229 {"zlhhou", VX(4, 0x335), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2
, RA
}},
10230 {"zsthex", VX(4, 0x338), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
10231 {"zsthe", VX(4, 0x339), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2
, RA
}},
10232 {"zsthox", VX(4, 0x33A), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
10233 {"zstho", VX(4, 0x33B), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2
, RA
}},
10234 {"zstwhx", VX(4, 0x33C), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
10235 {"zstwh", VX(4, 0x33D), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4
, RA
}},
10236 {"zstwwx", VX(4, 0x33E), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
10237 {"zstww", VX(4, 0x33F), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4
, RA
}},
10238 {"zlddmx", VX(4, 0x340), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10239 {"zlddu", VX(4, 0x341), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
10240 {"zldwmx", VX(4, 0x342), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10241 {"zldwu", VX(4, 0x343), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
10242 {"zldhmx", VX(4, 0x344), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10243 {"zldhu", VX(4, 0x345), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_8_EX0
, RA
}},
10244 {"zlwgsfdmx", VX(4, 0x348), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10245 {"zlwgsfdu", VX(4, 0x349), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
10246 {"zlwwosdmx", VX(4, 0x34A), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10247 {"zlwwosdu", VX(4, 0x34B), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
10248 {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10249 {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
10250 {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10251 {"zlwhsplatdu", VX(4, 0x34F), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
10252 {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10253 {"zlwhgwsfdu", VX(4, 0x351), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
10254 {"zlwhedmx", VX(4, 0x352), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10255 {"zlwhedu", VX(4, 0x353), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
10256 {"zlwhosdmx", VX(4, 0x354), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10257 {"zlwhosdu", VX(4, 0x355), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
10258 {"zlwhoudmx", VX(4, 0x356), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, RA
, RB
}},
10259 {"zlwhoudu", VX(4, 0x357), VX_MASK
, PPCLSP
, 0, {RD_EVEN
, EVUIMM_4_EX0
, RA
}},
10260 {"zlwhmx", VX(4, 0x358), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10261 {"zlwhu", VX(4, 0x359), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10262 {"zlwwmx", VX(4, 0x35A), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10263 {"zlwwu", VX(4, 0x35B), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10264 {"zlhgwsfmx", VX(4, 0x35C), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10265 {"zlhgwsfu", VX(4, 0x35D), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
10266 {"zlhhsplatmx", VX(4, 0x35E), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10267 {"zlhhsplatu", VX(4, 0x35F), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
10268 {"zstddmx", VX(4, 0x360), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
10269 {"zstddu", VX(4, 0x361), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
10270 {"zstdwmx", VX(4, 0x362), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
10271 {"zstdwu", VX(4, 0x363), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8_EX0
, RA
}},
10272 {"zstdhmx", VX(4, 0x364), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
10273 {"zstdhu", VX(4, 0x365), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_8_EX0
, RA
}},
10274 {"zstwhedmx", VX(4, 0x368), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
10275 {"zstwhedu", VX(4, 0x369), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4_EX0
, RA
}},
10276 {"zstwhodmx", VX(4, 0x36A), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, RA
, RB
}},
10277 {"zstwhodu", VX(4, 0x36B), VX_MASK
, PPCLSP
, 0, {RS_EVEN
, EVUIMM_4_EX0
, RA
}},
10278 {"zlhhemx", VX(4, 0x370), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10279 {"zlhheu", VX(4, 0x371), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
10280 {"zlhhosmx", VX(4, 0x372), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10281 {"zlhhosu", VX(4, 0x373), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
10282 {"zlhhoumx", VX(4, 0x374), VX_MASK
, PPCLSP
, 0, {RD
, RA
, RB
}},
10283 {"zlhhouu", VX(4, 0x375), VX_MASK
, PPCLSP
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
10284 {"zsthemx", VX(4, 0x378), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
10285 {"zstheu", VX(4, 0x379), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
10286 {"zsthomx", VX(4, 0x37A), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
10287 {"zsthou", VX(4, 0x37B), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
10288 {"zstwhmx", VX(4, 0x37C), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
10289 {"zstwhu", VX(4, 0x37D), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
10290 {"zstwwmx", VX(4, 0x37E), VX_MASK
, PPCLSP
, 0, {RS
, RA
, RB
}},
10291 {"zstwwu", VX(4, 0x37F), VX_MASK
, PPCLSP
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
10293 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
10294 {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
10295 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
10296 {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK
, PPCVLE
, 0, {CRD32
, RA
, SCLSCI8
}},
10297 {"e_addi", SCI8(6,16), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
10298 {"e_subi", SCI8(6,16), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8N
}},
10299 {"e_addi.", SCI8(6,17), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
10300 {"e_addic", SCI8(6,18), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
10301 {"e_subic", SCI8(6,18), SCI8_MASK
, PPCVLE
, EXT
, {RT
, RA
, SCLSCI8N
}},
10302 {"e_addic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
10303 {"e_subic.", SCI8(6,19), SCI8_MASK
, PPCVLE
, EXT
, {RT
, RA
, SCLSCI8N
}},
10304 {"e_mulli", SCI8(6,20), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
10305 {"e_subfic", SCI8(6,22), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
10306 {"e_subfic.", SCI8(6,23), SCI8_MASK
, PPCVLE
, 0, {RT
, RA
, SCLSCI8
}},
10307 {"e_andi", SCI8(6,24), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
10308 {"e_andi.", SCI8(6,25), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
10309 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE
, EXT
, {0}},
10310 {"e_ori", SCI8(6,26), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
10311 {"e_ori.", SCI8(6,27), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
10312 {"e_xori", SCI8(6,28), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
10313 {"e_xori.", SCI8(6,29), SCI8_MASK
, PPCVLE
, 0, {RA
, RS
, SCLSCI8
}},
10314 {"e_lbzu", OPVUP(6,0), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
10315 {"e_lhau", OPVUP(6,3), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
10316 {"e_lhzu", OPVUP(6,1), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
10317 {"e_lmw", OPVUP(6,8), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
10318 {"e_lwzu", OPVUP(6,2), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
10319 {"e_stbu", OPVUP(6,4), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
10320 {"e_sthu", OPVUP(6,5), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
10321 {"e_stwu", OPVUP(6,6), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
10322 {"e_stmw", OPVUP(6,9), OPVUP_MASK
, PPCVLE
, 0, {RT
, D8
, RA0
}},
10323 {"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10324 {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10325 {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10326 {"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10327 {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10328 {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10329 {"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10330 {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10331 {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10332 {"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10333 {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10334 {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10335 {"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10336 {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10337 {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10338 {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10339 {"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK
, PPCVLE
, 0, {D8
, RA0
}},
10340 {"e_add16i", OP(7), OP_MASK
, PPCVLE
, 0, {RT
, RA
, SI
}},
10341 {"e_la", OP(7), OP_MASK
, PPCVLE
, EXT
, {RT
, D
, RA0
}},
10342 {"e_sub16i", OP(7), OP_MASK
, PPCVLE
, EXT
, {RT
, RA
, NSI
}},
10344 {"se_addi", SE_IM5(8,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
10345 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
10346 {"se_subi", SE_IM5(9,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
10347 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, OIMM5
}},
10348 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
10349 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
10350 {"se_andi", SE_IM5(11,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
10352 {"e_lbz", OP(12), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
10353 {"e_stb", OP(13), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
10354 {"e_lha", OP(14), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
10356 {"se_srw", SE_RR(16,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
10357 {"se_sraw", SE_RR(16,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
10358 {"se_slw", SE_RR(16,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
10359 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE
, EXT
, {0}},
10360 {"se_or", SE_RR(17,0), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
10361 {"se_andc", SE_RR(17,1), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
10362 {"se_and", SE_RR(17,2), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
10363 {"se_and.", SE_RR(17,3), SE_RR_MASK
, PPCVLE
, 0, {RX
, RY
}},
10364 {"se_li", IM7(9), IM7_MASK
, PPCVLE
, 0, {RX
, UI7
}},
10366 {"e_lwz", OP(20), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
10367 {"e_stw", OP(21), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
10368 {"e_lhz", OP(22), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
10369 {"e_sth", OP(23), OP_MASK
, PPCVLE
, 0, {RT
, D
, RA0
}},
10371 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
10372 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
10373 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
10374 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
10375 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
10376 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
10377 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK
, PPCVLE
, 0, {RX
, UI5
}},
10379 {"e_lis", I16L(28,28), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
10380 {"e_and2is.", I16L(28,29), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
10381 {"e_or2is", I16L(28,26), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
10382 {"e_and2i.", I16L(28,25), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
10383 {"e_or2i", I16L(28,24), I16L_MASK
, PPCVLE
, 0, {RD
, VLEUIMML
}},
10384 {"e_cmphl16i", IA16(28,23), IA16_MASK
, PPCVLE
, 0, {RA
, VLEUIMM
}},
10385 {"e_cmph16i", IA16(28,22), IA16_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
10386 {"e_cmpl16i", I16A(28,21), I16A_MASK
, PPCVLE
, 0, {RA
, VLEUIMM
}},
10387 {"e_mull2i", I16A(28,20), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
10388 {"e_cmp16i", IA16(28,19), IA16_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
10389 {"e_sub2is", I16A(28,18), I16A_MASK
, PPCVLE
, EXT
, {RA
, VLENSIMM
}},
10390 {"e_add2is", I16A(28,18), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
10391 {"e_sub2i.", I16A(28,17), I16A_MASK
, PPCVLE
, EXT
, {RA
, VLENSIMM
}},
10392 {"e_add2i.", I16A(28,17), I16A_MASK
, PPCVLE
, 0, {RA
, VLESIMM
}},
10393 {"e_li", LI20(28,0), LI20_MASK
, PPCVLE
, 0, {RT
, IMM20
}},
10394 {"e_rlwimi", M(29,0), M_MASK
, PPCVLE
, 0, {RA
, RS
, SH
, MB
, ME
}},
10395 {"e_inslwi", M(29,0), M_MASK
, PPCVLE
, EXT
, {RA
, RS
, ILWn
, ILWb
}},
10396 {"e_insrwi", M(29,0), M_MASK
, PPCVLE
, EXT
, {RA
, RS
, IRWn
, IRWb
}},
10397 {"e_rotlwi", MME(29,31,1), MMBME_MASK
, PPCVLE
, EXT
, {RA
, RS
, SH
}},
10398 {"e_rotrwi", MME(29,31,1), MMBME_MASK
, PPCVLE
, EXT
, {RA
, RS
, RRWn
}},
10399 {"e_clrlwi", MME(29,31,1), MSHME_MASK
, PPCVLE
, EXT
, {RA
, RS
, MB
}},
10400 {"e_clrrwi", M(29,1), MSHMB_MASK
, PPCVLE
, EXT
, {RA
, RS
, CRWn
}},
10401 {"e_rlwinm", M(29,1), M_MASK
, PPCVLE
, 0, {RA
, RS
, SH
, MBE
, ME
}},
10402 {"e_extlwi", M(29,1), MMB_MASK
, PPCVLE
, EXT
, {RA
, RS
, ELWn
, SH
}},
10403 {"e_extrwi", MME(29,31,1), MME_MASK
, PPCVLE
, EXT
, {RA
, RS
, ERWn
, ERWb
}},
10404 {"e_clrlslwi", M(29,1), M_MASK
, PPCVLE
, EXT
, {RA
, RS
, CSLWb
, CSLWn
}},
10405 {"e_b", BD24(30,0,0), BD24_MASK
, PPCVLE
, 0, {B24
}},
10406 {"e_bl", BD24(30,0,1), BD24_MASK
, PPCVLE
, 0, {B24
}},
10407 {"e_bdnz", EBD15(30,8,BO32DNZ
,0), EBD15_MASK
, PPCVLE
, EXT
, {B15
}},
10408 {"e_bdnzl", EBD15(30,8,BO32DNZ
,1), EBD15_MASK
, PPCVLE
, EXT
, {B15
}},
10409 {"e_bdz", EBD15(30,8,BO32DZ
,0), EBD15_MASK
, PPCVLE
, EXT
, {B15
}},
10410 {"e_bdzl", EBD15(30,8,BO32DZ
,1), EBD15_MASK
, PPCVLE
, EXT
, {B15
}},
10411 {"e_bge", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10412 {"e_bgel", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10413 {"e_bnl", EBD15BI(30,8,BO32F
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10414 {"e_bnll", EBD15BI(30,8,BO32F
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10415 {"e_blt", EBD15BI(30,8,BO32T
,CBLT
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10416 {"e_bltl", EBD15BI(30,8,BO32T
,CBLT
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10417 {"e_bgt", EBD15BI(30,8,BO32T
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10418 {"e_bgtl", EBD15BI(30,8,BO32T
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10419 {"e_ble", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10420 {"e_blel", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10421 {"e_bng", EBD15BI(30,8,BO32F
,CBGT
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10422 {"e_bngl", EBD15BI(30,8,BO32F
,CBGT
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10423 {"e_bne", EBD15BI(30,8,BO32F
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10424 {"e_bnel", EBD15BI(30,8,BO32F
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10425 {"e_beq", EBD15BI(30,8,BO32T
,CBEQ
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10426 {"e_beql", EBD15BI(30,8,BO32T
,CBEQ
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10427 {"e_bso", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10428 {"e_bsol", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10429 {"e_bun", EBD15BI(30,8,BO32T
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10430 {"e_bunl", EBD15BI(30,8,BO32T
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10431 {"e_bns", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10432 {"e_bnsl", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10433 {"e_bnu", EBD15BI(30,8,BO32F
,CBSO
,0), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10434 {"e_bnul", EBD15BI(30,8,BO32F
,CBSO
,1), EBD15BI_MASK
, PPCVLE
, EXT
, {CRS
,B15
}},
10435 {"e_bc", BD15(30,8,0), BD15_MASK
, PPCVLE
, 0, {BO32
, BI32
, B15
}},
10436 {"e_bcl", BD15(30,8,1), BD15_MASK
, PPCVLE
, 0, {BO32
, BI32
, B15
}},
10438 {"e_bf", EBD15(30,8,BO32F
,0), EBD15_MASK
, PPCVLE
, EXT
, {BI32
,B15
}},
10439 {"e_bfl", EBD15(30,8,BO32F
,1), EBD15_MASK
, PPCVLE
, EXT
, {BI32
,B15
}},
10440 {"e_bt", EBD15(30,8,BO32T
,0), EBD15_MASK
, PPCVLE
, EXT
, {BI32
,B15
}},
10441 {"e_btl", EBD15(30,8,BO32T
,1), EBD15_MASK
, PPCVLE
, EXT
, {BI32
,B15
}},
10443 {"e_cmph", X(31,14), X_MASK
, PPCVLE
, 0, {CRD
, RA
, RB
}},
10444 {"e_sc", X(31,36), XRTRA_MASK
, PPCVLE
, 0, {ELEV
}},
10445 {"e_cmphl", X(31,46), X_MASK
, PPCVLE
, 0, {CRD
, RA
, RB
}},
10446 {"e_crandc", XL(31,129), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
10447 {"e_crnand", XL(31,225), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
10448 {"e_crnot", XL(31,33), XL_MASK
, PPCVLE
, EXT
, {BT
, BAB
}},
10449 {"e_crnor", XL(31,33), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
10450 {"e_crclr", XL(31,193), XL_MASK
, PPCVLE
, EXT
, {BTAB
}},
10451 {"e_crxor", XL(31,193), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
10452 {"e_mcrf", XL(31,16), XL_MASK
, PPCVLE
, 0, {CRD
, CR
}},
10453 {"e_slwi", EX(31,112), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
10454 {"e_slwi.", EX(31,113), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
10456 {"e_crand", XL(31,257), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
10458 {"e_rlw", EX(31,560), EX_MASK
, PPCVLE
, 0, {RA
, RS
, RB
}},
10459 {"e_rlw.", EX(31,561), EX_MASK
, PPCVLE
, 0, {RA
, RS
, RB
}},
10461 {"e_crset", XL(31,289), XL_MASK
, PPCVLE
, EXT
, {BTAB
}},
10462 {"e_creqv", XL(31,289), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
10464 {"e_rlwi", EX(31,624), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
10465 {"e_rlwi.", EX(31,625), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
10467 {"e_crorc", XL(31,417), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
10469 {"e_crmove", XL(31,449), XL_MASK
, PPCVLE
, EXT
, {BT
, BAB
}},
10470 {"e_cror", XL(31,449), XL_MASK
, PPCVLE
, 0, {BT
, BA
, BB
}},
10472 {"mtmas1", XSPR(31,467,625), XSPR_MASK
, PPCVLE
, EXT
, {RS
}},
10474 {"e_srwi", EX(31,1136), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
10475 {"e_srwi.", EX(31,1137), EX_MASK
, PPCVLE
, 0, {RA
, RS
, SH
}},
10477 {"se_lbz", SD4(8), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SD
, RX
}},
10479 {"se_stb", SD4(9), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SD
, RX
}},
10481 {"se_lhz", SD4(10), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDH
, RX
}},
10483 {"se_sth", SD4(11), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDH
, RX
}},
10485 {"se_lwz", SD4(12), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDW
, RX
}},
10487 {"se_stw", SD4(13), SD4_MASK
, PPCVLE
, 0, {RZ
, SE_SDW
, RX
}},
10489 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10490 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10491 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10492 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10493 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10494 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10495 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10496 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK
, PPCVLE
, EXT
, {BI16
, B8
}},
10497 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10498 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10499 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10500 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10501 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK
, PPCVLE
, EXT
, {B8
}},
10502 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK
, PPCVLE
, EXT
, {BI16
, B8
}},
10503 {"se_bc", BD8IO(28), BD8IO_MASK
, PPCVLE
, 0, {BO16
, BI16
, B8
}},
10504 {"se_b", BD8(58,0,0), BD8_MASK
, PPCVLE
, 0, {B8
}},
10505 {"se_bl", BD8(58,0,1), BD8_MASK
, PPCVLE
, 0, {B8
}},
10508 const unsigned int vle_num_opcodes
=
10509 sizeof (vle_opcodes
) / sizeof (vle_opcodes
[0]);
10511 /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */
10512 const struct powerpc_opcode spe2_opcodes
[] = {
10513 {"evdotpwcssi", VX (4, 128), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10514 {"evdotpwcsmi", VX (4, 129), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10515 {"evdotpwcssfr", VX (4, 130), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10516 {"evdotpwcssf", VX (4, 131), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10517 {"evdotpwgasmf", VX (4, 136), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10518 {"evdotpwxgasmf", VX (4, 137), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10519 {"evdotpwgasmfr", VX (4, 138), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10520 {"evdotpwxgasmfr", VX (4, 139), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10521 {"evdotpwgssmf", VX (4, 140), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10522 {"evdotpwxgssmf", VX (4, 141), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10523 {"evdotpwgssmfr", VX (4, 142), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10524 {"evdotpwxgssmfr", VX (4, 143), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10525 {"evdotpwcssiaaw3", VX (4, 144), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10526 {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10527 {"evdotpwcssfraaw3", VX (4, 146), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10528 {"evdotpwcssfaaw3", VX (4, 147), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10529 {"evdotpwgasmfaa3", VX (4, 152), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10530 {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10531 {"evdotpwgasmfraa3", VX (4, 154), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10532 {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10533 {"evdotpwgssmfaa3", VX (4, 156), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10534 {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10535 {"evdotpwgssmfraa3", VX (4, 158), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10536 {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10537 {"evdotpwcssia", VX (4, 160), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10538 {"evdotpwcsmia", VX (4, 161), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10539 {"evdotpwcssfra", VX (4, 162), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10540 {"evdotpwcssfa", VX (4, 163), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10541 {"evdotpwgasmfa", VX (4, 168), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10542 {"evdotpwxgasmfa", VX (4, 169), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10543 {"evdotpwgasmfra", VX (4, 170), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10544 {"evdotpwxgasmfra", VX (4, 171), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10545 {"evdotpwgssmfa", VX (4, 172), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10546 {"evdotpwxgssmfa", VX (4, 173), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10547 {"evdotpwgssmfra", VX (4, 174), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10548 {"evdotpwxgssmfra", VX (4, 175), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10549 {"evdotpwcssiaaw", VX (4, 176), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10550 {"evdotpwcsmiaaw", VX (4, 177), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10551 {"evdotpwcssfraaw", VX (4, 178), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10552 {"evdotpwcssfaaw", VX (4, 179), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10553 {"evdotpwgasmfaa", VX (4, 184), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10554 {"evdotpwxgasmfaa", VX (4, 185), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10555 {"evdotpwgasmfraa", VX (4, 186), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10556 {"evdotpwxgasmfraa", VX (4, 187), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10557 {"evdotpwgssmfaa", VX (4, 188), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10558 {"evdotpwxgssmfaa", VX (4, 189), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10559 {"evdotpwgssmfraa", VX (4, 190), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10560 {"evdotpwxgssmfraa", VX (4, 191), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10561 {"evdotphihcssi", VX (4, 256), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10562 {"evdotplohcssi", VX (4, 257), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10563 {"evdotphihcssf", VX (4, 258), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10564 {"evdotplohcssf", VX (4, 259), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10565 {"evdotphihcsmi", VX (4, 264), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10566 {"evdotplohcsmi", VX (4, 265), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10567 {"evdotphihcssfr", VX (4, 266), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10568 {"evdotplohcssfr", VX (4, 267), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10569 {"evdotphihcssiaaw3", VX (4, 272), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10570 {"evdotplohcssiaaw3", VX (4, 273), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10571 {"evdotphihcssfaaw3", VX (4, 274), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10572 {"evdotplohcssfaaw3", VX (4, 275), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10573 {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10574 {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10575 {"evdotphihcssfraaw3", VX (4, 282), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10576 {"evdotplohcssfraaw3", VX (4, 283), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10577 {"evdotphihcssia", VX (4, 288), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10578 {"evdotplohcssia", VX (4, 289), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10579 {"evdotphihcssfa", VX (4, 290), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10580 {"evdotplohcssfa", VX (4, 291), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10581 {"evdotphihcsmia", VX (4, 296), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10582 {"evdotplohcsmia", VX (4, 297), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10583 {"evdotphihcssfra", VX (4, 298), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10584 {"evdotplohcssfra", VX (4, 299), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10585 {"evdotphihcssiaaw", VX (4, 304), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10586 {"evdotplohcssiaaw", VX (4, 305), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10587 {"evdotphihcssfaaw", VX (4, 306), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10588 {"evdotplohcssfaaw", VX (4, 307), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10589 {"evdotphihcsmiaaw", VX (4, 312), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10590 {"evdotplohcsmiaaw", VX (4, 313), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10591 {"evdotphihcssfraaw", VX (4, 314), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10592 {"evdotplohcssfraaw", VX (4, 315), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10593 {"evdotphausi", VX (4, 320), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10594 {"evdotphassi", VX (4, 321), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10595 {"evdotphasusi", VX (4, 322), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10596 {"evdotphassf", VX (4, 323), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10597 {"evdotphsssf", VX (4, 327), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10598 {"evdotphaumi", VX (4, 328), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10599 {"evdotphasmi", VX (4, 329), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10600 {"evdotphasumi", VX (4, 330), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10601 {"evdotphassfr", VX (4, 331), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10602 {"evdotphssmi", VX (4, 333), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10603 {"evdotphsssi", VX (4, 333), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10604 {"evdotphsssfr", VX (4, 335), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10605 {"evdotphausiaaw3", VX (4, 336), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10606 {"evdotphassiaaw3", VX (4, 337), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10607 {"evdotphasusiaaw3", VX (4, 338), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10608 {"evdotphassfaaw3", VX (4, 339), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10609 {"evdotphsssiaaw3", VX (4, 341), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10610 {"evdotphsssfaaw3", VX (4, 343), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10611 {"evdotphaumiaaw3", VX (4, 344), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10612 {"evdotphasmiaaw3", VX (4, 345), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10613 {"evdotphasumiaaw3", VX (4, 346), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10614 {"evdotphassfraaw3", VX (4, 347), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10615 {"evdotphssmiaaw3", VX (4, 349), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10616 {"evdotphsssfraaw3", VX (4, 351), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10617 {"evdotphausia", VX (4, 352), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10618 {"evdotphassia", VX (4, 353), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10619 {"evdotphasusia", VX (4, 354), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10620 {"evdotphassfa", VX (4, 355), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10621 {"evdotphsssfa", VX (4, 359), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10622 {"evdotphaumia", VX (4, 360), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10623 {"evdotphasmia", VX (4, 361), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10624 {"evdotphasumia", VX (4, 362), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10625 {"evdotphassfra", VX (4, 363), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10626 {"evdotphssmia", VX (4, 365), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10627 {"evdotphsssia", VX (4, 365), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10628 {"evdotphsssfra", VX (4, 367), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10629 {"evdotphausiaaw", VX (4, 368), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10630 {"evdotphassiaaw", VX (4, 369), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10631 {"evdotphasusiaaw", VX (4, 370), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10632 {"evdotphassfaaw", VX (4, 371), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10633 {"evdotphsssiaaw", VX (4, 373), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10634 {"evdotphsssfaaw", VX (4, 375), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10635 {"evdotphaumiaaw", VX (4, 376), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10636 {"evdotphasmiaaw", VX (4, 377), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10637 {"evdotphasumiaaw", VX (4, 378), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10638 {"evdotphassfraaw", VX (4, 379), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10639 {"evdotphssmiaaw", VX (4, 381), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10640 {"evdotphsssfraaw", VX (4, 383), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10641 {"evdotp4hgaumi", VX (4, 384), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10642 {"evdotp4hgasmi", VX (4, 385), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10643 {"evdotp4hgasumi", VX (4, 386), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10644 {"evdotp4hgasmf", VX (4, 387), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10645 {"evdotp4hgssmi", VX (4, 388), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10646 {"evdotp4hgssmf", VX (4, 389), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10647 {"evdotp4hxgasmi", VX (4, 390), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10648 {"evdotp4hxgasmf", VX (4, 391), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10649 {"evdotpbaumi", VX (4, 392), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10650 {"evdotpbasmi", VX (4, 393), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10651 {"evdotpbasumi", VX (4, 394), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10652 {"evdotp4hxgssmi", VX (4, 398), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10653 {"evdotp4hxgssmf", VX (4, 399), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10654 {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10655 {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10656 {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10657 {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10658 {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10659 {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10660 {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10661 {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10662 {"evdotpbaumiaaw3", VX (4, 408), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10663 {"evdotpbasmiaaw3", VX (4, 409), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10664 {"evdotpbasumiaaw3", VX (4, 410), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10665 {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10666 {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10667 {"evdotp4hgaumia", VX (4, 416), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10668 {"evdotp4hgasmia", VX (4, 417), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10669 {"evdotp4hgasumia", VX (4, 418), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10670 {"evdotp4hgasmfa", VX (4, 419), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10671 {"evdotp4hgssmia", VX (4, 420), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10672 {"evdotp4hgssmfa", VX (4, 421), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10673 {"evdotp4hxgasmia", VX (4, 422), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10674 {"evdotp4hxgasmfa", VX (4, 423), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10675 {"evdotpbaumia", VX (4, 424), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10676 {"evdotpbasmia", VX (4, 425), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10677 {"evdotpbasumia", VX (4, 426), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10678 {"evdotp4hxgssmia", VX (4, 430), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10679 {"evdotp4hxgssmfa", VX (4, 431), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10680 {"evdotp4hgaumiaa", VX (4, 432), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10681 {"evdotp4hgasmiaa", VX (4, 433), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10682 {"evdotp4hgasumiaa", VX (4, 434), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10683 {"evdotp4hgasmfaa", VX (4, 435), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10684 {"evdotp4hgssmiaa", VX (4, 436), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10685 {"evdotp4hgssmfaa", VX (4, 437), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10686 {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10687 {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10688 {"evdotpbaumiaaw", VX (4, 440), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10689 {"evdotpbasmiaaw", VX (4, 441), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10690 {"evdotpbasumiaaw", VX (4, 442), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10691 {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10692 {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10693 {"evdotpwausi", VX (4, 448), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10694 {"evdotpwassi", VX (4, 449), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10695 {"evdotpwasusi", VX (4, 450), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10696 {"evdotpwaumi", VX (4, 456), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10697 {"evdotpwasmi", VX (4, 457), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10698 {"evdotpwasumi", VX (4, 458), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10699 {"evdotpwssmi", VX (4, 461), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10700 {"evdotpwsssi", VX (4, 461), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10701 {"evdotpwausiaa3", VX (4, 464), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10702 {"evdotpwassiaa3", VX (4, 465), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10703 {"evdotpwasusiaa3", VX (4, 466), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10704 {"evdotpwsssiaa3", VX (4, 469), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10705 {"evdotpwaumiaa3", VX (4, 472), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10706 {"evdotpwasmiaa3", VX (4, 473), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10707 {"evdotpwasumiaa3", VX (4, 474), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10708 {"evdotpwssmiaa3", VX (4, 477), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10709 {"evdotpwausia", VX (4, 480), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10710 {"evdotpwassia", VX (4, 481), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10711 {"evdotpwasusia", VX (4, 482), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10712 {"evdotpwaumia", VX (4, 488), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10713 {"evdotpwasmia", VX (4, 489), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10714 {"evdotpwasumia", VX (4, 490), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10715 {"evdotpwssmia", VX (4, 493), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10716 {"evdotpwsssia", VX (4, 493), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10717 {"evdotpwausiaa", VX (4, 496), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10718 {"evdotpwassiaa", VX (4, 497), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10719 {"evdotpwasusiaa", VX (4, 498), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10720 {"evdotpwsssiaa", VX (4, 501), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10721 {"evdotpwaumiaa", VX (4, 504), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10722 {"evdotpwasmiaa", VX (4, 505), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10723 {"evdotpwasumiaa", VX (4, 506), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10724 {"evdotpwssmiaa", VX (4, 509), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10725 {"evaddib", VX (4, 515), VX_MASK
, PPCSPE2
, 0, {RD
, RB
, UIMM
}},
10726 {"evaddih", VX (4, 513), VX_MASK
, PPCSPE2
, 0, {RD
, RB
, UIMM
}},
10727 {"evsubifh", VX (4, 517), VX_MASK
, PPCSPE2
, 0, {RD
, UIMM
, RB
}},
10728 {"evsubifb", VX (4, 519), VX_MASK
, PPCSPE2
, 0, {RD
, UIMM
, RB
}},
10729 {"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10730 {"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10731 {"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10732 {"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10733 {"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10734 {"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10735 {"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10736 {"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10737 {"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10738 {"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10739 {"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10740 {"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10741 {"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10742 {"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10743 {"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10744 {"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10745 {"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10746 {"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10747 {"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10748 {"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10749 {"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10750 {"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10751 {"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10752 {"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10753 {"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10754 {"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10755 {"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10756 {"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10757 {"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10758 {"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10759 {"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10760 {"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10761 {"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10762 {"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10763 {"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10764 {"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10765 {"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10766 {"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10767 {"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10768 {"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10769 {"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10770 {"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10771 {"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10772 {"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10773 {"circinc", VX (4, 528), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10774 {"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10775 {"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10776 {"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10777 {"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10778 {"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10779 {"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10780 {"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10781 {"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10782 {"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10783 {"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10784 {"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10785 {"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10786 {"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10787 {"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10788 {"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10789 {"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10790 {"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10791 {"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10792 {"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10793 {"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10794 {"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10795 {"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10796 {"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10797 {"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10798 {"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10799 {"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10800 {"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10801 {"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10802 {"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10803 {"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10804 {"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10805 {"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10806 {"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10807 {"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10808 {"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10809 {"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10810 {"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10811 {"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10812 {"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10813 {"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
10814 {"evmaxmagws", VX (4, 543), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10815 {"evsl", VX (4, 549), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10816 {"evsli", VX (4, 551), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
10817 {"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10818 {"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10819 {"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10820 {"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10821 {"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10822 {"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10823 {"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10824 {"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10825 {"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10826 {"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10827 {"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10828 {"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10829 {"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10830 {"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10831 {"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10832 {"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10833 {"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10834 {"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10835 {"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10836 {"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10837 {"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10838 {"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10839 {"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10840 {"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10841 {"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10842 {"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, SIMM
}},
10843 {"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
10844 {"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
10845 {"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
10846 {"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
10847 {"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK
, PPCSPE2
, 0, {CRFD
, RA
, RB
}},
10848 {"evswapbhilo", VX (4, 568), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10849 {"evswapblohi", VX (4, 569), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10850 {"evswaphhilo", VX (4, 570), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10851 {"evswaphlohi", VX (4, 571), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10852 {"evswaphe", VX (4, 572), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10853 {"evswaphhi", VX (4, 573), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10854 {"evswaphlo", VX (4, 574), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10855 {"evswapho", VX (4, 575), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10856 {"evinsb", VX (4, 584), VX_MASK_DDD
, PPCSPE2
, 0, {RD
, RA
, DDD
, BBB
}},
10857 {"evxtrb", VX (4, 586), VX_MASK_DDD
, PPCSPE2
, 0, {RD
, RA
, DDD
, BBB
}},
10858 {"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK
, PPCSPE2
, 0, {RD
, RA
, HH
}},
10859 {"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK
, PPCSPE2
, 0, {RD
, RA
, BBB
}},
10860 {"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK
, PPCSPE2
, 0, {RD
, RA
, DD
, HH
}},
10861 {"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
10862 {"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
10863 {"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK
, PPCSPE2
, 0, {RD
, RA
, MMMM
}},
10864 {"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK
, PPCSPE2
, 0, {RD
, RA
, DD
, HH
}},
10865 {"evselbitm0", VX (4, 592), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10866 {"evselbitm1", VX (4, 593), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10867 {"evselbit", VX (4, 594), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10868 {"evperm", VX (4, 596), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10869 {"evperm2", VX (4, 597), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10870 {"evperm3", VX (4, 598), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10871 {"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
, VX_OFF_SPE2
}},
10872 {"evsrbu", VX (4, 608), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10873 {"evsrbs", VX (4, 609), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10874 {"evsrbiu", VX (4, 610), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
10875 {"evsrbis", VX (4, 611), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
10876 {"evslb", VX (4, 612), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10877 {"evrlb", VX (4, 613), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10878 {"evslbi", VX (4, 614), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
10879 {"evrlbi", VX (4, 615), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT8
}},
10880 {"evsrhu", VX (4, 616), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10881 {"evsrhs", VX (4, 617), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10882 {"evsrhiu", VX (4, 618), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
10883 {"evsrhis", VX (4, 619), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
10884 {"evslh", VX (4, 620), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10885 {"evrlh", VX (4, 621), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10886 {"evslhi", VX (4, 622), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
10887 {"evrlhi", VX (4, 623), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM_LT16
}},
10888 {"evsru", VX (4, 624), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10889 {"evsrs", VX (4, 625), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10890 {"evsriu", VX (4, 626), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
10891 {"evsris", VX (4, 627), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, EVUIMM
}},
10892 {"evlvsl", VX (4, 628), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10893 {"evlvsr", VX (4, 629), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10894 {"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
10895 {"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
10896 {"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK
, PPCSPE2
, 0, {RD
, RA
, NNN
}},
10897 {"evldbx", VX (4, 774), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10898 {"evldb", VX (4, 775), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8
, RA
}},
10899 {"evlhhsplathx", VX (4, 778), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10900 {"evlhhsplath", VX (4, 779), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2
, RA
}},
10901 {"evlwbsplatwx", VX (4, 786), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10902 {"evlwbsplatw", VX (4, 787), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
10903 {"evlwhsplatwx", VX (4, 794), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10904 {"evlwhsplatw", VX (4, 795), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
10905 {"evlbbsplatbx", VX (4, 798), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10906 {"evlbbsplatb", VX (4, 799), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_1
, RA
}},
10907 {"evstdbx", VX (4, 806), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10908 {"evstdb", VX (4, 807), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8
, RA
}},
10909 {"evlwbex", VX (4, 810), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10910 {"evlwbe", VX (4, 811), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
10911 {"evlwboux", VX (4, 812), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10912 {"evlwbou", VX (4, 813), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
10913 {"evlwbosx", VX (4, 814), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10914 {"evlwbos", VX (4, 815), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4
, RA
}},
10915 {"evstwbex", VX (4, 818), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10916 {"evstwbe", VX (4, 819), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
10917 {"evstwbox", VX (4, 822), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10918 {"evstwbo", VX (4, 823), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
10919 {"evstwbx", VX (4, 826), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10920 {"evstwb", VX (4, 827), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4
, RA
}},
10921 {"evsthbx", VX (4, 830), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10922 {"evsthb", VX (4, 831), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_2
, RA
}},
10923 {"evlddmx", VX (4, 832), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10924 {"evlddu", VX (4, 833), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
10925 {"evldwmx", VX (4, 834), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10926 {"evldwu", VX (4, 835), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
10927 {"evldhmx", VX (4, 836), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10928 {"evldhu", VX (4, 837), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
10929 {"evldbmx", VX (4, 838), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10930 {"evldbu", VX (4, 839), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_8_EX0
, RA
}},
10931 {"evlhhesplatmx", VX (4, 840), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10932 {"evlhhesplatu", VX (4, 841), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
10933 {"evlhhsplathmx", VX (4, 842), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10934 {"evlhhsplathu", VX (4, 843), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
10935 {"evlhhousplatmx", VX (4, 844), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10936 {"evlhhousplatu", VX (4, 845), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
10937 {"evlhhossplatmx", VX (4, 846), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10938 {"evlhhossplatu", VX (4, 847), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_2_EX0
, RA
}},
10939 {"evlwhemx", VX (4, 848), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10940 {"evlwheu", VX (4, 849), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10941 {"evlwbsplatwmx", VX (4, 850), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10942 {"evlwbsplatwu", VX (4, 851), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10943 {"evlwhoumx", VX (4, 852), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10944 {"evlwhouu", VX (4, 853), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10945 {"evlwhosmx", VX (4, 854), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10946 {"evlwhosu", VX (4, 855), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10947 {"evlwwsplatmx", VX (4, 856), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10948 {"evlwwsplatu", VX (4, 857), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10949 {"evlwhsplatwmx", VX (4, 858), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10950 {"evlwhsplatwu", VX (4, 859), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10951 {"evlwhsplatmx", VX (4, 860), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10952 {"evlwhsplatu", VX (4, 861), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10953 {"evlbbsplatbmx", VX (4, 862), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10954 {"evlbbsplatbu", VX (4, 863), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_1_EX0
, RA
}},
10955 {"evstddmx", VX (4, 864), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10956 {"evstddu", VX (4, 865), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
10957 {"evstdwmx", VX (4, 866), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10958 {"evstdwu", VX (4, 867), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
10959 {"evstdhmx", VX (4, 868), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10960 {"evstdhu", VX (4, 869), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
10961 {"evstdbmx", VX (4, 870), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10962 {"evstdbu", VX (4, 871), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_8_EX0
, RA
}},
10963 {"evlwbemx", VX (4, 874), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10964 {"evlwbeu", VX (4, 875), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10965 {"evlwboumx", VX (4, 876), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10966 {"evlwbouu", VX (4, 877), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10967 {"evlwbosmx", VX (4, 878), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10968 {"evlwbosu", VX (4, 879), VX_MASK
, PPCSPE2
, 0, {RD
, EVUIMM_4_EX0
, RA
}},
10969 {"evstwhemx", VX (4, 880), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10970 {"evstwheu", VX (4, 881), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
10971 {"evstwbemx", VX (4, 882), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10972 {"evstwbeu", VX (4, 883), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
10973 {"evstwhomx", VX (4, 884), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10974 {"evstwhou", VX (4, 885), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
10975 {"evstwbomx", VX (4, 886), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10976 {"evstwbou", VX (4, 887), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
10977 {"evstwwemx", VX (4, 888), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10978 {"evstwweu", VX (4, 889), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
10979 {"evstwbmx", VX (4, 890), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10980 {"evstwbu", VX (4, 891), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
10981 {"evstwwomx", VX (4, 892), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10982 {"evstwwou", VX (4, 893), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_4_EX0
, RA
}},
10983 {"evsthbmx", VX (4, 894), VX_MASK
, PPCSPE2
, 0, {RS
, RA
, RB
}},
10984 {"evsthbu", VX (4, 895), VX_MASK
, PPCSPE2
, 0, {RS
, EVUIMM_2_EX0
, RA
}},
10985 {"evmhusi", VX (4, 1024), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10986 {"evmhssi", VX (4, 1025), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10987 {"evmhsusi", VX (4, 1026), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10988 {"evmhssf", VX (4, 1028), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10989 {"evmhumi", VX (4, 1029), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10990 {"evmhssfr", VX (4, 1030), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10991 {"evmhesumi", VX (4, 1034), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10992 {"evmhosumi", VX (4, 1038), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10993 {"evmbeumi", VX (4, 1048), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10994 {"evmbesmi", VX (4, 1049), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10995 {"evmbesumi", VX (4, 1050), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10996 {"evmboumi", VX (4, 1052), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10997 {"evmbosmi", VX (4, 1053), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10998 {"evmbosumi", VX (4, 1054), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
10999 {"evmhesumia", VX (4, 1066), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11000 {"evmhosumia", VX (4, 1070), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11001 {"evmbeumia", VX (4, 1080), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11002 {"evmbesmia", VX (4, 1081), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11003 {"evmbesumia", VX (4, 1082), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11004 {"evmboumia", VX (4, 1084), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11005 {"evmbosmia", VX (4, 1085), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11006 {"evmbosumia", VX (4, 1086), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11007 {"evmwusiw", VX (4, 1088), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11008 {"evmwssiw", VX (4, 1089), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11009 {"evmwhssfr", VX (4, 1094), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11010 {"evmwehgsmfr", VX (4, 1110), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11011 {"evmwehgsmf", VX (4, 1111), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11012 {"evmwohgsmfr", VX (4, 1118), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11013 {"evmwohgsmf", VX (4, 1119), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11014 {"evmwhssfra", VX (4, 1126), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11015 {"evmwehgsmfra", VX (4, 1142), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11016 {"evmwehgsmfa", VX (4, 1143), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11017 {"evmwohgsmfra", VX (4, 1150), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11018 {"evmwohgsmfa", VX (4, 1151), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11019 {"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11020 {"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11021 {"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11022 {"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11023 {"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11024 {"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11025 {"evaddh", VX (4, 1160), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11026 {"evaddhss", VX (4, 1161), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11027 {"evsubfh", VX (4, 1162), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11028 {"evsubfhss", VX (4, 1163), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11029 {"evaddhx", VX (4, 1164), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11030 {"evaddhxss", VX (4, 1165), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11031 {"evsubfhx", VX (4, 1166), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11032 {"evsubfhxss", VX (4, 1167), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11033 {"evaddd", VX (4, 1168), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11034 {"evadddss", VX (4, 1169), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11035 {"evsubfd", VX (4, 1170), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11036 {"evsubfdss", VX (4, 1171), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11037 {"evaddb", VX (4, 1172), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11038 {"evaddbss", VX (4, 1173), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11039 {"evsubfb", VX (4, 1174), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11040 {"evsubfbss", VX (4, 1175), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11041 {"evaddsubfh", VX (4, 1176), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11042 {"evaddsubfhss", VX (4, 1177), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11043 {"evsubfaddh", VX (4, 1178), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11044 {"evsubfaddhss", VX (4, 1179), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11045 {"evaddsubfhx", VX (4, 1180), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11046 {"evaddsubfhxss", VX (4, 1181), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11047 {"evsubfaddhx", VX (4, 1182), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11048 {"evsubfaddhxss", VX (4, 1183), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11049 {"evadddus", VX (4, 1184), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11050 {"evaddbus", VX (4, 1185), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11051 {"evsubfdus", VX (4, 1186), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11052 {"evsubfbus", VX (4, 1187), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11053 {"evaddwus", VX (4, 1188), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11054 {"evaddwxus", VX (4, 1189), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11055 {"evsubfwus", VX (4, 1190), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11056 {"evsubfwxus", VX (4, 1191), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11057 {"evadd2subf2h", VX (4, 1192), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11058 {"evadd2subf2hss", VX (4, 1193), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11059 {"evsubf2add2h", VX (4, 1194), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11060 {"evsubf2add2hss", VX (4, 1195), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11061 {"evaddhus", VX (4, 1196), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11062 {"evaddhxus", VX (4, 1197), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11063 {"evsubfhus", VX (4, 1198), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11064 {"evsubfhxus", VX (4, 1199), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11065 {"evaddwss", VX (4, 1201), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11066 {"evsubfwss", VX (4, 1203), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11067 {"evaddwx", VX (4, 1204), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11068 {"evaddwxss", VX (4, 1205), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11069 {"evsubfwx", VX (4, 1206), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11070 {"evsubfwxss", VX (4, 1207), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11071 {"evaddsubfw", VX (4, 1208), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11072 {"evaddsubfwss", VX (4, 1209), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11073 {"evsubfaddw", VX (4, 1210), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11074 {"evsubfaddwss", VX (4, 1211), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11075 {"evaddsubfwx", VX (4, 1212), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11076 {"evaddsubfwxss", VX (4, 1213), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11077 {"evsubfaddwx", VX (4, 1214), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11078 {"evsubfaddwxss", VX (4, 1215), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11079 {"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK
, PPCSPE2
, 0, {RD
}},
11080 {"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11081 {"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11082 {"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11083 {"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11084 {"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11085 {"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11086 {"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11087 {"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11088 {"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11089 {"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11090 {"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11091 {"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11092 {"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11093 {"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11094 {"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11095 {"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11096 {"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11097 {"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11098 {"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11099 {"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11100 {"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11101 {"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11102 {"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11103 {"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK
, PPCSPE2
, 0, {RD
, RA
}},
11104 {"evdivwsf", VX (4, 1228), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11105 {"evdivwuf", VX (4, 1229), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11106 {"evdivs", VX (4, 1230), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11107 {"evdivu", VX (4, 1231), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11108 {"evaddwegsi", VX (4, 1232), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11109 {"evaddwegsf", VX (4, 1233), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11110 {"evsubfwegsi", VX (4, 1234), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11111 {"evsubfwegsf", VX (4, 1235), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11112 {"evaddwogsi", VX (4, 1236), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11113 {"evaddwogsf", VX (4, 1237), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11114 {"evsubfwogsi", VX (4, 1238), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11115 {"evsubfwogsf", VX (4, 1239), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11116 {"evaddhhiuw", VX (4, 1240), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11117 {"evaddhhisw", VX (4, 1241), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11118 {"evsubfhhiuw", VX (4, 1242), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11119 {"evsubfhhisw", VX (4, 1243), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11120 {"evaddhlouw", VX (4, 1244), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11121 {"evaddhlosw", VX (4, 1245), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11122 {"evsubfhlouw", VX (4, 1246), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11123 {"evsubfhlosw", VX (4, 1247), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11124 {"evmhesusiaaw", VX (4, 1282), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11125 {"evmhosusiaaw", VX (4, 1286), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11126 {"evmhesumiaaw", VX (4, 1290), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11127 {"evmhosumiaaw", VX (4, 1294), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11128 {"evmbeusiaah", VX (4, 1296), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11129 {"evmbessiaah", VX (4, 1297), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11130 {"evmbesusiaah", VX (4, 1298), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11131 {"evmbousiaah", VX (4, 1300), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11132 {"evmbossiaah", VX (4, 1301), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11133 {"evmbosusiaah", VX (4, 1302), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11134 {"evmbeumiaah", VX (4, 1304), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11135 {"evmbesmiaah", VX (4, 1305), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11136 {"evmbesumiaah", VX (4, 1306), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11137 {"evmboumiaah", VX (4, 1308), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11138 {"evmbosmiaah", VX (4, 1309), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11139 {"evmbosumiaah", VX (4, 1310), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11140 {"evmwlusiaaw3", VX (4, 1346), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11141 {"evmwlssiaaw3", VX (4, 1347), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11142 {"evmwhssfraaw3", VX (4, 1348), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11143 {"evmwhssfaaw3", VX (4, 1349), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11144 {"evmwhssfraaw", VX (4, 1350), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11145 {"evmwhssfaaw", VX (4, 1351), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11146 {"evmwlumiaaw3", VX (4, 1354), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11147 {"evmwlsmiaaw3", VX (4, 1355), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11148 {"evmwusiaa", VX (4, 1360), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11149 {"evmwssiaa", VX (4, 1361), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11150 {"evmwehgsmfraa", VX (4, 1366), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11151 {"evmwehgsmfaa", VX (4, 1367), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11152 {"evmwohgsmfraa", VX (4, 1374), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11153 {"evmwohgsmfaa", VX (4, 1375), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11154 {"evmhesusianw", VX (4, 1410), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11155 {"evmhosusianw", VX (4, 1414), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11156 {"evmhesumianw", VX (4, 1418), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11157 {"evmhosumianw", VX (4, 1422), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11158 {"evmbeusianh", VX (4, 1424), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11159 {"evmbessianh", VX (4, 1425), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11160 {"evmbesusianh", VX (4, 1426), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11161 {"evmbousianh", VX (4, 1428), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11162 {"evmbossianh", VX (4, 1429), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11163 {"evmbosusianh", VX (4, 1430), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11164 {"evmbeumianh", VX (4, 1432), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11165 {"evmbesmianh", VX (4, 1433), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11166 {"evmbesumianh", VX (4, 1434), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11167 {"evmboumianh", VX (4, 1436), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11168 {"evmbosmianh", VX (4, 1437), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11169 {"evmbosumianh", VX (4, 1438), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11170 {"evmwlusianw3", VX (4, 1474), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11171 {"evmwlssianw3", VX (4, 1475), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11172 {"evmwhssfranw3", VX (4, 1476), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11173 {"evmwhssfanw3", VX (4, 1477), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11174 {"evmwhssfranw", VX (4, 1478), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11175 {"evmwhssfanw", VX (4, 1479), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11176 {"evmwlumianw3", VX (4, 1482), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11177 {"evmwlsmianw3", VX (4, 1483), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11178 {"evmwusian", VX (4, 1488), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11179 {"evmwssian", VX (4, 1489), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11180 {"evmwehgsmfran", VX (4, 1494), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11181 {"evmwehgsmfan", VX (4, 1495), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11182 {"evmwohgsmfran", VX (4, 1502), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11183 {"evmwohgsmfan", VX (4, 1503), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11184 {"evseteqb", VX (4, 1536), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11185 {"evseteqb.", VX (4, 1537), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11186 {"evseteqh", VX (4, 1538), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11187 {"evseteqh.", VX (4, 1539), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11188 {"evseteqw", VX (4, 1540), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11189 {"evseteqw.", VX (4, 1541), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11190 {"evsetgthu", VX (4, 1544), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11191 {"evsetgthu.", VX (4, 1545), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11192 {"evsetgths", VX (4, 1546), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11193 {"evsetgths.", VX (4, 1547), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11194 {"evsetgtwu", VX (4, 1548), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11195 {"evsetgtwu.", VX (4, 1549), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11196 {"evsetgtws", VX (4, 1550), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11197 {"evsetgtws.", VX (4, 1551), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11198 {"evsetgtbu", VX (4, 1552), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11199 {"evsetgtbu.", VX (4, 1553), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11200 {"evsetgtbs", VX (4, 1554), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11201 {"evsetgtbs.", VX (4, 1555), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11202 {"evsetltbu", VX (4, 1556), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11203 {"evsetltbu.", VX (4, 1557), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11204 {"evsetltbs", VX (4, 1558), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11205 {"evsetltbs.", VX (4, 1559), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11206 {"evsetlthu", VX (4, 1560), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11207 {"evsetlthu.", VX (4, 1561), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11208 {"evsetlths", VX (4, 1562), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11209 {"evsetlths.", VX (4, 1563), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11210 {"evsetltwu", VX (4, 1564), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11211 {"evsetltwu.", VX (4, 1565), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11212 {"evsetltws", VX (4, 1566), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11213 {"evsetltws.", VX (4, 1567), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11214 {"evsaduw", VX (4, 1568), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11215 {"evsadsw", VX (4, 1569), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11216 {"evsad4ub", VX (4, 1570), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11217 {"evsad4sb", VX (4, 1571), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11218 {"evsad2uh", VX (4, 1572), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11219 {"evsad2sh", VX (4, 1573), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11220 {"evsaduwa", VX (4, 1576), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11221 {"evsadswa", VX (4, 1577), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11222 {"evsad4uba", VX (4, 1578), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11223 {"evsad4sba", VX (4, 1579), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11224 {"evsad2uha", VX (4, 1580), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11225 {"evsad2sha", VX (4, 1581), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11226 {"evabsdifuw", VX (4, 1584), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11227 {"evabsdifsw", VX (4, 1585), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11228 {"evabsdifub", VX (4, 1586), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11229 {"evabsdifsb", VX (4, 1587), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11230 {"evabsdifuh", VX (4, 1588), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11231 {"evabsdifsh", VX (4, 1589), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11232 {"evsaduwaa", VX (4, 1592), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11233 {"evsadswaa", VX (4, 1593), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11234 {"evsad4ubaaw", VX (4, 1594), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11235 {"evsad4sbaaw", VX (4, 1595), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11236 {"evsad2uhaaw", VX (4, 1596), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11237 {"evsad2shaaw", VX (4, 1597), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11238 {"evpkshubs", VX (4, 1600), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11239 {"evpkshsbs", VX (4, 1601), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11240 {"evpkswuhs", VX (4, 1602), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11241 {"evpkswshs", VX (4, 1603), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11242 {"evpkuhubs", VX (4, 1604), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11243 {"evpkuwuhs", VX (4, 1605), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11244 {"evpkswshilvs", VX (4, 1606), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11245 {"evpkswgshefrs", VX (4, 1607), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11246 {"evpkswshfrs", VX (4, 1608), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11247 {"evpkswshilvfrs", VX (4, 1609), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11248 {"evpksdswfrs", VX (4, 1610), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11249 {"evpksdshefrs", VX (4, 1611), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11250 {"evpkuduws", VX (4, 1612), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11251 {"evpksdsws", VX (4, 1613), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11252 {"evpkswgswfrs", VX (4, 1614), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11253 {"evilveh", VX (4, 1616), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11254 {"evilveoh", VX (4, 1617), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11255 {"evilvhih", VX (4, 1618), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11256 {"evilvhiloh", VX (4, 1619), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11257 {"evilvloh", VX (4, 1620), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11258 {"evilvlohih", VX (4, 1621), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11259 {"evilvoeh", VX (4, 1622), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11260 {"evilvoh", VX (4, 1623), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11261 {"evdlveb", VX (4, 1624), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11262 {"evdlveh", VX (4, 1625), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11263 {"evdlveob", VX (4, 1626), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11264 {"evdlveoh", VX (4, 1627), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11265 {"evdlvob", VX (4, 1628), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11266 {"evdlvoh", VX (4, 1629), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11267 {"evdlvoeb", VX (4, 1630), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11268 {"evdlvoeh", VX (4, 1631), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11269 {"evmaxbu", VX (4, 1632), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11270 {"evmaxbs", VX (4, 1633), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11271 {"evmaxhu", VX (4, 1634), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11272 {"evmaxhs", VX (4, 1635), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11273 {"evmaxwu", VX (4, 1636), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11274 {"evmaxws", VX (4, 1637), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11275 {"evmaxdu", VX (4, 1638), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11276 {"evmaxds", VX (4, 1639), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11277 {"evminbu", VX (4, 1640), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11278 {"evminbs", VX (4, 1641), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11279 {"evminhu", VX (4, 1642), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11280 {"evminhs", VX (4, 1643), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11281 {"evminwu", VX (4, 1644), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11282 {"evminws", VX (4, 1645), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11283 {"evmindu", VX (4, 1646), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11284 {"evminds", VX (4, 1647), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11285 {"evavgwu", VX (4, 1648), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11286 {"evavgws", VX (4, 1649), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11287 {"evavgbu", VX (4, 1650), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11288 {"evavgbs", VX (4, 1651), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11289 {"evavghu", VX (4, 1652), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11290 {"evavghs", VX (4, 1653), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11291 {"evavgdu", VX (4, 1654), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11292 {"evavgds", VX (4, 1655), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11293 {"evavgwur", VX (4, 1656), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11294 {"evavgwsr", VX (4, 1657), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11295 {"evavgbur", VX (4, 1658), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11296 {"evavgbsr", VX (4, 1659), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11297 {"evavghur", VX (4, 1660), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11298 {"evavghsr", VX (4, 1661), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11299 {"evavgdur", VX (4, 1662), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11300 {"evavgdsr", VX (4, 1663), VX_MASK
, PPCSPE2
, 0, {RD
, RA
, RB
}},
11303 const unsigned int spe2_num_opcodes
=
11304 sizeof (spe2_opcodes
) / sizeof (spe2_opcodes
[0]);