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PowerPC opcode table and disassembler.
[binutils-gdb.git] / opcodes / ppc-opc.c
1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 2, or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20
21 #include <stdio.h>
22 #include "ansidecl.h"
23 #include "opcode/ppc.h"
24
25 /* This file holds the PowerPC opcode table. The opcode table
26 includes almost all of the extended instruction mnemonics. This
27 permits the disassembler to use them, and simplifies the assembler
28 logic, at the cost of increasing the table size. The table is
29 strictly constant data, so the compiler should be able to put it in
30 the .text section.
31
32 This file also holds the operand table. All knowledge about
33 inserting operands into instructions and vice-versa is kept in this
34 file. */
35 \f
36 /* Local insertion and extraction functions. */
37
38 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
39 static long extract_bat PARAMS ((unsigned long, int *));
40 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
41 static long extract_bba PARAMS ((unsigned long, int *));
42 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
43 static long extract_bd PARAMS ((unsigned long, int *));
44 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
45 static long extract_bdm PARAMS ((unsigned long, int *));
46 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
47 static long extract_bdp PARAMS ((unsigned long, int *));
48 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
49 static long extract_bo PARAMS ((unsigned long, int *));
50 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
51 static long extract_boe PARAMS ((unsigned long, int *));
52 static unsigned long insert_cr PARAMS ((unsigned long, long, const char **));
53 static long extract_cr PARAMS ((unsigned long, int *));
54 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
55 static long extract_ds PARAMS ((unsigned long, int *));
56 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
57 static long extract_li PARAMS ((unsigned long, int *));
58 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
59 static long extract_mb6 PARAMS ((unsigned long, int *));
60 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
61 static long extract_nsi PARAMS ((unsigned long, int *));
62 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
63 static long extract_rbs PARAMS ((unsigned long, int *));
64 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
65 static long extract_sh6 PARAMS ((unsigned long, int *));
66 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
67 static long extract_spr PARAMS ((unsigned long, int *));
68 \f
69 /* The operands table.
70
71 The fields are bits, shift, signed, insert, extract, flags. */
72
73 const struct powerpc_operand powerpc_operands[] =
74 {
75 /* The zero index is used to indicate the end of the list of
76 operands. */
77 #define UNUSED (0)
78 { 0, 0, 0, 0, 0, 0 },
79
80 /* The BA field in an XL form instruction. */
81 #define BA (UNUSED + 1)
82 #define BA_MASK (0x1f << 16)
83 { 5, 16, 0, 0, 0, PPC_OPERAND_CR },
84
85 /* The BA field in an XL form instruction when it must be the same
86 as the BT field in the same instruction. */
87 #define BAT (BA + 1)
88 { 5, 16, 0, insert_bat, extract_bat, PPC_OPERAND_FAKE },
89
90 /* The BB field in an XL form instruction. */
91 #define BB (BAT + 1)
92 #define BB_MASK (0x1f << 11)
93 { 5, 11, 0, 0, 0, PPC_OPERAND_CR },
94
95 /* The BB field in an XL form instruction when it must be the same
96 as the BA field in the same instruction. */
97 #define BBA (BB + 1)
98 { 5, 11, 0, insert_bba, extract_bba, PPC_OPERAND_FAKE },
99
100 /* The BD field in a B form instruction. The lower two bits are
101 forced to zero. */
102 #define BD (BBA + 1)
103 { 16, 0, 1, insert_bd, extract_bd, PPC_OPERAND_RELATIVE },
104
105 /* The BD field in a B form instruction when absolute addressing is
106 used. */
107 #define BDA (BD + 1)
108 { 16, 0, 1, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE },
109
110 /* The BD field in a B form instruction when the - modifier is used.
111 This sets the y bit of the BO field appropriately. */
112 #define BDM (BDA + 1)
113 { 16, 0, 1, insert_bdm, extract_bdm, PPC_OPERAND_RELATIVE },
114
115 /* The BD field in a B form instruction when the - modifier is used
116 and absolute address is used. */
117 #define BDMA (BDM + 1)
118 { 16, 0, 1, insert_bdm, extract_bdm, PPC_OPERAND_ABSOLUTE },
119
120 /* The BD field in a B form instruction when the + modifier is used.
121 This sets the y bit of the BO field appropriately. */
122 #define BDP (BDMA + 1)
123 { 16, 0, 1, insert_bdp, extract_bdp, PPC_OPERAND_RELATIVE },
124
125 /* The BD field in a B form instruction when the + modifier is used
126 and absolute addressing is used. */
127 #define BDPA (BDP + 1)
128 { 16, 0, 1, insert_bdp, extract_bdp, PPC_OPERAND_ABSOLUTE },
129
130 /* The BF field in an X or XL form instruction. */
131 #define BF (BDPA + 1)
132 { 3, 23, 0, 0, 0, PPC_OPERAND_CR },
133
134 /* An optional BF field. This is used for comparison instructions,
135 in which an omitted BF field is taken as zero. */
136 #define OBF (BF + 1)
137 { 3, 23, 0, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
138
139 /* The BFA field in an X or XL form instruction. */
140 #define BFA (OBF + 1)
141 { 3, 18, 0, 0, 0, PPC_OPERAND_CR },
142
143 /* The BI field in a B form or XL form instruction. */
144 #define BI (BFA + 1)
145 #define BI_MASK (0x1f << 16)
146 { 5, 16, 0, 0, 0, PPC_OPERAND_CR },
147
148 /* The BO field in a B form instruction. Certain values are
149 illegal. */
150 #define BO (BI + 1)
151 #define BO_MASK (0x1f << 21)
152 { 5, 21, 0, insert_bo, extract_bo, 0 },
153
154 /* The BO field in a B form instruction when the + or - modifier is
155 used. This is like the BO field, but it must be even. */
156 #define BOE (BO + 1)
157 { 5, 21, 0, insert_boe, extract_boe, 0 },
158
159 /* The BT field in an X or XL form instruction. */
160 #define BT (BOE + 1)
161 { 5, 21, 0, 0, 0, PPC_OPERAND_CR },
162
163 /* The condition register number portion of the BI field in a B form
164 or XL form instruction. This is used for the extended
165 conditional branch mnemonics, which set the lower two bits of the
166 BI field. This field is optional. */
167 #define CR (BT + 1)
168 { 5, 16, 0, insert_cr, extract_cr, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
169
170 /* The D field in a D form instruction. This is a displacement off
171 a register, and implies that the next operand is a register in
172 parentheses. */
173 #define D (CR + 1)
174 { 16, 0, 1, 0, 0, PPC_OPERAND_PARENS },
175
176 /* The DS field in a DS form instruction. This is like D, but the
177 lower two bits are forced to zero. */
178 #define DS (D + 1)
179 { 16, 0, 1, insert_ds, extract_ds, PPC_OPERAND_PARENS },
180
181 /* The FL1 field in a POWER SC form instruction. */
182 #define FL1 (DS + 1)
183 { 4, 12, 0, 0, 0, 0 },
184
185 /* The FL2 field in a POWER SC form instruction. */
186 #define FL2 (FL1 + 1)
187 { 3, 2, 0, 0, 0, 0 },
188
189 /* The FLM field in an XFL form instruction. */
190 #define FLM (FL2 + 1)
191 { 8, 17, 0, 0, 0, 0 },
192
193 /* The FRA field in an X or A form instruction. */
194 #define FRA (FLM + 1)
195 #define FRA_MASK (0x1f << 16)
196 { 5, 16, 0, 0, 0, PPC_OPERAND_FPR },
197
198 /* The FRB field in an X or A form instruction. */
199 #define FRB (FRA + 1)
200 #define FRB_MASK (0x1f << 11)
201 { 5, 11, 0, 0, 0, PPC_OPERAND_FPR },
202
203 /* The FRC field in an A form instruction. */
204 #define FRC (FRB + 1)
205 #define FRC_MASK (0x1f << 6)
206 { 5, 6, 0, 0, 0, PPC_OPERAND_FPR },
207
208 /* The FRS field in an X form instruction or the FRT field in a D, X
209 or A form instruction. */
210 #define FRS (FRC + 1)
211 #define FRT (FRS)
212 { 5, 21, 0, 0, 0, PPC_OPERAND_FPR },
213
214 /* The FXM field in an XFX instruction. */
215 #define FXM (FRS + 1)
216 { 8, 12, 0, 0, 0, 0 },
217
218 /* The L field in a D or X form instruction. */
219 #define L (FXM + 1)
220 { 1, 21, 0, 0, 0, PPC_OPERAND_OPTIONAL },
221
222 /* The LEV field in a POWER SC form instruction. */
223 #define LEV (L + 1)
224 { 7, 5, 0, 0, 0, 0 },
225
226 /* The LI field in an I form instruction. The lower two bits are
227 forced to zero. */
228 #define LI (LEV + 1)
229 { 25, 0, 1, insert_li, extract_li, PPC_OPERAND_RELATIVE },
230
231 /* The LI field in an I form instruction when used as an absolute
232 address. */
233 #define LIA (LI + 1)
234 { 25, 0, 1, insert_li, extract_li, PPC_OPERAND_ABSOLUTE },
235
236 /* The MB field in an M form instruction. */
237 #define MB (LIA + 1)
238 #define MB_MASK (0x1f << 6)
239 { 5, 6, 0, 0, 0, 0 },
240
241 /* The ME field in an M form instruction. */
242 #define ME (MB + 1)
243 #define ME_MASK (0x1f << 1)
244 { 5, 1, 0, 0, 0, 0 },
245
246 /* The MB or ME field in an MD or MDS form instruction. The high
247 bit is wrapped to the low end. */
248 #define MB6 (ME + 1)
249 #define ME6 (MB6)
250 #define MB6_MASK (0x3f << 5)
251 { 6, 5, 0, insert_mb6, extract_mb6, 0 },
252
253 /* The NB field in an X form instruction or the SH field in an X or
254 M form instruction. */
255 #define NB (MB6 + 1)
256 #define SH (NB)
257 #define SH_MASK (0x1f << 11)
258 { 5, 11, 0, 0, 0, 0 },
259
260 /* The NSI field in a D form instruction. This is the same as the
261 SI field, only negated. */
262 #define NSI (NB + 1)
263 { 16, 0, 1, insert_nsi, extract_nsi, PPC_OPERAND_NEGATIVE },
264
265 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
266 #define RA (NSI + 1)
267 #define RA_MASK (0x1f << 16)
268 { 5, 16, 0, 0, 0, PPC_OPERAND_GPR },
269
270 /* The RB field in an X, XO, M, or MDS form instruction. */
271 #define RB (RA + 1)
272 #define RB_MASK (0x1f << 11)
273 { 5, 11, 0, 0, 0, PPC_OPERAND_GPR },
274
275 /* The RB field in an X form instruction when it must be the same as
276 the RS field in the instruction. This is used for extended
277 mnemonics like mr. */
278 #define RBS (RB + 1)
279 { 5, 1, 0, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
280
281 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
282 instruction or the RT field in a D, DS, X, XFX or XO form
283 instruction. */
284 #define RS (RBS + 1)
285 #define RT (RS)
286 #define RT_MASK (0x1f << 21)
287 { 5, 21, 0, 0, 0, PPC_OPERAND_GPR },
288
289 /* The SH field in an MD form instruction. This is split. */
290 #define SH6 (RS + 1)
291 #define SH6_MASK ((0x1f << 11) | (1 << 1))
292 { 6, 1, 0, insert_sh6, extract_sh6, 0 },
293
294 /* The SI field in a D form instruction. */
295 #define SI (SH6 + 1)
296 { 16, 0, 1, 0, 0, 0 },
297
298 /* The SPR or TBR field in an XFX form instruction. This is
299 flipped--the lower 5 bits are stored in the upper 5 and vice-
300 versa. */
301 #define SPR (SI + 1)
302 #define TBR (SPR)
303 #define SPR_MASK (0x3ff << 11)
304 { 10, 11, 0, insert_spr, extract_spr, 0 },
305
306 /* The SR field in an X form instruction. */
307 #define SR (SPR + 1)
308 { 4, 16, 0, 0, 0, 0 },
309
310 /* The SV field in a POWER SC form instruction. */
311 #define SV (SR + 1)
312 { 14, 2, 0, 0, 0, 0 },
313
314 /* The TO field in a D or X form instruction. */
315 #define TO (SV + 1)
316 #define TO_MASK (0x1f << 21)
317 { 5, 21, 0, 0, 0, 0 },
318
319 /* The U field in an X form instruction. */
320 #define U (TO + 1)
321 { 4, 12, 0, 0, 0, 0 },
322
323 /* The UI field in a D form instruction. */
324 #define UI (U + 1)
325 { 16, 0, 0, 0, 0, 0 },
326 };
327
328 /* The functions used to insert and extract complicated operands. */
329
330 /* The BA field in an XL form instruction when it must be the same as
331 the BT field in the same instruction. This operand is marked FAKE.
332 The insertion function just copies the BT field into the BA field,
333 and the extraction function just checks that the fields are the
334 same. */
335
336 /*ARGSUSED*/
337 static unsigned long
338 insert_bat (insn, value, errmsg)
339 unsigned long insn;
340 long value;
341 const char **errmsg;
342 {
343 return insn | (((insn >> 21) & 0x1f) << 16);
344 }
345
346 static long
347 extract_bat (insn, invalid)
348 unsigned long insn;
349 int *invalid;
350 {
351 if (invalid != (int *) NULL
352 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
353 *invalid = 1;
354 return 0;
355 }
356
357 /* The BB field in an XL form instruction when it must be the same as
358 the BA field in the same instruction. This operand is marked FAKE.
359 The insertion function just copies the BA field into the BB field,
360 and the extraction function just checks that the fields are the
361 same. */
362
363 /*ARGSUSED*/
364 static unsigned long
365 insert_bba (insn, value, errmsg)
366 unsigned long insn;
367 long value;
368 const char **errmsg;
369 {
370 return insn | (((insn >> 16) & 0x1f) << 11);
371 }
372
373 static long
374 extract_bba (insn, invalid)
375 unsigned long insn;
376 int *invalid;
377 {
378 if (invalid != (int *) NULL
379 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
380 *invalid = 1;
381 return 0;
382 }
383
384 /* The BD field in a B form instruction. The lower two bits are
385 forced to zero. */
386
387 /*ARGSUSED*/
388 static unsigned long
389 insert_bd (insn, value, errmsg)
390 unsigned long insn;
391 long value;
392 const char **errmsg;
393 {
394 return insn | (value & 0xfffc);
395 }
396
397 /*ARGSUSED*/
398 static long
399 extract_bd (insn, invalid)
400 unsigned long insn;
401 int *invalid;
402 {
403 if ((insn & 0x8000) != 0)
404 return (insn & 0xfffc) - 0x10000;
405 else
406 return insn & 0xfffc;
407 }
408
409 /* The BD field in a B form instruction when the - modifier is used.
410 This modifier means that the branch is not expected to be taken.
411 We must set the y bit of the BO field to 1 if the offset is
412 negative. When extracting, we require that the y bit be 1 and that
413 the offset be positive, since if the y bit is 0 we just want to
414 print the normal form of the instruction. */
415
416 /*ARGSUSED*/
417 static unsigned long
418 insert_bdm (insn, value, errmsg)
419 unsigned long insn;
420 long value;
421 const char **errmsg;
422 {
423 if ((value & 0x8000) != 0)
424 insn |= 1 << 21;
425 return insn | (value & 0xfffc);
426 }
427
428 static long
429 extract_bdm (insn, invalid)
430 unsigned long insn;
431 int *invalid;
432 {
433 if (invalid != (int *) NULL
434 && ((insn & (1 << 21)) == 0
435 || (insn & (1 << 15) == 0)))
436 *invalid = 1;
437 if ((insn & 0x8000) != 0)
438 return (insn & 0xfffc) - 0x10000;
439 else
440 return insn & 0xfffc;
441 }
442
443 /* The BD field in a B form instruction when the + modifier is used.
444 This is like BDM, above, except that the branch is expected to be
445 taken. */
446
447 /*ARGSUSED*/
448 static unsigned long
449 insert_bdp (insn, value, errmsg)
450 unsigned long insn;
451 long value;
452 const char **errmsg;
453 {
454 if ((value & 0x8000) == 0)
455 insn |= 1 << 21;
456 return insn | (value & 0xfffc);
457 }
458
459 static long
460 extract_bdp (insn, invalid)
461 unsigned long insn;
462 int *invalid;
463 {
464 if (invalid != (int *) NULL
465 && ((insn & (1 << 21)) == 0
466 || (insn & (1 << 15)) != 0))
467 *invalid = 1;
468 if ((insn & 0x8000) != 0)
469 return (insn & 0xfffc) - 0x10000;
470 else
471 return insn & 0xfffc;
472 }
473
474 /* Check for legal values of a BO field. */
475
476 static int
477 valid_bo (value)
478 long value;
479 {
480 /* Certain encodings have bits that are required to be zero. These
481 are (z must be zero, y may be anything):
482 001zy
483 011zy
484 1z00y
485 1z01y
486 1z1zz
487 */
488 switch (value & 0x14)
489 {
490 default:
491 case 0:
492 return 1;
493 case 0x4:
494 return (value & 0x2) == 0;
495 case 0x10:
496 return (value & 0x8) == 0;
497 case 0x14:
498 return value == 0x14;
499 }
500 }
501
502 /* The BO field in a B form instruction. Warn about attempts to set
503 the field to an illegal value. */
504
505 static unsigned long
506 insert_bo (insn, value, errmsg)
507 unsigned long insn;
508 long value;
509 const char **errmsg;
510 {
511 if (errmsg != (const char **) NULL
512 && ! valid_bo (value))
513 *errmsg = "invalid conditional option";
514 return insn | ((value & 0x1f) << 21);
515 }
516
517 static long
518 extract_bo (insn, invalid)
519 unsigned long insn;
520 int *invalid;
521 {
522 long value;
523
524 value = (insn >> 21) & 0x1f;
525 if (invalid != (int *) NULL
526 && ! valid_bo (value))
527 *invalid = 1;
528 return value;
529 }
530
531 /* The BO field in a B form instruction when the + or - modifier is
532 used. This is like the BO field, but it must be even. When
533 extracting it, we force it to be even. */
534
535 static unsigned long
536 insert_boe (insn, value, errmsg)
537 unsigned long insn;
538 long value;
539 const char **errmsg;
540 {
541 if (errmsg != (const char **) NULL)
542 {
543 if (! valid_bo (value))
544 *errmsg = "invalid conditional option";
545 else if ((value & 1) != 0)
546 *errmsg = "attempt to set y bit when using + or - modifier";
547 }
548 return insn | ((value & 0x1f) << 21);
549 }
550
551 static long
552 extract_boe (insn, invalid)
553 unsigned long insn;
554 int *invalid;
555 {
556 long value;
557
558 value = (insn >> 21) & 0x1f;
559 if (invalid != (int *) NULL
560 && ! valid_bo (value))
561 *invalid = 1;
562 return value & 0x1e;
563 }
564
565 /* The condition register number portion of the BI field in a B form
566 or XL form instruction. This is used for the extended conditional
567 branch mnemonics, which set the lower two bits of the BI field. It
568 is the BI field with the lower two bits ignored. */
569
570 /*ARGSUSED*/
571 static unsigned long
572 insert_cr (insn, value, errmsg)
573 unsigned long insn;
574 long value;
575 const char **errmsg;
576 {
577 return insn | ((value & 0x1c) << 16);
578 }
579
580 /*ARGSUSED*/
581 static long
582 extract_cr (insn, invalid)
583 unsigned long insn;
584 int *invalid;
585 {
586 return (insn >> 16) & 0x1c;
587 }
588
589 /* The DS field in a DS form instruction. This is like D, but the
590 lower two bits are forced to zero. */
591
592 /*ARGSUSED*/
593 static unsigned long
594 insert_ds (insn, value, errmsg)
595 unsigned long insn;
596 long value;
597 const char **errmsg;
598 {
599 return insn | (value & 0xfffc);
600 }
601
602 /*ARGSUSED*/
603 static long
604 extract_ds (insn, invalid)
605 unsigned long insn;
606 int *invalid;
607 {
608 if ((insn & 0x8000) != 0)
609 return (insn & 0xfffc) - 0x10000;
610 else
611 return insn & 0xfffc;
612 }
613
614 /* The LI field in an I form instruction. The lower two bits are
615 forced to zero. */
616
617 /*ARGSUSED*/
618 static unsigned long
619 insert_li (insn, value, errmsg)
620 unsigned long insn;
621 long value;
622 const char **errmsg;
623 {
624 return insn | (value & 0x3fffffc);
625 }
626
627 /*ARGSUSED*/
628 static long
629 extract_li (insn, invalid)
630 unsigned long insn;
631 int *invalid;
632 {
633 if ((insn & 0x2000000) != 0)
634 return (insn & 0x3fffffc) - 0x4000000;
635 else
636 return insn & 0x3fffffc;
637 }
638
639 /* The MB or ME field in an MD or MDS form instruction. The high bit
640 is wrapped to the low end. */
641
642 /*ARGSUSED*/
643 static unsigned long
644 insert_mb6 (insn, value, errmsg)
645 unsigned long insn;
646 long value;
647 const char **errmsg;
648 {
649 return insn | ((value & 0x1f) << 6) | (value & 0x20);
650 }
651
652 /*ARGSUSED*/
653 static long
654 extract_mb6 (insn, invalid)
655 unsigned long insn;
656 int *invalid;
657 {
658 return ((insn >> 6) & 0x1f) | (insn & 0x20);
659 }
660
661 /* The NSI field in a D form instruction. This is the same as the SI
662 field, only negated. The extraction function always mark it as
663 invalid, since we never want to recognize an instruction which uses
664 a field of this type. */
665
666 /*ARGSUSED*/
667 static unsigned long
668 insert_nsi (insn, value, errmsg)
669 unsigned long insn;
670 long value;
671 const char **errmsg;
672 {
673 return insn | ((- value) & 0xffff);
674 }
675
676 static long
677 extract_nsi (insn, invalid)
678 unsigned long insn;
679 int *invalid;
680 {
681 if (invalid != (int *) NULL)
682 *invalid = 1;
683 if ((insn & 0x8000) != 0)
684 return - ((insn & 0xffff) - 0x10000);
685 else
686 return - (insn & 0xffff);
687 }
688
689 /* The RB field in an X form instruction when it must be the same as
690 the RS field in the instruction. This is used for extended
691 mnemonics like mr. This operand is marked FAKE. The insertion
692 function just copies the BT field into the BA field, and the
693 extraction function just checks that the fields are the same. */
694
695 /*ARGSUSED*/
696 static unsigned long
697 insert_rbs (insn, value, errmsg)
698 unsigned long insn;
699 long value;
700 const char **errmsg;
701 {
702 return insn | (((insn >> 21) & 0x1f) << 11);
703 }
704
705 static long
706 extract_rbs (insn, invalid)
707 unsigned long insn;
708 int *invalid;
709 {
710 if (invalid != (int *) NULL
711 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
712 *invalid = 1;
713 return 0;
714 }
715
716 /* The SH field in an MD form instruction. This is split. */
717
718 /*ARGSUSED*/
719 static unsigned long
720 insert_sh6 (insn, value, errmsg)
721 unsigned long insn;
722 long value;
723 const char **errmsg;
724 {
725 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
726 }
727
728 /*ARGSUSED*/
729 static long
730 extract_sh6 (insn, invalid)
731 unsigned long insn;
732 int *invalid;
733 {
734 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
735 }
736
737 /* The SPR or TBR field in an XFX form instruction. This is
738 flipped--the lower 5 bits are stored in the upper 5 and vice-
739 versa. */
740
741 static unsigned long
742 insert_spr (insn, value, errmsg)
743 unsigned long insn;
744 long value;
745 const char **errmsg;
746 {
747 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
748 }
749
750 static long
751 extract_spr (insn, invalid)
752 unsigned long insn;
753 int *invalid;
754 {
755 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
756 }
757 \f
758 /* Macros used to form opcodes. */
759
760 /* The main opcode. */
761 #define OP(x) (((x) & 0x3f) << 26)
762 #define OP_MASK OP (0x3f)
763
764 /* The main opcode combined with a trap code in the TO field of a D
765 form instruction. Used for extended mnemonics for the trap
766 instructions. */
767 #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
768 #define OPTO_MASK (OP_MASK | TO_MASK)
769
770 /* The main opcode combined with a comparison size bit in the L field
771 of a D form or X form instruction. Used for extended mnemonics for
772 the comparison instructions. */
773 #define OPL(x,l) (OP (x) | (((l) & 1) << 21))
774 #define OPL_MASK OPL (0x3f,1)
775
776 /* An A form instruction. */
777 #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
778 #define A_MASK A (0x3f, 0x1f, 1)
779
780 /* An A_MASK with the FRB field fixed. */
781 #define AFRB_MASK (A_MASK | FRB_MASK)
782
783 /* An A_MASK with the FRC field fixed. */
784 #define AFRC_MASK (A_MASK | FRC_MASK)
785
786 /* An A_MASK with the FRA and FRC fields fixed. */
787 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
788
789 /* A B form instruction. */
790 #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
791 #define B_MASK B (0x3f, 1, 1)
792
793 /* A B form instruction setting the BO field. */
794 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
795 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
796
797 /* A BBO_MASK with the y bit of the BO field removed. This permits
798 matching a conditional branch regardless of the setting of the y
799 bit. */
800 #define Y_MASK (1 << 21)
801 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
802
803 /* A B form instruction setting the BO field and the condition bits of
804 the BI field. */
805 #define BBOCB(op, bo, cb, aa, lk) \
806 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
807 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
808
809 /* A BBOCB_MASK with the y bit of the BO field removed. */
810 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
811
812 /* A BBOYCB_MASK in which the BI field is fixed. */
813 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
814
815 /* The main opcode mask with the RA field clear. */
816 #define DRA_MASK (OP_MASK | RA_MASK)
817
818 /* A DS form instruction. */
819 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
820 #define DS_MASK DSO (0x3f, 3)
821
822 /* An M form instruction. */
823 #define M(op, rc) (OP (op) | ((rc) & 1))
824 #define M_MASK M (0x3f, 1)
825
826 /* An M form instruction with the ME field specified. */
827 #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
828
829 /* An M_MASK with the MB and ME fields fixed. */
830 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
831
832 /* An M_MASK with the SH and ME fields fixed. */
833 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
834
835 /* An MD form instruction. */
836 #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
837 #define MD_MASK MD (0x3f, 0x7, 1)
838
839 /* An MD_MASK with the MB field fixed. */
840 #define MDMB_MASK (MD_MASK | MB6_MASK)
841
842 /* An MD_MASK with the SH field fixed. */
843 #define MDSH_MASK (MD_MASK | SH6_MASK)
844
845 /* An MDS form instruction. */
846 #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
847 #define MDS_MASK MDS (0x3f, 0xf, 1)
848
849 /* An MDS_MASK with the MB field fixed. */
850 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
851
852 /* An SC form instruction. */
853 #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
854 #define SC_MASK (OP_MASK | (0x3ff << 16))
855
856 /* An X form instruction. */
857 #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
858
859 /* An X form instruction with the RC bit specified. */
860 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
861
862 /* The mask for an X form instruction. */
863 #define X_MASK XRC (0x3f, 0x3ff, 1)
864
865 /* An X_MASK with the RA field fixed. */
866 #define XRA_MASK (X_MASK | RA_MASK)
867
868 /* An X_MASK with the RB field fixed. */
869 #define XRB_MASK (X_MASK | RB_MASK)
870
871 /* An X_MASK with the RT field fixed. */
872 #define XRT_MASK (X_MASK | RT_MASK)
873
874 /* An X_MASK with the RA and RB fields fixed. */
875 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
876
877 /* An X_MASK with the RT and RA fields fixed. */
878 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
879
880 /* An X form comparison instruction. */
881 #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
882
883 /* The mask for an X form comparison instruction. */
884 #define XCMP_MASK (X_MASK | (1 << 22))
885
886 /* The mask for an X form comparison instruction with the L field
887 fixed. */
888 #define XCMPL_MASK (XCMP_MASK | (1 << 21))
889
890 /* An X form trap instruction with the TO field specified. */
891 #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
892 #define XTO_MASK (X_MASK | TO_MASK)
893
894 /* An XFL form instruction. */
895 #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
896 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
897
898 /* An XL form instruction with the LK field set to 0. */
899 #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
900
901 /* An XL form instruction which uses the LK field. */
902 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
903
904 /* The mask for an XL form instruction. */
905 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
906
907 /* An XL form instruction which explicitly sets the BO field. */
908 #define XLO(op, bo, xop, lk) \
909 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
910 #define XLO_MASK (XL_MASK | BO_MASK)
911
912 /* An XL form instruction which explicitly sets the y bit of the BO
913 field. */
914 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
915 #define XLYLK_MASK (XL_MASK | Y_MASK)
916
917 /* An XL form instruction which sets the BO field and the condition
918 bits of the BI field. */
919 #define XLOCB(op, bo, cb, xop, lk) \
920 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
921 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
922
923 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
924 #define XLBB_MASK (XL_MASK | BB_MASK)
925 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
926 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
927
928 /* An XL_MASK with the BO and BB fields fixed. */
929 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
930
931 /* An XL_MASK with the BO, BI and BB fields fixed. */
932 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
933
934 /* An XO form instruction. */
935 #define XO(op, xop, oe, rc) \
936 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
937 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
938
939 /* An XO_MASK with the RB field fixed. */
940 #define XORB_MASK (XO_MASK | RB_MASK)
941
942 /* An XS form instruction. */
943 #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
944 #define XS_MASK XS (0x3f, 0x1ff, 1)
945
946 /* An XFX form instruction with the SPR field filled in. */
947 #define XSPR(op, xop, spr) \
948 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
949 #define XSPR_MASK (X_MASK | SPR_MASK)
950
951 /* The BO encodings used in extended conditional branch mnemonics. */
952 #define BODNZF (0x0)
953 #define BODNZFP (0x1)
954 #define BODZF (0x2)
955 #define BODZFP (0x3)
956 #define BOF (0x4)
957 #define BOFP (0x5)
958 #define BODNZT (0x8)
959 #define BODNZTP (0x9)
960 #define BODZT (0xa)
961 #define BODZTP (0xb)
962 #define BOT (0xc)
963 #define BOTP (0xd)
964 #define BODNZ (0x10)
965 #define BODNZP (0x11)
966 #define BODZ (0x12)
967 #define BODZP (0x13)
968 #define BOU (0x14)
969
970 /* The BI condition bit encodings used in extended conditional branch
971 mnemonics. */
972 #define CBLT (0)
973 #define CBGT (1)
974 #define CBEQ (2)
975 #define CBSO (3)
976
977 /* The TO encodings used in extended trap mnemonics. */
978 #define TOLGT (0x1)
979 #define TOLLT (0x2)
980 #define TOEQ (0x4)
981 #define TOLGE (0x5)
982 #define TOLNL (0x5)
983 #define TOLLE (0x6)
984 #define TOLNG (0x6)
985 #define TOGT (0x8)
986 #define TOGE (0xc)
987 #define TONL (0xc)
988 #define TOLT (0x10)
989 #define TOLE (0x14)
990 #define TONG (0x14)
991 #define TONE (0x18)
992 #define TOU (0x1f)
993 \f
994 /* Smaller names for the flags so each entry in the opcodes table will
995 fit on a single line. */
996 #define PPC PPC_OPCODE_PPC
997 #define POWER PPC_OPCODE_POWER
998 #define B32 PPC_OPCODE_32
999 #define B64 PPC_OPCODE_64
1000 \f
1001 /* The opcode table.
1002
1003 The format of the opcode table is:
1004
1005 NAME OPCODE MASK FLAGS { OPERANDS }
1006
1007 NAME is the name of the instruction.
1008 OPCODE is the instruction opcode.
1009 MASK is the opcode mask; this is used to tell the disassembler
1010 which bits in the actual opcode must match OPCODE.
1011 FLAGS are flags indicated what processors support the instruction.
1012 OPERANDS is the list of operands.
1013
1014 The disassembler reads the table in order and prints the first
1015 instruction which matches, so this table is sorted to put more
1016 specific instructions before more general instructions. It is also
1017 sorted by major opcode. */
1018
1019 const struct powerpc_opcode powerpc_opcodes[] = {
1020 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } },
1021 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } },
1022 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } },
1023 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } },
1024 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } },
1025 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } },
1026 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } },
1027 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } },
1028 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } },
1029 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } },
1030 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } },
1031 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } },
1032 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } },
1033 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } },
1034 { "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } },
1035
1036 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } },
1037 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } },
1038 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } },
1039 { "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } },
1040 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } },
1041 { "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } },
1042 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } },
1043 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } },
1044 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } },
1045 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } },
1046 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } },
1047 { "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } },
1048 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } },
1049 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } },
1050 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } },
1051 { "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } },
1052 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } },
1053 { "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } },
1054 { "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } },
1055 { "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } },
1056 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } },
1057 { "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } },
1058 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } },
1059 { "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } },
1060 { "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } },
1061 { "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } },
1062 { "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } },
1063 { "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } },
1064 { "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } },
1065 { "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } },
1066
1067 { "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } },
1068 { "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } },
1069
1070 { "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } },
1071 { "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } },
1072
1073 { "dozi", OP(9), OP_MASK, POWER, { RT, RA, SI } },
1074
1075 { "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } },
1076 { "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } },
1077 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
1078 { "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } },
1079
1080 { "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } },
1081 { "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } },
1082 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
1083 { "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } },
1084
1085 { "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } },
1086 { "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } },
1087 { "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } },
1088
1089 { "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } },
1090 { "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } },
1091 { "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } },
1092
1093 { "li", OP(14), DRA_MASK, PPC, { RT, SI } },
1094 { "lil", OP(14), DRA_MASK, POWER, { RT, SI } },
1095 { "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } },
1096 { "cal", OP(14), OP_MASK, POWER, { RT, RA, SI } },
1097 { "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } },
1098 { "la", OP(14), OP_MASK, PPC, { RT, D, RA } },
1099
1100 { "lis", OP(15), DRA_MASK, PPC, { RT, SI } },
1101 { "liu", OP(15), DRA_MASK, POWER, { RT, SI } },
1102 { "addis", OP(15), OP_MASK, PPC, { RT, RA, SI } },
1103 { "cau", OP(15), OP_MASK, POWER, { RT, RA, SI } },
1104 { "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } },
1105
1106 { "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1107 { "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1108 { "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
1109 { "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1110 { "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1111 { "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } },
1112 { "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1113 { "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1114 { "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } },
1115 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1116 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1117 { "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } },
1118 { "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1119 { "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1120 { "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
1121 { "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1122 { "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1123 { "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } },
1124 { "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1125 { "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1126 { "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } },
1127 { "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1128 { "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1129 { "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } },
1130 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1131 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1132 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1133 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1134 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1135 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1136 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1137 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1138 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1139 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1140 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1141 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1142 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1143 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1144 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1145 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1146 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1147 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1148 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1149 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1150 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1151 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1152 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1153 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1154 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1155 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1156 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1157 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1158 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1159 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1160 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1161 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1162 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1163 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1164 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1165 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1166 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1167 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1168 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1169 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1170 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1171 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1172 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1173 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1174 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1175 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1176 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1177 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1178 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1179 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1180 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1181 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1182 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1183 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1184 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1185 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1186 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1187 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1188 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1189 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1190 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1191 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1192 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1193 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1194 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1195 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1196 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1197 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1198 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1199 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1200 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1201 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1202 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1203 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1204 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1205 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1206 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1207 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1208 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1209 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1210 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1211 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1212 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1213 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1214 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1215 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1216 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1217 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1218 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1219 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1220 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1221 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1222 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1223 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1224 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1225 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1226 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1227 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1228 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1229 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1230 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1231 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1232 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1233 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1234 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1235 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1236 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1237 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1238 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1239 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1240 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1241 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1242 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1243 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1244 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1245 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1246 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1247 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1248 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1249 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1250 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1251 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1252 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1253 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1254 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1255 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1256 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1257 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1258 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1259 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1260 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1261 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1262 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1263 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1264 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1265 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1266 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1267 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1268 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1269 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1270 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1271 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1272 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1273 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1274 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1275 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1276 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1277 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1278 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1279 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1280 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1281 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1282 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1283 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1284 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1285 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1286 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1287 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1288 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1289 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1290 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1291 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1292 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1293 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1294 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1295 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1296 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1297 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1298 { "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1299 { "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1300 { "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } },
1301 { "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } },
1302 { "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1303 { "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1304 { "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } },
1305 { "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } },
1306 { "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1307 { "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1308 { "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1309 { "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } },
1310 { "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1311 { "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1312 { "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1313 { "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } },
1314 { "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1315 { "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1316 { "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } },
1317 { "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } },
1318 { "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1319 { "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1320 { "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } },
1321 { "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } },
1322 { "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1323 { "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1324 { "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1325 { "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } },
1326 { "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1327 { "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1328 { "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1329 { "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } },
1330 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1331 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1332 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1333 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1334 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1335 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1336 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1337 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1338 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1339 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1340 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1341 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1342 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1343 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1344 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1345 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1346 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1347 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1348 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1349 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1350 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1351 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1352 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1353 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1354 { "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } },
1355 { "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } },
1356 { "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } },
1357 { "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } },
1358 { "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } },
1359 { "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } },
1360 { "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } },
1361 { "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } },
1362 { "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } },
1363 { "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } },
1364 { "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } },
1365 { "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } },
1366
1367 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1368 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
1369 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
1370 { "svca", SC(17,1,0), SC_MASK, POWER, { SV } },
1371 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
1372
1373 { "b", B(18,0,0), B_MASK, PPC|POWER, { LI } },
1374 { "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } },
1375 { "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } },
1376 { "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } },
1377
1378 { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
1379
1380 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1381 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } },
1382 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1383 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } },
1384 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1385 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1386 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1387 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1388 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1389 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1390 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1391 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1392 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1393 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1394 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1395 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1396 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1397 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1398 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1399 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1400 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1401 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1402 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1403 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1404 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1405 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1406 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1407 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1408 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1409 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1410 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1411 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1412 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1413 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1414 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1415 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1416 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1417 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1418 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1419 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1420 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1421 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1422 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1423 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1424 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1425 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1426 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1427 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1428 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1429 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1430 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1431 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1432 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1433 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1434 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1435 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1436 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1437 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1438 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1439 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1440 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1441 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1442 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1443 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1444 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1445 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1446 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1447 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1448 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1449 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1450 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1451 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1452 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1453 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1454 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1455 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1456 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1457 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1458 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1459 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1460 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1461 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1462 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1463 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1464 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1465 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1466 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1467 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1468 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1469 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1470 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1471 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1472 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1473 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1474 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1475 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1476 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1477 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1478 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1479 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1480 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1481 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1482 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1483 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1484 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1485 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1486 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1487 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1488 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1489 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1490 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } },
1491 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } },
1492 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1493 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1494 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } },
1495 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } },
1496 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1497 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1498 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } },
1499 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } },
1500 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1501 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1502 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } },
1503 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } },
1504 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1505 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1506 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1507 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1508 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1509 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1510 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1511 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1512 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1513 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1514 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1515 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1516 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1517 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1518 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1519 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1520 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1521 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1522 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1523 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1524 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1525 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1526 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1527 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1528 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } },
1529 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } },
1530 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1531 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1532 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1533 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1534 { "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } },
1535 { "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } },
1536
1537 { "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } },
1538 { "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } },
1539
1540 { "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } },
1541
1542 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
1543
1544 { "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } },
1545
1546 { "isync", XL(19,150), 0xffffffff, PPC, { 0 } },
1547 { "ics", XL(19,150), 0xffffffff, POWER, { 0 } },
1548
1549 { "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } },
1550 { "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } },
1551
1552 { "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } },
1553
1554 { "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } },
1555
1556 { "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } },
1557 { "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } },
1558
1559 { "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } },
1560
1561 { "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } },
1562 { "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } },
1563
1564 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC, { 0 } },
1565 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC, { 0 } },
1566 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1567 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1568 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1569 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1570 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1571 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1572 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1573 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1574 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1575 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1576 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1577 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1578 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1579 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1580 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1581 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1582 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1583 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1584 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1585 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1586 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1587 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1588 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1589 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1590 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1591 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1592 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1593 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1594 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1595 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1596 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1597 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1598 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1599 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1600 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1601 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1602 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1603 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1604 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1605 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1606 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1607 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1608 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1609 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1610 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1611 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1612 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1613 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1614 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1615 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1616 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1617 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1618 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1619 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1620 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1621 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1622 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1623 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1624 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1625 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1626 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1627 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1628 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1629 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1630 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1631 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1632 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1633 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1634 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1635 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1636 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1637 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1638 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1639 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1640 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } },
1641 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1642 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1643 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } },
1644 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1645 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1646 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } },
1647 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1648 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1649 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } },
1650 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } },
1651 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1652 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1653 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } },
1654 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1655 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1656 { "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } },
1657 { "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } },
1658
1659 { "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MB,ME } },
1660 { "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MB,ME } },
1661
1662 { "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MB,ME } },
1663 { "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MB,ME } },
1664
1665 { "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } },
1666 { "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } },
1667 { "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MB,ME } },
1668 { "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MB,ME } },
1669 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } },
1670 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } },
1671 { "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MB,ME } },
1672 { "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MB,ME } },
1673
1674 { "rlmi", M(22,0), M_MASK, POWER, { RA,RS,RB,MB,ME } },
1675 { "rlmi.", M(22,1), M_MASK, POWER, { RA,RS,RB,MB,ME } },
1676
1677 { "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } },
1678 { "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MB,ME } },
1679 { "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MB,ME } },
1680 { "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } },
1681 { "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MB,ME } },
1682 { "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MB,ME } },
1683
1684 { "nop", OP(24), 0xffffffff, PPC, { 0 } },
1685 { "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } },
1686 { "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } },
1687
1688 { "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } },
1689 { "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } },
1690
1691 { "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } },
1692 { "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } },
1693
1694 { "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } },
1695 { "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } },
1696
1697 { "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } },
1698 { "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } },
1699
1700 { "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } },
1701 { "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } },
1702
1703 { "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1704 { "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1705 { "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1706 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1707 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1708 { "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1709
1710 { "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1711 { "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1712
1713 { "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1714 { "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1715
1716 { "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1717 { "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1718
1719 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1720 { "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1721 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1722 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1723
1724 { "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1725 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1726
1727 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
1728 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
1729 { "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
1730 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
1731
1732 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } },
1733 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } },
1734 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } },
1735 { "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } },
1736 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } },
1737 { "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } },
1738 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } },
1739 { "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } },
1740 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } },
1741 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } },
1742 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } },
1743 { "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } },
1744 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } },
1745 { "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } },
1746 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } },
1747 { "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } },
1748 { "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } },
1749 { "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } },
1750 { "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } },
1751 { "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } },
1752 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } },
1753 { "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } },
1754 { "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } },
1755 { "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } },
1756 { "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } },
1757 { "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } },
1758 { "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } },
1759 { "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } },
1760 { "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } },
1761 { "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } },
1762 { "t", X(31,4), X_MASK, POWER, { TO, RA, RB } },
1763
1764 { "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } },
1765 { "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } },
1766 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
1767 { "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } },
1768 { "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } },
1769 { "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } },
1770 { "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } },
1771 { "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } },
1772 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
1773 { "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } },
1774 { "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } },
1775 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
1776
1777 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
1778 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
1779
1780 { "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } },
1781 { "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } },
1782 { "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } },
1783 { "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } },
1784 { "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } },
1785 { "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } },
1786 { "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } },
1787 { "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } },
1788
1789 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
1790 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
1791
1792 { "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } },
1793
1794 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
1795
1796 { "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } },
1797
1798 { "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } },
1799 { "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } },
1800
1801 { "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } },
1802 { "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } },
1803 { "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } },
1804 { "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } },
1805
1806 { "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } },
1807 { "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } },
1808 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } },
1809 { "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } },
1810
1811 { "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } },
1812 { "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } },
1813
1814 { "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } },
1815 { "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } },
1816
1817 { "maskg", XRC(31,29,0), X_MASK, POWER, { RA, RS, RB } },
1818 { "maskg.", XRC(31,29,1), X_MASK, POWER, { RA, RS, RB } },
1819
1820 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
1821 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
1822 { "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
1823 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
1824
1825 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
1826 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
1827 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
1828 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
1829 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
1830 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
1831 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
1832 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
1833
1834 { "ldux", X(31,53), X_MASK, PPC|B64, { RT, RA, RB } },
1835
1836 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
1837
1838 { "lwzux", X(31,55), X_MASK, PPC, { RT, RA, RB } },
1839 { "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
1840
1841 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } },
1842 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } },
1843
1844 { "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } },
1845 { "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } },
1846
1847 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } },
1848 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } },
1849 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } },
1850 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } },
1851 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } },
1852 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } },
1853 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } },
1854 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } },
1855 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } },
1856 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } },
1857 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } },
1858 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } },
1859 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } },
1860 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } },
1861 { "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } },
1862
1863 { "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
1864 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
1865
1866 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
1867 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
1868
1869 { "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } },
1870
1871 { "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } },
1872
1873 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
1874
1875 { "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } },
1876
1877 { "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } },
1878 { "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } },
1879 { "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } },
1880 { "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } },
1881
1882 { "mul", XO(31,107,0,0), XO_MASK, POWER, { RT, RA, RB } },
1883 { "mul.", XO(31,107,0,1), XO_MASK, POWER, { RT, RA, RB } },
1884 { "mulo", XO(31,107,1,0), XO_MASK, POWER, { RT, RA, RB } },
1885 { "mulo.", XO(31,107,1,1), XO_MASK, POWER, { RT, RA, RB } },
1886
1887 { "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
1888
1889 { "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RA, RB } },
1890
1891 { "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
1892 { "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
1893 { "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
1894 { "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } },
1895
1896 { "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } },
1897 { "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } },
1898 { "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } },
1899 { "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } },
1900 { "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } },
1901 { "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } },
1902 { "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } },
1903 { "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } },
1904
1905 { "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } },
1906 { "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } },
1907 { "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } },
1908 { "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } },
1909 { "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } },
1910 { "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } },
1911 { "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } },
1912 { "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } },
1913
1914 { "mtcrf", X(31,144), X_MASK|(1<<20)|(1<<11), PPC|POWER, { FXM, RS } },
1915
1916 { "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } },
1917
1918 { "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } },
1919
1920 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
1921
1922 { "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } },
1923 { "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } },
1924
1925 { "slq", XRC(31,152,0), X_MASK, POWER, { RA, RS, RB } },
1926 { "slq.", XRC(31,152,1), X_MASK, POWER, { RA, RS, RB } },
1927
1928 { "sle", XRC(31,153,0), X_MASK, POWER, { RA, RS, RB } },
1929 { "sle.", XRC(31,153,1), X_MASK, POWER, { RA, RS, RB } },
1930
1931 { "stdux", X(31,181), X_MASK, PPC|B64, { RS, RA, RB } },
1932
1933 { "stwux", X(31,183), X_MASK, PPC, { RS, RA, RB } },
1934 { "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } },
1935
1936 { "sliq", XRC(31,184,0), X_MASK, POWER, { RA, RS, SH } },
1937 { "sliq.", XRC(31,184,1), X_MASK, POWER, { RA, RS, SH } },
1938
1939 { "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } },
1940 { "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } },
1941 { "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } },
1942 { "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } },
1943 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } },
1944 { "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } },
1945 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } },
1946 { "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } },
1947
1948 { "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } },
1949 { "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } },
1950 { "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } },
1951 { "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } },
1952 { "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } },
1953 { "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } },
1954 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } },
1955 { "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } },
1956
1957 { "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } },
1958
1959 { "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } },
1960
1961 { "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } },
1962
1963 { "sllq", XRC(31,216,0), X_MASK, POWER, { RA, RS, RB } },
1964 { "sllq.", XRC(31,216,1), X_MASK, POWER, { RA, RS, RB } },
1965
1966 { "sleq", XRC(31,217,0), X_MASK, POWER, { RA, RS, RB } },
1967 { "sleq.", XRC(31,217,1), X_MASK, POWER, { RA, RS, RB } },
1968
1969 { "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } },
1970 { "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } },
1971 { "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } },
1972 { "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } },
1973 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } },
1974 { "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } },
1975 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } },
1976 { "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } },
1977
1978 { "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
1979 { "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
1980 { "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
1981 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
1982
1983 { "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } },
1984 { "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } },
1985 { "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } },
1986 { "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } },
1987 { "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } },
1988 { "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } },
1989 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } },
1990 { "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } },
1991
1992 { "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } },
1993 { "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } },
1994 { "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } },
1995 { "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } },
1996 { "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } },
1997 { "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } },
1998 { "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } },
1999 { "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } },
2000
2001 { "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } },
2002 { "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } },
2003
2004 { "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
2005
2006 { "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RA, RB } },
2007
2008 { "slliq", XRC(31,248,0), X_MASK, POWER, { RA, RS, SH } },
2009 { "slliq.", XRC(31,248,1), X_MASK, POWER, { RA, RS, SH } },
2010
2011 { "doz", XO(31,264,0,0), XO_MASK, POWER, { RT, RA, RB } },
2012 { "doz.", XO(31,264,0,1), XO_MASK, POWER, { RT, RA, RB } },
2013 { "dozo", XO(31,264,1,0), XO_MASK, POWER, { RT, RA, RB } },
2014 { "dozo.", XO(31,264,1,1), XO_MASK, POWER, { RT, RA, RB } },
2015
2016 { "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } },
2017 { "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } },
2018 { "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } },
2019 { "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } },
2020 { "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } },
2021 { "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } },
2022 { "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } },
2023 { "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } },
2024
2025 { "lscbx", XRC(31,277,0), X_MASK, POWER, { RT, RA, RB } },
2026 { "lscbx.", XRC(31,277,1), X_MASK, POWER, { RT, RA, RB } },
2027
2028 { "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
2029
2030 { "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } },
2031
2032 { "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2033 { "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2034
2035 { "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
2036 { "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } },
2037
2038 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2039
2040 { "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RA, RB } },
2041
2042 { "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2043 { "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2044
2045 { "div", XO(31,331,0,0), XO_MASK, POWER, { RT, RA, RB } },
2046 { "div.", XO(31,331,0,1), XO_MASK, POWER, { RT, RA, RB } },
2047 { "divo", XO(31,331,1,0), XO_MASK, POWER, { RT, RA, RB } },
2048 { "divo.", XO(31,331,1,1), XO_MASK, POWER, { RT, RA, RB } },
2049
2050 { "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } },
2051 { "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } },
2052 { "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } },
2053 { "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } },
2054
2055 { "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } },
2056
2057 { "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } },
2058
2059 { "abs", XO(31,360,0,0), XORB_MASK, POWER, { RT, RA } },
2060 { "abs.", XO(31,360,0,1), XORB_MASK, POWER, { RT, RA } },
2061 { "abso", XO(31,360,1,0), XORB_MASK, POWER, { RT, RA } },
2062 { "abso.", XO(31,360,1,1), XORB_MASK, POWER, { RT, RA } },
2063
2064 { "divs", XO(31,363,0,0), XO_MASK, POWER, { RT, RA, RB } },
2065 { "divs.", XO(31,363,0,1), XO_MASK, POWER, { RT, RA, RB } },
2066 { "divso", XO(31,363,1,0), XO_MASK, POWER, { RT, RA, RB } },
2067 { "divso.", XO(31,363,1,1), XO_MASK, POWER, { RT, RA, RB } },
2068
2069 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2070
2071 { "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2072
2073 { "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RA, RB } },
2074
2075 { "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RA, RB } },
2076
2077 { "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } },
2078
2079 { "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2080 { "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2081
2082 { "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2083 { "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2084
2085 { "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } },
2086
2087 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2088
2089 { "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RA, RB } },
2090
2091 { "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2092 { "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2093 { "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2094 { "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2095
2096 { "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2097 { "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2098 { "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2099 { "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2100
2101 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
2102 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
2103 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
2104 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
2105
2106 { "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } },
2107 { "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } },
2108 { "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } },
2109 { "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } },
2110
2111 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
2112
2113 { "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2114 { "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2115
2116 { "nabs", XO(31,488,0,0), XORB_MASK, POWER, { RT, RA } },
2117 { "nabs.", XO(31,488,0,1), XORB_MASK, POWER, { RT, RA } },
2118 { "nabso", XO(31,488,1,0), XORB_MASK, POWER, { RT, RA } },
2119 { "nabso.", XO(31,488,1,1), XORB_MASK, POWER, { RT, RA } },
2120
2121 { "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2122 { "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2123 { "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2124 { "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2125
2126 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
2127 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
2128 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
2129 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
2130
2131 { "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } },
2132
2133 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
2134
2135 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } },
2136
2137 { "clcs", X(31,531), XRB_MASK, POWER, { RT, RA } },
2138
2139 { "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } },
2140 { "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } },
2141
2142 { "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } },
2143 { "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } },
2144
2145 { "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } },
2146
2147 { "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } },
2148 { "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } },
2149 { "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } },
2150 { "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } },
2151
2152 { "rrib", XRC(31,537,0), X_MASK, POWER, { RA, RS, RB } },
2153 { "rrib.", XRC(31,537,1), X_MASK, POWER, { RA, RS, RB } },
2154
2155 { "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } },
2156 { "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } },
2157
2158 { "maskir", XRC(31,541,0), X_MASK, POWER, { RA, RS, RB } },
2159 { "maskir.", XRC(31,541,1), X_MASK, POWER, { RA, RS, RB } },
2160
2161 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
2162
2163 { "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RA, RB } },
2164
2165 { "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
2166
2167 { "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } },
2168 { "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } },
2169
2170 { "sync", X(31,598), 0xffffffff, PPC, { 0 } },
2171 { "dcs", X(31,598), 0xffffffff, POWER, { 0 } },
2172
2173 { "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } },
2174
2175 { "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } },
2176
2177 { "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } },
2178
2179 { "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RA, RB } },
2180
2181 { "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } },
2182
2183 { "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } },
2184 { "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } },
2185
2186 { "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } },
2187 { "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } },
2188
2189 { "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } },
2190
2191 { "srq", XRC(31,664,0), X_MASK, POWER, { RA, RS, RB } },
2192 { "srq.", XRC(31,664,1), X_MASK, POWER, { RA, RS, RB } },
2193
2194 { "sre", XRC(31,665,0), X_MASK, POWER, { RA, RS, RB } },
2195 { "sre.", XRC(31,665,1), X_MASK, POWER, { RA, RS, RB } },
2196
2197 { "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RA, RB } },
2198
2199 { "sriq", XRC(31,696,0), X_MASK, POWER, { RA, RS, SH } },
2200 { "sriq.", XRC(31,696,1), X_MASK, POWER, { RA, RS, SH } },
2201
2202 { "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } },
2203 { "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } },
2204
2205 { "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } },
2206
2207 { "srlq", XRC(31,728,0), X_MASK, POWER, { RA, RS, RB } },
2208 { "srlq.", XRC(31,728,1), X_MASK, POWER, { RA, RS, RB } },
2209
2210 { "sreq", XRC(31,729,0), X_MASK, POWER, { RA, RS, RB } },
2211 { "sreq.", XRC(31,729,1), X_MASK, POWER, { RA, RS, RB } },
2212
2213 { "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RA, RB } },
2214
2215 { "srliq", XRC(31,760,0), X_MASK, POWER, { RA, RS, SH } },
2216 { "srliq.", XRC(31,760,1), X_MASK, POWER, { RA, RS, SH } },
2217
2218 { "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } },
2219
2220 { "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } },
2221 { "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } },
2222 { "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } },
2223 { "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } },
2224
2225 { "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } },
2226 { "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } },
2227
2228 { "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } },
2229
2230 { "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } },
2231 { "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } },
2232 { "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } },
2233 { "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } },
2234
2235 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
2236
2237 { "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } },
2238
2239 { "sraq", XRC(31,920,0), X_MASK, POWER, { RA, RS, RB } },
2240 { "sraq.", XRC(31,920,1), X_MASK, POWER, { RA, RS, RB } },
2241
2242 { "srea", XRC(31,921,0), X_MASK, POWER, { RA, RS, RB } },
2243 { "srea.", XRC(31,921,1), X_MASK, POWER, { RA, RS, RB } },
2244
2245 { "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } },
2246 { "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } },
2247 { "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } },
2248 { "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } },
2249
2250 { "sraiq", XRC(31,952,0), X_MASK, POWER, { RA, RS, SH } },
2251 { "sraiq.", XRC(31,952,1), X_MASK, POWER, { RA, RS, SH } },
2252
2253 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
2254 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
2255
2256 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
2257
2258 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
2259
2260 { "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
2261 { "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
2262
2263 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2264 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2265
2266 { "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } },
2267 { "l", OP(32), OP_MASK, POWER, { RT, D, RA } },
2268
2269 { "lwzu", OP(33), OP_MASK, PPC, { RT, D, RA } },
2270 { "lu", OP(33), OP_MASK, POWER, { RT, D, RA } },
2271
2272 { "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } },
2273
2274 { "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RA } },
2275
2276 { "stw", OP(36), OP_MASK, PPC, { RS, D, RA } },
2277 { "st", OP(36), OP_MASK, POWER, { RS, D, RA } },
2278
2279 { "stwu", OP(37), OP_MASK, PPC, { RS, D, RA } },
2280 { "stu", OP(37), OP_MASK, POWER, { RS, D, RA } },
2281
2282 { "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } },
2283
2284 { "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RA } },
2285
2286 { "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } },
2287
2288 { "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RA } },
2289
2290 { "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } },
2291
2292 { "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RA } },
2293
2294 { "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } },
2295
2296 { "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RA } },
2297
2298 { "lmw", OP(46), OP_MASK, PPC, { RT, D, RA } },
2299 { "lm", OP(46), OP_MASK, POWER, { RT, D, RA } },
2300
2301 { "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } },
2302 { "stm", OP(47), OP_MASK, POWER, { RS, D, RA } },
2303
2304 { "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } },
2305
2306 { "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RA } },
2307
2308 { "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } },
2309
2310 { "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RA } },
2311
2312 { "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } },
2313
2314 { "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RA } },
2315
2316 { "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } },
2317
2318 { "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RA } },
2319
2320 { "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } },
2321
2322 { "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RA } },
2323
2324 { "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } },
2325
2326 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2327 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2328
2329 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2330 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2331
2332 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2333 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2334
2335 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2336 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2337
2338 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2339 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2340
2341 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2342 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2343
2344 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2345 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2346
2347 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2348 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2349
2350 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2351 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2352
2353 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2354 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2355
2356 { "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } },
2357
2358 { "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RA } },
2359
2360 { "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2361
2362 { "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2363 { "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2364
2365 { "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } },
2366 { "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } },
2367
2368 { "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } },
2369 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } },
2370
2371 { "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2372 { "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2373 { "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2374 { "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2375
2376 { "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2377 { "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2378 { "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2379 { "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2380
2381 { "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2382 { "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2383 { "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2384 { "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2385
2386 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2387 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2388
2389 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2390 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2391
2392 { "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2393 { "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2394 { "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2395 { "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2396
2397 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2398 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2399
2400 { "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2401 { "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2402 { "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2403 { "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2404
2405 { "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2406 { "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2407 { "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2408 { "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2409
2410 { "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2411 { "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2412 { "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2413 { "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2414
2415 { "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2416 { "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2417 { "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2418 { "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2419
2420 { "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2421
2422 { "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } },
2423 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } },
2424
2425 { "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2426 { "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2427
2428 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
2429
2430 { "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } },
2431 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } },
2432
2433 { "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2434 { "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2435
2436 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2437 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2438
2439 { "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2440 { "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2441
2442 { "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2443 { "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2444
2445 { "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } },
2446 { "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } },
2447
2448 { "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } },
2449 { "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } },
2450
2451 { "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2452 { "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2453
2454 { "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2455 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2456
2457 { "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2458 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2459
2460 };
2461
2462 const int powerpc_num_opcodes =
2463 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);