37f1aeb780caf70ebe5b2d82bab7dd9f753578ff
[binutils-gdb.git] / opcodes / ppc-opc.c
1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright (C) 1994-2023 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "opcode/ppc.h"
25 #include "opintl.h"
26 #include "libiberty.h"
27
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the text segment.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38
39 /* The functions used to insert and extract complicated operands. */
40
41 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
42
43 static uint64_t
44 insert_arx (uint64_t insn,
45 int64_t value,
46 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
47 const char **errmsg ATTRIBUTE_UNUSED)
48 {
49 value -= 8;
50 if (value < 0 || value >= 16)
51 {
52 *errmsg = _("invalid register");
53 value = 0xf;
54 }
55 return insn | value;
56 }
57
58 static int64_t
59 extract_arx (uint64_t insn,
60 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
61 int *invalid ATTRIBUTE_UNUSED)
62 {
63 return (insn & 0xf) + 8;
64 }
65
66 static uint64_t
67 insert_ary (uint64_t insn,
68 int64_t value,
69 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
70 const char **errmsg ATTRIBUTE_UNUSED)
71 {
72 value -= 8;
73 if (value < 0 || value >= 16)
74 {
75 *errmsg = _("invalid register");
76 value = 0xf;
77 }
78 return insn | (value << 4);
79 }
80
81 static int64_t
82 extract_ary (uint64_t insn,
83 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
84 int *invalid ATTRIBUTE_UNUSED)
85 {
86 return ((insn >> 4) & 0xf) + 8;
87 }
88
89 static uint64_t
90 insert_rx (uint64_t insn,
91 int64_t value,
92 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
93 const char **errmsg)
94 {
95 if (value >= 0 && value < 8)
96 ;
97 else if (value >= 24 && value <= 31)
98 value -= 16;
99 else
100 {
101 *errmsg = _("invalid register");
102 value = 0xf;
103 }
104 return insn | value;
105 }
106
107 static int64_t
108 extract_rx (uint64_t insn,
109 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
110 int *invalid ATTRIBUTE_UNUSED)
111 {
112 int64_t value = insn & 0xf;
113 if (value >= 0 && value < 8)
114 return value;
115 else
116 return value + 16;
117 }
118
119 static uint64_t
120 insert_ry (uint64_t insn,
121 int64_t value,
122 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
123 const char **errmsg)
124 {
125 if (value >= 0 && value < 8)
126 ;
127 else if (value >= 24 && value <= 31)
128 value -= 16;
129 else
130 {
131 *errmsg = _("invalid register");
132 value = 0xf;
133 }
134 return insn | (value << 4);
135 }
136
137 static int64_t
138 extract_ry (uint64_t insn,
139 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
140 int *invalid ATTRIBUTE_UNUSED)
141 {
142 int64_t value = (insn >> 4) & 0xf;
143 if (value >= 0 && value < 8)
144 return value;
145 else
146 return value + 16;
147 }
148
149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
150 VRA and VRB fields in a VX form instruction when they must be the same.
151 This is used for extended mnemonics like crclr. The extraction function
152 enforces that the fields are the same. */
153
154 static uint64_t
155 insert_bab (uint64_t insn,
156 int64_t value,
157 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
158 const char **errmsg ATTRIBUTE_UNUSED)
159 {
160 value &= 0x1f;
161 return insn | (value << 16) | (value << 11);
162 }
163
164 static int64_t
165 extract_bab (uint64_t insn,
166 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
167 int *invalid)
168 {
169 int64_t ba = (insn >> 16) & 0x1f;
170 int64_t bb = (insn >> 11) & 0x1f;
171
172 if (ba != bb)
173 *invalid = 1;
174 return ba;
175 }
176
177 /* The BT, BA and BB fields in an XL form instruction when they must all be
178 the same. This is used for extended mnemonics like crclr. The extraction
179 function enforces that the fields are the same. */
180
181 static uint64_t
182 insert_btab (uint64_t insn,
183 int64_t value,
184 ppc_cpu_t dialect,
185 const char **errmsg)
186 {
187 value &= 0x1f;
188 return (value << 21) | insert_bab (insn, value, dialect, errmsg);
189 }
190
191 static int64_t
192 extract_btab (uint64_t insn,
193 ppc_cpu_t dialect,
194 int *invalid)
195 {
196 int64_t bt = (insn >> 21) & 0x1f;
197 int64_t bab = extract_bab (insn, dialect, invalid);
198
199 if (bt != bab)
200 *invalid = 1;
201 return bt;
202 }
203
204 /* The BD field in a B form instruction when the - modifier is used.
205 This modifier means that the branch is not expected to be taken.
206 For chips built to versions of the architecture prior to version 2
207 (ie. not Power4 compatible), we set the y bit of the BO field to 1
208 if the offset is negative. When extracting, we require that the y
209 bit be 1 and that the offset be positive, since if the y bit is 0
210 we just want to print the normal form of the instruction.
211 Power4 compatible targets use two bits, "a", and "t", instead of
212 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
213 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
214 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
215 for branch on CTR. We only handle the taken/not-taken hint here.
216 Note that we don't relax the conditions tested here when
217 disassembling with -Many because insns using extract_bdm and
218 extract_bdp always occur in pairs. One or the other will always
219 be valid. */
220
221 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
222
223 static uint64_t
224 insert_bdm (uint64_t insn,
225 int64_t value,
226 ppc_cpu_t dialect,
227 const char **errmsg ATTRIBUTE_UNUSED)
228 {
229 if ((dialect & ISA_V2) == 0)
230 {
231 if ((value & 0x8000) != 0)
232 insn |= 1 << 21;
233 }
234 else
235 {
236 if ((insn & (0x14 << 21)) == (0x04 << 21))
237 insn |= 0x02 << 21;
238 else if ((insn & (0x14 << 21)) == (0x10 << 21))
239 insn |= 0x08 << 21;
240 }
241 return insn | (value & 0xfffc);
242 }
243
244 static int64_t
245 extract_bdm (uint64_t insn,
246 ppc_cpu_t dialect,
247 int *invalid)
248 {
249 if ((dialect & ISA_V2) == 0)
250 {
251 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
252 *invalid = 1;
253 }
254 else
255 {
256 if ((insn & (0x17 << 21)) != (0x06 << 21)
257 && (insn & (0x1d << 21)) != (0x18 << 21))
258 *invalid = 1;
259 }
260
261 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
262 }
263
264 /* The BD field in a B form instruction when the + modifier is used.
265 This is like BDM, above, except that the branch is expected to be
266 taken. */
267
268 static uint64_t
269 insert_bdp (uint64_t insn,
270 int64_t value,
271 ppc_cpu_t dialect,
272 const char **errmsg ATTRIBUTE_UNUSED)
273 {
274 if ((dialect & ISA_V2) == 0)
275 {
276 if ((value & 0x8000) == 0)
277 insn |= 1 << 21;
278 }
279 else
280 {
281 if ((insn & (0x14 << 21)) == (0x04 << 21))
282 insn |= 0x03 << 21;
283 else if ((insn & (0x14 << 21)) == (0x10 << 21))
284 insn |= 0x09 << 21;
285 }
286 return insn | (value & 0xfffc);
287 }
288
289 static int64_t
290 extract_bdp (uint64_t insn,
291 ppc_cpu_t dialect,
292 int *invalid)
293 {
294 if ((dialect & ISA_V2) == 0)
295 {
296 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
297 *invalid = 1;
298 }
299 else
300 {
301 if ((insn & (0x17 << 21)) != (0x07 << 21)
302 && (insn & (0x1d << 21)) != (0x19 << 21))
303 *invalid = 1;
304 }
305
306 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
307 }
308
309 static inline int
310 valid_bo_pre_v2 (int64_t value)
311 {
312 /* Certain encodings have bits that are required to be zero.
313 These are (z must be zero, y may be anything):
314 0000y
315 0001y
316 001zy
317 0100y
318 0101y
319 011zy
320 1z00y
321 1z01y
322 1z1zz
323 */
324 if ((value & 0x14) == 0)
325 /* BO: 0000y, 0001y, 0100y, 0101y. */
326 return 1;
327 else if ((value & 0x14) == 0x4)
328 /* BO: 001zy, 011zy. */
329 return (value & 0x2) == 0;
330 else if ((value & 0x14) == 0x10)
331 /* BO: 1z00y, 1z01y. */
332 return (value & 0x8) == 0;
333 else
334 /* BO: 1z1zz. */
335 return value == 0x14;
336 }
337
338 static inline int
339 valid_bo_post_v2 (int64_t value)
340 {
341 /* Certain encodings have bits that are required to be zero.
342 These are (z must be zero, a & t may be anything):
343 0000z
344 0001z
345 001at
346 0100z
347 0101z
348 011at
349 1a00t
350 1a01t
351 1z1zz
352 */
353 if ((value & 0x14) == 0)
354 /* BO: 0000z, 0001z, 0100z, 0101z. */
355 return (value & 0x1) == 0;
356 else if ((value & 0x14) == 0x14)
357 /* BO: 1z1zz. */
358 return value == 0x14;
359 else if ((value & 0x14) == 0x4)
360 /* BO: 001at, 011at, with "at" == 0b01 being reserved. */
361 return (value & 0x3) != 1;
362 else if ((value & 0x14) == 0x10)
363 /* BO: 1a00t, 1a01t, with "at" == 0b01 being reserved. */
364 return (value & 0x9) != 1;
365 else
366 return 1;
367 }
368
369 /* Check for legal values of a BO field. */
370
371 static int
372 valid_bo (int64_t value, ppc_cpu_t dialect, int extract)
373 {
374 int valid_y = valid_bo_pre_v2 (value);
375 int valid_at = valid_bo_post_v2 (value);
376
377 /* When disassembling with -Many, accept either encoding on the
378 second pass through opcodes. */
379 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
380 return valid_y || valid_at;
381 if ((dialect & ISA_V2) == 0)
382 return valid_y;
383 else
384 return valid_at;
385 }
386
387 /* The BO field in a B form instruction. Warn about attempts to set
388 the field to an illegal value. */
389
390 static uint64_t
391 insert_bo (uint64_t insn,
392 int64_t value,
393 ppc_cpu_t dialect,
394 const char **errmsg)
395 {
396 if (!valid_bo (value, dialect, 0))
397 *errmsg = _("invalid conditional option");
398 else if (PPC_OP (insn) == 19
399 && (((insn >> 1) & 0x3ff) == 528) && ! (value & 4))
400 *errmsg = _("invalid counter access");
401 return insn | ((value & 0x1f) << 21);
402 }
403
404 static int64_t
405 extract_bo (uint64_t insn,
406 ppc_cpu_t dialect,
407 int *invalid)
408 {
409 int64_t value = (insn >> 21) & 0x1f;
410 if (!valid_bo (value, dialect, 1))
411 *invalid = 1;
412 return value;
413 }
414
415 /* For the given BO value, return a bit mask detailing which bits
416 define the branch hints. */
417
418 static int64_t
419 get_bo_hint_mask (int64_t bo, ppc_cpu_t dialect)
420 {
421 if ((dialect & ISA_V2) == 0)
422 {
423 if ((bo & 0x14) != 0x14)
424 /* BO: 0000y, 0001y, 001zy, 0100y, 0101y, 011zy, 1z00y, 1z01y . */
425 return 1;
426 else
427 /* BO: 1z1zz. */
428 return 0;
429 }
430 else
431 {
432 if ((bo & 0x14) == 0x4)
433 /* BO: 001at, 011at. */
434 return 0x3;
435 else if ((bo & 0x14) == 0x10)
436 /* BO: 1a00t, 1a01t. */
437 return 0x9;
438 else
439 /* BO: 0000z, 0001z, 0100z, 0101z, 1z1zz. */
440 return 0;
441 }
442 }
443
444 /* The BO field in a B form instruction when the + or - modifier is used. */
445
446 static uint64_t
447 insert_boe (uint64_t insn,
448 int64_t value,
449 ppc_cpu_t dialect,
450 const char **errmsg,
451 int branch_taken)
452 {
453 int64_t implied_hint;
454 int64_t hint_mask = get_bo_hint_mask (value, dialect);
455
456 if (branch_taken)
457 implied_hint = hint_mask;
458 else
459 implied_hint = hint_mask & ~1;
460
461 /* The branch hint bit(s) in the BO field must either be zero or exactly
462 match the branch hint bits implied by the '+' or '-' modifier. */
463 if (implied_hint == 0)
464 *errmsg = _("BO value implies no branch hint, when using + or - modifier");
465 else if ((value & hint_mask) != 0
466 && (value & hint_mask) != implied_hint)
467 {
468 if ((dialect & ISA_V2) == 0)
469 *errmsg = _("attempt to set y bit when using + or - modifier");
470 else
471 *errmsg = _("attempt to set 'at' bits when using + or - modifier");
472 }
473
474 value |= implied_hint;
475
476 return insert_bo (insn, value, dialect, errmsg);
477 }
478
479 static int64_t
480 extract_boe (uint64_t insn,
481 ppc_cpu_t dialect,
482 int *invalid,
483 int branch_taken)
484 {
485 int64_t value = (insn >> 21) & 0x1f;
486 int64_t implied_hint;
487 int64_t hint_mask = get_bo_hint_mask (value, dialect);
488
489 if (branch_taken)
490 implied_hint = hint_mask;
491 else
492 implied_hint = hint_mask & ~1;
493
494 if (!valid_bo (value, dialect, 1)
495 || implied_hint == 0
496 || (value & hint_mask) != implied_hint)
497 *invalid = 1;
498 return value;
499 }
500
501 /* The BO field in a B form instruction when the - modifier is used. */
502
503 static uint64_t
504 insert_bom (uint64_t insn,
505 int64_t value,
506 ppc_cpu_t dialect,
507 const char **errmsg)
508 {
509 return insert_boe (insn, value, dialect, errmsg, 0);
510 }
511
512 static int64_t
513 extract_bom (uint64_t insn,
514 ppc_cpu_t dialect,
515 int *invalid)
516 {
517 return extract_boe (insn, dialect, invalid, 0);
518 }
519
520 /* The BO field in a B form instruction when the + modifier is used. */
521
522 static uint64_t
523 insert_bop (uint64_t insn,
524 int64_t value,
525 ppc_cpu_t dialect,
526 const char **errmsg)
527 {
528 return insert_boe (insn, value, dialect, errmsg, 1);
529 }
530
531 static int64_t
532 extract_bop (uint64_t insn,
533 ppc_cpu_t dialect,
534 int *invalid)
535 {
536 return extract_boe (insn, dialect, invalid, 1);
537 }
538
539 /* The DCMX field in a X form instruction when the field is split
540 into separate DC, DM and DX fields. */
541
542 static uint64_t
543 insert_dcmxs (uint64_t insn,
544 int64_t value,
545 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
546 const char **errmsg ATTRIBUTE_UNUSED)
547 {
548 return (insn
549 | ((value & 0x1f) << 16)
550 | ((value & 0x20) >> 3)
551 | (value & 0x40));
552 }
553
554 static int64_t
555 extract_dcmxs (uint64_t insn,
556 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
557 int *invalid ATTRIBUTE_UNUSED)
558 {
559 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
560 }
561
562 /* The DW field in a X form instruction when the field is split
563 into separate D and DX fields. */
564
565 static uint64_t
566 insert_dw (uint64_t insn,
567 int64_t value,
568 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
569 const char **errmsg ATTRIBUTE_UNUSED)
570 {
571 /* DW offsets must be in the range [-512, -8] and be a multiple of 8. */
572 if (value < -512
573 || value > -8
574 || (value & 0x7) != 0)
575 *errmsg = _("invalid offset: must be in the range [-512, -8] "
576 "and be a multiple of 8");
577
578 return insn | ((value & 0xf8) << 18) | ((value >> 8) & 1);
579 }
580
581 static int64_t
582 extract_dw (uint64_t insn,
583 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
584 int *invalid ATTRIBUTE_UNUSED)
585 {
586 int64_t dw = ((insn & 1) << 8) | ((insn >> 18) & 0xf8);
587 return dw - 512;
588 }
589
590 /* The D field in a DX form instruction when the field is split
591 into separate D0, D1 and D2 fields. */
592
593 static uint64_t
594 insert_dxd (uint64_t insn,
595 int64_t value,
596 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
597 const char **errmsg ATTRIBUTE_UNUSED)
598 {
599 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
600 }
601
602 static int64_t
603 extract_dxd (uint64_t insn,
604 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
605 int *invalid ATTRIBUTE_UNUSED)
606 {
607 uint64_t dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
608 return (dxd ^ 0x8000) - 0x8000;
609 }
610
611 static uint64_t
612 insert_dxdn (uint64_t insn,
613 int64_t value,
614 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
615 const char **errmsg ATTRIBUTE_UNUSED)
616 {
617 return insert_dxd (insn, -value, dialect, errmsg);
618 }
619
620 static int64_t
621 extract_dxdn (uint64_t insn,
622 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
623 int *invalid)
624 {
625 return -extract_dxd (insn, dialect, invalid);
626 }
627
628 /* The D field in a 64-bit D form prefix instruction when the field is split
629 into separate D0 and D1 fields. */
630
631 static uint64_t
632 insert_d34 (uint64_t insn,
633 int64_t value,
634 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
635 const char **errmsg ATTRIBUTE_UNUSED)
636 {
637 return insn | ((value & 0x3ffff0000ULL) << 16) | (value & 0xffff);
638 }
639
640 static int64_t
641 extract_d34 (uint64_t insn,
642 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
643 int *invalid ATTRIBUTE_UNUSED)
644 {
645 int64_t mask = 1ULL << 33;
646 int64_t value = ((insn >> 16) & 0x3ffff0000ULL) | (insn & 0xffff);
647 value = (value ^ mask) - mask;
648 return value;
649 }
650
651 /* The NSI34 field in an 8-byte D form prefix instruction. This is the same
652 as the SI34 field, only negated. The extraction function always marks it
653 as invalid, since we never want to recognize an instruction which uses
654 a field of this type. */
655
656 static uint64_t
657 insert_nsi34 (uint64_t insn,
658 int64_t value,
659 ppc_cpu_t dialect,
660 const char **errmsg)
661 {
662 return insert_d34 (insn, -value, dialect, errmsg);
663 }
664
665 static int64_t
666 extract_nsi34 (uint64_t insn,
667 ppc_cpu_t dialect,
668 int *invalid)
669 {
670 int64_t value = extract_d34 (insn, dialect, invalid);
671 *invalid = 1;
672 return -value;
673 }
674
675 /* The split IMM32 field in a vector splat insn. */
676
677 static uint64_t
678 insert_imm32 (uint64_t insn,
679 int64_t value,
680 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
681 const char **errmsg ATTRIBUTE_UNUSED)
682 {
683 return insn | ((value & 0xffff0000) << 16) | (value & 0xffff);
684 }
685
686 static int64_t
687 extract_imm32 (uint64_t insn,
688 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
689 int *invalid ATTRIBUTE_UNUSED)
690 {
691 return (insn & 0xffff) | ((insn >> 16) & 0xffff0000);
692 }
693
694 /* The R field in an 8-byte prefix instruction when there are restrictions
695 between R's value and the RA value (ie, they cannot both be non zero). */
696
697 static uint64_t
698 insert_pcrel (uint64_t insn,
699 int64_t value,
700 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
701 const char **errmsg)
702 {
703 value &= 0x1;
704 int64_t ra = (insn >> 16) & 0x1f;
705 if (ra != 0 && value != 0)
706 *errmsg = _("invalid R operand");
707
708 return insn | (value << 52);
709 }
710
711 static int64_t
712 extract_pcrel (uint64_t insn,
713 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
714 int *invalid)
715 {
716 /* If called with *invalid < 0 to return the value for missing
717 operands, *invalid will be the negative count of missing operands
718 including this one. Return a default value of 1 if the PRA0/PRAQ
719 operand was also omitted (ie. *invalid is -2). Return a default
720 value of 0 if the PRA0/PRAQ operand was not omitted
721 (ie. *invalid is -1). */
722 if (*invalid < 0)
723 return ~ *invalid & 1;
724
725 int64_t ra = (insn >> 16) & 0x1f;
726 int64_t pcrel = (insn >> 52) & 0x1;
727 if (ra != 0 && pcrel != 0)
728 *invalid = 1;
729
730 return pcrel;
731 }
732
733 /* Variant of extract_pcrel that sets invalid for R bit clear. Used
734 to disassemble "paddi rt,0,offset,1" as "pla rt,offset". */
735
736 static int64_t
737 extract_pcrel1 (uint64_t insn,
738 ppc_cpu_t dialect,
739 int *invalid)
740 {
741 int64_t pcrel = extract_pcrel (insn, dialect, invalid);
742 if (!pcrel)
743 *invalid = 1;
744 return pcrel;
745 }
746
747 /* FXM mask in mfcr and mtcrf instructions. */
748
749 static uint64_t
750 insert_fxm (uint64_t insn,
751 int64_t value,
752 ppc_cpu_t dialect,
753 const char **errmsg)
754 {
755 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
756 one bit of the mask field is set. */
757 if ((insn & (1 << 20)) != 0)
758 {
759 if (value == 0 || (value & -value) != value)
760 {
761 *errmsg = _("invalid mask field");
762 value = 0;
763 }
764 }
765
766 /* If only one bit of the FXM field is set, we can use the new form
767 of the instruction, which is faster. Unlike the Power4 branch hint
768 encoding, this is not backward compatible. Do not generate the
769 new form unless -mpower4 has been given, or -many and the two
770 operand form of mfcr was used. */
771 else if (value > 0
772 && (value & -value) == value
773 && ((dialect & PPC_OPCODE_POWER4) != 0
774 || ((dialect & PPC_OPCODE_ANY) != 0
775 && (insn & (0x3ff << 1)) == 19 << 1)))
776 insn |= 1 << 20;
777
778 /* Any other value on mfcr is an error. */
779 else if ((insn & (0x3ff << 1)) == 19 << 1)
780 {
781 /* A value of -1 means we used the one operand form of
782 mfcr which is valid. */
783 if (value != -1)
784 *errmsg = _("invalid mfcr mask");
785 value = 0;
786 }
787
788 return insn | ((value & 0xff) << 12);
789 }
790
791 static int64_t
792 extract_fxm (uint64_t insn,
793 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
794 int *invalid)
795 {
796 /* Return a value of -1 for a missing optional operand, which is
797 used as a flag by insert_fxm. */
798 if (*invalid < 0)
799 return -1;
800
801 int64_t mask = (insn >> 12) & 0xff;
802 /* Is this a Power4 insn? */
803 if ((insn & (1 << 20)) != 0)
804 {
805 /* Exactly one bit of MASK should be set. */
806 if (mask == 0 || (mask & -mask) != mask)
807 *invalid = 1;
808 }
809
810 /* Check that non-power4 form of mfcr has a zero MASK. */
811 else if ((insn & (0x3ff << 1)) == 19 << 1)
812 {
813 if (mask != 0)
814 *invalid = 1;
815 else
816 mask = -1;
817 }
818
819 return mask;
820 }
821
822 /* L field in the paste. instruction. */
823
824 static uint64_t
825 insert_l1opt (uint64_t insn,
826 int64_t value,
827 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
828 const char **errmsg ATTRIBUTE_UNUSED)
829 {
830 return insn | ((value & 1) << 21);
831 }
832
833 static int64_t
834 extract_l1opt (uint64_t insn,
835 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
836 int *invalid)
837 {
838 /* Return a value of 1 for a missing optional operand. */
839 if (*invalid < 0)
840 return 1;
841
842 return (insn >> 21) & 1;
843 }
844
845 static uint64_t
846 insert_li20 (uint64_t insn,
847 int64_t value,
848 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
849 const char **errmsg ATTRIBUTE_UNUSED)
850 {
851 return (insn
852 | ((value & 0xf0000) >> 5)
853 | ((value & 0x0f800) << 5)
854 | (value & 0x7ff));
855 }
856
857 static int64_t
858 extract_li20 (uint64_t insn,
859 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
860 int *invalid ATTRIBUTE_UNUSED)
861 {
862 return ((((insn << 5) & 0xf0000)
863 | ((insn >> 5) & 0xf800)
864 | (insn & 0x7ff)) ^ 0x80000) - 0x80000;
865 }
866
867 /* The 2-bit/3-bit L or 2-bit WC field in a SYNC, DCBF or WAIT instruction.
868 For SYNC, some L values are reserved:
869 * Values 6 and 7 are reserved on newer server cpus.
870 * Value 3 is reserved on all server cpus.
871 * Value 2 is reserved on all other cpus.
872 For DCBF, some L values are reserved:
873 * Values 2, 5 and 7 are reserved on all cpus.
874 For WAIT, some WC values are reserved:
875 * Value 3 is reserved on all server cpus.
876 * Values 1 and 2 are reserved on older server cpus. */
877
878 static uint64_t
879 insert_ls (uint64_t insn,
880 int64_t value,
881 ppc_cpu_t dialect,
882 const char **errmsg)
883 {
884 int64_t mask;
885
886 if (((insn >> 1) & 0x3ff) == 598)
887 {
888 /* For SYNC, some L values are illegal. */
889 mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3;
890
891 /* If the value is within range, check for other illegal values. */
892 if ((value & mask) == value)
893 switch (value)
894 {
895 case 2:
896 if (dialect & PPC_OPCODE_POWER4)
897 break;
898 /* Fall through. */
899 case 3:
900 case 6:
901 case 7:
902 *errmsg = _("illegal L operand value");
903 break;
904 default:
905 break;
906 }
907 }
908 else if (((insn >> 1) & 0x3ff) == 86)
909 {
910 /* For DCBF, some L values are illegal. */
911 mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3;
912
913 /* If the value is within range, check for other illegal values. */
914 if ((value & mask) == value)
915 switch (value)
916 {
917 case 2:
918 case 5:
919 case 7:
920 *errmsg = _("illegal L operand value");
921 break;
922 default:
923 break;
924 }
925 }
926 else
927 {
928 /* For WAIT, some WC values are illegal. */
929 mask = 0x3;
930
931 /* If the value is within range, check for other illegal values. */
932 if ((dialect & PPC_OPCODE_A2) == 0
933 && (dialect & PPC_OPCODE_E500MC) == 0
934 && (value & mask) == value)
935 switch (value)
936 {
937 case 1:
938 case 2:
939 if (dialect & PPC_OPCODE_POWER10)
940 break;
941 /* Fall through. */
942 case 3:
943 *errmsg = _("illegal WC operand value");
944 break;
945 default:
946 break;
947 }
948 }
949
950 return insn | ((value & mask) << 21);
951 }
952
953 static int64_t
954 extract_ls (uint64_t insn,
955 ppc_cpu_t dialect,
956 int *invalid)
957 {
958 uint64_t value;
959
960 /* Missing optional operands have a value of zero. */
961 if (*invalid < 0)
962 return 0;
963
964 if (((insn >> 1) & 0x3ff) == 598)
965 {
966 /* For SYNC, some L values are illegal. */
967 int64_t mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3;
968
969 value = (insn >> 21) & mask;
970 switch (value)
971 {
972 case 2:
973 if (dialect & PPC_OPCODE_POWER4)
974 break;
975 /* Fall through. */
976 case 3:
977 case 6:
978 case 7:
979 *invalid = 1;
980 break;
981 default:
982 break;
983 }
984 }
985 else if (((insn >> 1) & 0x3ff) == 86)
986 {
987 /* For DCBF, some L values are illegal. */
988 int64_t mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3;
989
990 value = (insn >> 21) & mask;
991 switch (value)
992 {
993 case 2:
994 case 5:
995 case 7:
996 *invalid = 1;
997 break;
998 default:
999 break;
1000 }
1001 }
1002 else
1003 {
1004 /* For WAIT, some WC values are illegal. */
1005 value = (insn >> 21) & 0x3;
1006 if ((dialect & PPC_OPCODE_A2) == 0
1007 && (dialect & PPC_OPCODE_E500MC) == 0)
1008 switch (value)
1009 {
1010 case 1:
1011 case 2:
1012 if (dialect & PPC_OPCODE_POWER10)
1013 break;
1014 /* Fall through. */
1015 case 3:
1016 *invalid = 1;
1017 break;
1018 default:
1019 break;
1020 }
1021 }
1022
1023 return value;
1024 }
1025
1026 /* The 4-bit E field in a sync instruction that accepts 2 operands.
1027 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1028 the complement of ESYNC-bit2. */
1029
1030 static uint64_t
1031 insert_esync (uint64_t insn,
1032 int64_t value,
1033 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1034 const char **errmsg)
1035 {
1036 uint64_t ls = (insn >> 21) & 0x03;
1037
1038 if (value != 0
1039 && ((~value >> 1) & 0x1) != ls)
1040 *errmsg = _("incompatible L operand value");
1041
1042 return insn | ((value & 0xf) << 16);
1043 }
1044
1045 static int64_t
1046 extract_esync (uint64_t insn,
1047 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1048 int *invalid)
1049 {
1050 /* Missing optional operands have a value of zero. */
1051 if (*invalid < 0)
1052 return 0;
1053
1054 uint64_t ls = (insn >> 21) & 0x3;
1055 uint64_t value = (insn >> 16) & 0xf;
1056 if (value != 0
1057 && ((~value >> 1) & 0x1) != ls)
1058 *invalid = 1;
1059 return value;
1060 }
1061
1062 /* The n operand of clrrwi, which sets the ME field to 31 - n. */
1063
1064 static uint64_t
1065 insert_crwn (uint64_t insn,
1066 int64_t value,
1067 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1068 const char **errmsg ATTRIBUTE_UNUSED)
1069 {
1070 return insn | ((~value & 0x1f) << 1);
1071 }
1072
1073 static int64_t
1074 extract_crwn (uint64_t insn,
1075 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1076 int *invalid ATTRIBUTE_UNUSED)
1077 {
1078 return ~(insn >> 1) & 0x1f;
1079 }
1080
1081 /* The n operand of extlwi, which sets the ME field to n - 1. */
1082
1083 static uint64_t
1084 insert_elwn (uint64_t insn,
1085 int64_t value,
1086 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1087 const char **errmsg ATTRIBUTE_UNUSED)
1088 {
1089 return insn | (((value - 1) & 0x1f) << 1);
1090 }
1091
1092 static int64_t
1093 extract_elwn (uint64_t insn,
1094 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1095 int *invalid ATTRIBUTE_UNUSED)
1096 {
1097 return ((insn >> 1) & 0x1f) + 1;
1098 }
1099
1100 /* The n operand of extrwi, sets MB = 32 - n. */
1101
1102 static uint64_t
1103 insert_erwn (uint64_t insn,
1104 int64_t value,
1105 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1106 const char **errmsg ATTRIBUTE_UNUSED)
1107 {
1108 return insn | ((-value & 0x1f) << 6);
1109 }
1110
1111 static int64_t
1112 extract_erwn (uint64_t insn,
1113 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1114 int *invalid ATTRIBUTE_UNUSED)
1115 {
1116 return (~(insn >> 6) & 0x1f) + 1;
1117 }
1118
1119 /* The b operand of extrwi, sets SH = b + n. */
1120
1121 static uint64_t
1122 insert_erwb (uint64_t insn,
1123 int64_t value,
1124 ppc_cpu_t dialect,
1125 const char **errmsg ATTRIBUTE_UNUSED)
1126 {
1127 int64_t n = extract_erwn (insn, dialect, NULL);
1128 return insn | (((n + value) & 0x1f) << 11);
1129 }
1130
1131 static int64_t
1132 extract_erwb (uint64_t insn,
1133 ppc_cpu_t dialect,
1134 int *invalid ATTRIBUTE_UNUSED)
1135 {
1136 int64_t n = extract_erwn (insn, dialect, NULL);
1137 return ((insn >> 11) - n) & 0x1f;
1138 }
1139
1140 /* The n and b operands of clrlslwi. */
1141
1142 static uint64_t
1143 insert_cslwn (uint64_t insn,
1144 int64_t value,
1145 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1146 const char **errmsg ATTRIBUTE_UNUSED)
1147 {
1148 uint64_t mb = 0x1f << 6;
1149 int64_t b = (insn >> 6) & 0x1f;
1150 return ((insn & ~mb) | ((value & 0x1f) << 11) | (((b - value) & 0x1f) << 6)
1151 | ((~value & 0x1f) << 1));
1152 }
1153
1154 static int64_t
1155 extract_cslwb (uint64_t insn,
1156 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1157 int *invalid)
1158 {
1159 int64_t sh = (insn >> 11) & 0x1f;
1160 int64_t mb = (insn >> 6) & 0x1f;
1161 int64_t me = (insn >> 1) & 0x1f;
1162 if (sh != 31 - me)
1163 *invalid = 1;
1164 return (mb + sh) & 0x1f;
1165 }
1166
1167 /* The n and b operands of inslwi. */
1168
1169 static uint64_t
1170 insert_ilwb (uint64_t insn,
1171 int64_t value,
1172 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1173 const char **errmsg ATTRIBUTE_UNUSED)
1174 {
1175 uint64_t me = 0x1f << 1;
1176 int64_t n = (insn >> 1) & 0x1f;
1177 return ((insn & ~me) | ((-value & 0x1f) << 11) | ((value & 0x1f) << 6)
1178 | (((value + n - 1) & 0x1f) << 1));
1179 }
1180
1181 static int64_t
1182 extract_ilwn (uint64_t insn,
1183 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1184 int *invalid)
1185 {
1186 int64_t sh = (insn >> 11) & 0x1f;
1187 int64_t mb = (insn >> 6) & 0x1f;
1188 int64_t me = (insn >> 1) & 0x1f;
1189 if (((sh + mb) & 0x1f) != 0)
1190 *invalid = 1;
1191 return ((me - mb) & 0x1f) + 1;
1192 }
1193
1194 /* The n and b operands of insrwi. */
1195
1196 static uint64_t
1197 insert_irwb (uint64_t insn,
1198 int64_t value,
1199 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1200 const char **errmsg ATTRIBUTE_UNUSED)
1201 {
1202 uint64_t me = 0x1f << 1;
1203 int64_t n = (insn >> 1) & 0x1f;
1204 return ((insn & ~me) | ((-(value + n) & 0x1f) << 11) | ((value & 0x1f) << 6)
1205 | (((value + n - 1) & 0x1f) << 1));
1206 }
1207
1208 static int64_t
1209 extract_irwn (uint64_t insn,
1210 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1211 int *invalid)
1212 {
1213 int64_t sh = (insn >> 11) & 0x1f;
1214 int64_t mb = (insn >> 6) & 0x1f;
1215 int64_t me = (insn >> 1) & 0x1f;
1216 if (((sh + me + 1) & 0x1f) != 0)
1217 *invalid = 1;
1218 return ((me - mb) & 0x1f) + 1;
1219 }
1220
1221 /* The MB and ME fields in an M form instruction expressed as a single
1222 operand which is itself a bitmask. The extraction function always
1223 marks it as invalid, since we never want to recognize an
1224 instruction which uses a field of this type. */
1225
1226 static uint64_t
1227 insert_mbe (uint64_t insn,
1228 int64_t value,
1229 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1230 const char **errmsg)
1231 {
1232 uint64_t uval, mask;
1233 long mb, me, mx, count, last;
1234
1235 uval = value;
1236
1237 if (uval == 0)
1238 {
1239 *errmsg = _("illegal bitmask");
1240 return insn;
1241 }
1242
1243 mb = 0;
1244 me = 32;
1245 if ((uval & 1) != 0)
1246 last = 1;
1247 else
1248 last = 0;
1249 count = 0;
1250
1251 /* mb: location of last 0->1 transition */
1252 /* me: location of last 1->0 transition */
1253 /* count: # transitions */
1254
1255 for (mx = 0, mask = (uint64_t) 1 << 31; mx < 32; ++mx, mask >>= 1)
1256 {
1257 if ((uval & mask) && !last)
1258 {
1259 ++count;
1260 mb = mx;
1261 last = 1;
1262 }
1263 else if (!(uval & mask) && last)
1264 {
1265 ++count;
1266 me = mx;
1267 last = 0;
1268 }
1269 }
1270 if (me == 0)
1271 me = 32;
1272
1273 if (count != 2 && (count != 0 || ! last))
1274 *errmsg = _("illegal bitmask");
1275
1276 return insn | (mb << 6) | ((me - 1) << 1);
1277 }
1278
1279 static int64_t
1280 extract_mbe (uint64_t insn,
1281 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1282 int *invalid)
1283 {
1284 int64_t ret;
1285 long mb, me;
1286 long i;
1287
1288 *invalid = 1;
1289
1290 mb = (insn >> 6) & 0x1f;
1291 me = (insn >> 1) & 0x1f;
1292 if (mb < me + 1)
1293 {
1294 ret = 0;
1295 for (i = mb; i <= me; i++)
1296 ret |= (uint64_t) 1 << (31 - i);
1297 }
1298 else if (mb == me + 1)
1299 ret = ~0;
1300 else /* (mb > me + 1) */
1301 {
1302 ret = ~0;
1303 for (i = me + 1; i < mb; i++)
1304 ret &= ~((uint64_t) 1 << (31 - i));
1305 }
1306 return ret;
1307 }
1308
1309 /* The MB or ME field in an MD or MDS form instruction. The high bit
1310 is wrapped to the low end. */
1311
1312 static uint64_t
1313 insert_mb6 (uint64_t insn,
1314 int64_t value,
1315 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1316 const char **errmsg ATTRIBUTE_UNUSED)
1317 {
1318 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1319 }
1320
1321 static int64_t
1322 extract_mb6 (uint64_t insn,
1323 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1324 int *invalid ATTRIBUTE_UNUSED)
1325 {
1326 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1327 }
1328
1329 /* The n operand of extrdi, which sets MB field. */
1330
1331 static uint64_t
1332 insert_erdn (uint64_t insn,
1333 int64_t value,
1334 ppc_cpu_t dialect,
1335 const char **errmsg)
1336 {
1337 return insert_mb6 (insn, -value, dialect, errmsg);
1338 }
1339
1340 static int64_t
1341 extract_erdn (uint64_t insn,
1342 ppc_cpu_t dialect,
1343 int *invalid)
1344 {
1345 return (~extract_mb6 (insn, dialect, invalid) & 63) + 1;
1346 }
1347
1348 /* The n operand of extldi, which sets ME field. */
1349
1350 static uint64_t
1351 insert_eldn (uint64_t insn,
1352 int64_t value,
1353 ppc_cpu_t dialect,
1354 const char **errmsg)
1355 {
1356 return insert_mb6 (insn, value - 1, dialect, errmsg);
1357 }
1358
1359 static int64_t
1360 extract_eldn (uint64_t insn,
1361 ppc_cpu_t dialect,
1362 int *invalid)
1363 {
1364 return extract_mb6 (insn, dialect, invalid) + 1;
1365 }
1366
1367 /* The n operand of clrrdi, which set ME field. */
1368
1369 static uint64_t
1370 insert_crdn (uint64_t insn,
1371 int64_t value,
1372 ppc_cpu_t dialect,
1373 const char **errmsg)
1374 {
1375 return insert_mb6 (insn, 63 - value, dialect, errmsg);
1376 }
1377
1378 static int64_t
1379 extract_crdn (uint64_t insn,
1380 ppc_cpu_t dialect,
1381 int *invalid)
1382 {
1383 return 63 - extract_mb6 (insn, dialect, invalid);
1384 }
1385
1386 /* The NB field in an X form instruction. The value 32 is stored as
1387 0. */
1388
1389 static int64_t
1390 extract_nb (uint64_t insn,
1391 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1392 int *invalid ATTRIBUTE_UNUSED)
1393 {
1394 int64_t ret;
1395
1396 ret = (insn >> 11) & 0x1f;
1397 if (ret == 0)
1398 ret = 32;
1399 return ret;
1400 }
1401
1402 /* The NB field in an lswi instruction, which has special value
1403 restrictions. The value 32 is stored as 0. */
1404
1405 static uint64_t
1406 insert_nbi (uint64_t insn,
1407 int64_t value,
1408 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1409 const char **errmsg ATTRIBUTE_UNUSED)
1410 {
1411 int64_t rtvalue = (insn >> 21) & 0x1f;
1412 int64_t ravalue = (insn >> 16) & 0x1f;
1413
1414 if (value == 0)
1415 value = 32;
1416 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1417 : ravalue))
1418 *errmsg = _("address register in load range");
1419 return insn | ((value & 0x1f) << 11);
1420 }
1421
1422 /* The NSI field in a D form instruction. This is the same as the SI
1423 field, only negated. The extraction function always marks it as
1424 invalid, since we never want to recognize an instruction which uses
1425 a field of this type. */
1426
1427 static uint64_t
1428 insert_nsi (uint64_t insn,
1429 int64_t value,
1430 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1431 const char **errmsg ATTRIBUTE_UNUSED)
1432 {
1433 return insn | (-value & 0xffff);
1434 }
1435
1436 static int64_t
1437 extract_nsi (uint64_t insn,
1438 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1439 int *invalid)
1440 {
1441 *invalid = 1;
1442 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1443 }
1444
1445 /* The 2-bit SC field in a SYNC or PL field in a WAIT instruction.
1446 For WAIT, some PL values are reserved:
1447 * Values 1, 2 and 3 are reserved. */
1448
1449 static uint64_t
1450 insert_pl (uint64_t insn,
1451 int64_t value,
1452 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1453 const char **errmsg)
1454 {
1455 /* For WAIT, some PL values are illegal. */
1456 if (((insn >> 1) & 0x3ff) == 30
1457 && value != 0)
1458 *errmsg = _("illegal PL operand value");
1459 return insn | ((value & 0x3) << 16);
1460 }
1461
1462 static int64_t
1463 extract_pl (uint64_t insn,
1464 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1465 int *invalid)
1466 {
1467 /* Missing optional operands have a value of zero. */
1468 if (*invalid < 0)
1469 return 0;
1470
1471 uint64_t value = (insn >> 16) & 0x3;
1472
1473 /* For WAIT, some PL values are illegal. */
1474 if (((insn >> 1) & 0x3ff) == 30
1475 && value != 0)
1476 *invalid = 1;
1477 return value;
1478 }
1479
1480 /* The 2-bit P field in a MMA XX2-form instruction. This is split. */
1481
1482 static uint64_t
1483 insert_p2 (uint64_t insn,
1484 int64_t value,
1485 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1486 const char **errmsg ATTRIBUTE_UNUSED)
1487 {
1488 return insn | ((value & 0x2) << 15) | ((value & 0x1) << 11);
1489 }
1490
1491 static int64_t
1492 extract_p2 (uint64_t insn,
1493 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1494 int *invalid ATTRIBUTE_UNUSED)
1495 {
1496 uint64_t value = ((insn >> 15) & 0x2) | ((insn >> 11) & 0x1);
1497 return value;
1498 }
1499
1500 /* The RA field in a D or X form instruction which is an updating
1501 load, which means that the RA field may not be zero and may not
1502 equal the RT field. */
1503
1504 static uint64_t
1505 insert_ral (uint64_t insn,
1506 int64_t value,
1507 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1508 const char **errmsg)
1509 {
1510 if (value == 0
1511 || (uint64_t) value == ((insn >> 21) & 0x1f))
1512 *errmsg = "invalid register operand when updating";
1513 return insn | ((value & 0x1f) << 16);
1514 }
1515
1516 static int64_t
1517 extract_ral (uint64_t insn,
1518 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1519 int *invalid)
1520 {
1521 int64_t rtvalue = (insn >> 21) & 0x1f;
1522 int64_t ravalue = (insn >> 16) & 0x1f;
1523
1524 if (rtvalue == ravalue || ravalue == 0)
1525 *invalid = 1;
1526 return ravalue;
1527 }
1528
1529 /* The RA field in an lmw instruction, which has special value
1530 restrictions. */
1531
1532 static uint64_t
1533 insert_ram (uint64_t insn,
1534 int64_t value,
1535 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1536 const char **errmsg)
1537 {
1538 if ((uint64_t) value >= ((insn >> 21) & 0x1f))
1539 *errmsg = _("index register in load range");
1540 return insn | ((value & 0x1f) << 16);
1541 }
1542
1543 static int64_t
1544 extract_ram (uint64_t insn,
1545 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1546 int *invalid)
1547 {
1548 uint64_t rtvalue = (insn >> 21) & 0x1f;
1549 uint64_t ravalue = (insn >> 16) & 0x1f;
1550
1551 if (ravalue >= rtvalue)
1552 *invalid = 1;
1553 return ravalue;
1554 }
1555
1556 /* The RA field in the DQ form lq or an lswx instruction, which have special
1557 value restrictions. */
1558
1559 static uint64_t
1560 insert_raq (uint64_t insn,
1561 int64_t value,
1562 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1563 const char **errmsg)
1564 {
1565 int64_t rtvalue = (insn >> 21) & 0x1f;
1566
1567 if (value == rtvalue)
1568 *errmsg = _("source and target register operands must be different");
1569 return insn | ((value & 0x1f) << 16);
1570 }
1571
1572 static int64_t
1573 extract_raq (uint64_t insn,
1574 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1575 int *invalid)
1576 {
1577 /* Missing optional operands have a value of zero. */
1578 if (*invalid < 0)
1579 return 0;
1580
1581 uint64_t rtvalue = (insn >> 21) & 0x1f;
1582 uint64_t ravalue = (insn >> 16) & 0x1f;
1583 if (ravalue == rtvalue)
1584 *invalid = 1;
1585 return ravalue;
1586 }
1587
1588 /* The RA field in a D or X form instruction which is an updating
1589 store or an updating floating point load, which means that the RA
1590 field may not be zero. */
1591
1592 static uint64_t
1593 insert_ras (uint64_t insn,
1594 int64_t value,
1595 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1596 const char **errmsg)
1597 {
1598 if (value == 0)
1599 *errmsg = _("invalid register operand when updating");
1600 return insn | ((value & 0x1f) << 16);
1601 }
1602
1603 static int64_t
1604 extract_ras (uint64_t insn,
1605 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1606 int *invalid)
1607 {
1608 uint64_t ravalue = (insn >> 16) & 0x1f;
1609
1610 if (ravalue == 0)
1611 *invalid = 1;
1612 return ravalue;
1613 }
1614
1615 /* The RS and RB fields in an X form instruction when they must be the same.
1616 This is used for extended mnemonics like mr. The extraction function
1617 enforces that the fields are the same. */
1618
1619 static uint64_t
1620 insert_rsb (uint64_t insn,
1621 int64_t value,
1622 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1623 const char **errmsg ATTRIBUTE_UNUSED)
1624 {
1625 value &= 0x1f;
1626 return insn | (value << 21) | (value << 11);
1627 }
1628
1629 static int64_t
1630 extract_rsb (uint64_t insn,
1631 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1632 int *invalid)
1633 {
1634 int64_t rs = (insn >> 21) & 0x1f;
1635 int64_t rb = (insn >> 11) & 0x1f;
1636
1637 if (rs != rb)
1638 *invalid = 1;
1639 return rs;
1640 }
1641
1642 /* The RB field in an lswx instruction, which has special value
1643 restrictions. */
1644
1645 static uint64_t
1646 insert_rbx (uint64_t insn,
1647 int64_t value,
1648 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1649 const char **errmsg)
1650 {
1651 int64_t rtvalue = (insn >> 21) & 0x1f;
1652
1653 if (value == rtvalue)
1654 *errmsg = _("source and target register operands must be different");
1655 return insn | ((value & 0x1f) << 11);
1656 }
1657
1658 static int64_t
1659 extract_rbx (uint64_t insn,
1660 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1661 int *invalid)
1662 {
1663 uint64_t rtvalue = (insn >> 21) & 0x1f;
1664 uint64_t rbvalue = (insn >> 11) & 0x1f;
1665
1666 if (rbvalue == rtvalue)
1667 *invalid = 1;
1668 return rbvalue;
1669 }
1670
1671 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1672 static uint64_t
1673 insert_sci8 (uint64_t insn,
1674 int64_t value,
1675 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1676 const char **errmsg)
1677 {
1678 uint64_t fill_scale = 0;
1679 uint64_t ui8 = value;
1680
1681 if ((ui8 & 0xffffff00) == 0)
1682 ;
1683 else if ((ui8 & 0xffffff00) == 0xffffff00)
1684 fill_scale = 0x400;
1685 else if ((ui8 & 0xffff00ff) == 0)
1686 {
1687 fill_scale = 1 << 8;
1688 ui8 >>= 8;
1689 }
1690 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1691 {
1692 fill_scale = 0x400 | (1 << 8);
1693 ui8 >>= 8;
1694 }
1695 else if ((ui8 & 0xff00ffff) == 0)
1696 {
1697 fill_scale = 2 << 8;
1698 ui8 >>= 16;
1699 }
1700 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1701 {
1702 fill_scale = 0x400 | (2 << 8);
1703 ui8 >>= 16;
1704 }
1705 else if ((ui8 & 0x00ffffff) == 0)
1706 {
1707 fill_scale = 3 << 8;
1708 ui8 >>= 24;
1709 }
1710 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1711 {
1712 fill_scale = 0x400 | (3 << 8);
1713 ui8 >>= 24;
1714 }
1715 else
1716 {
1717 *errmsg = _("illegal immediate value");
1718 ui8 = 0;
1719 }
1720
1721 return insn | fill_scale | (ui8 & 0xff);
1722 }
1723
1724 static int64_t
1725 extract_sci8 (uint64_t insn,
1726 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1727 int *invalid ATTRIBUTE_UNUSED)
1728 {
1729 int64_t fill = insn & 0x400;
1730 int64_t scale_factor = (insn & 0x300) >> 5;
1731 int64_t value = (insn & 0xff) << scale_factor;
1732
1733 if (fill != 0)
1734 value |= ~((int64_t) 0xff << scale_factor);
1735 return value;
1736 }
1737
1738 static uint64_t
1739 insert_sci8n (uint64_t insn,
1740 int64_t value,
1741 ppc_cpu_t dialect,
1742 const char **errmsg)
1743 {
1744 return insert_sci8 (insn, -value, dialect, errmsg);
1745 }
1746
1747 static int64_t
1748 extract_sci8n (uint64_t insn,
1749 ppc_cpu_t dialect,
1750 int *invalid)
1751 {
1752 return -extract_sci8 (insn, dialect, invalid);
1753 }
1754
1755 static uint64_t
1756 insert_oimm (uint64_t insn,
1757 int64_t value,
1758 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1759 const char **errmsg ATTRIBUTE_UNUSED)
1760 {
1761 return insn | (((value - 1) & 0x1f) << 4);
1762 }
1763
1764 static int64_t
1765 extract_oimm (uint64_t insn,
1766 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1767 int *invalid ATTRIBUTE_UNUSED)
1768 {
1769 return ((insn >> 4) & 0x1f) + 1;
1770 }
1771
1772 /* The n operand of rotrwi, sets SH = 32 - n. */
1773
1774 static uint64_t
1775 insert_rrwn (uint64_t insn,
1776 int64_t value,
1777 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1778 const char **errmsg ATTRIBUTE_UNUSED)
1779 {
1780 return insn | ((-value & 0x1f) << 11);
1781 }
1782
1783 static int64_t
1784 extract_rrwn (uint64_t insn,
1785 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1786 int *invalid ATTRIBUTE_UNUSED)
1787 {
1788 return 31 & -(insn >> 11);
1789 }
1790
1791 /* The n operand of slwi, sets SH = n and ME = 31 - n. */
1792
1793 static uint64_t
1794 insert_slwn (uint64_t insn,
1795 int64_t value,
1796 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1797 const char **errmsg ATTRIBUTE_UNUSED)
1798 {
1799 return insn | ((value & 0x1f) << 11) | ((~value & 0x1f) << 1);
1800 }
1801
1802 static int64_t
1803 extract_slwn (uint64_t insn,
1804 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1805 int *invalid)
1806 {
1807 int64_t sh = (insn >> 11) & 0x1f;
1808 int64_t nme = ~(insn >> 1) & 0x1f;
1809 if (sh != nme)
1810 *invalid = 1;
1811 return sh;
1812 }
1813
1814 /* The n operand of srwi, sets SH = 32 - n and MB = n. */
1815
1816 static uint64_t
1817 insert_srwn (uint64_t insn,
1818 int64_t value,
1819 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1820 const char **errmsg ATTRIBUTE_UNUSED)
1821 {
1822 return insn | ((-value & 0x1f) << 11) | ((value & 0x1f) << 6);
1823 }
1824
1825 static int64_t
1826 extract_srwn (uint64_t insn,
1827 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1828 int *invalid)
1829 {
1830 int64_t nsh = -(insn >> 11) & 0x1f;
1831 int64_t mb = (insn >> 6) & 0x1f;
1832 if (nsh != mb)
1833 *invalid = 1;
1834 return nsh;
1835 }
1836
1837 /* The SH field in an MD form instruction. This is split. */
1838
1839 static uint64_t
1840 insert_sh6 (uint64_t insn,
1841 int64_t value,
1842 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1843 const char **errmsg ATTRIBUTE_UNUSED)
1844 {
1845 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1846 }
1847
1848 static int64_t
1849 extract_sh6 (uint64_t insn,
1850 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1851 int *invalid ATTRIBUTE_UNUSED)
1852 {
1853 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1854 }
1855
1856 /* The n operand of rotrdi, which writes to SH field. */
1857
1858 static uint64_t
1859 insert_rrdn (uint64_t insn,
1860 int64_t value,
1861 ppc_cpu_t dialect,
1862 const char **errmsg)
1863 {
1864 return insert_sh6 (insn, -value, dialect, errmsg);
1865 }
1866
1867 static int64_t
1868 extract_rrdn (uint64_t insn,
1869 ppc_cpu_t dialect,
1870 int *invalid)
1871 {
1872 return -extract_sh6 (insn, dialect, invalid) & 63;
1873 }
1874
1875 /* The n operand of sldi, which writes to SH and ME fields. */
1876
1877 static uint64_t
1878 insert_sldn (uint64_t insn,
1879 int64_t value,
1880 ppc_cpu_t dialect,
1881 const char **errmsg)
1882 {
1883 insn = insert_sh6 (insn, value, dialect, errmsg);
1884 return insert_crdn (insn, value, dialect, errmsg);
1885 }
1886
1887 static int64_t
1888 extract_sldn (uint64_t insn,
1889 ppc_cpu_t dialect,
1890 int *invalid)
1891 {
1892 int64_t sh = extract_sh6 (insn, dialect, invalid);
1893 int64_t me = extract_crdn (insn, dialect, invalid);
1894 if (me != sh)
1895 *invalid = 1;
1896 return sh;
1897 }
1898
1899 /* The n operand of srdi, which writes to SH and MB fields. */
1900
1901 static uint64_t
1902 insert_srdn (uint64_t insn,
1903 int64_t value,
1904 ppc_cpu_t dialect,
1905 const char **errmsg)
1906 {
1907 insn = insert_rrdn (insn, value, dialect, errmsg);
1908 return insert_mb6 (insn, value, dialect, errmsg);
1909 }
1910
1911 static int64_t
1912 extract_srdn (uint64_t insn,
1913 ppc_cpu_t dialect,
1914 int *invalid)
1915 {
1916 int64_t sh = extract_rrdn (insn, dialect, invalid);
1917 int64_t mb = extract_mb6 (insn, dialect, invalid);
1918 if (mb != sh)
1919 *invalid = 1;
1920 return sh;
1921 }
1922
1923 /* The b operand of extrdi, which sets SH field. */
1924
1925 static uint64_t
1926 insert_erdb (uint64_t insn,
1927 int64_t value,
1928 ppc_cpu_t dialect,
1929 const char **errmsg)
1930 {
1931 int64_t n = extract_erdn (insn, dialect, NULL);
1932 return insert_sh6 (insn, value + n, dialect, errmsg);
1933 }
1934
1935 static int64_t
1936 extract_erdb (uint64_t insn,
1937 ppc_cpu_t dialect,
1938 int *invalid)
1939 {
1940 int64_t sh = extract_sh6 (insn, dialect, invalid);
1941 int64_t n = extract_erdn (insn, dialect, invalid);
1942 return (sh - n) & 63;
1943 }
1944
1945 /* The b and n operands of clrlsldi. */
1946
1947 static uint64_t
1948 insert_csldn (uint64_t insn,
1949 int64_t value,
1950 ppc_cpu_t dialect,
1951 const char **errmsg)
1952 {
1953 uint64_t mb6 = 0x3f << 5;
1954 int64_t b = extract_mb6 (insn, dialect, NULL);
1955 insn = insert_mb6 (insn & ~mb6, b - value, dialect, errmsg);
1956 return insert_sh6 (insn, value, dialect, errmsg);
1957 }
1958
1959 static int64_t
1960 extract_csldb (uint64_t insn,
1961 ppc_cpu_t dialect,
1962 int *invalid)
1963 {
1964 int64_t sh = extract_sh6 (insn, dialect, invalid);
1965 int64_t mb = extract_mb6 (insn, dialect, invalid);
1966 return (mb + sh) & 63;
1967 }
1968
1969 /* The b and n operands of insrdi. */
1970
1971 static uint64_t
1972 insert_irdb (uint64_t insn,
1973 int64_t value,
1974 ppc_cpu_t dialect,
1975 const char **errmsg)
1976 {
1977 uint64_t sh6 = (0x1f << 11) | 2;
1978 int64_t n = extract_sh6 (insn, dialect, NULL);
1979 insn = insert_sh6 (insn & ~sh6, -(value + n), dialect, errmsg);
1980 return insert_mb6 (insn, value, dialect, errmsg);
1981 }
1982
1983 static int64_t
1984 extract_irdn (uint64_t insn,
1985 ppc_cpu_t dialect,
1986 int *invalid)
1987 {
1988 int64_t sh = extract_sh6 (insn, dialect, invalid);
1989 int64_t mb = extract_mb6 (insn, dialect, invalid);
1990 return (~(mb + sh) & 63) + 1;
1991 }
1992
1993 /* The SPR field in an XFX form instruction. This is flipped--the
1994 lower 5 bits are stored in the upper 5 and vice- versa. */
1995
1996 static uint64_t
1997 insert_spr (uint64_t insn,
1998 int64_t value,
1999 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2000 const char **errmsg ATTRIBUTE_UNUSED)
2001 {
2002 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2003 }
2004
2005 static int64_t
2006 extract_spr (uint64_t insn,
2007 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2008 int *invalid ATTRIBUTE_UNUSED)
2009 {
2010 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2011 }
2012
2013 /* Some dialects have 8 [DI]BAT registers instead of the standard 4. */
2014 #define ALLOW8_BAT (PPC_OPCODE_750)
2015
2016 static uint64_t
2017 insert_sprbat (uint64_t insn,
2018 int64_t value,
2019 ppc_cpu_t dialect,
2020 const char **errmsg)
2021 {
2022 if ((uint64_t) value > 7
2023 || ((uint64_t) value > 3 && (dialect & ALLOW8_BAT) == 0))
2024 *errmsg = _("invalid bat number");
2025
2026 /* If this is [di]bat4..7 then use spr 560..575, otherwise 528..543. */
2027 if ((uint64_t) value > 3)
2028 value = ((value & 3) << 6) | 1;
2029 else
2030 value = value << 6;
2031
2032 return insn | (value << 11);
2033 }
2034
2035 static int64_t
2036 extract_sprbat (uint64_t insn,
2037 ppc_cpu_t dialect,
2038 int *invalid)
2039 {
2040 uint64_t val = (insn >> 17) & 0x3;
2041
2042 val = val + ((insn >> 9) & 0x4);
2043 if (val > 3 && (dialect & ALLOW8_BAT) == 0)
2044 *invalid = 1;
2045 return val;
2046 }
2047
2048 /* Some dialects have 8 SPRG registers instead of the standard 4. */
2049 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
2050
2051 static uint64_t
2052 insert_sprg (uint64_t insn,
2053 int64_t value,
2054 ppc_cpu_t dialect,
2055 const char **errmsg)
2056 {
2057 if ((uint64_t) value > 7
2058 || ((uint64_t) value > 3 && (dialect & ALLOW8_SPRG) == 0))
2059 *errmsg = _("invalid sprg number");
2060
2061 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2062 user mode. Anything else must use spr 272..279. */
2063 if ((uint64_t) value <= 3 || (insn & 0x100) != 0)
2064 value |= 0x10;
2065
2066 return insn | ((value & 0x17) << 16);
2067 }
2068
2069 static int64_t
2070 extract_sprg (uint64_t insn,
2071 ppc_cpu_t dialect,
2072 int *invalid)
2073 {
2074 uint64_t val = (insn >> 16) & 0x1f;
2075
2076 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
2077 If not BOOKE, 405 or VLE, then both use only 272..275. */
2078 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
2079 || (val - 0x10 > 7 && (insn & 0x100) != 0)
2080 || val <= 3
2081 || (val & 8) != 0)
2082 *invalid = 1;
2083 return val & 7;
2084 }
2085
2086 /* The TBR field in an XFX instruction. This is just like SPR, but it
2087 is optional. */
2088
2089 static uint64_t
2090 insert_tbr (uint64_t insn,
2091 int64_t value,
2092 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2093 const char **errmsg)
2094 {
2095 if (value != 268 && value != 269)
2096 *errmsg = _("invalid tbr number");
2097 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2098 }
2099
2100 static int64_t
2101 extract_tbr (uint64_t insn,
2102 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2103 int *invalid)
2104 {
2105 /* Missing optional operands have a value of 268. */
2106 if (*invalid < 0)
2107 return 268;
2108
2109 int64_t ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2110 if (ret != 268 && ret != 269)
2111 *invalid = 1;
2112 return ret;
2113 }
2114
2115 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2116
2117 static uint64_t
2118 insert_xt6 (uint64_t insn,
2119 int64_t value,
2120 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2121 const char **errmsg ATTRIBUTE_UNUSED)
2122 {
2123 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2124 }
2125
2126 static int64_t
2127 extract_xt6 (uint64_t insn,
2128 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2129 int *invalid ATTRIBUTE_UNUSED)
2130 {
2131 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2132 }
2133
2134 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
2135 static uint64_t
2136 insert_xtq6 (uint64_t insn,
2137 int64_t value,
2138 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2139 const char **errmsg ATTRIBUTE_UNUSED)
2140 {
2141 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2142 }
2143
2144 static int64_t
2145 extract_xtq6 (uint64_t insn,
2146 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2147 int *invalid ATTRIBUTE_UNUSED)
2148 {
2149 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2150 }
2151
2152 /* The 5-bit XAp field in an XX3 form instruction. This is split. */
2153
2154 static uint64_t
2155 insert_xa5 (uint64_t insn,
2156 int64_t value,
2157 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2158 const char **errmsg ATTRIBUTE_UNUSED)
2159 {
2160 return insn | ((value & 0x1e) << 16) | ((value & 0x20) >> 3);
2161 }
2162
2163 static int64_t
2164 extract_xa5 (uint64_t insn,
2165 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2166 int *invalid ATTRIBUTE_UNUSED)
2167 {
2168 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1e);
2169 }
2170
2171 /* The XA field in an XX3 form instruction. This is split. */
2172
2173 static uint64_t
2174 insert_xa6 (uint64_t insn,
2175 int64_t value,
2176 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2177 const char **errmsg ATTRIBUTE_UNUSED)
2178 {
2179 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2180 }
2181
2182 static int64_t
2183 extract_xa6 (uint64_t insn,
2184 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2185 int *invalid ATTRIBUTE_UNUSED)
2186 {
2187 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2188 }
2189
2190 /* The XA field in an MMA XX3 form instruction. This is split
2191 and must not overlap with the ACC operand. */
2192
2193 static uint64_t
2194 insert_xa6a (uint64_t insn,
2195 int64_t value,
2196 ppc_cpu_t dialect,
2197 const char **errmsg)
2198 {
2199 int64_t acc = (insn >> 23) & 0x7;
2200 /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions. */
2201 if ((dialect & PPC_OPCODE_FUTURE) == 0
2202 && (value >> 2) == acc)
2203 *errmsg = _("VSR overlaps ACC operand");
2204 return insert_xa6 (insn, value, dialect, errmsg);
2205 }
2206
2207 static int64_t
2208 extract_xa6a (uint64_t insn,
2209 ppc_cpu_t dialect,
2210 int *invalid)
2211 {
2212 int64_t acc = (insn >> 23) & 0x7;
2213 int64_t value = extract_xa6 (insn, dialect, invalid);
2214 /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions. */
2215 if ((dialect & PPC_OPCODE_FUTURE) == 0
2216 && (value >> 2) == acc)
2217 *invalid = 1;
2218 return value;
2219 }
2220
2221 /* The 5-bit XB field in an XX3 form instruction. This is split. */
2222
2223 static uint64_t
2224 insert_xb5 (uint64_t insn,
2225 int64_t value,
2226 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2227 const char **errmsg ATTRIBUTE_UNUSED)
2228 {
2229 return insn | ((value & 0x1e) << 11) | ((value & 0x20) >> 4);
2230 }
2231
2232 static int64_t
2233 extract_xb5 (uint64_t insn,
2234 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2235 int *invalid ATTRIBUTE_UNUSED)
2236 {
2237 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1e);
2238 }
2239 /* The XB field in an XX3 form instruction. This is split. */
2240
2241 static uint64_t
2242 insert_xb6 (uint64_t insn,
2243 int64_t value,
2244 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2245 const char **errmsg ATTRIBUTE_UNUSED)
2246 {
2247 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2248 }
2249
2250 static int64_t
2251 extract_xb6 (uint64_t insn,
2252 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2253 int *invalid ATTRIBUTE_UNUSED)
2254 {
2255 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2256 }
2257
2258 /* The XB field in an MMA XX3 form instruction. This is split
2259 and must not overlap with the ACC operand. */
2260
2261 static uint64_t
2262 insert_xb6a (uint64_t insn,
2263 int64_t value,
2264 ppc_cpu_t dialect,
2265 const char **errmsg)
2266 {
2267 int64_t acc = (insn >> 23) & 0x7;
2268 /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions. */
2269 if ((dialect & PPC_OPCODE_FUTURE) == 0
2270 && (value >> 2) == acc)
2271 *errmsg = _("VSR overlaps ACC operand");
2272 return insert_xb6 (insn, value, dialect, errmsg);
2273 }
2274
2275 static int64_t
2276 extract_xb6a (uint64_t insn,
2277 ppc_cpu_t dialect,
2278 int *invalid)
2279 {
2280 int64_t acc = (insn >> 23) & 0x7;
2281 int64_t value = extract_xb6 (insn, dialect, invalid);
2282 /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions. */
2283 if ((dialect & PPC_OPCODE_FUTURE) == 0
2284 && (value >> 2) == acc)
2285 *invalid = 1;
2286 return value;
2287 }
2288
2289 /* The XA and XB fields in an XX3 form instruction when they must be the same.
2290 This is used for extended mnemonics like xvmovdp. The extraction function
2291 enforces that the fields are the same. */
2292
2293 static uint64_t
2294 insert_xab6 (uint64_t insn,
2295 int64_t value,
2296 ppc_cpu_t dialect,
2297 const char **errmsg)
2298 {
2299 return insert_xa6 (insn, value, dialect, errmsg)
2300 | insert_xb6 (insn, value, dialect, errmsg);
2301 }
2302
2303 static int64_t
2304 extract_xab6 (uint64_t insn,
2305 ppc_cpu_t dialect,
2306 int *invalid)
2307 {
2308 int64_t xa6 = extract_xa6 (insn, dialect, invalid);
2309 int64_t xb6 = extract_xb6 (insn, dialect, invalid);
2310
2311 if (xa6 != xb6)
2312 *invalid = 1;
2313 return xa6;
2314 }
2315
2316 /* The XC field in an XX4 form instruction. This is split. */
2317
2318 static uint64_t
2319 insert_xc6 (uint64_t insn,
2320 int64_t value,
2321 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2322 const char **errmsg ATTRIBUTE_UNUSED)
2323 {
2324 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2325 }
2326
2327 static int64_t
2328 extract_xc6 (uint64_t insn,
2329 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2330 int *invalid ATTRIBUTE_UNUSED)
2331 {
2332 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2333 }
2334
2335 /* The split XTp and XSp field in a vector paired insn. */
2336
2337 static uint64_t
2338 insert_xtp (uint64_t insn,
2339 int64_t value,
2340 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2341 const char **errmsg ATTRIBUTE_UNUSED)
2342 {
2343 return insn | ((value & 0x1e) << 21) | ((value & 0x20) << (21 - 5));
2344 }
2345
2346 static int64_t
2347 extract_xtp (uint64_t insn,
2348 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2349 int *invalid ATTRIBUTE_UNUSED)
2350 {
2351 return ((insn >> (21 - 5)) & 0x20) | ((insn >> 21) & 0x1e);
2352 }
2353
2354 /* The split XT field in a vector splat insn. */
2355
2356 static uint64_t
2357 insert_xts (uint64_t insn,
2358 int64_t value,
2359 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2360 const char **errmsg ATTRIBUTE_UNUSED)
2361 {
2362 return insn | ((value & 0x1f) << 21) | ((value & 0x20) << (16 - 5));
2363 }
2364
2365 static int64_t
2366 extract_xts (uint64_t insn,
2367 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2368 int *invalid ATTRIBUTE_UNUSED)
2369 {
2370 return ((insn >> (16 - 5)) & 0x20) | ((insn >> 21) & 0x1f);
2371 }
2372
2373 static uint64_t
2374 insert_dm (uint64_t insn,
2375 int64_t value,
2376 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2377 const char **errmsg)
2378 {
2379 if (value != 0 && value != 1)
2380 *errmsg = _("invalid constant");
2381 return insn | (((value) ? 3 : 0) << 8);
2382 }
2383
2384 static int64_t
2385 extract_dm (uint64_t insn,
2386 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2387 int *invalid)
2388 {
2389 int64_t value = (insn >> 8) & 3;
2390 if (value != 0 && value != 3)
2391 *invalid = 1;
2392 return (value) ? 1 : 0;
2393 }
2394
2395 /* The VLESIMM field in an I16A form instruction. This is split. */
2396
2397 static uint64_t
2398 insert_vlesi (uint64_t insn,
2399 int64_t value,
2400 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2401 const char **errmsg ATTRIBUTE_UNUSED)
2402 {
2403 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2404 }
2405
2406 static int64_t
2407 extract_vlesi (uint64_t insn,
2408 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2409 int *invalid ATTRIBUTE_UNUSED)
2410 {
2411 int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2412 value = (value ^ 0x8000) - 0x8000;
2413 return value;
2414 }
2415
2416 static uint64_t
2417 insert_vlensi (uint64_t insn,
2418 int64_t value,
2419 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2420 const char **errmsg ATTRIBUTE_UNUSED)
2421 {
2422 value = -value;
2423 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2424 }
2425 static int64_t
2426 extract_vlensi (uint64_t insn,
2427 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2428 int *invalid)
2429 {
2430 int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2431 value = (value ^ 0x8000) - 0x8000;
2432 /* Don't use for disassembly. */
2433 *invalid = 1;
2434 return -value;
2435 }
2436
2437 /* The VLEUIMM field in an I16A form instruction. This is split. */
2438
2439 static uint64_t
2440 insert_vleui (uint64_t insn,
2441 int64_t value,
2442 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2443 const char **errmsg ATTRIBUTE_UNUSED)
2444 {
2445 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2446 }
2447
2448 static int64_t
2449 extract_vleui (uint64_t insn,
2450 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2451 int *invalid ATTRIBUTE_UNUSED)
2452 {
2453 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2454 }
2455
2456 /* The VLEUIMML field in an I16L form instruction. This is split. */
2457
2458 static uint64_t
2459 insert_vleil (uint64_t insn,
2460 int64_t value,
2461 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2462 const char **errmsg ATTRIBUTE_UNUSED)
2463 {
2464 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2465 }
2466
2467 static int64_t
2468 extract_vleil (uint64_t insn,
2469 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2470 int *invalid ATTRIBUTE_UNUSED)
2471 {
2472 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2473 }
2474
2475 static uint64_t
2476 insert_evuimm1_ex0 (uint64_t insn,
2477 int64_t value,
2478 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2479 const char **errmsg)
2480 {
2481 if (value <= 0 || value > 0x1f)
2482 *errmsg = _("UIMM = 00000 is illegal");
2483 return insn | ((value & 0x1f) << 11);
2484 }
2485
2486 static int64_t
2487 extract_evuimm1_ex0 (uint64_t insn,
2488 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2489 int *invalid)
2490 {
2491 int64_t value = ((insn >> 11) & 0x1f);
2492 if (value == 0)
2493 *invalid = 1;
2494
2495 return value;
2496 }
2497
2498 static uint64_t
2499 insert_evuimm2_ex0 (uint64_t insn,
2500 int64_t value,
2501 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2502 const char **errmsg)
2503 {
2504 if (value <= 0 || value > 0x3e)
2505 *errmsg = _("UIMM = 00000 is illegal");
2506 return insn | ((value & 0x3e) << 10);
2507 }
2508
2509 static int64_t
2510 extract_evuimm2_ex0 (uint64_t insn,
2511 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2512 int *invalid)
2513 {
2514 int64_t value = ((insn >> 10) & 0x3e);
2515 if (value == 0)
2516 *invalid = 1;
2517
2518 return value;
2519 }
2520
2521 static uint64_t
2522 insert_evuimm4_ex0 (uint64_t insn,
2523 int64_t value,
2524 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2525 const char **errmsg)
2526 {
2527 if (value <= 0 || value > 0x7c)
2528 *errmsg = _("UIMM = 00000 is illegal");
2529 return insn | ((value & 0x7c) << 9);
2530 }
2531
2532 static int64_t
2533 extract_evuimm4_ex0 (uint64_t insn,
2534 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2535 int *invalid)
2536 {
2537 int64_t value = ((insn >> 9) & 0x7c);
2538 if (value == 0)
2539 *invalid = 1;
2540
2541 return value;
2542 }
2543
2544 static uint64_t
2545 insert_evuimm8_ex0 (uint64_t insn,
2546 int64_t value,
2547 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2548 const char **errmsg)
2549 {
2550 if (value <= 0 || value > 0xf8)
2551 *errmsg = _("UIMM = 00000 is illegal");
2552 return insn | ((value & 0xf8) << 8);
2553 }
2554
2555 static int64_t
2556 extract_evuimm8_ex0 (uint64_t insn,
2557 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2558 int *invalid)
2559 {
2560 int64_t value = ((insn >> 8) & 0xf8);
2561 if (value == 0)
2562 *invalid = 1;
2563
2564 return value;
2565 }
2566
2567 static uint64_t
2568 insert_evuimm_lt8 (uint64_t insn,
2569 int64_t value,
2570 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2571 const char **errmsg)
2572 {
2573 if (value < 0 || value > 7)
2574 *errmsg = _("UIMM values >7 are illegal");
2575 return insn | ((value & 0x7) << 11);
2576 }
2577
2578 static int64_t
2579 extract_evuimm_lt8 (uint64_t insn,
2580 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2581 int *invalid)
2582 {
2583 int64_t value = ((insn >> 11) & 0x1f);
2584 if (value > 7)
2585 *invalid = 1;
2586
2587 return value;
2588 }
2589
2590 static uint64_t
2591 insert_evuimm_lt16 (uint64_t insn,
2592 int64_t value,
2593 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2594 const char **errmsg)
2595 {
2596 if (value < 0 || value > 15)
2597 *errmsg = _("UIMM values >15 are illegal");
2598 return insn | ((value & 0xf) << 11);
2599 }
2600
2601 static int64_t
2602 extract_evuimm_lt16 (uint64_t insn,
2603 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2604 int *invalid)
2605 {
2606 int64_t value = ((insn >> 11) & 0x1f);
2607 if (value > 15)
2608 *invalid = 1;
2609
2610 return value;
2611 }
2612
2613 static uint64_t
2614 insert_rD_rS_even (uint64_t insn,
2615 int64_t value,
2616 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2617 const char **errmsg)
2618 {
2619 if ((value & 0x1) != 0)
2620 *errmsg = _("GPR odd is illegal");
2621 return insn | ((value & 0x1e) << 21);
2622 }
2623
2624 static int64_t
2625 extract_rD_rS_even (uint64_t insn,
2626 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2627 int *invalid)
2628 {
2629 int64_t value = ((insn >> 21) & 0x1f);
2630 if ((value & 0x1) != 0)
2631 *invalid = 1;
2632
2633 return value;
2634 }
2635
2636 static uint64_t
2637 insert_off_lsp (uint64_t insn,
2638 int64_t value,
2639 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2640 const char **errmsg)
2641 {
2642 if (value <= 0 || value > 0x3)
2643 *errmsg = _("invalid offset");
2644 return insn | (value & 0x3);
2645 }
2646
2647 static int64_t
2648 extract_off_lsp (uint64_t insn,
2649 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2650 int *invalid)
2651 {
2652 int64_t value = (insn & 0x3);
2653 if (value == 0)
2654 *invalid = 1;
2655
2656 return value;
2657 }
2658
2659 static uint64_t
2660 insert_off_spe2 (uint64_t insn,
2661 int64_t value,
2662 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2663 const char **errmsg)
2664 {
2665 if (value <= 0 || value > 0x7)
2666 *errmsg = _("invalid offset");
2667 return insn | (value & 0x7);
2668 }
2669
2670 static int64_t
2671 extract_off_spe2 (uint64_t insn,
2672 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2673 int *invalid)
2674 {
2675 int64_t value = (insn & 0x7);
2676 if (value == 0)
2677 *invalid = 1;
2678
2679 return value;
2680 }
2681
2682 static uint64_t
2683 insert_Ddd (uint64_t insn,
2684 int64_t value,
2685 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2686 const char **errmsg)
2687 {
2688 if (value < 0 || value > 0x7)
2689 *errmsg = _("invalid Ddd value");
2690 return insn | ((value & 0x3) << 11) | ((value & 0x4) >> 2);
2691 }
2692
2693 static int64_t
2694 extract_Ddd (uint64_t insn,
2695 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2696 int *invalid ATTRIBUTE_UNUSED)
2697 {
2698 return ((insn >> 11) & 0x3) | ((insn << 2) & 0x4);
2699 }
2700
2701 static uint64_t
2702 insert_sxl (uint64_t insn,
2703 int64_t value,
2704 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2705 const char **errmsg ATTRIBUTE_UNUSED)
2706 {
2707 return insn | ((value & 0x1) << 11);
2708 }
2709
2710 static int64_t
2711 extract_sxl (uint64_t insn,
2712 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2713 int *invalid)
2714 {
2715 /* Missing optional operands have a value of one. */
2716 if (*invalid < 0)
2717 return 1;
2718 return (insn >> 11) & 0x1;
2719 }
2720
2721 /* The list of embedded processors that use the embedded operand ordering
2722 for the 3 operand dcbt and dcbtst instructions. */
2723 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
2724 | PPC_OPCODE_A2)
2725
2726 /* ISA 2.03 and later specify extended mnemonics dcbtct, dcbtds, and
2727 dcbtstct, dcbtstds with a note saying these should be used in new
2728 programs rather than the base mnemonics "so that it can be coded
2729 with TH as the last operand for all categories". For that reason
2730 the extended mnemonics are enabled in the assembler for the
2731 embedded processors, but not for the disassembler so as to display
2732 the embedded dcbt or dcbtst expected form with TH first for
2733 embedded programmers. */
2734
2735 static uint64_t
2736 insert_thct (uint64_t insn,
2737 int64_t value,
2738 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2739 const char **errmsg)
2740 {
2741 if ((uint64_t) value > 7)
2742 *errmsg = _("invalid TH value");
2743 return insn | ((value & 7) << 21);
2744 }
2745
2746 static int64_t
2747 extract_thct (uint64_t insn,
2748 ppc_cpu_t dialect,
2749 int *invalid)
2750 {
2751 /* Missing optional operands have a value of 0. */
2752 if (*invalid < 0)
2753 return 0;
2754
2755 int64_t value = (insn >> 21) & 0x1f;
2756 if (value > 7 || (dialect & DCBT_EO) != 0)
2757 *invalid = 1;
2758
2759 return value;
2760 }
2761
2762 static uint64_t
2763 insert_thds (uint64_t insn,
2764 int64_t value,
2765 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2766 const char **errmsg)
2767 {
2768 if (value < 8 || value > 15)
2769 *errmsg = _("invalid TH value");
2770 return insn | ((value & 0x1f) << 21);
2771 }
2772
2773 static int64_t
2774 extract_thds (uint64_t insn,
2775 ppc_cpu_t dialect,
2776 int *invalid)
2777 {
2778 /* Missing optional operands have a value of 8. */
2779 if (*invalid < 0)
2780 return 8;
2781
2782 int64_t value = (insn >> 21) & 0x1f;
2783 if (value < 8 || value > 15 || (dialect & DCBT_EO) != 0)
2784 *invalid = 1;
2785
2786 return value;
2787 }
2788 \f
2789 /* The operands table.
2790
2791 The fields are bitm, shift, insert, extract, flags.
2792
2793 We used to put parens around the various additions, like the one
2794 for BA just below. However, that caused trouble with feeble
2795 compilers with a limit on depth of a parenthesized expression, like
2796 (reportedly) the compiler in Microsoft Developer Studio 5. So we
2797 omit the parens, since the macros are never used in a context where
2798 the addition will be ambiguous. */
2799
2800 const struct powerpc_operand powerpc_operands[] =
2801 {
2802 /* The zero index is used to indicate the end of the list of
2803 operands. */
2804 #define UNUSED 0
2805 { 0, 0, NULL, NULL, 0 },
2806
2807 /* The BA field in an XL form instruction. */
2808 #define BA UNUSED + 1
2809 /* The BI field in a B form or XL form instruction. */
2810 #define BI BA
2811 #define BI_MASK (0x1f << 16)
2812 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
2813
2814 /* The BT, BA and BB fields in a XL form instruction when they must all
2815 be the same. */
2816 #define BTAB BA + 1
2817 { 0x1f, 21, insert_btab, extract_btab, PPC_OPERAND_CR_BIT },
2818
2819 /* The BB field in an XL form instruction. */
2820 #define BB BTAB + 1
2821 #define BB_MASK (0x1f << 11)
2822 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
2823
2824 /* The BA and BB fields in a XL form instruction when they must be
2825 the same. */
2826 #define BAB BB + 1
2827 { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_CR_BIT },
2828
2829 /* The VRA and VRB fields in a VX form instruction when they must be the same.
2830 This is used for extended mnemonics like vmr. */
2831 #define VAB BAB + 1
2832 { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_VR },
2833
2834 /* The RA and RB fields in a VX form instruction when they must be the same.
2835 This is used for extended mnemonics like evmr. */
2836 #define RAB VAB + 1
2837 { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_GPR },
2838
2839 #define BC RAB + 1
2840 { 0x1f, 6, NULL, NULL, PPC_OPERAND_CR_BIT },
2841
2842 /* The BD field in a B form instruction. The lower two bits are
2843 forced to zero. */
2844 #define BD BC + 1
2845 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
2846
2847 /* The BD field in a B form instruction when absolute addressing is
2848 used. */
2849 #define BDA BD + 1
2850 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
2851
2852 /* The BD field in a B form instruction when the - modifier is used.
2853 This sets the y bit of the BO field appropriately. */
2854 #define BDM BDA + 1
2855 { 0xfffc, 0, insert_bdm, extract_bdm,
2856 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
2857
2858 /* The BD field in a B form instruction when the - modifier is used
2859 and absolute address is used. */
2860 #define BDMA BDM + 1
2861 { 0xfffc, 0, insert_bdm, extract_bdm,
2862 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
2863
2864 /* The BD field in a B form instruction when the + modifier is used.
2865 This sets the y bit of the BO field appropriately. */
2866 #define BDP BDMA + 1
2867 { 0xfffc, 0, insert_bdp, extract_bdp,
2868 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
2869
2870 /* The BD field in a B form instruction when the + modifier is used
2871 and absolute addressing is used. */
2872 #define BDPA BDP + 1
2873 { 0xfffc, 0, insert_bdp, extract_bdp,
2874 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
2875
2876 /* The BF field in an X or XL form instruction. */
2877 #define BF BDPA + 1
2878 /* The CRFD field in an X form instruction. */
2879 #define CRFD BF
2880 /* The CRD field in an XL form instruction. */
2881 #define CRD BF
2882 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
2883
2884 /* The BF field in an X or XL form instruction. */
2885 #define BFF BF + 1
2886 { 0x7, 23, NULL, NULL, 0 },
2887
2888 /* The ACC field in a VSX ACC 8LS:D-form instruction. */
2889 #define ACC BFF + 1
2890 { 0x7, 23, NULL, NULL, PPC_OPERAND_ACC },
2891
2892 /* The DMR field in a MMA instruction. */
2893 #define DMR ACC + 1
2894 { 0x7, 23, NULL, NULL, PPC_OPERAND_DMR },
2895
2896 /* The second DMR field in a two DMR operand MMA instruction. */
2897 #define DMRAB DMR + 1
2898 { 0x7, 13, NULL, NULL, PPC_OPERAND_DMR },
2899
2900 /* An optional BF field. This is used for comparison instructions,
2901 in which an omitted BF field is taken as zero. */
2902 #define OBF DMRAB + 1
2903 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
2904
2905 /* The BFA field in an X or XL form instruction. */
2906 #define BFA OBF + 1
2907 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
2908
2909 /* The BO field in a B form instruction. Certain values are
2910 illegal. */
2911 #define BO BFA + 1
2912 #define BO_MASK (0x1f << 21)
2913 { 0x1f, 21, insert_bo, extract_bo, 0 },
2914
2915 /* The BO field in a B form instruction when the - modifier is used. */
2916 #define BOM BO + 1
2917 { 0x1f, 21, insert_bom, extract_bom, 0 },
2918
2919 /* The BO field in a B form instruction when the + modifier is used. */
2920 #define BOP BOM + 1
2921 { 0x1f, 21, insert_bop, extract_bop, 0 },
2922
2923 /* The RM field in an X form instruction. */
2924 #define RM BOP + 1
2925 #define DD RM
2926 #define mo1 RM
2927 { 0x3, 11, NULL, NULL, 0 },
2928
2929 #define BH RM + 1
2930 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
2931
2932 /* The BT field in an X or XL form instruction. */
2933 #define BT BH + 1
2934 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
2935
2936 /* The BT field in a mtfsb0 or mtfsb1 instruction. */
2937 #define BTF BT + 1
2938 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG },
2939
2940 /* The BI16 field in a BD8 form instruction. */
2941 #define BI16 BTF + 1
2942 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
2943
2944 /* The BI32 field in a BD15 form instruction. */
2945 #define BI32 BI16 + 1
2946 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
2947
2948 /* The BO32 field in a BD15 form instruction. */
2949 #define BO32 BI32 + 1
2950 { 0x3, 20, NULL, NULL, 0 },
2951
2952 /* The B8 field in a BD8 form instruction. */
2953 #define B8 BO32 + 1
2954 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
2955
2956 /* The B15 field in a BD15 form instruction. The lowest bit is
2957 forced to zero. */
2958 #define B15 B8 + 1
2959 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
2960
2961 /* The B24 field in a BD24 form instruction. The lowest bit is
2962 forced to zero. */
2963 #define B24 B15 + 1
2964 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
2965
2966 /* The condition register number portion of the BI field in a B form
2967 or XL form instruction. This is used for the extended
2968 conditional branch mnemonics, which set the lower two bits of the
2969 BI field. This field is optional. */
2970 #define CR B24 + 1
2971 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
2972
2973 /* The CRB field in an X form instruction. */
2974 #define CRB CR + 1
2975 /* The MB field in an M form instruction. */
2976 #define MB CRB
2977 #define MB_MASK (0x1f << 6)
2978 { 0x1f, 6, NULL, NULL, 0 },
2979
2980 /* The CRD32 field in an XL form instruction. */
2981 #define CRD32 CRB + 1
2982 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
2983
2984 /* The CRFS field in an X form instruction. */
2985 #define CRFS CRD32 + 1
2986 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
2987
2988 #define CRS CRFS + 1
2989 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
2990
2991 /* The CT field in an X form instruction. */
2992 #define CT CRS + 1
2993 /* The MO field in an mbar instruction. */
2994 #define MO CT
2995 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
2996
2997 /* The TH field in dcbtct. */
2998 #define THCT CT + 1
2999 { 0x1f, 21, insert_thct, extract_thct, PPC_OPERAND_OPTIONAL },
3000
3001 /* The TH field in dcbtds. */
3002 #define THDS THCT + 1
3003 { 0x1f, 21, insert_thds, extract_thds, PPC_OPERAND_OPTIONAL },
3004
3005 /* The D field in a D form instruction. This is a displacement off
3006 a register, and implies that the next operand is a register in
3007 parentheses. */
3008 #define D THDS + 1
3009 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
3010
3011 /* The D8 field in a D form instruction. This is a displacement off
3012 a register, and implies that the next operand is a register in
3013 parentheses. */
3014 #define D8 D + 1
3015 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
3016
3017 /* The DCMX field in an X form instruction. */
3018 #define DCMX D8 + 1
3019 { 0x7f, 16, NULL, NULL, 0 },
3020
3021 /* The split DCMX field in an X form instruction. */
3022 #define DCMXS DCMX + 1
3023 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
3024
3025 /* The DQ field in a DQ form instruction. This is like D, but the
3026 lower four bits are forced to zero. */
3027 #define DQ DCMXS + 1
3028 { 0xfff0, 0, NULL, NULL,
3029 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
3030
3031 /* The DS field in a DS form instruction. This is like D, but the
3032 lower two bits are forced to zero. */
3033 #define DS DQ + 1
3034 { 0xfffc, 0, NULL, NULL,
3035 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
3036
3037 /* The D field in an 8-byte D form prefix instruction. This is a displacement
3038 off a register, and implies that the next operand is a register in
3039 parentheses. */
3040 #define D34 DS + 1
3041 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_d34, extract_d34,
3042 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
3043
3044 /* The SI field in an 8-byte D form prefix instruction. */
3045 #define SI34 D34 + 1
3046 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_d34, extract_d34, PPC_OPERAND_SIGNED },
3047
3048 /* The NSI field in an 8-byte D form prefix instruction. This is the
3049 same as the SI34 field, only negated. */
3050 #define NSI34 SI34 + 1
3051 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34,
3052 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
3053
3054 /* The IMM32 field in a vector splat immediate prefix instruction. */
3055 #define IMM32 NSI34 + 1
3056 { 0xffffffff, PPC_OPSHIFT_INV, insert_imm32, extract_imm32, 0},
3057
3058 /* The UIM field in a vector permute extended prefix instruction. */
3059 #define UIM3 IMM32 + 1
3060 { 0x7, 32, NULL, NULL, 0},
3061
3062 /* The UIM field in a vector eval prefix instruction. */
3063 #define UIM8 UIM3 + 1
3064 { 0xff, 32, NULL, NULL, 0},
3065
3066 /* The IX field in xxsplti32dx. */
3067 #define IX UIM8 + 1
3068 { 0x1, 17, NULL, NULL, 0 },
3069
3070 /* The PMSK field in GER rank 8 prefix instructions. */
3071 #define PMSK8 IX + 1
3072 { 0xff, 40, NULL, NULL, 0 },
3073
3074 /* The PMSK field in GER rank 4 prefix instructions. */
3075 #define PMSK4 PMSK8 + 1
3076 { 0xf, 44, NULL, NULL, 0 },
3077
3078 /* The PMSK field in GER rank 2 prefix instructions. */
3079 #define PMSK2 PMSK4 + 1
3080 { 0x3, 46, NULL, NULL, 0 },
3081
3082 /* The XMSK field in GER prefix instructions. */
3083 #define XMSK PMSK2 + 1
3084 { 0xf, 36, NULL, NULL, 0 },
3085
3086 /* The XMSK field in GERX prefix instructions. */
3087 #define XMSK8 XMSK + 1
3088 { 0xff, 36, NULL, NULL, 0 },
3089
3090 /* The YMSK field in GER prefix instructions. */
3091 #define YMSK XMSK8 + 1
3092 { 0xf, 32, NULL, NULL, 0 },
3093
3094 /* The YMSK field in 64-bit GER prefix instructions. */
3095 #define YMSK2 YMSK + 1
3096 { 0x3, 34, NULL, NULL, 0 },
3097
3098 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
3099 unsigned imediate */
3100 #define DUIS YMSK2 + 1
3101 #define BHRBE DUIS
3102 { 0x3ff, 11, NULL, NULL, 0 },
3103
3104 /* The split DW field in a X form instruction. */
3105 #define DW DUIS + 1
3106 { -1, PPC_OPSHIFT_INV, insert_dw, extract_dw,
3107 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED},
3108
3109 /* The split D field in a DX form instruction. */
3110 #define DXD DW + 1
3111 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
3112 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
3113
3114 /* The split ND field in a DX form instruction.
3115 This is the same as the DX field, only negated. */
3116 #define NDXD DXD + 1
3117 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
3118 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
3119
3120 /* The E field in a wrteei instruction. */
3121 /* And the W bit in the pair singles instructions. */
3122 /* And the ST field in a VX form instruction. */
3123 #define E NDXD + 1
3124 #define PSW E
3125 #define ST E
3126 { 0x1, 15, NULL, NULL, 0 },
3127
3128 /* The FL1 field in a POWER SC form instruction. */
3129 #define FL1 E + 1
3130 /* The U field in an X form instruction. */
3131 #define U FL1
3132 { 0xf, 12, NULL, NULL, 0 },
3133
3134 /* The FL2 field in a POWER SC form instruction. */
3135 #define FL2 FL1 + 1
3136 { 0x7, 2, NULL, NULL, 0 },
3137
3138 /* The FLM field in an XFL form instruction. */
3139 #define FLM FL2 + 1
3140 { 0xff, 17, NULL, NULL, 0 },
3141
3142 /* The FRA field in an X or A form instruction. */
3143 #define FRA FLM + 1
3144 #define FRA_MASK (0x1f << 16)
3145 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
3146
3147 /* The FRAp field of DFP instructions. */
3148 #define FRAp FRA + 1
3149 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
3150
3151 /* The FRB field in an X or A form instruction. */
3152 #define FRB FRAp + 1
3153 #define FRB_MASK (0x1f << 11)
3154 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
3155
3156 /* The FRBp field of DFP instructions. */
3157 #define FRBp FRB + 1
3158 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
3159
3160 /* The FRC field in an A form instruction. */
3161 #define FRC FRBp + 1
3162 #define FRC_MASK (0x1f << 6)
3163 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
3164
3165 /* The FRS field in an X form instruction or the FRT field in a D, X
3166 or A form instruction. */
3167 #define FRS FRC + 1
3168 #define FRT FRS
3169 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
3170
3171 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
3172 instructions. */
3173 #define FRSp FRS + 1
3174 #define FRTp FRSp
3175 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
3176
3177 /* The FXM field in an XFX instruction. */
3178 #define FXM FRSp + 1
3179 { 0xff, 12, insert_fxm, extract_fxm, 0 },
3180
3181 /* Power4 version for mfcr. */
3182 #define FXM4 FXM + 1
3183 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
3184
3185 /* The IMM20 field in an LI instruction. */
3186 #define IMM20 FXM4 + 1
3187 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
3188
3189 /* The L field in a D or X form instruction. */
3190 #define L IMM20 + 1
3191 { 0x1, 21, NULL, NULL, 0 },
3192
3193 /* The optional L field in tlbie and tlbiel instructions. */
3194 #define LOPT L + 1
3195 /* The R field in a HTM X form instruction. */
3196 #define HTM_R LOPT
3197 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
3198
3199 /* The optional L field in the paste. instruction. This is similar to LOPT
3200 above, but with a default value of 1. */
3201 #define L1OPT LOPT + 1
3202 { 0x1, 21, insert_l1opt, extract_l1opt, PPC_OPERAND_OPTIONAL },
3203
3204 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
3205 #define L32OPT L1OPT + 1
3206 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
3207
3208 /* The 2-bit L or WC field in an X (sync, dcbf or wait) form instruction. */
3209 #define L2OPT L32OPT + 1
3210 #define LS L2OPT
3211 #define WC L2OPT
3212 { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL },
3213
3214 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
3215 #define SVC_LEV L2OPT + 1
3216 { 0x7f, 5, NULL, NULL, 0 },
3217
3218 /* The LEV field in an SC form instruction. */
3219 #define LEV SVC_LEV + 1
3220 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
3221
3222 /* The LI field in an I form instruction. The lower two bits are
3223 forced to zero. */
3224 #define LI LEV + 1
3225 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
3226
3227 /* The LI field in an I form instruction when used as an absolute
3228 address. */
3229 #define LIA LI + 1
3230 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
3231
3232 /* The 3-bit L field in a sync or dcbf instruction. */
3233 #define LS3 LIA + 1
3234 #define L3OPT LS3
3235 { 0x7, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL },
3236
3237 /* The ME field in an M form instruction. */
3238 #define ME LS3 + 1
3239 #define ME_MASK (0x1f << 1)
3240 { 0x1f, 1, NULL, NULL, 0 },
3241
3242 #define CRWn ME + 1
3243 { 0x1f, 1, insert_crwn, extract_crwn, 0 },
3244
3245 #define ELWn CRWn + 1
3246 { 0x1f, 1, insert_elwn, extract_elwn, PPC_OPERAND_PLUS1 },
3247
3248 #define ERWn ELWn + 1
3249 { 0x1f, 6, insert_erwn, extract_erwn, 0 },
3250
3251 #define ERWb ERWn + 1
3252 { 0x1f, 11, insert_erwb, extract_erwb, 0 },
3253
3254 #define CSLWb ERWb + 1
3255 { 0x1f, 6, NULL, extract_cslwb, 0 },
3256
3257 #define CSLWn CSLWb + 1
3258 { 0x1f, 11, insert_cslwn, NULL, 0 },
3259
3260 #define ILWn CSLWn + 1
3261 { 0x1f, 1, NULL, extract_ilwn, PPC_OPERAND_PLUS1 },
3262
3263 #define ILWb ILWn + 1
3264 { 0x1f, 6, insert_ilwb, NULL, 0 },
3265
3266 #define IRWn ILWb + 1
3267 { 0x1f, 1, NULL, extract_irwn, PPC_OPERAND_PLUS1 },
3268
3269 #define IRWb IRWn + 1
3270 { 0x1f, 6, insert_irwb, NULL, 0 },
3271
3272 /* The MB and ME fields in an M form instruction expressed a single
3273 operand which is a bitmask indicating which bits to select. This
3274 is a two operand form using PPC_OPERAND_NEXT. See the
3275 description in opcode/ppc.h for what this means. */
3276 #define MBE IRWb + 1
3277 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
3278 { -1, 0, insert_mbe, extract_mbe, 0 },
3279
3280 /* The MB or ME field in an MD or MDS form instruction. The high
3281 bit is wrapped to the low end. */
3282 #define MB6 MBE + 2
3283 #define ME6 MB6
3284 #define MB6_MASK (0x3f << 5)
3285 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
3286
3287 #define ELDn MB6 + 1
3288 { 0x3f, 5, insert_eldn, extract_eldn, PPC_OPERAND_PLUS1 },
3289
3290 #define ERDn ELDn + 1
3291 { 0x3f, 5, insert_erdn, extract_erdn, 0 },
3292
3293 #define CRDn ERDn + 1
3294 { 0x3f, 5, insert_crdn, extract_crdn, 0 },
3295
3296 /* The NB field in an X form instruction. The value 32 is stored as
3297 0. */
3298 #define NB CRDn + 1
3299 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
3300
3301 /* The NBI field in an lswi instruction, which has special value
3302 restrictions. The value 32 is stored as 0. */
3303 #define NBI NB + 1
3304 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
3305
3306 /* The NSI field in a D form instruction. This is the same as the
3307 SI field, only negated. */
3308 #define NSI NBI + 1
3309 { 0xffff, 0, insert_nsi, extract_nsi,
3310 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
3311
3312 /* The NSI field in a D form instruction when we accept a wide range
3313 of positive values. */
3314 #define NSISIGNOPT NSI + 1
3315 { 0xffff, 0, insert_nsi, extract_nsi,
3316 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
3317
3318 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
3319 #define RA NSISIGNOPT + 1
3320 #define RA_MASK (0x1f << 16)
3321 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
3322
3323 /* As above, but 0 in the RA field means zero, not r0. */
3324 #define RA0 RA + 1
3325 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
3326
3327 /* Similar to above, but optional. */
3328 #define PRA0 RA0 + 1
3329 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 | PPC_OPERAND_OPTIONAL },
3330
3331 /* The RA field in the DQ form lq or an lswx instruction, which have
3332 special value restrictions. */
3333 #define RAQ PRA0 + 1
3334 #define RAX RAQ
3335 { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 },
3336
3337 /* Similar to above, but optional. */
3338 #define PRAQ RAQ + 1
3339 { 0x1f, 16, insert_raq, extract_raq,
3340 PPC_OPERAND_GPR_0 | PPC_OPERAND_OPTIONAL },
3341
3342 /* The R field in an 8-byte D, DS, DQ or X form prefix instruction. */
3343 #define PCREL PRAQ + 1
3344 #define PCREL_MASK (1ULL << 52)
3345 { 0x1, 52, insert_pcrel, extract_pcrel, PPC_OPERAND_OPTIONAL },
3346
3347 #define PCREL1 PCREL + 1
3348 { 0x1, 52, insert_pcrel, extract_pcrel1, PPC_OPERAND_OPTIONAL },
3349
3350 /* The RA field in a D or X form instruction which is an updating
3351 load, which means that the RA field may not be zero and may not
3352 equal the RT field. */
3353 #define RAL PCREL1 + 1
3354 { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 },
3355
3356 /* The RA field in an lmw instruction, which has special value
3357 restrictions. */
3358 #define RAM RAL + 1
3359 { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 },
3360
3361 /* The RA field in a D or X form instruction which is an updating
3362 store or an updating floating point load, which means that the RA
3363 field may not be zero. */
3364 #define RAS RAM + 1
3365 { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 },
3366
3367 /* The RA field of the tlbwe, dccci and iccci instructions,
3368 which are optional. */
3369 #define RAOPT RAS + 1
3370 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
3371
3372 /* The RB field in an X, XO, M, or MDS form instruction. */
3373 #define RB RAOPT + 1
3374 #define RB_MASK (0x1f << 11)
3375 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
3376
3377 /* The RS and RB fields in an X form instruction when they must be the same.
3378 This is used for extended mnemonics like mr. */
3379 #define RSB RB + 1
3380 { 0x1f, 11, insert_rsb, extract_rsb, PPC_OPERAND_GPR },
3381
3382 /* The RB field in an lswx instruction, which has special value
3383 restrictions. */
3384 #define RBX RSB + 1
3385 { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR },
3386
3387 /* The RB field of the dccci and iccci instructions, which are optional. */
3388 #define RBOPT RBX + 1
3389 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
3390
3391 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
3392 #define RC RBOPT + 1
3393 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
3394
3395 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
3396 instruction or the RT field in a D, DS, X, XFX or XO form
3397 instruction. */
3398 #define RS RC + 1
3399 #define RT RS
3400 #define RT_MASK (0x1f << 21)
3401 #define RD RS
3402 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
3403
3404 #define RD_EVEN RS + 1
3405 #define RS_EVEN RD_EVEN
3406 { 0x1f, 21, insert_rD_rS_even, extract_rD_rS_even, PPC_OPERAND_GPR },
3407
3408 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
3409 which have special value restrictions. */
3410 #define RSQ RS_EVEN + 1
3411 #define RTQ RSQ
3412 #define Q_MASK (1 << 21)
3413 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
3414
3415 /* The RS field of the tlbwe instruction, which is optional. */
3416 #define RSO RSQ + 1
3417 #define RTO RSO
3418 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
3419
3420 /* The RX field of the SE_RR form instruction. */
3421 #define RX RSO + 1
3422 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
3423
3424 /* The ARX field of the SE_RR form instruction. */
3425 #define ARX RX + 1
3426 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
3427
3428 /* The RY field of the SE_RR form instruction. */
3429 #define RY ARX + 1
3430 #define RZ RY
3431 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
3432
3433 /* The ARY field of the SE_RR form instruction. */
3434 #define ARY RY + 1
3435 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
3436
3437 /* The SCLSCI8 field in a D form instruction. */
3438 #define SCLSCI8 ARY + 1
3439 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
3440
3441 /* The SCLSCI8N field in a D form instruction. This is the same as the
3442 SCLSCI8 field, only negated. */
3443 #define SCLSCI8N SCLSCI8 + 1
3444 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
3445 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
3446
3447 /* The SD field of the SD4 form instruction. */
3448 #define SE_SD SCLSCI8N + 1
3449 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
3450
3451 /* The SD field of the SD4 form instruction, for halfword. */
3452 #define SE_SDH SE_SD + 1
3453 { 0x1e, 7, NULL, NULL, PPC_OPERAND_PARENS },
3454
3455 /* The SD field of the SD4 form instruction, for word. */
3456 #define SE_SDW SE_SDH + 1
3457 { 0x3c, 6, NULL, NULL, PPC_OPERAND_PARENS },
3458
3459 /* The SH field in an X or M form instruction. */
3460 #define SH SE_SDW + 1
3461 #define SH_MASK (0x1f << 11)
3462 /* The other UIMM field in a EVX form instruction. */
3463 #define EVUIMM SH
3464 /* The FC field in an atomic X form instruction. */
3465 #define FC SH
3466 #define UIM5 SH
3467 { 0x1f, 11, NULL, NULL, 0 },
3468
3469 #define RRWn SH + 1
3470 { 0x1f, 11, insert_rrwn, extract_rrwn, 0 },
3471
3472 #define SLWn RRWn + 1
3473 { 0x1f, 11, insert_slwn, extract_slwn, 0 },
3474
3475 #define SRWn SLWn + 1
3476 { 0x1f, 11, insert_srwn, extract_srwn, 0 },
3477
3478 #define EVUIMM_LT8 SRWn + 1
3479 { 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 },
3480
3481 #define EVUIMM_LT16 EVUIMM_LT8 + 1
3482 { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 },
3483
3484 /* The SI field in a HTM X form instruction. */
3485 #define HTM_SI EVUIMM_LT16 + 1
3486 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
3487
3488 /* The SH field in an MD form instruction. This is split. */
3489 #define SH6 HTM_SI + 1
3490 #define SH6_MASK ((0x1f << 11) | (1 << 1))
3491 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
3492
3493 #define RRDn SH6 + 1
3494 { 0x3f, PPC_OPSHIFT_INV, insert_rrdn, extract_rrdn, 0 },
3495
3496 #define SLDn RRDn + 1
3497 { 0x3f, PPC_OPSHIFT_INV, insert_sldn, extract_sldn, 0 },
3498
3499 #define SRDn SLDn + 1
3500 { 0x3f, PPC_OPSHIFT_INV, insert_srdn, extract_srdn, 0 },
3501
3502 #define ERDb SRDn + 1
3503 { 0x3f, PPC_OPSHIFT_INV, insert_erdb, extract_erdb, 0 },
3504
3505 #define CSLDn ERDb + 1
3506 { 0x3f, PPC_OPSHIFT_SH6, insert_csldn, extract_sh6, 0 },
3507
3508 #define CSLDb CSLDn + 1
3509 { 0x3f, 5, insert_mb6, extract_csldb, 0 },
3510
3511 #define IRDn CSLDb + 1
3512 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_irdn, PPC_OPERAND_PLUS1 },
3513
3514 #define IRDb IRDn + 1
3515 { 0x3f, 5, insert_irdb, extract_mb6, 0 },
3516
3517 /* The SH field of some variants of the tlbre and tlbwe
3518 instructions, and the ELEV field of the e_sc instruction. */
3519 #define SHO IRDb + 1
3520 #define ELEV SHO
3521 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
3522
3523 /* The SI field in a D form instruction. */
3524 #define SI SHO + 1
3525 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
3526
3527 /* The SI field in a D form instruction when we accept a wide range
3528 of positive values. */
3529 #define SISIGNOPT SI + 1
3530 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
3531
3532 /* The SI8 field in a D form instruction. */
3533 #define SI8 SISIGNOPT + 1
3534 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
3535
3536 /* The SPR field in an XFX form instruction. This is flipped--the
3537 lower 5 bits are stored in the upper 5 and vice- versa. */
3538 #define SPR SI8 + 1
3539 #define PMR SPR
3540 #define TMR SPR
3541 #define SPR_MASK (0x3ff << 11)
3542 { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR },
3543
3544 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
3545 #define SPRBAT SPR + 1
3546 #define SPRBAT_MASK (0xc1 << 11)
3547 { 0x7, PPC_OPSHIFT_INV, insert_sprbat, extract_sprbat, PPC_OPERAND_SPR },
3548
3549 /* The GQR index number in an XFX form m[ft]gqr instruction. */
3550 #define SPRGQR SPRBAT + 1
3551 #define SPRGQR_MASK (0x7 << 16)
3552 { 0x7, 16, NULL, NULL, PPC_OPERAND_GQR },
3553
3554 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
3555 #define SPRG SPRGQR + 1
3556 { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR },
3557
3558 /* The SR field in an X form instruction. */
3559 #define SR SPRG + 1
3560 /* The 4-bit UIMM field in a VX form instruction. */
3561 #define UIMM4 SR
3562 { 0xf, 16, NULL, NULL, 0 },
3563
3564 /* The STRM field in an X AltiVec form instruction. */
3565 #define STRM SR + 1
3566 /* The T field in a tlbilx form instruction. */
3567 #define T STRM
3568 /* The L field in wclr instructions. */
3569 #define L2 STRM
3570 { 0x3, 21, NULL, NULL, 0 },
3571
3572 /* The ESYNC field in an X (sync) form instruction. */
3573 #define ESYNC STRM + 1
3574 { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL },
3575
3576 /* The SV field in a POWER SC form instruction. */
3577 #define SV ESYNC + 1
3578 { 0x3fff, 2, NULL, NULL, 0 },
3579
3580 /* The TBR field in an XFX form instruction. This is like the SPR
3581 field, but it is optional. */
3582 #define TBR SV + 1
3583 { 0x3ff, 11, insert_tbr, extract_tbr,
3584 PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL },
3585
3586 /* The TO field in a D or X form instruction. */
3587 #define TO TBR + 1
3588 #define DUI TO
3589 #define SVme TO
3590 #define SVG TO
3591 #define TO_MASK (0x1f << 21)
3592 { 0x1f, 21, NULL, NULL, 0 },
3593
3594 /* The UI field in a D form instruction. */
3595 #define UI TO + 1
3596 { 0xffff, 0, NULL, NULL, 0 },
3597
3598 #define UISIGNOPT UI + 1
3599 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
3600
3601 /* The IMM field in an SE_IM5 instruction. */
3602 #define UI5 UISIGNOPT + 1
3603 { 0x1f, 4, NULL, NULL, 0 },
3604
3605 /* The OIMM field in an SE_OIM5 instruction. */
3606 #define OIMM5 UI5 + 1
3607 { 0x1f, 4, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
3608
3609 /* The UI7 field in an SE_LI instruction. */
3610 #define UI7 OIMM5 + 1
3611 { 0x7f, 4, NULL, NULL, 0 },
3612
3613 /* The VA field in a VA, VX or VXR form instruction. */
3614 #define VA UI7 + 1
3615 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
3616
3617 /* The VB field in a VA, VX or VXR form instruction. */
3618 #define VB VA + 1
3619 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
3620
3621 /* The VC field in a VA form instruction. */
3622 #define VC VB + 1
3623 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
3624
3625 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
3626 #define VD VC + 1
3627 #define VS VD
3628 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
3629
3630 /* The SIMM field in a VX form instruction, and TE in Z form. */
3631 #define SIMM VD + 1
3632 #define TE SIMM
3633 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
3634
3635 /* The UIMM field in a VX form instruction. */
3636 #define UIMM SIMM + 1
3637 #define DCTL UIMM
3638 #define rmm UIMM
3639 { 0x1f, 16, NULL, NULL, 0 },
3640
3641 /* The 3-bit UIMM field in a VX form instruction. */
3642 #define UIMM3 UIMM + 1
3643 { 0x7, 16, NULL, NULL, 0 },
3644
3645 /* The 6-bit UIM field in a X form instruction. */
3646 #define UIM6 UIMM3 + 1
3647 { 0x3f, 16, NULL, NULL, 0 },
3648
3649 /* The SIX field in a VX form instruction. */
3650 #define SIX UIM6 + 1
3651 #define MMMM SIX
3652 { 0xf, 11, NULL, NULL, 0 },
3653
3654 /* The PS field in a VX form instruction. */
3655 #define PS SIX + 1
3656 { 0x1, 9, NULL, NULL, 0 },
3657
3658 /* The SH field in a vector shift double by bit immediate instruction. */
3659 #define SH3 PS + 1
3660 { 0x7, 6, NULL, NULL, 0 },
3661
3662 /* The SHB field in a VA form instruction. */
3663 #define SHB SH3 + 1
3664 { 0xf, 6, NULL, NULL, 0 },
3665
3666 /* The other UIMM field in a half word EVX form instruction. */
3667 #define EVUIMM_1 SHB + 1
3668 { 0x1f, 11, NULL, NULL, PPC_OPERAND_PARENS },
3669
3670 #define EVUIMM_1_EX0 EVUIMM_1 + 1
3671 { 0x1f, 11, insert_evuimm1_ex0, extract_evuimm1_ex0, PPC_OPERAND_PARENS },
3672
3673 #define EVUIMM_2 EVUIMM_1_EX0 + 1
3674 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
3675
3676 #define EVUIMM_2_EX0 EVUIMM_2 + 1
3677 { 0x3e, 10, insert_evuimm2_ex0, extract_evuimm2_ex0, PPC_OPERAND_PARENS },
3678
3679 /* The other UIMM field in a word EVX form instruction. */
3680 #define EVUIMM_4 EVUIMM_2_EX0 + 1
3681 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
3682
3683 #define EVUIMM_4_EX0 EVUIMM_4 + 1
3684 { 0x7c, 9, insert_evuimm4_ex0, extract_evuimm4_ex0, PPC_OPERAND_PARENS },
3685
3686 /* The other UIMM field in a double EVX form instruction. */
3687 #define EVUIMM_8 EVUIMM_4_EX0 + 1
3688 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
3689
3690 #define EVUIMM_8_EX0 EVUIMM_8 + 1
3691 { 0xf8, 8, insert_evuimm8_ex0, extract_evuimm8_ex0, PPC_OPERAND_PARENS },
3692
3693 /* The WS or DRM field in an X form instruction. */
3694 #define WS EVUIMM_8_EX0 + 1
3695 #define DRM WS
3696 /* The NNN field in a VX form instruction for SPE2 */
3697 #define NNN WS
3698 { 0x7, 11, NULL, NULL, 0 },
3699
3700 /* PowerPC paired singles extensions. */
3701 /* W bit in the pair singles instructions for x type instructions. */
3702 #define PSWM WS + 1
3703 /* The BO16 field in a BD8 form instruction. */
3704 #define BO16 PSWM
3705 /* The pst field in a SVRM form instruction. */
3706 #define pst PSWM
3707 /* The L field in a XO form instruction. */
3708 #define XOL PSWM
3709 { 0x1, 10, 0, 0, 0 },
3710
3711 /* IDX bits for quantization in the pair singles instructions. */
3712 #define PSQ PSWM + 1
3713 { 0x7, 12, 0, 0, PPC_OPERAND_GQR },
3714
3715 /* IDX bits for quantization in the pair singles x-type instructions. */
3716 #define PSQM PSQ + 1
3717 { 0x7, 7, 0, 0, PPC_OPERAND_GQR },
3718
3719 /* Smaller D field for quantization in the pair singles instructions. */
3720 #define PSD PSQM + 1
3721 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
3722
3723 /* The L field in an mtmsrd or A form instruction or R or W in an
3724 X form. */
3725 #define A_L PSD + 1
3726 #define W A_L
3727 #define X_R A_L
3728 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
3729
3730 /* The RMC or CY field in a Z23 form instruction. */
3731 #define RMC A_L + 1
3732 #define CY RMC
3733 #define ew RMC
3734 { 0x3, 9, NULL, NULL, 0 },
3735
3736 #define R RMC + 1
3737 #define MP R
3738 #define P1 R
3739 { 0x1, 16, NULL, NULL, 0 },
3740
3741 #define RIC R + 1
3742 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
3743
3744 #define PRS RIC + 1
3745 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
3746
3747 #define SP PRS + 1
3748 #define mi0 SP
3749 { 0x3, 19, NULL, NULL, 0 },
3750
3751 #define S SP + 1
3752 { 0x1, 20, NULL, NULL, 0 },
3753
3754 /* The S field in a XL form instruction. */
3755 #define SXL S + 1
3756 { 0x1, 11, insert_sxl, extract_sxl, PPC_OPERAND_OPTIONAL },
3757
3758 /* SH field starting at bit position 16. */
3759 #define SH16 SXL + 1
3760 /* The DCM and DGM fields in a Z form instruction. */
3761 #define DCM SH16
3762 #define DGM DCM
3763 { 0x3f, 10, NULL, NULL, 0 },
3764
3765 /* The EH field in larx instruction. */
3766 #define EH SH16 + 1
3767 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
3768
3769 /* The L field in an mtfsf or XFL form instruction. */
3770 /* The A field in a HTM X form instruction. */
3771 #define XFL_L EH + 1
3772 #define HTM_A XFL_L
3773 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
3774
3775 /* Xilinx APU related masks and macros */
3776 #define FCRT XFL_L + 1
3777 #define FCRT_MASK (0x1f << 21)
3778 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
3779
3780 /* Xilinx FSL related masks and macros */
3781 #define FSL FCRT + 1
3782 #define FSL_MASK (0x1f << 11)
3783 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
3784
3785 /* Xilinx UDI related masks and macros */
3786 #define URT FSL + 1
3787 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
3788
3789 #define URA URT + 1
3790 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
3791
3792 #define URB URA + 1
3793 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
3794
3795 #define URC URB + 1
3796 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
3797
3798 /* The VLESIMM field in a D form instruction. */
3799 #define VLESIMM URC + 1
3800 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
3801 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
3802
3803 /* The VLENSIMM field in a D form instruction. */
3804 #define VLENSIMM VLESIMM + 1
3805 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
3806 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
3807
3808 /* The VLEUIMM field in a D form instruction. */
3809 #define VLEUIMM VLENSIMM + 1
3810 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
3811
3812 /* The VLEUIMML field in a D form instruction. */
3813 #define VLEUIMML VLEUIMM + 1
3814 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
3815
3816 /* The XT and XS fields in an XX1 or XX3 form instruction. This is
3817 split. */
3818 #define XS6 VLEUIMML + 1
3819 #define XT6 XS6
3820 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
3821
3822 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
3823 #define XSQ6 XT6 + 1
3824 #define XTQ6 XSQ6
3825 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
3826
3827 /* The split XTp and XSp field in a vector paired instruction. */
3828 #define XTP XSQ6 + 1
3829 #define XSP XTP
3830 { 0x3e, PPC_OPSHIFT_INV, insert_xtp, extract_xtp, PPC_OPERAND_VSR },
3831
3832 #define XTS XTP + 1
3833 { 0x3f, PPC_OPSHIFT_INV, insert_xts, extract_xts, PPC_OPERAND_VSR },
3834
3835 /* The XT field in a plxv instruction. Runs into the OP field. */
3836 #define XTOP XTS + 1
3837 { 0x3f, 21, NULL, NULL, PPC_OPERAND_VSR },
3838
3839 /* The XA field in an XX3 form instruction. This is split. */
3840 #define XA6 XTOP + 1
3841 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
3842
3843 /* The XA field in an MMA XX3 form instruction. This is split and
3844 must not overlap with the ACC operand. */
3845 #define XA6a XA6 + 1
3846 { 0x3f, PPC_OPSHIFT_INV, insert_xa6a, extract_xa6a, PPC_OPERAND_VSR },
3847
3848 /* The XAp field in an MMA XX3 form instruction. This is split.
3849 This is like XA6a, but must be even. */
3850 #define XA6ap XA6a + 1
3851 { 0x3e, PPC_OPSHIFT_INV, insert_xa6a, extract_xa6a, PPC_OPERAND_VSR },
3852
3853 /* The 5-bit XAp field in an MMA XX3 form instruction. This is split.
3854 This is like XA6, but must be even. */
3855 #define XA5p XA6ap + 1
3856 { 0x3e, PPC_OPSHIFT_INV, insert_xa5, extract_xa5, PPC_OPERAND_VSR },
3857
3858 /* The XB field in an XX2 or XX3 form instruction. This is split. */
3859 #define XB6 XA5p + 1
3860 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
3861
3862 /* The XB field in an XX3 form instruction. This is split and
3863 must not overlap with the ACC operand. */
3864 #define XB6a XB6 + 1
3865 { 0x3f, PPC_OPSHIFT_INV, insert_xb6a, extract_xb6a, PPC_OPERAND_VSR },
3866
3867 /* The 5-bit XBp field in an MMA XX3 form instruction. This is split.
3868 This is like XB6, but must be even. */
3869 #define XB5p XB6a + 1
3870 { 0x3e, PPC_OPSHIFT_INV, insert_xb5, extract_xb5, PPC_OPERAND_VSR },
3871
3872 /* The XA and XB fields in an XX3 form instruction when they must be the same.
3873 This is used in extended mnemonics like xvmovdp. This is split. */
3874 #define XAB6 XB5p + 1
3875 { 0x3f, PPC_OPSHIFT_INV, insert_xab6, extract_xab6, PPC_OPERAND_VSR },
3876
3877 /* The XC field in an XX4 form instruction. This is split. */
3878 #define XC6 XAB6 + 1
3879 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
3880
3881 /* The DM or SHW field in an XX3 form instruction. */
3882 #define DM XC6 + 1
3883 #define SHW DM
3884 { 0x3, 8, NULL, NULL, 0 },
3885
3886 /* The DM field in an extended mnemonic XX3 form instruction. */
3887 #define DMEX DM + 1
3888 { 0x3, 8, insert_dm, extract_dm, 0 },
3889
3890 /* The UIM field in an XX2 form instruction. */
3891 #define UIM DMEX + 1
3892 /* The 2-bit UIMM field in a VX form instruction. */
3893 #define UIMM2 UIM
3894 /* The 2-bit L field in a darn instruction. */
3895 #define LRAND UIM
3896 { 0x3, 16, NULL, NULL, 0 },
3897
3898 #define ERAT_T UIM + 1
3899 { 0x7, 21, NULL, NULL, 0 },
3900
3901 #define IH ERAT_T + 1
3902 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
3903
3904 /* The 2-bit SC or PL field in an X form instruction. */
3905 #define SC2 IH + 1
3906 #define PL SC2
3907 { 0x3, 16, insert_pl, extract_pl, PPC_OPERAND_OPTIONAL },
3908
3909 #define P2 PL + 1
3910 { 0x3, PPC_OPSHIFT_INV, insert_p2, extract_p2, 0 },
3911
3912 /* The 8-bit IMM8 field in a XX1 form instruction. */
3913 #define IMM8 P2 + 1
3914 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
3915
3916 #define VX_OFF IMM8 + 1
3917 { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 },
3918
3919 #define VX_OFF_SPE2 VX_OFF + 1
3920 { 0x7, 0, insert_off_spe2, extract_off_spe2, 0 },
3921
3922 #define BBB VX_OFF_SPE2 + 1
3923 { 0x7, 13, NULL, NULL, 0 },
3924
3925 #define DDD BBB + 1
3926 #define VX_MASK_DDD (VX_MASK & ~0x1)
3927 { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 },
3928
3929 #define HH DDD + 1
3930 #define mo0 HH
3931 { 0x3, 13, NULL, NULL, 0 },
3932
3933 #define SVi HH + 1
3934 { 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO },
3935
3936 #define vf SVi + 1
3937 #define sk vf
3938 { 0x1, 6, NULL, NULL, 0 },
3939
3940 #define vs vf + 1
3941 #define mm vs
3942 { 0x1, 7, NULL, NULL, 0 },
3943
3944 #define ms vs + 1
3945 #define yx ms
3946 { 0x1, 8, NULL, NULL, 0 },
3947
3948 #define SVLcr ms + 1
3949 { 0x1, 5, NULL, NULL, 0 },
3950
3951 #define SVxd SVLcr + 1
3952 { 0x1f, 21, NULL, NULL, PPC_OPERAND_NONZERO },
3953
3954 #define SVyd SVxd + 1
3955 { 0x1f, 16, NULL, NULL, PPC_OPERAND_NONZERO },
3956
3957 #define SVzd SVyd + 1
3958 #define SVd SVzd
3959 { 0x1f, 11, NULL, NULL, PPC_OPERAND_NONZERO },
3960
3961 #define SVrm SVzd + 1
3962 { 0xf, 7, NULL, NULL, 0 },
3963
3964 #define mi1 SVrm + 1
3965 { 0x3, 17, NULL, NULL, 0 },
3966
3967 #define mi2 mi1 + 1
3968 { 0x3, 15, NULL, NULL, 0 },
3969 };
3970
3971 const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
3972 \f
3973 /* Macros used to form opcodes. */
3974
3975 /* The main opcode. */
3976 #define OP(x) ((((uint64_t)(x)) & 0x3f) << 26)
3977 #define OP_MASK OP (0x3f)
3978
3979 /* The prefix opcode. */
3980 #define PREFIX_OP (1ULL << 58)
3981
3982 /* The 2-bit prefix form. */
3983 #define PREFIX_FORM(x) ((x & 3ULL) << 56)
3984
3985 #define SUFFIX_MASK ((1ULL << 32) - 1)
3986 #define PREFIX_MASK (SUFFIX_MASK << 32)
3987
3988 /* Prefix insn, eight byte load/store form 8LS. */
3989 #define P8LS (PREFIX_OP | PREFIX_FORM (0))
3990
3991 /* Prefix insn, eight byte register to register form 8RR. */
3992 #define P8RR (PREFIX_OP | PREFIX_FORM (1))
3993
3994 /* Prefix insn, modified load/store form MLS. */
3995 #define PMLS (PREFIX_OP | PREFIX_FORM (2))
3996
3997 /* Prefix insn, modified register to register form MRR. */
3998 #define PMRR (PREFIX_OP | PREFIX_FORM (3))
3999
4000 /* Prefix insn, modified masked immediate register to register form MMIRR. */
4001 #define PMMIRR (PREFIX_OP | PREFIX_FORM (3) | (9ULL << 52))
4002
4003 /* An 8-byte D form prefix instruction. */
4004 #define P_D_MASK (((-1ULL << 50) & ~PCREL_MASK) | OP_MASK)
4005
4006 /* The same as P_D_MASK, but with the RA and PCREL fields specified. */
4007 #define P_DRAPCREL_MASK (P_D_MASK | PCREL_MASK | RA_MASK)
4008
4009 /* Mask for prefix X form instructions. */
4010 #define P_X_MASK (PREFIX_MASK | X_MASK)
4011 #define P_XX1_MASK (PREFIX_MASK | XX1_MASK)
4012
4013 /* Mask for prefix vector permute insns. */
4014 #define P_XX4_MASK (PREFIX_MASK | XX4_MASK)
4015 #define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32))
4016 #define P_U8XX4_MASK (P_XX4_MASK & ~(0xffULL << 32))
4017
4018 /* MMIRR:XX3-form 8-byte outer product instructions. */
4019 #define P_GER_MASK ((-1ULL << 40) | XX3ACC_MASK)
4020 #define P_GER2_MASK (P_GER_MASK & ~(3ULL << 46))
4021 #define P_GER4_MASK (P_GER_MASK & ~(15ULL << 44))
4022 #define P_GER8_MASK (P_GER_MASK & ~(255ULL << 40))
4023 #define P_GER64_MASK (P_GER_MASK | (3ULL << 32))
4024 #define P_GERX4_MASK ((-1ULL << 48) | XX3GERX_MASK)
4025 #define P_GERX2_MASK (P_GERX4_MASK & ~(3ULL << 46))
4026
4027 /* Vector splat immediate op. */
4028 #define VSOP(op, xop) (OP (op) | (xop << 17))
4029 #define P_VS_MASK ((-1ULL << 48) | VSOP (0x3f, 0xf))
4030 #define P_VSI_MASK ((-1ULL << 48) | VSOP (0x3f, 0xe))
4031
4032 /* The main opcode combined with a trap code in the TO field of a D
4033 form instruction. Used for extended mnemonics for the trap
4034 instructions. */
4035 #define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21))
4036 #define OPTO_MASK (OP_MASK | TO_MASK)
4037
4038 /* The main opcode combined with a comparison size bit in the L field
4039 of a D form or X form instruction. Used for extended mnemonics for
4040 the comparison instructions. */
4041 #define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21))
4042 #define OPL_MASK OPL (0x3f,1)
4043
4044 /* The main opcode combined with an update code in D form instruction.
4045 Used for extended mnemonics for VLE memory instructions. */
4046 #define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8))
4047 #define OPVUP_MASK OPVUP (0x3f, 0xff)
4048
4049 /* The main opcode combined with an update code and the RT fields
4050 specified in D form instruction. Used for VLE volatile context
4051 save/restore instructions. */
4052 #define OPVUPRT(x,vup,rt) \
4053 (OPVUP (x, vup) \
4054 | ((((uint64_t)(rt)) & 0x1f) << 21))
4055 #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
4056
4057 /* An A form instruction. */
4058 #define A(op, xop, rc) \
4059 (OP (op) \
4060 | ((((uint64_t)(xop)) & 0x1f) << 1) \
4061 | (((uint64_t)(rc)) & 1))
4062 #define A_MASK A (0x3f, 0x1f, 1)
4063
4064 /* An A_MASK with the FRB field fixed. */
4065 #define AFRB_MASK (A_MASK | FRB_MASK)
4066
4067 /* An A_MASK with the FRC field fixed. */
4068 #define AFRC_MASK (A_MASK | FRC_MASK)
4069
4070 /* An A_MASK with the FRA and FRC fields fixed. */
4071 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
4072
4073 /* An AFRAFRC_MASK, but with L bit clear. */
4074 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16))
4075
4076 /* A B form instruction. */
4077 #define B(op, aa, lk) \
4078 (OP (op) \
4079 | ((((uint64_t)(aa)) & 1) << 1) \
4080 | ((lk) & 1))
4081 #define B_MASK B (0x3f, 1, 1)
4082
4083 /* A BD8 form instruction. This is a 16-bit instruction. */
4084 #define BD8(op, aa, lk) \
4085 (((((uint64_t)(op)) & 0x3f) << 10) \
4086 | (((aa) & 1) << 9) \
4087 | (((lk) & 1) << 8))
4088 #define BD8_MASK BD8 (0x3f, 1, 1)
4089
4090 /* Another BD8 form instruction. This is a 16-bit instruction. */
4091 #define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11)
4092 #define BD8IO_MASK BD8IO (0x1f)
4093
4094 /* A BD8 form instruction for simplified mnemonics. */
4095 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
4096 /* A mask that excludes BO32 and BI32. */
4097 #define EBD8IO1_MASK 0xf800
4098 /* A mask that includes BO32 and excludes BI32. */
4099 #define EBD8IO2_MASK 0xfc00
4100 /* A mask that include BO32 AND BI32. */
4101 #define EBD8IO3_MASK 0xff00
4102
4103 /* A BD15 form instruction. */
4104 #define BD15(op, aa, lk) \
4105 (OP (op) \
4106 | ((((uint64_t)(aa)) & 0xf) << 22) \
4107 | ((lk) & 1))
4108 #define BD15_MASK BD15 (0x3f, 0xf, 1)
4109
4110 /* A BD15 form instruction for extended conditional branch mnemonics. */
4111 #define EBD15(op, aa, bo, lk) \
4112 (((op) & 0x3fu) << 26) \
4113 | (((aa) & 0xf) << 22) \
4114 | (((bo) & 0x3) << 20) \
4115 | ((lk) & 1)
4116 #define EBD15_MASK 0xfff00001
4117
4118 /* A BD15 form instruction for extended conditional branch mnemonics
4119 with BI. */
4120 #define EBD15BI(op, aa, bo, bi, lk) \
4121 ((((op) & 0x3fu) << 26) \
4122 | (((aa) & 0xf) << 22) \
4123 | (((bo) & 0x3) << 20) \
4124 | (((bi) & 0x3) << 16) \
4125 | ((lk) & 1))
4126
4127 #define EBD15BI_MASK 0xfff30001
4128
4129 /* A BD24 form instruction. */
4130 #define BD24(op, aa, lk) \
4131 (OP (op) \
4132 | ((((uint64_t)(aa)) & 1) << 25) \
4133 | ((lk) & 1))
4134 #define BD24_MASK BD24 (0x3f, 1, 1)
4135
4136 /* A B form instruction setting the BO field. */
4137 #define BBO(op, bo, aa, lk) \
4138 (B ((op), (aa), (lk)) \
4139 | ((((uint64_t)(bo)) & 0x1f) << 21))
4140 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
4141
4142 /* A BBO_MASK with the y bit of the BO field removed. This permits
4143 matching a conditional branch regardless of the setting of the y
4144 bit. Similarly for the 'at' bits used for power4 branch hints. */
4145 #define Y_MASK (((uint64_t) 1) << 21)
4146 #define AT1_MASK (((uint64_t) 3) << 21)
4147 #define AT2_MASK (((uint64_t) 9) << 21)
4148 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
4149 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
4150
4151 /* A B form instruction setting the BO field and the condition bits of
4152 the BI field. */
4153 #define BBOCB(op, bo, cb, aa, lk) \
4154 (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16))
4155 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
4156
4157 /* A BBOCB_MASK with the y bit of the BO field removed. */
4158 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
4159 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
4160 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
4161
4162 /* A BBOYCB_MASK in which the BI field is fixed. */
4163 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
4164 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
4165
4166 /* A VLE C form instruction. */
4167 #define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1))
4168 #define C_LK_MASK C_LK(0x7fff, 1)
4169 #define C(x) ((((uint64_t)(x)) & 0xffff))
4170 #define C_MASK C(0xffff)
4171
4172 /* An Context form instruction. */
4173 #define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7))
4174 #define CTX_MASK CTX(0x3f, 0x7)
4175
4176 /* An User Context form instruction. */
4177 #define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
4178 #define UCTX_MASK UCTX(0x3f, 0x1f)
4179
4180 /* The main opcode mask with the RA field clear. */
4181 #define DRA_MASK (OP_MASK | RA_MASK)
4182
4183 /* A DQ form VSX instruction. */
4184 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
4185 #define DQX_MASK DQX (0x3f, 7)
4186
4187 /* A DQ form VSX vector paired instruction. */
4188 #define DQXP(op, xop) (OP (op) | ((xop) & 0xf))
4189 #define DQXP_MASK DQXP (0x3f, 0xf)
4190
4191 /* A DS form instruction. */
4192 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
4193 #define DS_MASK DSO (0x3f, 3)
4194
4195 /* An DX form instruction. */
4196 #define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
4197 #define DX_MASK DX (0x3f, 0x1f)
4198 /* An DX form instruction with the D bits specified. */
4199 #define NODX_MASK (DX_MASK | 0x1fffc1)
4200
4201 /* An EVSEL form instruction. */
4202 #define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3)
4203 #define EVSEL_MASK EVSEL(0x3f, 0xff)
4204
4205 /* An IA16 form instruction. */
4206 #define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
4207 #define IA16_MASK IA16(0x3f, 0x1f)
4208
4209 /* An I16A form instruction. */
4210 #define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
4211 #define I16A_MASK I16A(0x3f, 0x1f)
4212
4213 /* An I16L form instruction. */
4214 #define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11)
4215 #define I16L_MASK I16L(0x3f, 0x1f)
4216
4217 /* An IM7 form instruction. */
4218 #define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11)
4219 #define IM7_MASK IM7(0x1f)
4220
4221 /* An M form instruction. */
4222 #define M(op, rc) (OP (op) | ((rc) & 1))
4223 #define M_MASK M (0x3f, 1)
4224
4225 /* An LI20 form instruction. */
4226 #define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15)
4227 #define LI20_MASK LI20(0x3f, 0x1)
4228
4229 /* An M form instruction with the ME field specified. */
4230 #define MME(op, me, rc) \
4231 (M ((op), (rc)) \
4232 | ((((uint64_t)(me)) & 0x1f) << 1))
4233
4234 /* An M_MASK with the MB field fixed. */
4235 #define MMB_MASK (M_MASK | MB_MASK)
4236
4237 /* An M_MASK with the ME field fixed. */
4238 #define MME_MASK (M_MASK | ME_MASK)
4239
4240 /* An M_MASK with the MB and ME fields fixed. */
4241 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
4242
4243 /* An M_MASK with the SH and ME fields fixed. */
4244 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
4245
4246 /* An M_MASK with the SH and MB fields fixed. */
4247 #define MSHMB_MASK (M_MASK | SH_MASK | MB_MASK)
4248
4249 /* An MD form instruction. */
4250 #define MD(op, xop, rc) \
4251 (OP (op) \
4252 | ((((uint64_t)(xop)) & 0x7) << 2) \
4253 | ((rc) & 1))
4254 #define MD_MASK MD (0x3f, 0x7, 1)
4255
4256 /* An MD_MASK with the MB field fixed. */
4257 #define MDMB_MASK (MD_MASK | MB6_MASK)
4258
4259 /* An MD_MASK with the SH field fixed. */
4260 #define MDSH_MASK (MD_MASK | SH6_MASK)
4261
4262 /* An MDS form instruction. */
4263 #define MDS(op, xop, rc) \
4264 (OP (op) \
4265 | ((((uint64_t)(xop)) & 0xf) << 1) \
4266 | ((rc) & 1))
4267 #define MDS_MASK MDS (0x3f, 0xf, 1)
4268
4269 /* An MDS_MASK with the MB field fixed. */
4270 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
4271
4272 /* An SC form instruction. */
4273 #define SC(op, sa, lk) \
4274 (OP (op) \
4275 | ((((uint64_t)(sa)) & 1) << 1) \
4276 | ((lk) & 1))
4277 #define SC_MASK \
4278 (OP_MASK \
4279 | (((uint64_t) 0x3ff) << 16) \
4280 | (((uint64_t) 1) << 1) \
4281 | 1)
4282
4283 /* An SCI8 form instruction. */
4284 #define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11))
4285 #define SCI8_MASK SCI8(0x3f, 0x1f)
4286
4287 /* An SCI8 form instruction. */
4288 #define SCI8BF(op, fop, xop) \
4289 (OP (op) \
4290 | ((((uint64_t)(xop)) & 0x1f) << 11) \
4291 | (((fop) & 7) << 23))
4292 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
4293
4294 /* An SD4 form instruction. This is a 16-bit instruction. */
4295 #define SD4(op) ((((uint64_t)(op)) & 0xf) << 12)
4296 #define SD4_MASK SD4(0xf)
4297
4298 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
4299 #define SE_IM5(op, xop) \
4300 (((((uint64_t)(op)) & 0x3f) << 10) \
4301 | (((xop) & 0x1) << 9))
4302 #define SE_IM5_MASK SE_IM5(0x3f, 1)
4303
4304 /* An SE_R form instruction. This is a 16-bit instruction. */
4305 #define SE_R(op, xop) \
4306 (((((uint64_t)(op)) & 0x3f) << 10) \
4307 | (((xop) & 0x3f) << 4))
4308 #define SE_R_MASK SE_R(0x3f, 0x3f)
4309
4310 /* An SE_RR form instruction. This is a 16-bit instruction. */
4311 #define SE_RR(op, xop) \
4312 (((((uint64_t)(op)) & 0x3f) << 10) \
4313 | (((xop) & 0x3) << 8))
4314 #define SE_RR_MASK SE_RR(0x3f, 3)
4315
4316 /* A VX form instruction. */
4317 #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
4318
4319 /* The mask for an VX form instruction. */
4320 #define VX_MASK VX(0x3f, 0x7ff)
4321
4322 /* A VX LSP form instruction. */
4323 #define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff))
4324
4325 /* The mask for an VX LSP form instruction. */
4326 #define VX_LSP_MASK VX_LSP(0x3f, 0xffff)
4327 #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc)
4328
4329 /* Additional format of VX SPE2 form instruction. */
4330 #define VX_RA_CONST(op, xop, bits11_15) \
4331 (OP (op) \
4332 | (((uint64_t)(bits11_15) & 0x1f) << 16) \
4333 | (((uint64_t)(xop)) & 0x7ff))
4334 #define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f)
4335
4336 #define VX_RB_CONST(op, xop, bits16_20) \
4337 (OP (op) \
4338 | (((uint64_t)(bits16_20) & 0x1f) << 11) \
4339 | (((uint64_t)(xop)) & 0x7ff))
4340 #define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f)
4341
4342 #define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8)
4343
4344 #define VX_SPE_CRFD(op, xop, bits9_10) \
4345 (OP (op) \
4346 | (((uint64_t)(bits9_10) & 0x3) << 21) \
4347 | (((uint64_t)(xop)) & 0x7ff))
4348 #define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3)
4349
4350 #define VX_SPE2_CLR(op, xop, bit16) \
4351 (OP (op) \
4352 | (((uint64_t)(bit16) & 0x1) << 15) \
4353 | (((uint64_t)(xop)) & 0x7ff))
4354 #define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1)
4355
4356 #define VX_SPE2_SPLATB(op, xop, bits19_20) \
4357 (OP (op) \
4358 | (((uint64_t)(bits19_20) & 0x3) << 11) \
4359 | (((uint64_t)(xop)) & 0x7ff))
4360 #define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3)
4361
4362 #define VX_SPE2_OCTET(op, xop, bits16_17) \
4363 (OP (op) \
4364 | (((uint64_t)(bits16_17) & 0x3) << 14) \
4365 | (((uint64_t)(xop)) & 0x7ff))
4366 #define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7)
4367
4368 #define VX_SPE2_DDHH(op, xop, bit16) \
4369 (OP (op) \
4370 | (((uint64_t)(bit16) & 0x1) << 15) \
4371 | (((uint64_t)(xop)) & 0x7ff))
4372 #define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1)
4373
4374 #define VX_SPE2_HH(op, xop, bit16, bits19_20) \
4375 (OP (op) \
4376 | (((uint64_t)(bit16) & 0x1) << 15) \
4377 | (((uint64_t)(bits19_20) & 0x3) << 11) \
4378 | (((uint64_t)(xop)) & 0x7ff))
4379 #define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3)
4380
4381 #define VX_SPE2_EVMAR(op, xop) \
4382 (OP (op) \
4383 | ((uint64_t)(0x1) << 11) \
4384 | (((uint64_t)(xop)) & 0x7ff))
4385 #define VX_SPE2_EVMAR_MASK \
4386 (VX_SPE2_EVMAR(0x3f, 0x7ff) \
4387 | ((uint64_t)(0x1) << 11))
4388
4389 /* A VX_MASK with the VA field fixed. */
4390 #define VXVA_MASK (VX_MASK | (0x1f << 16))
4391
4392 /* A VX_MASK with the VB field fixed. */
4393 #define VXVB_MASK (VX_MASK | (0x1f << 11))
4394
4395 /* A VX_MASK with the VA and VB fields fixed. */
4396 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
4397
4398 /* A VX_MASK with the VD and VA fields fixed. */
4399 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
4400
4401 /* A VX_MASK with a UIMM4 field. */
4402 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
4403
4404 /* A VX_MASK with a UIMM3 field. */
4405 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
4406
4407 /* A VX_MASK with a UIMM2 field. */
4408 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
4409
4410 /* A VX_MASK with a PS field. */
4411 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
4412
4413 /* A VX_MASK with the VA field fixed with a PS field. */
4414 #define VXVAPS_MASK (VXVA_MASK & ~(0x1 << 9))
4415
4416 /* A VX_MASK with the VA field fixed with a MP field. */
4417 #define VXVAM_MASK (VXVA_MASK & ~(0x1 << 16))
4418
4419 /* A VX_MASK for instructions using a BF field. */
4420 #define VXBF_MASK (VX_MASK | (3 << 21))
4421
4422 /* A VX_MASK for instructions with an RC field. */
4423 #define VXRC_MASK (VX_MASK & ~(0x1f << 6))
4424
4425 /* A VX_MASK for instructions with a SH field. */
4426 #define VXSH_MASK (VX_MASK & ~(0x7 << 6))
4427
4428 /* A VA form instruction. */
4429 #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f))
4430
4431 /* The mask for an VA form instruction. */
4432 #define VXA_MASK VXA(0x3f, 0x3f)
4433
4434 /* A VXA_MASK with a SHB field. */
4435 #define VXASHB_MASK (VXA_MASK | (1 << 10))
4436
4437 /* A VXR form instruction. */
4438 #define VXR(op, xop, rc) \
4439 (OP (op) \
4440 | (((uint64_t)(rc) & 1) << 10) \
4441 | (((uint64_t)(xop)) & 0x3ff))
4442
4443 /* The mask for a VXR form instruction. */
4444 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
4445
4446 /* A VX form instruction with a VA tertiary opcode. */
4447 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
4448
4449 #define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1))
4450 #define VXASH_MASK VXASH (0x3f, 0x1f)
4451
4452 /* An X form instruction. */
4453 #define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
4454
4455 /* A X form instruction for Quad-Precision FP Instructions. */
4456 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
4457
4458 /* An EX form instruction. */
4459 #define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
4460
4461 /* The mask for an EX form instruction. */
4462 #define EX_MASK EX (0x3f, 0x7ff)
4463
4464 /* An XX2 form instruction. */
4465 #define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2))
4466
4467 /* A XX2 form instruction with the VA bits specified. */
4468 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
4469
4470 /* An XX3 form instruction. */
4471 #define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3))
4472
4473 /* An XX3 form instruction with the RC bit specified. */
4474 #define XX3RC(op, xop, rc) \
4475 (OP (op) \
4476 | (((uint64_t)(rc) & 1) << 10) \
4477 | ((((uint64_t)(xop)) & 0x7f) << 3))
4478
4479 /* An XX4 form instruction. */
4480 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
4481
4482 /* A Z form instruction. */
4483 #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1))
4484
4485 /* An X form instruction with the RC bit specified. */
4486 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
4487
4488 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
4489 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
4490
4491 /* An X form instruction with the RA bits specified as two ops. */
4492 #define XMMF(op, xop, mop0, mop1) \
4493 (X ((op), (xop)) \
4494 | ((mop0) & 3) << 19 \
4495 | ((mop1) & 7) << 16)
4496
4497 /* A Z form instruction with the RC bit specified. */
4498 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
4499
4500 /* The mask for an X form instruction. */
4501 #define X_MASK XRC (0x3f, 0x3ff, 1)
4502
4503 /* The mask for an X form instruction with the BF bits specified. */
4504 #define XBF_MASK (X_MASK | (3 << 21))
4505
4506 /* An X form instruction without the RC field specified. */
4507 #define XRC_MASK XRC (0x3f, 0x3ff, 0)
4508
4509 /* An X form wait instruction with everything filled in except the WC
4510 field. */
4511 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
4512
4513 /* An X form wait instruction with everything filled in except the WC
4514 and PL fields. */
4515 #define XWCPL_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | (3 << 18) | RB_MASK)
4516
4517 /* The mask for an XX1 form instruction. */
4518 #define XX1_MASK X (0x3f, 0x3ff)
4519
4520 /* An XX1_MASK with the RB field fixed. */
4521 #define XX1RB_MASK (XX1_MASK | RB_MASK)
4522
4523 /* The mask for an XX2 form instruction. */
4524 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
4525
4526 /* The mask for an XX2 form instruction with the UIM bits specified. */
4527 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
4528
4529 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */
4530 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
4531
4532 /* The mask for an XX2 form instruction with the BF bits specified. */
4533 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
4534
4535 /* The mask for an XX2 form instruction with the BF and DCMX bits
4536 specified. */
4537 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
4538
4539 /* The mask for an XX2 form instruction with a split DCMX bits
4540 specified. */
4541 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
4542
4543 /* The mask for an XX3 form instruction. */
4544 #define XX3_MASK XX3 (0x3f, 0xff)
4545
4546 /* The mask for an XX3 form instruction with the BF bits specified. */
4547 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
4548
4549 /* An X_MASK with an accumulator register and the RA and RB fields fixed. */
4550 #define XACC_MASK (X_MASK | RA_MASK | RB_MASK | (3 << 21))
4551 #define XDMR_MASK XACC_MASK
4552
4553 /* An X_MASK with two dense math register. */
4554 #define XDMRDMR_MASK (X_MASK | RA_MASK | (3 << 21) | (3 << 11))
4555
4556 /* The mask for an XX3 form instruction with the DM or SHW bits
4557 specified. */
4558 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
4559 #define XX3SHW_MASK XX3DM_MASK
4560
4561 /* The masks for X* form instructions with an ACC/DMR register. */
4562 #define XX2ACC_MASK (XX2 (0x3f, 0x1ff) | (3 << 21) | 1)
4563 #define XX3ACC_MASK (XX3_MASK | (3 << 21) | 1)
4564 #define XX3DMR_MASK (XX3ACC_MASK | (1 << 11))
4565 #define XX2DMR_MASK (XX2ACC_MASK | (0xf << 17))
4566 #define XX3GERX_MASK (XX3ACC_MASK | (1 << 16))
4567
4568 /* The mask for an XX4 form instruction. */
4569 #define XX4_MASK XX4 (0x3f, 0x3)
4570
4571 /* An X form wait instruction with everything filled in except the WC
4572 field. */
4573 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
4574
4575 /* The mask for an XMMF form instruction. */
4576 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
4577
4578 /* The mask for a Z form instruction. */
4579 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
4580 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4581
4582 /* An X_MASK with the RA/VA field fixed. */
4583 #define XRA_MASK (X_MASK | RA_MASK)
4584 #define XVA_MASK XRA_MASK
4585
4586 /* An XRA_MASK with the A_L/W field clear. */
4587 #define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16))
4588 #define XRLA_MASK XWRA_MASK
4589
4590 /* An X_MASK with the RB field fixed. */
4591 #define XRB_MASK (X_MASK | RB_MASK)
4592
4593 /* An X_MASK with the RT field fixed. */
4594 #define XRT_MASK (X_MASK | RT_MASK)
4595
4596 /* An XRT_MASK mask with the 2 L bits clear. */
4597 #define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21))
4598
4599 /* An XRT_MASK mask with the 3 L bits clear. */
4600 #define XL3RT_MASK (XRT_MASK & ~((uint64_t) 0x7 << 21))
4601
4602 /* An X_MASK with the RA and RB fields fixed. */
4603 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
4604
4605 /* An XBF_MASK with the RA and RB fields fixed. */
4606 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
4607
4608 /* An XRARB_MASK, but with the L bit clear. */
4609 #define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16))
4610
4611 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */
4612 #define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16))
4613
4614 /* An X_MASK with the RT and RA fields fixed. */
4615 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
4616
4617 /* An X_MASK with the RT and RB fields fixed. */
4618 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
4619
4620 /* An XRTRA_MASK, but with L bit clear. */
4621 #define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21))
4622
4623 /* An X_MASK with the RT, RA and RB fields fixed. */
4624 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
4625
4626 /* An XRTRARB_MASK, but with L bit clear. */
4627 #define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21))
4628
4629 /* An XRTRARB_MASK, but with A bit clear. */
4630 #define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25))
4631
4632 /* An XRTRARB_MASK, but with BF bits clear. */
4633 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23))
4634
4635 /* An X form instruction with the L bit specified. */
4636 #define XOPL(op, xop, l) \
4637 (X ((op), (xop)) \
4638 | ((((uint64_t)(l)) & 1) << 21))
4639
4640 /* An X form instruction with the 2 L bits specified. */
4641 #define XOPL2(op, xop, l) \
4642 (X ((op), (xop)) \
4643 | ((((uint64_t)(l)) & 3) << 21))
4644
4645 /* An X form instruction with the 3 L bits specified. */
4646 #define XOPL3(op, xop, l) \
4647 (X ((op), (xop)) \
4648 | ((((uint64_t)(l)) & 7) << 21))
4649
4650 /* An X form instruction with the WC and PL bits specified. */
4651 #define XWCPL(op, xop, wc, pl) \
4652 (XOPL3 ((op), (xop), (wc)) \
4653 | ((((uint64_t)(pl)) & 3) << 16))
4654
4655 /* An X form instruction with the L bit and RC bit specified. */
4656 #define XRCL(op, xop, l, rc) \
4657 (XRC ((op), (xop), (rc)) \
4658 | ((((uint64_t)(l)) & 1) << 21))
4659
4660 /* An X form instruction with RT fields specified */
4661 #define XRT(op, xop, rt) \
4662 (X ((op), (xop)) \
4663 | ((((uint64_t)(rt)) & 0x1f) << 21))
4664
4665 /* An X form instruction with RT and RA fields specified */
4666 #define XRTRA(op, xop, rt, ra) \
4667 (X ((op), (xop)) \
4668 | ((((uint64_t)(rt)) & 0x1f) << 21) \
4669 | ((((uint64_t)(ra)) & 0x1f) << 16))
4670
4671 /* The mask for an X form comparison instruction. */
4672 #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22))
4673
4674 /* The mask for an X form comparison instruction with the L field
4675 fixed. */
4676 #define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21))
4677
4678 /* An X form trap instruction with the TO field specified. */
4679 #define XTO(op, xop, to) \
4680 (X ((op), (xop)) \
4681 | ((((uint64_t)(to)) & 0x1f) << 21))
4682 #define XTO_MASK (X_MASK | TO_MASK)
4683
4684 /* An X form tlb instruction with the SH field specified. */
4685 #define XTLB(op, xop, sh) \
4686 (X ((op), (xop)) \
4687 | ((((uint64_t)(sh)) & 0x1f) << 11))
4688 #define XTLB_MASK (X_MASK | SH_MASK)
4689
4690 /* An X form sync instruction. */
4691 #define XSYNC(op, xop, l) \
4692 (X ((op), (xop)) \
4693 | ((((uint64_t)(l)) & 3) << 21))
4694
4695 /* An X form sync instruction with everything filled in except the LS
4696 field. */
4697 #define XSYNC_MASK (0xff9fffff)
4698
4699 /* An X form sync instruction with everything filled in except the L
4700 and E fields. */
4701 #define XSYNCLE_MASK (0xff90ffff)
4702
4703 /* An X form sync instruction. */
4704 #define XSYNCLS(op, xop, l, s) \
4705 (X ((op), (xop)) \
4706 | ((((uint64_t)(l)) & 7) << 21) \
4707 | ((((uint64_t)(s)) & 3) << 16))
4708
4709 /* An X form sync instruction with everything filled in except the
4710 L and SC fields. */
4711 #define XSYNCLS_MASK (0xff1cffff)
4712
4713 /* An X_MASK, but with the EH bit clear. */
4714 #define XEH_MASK (X_MASK & ~((uint64_t )1))
4715
4716 /* An X form AltiVec dss instruction. */
4717 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25))
4718 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
4719
4720 /* An XFL form instruction. */
4721 #define XFL(op, xop, rc) \
4722 (OP (op) \
4723 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
4724 | (((uint64_t)(rc)) & 1))
4725 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
4726
4727 /* An X form isel instruction. */
4728 #define XISEL(op, xop, cr) (OP (op) | ((xop) << 1) | ((cr) << 6))
4729 #define XISEL_MASK XISEL(0x3f, 0x1f, 0)
4730
4731 /* An XL form instruction with the LK field set to 0. */
4732 #define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1))
4733
4734 /* An XL form instruction which uses the LK field. */
4735 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
4736
4737 /* The mask for an XL form instruction. */
4738 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
4739
4740 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
4741 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
4742
4743 /* An XL form instruction which explicitly sets the BO field. */
4744 #define XLO(op, bo, xop, lk) \
4745 (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21))
4746 #define XLO_MASK (XL_MASK | BO_MASK)
4747
4748 /* An XL form instruction which sets the BO field and the condition
4749 bits of the BI field. */
4750 #define XLOCB(op, bo, cb, xop, lk) \
4751 (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16))
4752
4753 /* An XL_MASK with the BB field fixed. */
4754 #define XLBB_MASK (XL_MASK | BB_MASK)
4755
4756 /* A mask for branch instructions using the BH field. */
4757 #define XLBH_MASK (XL_MASK | (BB_MASK & ~(3 << 11)))
4758
4759 /* An XLBH_MASK with the BO field fixed. */
4760 #define XLBOBB_MASK (XLBH_MASK | BO_MASK)
4761
4762 /* An XLBH_MASK with the BO and BI fields fixed. */
4763 #define XLBOBIBB_MASK (XLBOBB_MASK | BI_MASK)
4764
4765 /* An XLBH_MASK with the BO and condition bits of the BI fields fixed. */
4766 #define XLBOCBBB_MASK (XLBOBB_MASK | (3 << 16))
4767
4768 /* An X form mbar instruction with MO field. */
4769 #define XMBAR(op, xop, mo) \
4770 (X ((op), (xop)) \
4771 | ((((uint64_t)(mo)) & 1) << 21))
4772
4773 /* An XO form instruction. */
4774 #define XO(op, xop, oe, rc) \
4775 (OP (op) \
4776 | ((((uint64_t)(xop)) & 0x1ff) << 1) \
4777 | ((((uint64_t)(oe)) & 1) << 10) \
4778 | (((unsigned long)(rc)) & 1))
4779 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
4780 #define XOL_MASK XO (0x3f, 0x1ff, 0, 1)
4781
4782 /* An XO_MASK with the RB field fixed. */
4783 #define XORB_MASK (XO_MASK | RB_MASK)
4784
4785 /* An XOPS form instruction for paired singles. */
4786 #define XOPS(op, xop, rc) \
4787 (OP (op) \
4788 | ((((uint64_t)(xop)) & 0x3ff) << 1) \
4789 | (((uint64_t)(rc)) & 1))
4790 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
4791
4792
4793 /* An XS form instruction. */
4794 #define XS(op, xop, rc) \
4795 (OP (op) \
4796 | ((((uint64_t)(xop)) & 0x1ff) << 2) \
4797 | (((uint64_t)(rc)) & 1))
4798 #define XS_MASK XS (0x3f, 0x1ff, 1)
4799
4800 /* A mask for the FXM version of an XFX form instruction. */
4801 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
4802
4803 /* An XFX form instruction with the FXM field filled in. */
4804 #define XFXM(op, xop, fxm, p4) \
4805 (X ((op), (xop)) \
4806 | ((((uint64_t)(fxm)) & 0xff) << 12) \
4807 | ((uint64_t)(p4) << 20))
4808
4809 /* An XFX form instruction with the SPR field filled in. */
4810 #define XSPR(op, xop, spr) \
4811 (X ((op), (xop)) \
4812 | ((((uint64_t)(spr)) & 0x1f) << 16) \
4813 | ((((uint64_t)(spr)) & 0x3e0) << 6))
4814 #define XSPR_MASK (X_MASK | SPR_MASK)
4815
4816 /* An XFX form instruction with the SPR field filled in except for the
4817 SPRBAT field. */
4818 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
4819
4820 /* An XFX form instruction with the SPR field filled in except for the
4821 SPRGQR field. */
4822 #define XSPRGQR_MASK (XSPR_MASK &~ SPRGQR_MASK)
4823
4824 /* An XFX form instruction with the SPR field filled in except for the
4825 SPRG field. */
4826 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
4827
4828 /* An X form instruction with everything filled in except the E field. */
4829 #define XE_MASK (0xffff7fff)
4830
4831 /* An X form user context instruction. */
4832 #define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f))
4833 #define XUC_MASK XUC(0x3f, 0x1f)
4834
4835 /* An XW form instruction. */
4836 #define XW(op, xop, rc) \
4837 (OP (op) \
4838 | ((((uint64_t)(xop)) & 0x3f) << 1) \
4839 | ((rc) & 1))
4840 /* The mask for a G form instruction. rc not supported at present. */
4841 #define XW_MASK XW (0x3f, 0x3f, 0)
4842
4843 /* An APU form instruction. */
4844 #define APU(op, xop, rc) \
4845 (OP (op) \
4846 | (((uint64_t)(xop)) & 0x3ff) << 1 \
4847 | ((rc) & 1))
4848
4849 /* The mask for an APU form instruction. */
4850 #define APU_MASK APU (0x3f, 0x3ff, 1)
4851 #define APU_RT_MASK (APU_MASK | RT_MASK)
4852 #define APU_RA_MASK (APU_MASK | RA_MASK)
4853
4854 /* An SVL form instruction. */
4855 #define SVL(op, xop, rc) \
4856 (OP (op) \
4857 | ((((uint64_t)(xop)) & 0x1f) << 1) \
4858 | (((uint64_t)(rc)) & 1))
4859 #define SVL_MASK SVL (0x3f, 0x1f, 1)
4860
4861 /* An SVM form instruction. */
4862 #define SVM(op, xop) \
4863 (OP (op) \
4864 | (((uint64_t)(xop)) & 0x3f))
4865 #define SVM_MASK SVM (0x3f, 0x3f)
4866
4867 /* An SVRM form instruction. */
4868 #define SVRM(op, xop) \
4869 (OP (op) \
4870 | (((uint64_t)(xop)) & 0x3f))
4871 #define SVRM_MASK SVRM (0x3f, 0x3f)
4872
4873 /* An SVI form instruction. */
4874 #define SVI(op, xop) \
4875 (OP (op) \
4876 | (((uint64_t)(xop)) & 0x3f))
4877 #define SVI_MASK SVI (0x3f, 0x3f)
4878
4879 /* The BO encodings used in extended conditional branch mnemonics. */
4880 #define BODNZF (0x0)
4881 #define BODNZFP (0x1)
4882 #define BODZF (0x2)
4883 #define BODZFP (0x3)
4884 #define BODNZT (0x8)
4885 #define BODNZTP (0x9)
4886 #define BODZT (0xa)
4887 #define BODZTP (0xb)
4888
4889 #define BOF (0x4)
4890 #define BOFP (0x5)
4891 #define BOFM4 (0x6)
4892 #define BOFP4 (0x7)
4893 #define BOT (0xc)
4894 #define BOTP (0xd)
4895 #define BOTM4 (0xe)
4896 #define BOTP4 (0xf)
4897
4898 #define BODNZ (0x10)
4899 #define BODNZP (0x11)
4900 #define BODZ (0x12)
4901 #define BODZP (0x13)
4902 #define BODNZM4 (0x18)
4903 #define BODNZP4 (0x19)
4904 #define BODZM4 (0x1a)
4905 #define BODZP4 (0x1b)
4906
4907 #define BOU (0x14)
4908
4909 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
4910 #define BO16F (0x0)
4911 #define BO16T (0x1)
4912
4913 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
4914 #define BO32F (0x0)
4915 #define BO32T (0x1)
4916 #define BO32DNZ (0x2)
4917 #define BO32DZ (0x3)
4918
4919 /* The BI condition bit encodings used in extended conditional branch
4920 mnemonics. */
4921 #define CBLT (0)
4922 #define CBGT (1)
4923 #define CBEQ (2)
4924 #define CBSO (3)
4925
4926 /* The TO encodings used in extended trap mnemonics. */
4927 #define TOLGT (0x1)
4928 #define TOLLT (0x2)
4929 #define TOEQ (0x4)
4930 #define TOLGE (0x5)
4931 #define TOLNL (0x5)
4932 #define TOLLE (0x6)
4933 #define TOLNG (0x6)
4934 #define TOGT (0x8)
4935 #define TOGE (0xc)
4936 #define TONL (0xc)
4937 #define TOLT (0x10)
4938 #define TOLE (0x14)
4939 #define TONG (0x14)
4940 #define TONE (0x18)
4941 #define TOU (0x1f)
4942 \f
4943 /* Smaller names for the flags so each entry in the opcodes table will
4944 fit on a single line. */
4945 #undef PPC
4946 #define PPC PPC_OPCODE_PPC
4947 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
4948 #define POWER4 PPC_OPCODE_POWER4
4949 #define POWER5 PPC_OPCODE_POWER5
4950 #define POWER6 PPC_OPCODE_POWER6
4951 #define POWER7 PPC_OPCODE_POWER7
4952 #define POWER8 PPC_OPCODE_POWER8
4953 #define POWER9 PPC_OPCODE_POWER9
4954 #define POWER10 PPC_OPCODE_POWER10
4955 #define FUTURE PPC_OPCODE_FUTURE
4956 #define CELL PPC_OPCODE_CELL
4957 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
4958 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
4959 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
4960 #define PPC403 PPC_OPCODE_403
4961 #define PPC405 PPC_OPCODE_405
4962 #define PPC440 PPC_OPCODE_440
4963 #define PPC464 PPC440
4964 #define PPC476 PPC_OPCODE_476
4965 #define PPC750 PPC_OPCODE_750
4966 #define GEKKO PPC_OPCODE_750
4967 #define BROADWAY PPC_OPCODE_750
4968 #define PPC7450 PPC_OPCODE_7450
4969 #define PPC860 PPC_OPCODE_860
4970 #define PPCPS PPC_OPCODE_PPCPS
4971 #define PPCVEC PPC_OPCODE_ALTIVEC
4972 #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500)
4973 #define PPCVEC3 PPC_OPCODE_POWER9
4974 #define PPCVSX PPC_OPCODE_VSX
4975 #define PPCVSX2 PPC_OPCODE_POWER8
4976 #define PPCVSX3 PPC_OPCODE_POWER9
4977 #define PPCVSX4 PPC_OPCODE_POWER10
4978 #define PPCVSXF PPC_OPCODE_FUTURE
4979 #define POWER PPC_OPCODE_POWER
4980 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
4981 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
4982 #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \
4983 | PPC_OPCODE_COMMON)
4984 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
4985 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
4986 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
4987 #define MFDEC1 PPC_OPCODE_POWER
4988 #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \
4989 | PPC_OPCODE_TITAN)
4990 #define BOOKE PPC_OPCODE_BOOKE
4991 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
4992 #define PPCE300 PPC_OPCODE_E300
4993 #define PPCSPE PPC_OPCODE_SPE
4994 #define PPCSPE2 PPC_OPCODE_SPE2
4995 #define PPCISEL PPC_OPCODE_ISEL
4996 #define PPCEFS PPC_OPCODE_EFS
4997 #define PPCEFS2 PPC_OPCODE_EFS2
4998 #define PPCBRLK PPC_OPCODE_BRLOCK
4999 #define PPCPMR PPC_OPCODE_PMR
5000 #define PPCTMR PPC_OPCODE_TMR
5001 #define PPCCHLK PPC_OPCODE_CACHELCK
5002 #define PPCRFMCI PPC_OPCODE_RFMCI
5003 #define E500MC PPC_OPCODE_E500MC
5004 #define PPCA2 PPC_OPCODE_A2
5005 #define TITAN PPC_OPCODE_TITAN
5006 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
5007 #define E500 PPC_OPCODE_E500
5008 #define E6500 PPC_OPCODE_E6500
5009 #define PPCVLE PPC_OPCODE_VLE
5010 #define PPCHTM PPC_OPCODE_POWER8
5011 #define E200Z4 PPC_OPCODE_E200Z4
5012 #define PPCLSP PPC_OPCODE_LSP
5013 #define SVP64 PPC_OPCODE_SVP64
5014 /* Used to mark extended mnemonic in deprecated field so that -Mraw
5015 won't use this variant in disassembly. */
5016 #define EXT PPC_OPCODE_RAW
5017 \f
5018 /* The opcode table.
5019
5020 The format of the opcode table is:
5021
5022 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
5023
5024 NAME is the name of the instruction.
5025 OPCODE is the instruction opcode.
5026 MASK is the opcode mask; this is used to tell the disassembler
5027 which bits in the actual opcode must match OPCODE.
5028 FLAGS are flags indicating which processors support the instruction.
5029 ANTI indicates which processors don't support the instruction.
5030 OPERANDS is the list of operands.
5031
5032 The disassembler reads the table in order and prints the first
5033 instruction which matches, so this table is sorted to put more
5034 specific instructions before more general instructions.
5035
5036 This table must be sorted by major opcode. Please try to keep it
5037 vaguely sorted within major opcode too, except of course where
5038 constrained otherwise by disassembler operation. */
5039
5040 const struct powerpc_opcode powerpc_opcodes[] = {
5041 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
5042 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5043 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5044 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5045 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5046 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5047 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5048 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5049 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5050 {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5051 {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5052 {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5053 {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5054 {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5055 {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5056 {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}},
5057 {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
5058
5059 {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5060 {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5061 {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5062 {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5063 {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5064 {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5065 {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5066 {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5067 {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5068 {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5069 {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5070 {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5071 {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5072 {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5073 {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5074 {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5075 {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5076 {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5077 {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5078 {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5079 {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5080 {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5081 {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5082 {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5083 {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5084 {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5085 {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5086 {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5087 {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}},
5088 {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}},
5089 {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
5090 {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
5091
5092 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
5093 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5094 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
5095 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5096 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5097 {"vrlq", VX (4, 5), VX_MASK, POWER10, 0, {VD, VA, VB}},
5098 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5099 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5100 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5101 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5102 {"vdivuq", VX (4, 11), VX_MASK, POWER10, 0, {VD, VA, VB}},
5103 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
5104 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5105 {"vstribl", VXVA(4,13,0), VXVA_MASK, POWER10, 0, {VD, VB}},
5106 {"vstribr", VXVA(4,13,1), VXVA_MASK, POWER10, 0, {VD, VB}},
5107 {"vstrihl", VXVA(4,13,2), VXVA_MASK, POWER10, 0, {VD, VB}},
5108 {"vstrihr", VXVA(4,13,3), VXVA_MASK, POWER10, 0, {VD, VB}},
5109 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
5110 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5111 {"vinsbvlx", VX (4, 15), VX_MASK, POWER10, 0, {VD, RA, VB}},
5112 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5113 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5114 {"mtvsrbmi", DX (4,10), DX_MASK, POWER10, 0, {VD, DXD}},
5115 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5116 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5117 {"vsldbi", VX (4, 22), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}},
5118 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5119 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5120 {"vextdubvlx", VX (4, 24), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5121 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
5122 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5123 {"vextdubvrx", VX (4, 25), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5124 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
5125 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5126 {"vextduhvlx", VX (4, 26), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5127 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
5128 {"vextduhvrx", VX (4, 27), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5129 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
5130 {"vextduwvlx", VX (4, 28), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5131 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5132 {"vextduwvrx", VX (4, 29), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5133 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5134 {"vextddvlx", VX (4, 30), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5135 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5136 {"vextddvrx", VX (4, 31), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},
5137 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5138 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5139 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5140 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5141 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
5142 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5143 {"vmsumcud", VXA(4, 23), VXA_MASK, POWER10, 0, {VD, VA, VB, VC}},
5144 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5145 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5146 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5147 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5148 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5149 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5150 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5151 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5152 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5153 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5154 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5155 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5156 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
5157 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
5158 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
5159 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5160 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
5161 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5162 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
5163 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
5164 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
5165 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
5166 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
5167 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
5168 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
5169 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
5170 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
5171 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
5172 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5173 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5174 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5175 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5176 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
5177 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5178 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
5179 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5180 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
5181 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5182 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
5183 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
5184 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
5185 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
5186 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5187 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5188 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5189 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5190 {"vrlqmi", VX (4, 69), VX_MASK, POWER10, 0, {VD, VA, VB}},
5191 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5192 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5193 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5194 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5195 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
5196 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5197 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
5198 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5199 {"vinshvlx", VX (4, 79), VX_MASK, POWER10, 0, {VD, RA, VB}},
5200 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
5201 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5202 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
5203 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5204 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5205 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5206 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5207 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5208 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
5209 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5210 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5211 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5212 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5213 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5214 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5215 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5216 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5217 {"vdivuw", VX (4, 139), VX_MASK, POWER10, 0, {VD, VA, VB}},
5218 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5219 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5220 {"vinswvlx", VX (4, 143), VX_MASK, POWER10, 0, {VD, RA, VB}},
5221 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
5222 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
5223 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5224 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5225 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
5226 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5227 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5228 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5229 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5230 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5231 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
5232 {"vmuloud", VX (4, 200), VX_MASK, POWER10, 0, {VD, VA, VB}},
5233 {"vdivud", VX (4, 203), VX_MASK, POWER10, 0, {VD, VA, VB}},
5234 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5235 {"vinsw", VX (4, 207), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}},
5236 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5237 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5238 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5239 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5240 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5241 {"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {BF, VA, VB}},
5242 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5243 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5244 {"vslq", VX (4, 261), VX_MASK, POWER10, 0, {VD, VA, VB}},
5245 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5246 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5247 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5248 {"vdivsq", VX (4, 267), VX_MASK, POWER10, 0, {VD, VA, VB}},
5249 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5250 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5251 {"vinsbvrx", VX (4, 271), VX_MASK, POWER10, 0, {VD, RA, VB}},
5252 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
5253 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5254 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
5255 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5256 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5257 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5258 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5259 {"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {BF, VA, VB}},
5260 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5261 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5262 {"vrlqnm", VX (4, 325), VX_MASK, POWER10, 0, {VD, VA, VB}},
5263 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5264 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5265 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5266 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5267 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5268 {"vinshvrx", VX (4, 335), VX_MASK, POWER10, 0, {VD, RA, VB}},
5269 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5270 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5271 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5272 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5273 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5274 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5275 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5276 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5277 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5278 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5279 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5280 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5281 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5282 {"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}},
5283 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5284 {"vclrlb", VX (4, 397), VX_MASK, POWER10, 0, {VD, VA, RB}},
5285 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5286 {"vinswvrx", VX (4, 399), VX_MASK, POWER10, 0, {VD, RA, VB}},
5287 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5288 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5289 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5290 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5291 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5292 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5293 {"vcmpequq", VXR(4, 455,0), VXR_MASK, POWER10, 0, {VD, VA, VB}},
5294 {"vmulosd", VX (4, 456), VX_MASK, POWER10, 0, {VD, VA, VB}},
5295 {"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}},
5296 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5297 {"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}},
5298 {"vclrrb", VX (4, 461), VX_MASK, POWER10, 0, {VD, VA, RB}},
5299 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5300 {"vinsd", VX (4, 463), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}},
5301 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5302 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5303 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5304 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5305 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5306 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5307 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
5308 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
5309 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5310 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, EXT, {RS, RB, RA}},
5311 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5312 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5313 {"vsrq", VX (4, 517), VX_MASK, POWER10, 0, {VD, VA, VB}},
5314 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, EXT, {RS, RB, UIMM}},
5315 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
5316 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5317 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
5318 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5319 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
5320 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
5321 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5322 {"vdiveuq", VX (4, 523), VX_MASK, POWER10, 0, {VD, VA, VB}},
5323 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
5324 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
5325 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
5326 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5327 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
5328 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
5329 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5330 {"vinsblx", VX (4, 527), VX_MASK, POWER10, 0, {VD, RA, RB}},
5331 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5332 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
5333 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
5334 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5335 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5336 {"vsrdbi", VX (4, 534), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}},
5337 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5338 {"evmr", VX (4, 535), VX_MASK, PPCSPE, EXT, {RS, RAB}},
5339 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5340 {"evnot", VX (4, 536), VX_MASK, PPCSPE, EXT, {RS, RAB}},
5341 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5342 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5343 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5344 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5345 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5346 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5347 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5348 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
5349 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
5350 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5351 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
5352 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5353 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
5354 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
5355 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
5356 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5357 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5358 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5359 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5360 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5361 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5362 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5363 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5364 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5365 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5366 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5367 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5368 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5369 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5370 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5371 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5372 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5373 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
5374 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5375 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5376 {"vinshlx", VX (4, 591), VX_MASK, POWER10, 0, {VD, RA, RB}},
5377 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5378 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
5379 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5380 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5381 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5382 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5383 {"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5384 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5385 {"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5386 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
5387 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5388 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
5389 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
5390 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5391 {"vcmpgtuq", VXR(4, 647,0), VXR_MASK, POWER10, 0, {VD, VA, VB}},
5392 {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}},
5393 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5394 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5395 {"vmulhuw", VX (4, 649), VX_MASK, POWER10, 0, {VD, VA, VB}},
5396 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5397 {"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5398 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5399 {"vdiveuw", VX (4, 651), VX_MASK, POWER10, 0, {VD, VA, VB}},
5400 {"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5401 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5402 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
5403 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5404 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5405 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5406 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5407 {"vinswlx", VX (4, 655), VX_MASK, POWER10, 0, {VD, RA, RB}},
5408 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
5409 {"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
5410 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
5411 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
5412 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
5413 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
5414 {"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
5415 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
5416 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
5417 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
5418 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
5419 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5420 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
5421 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5422 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5423 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5424 {"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5425 {"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5426 {"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5427 {"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5428 {"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5429 {"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5430 {"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5431 {"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5432 {"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5433 {"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5434 {"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5435 {"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5436 {"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5437 {"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5438 {"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5439 {"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5440 {"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5441 {"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5442 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5443 {"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5444 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5445 {"evsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5446 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5447 {"evssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5448 {"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
5449 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5450 {"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
5451 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
5452 {"evsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
5453 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5454 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
5455 {"evsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
5456 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
5457 {"evsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
5458 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5459 {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}},
5460 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
5461 {"vmuleud", VX (4, 712), VX_MASK, POWER10, 0, {VD, VA, VB}},
5462 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5463 {"evsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5464 {"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}},
5465 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5466 {"evsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5467 {"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
5468 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5469 {"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}},
5470 {"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
5471 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5472 {"evscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5473 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5474 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5475 {"evsgmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5476 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5477 {"evsgmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5478 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5479 {"vinsdlx", VX (4, 719), VX_MASK, POWER10, 0, {VD, RA, RB}},
5480 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
5481 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
5482 {"evscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
5483 {"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
5484 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
5485 {"evscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
5486 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
5487 {"evscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
5488 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
5489 {"evscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
5490 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
5491 {"evsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
5492 {"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
5493 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
5494 {"evsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
5495 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
5496 {"evsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
5497 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
5498 {"evsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
5499 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
5500 {"evsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
5501 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5502 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
5503 {"evsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
5504 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5505 {"evststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5506 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5507 {"evststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5508 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5509 {"evststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5510 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5511 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5512 {"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
5513 {"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}},
5514 {"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
5515 {"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}},
5516 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
5517 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
5518 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
5519 {"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}},
5520 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5521 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5522 {"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
5523 {"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}},
5524 {"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
5525 {"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}},
5526 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5527 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5528 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5529 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
5530 {"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
5531 {"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
5532 {"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
5533 {"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
5534 {"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
5535 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
5536 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
5537 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
5538 {"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
5539 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
5540 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
5541 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
5542 {"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
5543 {"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
5544 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5545 {"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
5546 {"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
5547 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5548 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5549 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5550 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5551 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5552 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5553 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5554 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5555 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5556 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5557 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5558 {"vsraq", VX (4, 773), VX_MASK, POWER10, 0, {VD, VA, VB}},
5559 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5560 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5561 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5562 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5563 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
5564 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5565 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5566 {"vdivesq", VX (4, 779), VX_MASK, POWER10, 0, {VD, VA, VB}},
5567 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5568 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
5569 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5570 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
5571 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5572 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5573 {"vinsbrx", VX (4, 783), VX_MASK, POWER10, 0, {VD, RA, RB}},
5574 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
5575 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5576 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5577 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5578 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5579 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5580 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5581 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5582 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5583 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
5584 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5585 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
5586 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5587 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5588 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5589 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5590 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5591 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5592 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5593 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5594 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5595 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5596 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5597 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5598 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5599 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5600 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5601 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5602 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5603 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5604 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5605 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5606 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5607 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5608 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5609 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5610 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5611 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
5612 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5613 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5614 {"vinshrx", VX (4, 847), VX_MASK, POWER10, 0, {VD, RA, RB}},
5615 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5616 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5617 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
5618 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
5619 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
5620 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
5621 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5622 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5623 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5624 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5625 {"vcmpgtsq", VXR(4, 903,0), VXR_MASK, POWER10, 0, {VD, VA, VB}},
5626 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5627 {"vmulhsw", VX (4, 905), VX_MASK, POWER10, 0, {VD, VA, VB}},
5628 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5629 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5630 {"vdivesw", VX (4, 907), VX_MASK, POWER10, 0, {VD, VA, VB}},
5631 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
5632 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5633 {"vinswrx", VX (4, 911), VX_MASK, POWER10, 0, {VD, RA, RB}},
5634 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5635 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5636 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5637 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5638 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5639 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
5640 {"vmulesd", VX (4, 968), VX_MASK, POWER10, 0, {VD, VA, VB}},
5641 {"vmulhsd", VX (4, 969), VX_MASK, POWER10, 0, {VD, VA, VB}},
5642 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5643 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5644 {"vdivesd", VX (4, 971), VX_MASK, POWER10, 0, {VD, VA, VB}},
5645 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
5646 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
5647 {"vinsdrx", VX (4, 975), VX_MASK, POWER10, 0, {VD, RA, RB}},
5648 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5649 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5650 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5651 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5652 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5653 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
5654 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5655 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5656 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5657 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5658 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5659 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5660 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5661 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5662 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5663 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5664 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5665 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5666 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5667 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5668 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5669 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5670 {"vstribl.", VXVA(4,1037,0), VXVA_MASK, POWER10, 0, {VD, VB}},
5671 {"vstribr.", VXVA(4,1037,1), VXVA_MASK, POWER10, 0, {VD, VB}},
5672 {"vstrihl.", VXVA(4,1037,2), VXVA_MASK, POWER10, 0, {VD, VB}},
5673 {"vstrihr.", VXVA(4,1037,3), VXVA_MASK, POWER10, 0, {VD, VB}},
5674 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5675 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5676 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5677 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5678 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5679 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5680 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5681 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5682 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5683 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5684 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5685 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5686 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5687 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5688 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5689 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
5690 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5691 {"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5692 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5693 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5694 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5695 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5696 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5697 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5698 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5699 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5700 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5701 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5702 {"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5703 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5704 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5705 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5706 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5707 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5708 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5709 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5710 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5711 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5712 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5713 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5714 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5715 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5716 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5717 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5718 {"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5719 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5720 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5721 {"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5722 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5723 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5724 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5725 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5726 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5727 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5728 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5729 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5730 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5731 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5732 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5733 {"vmr", VX (4,1156), VX_MASK, PPCVEC, EXT, {VD, VAB}},
5734 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5735 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5736 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5737 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5738 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5739 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5740 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5741 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5742 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5743 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5744 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5745 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
5746 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
5747 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
5748 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
5749 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
5750 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
5751 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5752 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5753 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5754 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5755 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
5756 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5757 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5758 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5759 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
5760 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
5761 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
5762 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
5763 {"vgnb", VX (4,1228), VX_MASK, POWER10, 0, {RT, VB, UIMM3}},
5764 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5765 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5766 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5767 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5768 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5769 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5770 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
5771 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5772 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5773 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
5774 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5775 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5776 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5777 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5778 {"vnot", VX (4,1284), VX_MASK, PPCVEC, EXT, {VD, VAB}},
5779 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5780 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5781 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5782 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5783 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5784 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5785 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5786 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5787 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5788 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5789 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5790 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5791 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5792 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5793 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5794 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5795 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5796 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5797 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5798 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5799 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5800 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5801 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5802 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5803 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5804 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5805 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5806 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5807 {"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5808 {"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5809 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5810 {"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5811 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5812 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5813 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5814 {"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5815 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5816 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5817 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5818 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5819 {"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5820 {"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5821 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5822 {"vcfuged", VX (4,1357), VX_MASK, POWER10, 0, {VD, VA, VB}},
5823 {"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5824 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5825 {"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5826 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5827 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5828 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5829 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5830 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5831 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5832 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5833 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5834 {"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5835 {"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5836 {"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5837 {"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5838 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5839 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5840 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5841 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5842 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
5843 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
5844 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5845 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
5846 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
5847 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
5848 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5849 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5850 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5851 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5852 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5853 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5854 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5855 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5856 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5857 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5858 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5859 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5860 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5861 {"vpextd", VX (4,1421), VX_MASK, POWER10, 0, {VD, VA, VB}},
5862 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5863 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5864 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5865 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5866 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5867 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5868 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5869 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5870 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5871 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5872 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5873 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
5874 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5875 {"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5876 {"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5877 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5878 {"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5879 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5880 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5881 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}},
5882 {"vcmpequq.", VXR(4, 455,1), VXR_MASK, POWER10, 0, {VD, VA, VB}},
5883 {"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5884 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
5885 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5886 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5887 {"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5888 {"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5889 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5890 {"vpdepd", VX (4,1485), VX_MASK, POWER10, 0, {VD, VA, VB}},
5891 {"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5892 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5893 {"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5894 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5895 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5896 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5897 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5898 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5899 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5900 {"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5901 {"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5902 {"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5903 {"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5904 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5905 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5906 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5907 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
5908 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
5909 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5910 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5911 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5912 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5913 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5914 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5915 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5916 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5917 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5918 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5919 {"vextsd2q", VXVA(4,1538,27), VXVA_MASK, POWER10, 0, {VD, VB}},
5920 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5921 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5922 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5923 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
5924 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
5925 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5926 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
5927 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
5928 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5929 {"vmoduq", VX (4,1547), VX_MASK, POWER10, 0, {VD, VA, VB}},
5930 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5931 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5932
5933 {"vexpandbm", VXVA(4,1602,0), VXVA_MASK, POWER10, 0, {VD, VB}},
5934 {"vexpandhm", VXVA(4,1602,1), VXVA_MASK, POWER10, 0, {VD, VB}},
5935 {"vexpandwm", VXVA(4,1602,2), VXVA_MASK, POWER10, 0, {VD, VB}},
5936 {"vexpanddm", VXVA(4,1602,3), VXVA_MASK, POWER10, 0, {VD, VB}},
5937 {"vexpandqm", VXVA(4,1602,4), VXVA_MASK, POWER10, 0, {VD, VB}},
5938 {"vextractbm", VXVA(4,1602,8), VXVA_MASK, POWER10, 0, {RT, VB}},
5939 {"vextracthm", VXVA(4,1602,9), VXVA_MASK, POWER10, 0, {RT, VB}},
5940 {"vextractwm", VXVA(4,1602,10), VXVA_MASK, POWER10, 0, {RT, VB}},
5941 {"vextractdm", VXVA(4,1602,11), VXVA_MASK, POWER10, 0, {RT, VB}},
5942 {"vextractqm", VXVA(4,1602,12), VXVA_MASK, POWER10, 0, {RT, VB}},
5943 {"mtvsrbm", VXVA(4,1602,16), VXVA_MASK, POWER10, 0, {VD, RB}},
5944 {"mtvsrhm", VXVA(4,1602,17), VXVA_MASK, POWER10, 0, {VD, RB}},
5945 {"mtvsrwm", VXVA(4,1602,18), VXVA_MASK, POWER10, 0, {VD, RB}},
5946 {"mtvsrdm", VXVA(4,1602,19), VXVA_MASK, POWER10, 0, {VD, RB}},
5947 {"mtvsrqm", VXVA(4,1602,20), VXVA_MASK, POWER10, 0, {VD, RB}},
5948 {"vcntmbb", VXVA(4,1602,24), VXVAM_MASK, POWER10, 0, {RT, VB, MP}},
5949 {"vcntmbh", VXVA(4,1602,26), VXVAM_MASK, POWER10, 0, {RT, VB, MP}},
5950 {"vcntmbw", VXVA(4,1602,28), VXVAM_MASK, POWER10, 0, {RT, VB, MP}},
5951 {"vcntmbd", VXVA(4,1602,30), VXVAM_MASK, POWER10, 0, {RT, VB, MP}},
5952
5953 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
5954 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5955 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5956 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
5957 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
5958 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5959 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5960 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5961 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
5962 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5963 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5964 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
5965 {"vcmpgtuq.", VXR(4, 647,1), VXR_MASK, POWER10, 0, {VD, VA, VB}},
5966 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
5967 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5968 {"vmoduw", VX (4,1675), VX_MASK, POWER10, 0, {VD, VA, VB}},
5969 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5970 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5971 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
5972 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5973 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5974 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
5975 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
5976 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
5977 {"vmodud", VX (4,1739), VX_MASK, POWER10, 0, {VD, VA, VB}},
5978 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5979 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5980 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5981 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5982 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5983 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5984 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
5985 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
5986 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5987 {"vmodsq", VX (4,1803), VX_MASK, POWER10, 0, {VD, VA, VB}},
5988 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5989 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
5990 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
5991 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5992 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5993 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
5994 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5995 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5996 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5997 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
5998 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
5999 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
6000 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
6001 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
6002 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
6003 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
6004 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
6005 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
6006 {"vclzdm", VX (4,1924), VX_MASK, POWER10, 0, {VD, VA, VB}},
6007 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
6008 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
6009 {"vcmpgtsq.", VXR(4, 903,1), VXR_MASK, POWER10, 0, {VD, VA, VB}},
6010 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
6011 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
6012 {"vmodsw", VX (4,1931), VX_MASK, POWER10, 0, {VD, VA, VB}},
6013 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
6014 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
6015 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
6016 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
6017 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
6018 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
6019 {"vctzdm", VX (4,1988), VX_MASK, POWER10, 0, {VD, VA, VB}},
6020 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
6021 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
6022 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
6023 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}},
6024 {"vmodsd", VX (4,1995), VX_MASK, POWER10, 0, {VD, VA, VB}},
6025 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
6026 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
6027 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
6028 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
6029 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
6030
6031 {"lxvp", DQXP(6,0), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}},
6032 {"stxvp", DQXP(6,1), DQXP_MASK, POWER10, PPCVLE, {XSP, DQ, RA0}},
6033
6034 {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
6035 {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
6036
6037 {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
6038 {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
6039
6040 {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
6041
6042 {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE|EXT, {OBF, RA, UISIGNOPT}},
6043 {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE|EXT, {OBF, RA, UISIGNOPT}},
6044 {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
6045 {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
6046
6047 {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE|EXT, {OBF, RA, SI}},
6048 {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE|EXT, {OBF, RA, SI}},
6049 {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
6050 {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
6051
6052 {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
6053 {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
6054 {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE|EXT, {RT, RA, NSI}},
6055
6056 {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
6057 {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
6058 {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE|EXT, {RT, RA, NSI}},
6059
6060 {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE|EXT, {RT, SI}},
6061 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE|EXT, {RT, SI}},
6062 {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
6063 {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6064 {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE|EXT, {RT, RA0, NSI}},
6065 {"la", OP(14), OP_MASK, PPCCOM, PPCVLE|EXT, {RT, D, RA0}},
6066
6067 {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE|EXT, {RT, SISIGNOPT}},
6068 {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE|EXT, {RT, SISIGNOPT}},
6069 {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
6070 {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
6071 {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE|EXT, {RT, RA0, NSISIGNOPT}},
6072
6073 {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDM}},
6074 {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDP}},
6075 {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BD}},
6076 {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE|EXT, {BD}},
6077 {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDM}},
6078 {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDP}},
6079 {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BD}},
6080 {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE|EXT, {BD}},
6081 {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDMA}},
6082 {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDPA}},
6083 {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDA}},
6084 {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE|EXT, {BDA}},
6085 {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDMA}},
6086 {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDPA}},
6087 {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDA}},
6088 {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE|EXT, {BDA}},
6089 {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDM}},
6090 {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDP}},
6091 {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE|EXT, {BD}},
6092 {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDM}},
6093 {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDP}},
6094 {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE|EXT, {BD}},
6095 {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDMA}},
6096 {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDPA}},
6097 {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE|EXT, {BDA}},
6098 {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDMA}},
6099 {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDPA}},
6100 {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE|EXT, {BDA}},
6101
6102 {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6103 {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6104 {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6105 {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6106 {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6107 {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6108 {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6109 {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6110 {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6111 {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6112 {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6113 {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6114 {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6115 {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6116 {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6117 {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6118 {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6119 {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6120 {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6121 {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6122 {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6123 {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6124 {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6125 {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6126 {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6127 {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6128 {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6129 {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6130 {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6131 {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6132 {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6133 {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6134 {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6135 {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6136 {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6137 {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6138 {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6139 {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6140 {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6141 {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6142 {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6143 {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6144 {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6145 {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6146 {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6147 {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6148 {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6149 {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6150 {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6151 {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6152 {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6153 {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6154 {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6155 {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6156 {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6157 {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6158 {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6159 {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6160 {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6161 {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6162 {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6163 {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6164 {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6165 {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6166 {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6167 {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BD}},
6168 {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6169 {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6170 {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6171 {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6172 {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6173 {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BD}},
6174 {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6175 {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6176 {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6177 {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6178 {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6179 {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDA}},
6180 {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6181 {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6182 {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6183 {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6184 {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6185 {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDA}},
6186
6187 {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6188 {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6189 {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6190 {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6191 {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6192 {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6193 {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6194 {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6195 {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6196 {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6197 {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6198 {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6199 {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6200 {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6201 {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6202 {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6203 {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6204 {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6205 {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6206 {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6207 {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6208 {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6209 {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6210 {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6211 {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6212 {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6213 {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6214 {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6215 {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6216 {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6217 {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6218 {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6219 {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6220 {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6221 {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6222 {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6223 {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6224 {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6225 {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6226 {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6227 {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6228 {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BD}},
6229 {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6230 {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6231 {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}},
6232 {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}},
6233 {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}},
6234 {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BD}},
6235 {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6236 {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6237 {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6238 {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6239 {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6240 {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDA}},
6241 {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6242 {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6243 {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}},
6244 {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}},
6245 {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}},
6246 {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDA}},
6247
6248 {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}},
6249 {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}},
6250 {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6251 {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}},
6252 {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}},
6253 {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6254 {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}},
6255 {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}},
6256 {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6257 {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}},
6258 {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}},
6259 {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6260 {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}},
6261 {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}},
6262 {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6263 {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}},
6264 {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}},
6265 {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6266 {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}},
6267 {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}},
6268 {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6269 {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}},
6270 {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}},
6271 {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6272
6273 {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDM}},
6274 {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDP}},
6275 {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6276 {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BD}},
6277 {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDM}},
6278 {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDP}},
6279 {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6280 {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BD}},
6281 {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDMA}},
6282 {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDPA}},
6283 {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6284 {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BDA}},
6285 {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDMA}},
6286 {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDPA}},
6287 {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6288 {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BDA}},
6289
6290 {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}},
6291 {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}},
6292 {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6293 {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}},
6294 {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}},
6295 {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6296 {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}},
6297 {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}},
6298 {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6299 {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}},
6300 {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}},
6301 {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6302 {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}},
6303 {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}},
6304 {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6305 {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}},
6306 {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}},
6307 {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6308 {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}},
6309 {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}},
6310 {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6311 {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}},
6312 {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}},
6313 {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6314
6315 {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDM}},
6316 {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDP}},
6317 {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6318 {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BD}},
6319 {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDM}},
6320 {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDP}},
6321 {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}},
6322 {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BD}},
6323 {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDMA}},
6324 {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDPA}},
6325 {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6326 {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BDA}},
6327 {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDMA}},
6328 {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDPA}},
6329 {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}},
6330 {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BDA}},
6331
6332 {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BDM}},
6333 {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BDP}},
6334 {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
6335 {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BDM}},
6336 {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BDP}},
6337 {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
6338 {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BDMA}},
6339 {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BDPA}},
6340 {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
6341 {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BDMA}},
6342 {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BDPA}},
6343 {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
6344
6345 {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
6346 {"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
6347 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
6348 {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
6349 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
6350 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
6351
6352 {"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
6353 {"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
6354 {"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
6355 {"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
6356
6357 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
6358
6359 {"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE|EXT, {RT}},
6360 {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
6361 {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE|EXT, {RT, NDXD}},
6362
6363 {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}},
6364 {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}},
6365 {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}},
6366 {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}},
6367 {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}},
6368 {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}},
6369 {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}},
6370 {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}},
6371 {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}},
6372 {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}},
6373 {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}},
6374 {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}},
6375 {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}},
6376 {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE|EXT, {BH}},
6377 {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}},
6378 {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE|EXT, {BH}},
6379 {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}},
6380 {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}},
6381 {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}},
6382 {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}},
6383 {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}},
6384 {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}},
6385 {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}},
6386 {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}},
6387
6388 {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6389 {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6390 {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6391 {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6392 {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6393 {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6394 {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6395 {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6396 {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6397 {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6398 {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6399 {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6400 {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6401 {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6402 {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6403 {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6404 {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6405 {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6406 {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6407 {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6408 {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6409 {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6410 {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6411 {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6412 {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6413 {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6414 {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6415 {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6416 {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6417 {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6418 {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6419 {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6420 {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6421 {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6422 {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6423 {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6424 {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6425 {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6426 {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6427 {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6428 {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6429 {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6430 {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6431 {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6432 {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6433 {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6434 {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6435 {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6436 {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6437 {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6438 {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6439 {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6440 {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6441 {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6442 {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6443 {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6444 {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6445 {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6446 {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6447 {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6448 {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6449 {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6450 {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6451 {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6452 {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6453 {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6454 {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6455 {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6456 {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6457 {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6458 {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6459 {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6460 {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6461 {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6462 {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6463 {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6464 {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6465 {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6466 {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6467 {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6468 {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6469 {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6470 {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6471 {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6472 {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6473 {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6474 {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6475 {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6476 {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6477 {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6478 {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6479 {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6480 {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6481 {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6482 {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6483 {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6484 {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6485 {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6486 {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6487 {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6488 {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6489 {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6490 {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6491 {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6492 {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6493 {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6494 {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6495 {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6496 {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6497 {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6498 {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6499 {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6500 {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6501 {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6502 {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6503 {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6504 {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}},
6505 {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6506 {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6507 {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6508 {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6509 {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6510 {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6511 {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6512 {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6513 {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6514 {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6515 {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6516 {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6517 {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6518 {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6519 {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6520 {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6521 {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6522 {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6523 {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6524 {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6525 {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6526 {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6527 {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6528
6529 {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6530 {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6531 {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6532 {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6533 {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6534 {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6535 {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6536 {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6537 {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6538 {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6539 {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6540 {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6541 {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6542 {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6543 {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6544 {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE|EXT, {BI, BH}},
6545 {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6546 {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6547 {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6548 {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE|EXT, {BI, BH}},
6549 {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6550 {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6551 {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6552 {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6553 {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6554 {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6555 {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6556 {"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6557 {"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6558 {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6559 {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6560 {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6561 {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6562 {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6563 {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6564 {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6565 {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6566 {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6567 {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6568 {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE|EXT, {BI, BH}},
6569 {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6570 {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6571 {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6572 {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE|EXT, {BI, BH}},
6573 {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6574 {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6575 {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6576 {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6577
6578 {"bclr-", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BH}},
6579 {"bclr+", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BH}},
6580 {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
6581 {"bcr", XLLK(19,16,0), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}},
6582 {"bclrl-", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BH}},
6583 {"bclrl+", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BH}},
6584 {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
6585 {"bcrl", XLLK(19,16,1), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}},
6586
6587 {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
6588
6589 {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE|EXT, {BT, BAB}},
6590 {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
6591
6592 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
6593 {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
6594 {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
6595 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
6596
6597 {"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
6598 {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
6599
6600 {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
6601
6602 {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
6603
6604 {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
6605
6606 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
6607 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
6608
6609 {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE|EXT, {BTAB}},
6610 {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
6611
6612 {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
6613
6614 {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
6615
6616 {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
6617
6618 {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
6619
6620 {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE|EXT, {BTAB}},
6621 {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
6622
6623 {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
6624 {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
6625
6626 {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
6627
6628 {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
6629
6630 {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
6631
6632 {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE|EXT, {BT, BAB}},
6633 {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
6634
6635 {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
6636 {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
6637
6638 {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE|EXT, {BH}},
6639 {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE|EXT, {BH}},
6640 {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6641 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6642 {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6643 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6644 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6645 {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6646 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6647 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6648 {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6649 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6650 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6651 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6652 {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6653 {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6654 {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6655 {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6656 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6657 {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6658 {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6659 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6660 {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6661 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6662 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6663 {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6664 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6665 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6666 {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6667 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6668 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6669 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6670 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6671 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6672 {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6673 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6674 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6675 {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6676 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6677 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6678 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6679 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6680 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6681 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6682 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6683 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6684 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6685 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6686 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6687 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6688 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6689 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6690 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6691 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6692 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6693 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6694 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6695 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6696 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6697 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6698 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6699 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6700 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6701 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6702 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6703 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6704 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6705 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6706 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6707 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6708 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6709 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6710 {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6711 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6712 {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6713 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6714 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6715 {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6716 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6717 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6718 {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6719 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6720 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6721 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6722 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6723 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6724 {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6725 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6726 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6727 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6728 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6729 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6730 {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6731 {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6732 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6733 {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6734 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6735 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6736 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6737 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6738 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}},
6739 {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}},
6740 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6741 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6742 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6743 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6744 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6745 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6746 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6747 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6748 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6749 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6750 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6751 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6752 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6753 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6754 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6755 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6756 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6757 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6758 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6759 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}},
6760
6761 {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6762 {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6763 {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6764 {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6765 {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6766 {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6767 {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6768 {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6769 {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6770 {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6771 {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6772 {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6773 {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6774 {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6775 {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}},
6776 {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}},
6777 {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6778 {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6779 {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6780 {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}},
6781
6782 {"bcctr-", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BH}},
6783 {"bcctr+", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BH}},
6784 {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
6785 {"bcc", XLLK(19,528,0), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}},
6786 {"bcctrl-", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BH}},
6787 {"bcctrl+", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BH}},
6788 {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
6789 {"bccl", XLLK(19,528,1), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}},
6790
6791 {"bdnztar", XLO(19,BODNZ,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6792 {"bdnztarl", XLO(19,BODNZ,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6793 {"bdztar", XLO(19,BODZ,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6794 {"bdztarl", XLO(19,BODZ,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6795 {"btar", XLO(19,BOU,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6796 {"btarl", XLO(19,BOU,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6797 {"bdnztar-", XLO(19,BODNZM4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6798 {"bdnztarl-", XLO(19,BODNZM4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6799 {"bdnztar+", XLO(19,BODNZP4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6800 {"bdnztarl+", XLO(19,BODNZP4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6801 {"bdztar-", XLO(19,BODZM4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6802 {"bdztarl-", XLO(19,BODZM4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6803 {"bdztar+", XLO(19,BODZP4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6804 {"bdztarl+", XLO(19,BODZP4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}},
6805
6806 {"bgetar", XLOCB(19,BOF,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6807 {"bnltar", XLOCB(19,BOF,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6808 {"bgetarl", XLOCB(19,BOF,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6809 {"bnltarl", XLOCB(19,BOF,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6810 {"bletar", XLOCB(19,BOF,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6811 {"bngtar", XLOCB(19,BOF,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6812 {"bletarl", XLOCB(19,BOF,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6813 {"bngtarl", XLOCB(19,BOF,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6814 {"bnetar", XLOCB(19,BOF,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6815 {"bnetarl", XLOCB(19,BOF,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6816 {"bnstar", XLOCB(19,BOF,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6817 {"bnutar", XLOCB(19,BOF,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6818 {"bnstarl", XLOCB(19,BOF,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6819 {"bnutarl", XLOCB(19,BOF,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6820 {"bgetar-", XLOCB(19,BOFM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6821 {"bnltar-", XLOCB(19,BOFM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6822 {"bgetarl-",XLOCB(19,BOFM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6823 {"bnltarl-",XLOCB(19,BOFM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6824 {"bletar-", XLOCB(19,BOFM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6825 {"bngtar-", XLOCB(19,BOFM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6826 {"bletarl-",XLOCB(19,BOFM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6827 {"bngtarl-",XLOCB(19,BOFM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6828 {"bnetar-", XLOCB(19,BOFM4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6829 {"bnetarl-",XLOCB(19,BOFM4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6830 {"bnstar-", XLOCB(19,BOFM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6831 {"bnutar-", XLOCB(19,BOFM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6832 {"bnstarl-",XLOCB(19,BOFM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6833 {"bnutarl-",XLOCB(19,BOFM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6834 {"bgetar+", XLOCB(19,BOFP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6835 {"bnltar+", XLOCB(19,BOFP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6836 {"bgetarl+",XLOCB(19,BOFP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6837 {"bnltarl+",XLOCB(19,BOFP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6838 {"bletar+", XLOCB(19,BOFP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6839 {"bngtar+", XLOCB(19,BOFP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6840 {"bletarl+",XLOCB(19,BOFP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6841 {"bngtarl+",XLOCB(19,BOFP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6842 {"bnetar+", XLOCB(19,BOFP4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6843 {"bnetarl+",XLOCB(19,BOFP4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6844 {"bnstar+", XLOCB(19,BOFP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6845 {"bnutar+", XLOCB(19,BOFP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6846 {"bnstarl+",XLOCB(19,BOFP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6847 {"bnutarl+",XLOCB(19,BOFP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6848 {"blttar", XLOCB(19,BOT,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6849 {"blttarl", XLOCB(19,BOT,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6850 {"bgttar", XLOCB(19,BOT,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6851 {"bgttarl", XLOCB(19,BOT,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6852 {"beqtar", XLOCB(19,BOT,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6853 {"beqtarl", XLOCB(19,BOT,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6854 {"bsotar", XLOCB(19,BOT,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6855 {"buntar", XLOCB(19,BOT,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6856 {"bsotarl", XLOCB(19,BOT,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6857 {"buntarl", XLOCB(19,BOT,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6858 {"blttar-", XLOCB(19,BOTM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6859 {"blttarl-",XLOCB(19,BOTM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6860 {"bgttar-", XLOCB(19,BOTM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6861 {"bgttarl-",XLOCB(19,BOTM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6862 {"beqtar-", XLOCB(19,BOTM4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6863 {"beqtarl-",XLOCB(19,BOTM4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6864 {"bsotar-", XLOCB(19,BOTM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6865 {"buntar-", XLOCB(19,BOTM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6866 {"bsotarl-",XLOCB(19,BOTM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6867 {"buntarl-",XLOCB(19,BOTM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6868 {"blttar+", XLOCB(19,BOTP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6869 {"blttarl+",XLOCB(19,BOTP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6870 {"bgttar+", XLOCB(19,BOTP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6871 {"bgttarl+",XLOCB(19,BOTP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6872 {"beqtar+", XLOCB(19,BOTP4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6873 {"beqtarl+",XLOCB(19,BOTP4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6874 {"bsotar+", XLOCB(19,BOTP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6875 {"buntar+", XLOCB(19,BOTP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6876 {"bsotarl+",XLOCB(19,BOTP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6877 {"buntarl+",XLOCB(19,BOTP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}},
6878
6879 {"bdnzftar", XLO(19,BODNZF,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6880 {"bdnzftarl", XLO(19,BODNZF,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6881 {"bdzftar", XLO(19,BODZF,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6882 {"bdzftarl", XLO(19,BODZF,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6883
6884 {"bftar", XLO(19,BOF,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6885 {"bftarl", XLO(19,BOF,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6886 {"bftar-", XLO(19,BOFM4,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6887 {"bftarl-", XLO(19,BOFM4,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6888 {"bftar+", XLO(19,BOFP4,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6889 {"bftarl+", XLO(19,BOFP4,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6890
6891 {"bdnzttar", XLO(19,BODNZT,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6892 {"bdnzttarl", XLO(19,BODNZT,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6893 {"bdzttar", XLO(19,BODZT,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6894 {"bdzttarl", XLO(19,BODZT,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6895
6896 {"bttar", XLO(19,BOT,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6897 {"bttarl", XLO(19,BOT,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6898 {"bttar-", XLO(19,BOTM4,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6899 {"bttarl-", XLO(19,BOTM4,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6900 {"bttar+", XLO(19,BOTP4,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6901 {"bttarl+", XLO(19,BOTP4,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}},
6902
6903 {"bctar-", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE|EXT, {BOM, BI, BH}},
6904 {"bctar+", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE|EXT, {BOP, BI, BH}},
6905 {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
6906 {"bctarl-", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE|EXT, {BOM, BI, BH}},
6907 {"bctarl+", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE|EXT, {BOP, BI, BH}},
6908 {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
6909
6910 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
6911 {"inslwi", M(20,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ILWn, ILWb}},
6912 {"insrwi", M(20,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, IRWn, IRWb}},
6913 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
6914
6915 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
6916 {"inslwi.", M(20,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ILWn, ILWb}},
6917 {"insrwi.", M(20,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, IRWn, IRWb}},
6918 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
6919
6920 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SH}},
6921 {"rotrwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RRWn}},
6922 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, MB}},
6923 {"clrrwi", M(21,0), MSHMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CRWn}},
6924 {"slwi", M(21,0), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SLWn}},
6925 {"srwi", MME(21,31,0), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SRWn}},
6926 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
6927 {"extlwi", M(21,0), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ELWn, SH}},
6928 {"extrwi", MME(21,31,0), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ERWn, ERWb}},
6929 {"clrlslwi", M(21,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CSLWb, CSLWn}},
6930 {"sli", M(21,0), MMB_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SLWn}},
6931 {"sri", MME(21,31,0), MME_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SRWn}},
6932 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
6933 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SH}},
6934 {"rotrwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RRWn}},
6935 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, MB}},
6936 {"clrrwi.", M(21,1), MSHMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CRWn}},
6937 {"slwi.", M(21,1), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SLWn}},
6938 {"srwi.", MME(21,31,1), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SRWn}},
6939 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
6940 {"extlwi.", M(21,1), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ELWn, SH}},
6941 {"extrwi.", MME(21,31,1), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ERWn, ERWb}},
6942 {"clrlslwi.", M(21,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CSLWb, CSLWn}},
6943 {"sli.", M(21,1), MMB_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SLWn}},
6944 {"sri.", MME(21,31,1), MME_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SRWn}},
6945 {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
6946
6947 {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
6948 {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
6949
6950 {"svstep", SVL(22,19,0), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
6951 {"svstep.", SVL(22,19,1), SVL_MASK, SVP64, PPCVLE, {RT, SVi, vf}},
6952
6953 {"svshape", SVM(22,25), SVM_MASK, SVP64, PPCVLE, {SVxd, SVyd, SVzd, SVrm, vf}},
6954
6955 {"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
6956 {"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
6957
6958 {"svindex", SVI(22,41), SVI_MASK, SVP64, PPCVLE, {SVG, rmm, SVd, ew, yx, mm, sk}},
6959
6960 {"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
6961
6962 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
6963 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
6964 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
6965 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
6966 {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
6967 {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
6968
6969 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE|EXT, {0}},
6970 {"exser", 0x63ff0000, 0xffffffff, POWER9, PPCVLE|EXT, {0}},
6971 {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
6972 {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
6973
6974 {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
6975 {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
6976
6977 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE|EXT, {0}},
6978 {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
6979 {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
6980
6981 {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
6982 {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
6983
6984 {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
6985 {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
6986
6987 {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
6988 {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
6989
6990 {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, SH6}},
6991 {"rotrdi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RRDn}},
6992 {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, MB6}},
6993 {"srdi", MD(30,0,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SRDn}},
6994 {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
6995 {"extrdi", MD(30,0,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, ERDn, ERDb}},
6996 {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, SH6}},
6997 {"rotrdi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RRDn}},
6998 {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, MB6}},
6999 {"srdi.", MD(30,0,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SRDn}},
7000 {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
7001 {"extrdi.", MD(30,0,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, ERDn, ERDb}},
7002
7003 {"clrrdi", MD(30,1,0), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, CRDn}},
7004 {"sldi", MD(30,1,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SLDn}},
7005 {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
7006 {"extldi", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, ELDn, SH6}},
7007 {"clrrdi.", MD(30,1,1), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, CRDn}},
7008 {"sldi.", MD(30,1,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SLDn}},
7009 {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
7010 {"extldi.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, ELDn, SH6}},
7011
7012 {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
7013 {"clrlsldi", MD(30,2,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, CSLDb, CSLDn}},
7014 {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
7015 {"clrlsldi.", MD(30,2,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, CSLDb, CSLDn}},
7016
7017 {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
7018 {"insrdi", MD(30,3,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, IRDn, IRDb}},
7019 {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
7020 {"insrdi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, IRDn, IRDb}},
7021
7022 {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RB}},
7023 {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
7024 {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RB}},
7025 {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
7026
7027 {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
7028 {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
7029
7030 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, EXT, {OBF, RA, RB}},
7031 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, EXT, {OBF, RA, RB}},
7032 {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
7033 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
7034
7035 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7036 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7037 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7038 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7039 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7040 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7041 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7042 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7043 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7044 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7045 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7046 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7047 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7048 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7049 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7050 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7051 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7052 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7053 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7054 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7055 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7056 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7057 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7058 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7059 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7060 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7061 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7062 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7063 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, EXT, {0}},
7064 {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, EXT, {RA, RB}},
7065 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, EXT, {RA, RB}},
7066 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
7067 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
7068
7069 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7070 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7071 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
7072
7073 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7074 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7075 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, EXT, {RT, RB, RA}},
7076 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7077 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7078 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, EXT, {RT, RB, RA}},
7079
7080 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
7081 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
7082
7083 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7084 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7085 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7086 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7087
7088 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
7089 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
7090
7091 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
7092
7093 {"lxvrbx", X(31,13), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7094
7095 {"isellt", XISEL(31,15,0), X_MASK, PPCISEL, EXT, {RT, RA0, RB}},
7096 {"iselgt", XISEL(31,15,1), X_MASK, PPCISEL, EXT, {RT, RA0, RB}},
7097 {"iseleq", XISEL(31,15,2), X_MASK, PPCISEL, EXT, {RT, RA0, RB}},
7098 {"isel", XISEL(31,15,0), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, BC}},
7099
7100 {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
7101 {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
7102 {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
7103 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
7104
7105 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
7106 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
7107
7108 {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
7109
7110 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
7111
7112 {"icbt", X(31,22), X_MASK, POWER5|BOOKE|PPCE300, 0, {CT, RA0, RB}},
7113
7114 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
7115 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
7116
7117 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
7118 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
7119 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
7120 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
7121
7122 {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
7123 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
7124 {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
7125 {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
7126
7127 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
7128 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
7129
7130 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
7131 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
7132
7133 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
7134 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
7135
7136 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7137
7138 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
7139 {"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, EXT, {0}},
7140 {"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, EXT, {0}},
7141 {"wait", X(31,30), XWCPL_MASK, POWER10, 0, {WC, PL}},
7142 {"wait", X(31,30), XWC_MASK, POWER9, POWER10, {WC}},
7143
7144 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7145
7146 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, EXT, {OBF, RA, RB}},
7147 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, EXT, {OBF, RA, RB}},
7148 {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
7149 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
7150
7151 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7152 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7153 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
7154
7155 {"lxvrhx", X(31,45), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7156
7157 {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}},
7158
7159 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7160
7161 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
7162
7163 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
7164
7165 {"lxvrwx", X(31,77), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7166
7167 {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
7168 {"sub", XO(31,40,0,0), XO_MASK, PPC, EXT, {RT, RB, RA}},
7169 {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
7170 {"sub.", XO(31,40,0,1), XO_MASK, PPC, EXT, {RT, RB, RA}},
7171
7172 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}},
7173 {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, EXT, {RA, VS}},
7174 {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
7175 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
7176
7177 {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
7178
7179 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
7180
7181 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
7182
7183 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
7184 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
7185
7186 {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
7187 {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
7188
7189 {"cntlzdm", X(31,59), X_MASK, POWER10, 0, {RA, RS, RB}},
7190
7191 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
7192 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
7193
7194 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, EXT, {0}},
7195 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, EXT, {0}},
7196 {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
7197
7198 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
7199
7200 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, EXT, {RA, RB}},
7201 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, EXT, {RA, RB}},
7202 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, EXT, {RA, RB}},
7203 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, EXT, {RA, RB}},
7204 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, EXT, {RA, RB}},
7205 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, EXT, {RA, RB}},
7206 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, EXT, {RA, RB}},
7207 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, EXT, {RA, RB}},
7208 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, EXT, {RA, RB}},
7209 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, EXT, {RA, RB}},
7210 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, EXT, {RA, RB}},
7211 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, EXT, {RA, RB}},
7212 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, EXT, {RA, RB}},
7213 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, EXT, {RA, RB}},
7214 {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, EXT, {RA, RB}},
7215 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
7216
7217 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
7218 {"subwus", XO(31,72,0,0), XO_MASK, FUTURE, EXT, {RT, RB, RA}},
7219 {"subwus.", XO(31,72,0,1), XO_MASK, FUTURE, EXT, {RT, RB, RA}},
7220 {"subdus", XO(31,72,1,0), XO_MASK, FUTURE, EXT, {RT, RB, RA}},
7221 {"subdus.", XO(31,72,1,1), XO_MASK, FUTURE, EXT, {RT, RB, RA}},
7222 {"subfus", XO(31,72,0,0), XOL_MASK, FUTURE, 0, {RT, XOL, RA, RB}},
7223 {"subfus.", XO(31,72,0,1), XOL_MASK, FUTURE, 0, {RT, XOL, RA, RB}},
7224 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
7225 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
7226
7227 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
7228 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
7229
7230 {"msgsndu", XRTRA(31,78,0,0), XRTRA_MASK, POWER9, 0, {RB}},
7231 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
7232 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
7233
7234 {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
7235
7236 {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
7237
7238 {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
7239
7240 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476|EXT, {RA0, RB}},
7241 {"dcbflp", XOPL2(31,86,3), XRT_MASK, POWER9, PPC476|EXT, {RA0, RB}},
7242 {"dcbfps", XOPL3(31,86,4), XRT_MASK, POWER10, PPC476|EXT, {RA0, RB}},
7243 {"dcbstps", XOPL3(31,86,6), XRT_MASK, POWER10, PPC476|EXT, {RA0, RB}},
7244 {"dcbf", X(31,86), XL3RT_MASK, POWER10, PPC476, {RA0, RB, L3OPT}},
7245 {"dcbf", X(31,86), XLRT_MASK, PPC, POWER10, {RA0, RB, L2OPT}},
7246
7247 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
7248
7249 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7250
7251 {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
7252
7253 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7254 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
7255
7256 {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
7257 {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
7258
7259 {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
7260 {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
7261
7262 {"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7263
7264 {"msgclru", XRTRA(31,110,0,0), XRTRA_MASK, POWER9, 0, {RB}},
7265 {"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}},
7266
7267 {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
7268
7269 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}},
7270 {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, EXT, {RA, VS}},
7271 {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
7272
7273 {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
7274
7275 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
7276
7277 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
7278
7279 {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
7280
7281 {"not", XRC(31,124,0), X_MASK, COM, EXT, {RA, RSB}},
7282 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
7283 {"not.", XRC(31,124,1), X_MASK, COM, EXT, {RA, RSB}},
7284 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
7285
7286 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
7287
7288 {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
7289
7290 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
7291
7292 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7293
7294 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7295 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
7296
7297 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7298 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7299 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7300 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7301
7302 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7303 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7304 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7305 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7306
7307 {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
7308
7309 {"stxvrbx", X(31,141), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7310
7311 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
7312 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
7313
7314 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, EXT, {RS}},
7315 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
7316 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
7317
7318 {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
7319
7320 {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
7321 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
7322 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
7323
7324 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
7325
7326 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
7327
7328 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
7329 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
7330
7331 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
7332 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
7333
7334 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
7335 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
7336
7337 {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
7338
7339 {"brw", X(31,155), XRB_MASK, POWER10, 0, {RA, RS}},
7340 {"pdepd", X(31,156), X_MASK, POWER10, 0, {RA, RS, RB}},
7341
7342 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7343
7344 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7345
7346 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
7347
7348 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7349
7350 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7351 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
7352
7353 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
7354
7355 {"stxvrhx", X(31,173), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7356
7357 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
7358 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
7359
7360 {"dmxxmfacc", XVA(31,177,0), XACC_MASK, POWER10, 0, {ACC}},
7361 {"xxmfacc", XVA(31,177,0), XACC_MASK, POWER10, 0, {ACC}},
7362 {"dmxxmtacc", XVA(31,177,1), XACC_MASK, POWER10, 0, {ACC}},
7363 {"xxmtacc", XVA(31,177,1), XACC_MASK, POWER10, 0, {ACC}},
7364 {"dmsetdmrz", XVA(31,177,2), XDMR_MASK, FUTURE, 0, {DMR}},
7365 {"dmsetaccz", XVA(31,177,3), XACC_MASK, POWER10, 0, {ACC}},
7366 {"xxsetaccz", XVA(31,177,3), XACC_MASK, POWER10, 0, {ACC}},
7367 {"dmmr", XVA(31,177,6), XDMRDMR_MASK,FUTURE, 0, {DMR, DMRAB}},
7368 {"dmxor", XVA(31,177,7), XDMRDMR_MASK,FUTURE, 0, {DMR, DMRAB}},
7369
7370 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
7371
7372 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, EXT, {FRT, RA}},
7373 {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, EXT, {VD, RA}},
7374 {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
7375 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
7376
7377 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
7378
7379 {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}},
7380 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
7381
7382 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
7383 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
7384
7385 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
7386 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
7387
7388 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
7389
7390 {"brd", X(31,187), XRB_MASK, POWER10, 0, {RA, RS}},
7391 {"pextd", X(31,188), X_MASK, POWER10, 0, {RA, RS, RB}},
7392
7393 {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
7394
7395 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
7396
7397 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7398 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
7399
7400 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
7401 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
7402 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
7403 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
7404
7405 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
7406 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
7407 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
7408 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
7409
7410 {"stxvrwx", X(31,205), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7411
7412 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
7413
7414 {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
7415
7416 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, EXT, {FRT, RA}},
7417 {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, EXT, {VD, RA}},
7418 {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
7419 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
7420
7421 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
7422
7423 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
7424
7425 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
7426
7427 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
7428 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
7429
7430 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
7431 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
7432
7433 {"brh", X(31,219), XRB_MASK, POWER10, 0, {RA, RS}},
7434 {"cfuged", X(31,220), X_MASK, POWER10, 0, {RA, RS, RB}},
7435
7436 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7437
7438 {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
7439
7440 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7441
7442 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7443 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
7444
7445 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
7446 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
7447 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
7448 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
7449
7450 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
7451 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
7452
7453 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
7454 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
7455 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
7456 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
7457
7458 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7459 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7460 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7461 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7462
7463 {"stxvrdx", X(31,237), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
7464
7465 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
7466 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
7467 {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
7468 {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
7469
7470 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, EXT, {FRT, RA}},
7471 {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, EXT, {VD, RA}},
7472 {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
7473
7474 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, EXT, {RA0, RB}},
7475 {"dcbtstct", X(31,246), X_MASK, POWER4, EXT, {RA0, RB, THCT}},
7476 {"dcbtstds", X(31,246), X_MASK, POWER4, EXT, {RA0, RB, THDS}},
7477 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
7478 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
7479 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
7480
7481 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
7482
7483 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
7484 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
7485
7486 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
7487
7488 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7489
7490 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
7491 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
7492
7493 {"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}},
7494
7495 {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
7496
7497 {"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}},
7498 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
7499
7500 {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
7501 {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
7502
7503 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
7504
7505 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7506 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7507 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
7508 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
7509
7510 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
7511
7512 {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
7513 {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
7514
7515 {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
7516
7517 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}},
7518 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
7519
7520 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
7521
7522 {"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
7523
7524 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
7525 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
7526
7527 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, EXT, {RA0, RB}},
7528 {"dcbna", XRT(31,278,0x11), XRT_MASK, POWER10, EXT, {RA0, RB}},
7529 {"dcbtct", X(31,278), X_MASK, POWER4, EXT, {RA0, RB, THCT}},
7530 {"dcbtds", X(31,278), X_MASK, POWER4, EXT, {RA0, RB, THDS}},
7531 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
7532 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
7533 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
7534
7535 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
7536
7537 {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
7538
7539 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
7540 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
7541
7542 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7543
7544 {"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}},
7545
7546 {"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}},
7547 {"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}},
7548
7549 {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
7550
7551 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
7552
7553 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
7554 {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
7555 {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
7556 {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
7557
7558 {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
7559
7560 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
7561
7562 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
7563
7564 {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
7565
7566 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
7567 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
7568
7569 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7570
7571 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
7572 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
7573 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
7574 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
7575 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
7576 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
7577 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
7578 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
7579 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
7580 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
7581 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
7582 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
7583 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
7584 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
7585 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
7586 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
7587 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
7588 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
7589 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
7590 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
7591 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
7592 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
7593 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
7594 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
7595 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
7596 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
7597 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
7598 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
7599 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
7600 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
7601 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
7602 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
7603 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
7604 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
7605 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
7606 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
7607
7608 {"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}},
7609
7610 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
7611
7612 {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
7613 {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
7614
7615 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
7616
7617 {"lxvpx", X(31,333), XX1_MASK, POWER10, 0, {XTP, RA0, RB}},
7618
7619 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
7620 {"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}},
7621
7622 {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
7623
7624 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, EXT, {RT}},
7625 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, EXT, {RT}},
7626 {"mfudscr", XSPR(31,339, 3), XSPR_MASK, POWER9, EXT, {RS}},
7627 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN|EXT, {RT}},
7628 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN|EXT, {RT}},
7629 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, EXT, {RT}},
7630 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, EXT, {RT}},
7631 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, EXT, {RT}},
7632 {"mfuamr", XSPR(31,339, 13), XSPR_MASK, POWER9, EXT, {RS}},
7633 {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, EXT, {RT}},
7634 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, EXT, {RT}},
7635 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN|EXT, {RT}},
7636 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN|EXT, {RT}},
7637 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1|EXT, {RT}},
7638 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, EXT, {RT}},
7639 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN|EXT, {RT}},
7640 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, EXT, {RT}},
7641 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, EXT, {RT}},
7642 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, EXT, {RT}},
7643 {"mfamr", XSPR(31,339, 29), XSPR_MASK, POWER7, EXT, {RS}},
7644 {"mfpidr", XSPR(31,339, 48), XSPR_MASK, POWER10, EXT, {RS}},
7645 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, EXT, {RT}},
7646 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, EXT, {RT}},
7647 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, EXT, {RT}},
7648 {"mfiamr", XSPR(31,339, 61), XSPR_MASK, POWER10, EXT, {RS}},
7649 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, EXT, {RT}},
7650 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, EXT, {RT}},
7651 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, EXT, {RT}},
7652 {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, EXT, {RT}},
7653 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, EXT, {RT}},
7654 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, EXT, {RT}},
7655 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, EXT, {RT}},
7656 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, EXT, {RT}},
7657 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, EXT, {RT}},
7658 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, EXT, {RT}},
7659 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, EXT, {RT}},
7660 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, EXT, {RT}},
7661 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, EXT, {RT}},
7662 {"mffscr", XSPR(31,339,153), XSPR_MASK, POWER10, EXT, {RS}},
7663 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, EXT, {RT}},
7664 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, EXT, {RT}},
7665 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, EXT, {RT}},
7666 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, EXT, {RT}},
7667 {"mfuamor", XSPR(31,339,157), XSPR_MASK, POWER7, EXT, {RS}},
7668 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, EXT, {RT}},
7669 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, EXT, {RT}},
7670 {"mfpspb", XSPR(31,339,159), XSPR_MASK, POWER10, EXT, {RS}},
7671 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, EXT, {RT}},
7672 {"mfdpdes", XSPR(31,339,176), XSPR_MASK, POWER10, EXT, {RS}},
7673 {"mfdawr0", XSPR(31,339,180), XSPR_MASK, POWER10, EXT, {RS}},
7674 {"mfdawr1", XSPR(31,339,181), XSPR_MASK, POWER10, EXT, {RS}},
7675 {"mfrpr", XSPR(31,339,186), XSPR_MASK, POWER10, EXT, {RS}},
7676 {"mfciabr", XSPR(31,339,187), XSPR_MASK, POWER10, EXT, {RS}},
7677 {"mfdawrx0", XSPR(31,339,188), XSPR_MASK, POWER10, EXT, {RS}},
7678 {"mfdawrx1", XSPR(31,339,189), XSPR_MASK, POWER10, EXT, {RS}},
7679 {"mfhfscr", XSPR(31,339,190), XSPR_MASK, POWER10, EXT, {RS}},
7680 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, EXT, {RT}},
7681 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, EXT, {RT}},
7682 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, EXT, {RT, SPRG}},
7683 {"mfusprg3", XSPR(31,339,259), XSPR_MASK, POWER10, EXT, {RT}},
7684 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, EXT, {RT}},
7685 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, EXT, {RT}},
7686 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, EXT, {RT}},
7687 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, EXT, {RT}},
7688 {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, EXT, {RT}},
7689 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, EXT, {RT, TBR}},
7690 {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, EXT, {RT}},
7691 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, EXT, {RT}},
7692 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, EXT, {RT}},
7693 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, EXT, {RT}},
7694 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, EXT, {RT}},
7695 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, EXT, {RT}},
7696 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN|EXT, {RT}},
7697 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, EXT, {RT}},
7698 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, EXT, {RT}},
7699 {"mfhsprg0", XSPR(31,339,304), XSPR_MASK, POWER10, EXT, {RS}},
7700 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, EXT, {RT}},
7701 {"mfhsprg1", XSPR(31,339,305), XSPR_MASK, POWER10, EXT, {RS}},
7702 {"mfhdisr", XSPR(31,339,306), XSPR_MASK, POWER10, EXT, {RS}},
7703 {"mfhdar", XSPR(31,339,307), XSPR_MASK, POWER10, EXT, {RS}},
7704 {"mfspurr", XSPR(31,339,308), XSPR_MASK, POWER10, EXT, {RS}},
7705 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, EXT, {RT}},
7706 {"mfpurr", XSPR(31,339,309), XSPR_MASK, POWER10, EXT, {RS}},
7707 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, EXT, {RT}},
7708 {"mfhdec", XSPR(31,339,310), XSPR_MASK, POWER10, EXT, {RS}},
7709 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, EXT, {RT}},
7710 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, EXT, {RT}},
7711 {"mfhrmor", XSPR(31,339,313), XSPR_MASK, POWER10, EXT, {RS}},
7712 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, EXT, {RT}},
7713 {"mfhsrr0", XSPR(31,339,314), XSPR_MASK, POWER10, EXT, {RS}},
7714 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, EXT, {RT}},
7715 {"mfhsrr1", XSPR(31,339,315), XSPR_MASK, POWER10, EXT, {RS}},
7716 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, EXT, {RT}},
7717 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, EXT, {RT}},
7718 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, EXT, {RT}},
7719 {"mflpcr", XSPR(31,339,318), XSPR_MASK, POWER10, EXT, {RS}},
7720 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, EXT, {RT}},
7721 {"mflpidr", XSPR(31,339,319), XSPR_MASK, POWER10, EXT, {RS}},
7722 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, EXT, {RT}},
7723 {"mfhmer", XSPR(31,339,336), XSPR_MASK, POWER7, EXT, {RS}},
7724 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, EXT, {RT}},
7725 {"mfhmeer", XSPR(31,339,337), XSPR_MASK, POWER7, EXT, {RS}},
7726 {"mfpcr", XSPR(31,339,338), XSPR_MASK, POWER10, EXT, {RS}},
7727 {"mfheir", XSPR(31,339,339), XSPR_MASK, POWER10, EXT, {RS}},
7728 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, EXT, {RT}},
7729 {"mfamor", XSPR(31,339,349), XSPR_MASK, POWER7, EXT, {RS}},
7730 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, EXT, {RT}},
7731 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, EXT, {RT}},
7732 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, EXT, {RT}},
7733 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, EXT, {RT}},
7734 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, EXT, {RT}},
7735 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, EXT, {RT}},
7736 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, EXT, {RT}},
7737 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, EXT, {RT}},
7738 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, EXT, {RT}},
7739 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, EXT, {RT}},
7740 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, EXT, {RT}},
7741 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, EXT, {RT}},
7742 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, EXT, {RT}},
7743 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, EXT, {RT}},
7744 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, EXT, {RT}},
7745 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, EXT, {RT}},
7746 {"mftir", XSPR(31,339,446), XSPR_MASK, POWER10, EXT, {RS}},
7747 {"mfptcr", XSPR(31,339,464), XSPR_MASK, POWER10, EXT, {RS}},
7748 {"mfusprg0", XSPR(31,339,496), XSPR_MASK, POWER10, EXT, {RS}},
7749 {"mfusprg1", XSPR(31,339,497), XSPR_MASK, POWER10, EXT, {RS}},
7750 {"mfurmor", XSPR(31,339,505), XSPR_MASK, POWER10, EXT, {RS}},
7751 {"mfusrr0", XSPR(31,339,506), XSPR_MASK, POWER10, EXT, {RS}},
7752 {"mfusrr1", XSPR(31,339,507), XSPR_MASK, POWER10, EXT, {RS}},
7753 {"mfsmfctrl", XSPR(31,339,511), XSPR_MASK, POWER10, EXT, {RS}},
7754 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, EXT, {RT}},
7755 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, EXT, {RT}},
7756 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, EXT, {RT}},
7757 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, EXT, {RT}},
7758 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, EXT, {RT}},
7759 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, EXT, {RT}},
7760 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, EXT, {RT}},
7761 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN|EXT, {RT, SPRBAT}},
7762 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN|EXT, {RT, SPRBAT}},
7763 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN|EXT, {RT, SPRBAT}},
7764 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN|EXT, {RT, SPRBAT}},
7765 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, EXT, {RT}},
7766 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, EXT, {RT}},
7767 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, EXT, {RT}},
7768 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, EXT, {RT}},
7769 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, EXT, {RT}},
7770 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, EXT, {RT}},
7771 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, EXT, {RT}},
7772 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, EXT, {RT}},
7773 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, EXT, {RT}},
7774 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN|EXT, {RT}},
7775 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, EXT, {RT}},
7776 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, EXT, {RT}},
7777 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, EXT, {RT}},
7778 {"mfusier2", XSPR(31,339,736), XSPR_MASK, POWER10, EXT, {RT}},
7779 {"mfsier2", XSPR(31,339,736), XSPR_MASK, POWER10, EXT, {RT}},
7780 {"mfusier3", XSPR(31,339,737), XSPR_MASK, POWER10, EXT, {RT}},
7781 {"mfsier3", XSPR(31,339,737), XSPR_MASK, POWER10, EXT, {RT}},
7782 {"mfummcr3", XSPR(31,339,738), XSPR_MASK, POWER10, EXT, {RT}},
7783 {"mfmmcr3", XSPR(31,339,738), XSPR_MASK, POWER10, EXT, {RT}},
7784 {"mfusier", XSPR(31,339,768), XSPR_MASK, POWER10, EXT, {RT}},
7785 {"mfsier", XSPR(31,339,768), XSPR_MASK, POWER10, EXT, {RT}},
7786 {"mfummcr2", XSPR(31,339,769), XSPR_MASK, POWER9, EXT, {RT}},
7787 {"mfmmcr2", XSPR(31,339,769), XSPR_MASK, POWER9, EXT, {RT}},
7788 {"mfummcra", XSPR(31,339,770), XSPR_MASK, POWER9, EXT, {RS}},
7789 {"mfmmcra", XSPR(31,339,770), XSPR_MASK, POWER7, EXT, {RS}},
7790 {"mfupmc1", XSPR(31,339,771), XSPR_MASK, POWER9, EXT, {RT}},
7791 {"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER7, EXT, {RT}},
7792 {"mfupmc2", XSPR(31,339,772), XSPR_MASK, POWER9, EXT, {RT}},
7793 {"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER7, EXT, {RT}},
7794 {"mfupmc3", XSPR(31,339,773), XSPR_MASK, POWER9, EXT, {RT}},
7795 {"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER7, EXT, {RT}},
7796 {"mfupmc4", XSPR(31,339,774), XSPR_MASK, POWER9, EXT, {RT}},
7797 {"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER7, EXT, {RT}},
7798 {"mfupmc5", XSPR(31,339,775), XSPR_MASK, POWER9, EXT, {RT}},
7799 {"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER7, EXT, {RT}},
7800 {"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, EXT, {RT}},
7801 {"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER7, EXT, {RT}},
7802 {"mfummcr0", XSPR(31,339,779), XSPR_MASK, POWER9, EXT, {RS}},
7803 {"mfmmcr0", XSPR(31,339,779), XSPR_MASK, POWER7, EXT, {RS}},
7804 {"mfusiar", XSPR(31,339,780), XSPR_MASK, POWER9, EXT, {RS}},
7805 {"mfsiar", XSPR(31,339,780), XSPR_MASK, POWER9, EXT, {RS}},
7806 {"mfusdar", XSPR(31,339,781), XSPR_MASK, POWER9, EXT, {RS}},
7807 {"mfsdar", XSPR(31,339,781), XSPR_MASK, POWER9, EXT, {RS}},
7808 {"mfummcr1", XSPR(31,339,782), XSPR_MASK, POWER9, EXT, {RS}},
7809 {"mfmmcr1", XSPR(31,339,782), XSPR_MASK, POWER7, EXT, {RS}},
7810 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, EXT, {RT}},
7811 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, EXT, {RT}},
7812 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, EXT, {RT}},
7813 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, EXT, {RT}},
7814 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, EXT, {RT}},
7815 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, EXT, {RT}},
7816 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, EXT, {RT}},
7817 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, EXT, {RT}},
7818 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, EXT, {RT}},
7819 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, EXT, {RT}},
7820 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, EXT, {RT}},
7821 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, EXT, {RT}},
7822 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, EXT, {RT}},
7823 {"mfbescrs", XSPR(31,339,800), XSPR_MASK, POWER9, EXT, {RS}},
7824 {"mfbescrsu", XSPR(31,339,801), XSPR_MASK, POWER9, EXT, {RS}},
7825 {"mfbescrr", XSPR(31,339,802), XSPR_MASK, POWER9, EXT, {RS}},
7826 {"mfbescrru", XSPR(31,339,803), XSPR_MASK, POWER9, EXT, {RS}},
7827 {"mfebbhr", XSPR(31,339,804), XSPR_MASK, POWER9, EXT, {RS}},
7828 {"mfebbrr", XSPR(31,339,805), XSPR_MASK, POWER9, EXT, {RS}},
7829 {"mfbescr", XSPR(31,339,806), XSPR_MASK, POWER9, EXT, {RS}},
7830 {"mftar", XSPR(31,339,815), XSPR_MASK, POWER9, EXT, {RS}},
7831 {"mfasdr", XSPR(31,339,816), XSPR_MASK, POWER10, EXT, {RS}},
7832 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, EXT, {RT}},
7833 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, EXT, {RT}},
7834 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, EXT, {RT}},
7835 {"mfpsscr", XSPR(31,339,823), XSPR_MASK, POWER10, EXT, {RS}},
7836 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, EXT, {RT}},
7837 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, EXT, {RT}},
7838 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, EXT, {RT}},
7839 {"mfic", XSPR(31,339,848), XSPR_MASK, POWER8, EXT, {RS}},
7840 {"mfvtb", XSPR(31,339,849), XSPR_MASK, POWER8, EXT, {RS}},
7841 {"mfhpsscr", XSPR(31,339,855), XSPR_MASK, POWER10, EXT, {RS}},
7842 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, EXT, {RT}},
7843 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, EXT, {RT}},
7844 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, EXT, {RT}},
7845 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, EXT, {RT}},
7846 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, EXT, {RT}},
7847 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, EXT, {RT}},
7848 {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER5, EXT, {RT}},
7849 {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER5, EXT, {RT}},
7850 {"mfgqr", XSPR(31,339,912), XSPRGQR_MASK, PPCPS, EXT, {RT, SPRGQR}},
7851 {"mfhid2", XSPR(31,339,920), XSPR_MASK, GEKKO, EXT, {RT}},
7852 {"mfwpar", XSPR(31,339,921), XSPR_MASK, GEKKO, EXT, {RT}},
7853 {"mfdmau", XSPR(31,339,922), XSPR_MASK, GEKKO, EXT, {RT}},
7854 {"mfdmal", XSPR(31,339,923), XSPR_MASK, GEKKO, EXT, {RT}},
7855 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, EXT, {RT}},
7856 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, EXT, {RT}},
7857 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, EXT, {RT}},
7858 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, EXT, {RT}},
7859 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, EXT, {RT}},
7860 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, EXT, {RT}},
7861 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, EXT, {RT}},
7862 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, EXT, {RT}},
7863 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, EXT, {RT}},
7864 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, EXT, {RT}},
7865 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, EXT, {RT}},
7866 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, EXT, {RT}},
7867 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, EXT, {RT}},
7868 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, EXT, {RT}},
7869 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, EXT, {RT}},
7870 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, EXT, {RT}},
7871 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, EXT, {RT}},
7872 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, EXT, {RT}},
7873 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, EXT, {RT}},
7874 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, EXT, {RT}},
7875 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, EXT, {RT}},
7876 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, EXT, {RT}},
7877 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, EXT, {RT}},
7878 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, EXT, {RT}},
7879 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, EXT, {RT}},
7880 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, EXT, {RT}},
7881 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, EXT, {RT}},
7882 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, EXT, {RT}},
7883 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, EXT, {RT}},
7884 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, EXT, {RT}},
7885 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, EXT, {RT}},
7886 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, EXT, {RT}},
7887 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, EXT, {RT}},
7888 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, EXT, {RT}},
7889 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, EXT, {RT}},
7890 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, EXT, {RT}},
7891 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, EXT, {RT}},
7892 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, EXT, {RT}},
7893 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, EXT, {RT}},
7894 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, EXT, {RT}},
7895 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, EXT, {RT}},
7896 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, EXT, {RT}},
7897 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, EXT, {RT}},
7898 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, EXT, {RT}},
7899 {"mfhid0", XSPR(31,339,1008), XSPR_MASK, GEKKO, EXT, {RT}},
7900 {"mfhid1", XSPR(31,339,1009), XSPR_MASK, GEKKO, EXT, {RT}},
7901 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, EXT, {RT}},
7902 {"mfiabr", XSPR(31,339,1010), XSPR_MASK, GEKKO, EXT, {RT}},
7903 {"mfhid4", XSPR(31,339,1011), XSPR_MASK, BROADWAY, EXT, {RT}},
7904 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, EXT, {RS}},
7905 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, EXT, {RT}},
7906 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, EXT, {RT}},
7907 {"mfdabr", XSPR(31,339,1013), XSPR_MASK, PPC750, EXT, {RT}},
7908 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, EXT, {RT}},
7909 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, EXT, {RT}},
7910 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, EXT, {RT}},
7911 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, EXT, {RT}},
7912 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, EXT, {RT}},
7913 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, EXT, {RT}},
7914 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, EXT, {RT}},
7915 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, EXT, {RT}},
7916 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, EXT, {RT}},
7917 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, EXT, {RT}},
7918 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, EXT, {RT}},
7919 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, EXT, {RT}},
7920 {"mfpir", XSPR(31,339,1023), XSPR_MASK, POWER10, EXT, {RT}},
7921 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, EXT, {RT}},
7922 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
7923
7924 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
7925
7926 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
7927 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
7928
7929 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
7930
7931 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7932
7933 {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
7934 {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
7935
7936 {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
7937 {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
7938
7939 {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
7940
7941 {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
7942
7943 {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4|EXT, {RT}},
7944 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
7945 {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4|EXT, {RT}},
7946
7947 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
7948
7949 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
7950 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
7951
7952 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
7953
7954 {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
7955
7956 {"setbc", X(31,384), XRB_MASK, POWER10, 0, {RT, BI}},
7957
7958 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
7959 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
7960
7961 {"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}},
7962
7963 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7964 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
7965
7966 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
7967 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
7968 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
7969 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
7970
7971 {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
7972 {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
7973
7974 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
7975
7976 {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
7977
7978 {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
7979
7980 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
7981
7982 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
7983 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
7984
7985 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
7986
7987 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
7988 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
7989
7990 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7991
7992 {"setbcr", X(31,416), XRB_MASK, POWER10, 0, {RT, BI}},
7993
7994 {"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}},
7995
7996 {"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}},
7997
7998 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
7999
8000 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8001 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8002 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8003 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8004
8005 {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
8006
8007 {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
8008
8009 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
8010
8011 {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
8012
8013 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
8014
8015 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
8016
8017 /* or 1,1,1 */
8018 {"cctpl", 0x7c210b78, 0xffffffff, CELL, EXT, {0}},
8019 /* or 2,2,2 */
8020 {"cctpm", 0x7c421378, 0xffffffff, CELL, EXT, {0}},
8021 /* or 3,3,3 */
8022 {"cctph", 0x7c631b78, 0xffffffff, CELL, EXT, {0}},
8023 /* or 26,26,26 */
8024 {"miso", 0x7f5ad378, 0xffffffff, POWER8|E6500, EXT, {0}},
8025 /* or 27,27,27 */
8026 {"yield", 0x7f7bdb78, 0xffffffff, POWER7, EXT, {0}},
8027 /* or 28,28,28 */
8028 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, EXT, {0}},
8029 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, EXT, {0}},
8030 /* or 29,29,29 */
8031 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, EXT, {0}},
8032 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, EXT, {0}},
8033 /* or 30,30,30 */
8034 {"mdoom", 0x7fdef378, 0xffffffff, POWER7, EXT, {0}},
8035 {"db12cyc", 0x7fdef378, 0xffffffff, CELL, EXT, {0}},
8036 /* or 31,31,31 */
8037 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, EXT, {0}},
8038
8039 {"mr", XRC(31,444,0), X_MASK, COM, EXT, {RA, RSB}},
8040 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
8041 {"mr.", XRC(31,444,1), X_MASK, COM, EXT, {RA, RSB}},
8042 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
8043
8044 {"setnbc", X(31,448), XRB_MASK, POWER10, 0, {RT, BI}},
8045
8046 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
8047 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
8048 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
8049 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
8050 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
8051 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
8052 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
8053 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
8054 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
8055 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
8056 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
8057 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
8058 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
8059 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
8060 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
8061 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
8062 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
8063 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
8064 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
8065 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
8066 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
8067 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
8068 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
8069 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
8070 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
8071 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
8072 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
8073 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
8074 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
8075 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
8076 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
8077 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
8078 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
8079 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
8080 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
8081 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
8082
8083 {"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}},
8084
8085 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
8086 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
8087
8088 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
8089 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
8090
8091 {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
8092 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
8093
8094 {"stxvpx", X(31,461), XX1_MASK, POWER10, 0, {XSP, RA0, RB}},
8095
8096 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
8097 {"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}},
8098
8099 {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
8100
8101 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, EXT, {RS}},
8102 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, EXT, {RS}},
8103 {"mtudscr", XSPR(31,467, 3), XSPR_MASK, POWER9, EXT, {RS}},
8104 {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, EXT, {RS}},
8105 {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, EXT, {RS}},
8106 {"mtuamr", XSPR(31,467, 13), XSPR_MASK, POWER9, EXT, {RS}},
8107 {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, EXT, {RS}},
8108 {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, EXT, {RS}},
8109 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN|EXT, {RS}},
8110 {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN|EXT, {RS}},
8111 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN|EXT, {RS}},
8112 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN|EXT, {RS}},
8113 {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, EXT, {RS}},
8114 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, EXT, {RS}},
8115 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN|EXT, {RS}},
8116 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, EXT, {RS}},
8117 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, EXT, {RS}},
8118 {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, EXT, {RS}},
8119 {"mtamr", XSPR(31,467, 29), XSPR_MASK, POWER7, EXT, {RS}},
8120 {"mtpidr", XSPR(31,467, 48), XSPR_MASK, POWER10, EXT, {RS}},
8121 {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, EXT, {RS}},
8122 {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, EXT, {RS}},
8123 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, EXT, {RS}},
8124 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, EXT, {RS}},
8125 {"mtiamr", XSPR(31,467, 61), XSPR_MASK, POWER10, EXT, {RS}},
8126 {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, EXT, {RS}},
8127 {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, EXT, {RS}},
8128 {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, EXT, {RS}},
8129 {"mttfhar", XSPR(31,467,128), XSPR_MASK, POWER9, EXT, {RS}},
8130 {"mttfiar", XSPR(31,467,129), XSPR_MASK, POWER9, EXT, {RS}},
8131 {"mttexasr", XSPR(31,467,130), XSPR_MASK, POWER9, EXT, {RS}},
8132 {"mttexasru", XSPR(31,467,131), XSPR_MASK, POWER9, EXT, {RS}},
8133 {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, EXT, {RS}},
8134 {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, EXT, {RS}},
8135 {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, EXT, {RS}},
8136 {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, EXT, {RS}},
8137 {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, EXT, {RS}},
8138 {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, EXT, {RS}},
8139 {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, EXT, {RS}},
8140 {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, EXT, {RS}},
8141 {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, EXT, {RS}},
8142 {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, EXT, {RS}},
8143 {"mtfscr", XSPR(31,467,153), XSPR_MASK, POWER10, EXT, {RS}},
8144 {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, EXT, {RS}},
8145 {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, EXT, {RS}},
8146 {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, EXT, {RS}},
8147 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, EXT, {RS}},
8148 {"mtuamor", XSPR(31,467,157), XSPR_MASK, POWER7, EXT, {RS}},
8149 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, EXT, {RS}},
8150 {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, EXT, {RS}},
8151 {"mtpspb", XSPR(31,467,159), XSPR_MASK, POWER10, EXT, {RS}},
8152 {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, EXT, {RS}},
8153 {"mtdpdes", XSPR(31,467,176), XSPR_MASK, POWER10, EXT, {RS}},
8154 {"mtdawr0", XSPR(31,467,180), XSPR_MASK, POWER10, EXT, {RS}},
8155 {"mtdawr1", XSPR(31,467,181), XSPR_MASK, POWER10, EXT, {RS}},
8156 {"mtrpr", XSPR(31,467,186), XSPR_MASK, POWER10, EXT, {RS}},
8157 {"mtciabr", XSPR(31,467,187), XSPR_MASK, POWER10, EXT, {RS}},
8158 {"mtdawrx0", XSPR(31,467,188), XSPR_MASK, POWER10, EXT, {RS}},
8159 {"mtdawrx1", XSPR(31,467,189), XSPR_MASK, POWER10, EXT, {RS}},
8160 {"mthfscr", XSPR(31,467,190), XSPR_MASK, POWER10, EXT, {RS}},
8161 {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, EXT, {RS}},
8162 {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, EXT, {RS}},
8163 {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, EXT, {SPRG, RS}},
8164 {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, EXT, {RS}},
8165 {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, EXT, {RS}},
8166 {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, EXT, {RS}},
8167 {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, EXT, {RS}},
8168 {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, EXT, {RS}},
8169 {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, EXT, {RS}},
8170 {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, EXT, {RS}},
8171 {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, EXT, {RS}},
8172 {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, EXT, {RS}},
8173 {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN|EXT, {RS}},
8174 {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, EXT, {RS}},
8175 {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, EXT, {RS}},
8176 {"mttbu40", XSPR(31,467,286), XSPR_MASK, POWER10, EXT, {RS}},
8177 {"mthsprg0", XSPR(31,467,304), XSPR_MASK, POWER10, EXT, {RS}},
8178 {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, EXT, {RS}},
8179 {"mthsprg1", XSPR(31,467,305), XSPR_MASK, POWER10, EXT, {RS}},
8180 {"mthdisr", XSPR(31,467,306), XSPR_MASK, POWER10, EXT, {RS}},
8181 {"mthdar", XSPR(31,467,307), XSPR_MASK, POWER10, EXT, {RS}},
8182 {"mtspurr", XSPR(31,467,308), XSPR_MASK, POWER10, EXT, {RS}},
8183 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, EXT, {RS}},
8184 {"mtpurr", XSPR(31,467,309), XSPR_MASK, POWER10, EXT, {RS}},
8185 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, EXT, {RS}},
8186 {"mthdec", XSPR(31,467,310), XSPR_MASK, POWER10, EXT, {RS}},
8187 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, EXT, {RS}},
8188 {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, EXT, {RS}},
8189 {"mthrmor", XSPR(31,467,313), XSPR_MASK, POWER10, EXT, {RS}},
8190 {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, EXT, {RS}},
8191 {"mthsrr0", XSPR(31,467,314), XSPR_MASK, POWER10, EXT, {RS}},
8192 {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, EXT, {RS}},
8193 {"mthsrr1", XSPR(31,467,315), XSPR_MASK, POWER10, EXT, {RS}},
8194 {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, EXT, {RS}},
8195 {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, EXT, {RS}},
8196 {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, EXT, {RS}},
8197 {"mtlpcr", XSPR(31,467,318), XSPR_MASK, POWER10, EXT, {RS}},
8198 {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, EXT, {RS}},
8199 {"mtlpidr", XSPR(31,467,319), XSPR_MASK, POWER10, EXT, {RS}},
8200 {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, EXT, {RS}},
8201 {"mthmer", XSPR(31,467,336), XSPR_MASK, POWER7, EXT, {RS}},
8202 {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, EXT, {RS}},
8203 {"mthmeer", XSPR(31,467,337), XSPR_MASK, POWER7, EXT, {RS}},
8204 {"mtpcr", XSPR(31,467,338), XSPR_MASK, POWER10, EXT, {RS}},
8205 {"mtheir", XSPR(31,467,339), XSPR_MASK, POWER10, EXT, {RS}},
8206 {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, EXT, {RS}},
8207 {"mtamor", XSPR(31,467,349), XSPR_MASK, POWER7, EXT, {RS}},
8208 {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, EXT, {RS}},
8209 {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, EXT, {RS}},
8210 {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, EXT, {RS}},
8211 {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, EXT, {RS}},
8212 {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, EXT, {RS}},
8213 {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, EXT, {RS}},
8214 {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, EXT, {RS}},
8215 {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, EXT, {RS}},
8216 {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, EXT, {RS}},
8217 {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, EXT, {RS}},
8218 {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, EXT, {RS}},
8219 {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, EXT, {RS}},
8220 {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, EXT, {RS}},
8221 {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, EXT, {RS}},
8222 {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, EXT, {RS}},
8223 {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, EXT, {RS}},
8224 {"mtptcr", XSPR(31,467,464), XSPR_MASK, POWER10, EXT, {RS}},
8225 {"mtusprg0", XSPR(31,467,496), XSPR_MASK, POWER10, EXT, {RS}},
8226 {"mtusprg1", XSPR(31,467,497), XSPR_MASK, POWER10, EXT, {RS}},
8227 {"mturmor", XSPR(31,467,505), XSPR_MASK, POWER10, EXT, {RS}},
8228 {"mtusrr0", XSPR(31,467,506), XSPR_MASK, POWER10, EXT, {RS}},
8229 {"mtusrr1", XSPR(31,467,507), XSPR_MASK, POWER10, EXT, {RS}},
8230 {"mtsmfctrl", XSPR(31,467,511), XSPR_MASK, POWER10, EXT, {RS}},
8231 {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, EXT, {RS}},
8232 {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, EXT, {RS}},
8233 {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, EXT, {RS}},
8234 {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, EXT, {RS}},
8235 {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, EXT, {RS}},
8236 {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, EXT, {RS}},
8237 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, EXT, {RS}},
8238 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN|EXT, {SPRBAT, RS}},
8239 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN|EXT, {SPRBAT, RS}},
8240 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN|EXT, {SPRBAT, RS}},
8241 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN|EXT, {SPRBAT, RS}},
8242 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, EXT, {RS}},
8243 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, EXT, {RS}},
8244 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, EXT, {RS}},
8245 {"mtsier2", XSPR(31,467,752), XSPR_MASK, POWER10, EXT, {RS}},
8246 {"mtsier3", XSPR(31,467,753), XSPR_MASK, POWER10, EXT, {RS}},
8247 {"mtmmcr3", XSPR(31,467,754), XSPR_MASK, POWER10, EXT, {RS}},
8248 {"mtummcr2", XSPR(31,467,769), XSPR_MASK, POWER9, EXT, {RS}},
8249 {"mtmmcr2", XSPR(31,467,769), XSPR_MASK, POWER9, EXT, {RS}},
8250 {"mtummcra", XSPR(31,467,770), XSPR_MASK, POWER9, EXT, {RS}},
8251 {"mtupmc1", XSPR(31,467,771), XSPR_MASK, POWER9, EXT, {RS}},
8252 {"mtupmc2", XSPR(31,467,772), XSPR_MASK, POWER9, EXT, {RS}},
8253 {"mtupmc3", XSPR(31,467,773), XSPR_MASK, POWER9, EXT, {RS}},
8254 {"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, EXT, {RS}},
8255 {"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, EXT, {RS}},
8256 {"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, EXT, {RS}},
8257 {"mtummcr0", XSPR(31,467,779), XSPR_MASK, POWER9, EXT, {RS}},
8258 {"mtsier", XSPR(31,467,784), XSPR_MASK, POWER10, EXT, {RS}},
8259 {"mtmmcra", XSPR(31,467,786), XSPR_MASK, POWER7, EXT, {RS}},
8260 {"mtpmc1", XSPR(31,467,787), XSPR_MASK, POWER7, EXT, {RS}},
8261 {"mtpmc2", XSPR(31,467,788), XSPR_MASK, POWER7, EXT, {RS}},
8262 {"mtpmc3", XSPR(31,467,789), XSPR_MASK, POWER7, EXT, {RS}},
8263 {"mtpmc4", XSPR(31,467,790), XSPR_MASK, POWER7, EXT, {RS}},
8264 {"mtpmc5", XSPR(31,467,791), XSPR_MASK, POWER7, EXT, {RS}},
8265 {"mtpmc6", XSPR(31,467,792), XSPR_MASK, POWER7, EXT, {RS}},
8266 {"mtmmcr0", XSPR(31,467,795), XSPR_MASK, POWER7, EXT, {RS}},
8267 {"mtsiar", XSPR(31,467,796), XSPR_MASK, POWER10, EXT, {RS}},
8268 {"mtsdar", XSPR(31,467,797), XSPR_MASK, POWER10, EXT, {RS}},
8269 {"mtmmcr1", XSPR(31,467,798), XSPR_MASK, POWER7, EXT, {RS}},
8270 {"mtbescrs", XSPR(31,467,800), XSPR_MASK, POWER9, EXT, {RS}},
8271 {"mtbescrsu", XSPR(31,467,801), XSPR_MASK, POWER9, EXT, {RS}},
8272 {"mtbescrr", XSPR(31,467,802), XSPR_MASK, POWER9, EXT, {RS}},
8273 {"mtbescrru", XSPR(31,467,803), XSPR_MASK, POWER9, EXT, {RS}},
8274 {"mtebbhr", XSPR(31,467,804), XSPR_MASK, POWER9, EXT, {RS}},
8275 {"mtebbrr", XSPR(31,467,805), XSPR_MASK, POWER9, EXT, {RS}},
8276 {"mtbescr", XSPR(31,467,806), XSPR_MASK, POWER9, EXT, {RS}},
8277 {"mttar", XSPR(31,467,815), XSPR_MASK, POWER9, EXT, {RS}},
8278 {"mtasdr", XSPR(31,467,816), XSPR_MASK, POWER10, EXT, {RS}},
8279 {"mtpsscr", XSPR(31,467,823), XSPR_MASK, POWER10, EXT, {RS}},
8280 {"mtic", XSPR(31,467,848), XSPR_MASK, POWER8, EXT, {RS}},
8281 {"mtvtb", XSPR(31,467,849), XSPR_MASK, POWER8, EXT, {RS}},
8282 {"mthpsscr", XSPR(31,467,855), XSPR_MASK, POWER10, EXT, {RS}},
8283 {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, EXT, {RS}},
8284 {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, EXT, {RS}},
8285 {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, EXT, {RS}},
8286 {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, EXT, {RS}},
8287 {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, EXT, {RS}},
8288 {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, EXT, {RS}},
8289 {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER5, EXT, {RS}},
8290 {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER5, EXT, {RS}},
8291 {"mtgqr", XSPR(31,467,912), XSPRGQR_MASK, PPCPS, EXT, {SPRGQR, RS}},
8292 {"mthid2", XSPR(31,467,920), XSPR_MASK, GEKKO, EXT, {RS}},
8293 {"mtwpar", XSPR(31,467,921), XSPR_MASK, GEKKO, EXT, {RS}},
8294 {"mtdmau", XSPR(31,467,922), XSPR_MASK, GEKKO, EXT, {RS}},
8295 {"mtdmal", XSPR(31,467,923), XSPR_MASK, GEKKO, EXT, {RS}},
8296 {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, EXT, {RS}},
8297 {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, EXT, {RS}},
8298 {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, EXT, {RS}},
8299 {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, EXT, {RS}},
8300 {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, EXT, {RS}},
8301 {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, EXT, {RS}},
8302 {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, EXT, {RS}},
8303 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, EXT, {RS}},
8304 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, EXT, {RS}},
8305 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, EXT, {RS}},
8306 {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, EXT, {RS}},
8307 {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, EXT, {RS}},
8308 {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, EXT, {RS}},
8309 {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, EXT, {RS}},
8310 {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, EXT, {RS}},
8311 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, EXT, {RS}},
8312 {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, EXT, {RS}},
8313 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, EXT, {RS}},
8314 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, EXT, {RS}},
8315 {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, EXT, {RS}},
8316 {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, EXT, {RS}},
8317 {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, EXT, {RS}},
8318 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, EXT, {RS}},
8319 {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, EXT, {RS}},
8320 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, EXT, {RS}},
8321 {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, EXT, {RS}},
8322 {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, EXT, {RS}},
8323 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, EXT, {RS}},
8324 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, EXT, {RS}},
8325 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, EXT, {RS}},
8326 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, EXT, {RS}},
8327 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, EXT, {RS}},
8328 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, EXT, {RS}},
8329 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, EXT, {RS}},
8330 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, EXT, {RS}},
8331 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, EXT, {RS}},
8332 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, EXT, {RS}},
8333 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, EXT, {RS}},
8334 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, EXT, {RS}},
8335 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, EXT, {RS}},
8336 {"mthid0", XSPR(31,467,1008), XSPR_MASK, GEKKO, EXT, {RS}},
8337 {"mthid1", XSPR(31,467,1009), XSPR_MASK, GEKKO, EXT, {RS}},
8338 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, EXT, {RS}},
8339 {"mtiabr", XSPR(31,467,1010), XSPR_MASK, GEKKO, EXT, {RS}},
8340 {"mthid4", XSPR(31,467,1011), XSPR_MASK, BROADWAY, EXT, {RS}},
8341 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, EXT, {RS}},
8342 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, EXT, {RS}},
8343 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, EXT, {RS}},
8344 {"mtdabr", XSPR(31,467,1013), XSPR_MASK, PPC750, EXT, {RS}},
8345 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, EXT, {RS}},
8346 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, EXT, {RS}},
8347 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, EXT, {RS}},
8348 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, EXT, {RS}},
8349 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, EXT, {RS}},
8350 {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, EXT, {RS}},
8351 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, EXT, {RS}},
8352 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, EXT, {RS}},
8353 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, EXT, {RS}},
8354 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, EXT, {RS}},
8355 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, EXT, {RS}},
8356 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, EXT, {RS}},
8357 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, EXT, {RS}},
8358 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
8359
8360 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
8361
8362 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
8363 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
8364
8365 {"setnbcr", X(31,480), XRB_MASK, POWER10, 0, {RT, BI}},
8366
8367 {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
8368
8369 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}},
8370
8371 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
8372
8373 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
8374
8375 {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
8376 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
8377
8378 {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
8379 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
8380
8381 {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
8382 {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
8383
8384 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
8385
8386 {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
8387 {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
8388
8389 {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
8390
8391 {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
8392
8393 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
8394
8395 {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
8396
8397 {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
8398 {"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
8399
8400 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
8401
8402 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
8403 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
8404
8405 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8406 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8407 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, EXT, {RT, RB, RA}},
8408 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8409 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8410 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, EXT, {RT, RB, RA}},
8411
8412 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8413 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8414 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8415 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8416
8417 {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
8418 {"lxvrl", X(31,525), XX1_MASK, PPCVSXF, 0, {XT6, RA0, RB}},
8419
8420 {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
8421
8422 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
8423
8424 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
8425 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
8426
8427 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
8428 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
8429
8430 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
8431
8432 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8433 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8434 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8435 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8436
8437 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
8438 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
8439
8440 {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
8441 {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
8442
8443 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
8444 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
8445
8446 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
8447 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
8448
8449 {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
8450 {"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
8451
8452 {"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}},
8453
8454 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
8455
8456 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
8457 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
8458
8459 {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
8460 {"subo", XO(31,40,1,0), XO_MASK, PPC, EXT, {RT, RB, RA}},
8461 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
8462 {"subo.", XO(31,40,1,1), XO_MASK, PPC, EXT, {RT, RB, RA}},
8463
8464 {"lxvrll", X(31,557), XX1_MASK, PPCVSXF, 0, {XT6, RA0, RB}},
8465
8466 {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
8467
8468 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
8469
8470 {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
8471 {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
8472
8473 {"cnttzdm", X(31,571), X_MASK, POWER10, 0, {RA, RS, RB}},
8474
8475 {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
8476
8477 {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
8478 {"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
8479
8480 {"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}},
8481
8482 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
8483
8484 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
8485
8486 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
8487 {"lxvprl", X(31,589), XX1_MASK, PPCVSXF, 0, {XTP, RA0, RB}},
8488
8489 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
8490
8491 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
8492 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
8493
8494 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476|EXT, {0}},
8495 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500|EXT, {0}},
8496 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, EXT, {0}},
8497 {"phwsync", XSYNCLS(31,598,4,0), 0xffffffff, POWER10, EXT, {0}},
8498 {"plwsync", XSYNCLS(31,598,5,0), 0xffffffff, POWER10, EXT, {0}},
8499 {"stncisync", XSYNCLS(31,598,1,1), 0xffffffff, POWER10, EXT, {0}},
8500 {"stcisync", XSYNCLS(31,598,0,2), 0xffffffff, POWER10, EXT, {0}},
8501 {"stsync", XSYNCLS(31,598,0,3), 0xffffffff, POWER10, EXT, {0}},
8502 {"sync", X(31,598), XSYNCLS_MASK, POWER10, BOOKE|PPC476, {LS3, SC2}},
8503 {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
8504 {"sync", X(31,598), XSYNC_MASK, PPCCOM, POWER10|BOOKE|PPC476, {LS}},
8505 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
8506 {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
8507 {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
8508 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
8509
8510 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
8511
8512 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
8513 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
8514
8515 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
8516
8517 {"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}},
8518
8519 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
8520
8521 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
8522
8523 {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
8524 {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
8525
8526 {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
8527 {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
8528
8529 {"lxvprll", X(31,621), XX1_MASK, PPCVSXF, 0, {XTP, RA0, RB}},
8530
8531 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
8532
8533 {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
8534
8535 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
8536
8537 {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
8538 {"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
8539
8540 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
8541 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
8542
8543 {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
8544 {"stxvrl", X(31,653), XX1_MASK, PPCVSXF, 0, {XS6, RA0, RB}},
8545
8546 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
8547
8548 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8549 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8550 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8551 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8552
8553 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8554 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8555 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8556 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8557
8558 {"hashstp", X(31,658), XRC_MASK, POWER8, 0, {RB, DW, RA0}},
8559
8560 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
8561
8562 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
8563
8564 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
8565 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
8566
8567 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
8568 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
8569
8570 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
8571
8572 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
8573 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
8574
8575 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
8576 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
8577
8578 {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
8579 {"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
8580
8581 {"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}},
8582
8583 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
8584 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
8585
8586 {"stxvrll", X(31,685), XX1_MASK, PPCVSXF, 0, {XS6, RA0, RB}},
8587
8588 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
8589 {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
8590
8591 {"hashchkp", X(31,690), XRC_MASK, POWER8, 0, {RB, DW, RA0}},
8592
8593 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
8594
8595 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
8596
8597 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
8598 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
8599
8600 {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
8601 {"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
8602
8603 {"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}},
8604
8605 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
8606
8607 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
8608
8609 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
8610 {"stxvprl", X(31,717), XX1_MASK, PPCVSXF, 0, {XSP, RA0, RB}},
8611
8612 {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
8613
8614 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
8615 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
8616 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
8617 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
8618
8619 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
8620 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
8621 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
8622 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
8623
8624 {"hashst", X(31,722), XRC_MASK, POWER8, 0, {RB, DW, RA0}},
8625
8626 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
8627 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
8628
8629 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
8630
8631 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
8632
8633 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
8634 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
8635
8636 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
8637 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
8638
8639 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
8640 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
8641
8642 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
8643
8644 {"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}},
8645
8646 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
8647
8648 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
8649
8650 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
8651 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
8652 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
8653 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
8654
8655 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
8656 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
8657
8658 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
8659 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
8660 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
8661 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
8662
8663 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8664 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8665 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8666 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8667
8668 {"stxvprll", X(31,749), XX1_MASK, PPCVSXF, 0, {XSP, RA0, RB}},
8669
8670 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, EXT, {0}},
8671 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, EXT, {0}},
8672 {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
8673
8674 {"hashchk", X(31,754), XRC_MASK, POWER8, 0, {RB, DW, RA0}},
8675
8676 {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
8677
8678 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
8679 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
8680
8681 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
8682
8683 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
8684 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
8685
8686 {"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}},
8687
8688 {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
8689
8690 {"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}},
8691 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
8692 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
8693
8694 {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
8695 {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
8696
8697 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8698 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8699 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
8700 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
8701
8702 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
8703 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
8704
8705 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
8706 {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
8707
8708 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
8709
8710 {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
8711
8712 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
8713
8714 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
8715
8716 {"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
8717 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
8718
8719 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8720 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8721 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8722 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8723
8724 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
8725 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
8726
8727 {"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}},
8728 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
8729
8730 {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}},
8731 {"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}},
8732 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
8733
8734 {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
8735 {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
8736
8737 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
8738
8739 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
8740
8741 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
8742
8743 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
8744
8745 {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
8746 {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
8747
8748 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
8749
8750 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
8751 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
8752 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
8753 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
8754
8755 {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
8756 {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
8757
8758 {"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}},
8759
8760 {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
8761
8762 {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
8763 {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
8764
8765 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
8766 {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
8767
8768 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
8769
8770 {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
8771
8772 {"slbiag", X(31,850), XRLARB_MASK, POWER10, 0, {RS, A_L}},
8773 {"slbiag", X(31,850), XRARB_MASK, POWER9, POWER10, {RS}},
8774
8775 {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
8776 {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
8777
8778 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
8779
8780 {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
8781 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
8782 {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
8783 {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
8784
8785 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
8786
8787 {"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}},
8788
8789 {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
8790 {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
8791
8792 {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
8793 {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
8794
8795 {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
8796
8797 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
8798
8799 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
8800
8801 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
8802
8803 {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
8804
8805 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
8806
8807 {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
8808 {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
8809
8810 {"paste.", XRC(31,902,1), XLRT_MASK, POWER10, 0, {RA0, RB, L1OPT}},
8811 {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, POWER10, {RA0, RB}},
8812
8813 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
8814 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
8815
8816 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8817 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8818 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8819 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8820
8821 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
8822 {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
8823
8824 {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
8825
8826 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
8827 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
8828
8829 {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
8830 {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
8831
8832 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
8833
8834 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
8835
8836 {"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
8837 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
8838
8839 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
8840 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
8841
8842 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
8843 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
8844
8845 {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
8846 {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
8847 {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
8848 {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
8849
8850 {"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}},
8851 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
8852
8853 {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}},
8854
8855 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, EXT, {RA0, RB}},
8856 {"wclrall", X(31,934), XRARB_MASK, PPCA2, EXT, {L2}},
8857 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
8858
8859 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
8860
8861 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8862 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8863 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8864 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
8865
8866 {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
8867 {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
8868
8869 {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
8870
8871 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2|EXT, {RT, RA}},
8872 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2|EXT, {RT, RA}},
8873 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
8874
8875 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
8876
8877 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
8878 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
8879
8880 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
8881
8882 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
8883 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
8884
8885 {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
8886 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
8887
8888 {"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}},
8889
8890 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
8891 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
8892
8893 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
8894 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
8895
8896 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
8897 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
8898
8899 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
8900 {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
8901
8902 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
8903 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, EXT, {RT, RA}},
8904 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, EXT, {RT, RA}},
8905 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
8906
8907 {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
8908
8909 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
8910
8911 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
8912
8913 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
8914
8915 {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
8916 {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
8917
8918 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
8919
8920 {"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}},
8921
8922 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
8923
8924 {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
8925 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
8926
8927 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
8928 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
8929
8930 {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
8931 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
8932
8933 {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
8934
8935 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
8936
8937 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
8938
8939 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
8940
8941 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
8942 {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
8943 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
8944
8945 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
8946
8947 {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
8948 {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
8949
8950 {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
8951 {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
8952
8953 {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
8954
8955 {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
8956
8957 {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
8958 {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
8959
8960 {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
8961 {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
8962
8963 {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
8964
8965 {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
8966
8967 {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
8968
8969 {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
8970
8971 {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
8972
8973 {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
8974
8975 {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
8976
8977 {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
8978
8979 {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
8980 {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
8981
8982 {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
8983 {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
8984
8985 {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
8986
8987 {"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
8988
8989 {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
8990
8991 {"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
8992
8993 {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
8994
8995 {"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
8996
8997 {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
8998
8999 {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
9000
9001 {"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
9002 {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
9003 {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
9004
9005 {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
9006 {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
9007 {"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
9008 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
9009 {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
9010
9011 {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
9012 {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
9013 {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
9014
9015 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9016 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9017
9018 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
9019 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
9020
9021 {"dmxvi8ger4pp",XX3(59,2), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9022 {"xvi8ger4pp", XX3(59,2), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9023 {"dmxvi8ger4", XX3(59,3), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9024 {"xvi8ger4", XX3(59,3), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9025
9026 {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9027 {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9028
9029 {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9030 {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9031
9032 {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9033 {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9034
9035 {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
9036 {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
9037
9038 {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
9039 {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
9040 {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
9041 {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
9042
9043 {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
9044 {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
9045
9046 {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
9047 {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
9048 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
9049 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
9050
9051 {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9052 {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9053
9054 {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9055 {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9056
9057 {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9058 {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9059
9060 {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9061 {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9062
9063 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9064 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9065
9066 {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
9067 {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
9068
9069 {"dmxvi8gerx4pp", XX3(59,10), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9070 {"dmxvi8gerx4", XX3(59,11), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9071
9072 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
9073 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
9074
9075 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
9076 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
9077
9078 {"dmxvf16ger2pp",XX3(59,18), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9079 {"xvf16ger2pp", XX3(59,18), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9080 {"dmxvf16ger2", XX3(59,19), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9081 {"xvf16ger2", XX3(59,19), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9082
9083 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
9084 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
9085
9086 {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
9087 {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
9088
9089 {"dmxvf32gerpp",XX3(59,26), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9090 {"xvf32gerpp", XX3(59,26), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9091 {"dmxvf32ger", XX3(59,27), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9092 {"xvf32ger", XX3(59,27), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9093
9094 {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
9095
9096 {"dmxvi4ger8pp",XX3(59,34), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9097 {"xvi4ger8pp", XX3(59,34), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9098 {"dmxvi4ger8", XX3(59,35), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9099 {"xvi4ger8", XX3(59,35), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9100
9101 {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
9102
9103 {"dmxvi16ger2spp",XX3(59,42), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9104 {"xvi16ger2spp", XX3(59,42), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9105 {"dmxvi16ger2s", XX3(59,43), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9106 {"xvi16ger2s", XX3(59,43), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9107
9108 {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
9109
9110 {"dmxvbf16ger2pp",XX3(59,50), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9111 {"xvbf16ger2pp", XX3(59,50), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9112 {"dmxvbf16ger2", XX3(59,51), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9113 {"xvbf16ger2", XX3(59,51), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9114
9115 {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
9116
9117 {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
9118 {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
9119
9120 {"dmxvf64gerpp",XX3(59,58), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
9121 {"xvf64gerpp", XX3(59,58), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
9122 {"dmxvf64ger", XX3(59,59), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
9123 {"xvf64ger", XX3(59,59), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
9124
9125 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9126 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9127
9128 {"dmxvf16gerx2pp", XX3(59,66), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9129 {"dmxvf16gerx2", XX3(59,67), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9130
9131 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9132 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9133
9134 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
9135 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
9136
9137 {"dmxvbf16gerx2pp", XX3(59,74), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9138 {"dmxvi16ger2", XX3(59,75), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9139 {"xvi16ger2", XX3(59,75), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9140
9141 {"dmxvf16ger2np", XX3(59,82), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9142 {"xvf16ger2np", XX3(59,82), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9143 {"dmxvf16gerx2np",XX3(59,83), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9144
9145 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9146 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9147
9148 {"dmxvf32gernp", XX3(59,90), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9149 {"xvf32gernp", XX3(59,90), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9150 {"dmxvbf16gerx2", XX3(59,91), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9151
9152 {"dmxvi8gerx4spp",XX3(59,98), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9153 {"dmxvi8ger4spp", XX3(59,99), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9154 {"xvi8ger4spp", XX3(59,99), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9155
9156 {"dmxvi16ger2pp", XX3(59,107), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9157 {"xvi16ger2pp", XX3(59,107), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9158
9159 {"dmxvbf16ger2np",XX3(59,114), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9160 {"xvbf16ger2np", XX3(59,114), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9161 {"dmxvbf16gerx2np",XX3(59,115), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9162
9163 {"dmxvf64gernp", XX3(59,122), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
9164 {"xvf64gernp", XX3(59,122), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
9165
9166 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9167 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9168
9169 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9170 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9171
9172 {"dmxvf16ger2pn", XX3(59,146), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9173 {"xvf16ger2pn", XX3(59,146), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9174 {"dmxvf16gerx2pn",XX3(59,147), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9175
9176 {"dmxvf32gerpn",XX3(59,154), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9177 {"xvf32gerpn", XX3(59,154), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9178
9179 {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
9180
9181 {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
9182 {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
9183
9184 {"dmxvbf16ger2pn",XX3(59,178), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9185 {"xvbf16ger2pn", XX3(59,178), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9186 {"dmxvbf16gerx2pn", XX3(59,179),XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9187
9188 {"dmxvf64gerpn",XX3(59,186), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
9189 {"xvf64gerpn", XX3(59,186), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
9190
9191 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9192 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9193
9194 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
9195 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
9196
9197 {"dmxvf16gerx2nn", XX3(59,202), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9198
9199 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
9200 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
9201
9202 {"dmxvf16ger2nn", XX3(59,210), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9203 {"xvf16ger2nn", XX3(59,210), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9204
9205 {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
9206 {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
9207
9208 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9209 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9210
9211 {"dmxvf32gernn",XX3(59,218), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9212 {"xvf32gernn", XX3(59,218), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9213
9214 {"dmxvbf16gerx2nn", XX3(59,234),XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
9215
9216 {"dmxvbf16ger2nn",XX3(59,242), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9217 {"xvbf16ger2nn", XX3(59,242), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
9218
9219 {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
9220 {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
9221
9222 {"dmxvf64gernn",XX3(59,250), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
9223 {"xvf64gernn", XX3(59,250), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
9224
9225 {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9226 {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9227 {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
9228 {"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9229 {"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
9230 {"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
9231 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
9232 {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9233 {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9234 {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6, DMEX}},
9235 {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XA6, XB6}},
9236 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}},
9237 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XA6, XB6}},
9238 {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
9239 {"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9240 {"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
9241 {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9242 {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9243 {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9244 {"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9245 {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9246 {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9247 {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9248 {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9249 {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9250 {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
9251 {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9252 {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9253 {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9254 {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9255 {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9256 {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9257 {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
9258 {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9259 {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9260 {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9261 {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9262 {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9263 {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9264 {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9265 {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
9266 {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9267 {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9268 {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9269 {"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9270 {"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
9271 {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9272 {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
9273 {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9274 {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9275 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9276 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9277 {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9278 {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9279 {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9280 {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9281 {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9282 {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9283 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9284 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9285 {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9286 {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9287 {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9288 {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9289 {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9290 {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
9291 {"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
9292 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9293 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9294 {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9295 {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9296 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
9297 {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9298 {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9299 {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9300 {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
9301 {"lxvkq", XVA(60,360,31), XVA_MASK&~1, POWER10, PPCVLE, {XT6, UIM5}},
9302 {"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
9303 {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9304 {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9305 {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
9306 {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9307 {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9308 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9309 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9310 {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9311 {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9312 {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9313 {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9314 {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9315 {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9316 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9317 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9318 {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9319 {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9320 {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9321 {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9322 {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9323 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9324 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9325 {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9326 {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9327 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
9328 {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9329 {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9330 {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9331 {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9332 {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9333 {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
9334 {"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9335 {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9336 {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9337 {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9338 {"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
9339 {"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9340 {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9341 {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9342 {"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
9343 {"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9344 {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9345 {"xxmr", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}},
9346 {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9347 {"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
9348 {"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
9349 {"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9350 {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9351 {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9352 {"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
9353 {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9354 {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9355 {"xxlnot", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}},
9356 {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9357 {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9358 {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9359 {"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
9360 {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9361 {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9362 {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9363 {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9364 {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9365 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
9366 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
9367 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9368 {"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9369 {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9370 {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9371 {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9372 {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9373 {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9374 {"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
9375 {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9376 {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
9377 {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9378 {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9379 {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9380 {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9381 {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9382 {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9383 {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9384 {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9385 {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9386 {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9387 {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}},
9388 {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9389 {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9390 {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9391 {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9392 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
9393 {"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9394 {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9395 {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9396 {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9397 {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9398 {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9399 {"dmxxextfdmr512",XX3(60,226), XX3DMR_MASK, FUTURE, PPCVLE, {XA5p, XB5p, DMR, P1}},
9400 {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9401 {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9402 {"xxgenpcvbm", X(60,916), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
9403 {"xxgenpcvhm", X(60,917), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
9404 {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
9405 {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9406 {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9407 {"dmxxinstdmr512",XX3(60,234), XX3DMR_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB5p,P1}},
9408 {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9409 {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9410 {"xxgenpcvwm", X(60,948), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
9411 {"xxgenpcvdm", X(60,949), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}},
9412 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9413 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9414 {"xvtlsbb", XX2VA(60,475,2),XX2BF_MASK, POWER10, PPCVLE, {BF, XB6}},
9415 {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9416 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9417 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9418 {"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9419 {"xvcvbf16spn", XX2VA(60,475,16),XX2_MASK, PPCVSX4, PPCVLE, {XT6, XB6}},
9420 {"xvcvspbf16", XX2VA(60,475,17),XX2_MASK, PPCVSX4, PPCVLE, {XT6, XB6}},
9421 {"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9422 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9423 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9424 {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
9425 {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}},
9426 {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9427 {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9428 {"dmxxextfdmr256",XX2(60,484), XX2DMR_MASK, FUTURE, PPCVLE, {XB5p, DMR, P2}},
9429 {"dmxxinstdmr256",XX2(60,485), XX2DMR_MASK, FUTURE, PPCVLE, {DMR, XB5p, P2}},
9430 {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9431 {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9432 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
9433 {"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
9434 {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
9435 {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9436 {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
9437
9438 {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
9439 {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
9440
9441 {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
9442 {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
9443 {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
9444 {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
9445 {"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
9446 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
9447 {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
9448
9449 {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
9450 {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
9451 {"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
9452
9453 {"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
9454
9455 {"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9456 {"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9457
9458 {"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
9459 {"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
9460
9461 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9462 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9463
9464 {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
9465 {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
9466
9467 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
9468 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
9469
9470 {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
9471 {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
9472
9473 {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
9474 {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
9475 {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
9476 {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
9477
9478 {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
9479 {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
9480 {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
9481 {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
9482
9483 {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9484 {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
9485 {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9486 {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
9487
9488 {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9489 {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
9490 {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9491 {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
9492
9493 {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9494 {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
9495 {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
9496 {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
9497
9498 {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
9499 {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
9500
9501 {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9502 {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9503
9504 {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
9505 {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
9506 {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
9507 {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
9508
9509 {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
9510 {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
9511 {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
9512 {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
9513
9514 {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
9515 {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
9516 {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
9517 {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
9518
9519 {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9520 {"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
9521 {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9522 {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
9523
9524 {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9525 {"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
9526 {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9527 {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
9528
9529 {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9530 {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
9531 {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9532 {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
9533
9534 {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9535 {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
9536 {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
9537 {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
9538
9539 {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
9540
9541 {"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9542 {"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9543
9544 {"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
9545 {"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
9546
9547 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9548 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9549
9550 {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
9551
9552 {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BTF}},
9553 {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BTF}},
9554
9555 {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
9556 {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
9557
9558 {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
9559
9560 {"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
9561 {"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
9562
9563 {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
9564 {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
9565
9566 {"xscmpeqqp", X(63,68), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9567
9568 {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BTF}},
9569 {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BTF}},
9570
9571 {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
9572 {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
9573
9574 {"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
9575 {"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
9576
9577 {"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
9578 {"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
9579
9580 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9581
9582 {"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
9583
9584 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
9585
9586 {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
9587
9588 {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
9589 {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
9590 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
9591 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
9592
9593 {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
9594 {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
9595
9596 {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
9597 {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
9598 {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
9599 {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
9600
9601 {"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
9602
9603 {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
9604
9605 {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
9606
9607 {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
9608
9609 {"xscmpgeqp", X(63,196), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9610
9611 {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
9612
9613 {"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
9614 {"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
9615
9616 {"xscmpgtqp", X(63,228), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9617
9618 {"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9619 {"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9620
9621 {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
9622 {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
9623
9624 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9625 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9626
9627 {"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
9628 {"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
9629
9630 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9631 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9632
9633 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9634 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9635
9636 {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
9637 {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
9638
9639 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9640 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9641
9642 {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
9643 {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
9644
9645 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9646 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9647
9648 {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
9649 {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
9650
9651 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9652 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9653
9654 {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
9655 {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
9656
9657 {"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9658 {"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9659
9660 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9661 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9662
9663 {"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9664 {"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9665
9666 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9667 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9668
9669 {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
9670 {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
9671
9672 {"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
9673 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
9674 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
9675 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
9676 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
9677 {"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
9678
9679 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
9680
9681 {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
9682
9683 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
9684 {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
9685
9686 {"xsmaxcqp", X(63,676), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9687
9688 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
9689
9690 {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
9691 {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
9692 {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
9693 {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
9694
9695 {"xsmincqp", X(63,740), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9696
9697 {"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
9698 {"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
9699
9700 {"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9701 {"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9702
9703 {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9704 {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9705 {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9706 {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9707 {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9708 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9709 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9710
9711 {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
9712 {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
9713 {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
9714 {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
9715
9716 {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
9717 {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
9718 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
9719 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
9720
9721 {"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
9722 {"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
9723
9724 {"xscvqpuqz", XVA(63,836,0), XVA_MASK, POWER10, PPCVLE, {VD, VB}},
9725 {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9726 {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9727 {"xscvuqqp", XVA(63,836,3), XVA_MASK, POWER10, PPCVLE, {VD, VB}},
9728 {"xscvqpsqz", XVA(63,836,8), XVA_MASK, POWER10, PPCVLE, {VD, VB}},
9729 {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9730 {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9731 {"xscvsqqp", XVA(63,836,11), XVA_MASK, POWER10, PPCVLE, {VD, VB}},
9732 {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9733 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9734 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9735 {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9736 {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
9737
9738 {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
9739
9740 {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
9741 {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
9742 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
9743 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
9744
9745 {"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
9746 {"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
9747
9748 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9749
9750 {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
9751 {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
9752
9753 {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
9754 {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
9755
9756 {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
9757
9758 {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
9759 {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
9760
9761 {"dcffixqq", XVA(63,994,0), XVA_MASK, POWER10, PPCVLE, {FRTp, VB}},
9762 {"dctfixqq", XVA(63,994,1), XVA_MASK, POWER10, PPCVLE, {VD, FRBp}},
9763 };
9764
9765 const unsigned int powerpc_num_opcodes = ARRAY_SIZE (powerpc_opcodes);
9766 \f
9767 /* The opcode table for 8-byte prefix instructions.
9768
9769 The format of this opcode table is the same as the main opcode table. */
9770
9771 const struct powerpc_opcode prefix_opcodes[] = {
9772 {"pnop", PMRR, PREFIX_MASK, POWER10, 0, {0}},
9773 {"pli", PMLS|OP(14), P_DRAPCREL_MASK, POWER10, EXT, {RT, SI34}},
9774 {"pla", PMLS|OP(14), P_D_MASK, POWER10, EXT, {RT, D34, PRA0, PCREL1}},
9775 {"paddi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, SI34, PCREL}},
9776 {"psubi", PMLS|OP(14), P_D_MASK, POWER10, EXT, {RT, RA0, NSI34, PCREL}},
9777 {"xxsplti32dx", P8RR|VSOP(32,0), P_VSI_MASK, POWER10, 0, {XTS, IX, IMM32}},
9778 {"xxspltidp", P8RR|VSOP(32,2), P_VS_MASK, POWER10, 0, {XTS, IMM32}},
9779 {"xxspltiw", P8RR|VSOP(32,3), P_VS_MASK, POWER10, 0, {XTS, IMM32}},
9780 {"plwz", PMLS|OP(32), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
9781 {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9782 {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9783 {"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9784 {"xxblendvd", P8RR|XX4(33,3), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9785 {"xxpermx", P8RR|XX4(34,0), P_UXX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM3}},
9786 {"xxeval", P8RR|XX4(34,1), P_U8XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM8}},
9787 {"plbz", PMLS|OP(34), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
9788 {"pstw", PMLS|OP(36), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
9789 {"pstb", PMLS|OP(38), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
9790 {"plhz", PMLS|OP(40), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
9791 {"plwa", P8LS|OP(41), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
9792 {"plxsd", P8LS|OP(42), P_D_MASK, POWER10, 0, {VD, D34, PRA0, PCREL}},
9793 {"plha", PMLS|OP(42), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
9794 {"plxssp", P8LS|OP(43), P_D_MASK, POWER10, 0, {VD, D34, PRA0, PCREL}},
9795 {"psth", PMLS|OP(44), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
9796 {"pstxsd", P8LS|OP(46), P_D_MASK, POWER10, 0, {VS, D34, PRA0, PCREL}},
9797 {"pstxssp", P8LS|OP(47), P_D_MASK, POWER10, 0, {VS, D34, PRA0, PCREL}},
9798 {"plfs", PMLS|OP(48), P_D_MASK, POWER10, 0, {FRT, D34, PRA0, PCREL}},
9799 {"plxv", P8LS|OP(50), P_D_MASK&~OP(1), POWER10, 0, {XTOP, D34, PRA0, PCREL}},
9800 {"plfd", PMLS|OP(50), P_D_MASK, POWER10, 0, {FRT, D34, PRA0, PCREL}},
9801 {"pstfs", PMLS|OP(52), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}},
9802 {"pstxv", P8LS|OP(54), P_D_MASK&~OP(1), POWER10, 0, {XTOP, D34, PRA0, PCREL}},
9803 {"pstfd", PMLS|OP(54), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}},
9804 {"plq", P8LS|OP(56), P_D_MASK, POWER10, 0, {RTQ, D34, PRAQ, PCREL}},
9805 {"pld", P8LS|OP(57), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
9806 {"plxvp", P8LS|OP(58), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PCREL}},
9807 {"pmdmxvi8ger4pp",PMMIRR|XX3(59,2), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
9808 {"pmxvi8ger4pp", PMMIRR|XX3(59,2), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
9809 {"pmdmxvi8ger4", PMMIRR|XX3(59,3), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
9810 {"pmxvi8ger4", PMMIRR|XX3(59,3), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
9811 {"pmdmxvi8gerx4pp",PMMIRR|XX3(59,10), P_GERX4_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},
9812 {"pmdmxvi8gerx4", PMMIRR|XX3(59,11), P_GERX4_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},
9813 {"pmdmxvf16ger2pp",PMMIRR|XX3(59,18), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9814 {"pmxvf16ger2pp", PMMIRR|XX3(59,18), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9815 {"pmdmxvf16ger2", PMMIRR|XX3(59,19), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9816 {"pmxvf16ger2", PMMIRR|XX3(59,19), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9817 {"pmdmxvf32gerpp",PMMIRR|XX3(59,26), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
9818 {"pmxvf32gerpp", PMMIRR|XX3(59,26), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
9819 {"pmdmxvf32ger", PMMIRR|XX3(59,27), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
9820 {"pmxvf32ger", PMMIRR|XX3(59,27), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
9821 {"pmdmxvi4ger8pp",PMMIRR|XX3(59,34), P_GER8_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},
9822 {"pmxvi4ger8pp", PMMIRR|XX3(59,34), P_GER8_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},
9823 {"pmdmxvi4ger8", PMMIRR|XX3(59,35), P_GER8_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},
9824 {"pmxvi4ger8", PMMIRR|XX3(59,35), P_GER8_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},
9825 {"pmdmxvi16ger2spp",PMMIRR|XX3(59,42), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9826 {"pmxvi16ger2spp",PMMIRR|XX3(59,42), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9827 {"pmdmxvi16ger2s",PMMIRR|XX3(59,43), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9828 {"pmxvi16ger2s", PMMIRR|XX3(59,43), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9829 {"pmdmxvbf16ger2pp",PMMIRR|XX3(59,50), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9830 {"pmxvbf16ger2pp",PMMIRR|XX3(59,50), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9831 {"pmdmxvbf16ger2",PMMIRR|XX3(59,51), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9832 {"pmxvbf16ger2", PMMIRR|XX3(59,51), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9833 {"pmdmxvf64gerpp",PMMIRR|XX3(59,58), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
9834 {"pmxvf64gerpp", PMMIRR|XX3(59,58), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
9835 {"pmdmxvf64ger", PMMIRR|XX3(59,59), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
9836 {"pmxvf64ger", PMMIRR|XX3(59,59), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
9837 {"pmdmxvf16gerx2pp",PMMIRR|XX3(59,66), P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
9838 {"pmdmxvf16gerx2",PMMIRR|XX3(59,67), P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
9839 {"pmdmxvbf16gerx2pp",PMMIRR|XX3(59,74),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
9840 {"pmdmxvi16ger2", PMMIRR|XX3(59,75), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9841 {"pmxvi16ger2", PMMIRR|XX3(59,75), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9842 {"pmdmxvf16ger2np",PMMIRR|XX3(59,82), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9843 {"pmxvf16ger2np", PMMIRR|XX3(59,82), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9844 {"pmdmxvf16gerx2np",PMMIRR|XX3(59,83), P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
9845 {"pmdmxvf32gernp",PMMIRR|XX3(59,90), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
9846 {"pmxvf32gernp", PMMIRR|XX3(59,90), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
9847 {"pmdmxvbf16gerx2",PMMIRR|XX3(59,91), P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
9848 {"pmdmxvi8gerx4spp",PMMIRR|XX3(59,98), P_GERX4_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},
9849 {"pmdmxvi8ger4spp",PMMIRR|XX3(59,99), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
9850 {"pmxvi8ger4spp", PMMIRR|XX3(59,99), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
9851 {"pmdmxvi16ger2pp",PMMIRR|XX3(59,107), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9852 {"pmxvi16ger2pp", PMMIRR|XX3(59,107), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9853 {"pmdmxvbf16ger2np",PMMIRR|XX3(59,114),P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9854 {"pmxvbf16ger2np",PMMIRR|XX3(59,114), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9855 {"pmdmxvbf16gerx2np",PMMIRR|XX3(59,115),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
9856 {"pmdmxvf64gernp",PMMIRR|XX3(59,122), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
9857 {"pmxvf64gernp", PMMIRR|XX3(59,122), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
9858 {"pmdmxvf16ger2pn",PMMIRR|XX3(59,146), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9859 {"pmxvf16ger2pn", PMMIRR|XX3(59,146), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9860 {"pmdmxvf16gerx2pn",PMMIRR|XX3(59,147),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
9861 {"pmdmxvf32gerpn",PMMIRR|XX3(59,154), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
9862 {"pmxvf32gerpn", PMMIRR|XX3(59,154), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
9863 {"pmdmxvbf16ger2pn",PMMIRR|XX3(59,178),P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9864 {"pmxvbf16ger2pn",PMMIRR|XX3(59,178), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9865 {"pmdmxvbf16gerx2pn",PMMIRR|XX3(59,179),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
9866 {"pmdmxvf64gerpn",PMMIRR|XX3(59,186), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
9867 {"pmxvf64gerpn", PMMIRR|XX3(59,186), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
9868 {"pmdmxvf16gerx2nn",PMMIRR|XX3(59,202),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
9869 {"pmdmxvf16ger2nn",PMMIRR|XX3(59,210), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9870 {"pmxvf16ger2nn", PMMIRR|XX3(59,210), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9871 {"pmdmxvf32gernn",PMMIRR|XX3(59,218), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
9872 {"pmxvf32gernn", PMMIRR|XX3(59,218), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}},
9873 {"pmdmxvbf16gerx2nn",PMMIRR|XX3(59,234),P_GERX2_MASK, FUTURE, 0, {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
9874 {"pmdmxvbf16ger2nn",PMMIRR|XX3(59,242),P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9875 {"pmxvbf16ger2nn",PMMIRR|XX3(59,242), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
9876 {"pmdmxvf64gernn",PMMIRR|XX3(59,250), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
9877 {"pmxvf64gernn", PMMIRR|XX3(59,250), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}},
9878 {"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCREL}},
9879 {"pstd", P8LS|OP(61), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
9880 {"pstxvp", P8LS|OP(62), P_D_MASK, POWER10, 0, {XSP, D34, PRA0, PCREL}},
9881 };
9882
9883 const unsigned int prefix_num_opcodes = ARRAY_SIZE (prefix_opcodes);
9884 \f
9885 /* The VLE opcode table.
9886
9887 The format of this opcode table is the same as the main opcode table. */
9888
9889 const struct powerpc_opcode vle_opcodes[] = {
9890 {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
9891 {"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
9892 {"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
9893 {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
9894 {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
9895 {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
9896 {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
9897 {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
9898 {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
9899 {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
9900 /* PPCRFMCI in the following does not enable the instruction for any
9901 PPC_OPCODE_RFMCI supporting cpu as vle_opcodes are all added to the
9902 assembler hash table or searched by the disassembler under control
9903 of PPC_OPCODE_VLE. It's there to set apuinfo. */
9904 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
9905 {"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}},
9906 {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
9907 {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
9908 {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
9909 {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
9910 {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
9911 {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
9912 {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
9913 {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
9914 {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
9915 {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
9916 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9917 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
9918 {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
9919 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9920 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9921 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9922 {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9923 {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9924 {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9925 {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9926 {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9927
9928 /* by major opcode */
9929 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
9930 {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
9931 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
9932 {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
9933 {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
9934 {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
9935 {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
9936 {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
9937 {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, EXT, {RT, RA, SCLSCI8N}},
9938 {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
9939 {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, EXT, {RT, RA, SCLSCI8N}},
9940 {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
9941 {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
9942 {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
9943 {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
9944 {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
9945 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, EXT, {0}},
9946 {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
9947 {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
9948 {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
9949 {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
9950 {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
9951 {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
9952 {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
9953 {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
9954 {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
9955 {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
9956 {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
9957 {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
9958 {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
9959 {"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9960 {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9961 {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9962 {"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9963 {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9964 {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9965 {"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9966 {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9967 {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9968 {"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9969 {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9970 {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9971 {"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9972 {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9973 {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9974 {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9975 {"e_stmvmcsrrw",OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
9976 {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
9977 {"e_la", OP(7), OP_MASK, PPCVLE, EXT, {RT, D, RA0}},
9978 {"e_sub16i", OP(7), OP_MASK, PPCVLE, EXT, {RT, RA, NSI}},
9979
9980 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
9981 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
9982 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
9983 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
9984 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
9985 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
9986 {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
9987
9988 {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
9989 {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
9990 {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
9991
9992 {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9993 {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9994 {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9995 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, EXT, {0}},
9996 {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9997 {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9998 {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9999 {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
10000 {"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
10001
10002 {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
10003 {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
10004 {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
10005 {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
10006
10007 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
10008 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
10009 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
10010 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
10011 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
10012 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
10013 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
10014
10015 {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
10016 {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
10017 {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
10018 {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
10019 {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
10020 {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
10021 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
10022 {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
10023 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10024 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
10025 {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, EXT, {RA, VLENSIMM}},
10026 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10027 {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, EXT, {RA, VLENSIMM}},
10028 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
10029 {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
10030 {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
10031 {"e_inslwi", M(29,0), M_MASK, PPCVLE, EXT, {RA, RS, ILWn, ILWb}},
10032 {"e_insrwi", M(29,0), M_MASK, PPCVLE, EXT, {RA, RS, IRWn, IRWb}},
10033 {"e_rotlwi", MME(29,31,1), MMBME_MASK, PPCVLE, EXT, {RA, RS, SH}},
10034 {"e_rotrwi", MME(29,31,1), MMBME_MASK, PPCVLE, EXT, {RA, RS, RRWn}},
10035 {"e_clrlwi", MME(29,31,1), MSHME_MASK, PPCVLE, EXT, {RA, RS, MB}},
10036 {"e_clrrwi", M(29,1), MSHMB_MASK, PPCVLE, EXT, {RA, RS, CRWn}},
10037 {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RS, SH, MBE, ME}},
10038 {"e_extlwi", M(29,1), MMB_MASK, PPCVLE, EXT, {RA, RS, ELWn, SH}},
10039 {"e_extrwi", MME(29,31,1), MME_MASK, PPCVLE, EXT, {RA, RS, ERWn, ERWb}},
10040 {"e_clrlslwi", M(29,1), M_MASK, PPCVLE, EXT, {RA, RS, CSLWb, CSLWn}},
10041 {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
10042 {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
10043 {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, EXT, {B15}},
10044 {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, EXT, {B15}},
10045 {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, EXT, {B15}},
10046 {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, EXT, {B15}},
10047 {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10048 {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10049 {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10050 {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10051 {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10052 {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10053 {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10054 {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10055 {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10056 {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10057 {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10058 {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10059 {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10060 {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10061 {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10062 {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10063 {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10064 {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10065 {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10066 {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10067 {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10068 {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10069 {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10070 {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}},
10071 {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
10072 {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
10073
10074 {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
10075 {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
10076 {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
10077 {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, EXT, {BI32,B15}},
10078
10079 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
10080 {"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}},
10081 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
10082 {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
10083 {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
10084 {"e_crnot", XL(31,33), XL_MASK, PPCVLE, EXT, {BT, BAB}},
10085 {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
10086 {"e_crclr", XL(31,193), XL_MASK, PPCVLE, EXT, {BTAB}},
10087 {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
10088 {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
10089 {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
10090 {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
10091
10092 {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
10093
10094 {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
10095 {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
10096
10097 {"e_crset", XL(31,289), XL_MASK, PPCVLE, EXT, {BTAB}},
10098 {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
10099
10100 {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
10101 {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
10102
10103 {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
10104
10105 {"e_crmove", XL(31,449), XL_MASK, PPCVLE, EXT, {BT, BAB}},
10106 {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
10107
10108 {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, EXT, {RS}},
10109
10110 {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
10111 {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
10112
10113 {"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
10114
10115 {"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
10116
10117 {"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
10118
10119 {"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
10120
10121 {"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
10122
10123 {"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
10124
10125 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10126 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10127 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10128 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10129 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10130 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10131 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10132 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, EXT, {BI16, B8}},
10133 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10134 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10135 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10136 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10137 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}},
10138 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, EXT, {BI16, B8}},
10139 {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
10140 {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
10141 {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
10142 };
10143
10144 const unsigned int vle_num_opcodes = ARRAY_SIZE (vle_opcodes);
10145
10146 const struct powerpc_opcode lsp_opcodes[] = {
10147 {"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
10148 {"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
10149 {"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10150 {"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10151 {"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10152 {"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10153 {"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10154 {"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10155 {"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10156 {"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10157 {"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10158 {"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10159 {"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10160 {"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10161 {"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10162 {"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10163 {"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10164 {"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10165 {"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10166 {"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10167 {"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10168 {"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10169 {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10170 {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10171 {"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10172 {"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10173 {"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10174 {"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10175 {"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10176 {"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10177 {"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10178 {"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10179 {"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10180 {"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10181 {"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10182 {"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10183 {"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
10184 {"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
10185 {"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
10186 {"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
10187 {"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
10188 {"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10189 {"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10190 {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10191 {"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10192 {"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10193 {"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10194 {"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10195 {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}},
10196 {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}},
10197 {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10198 {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10199 {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10200 {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10201 {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10202 {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10203 {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10204 {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10205 {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10206 {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10207 {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10208 {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10209 {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10210 {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10211 {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10212 {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10213 {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10214 {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10215 {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10216 {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10217 {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10218 {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}},
10219 {"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10220 {"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10221 {"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10222 {"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10223 {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0, {RD, RA, RB, VX_OFF}},
10224 {"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10225 {"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10226 {"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10227 {"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10228 {"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10229 {"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
10230 {"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
10231 {"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10232 {"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10233 {"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
10234 {"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
10235 {"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10236 {"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10237 {"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
10238 {"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
10239 {"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10240 {"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10241 {"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
10242 {"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
10243 {"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10244 {"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
10245 {"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10246 {"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
10247 {"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10248 {"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
10249 {"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10250 {"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10251 {"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10252 {"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10253 {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10254 {"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10255 {"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10256 {"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10257 {"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10258 {"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10259 {"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10260 {"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10261 {"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10262 {"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10263 {"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10264 {"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10265 {"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10266 {"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
10267 {"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10268 {"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
10269 {"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10270 {"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
10271 {"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10272 {"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
10273 {"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10274 {"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
10275 {"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10276 {"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
10277 {"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10278 {"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
10279 {"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10280 {"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
10281 {"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10282 {"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
10283 {"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10284 {"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
10285 {"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10286 {"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
10287 {"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10288 {"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
10289 {"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10290 {"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
10291 {"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10292 {"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
10293 {"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10294 {"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
10295 {"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10296 {"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
10297 {"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10298 {"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
10299 {"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10300 {"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
10301 {"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10302 {"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
10303 {"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10304 {"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10305 {"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10306 {"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10307 {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10308 {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10309 {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10310 {"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10311 {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10312 {"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10313 {"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10314 {"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10315 {"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10316 {"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10317 {"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10318 {"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10319 {"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10320 {"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
10321 {"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10322 {"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
10323 {"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10324 {"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
10325 {"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10326 {"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
10327 {"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10328 {"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}},
10329 {"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10330 {"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
10331 {"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10332 {"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
10333 {"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10334 {"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
10335 {"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10336 {"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
10337 {"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10338 {"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
10339 {"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10340 {"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
10341 {"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10342 {"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
10343 {"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10344 {"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
10345 {"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10346 {"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
10347 {"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10348 {"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
10349 {"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10350 {"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
10351 {"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10352 {"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10353 {"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10354 {"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10355 {"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10356 {"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10357 {"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10358 {"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10359 {"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10360 {"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10361 {"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10362 {"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10363 {"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10364 {"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10365 {"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10366 {"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10367 {"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10368 {"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10369 {"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10370 {"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10371 {"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10372 {"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10373 {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
10374 {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
10375 {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
10376 {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
10377 {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}},
10378 {"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10379 {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10380 {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10381 {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10382 {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10383 {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10384 {"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10385 {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10386 {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10387 {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10388 {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10389 {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10390 {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10391 {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10392 {"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10393 {"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10394 {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10395 {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10396 {"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10397 {"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10398 {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10399 {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10400 {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10401 {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10402 {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10403 {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10404 {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10405 {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10406 {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10407 {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10408 {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10409 {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10410 {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10411 {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10412 {"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10413 {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10414 {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10415 {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10416 {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10417 {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10418 {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10419 {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10420 {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10421 {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10422 {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10423 {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10424 {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10425 {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10426 {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10427 {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10428 {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10429 {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10430 {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10431 {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10432 {"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10433 {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10434 {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10435 {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10436 {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10437 {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10438 {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10439 {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10440 {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10441 {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10442 {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10443 {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10444 {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10445 {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10446 {"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10447 {"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10448 {"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10449 {"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10450 {"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10451 {"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10452 {"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10453 {"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10454 {"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10455 {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10456 {"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10457 {"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10458 {"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10459 {"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10460 {"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10461 {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10462 {"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10463 {"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10464 {"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10465 {"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10466 {"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10467 {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10468 {"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10469 {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10470 {"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10471 {"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10472 {"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10473 {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10474 {"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10475 {"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10476 {"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10477 {"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10478 {"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10479 {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10480 {"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10481 {"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10482 {"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10483 {"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10484 {"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10485 {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10486 {"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10487 {"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10488 {"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10489 {"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10490 {"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10491 {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10492 {"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10493 {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10494 {"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10495 {"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10496 {"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10497 {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10498 {"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10499 {"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10500 {"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10501 {"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10502 {"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10503 {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10504 {"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10505 {"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10506 {"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10507 {"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10508 {"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10509 {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10510 {"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10511 {"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10512 {"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10513 {"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10514 {"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10515 {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10516 {"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10517 {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10518 {"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10519 {"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10520 {"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10521 {"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10522 {"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10523 {"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10524 {"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10525 {"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10526 {"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10527 {"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10528 {"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10529 {"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10530 {"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10531 {"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10532 {"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10533 {"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10534 {"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10535 {"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10536 {"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10537 {"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10538 {"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10539 {"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10540 {"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10541 {"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10542 {"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10543 {"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10544 {"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10545 {"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10546 {"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10547 {"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10548 {"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10549 {"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10550 {"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10551 {"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10552 {"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10553 {"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10554 {"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10555 {"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10556 {"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10557 {"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10558 {"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10559 {"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10560 {"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10561 {"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10562 {"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10563 {"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10564 {"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10565 {"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10566 {"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10567 {"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10568 {"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10569 {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10570 {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10571 {"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10572 {"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10573 {"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10574 {"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10575 {"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10576 {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10577 {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10578 {"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10579 {"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10580 {"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10581 {"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10582 {"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10583 {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10584 {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10585 {"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10586 {"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10587 {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10588 {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10589 {"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10590 {"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10591 {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10592 {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10593 {"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10594 {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10595 {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10596 {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10597 {"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10598 {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10599 {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10600 {"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10601 {"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10602 {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10603 {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10604 {"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10605 {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10606 {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10607 {"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10608 {"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10609 {"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10610 {"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10611 {"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10612 {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10613 {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10614 {"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10615 {"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10616 {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10617 {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10618 {"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10619 {"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10620 {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10621 {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10622 {"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10623 {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10624 {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10625 {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10626 {"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10627 {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10628 {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10629 {"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10630 {"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10631 {"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10632 {"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10633 {"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10634 {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10635 {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10636 {"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10637 {"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10638 {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10639 {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10640 {"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10641 {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10642 {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10643 {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10644 {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10645 {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10646 {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10647 {"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10648 {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10649 {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10650 {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10651 {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10652 {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10653 {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10654 {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10655 {"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10656 {"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10657 {"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10658 {"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10659 {"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10660 {"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10661 {"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10662 {"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10663 {"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10664 {"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10665 {"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10666 {"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10667 {"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10668 {"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10669 {"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10670 {"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10671 {"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10672 {"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10673 {"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10674 {"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10675 {"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10676 {"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10677 {"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10678 {"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10679 {"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10680 {"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10681 {"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10682 {"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10683 {"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10684 {"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10685 {"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10686 {"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10687 {"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10688 {"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10689 {"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10690 {"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10691 {"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10692 {"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10693 {"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10694 {"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10695 {"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10696 {"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10697 {"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10698 {"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10699 {"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10700 {"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10701 {"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10702 {"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10703 {"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10704 {"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10705 {"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10706 {"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10707 {"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10708 {"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10709 {"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10710 {"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10711 {"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10712 {"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10713 {"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10714 {"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10715 {"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10716 {"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10717 {"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10718 {"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10719 {"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10720 {"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10721 {"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10722 {"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10723 {"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10724 {"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10725 {"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10726 {"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10727 {"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10728 {"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10729 {"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10730 {"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10731 {"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10732 {"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10733 {"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10734 {"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10735 {"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10736 {"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10737 {"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10738 {"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10739 {"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10740 {"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10741 {"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10742 {"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10743 {"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10744 {"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10745 {"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10746 {"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10747 {"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10748 {"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10749 {"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10750 {"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10751 {"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10752 {"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10753 {"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10754 {"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10755 {"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10756 {"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10757 {"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10758 {"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10759 {"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10760 {"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10761 {"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10762 {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10763 {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10764 {"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10765 {"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10766 {"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10767 {"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10768 {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10769 {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10770 {"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10771 {"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10772 {"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10773 {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10774 {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10775 {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10776 {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10777 {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10778 {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10779 {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10780 {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10781 {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10782 {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10783 {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10784 {"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10785 {"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10786 {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10787 {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10788 {"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10789 {"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10790 {"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10791 {"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10792 {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10793 {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10794 {"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10795 {"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10796 {"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10797 {"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10798 {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10799 {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10800 {"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10801 {"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10802 {"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10803 {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10804 {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10805 {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10806 {"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10807 {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10808 {"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10809 {"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10810 {"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10811 {"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10812 {"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10813 {"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10814 {"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10815 {"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10816 {"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10817 {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10818 {"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10819 {"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10820 {"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10821 {"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10822 {"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10823 {"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10824 {"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10825 };
10826
10827 const unsigned int lsp_num_opcodes = ARRAY_SIZE (lsp_opcodes);
10828
10829 /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */
10830 const struct powerpc_opcode spe2_opcodes[] = {
10831 {"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10832 {"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10833 {"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10834 {"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10835 {"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10836 {"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10837 {"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10838 {"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10839 {"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10840 {"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10841 {"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10842 {"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10843 {"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10844 {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10845 {"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10846 {"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10847 {"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10848 {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10849 {"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10850 {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10851 {"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10852 {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10853 {"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10854 {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10855 {"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10856 {"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10857 {"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10858 {"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10859 {"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10860 {"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10861 {"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10862 {"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10863 {"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10864 {"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10865 {"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10866 {"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10867 {"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10868 {"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10869 {"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10870 {"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10871 {"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10872 {"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10873 {"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10874 {"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10875 {"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10876 {"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10877 {"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10878 {"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10879 {"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10880 {"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10881 {"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10882 {"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10883 {"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10884 {"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10885 {"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10886 {"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10887 {"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10888 {"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10889 {"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10890 {"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10891 {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10892 {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10893 {"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10894 {"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10895 {"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10896 {"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10897 {"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10898 {"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10899 {"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10900 {"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10901 {"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10902 {"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10903 {"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10904 {"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10905 {"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10906 {"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10907 {"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10908 {"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10909 {"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10910 {"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10911 {"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10912 {"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10913 {"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10914 {"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10915 {"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10916 {"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10917 {"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10918 {"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10919 {"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10920 {"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10921 {"evdotphsssi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10922 {"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10923 {"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10924 {"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10925 {"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10926 {"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10927 {"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10928 {"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10929 {"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10930 {"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10931 {"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10932 {"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10933 {"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10934 {"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10935 {"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10936 {"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10937 {"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10938 {"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10939 {"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10940 {"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10941 {"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10942 {"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10943 {"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10944 {"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10945 {"evdotphsssia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10946 {"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10947 {"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10948 {"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10949 {"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10950 {"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10951 {"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10952 {"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10953 {"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10954 {"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10955 {"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10956 {"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10957 {"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10958 {"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10959 {"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10960 {"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10961 {"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10962 {"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10963 {"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10964 {"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10965 {"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10966 {"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10967 {"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10968 {"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10969 {"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10970 {"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10971 {"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10972 {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10973 {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10974 {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10975 {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10976 {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10977 {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10978 {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10979 {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10980 {"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10981 {"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10982 {"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10983 {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10984 {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10985 {"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10986 {"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10987 {"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10988 {"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10989 {"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10990 {"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10991 {"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10992 {"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10993 {"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10994 {"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10995 {"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10996 {"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10997 {"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10998 {"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10999 {"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11000 {"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11001 {"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11002 {"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11003 {"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11004 {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11005 {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11006 {"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11007 {"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11008 {"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11009 {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11010 {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11011 {"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11012 {"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11013 {"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11014 {"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11015 {"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11016 {"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11017 {"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11018 {"evdotpwsssi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11019 {"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11020 {"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11021 {"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11022 {"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11023 {"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11024 {"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11025 {"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11026 {"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11027 {"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11028 {"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11029 {"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11030 {"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11031 {"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11032 {"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11033 {"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11034 {"evdotpwsssia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11035 {"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11036 {"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11037 {"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11038 {"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11039 {"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11040 {"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11041 {"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11042 {"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11043 {"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}},
11044 {"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}},
11045 {"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}},
11046 {"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}},
11047 {"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11048 {"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11049 {"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11050 {"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11051 {"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11052 {"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11053 {"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11054 {"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11055 {"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11056 {"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11057 {"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11058 {"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11059 {"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11060 {"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11061 {"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11062 {"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11063 {"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11064 {"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11065 {"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11066 {"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11067 {"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11068 {"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11069 {"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11070 {"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11071 {"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11072 {"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11073 {"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11074 {"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11075 {"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11076 {"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11077 {"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11078 {"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11079 {"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11080 {"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11081 {"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11082 {"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11083 {"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11084 {"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11085 {"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11086 {"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11087 {"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11088 {"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11089 {"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11090 {"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11091 {"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11092 {"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11093 {"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11094 {"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11095 {"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11096 {"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11097 {"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11098 {"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11099 {"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11100 {"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11101 {"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11102 {"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11103 {"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11104 {"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11105 {"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11106 {"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11107 {"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11108 {"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11109 {"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11110 {"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11111 {"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11112 {"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11113 {"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11114 {"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11115 {"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11116 {"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11117 {"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11118 {"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11119 {"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11120 {"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11121 {"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11122 {"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11123 {"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11124 {"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11125 {"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11126 {"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11127 {"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11128 {"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11129 {"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11130 {"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11131 {"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11132 {"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11133 {"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11134 {"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
11135 {"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11136 {"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11137 {"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11138 {"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11139 {"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11140 {"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11141 {"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11142 {"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11143 {"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11144 {"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11145 {"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11146 {"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11147 {"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11148 {"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11149 {"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11150 {"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11151 {"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11152 {"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11153 {"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11154 {"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11155 {"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11156 {"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11157 {"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11158 {"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11159 {"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11160 {"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}},
11161 {"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
11162 {"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
11163 {"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
11164 {"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
11165 {"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}},
11166 {"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11167 {"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11168 {"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11169 {"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11170 {"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11171 {"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11172 {"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11173 {"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11174 {"evinsb", VX (4, 584), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}},
11175 {"evxtrb", VX (4, 586), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}},
11176 {"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK, PPCSPE2, 0, {RD, RA, HH}},
11177 {"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}},
11178 {"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}},
11179 {"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}},
11180 {"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}},
11181 {"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}},
11182 {"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}},
11183 {"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11184 {"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11185 {"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11186 {"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11187 {"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11188 {"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11189 {"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK, PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}},
11190 {"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11191 {"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11192 {"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
11193 {"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
11194 {"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11195 {"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11196 {"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
11197 {"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
11198 {"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11199 {"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11200 {"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
11201 {"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
11202 {"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11203 {"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11204 {"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
11205 {"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
11206 {"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11207 {"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11208 {"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
11209 {"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
11210 {"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11211 {"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11212 {"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
11213 {"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
11214 {"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
11215 {"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11216 {"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}},
11217 {"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11218 {"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}},
11219 {"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11220 {"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
11221 {"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11222 {"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
11223 {"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11224 {"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}},
11225 {"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11226 {"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}},
11227 {"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11228 {"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
11229 {"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11230 {"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
11231 {"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11232 {"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
11233 {"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11234 {"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
11235 {"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11236 {"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
11237 {"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11238 {"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
11239 {"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11240 {"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}},
11241 {"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11242 {"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
11243 {"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11244 {"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
11245 {"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11246 {"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
11247 {"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11248 {"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
11249 {"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11250 {"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
11251 {"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11252 {"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
11253 {"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11254 {"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
11255 {"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11256 {"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
11257 {"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11258 {"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11259 {"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11260 {"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11261 {"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11262 {"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11263 {"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11264 {"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11265 {"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11266 {"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11267 {"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11268 {"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11269 {"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11270 {"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11271 {"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11272 {"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}},
11273 {"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11274 {"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
11275 {"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11276 {"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
11277 {"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11278 {"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
11279 {"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11280 {"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
11281 {"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11282 {"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11283 {"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11284 {"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11285 {"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11286 {"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
11287 {"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11288 {"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11289 {"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11290 {"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11291 {"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11292 {"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11293 {"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11294 {"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11295 {"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11296 {"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11297 {"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11298 {"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11299 {"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11300 {"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
11301 {"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
11302 {"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}},
11303 {"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11304 {"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11305 {"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11306 {"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11307 {"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11308 {"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11309 {"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11310 {"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11311 {"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11312 {"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11313 {"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11314 {"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11315 {"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11316 {"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11317 {"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11318 {"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11319 {"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11320 {"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11321 {"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11322 {"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11323 {"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11324 {"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11325 {"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11326 {"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11327 {"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11328 {"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11329 {"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11330 {"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11331 {"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11332 {"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11333 {"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11334 {"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11335 {"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11336 {"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11337 {"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11338 {"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11339 {"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11340 {"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11341 {"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11342 {"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11343 {"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11344 {"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11345 {"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11346 {"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11347 {"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11348 {"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11349 {"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11350 {"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11351 {"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11352 {"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11353 {"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11354 {"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11355 {"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11356 {"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11357 {"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11358 {"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11359 {"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11360 {"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11361 {"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11362 {"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11363 {"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11364 {"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11365 {"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11366 {"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11367 {"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11368 {"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11369 {"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11370 {"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11371 {"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11372 {"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11373 {"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11374 {"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11375 {"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11376 {"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11377 {"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11378 {"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11379 {"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11380 {"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11381 {"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11382 {"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11383 {"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11384 {"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11385 {"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11386 {"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11387 {"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11388 {"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11389 {"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11390 {"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11391 {"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11392 {"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11393 {"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11394 {"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11395 {"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11396 {"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11397 {"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK, PPCSPE2, 0, {RD}},
11398 {"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11399 {"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11400 {"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11401 {"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11402 {"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11403 {"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11404 {"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11405 {"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11406 {"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11407 {"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11408 {"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11409 {"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11410 {"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11411 {"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11412 {"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11413 {"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11414 {"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11415 {"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11416 {"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11417 {"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11418 {"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11419 {"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11420 {"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11421 {"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
11422 {"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11423 {"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11424 {"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11425 {"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11426 {"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11427 {"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11428 {"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11429 {"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11430 {"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11431 {"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11432 {"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11433 {"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11434 {"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11435 {"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11436 {"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11437 {"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11438 {"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11439 {"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11440 {"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11441 {"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11442 {"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11443 {"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11444 {"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11445 {"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11446 {"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11447 {"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11448 {"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11449 {"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11450 {"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11451 {"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11452 {"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11453 {"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11454 {"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11455 {"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11456 {"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11457 {"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11458 {"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11459 {"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11460 {"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11461 {"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11462 {"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11463 {"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11464 {"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11465 {"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11466 {"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11467 {"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11468 {"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11469 {"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11470 {"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11471 {"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11472 {"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11473 {"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11474 {"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11475 {"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11476 {"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11477 {"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11478 {"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11479 {"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11480 {"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11481 {"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11482 {"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11483 {"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11484 {"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11485 {"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11486 {"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11487 {"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11488 {"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11489 {"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11490 {"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11491 {"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11492 {"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11493 {"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11494 {"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11495 {"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11496 {"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11497 {"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11498 {"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11499 {"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11500 {"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11501 {"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11502 {"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11503 {"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11504 {"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11505 {"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11506 {"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11507 {"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11508 {"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11509 {"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11510 {"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11511 {"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11512 {"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11513 {"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11514 {"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11515 {"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11516 {"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11517 {"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11518 {"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11519 {"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11520 {"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11521 {"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11522 {"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11523 {"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11524 {"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11525 {"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11526 {"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11527 {"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11528 {"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11529 {"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11530 {"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11531 {"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11532 {"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11533 {"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11534 {"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11535 {"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11536 {"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11537 {"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11538 {"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11539 {"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11540 {"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11541 {"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11542 {"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11543 {"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11544 {"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11545 {"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11546 {"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11547 {"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11548 {"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11549 {"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11550 {"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11551 {"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11552 {"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11553 {"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11554 {"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11555 {"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11556 {"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11557 {"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11558 {"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11559 {"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11560 {"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11561 {"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11562 {"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11563 {"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11564 {"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11565 {"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11566 {"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11567 {"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11568 {"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11569 {"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11570 {"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11571 {"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11572 {"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11573 {"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11574 {"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11575 {"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11576 {"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11577 {"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11578 {"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11579 {"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11580 {"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11581 {"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11582 {"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11583 {"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11584 {"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11585 {"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11586 {"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11587 {"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11588 {"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11589 {"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11590 {"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11591 {"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11592 {"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11593 {"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11594 {"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11595 {"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11596 {"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11597 {"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11598 {"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11599 {"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11600 {"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11601 {"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11602 {"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11603 {"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11604 {"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11605 {"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11606 {"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11607 {"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11608 {"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11609 {"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11610 {"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11611 {"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11612 {"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11613 {"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11614 {"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11615 {"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11616 {"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11617 {"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11618 {"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11619 };
11620
11621 const unsigned int spe2_num_opcodes = ARRAY_SIZE (spe2_opcodes);