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[binutils-gdb.git] / opcodes / sparc-dis.c
1 /* Print SPARC instructions.
2 Copyright (C) 1989, 91-93, 1995, 1996 Free Software Foundation, Inc.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18 #include "ansidecl.h"
19 #include "opcode/sparc.h"
20 #include "dis-asm.h"
21 #include "libiberty.h"
22 #include <string.h>
23
24 /* For faster lookup, after insns are sorted they are hashed. */
25 /* ??? I think there is room for even more improvement. */
26
27 #define HASH_SIZE 256
28 /* It is important that we only look at insn code bits as that is how the
29 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
30 of the main types (0,1,2,3). */
31 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
32 #define HASH_INSN(INSN) \
33 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
34 struct opcode_hash {
35 struct opcode_hash *next;
36 struct sparc_opcode *opcode;
37 };
38 static struct opcode_hash *opcode_hash_table[HASH_SIZE];
39 static void build_hash_table ();
40
41 /* Sign-extend a value which is N bits long. */
42 #define SEX(value, bits) \
43 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
44 >> ((8 * sizeof (int)) - bits) )
45
46 static char *reg_names[] =
47 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
48 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
49 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
50 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
51 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
52 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
53 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
54 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
55 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
56 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
57 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
58 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
59 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
60 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
61 };
62
63 #define freg_names (&reg_names[4 * 8])
64
65 /* These are ordered according to there register number in
66 rdpr and wrpr insns. */
67 static char *v9_priv_reg_names[] =
68 {
69 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
70 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
71 "wstate", "fq"
72 /* "ver" - special cased */
73 };
74
75 /* Macros used to extract instruction fields. Not all fields have
76 macros defined here, only those which are actually used. */
77
78 #define X_RD(i) (((i) >> 25) & 0x1f)
79 #define X_RS1(i) (((i) >> 14) & 0x1f)
80 #define X_LDST_I(i) (((i) >> 13) & 1)
81 #define X_ASI(i) (((i) >> 5) & 0xff)
82 #define X_RS2(i) (((i) >> 0) & 0x1f)
83 #define X_IMM13(i) (((i) >> 0) & 0x1fff)
84 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
85 #define X_IMM22(i) X_DISP22 (i)
86 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
87
88 /* These are for v9. */
89 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
90 #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
91 #define X_MEMBAR(i) ((i) & 0x7f)
92
93 /* Here is the union which was used to extract instruction fields
94 before the shift and mask macros were written.
95
96 union sparc_insn
97 {
98 unsigned long int code;
99 struct
100 {
101 unsigned int anop:2;
102 #define op ldst.anop
103 unsigned int anrd:5;
104 #define rd ldst.anrd
105 unsigned int op3:6;
106 unsigned int anrs1:5;
107 #define rs1 ldst.anrs1
108 unsigned int i:1;
109 unsigned int anasi:8;
110 #define asi ldst.anasi
111 unsigned int anrs2:5;
112 #define rs2 ldst.anrs2
113 #define shcnt rs2
114 } ldst;
115 struct
116 {
117 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
118 unsigned int IMM13:13;
119 #define imm13 IMM13.IMM13
120 } IMM13;
121 struct
122 {
123 unsigned int anop:2;
124 unsigned int a:1;
125 unsigned int cond:4;
126 unsigned int op2:3;
127 unsigned int DISP22:22;
128 #define disp22 branch.DISP22
129 #define imm22 disp22
130 } branch;
131 struct
132 {
133 unsigned int anop:2;
134 unsigned int a:1;
135 unsigned int z:1;
136 unsigned int rcond:3;
137 unsigned int op2:3;
138 unsigned int DISP16HI:2;
139 unsigned int p:1;
140 unsigned int _rs1:5;
141 unsigned int DISP16LO:14;
142 } branch16;
143 struct
144 {
145 unsigned int anop:2;
146 unsigned int adisp30:30;
147 #define disp30 call.adisp30
148 } call;
149 };
150
151 */
152
153 /* Nonzero if INSN is the opcode for a delayed branch. */
154 static int
155 is_delayed_branch (insn)
156 unsigned long insn;
157 {
158 struct opcode_hash *op;
159
160 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
161 {
162 CONST struct sparc_opcode *opcode = op->opcode;
163 if ((opcode->match & insn) == opcode->match
164 && (opcode->lose & insn) == 0)
165 return (opcode->flags & F_DELAYED);
166 }
167 return 0;
168 }
169
170 /* Nonzero of opcode table has been initialized. */
171 static int opcodes_initialized = 0;
172
173 /* extern void qsort (); */
174 static int compare_opcodes ();
175
176 /* Print one instruction from MEMADDR on INFO->STREAM.
177
178 We suffix the instruction with a comment that gives the absolute
179 address involved, as well as its symbolic form, if the instruction
180 is preceded by a findable `sethi' and it either adds an immediate
181 displacement to that register, or it is an `add' or `or' instruction
182 on that register. */
183
184 int
185 print_insn_sparc (memaddr, info)
186 bfd_vma memaddr;
187 disassemble_info *info;
188 {
189 FILE *stream = info->stream;
190 bfd_byte buffer[4];
191 unsigned long insn;
192 register unsigned int i;
193 register struct opcode_hash *op;
194 int sparc_v9_p = bfd_mach_sparc_v9_p (info->mach);
195
196 if (!opcodes_initialized)
197 {
198 qsort ((char *) sparc_opcodes, NUMOPCODES,
199 sizeof (sparc_opcodes[0]), compare_opcodes);
200 build_hash_table (sparc_opcodes, opcode_hash_table, NUMOPCODES);
201 opcodes_initialized = 1;
202 }
203
204 {
205 int status =
206 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
207 if (status != 0)
208 {
209 (*info->memory_error_func) (status, memaddr, info);
210 return -1;
211 }
212 }
213
214 insn = bfd_getb32 (buffer);
215
216 if (DISASM_RAW_INSN (info))
217 (*info->fprintf_func) (stream, "0x%08lx\t", insn);
218
219 info->insn_info_valid = 1; /* We do return this info */
220 info->insn_type = dis_nonbranch; /* Assume non branch insn */
221 info->branch_delay_insns = 0; /* Assume no delay */
222 info->target = 0; /* Assume no target known */
223
224 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
225 {
226 CONST struct sparc_opcode *opcode = op->opcode;
227
228 /* If the current architecture isn't sparc64, skip sparc64 insns. */
229 if (!sparc_v9_p
230 && opcode->architecture >= v9)
231 continue;
232
233 /* If the current architecture is sparc64, skip sparc32 only insns. */
234 if (sparc_v9_p
235 && (opcode->flags & F_NOTV9))
236 continue;
237
238 if ((opcode->match & insn) == opcode->match
239 && (opcode->lose & insn) == 0)
240 {
241 /* Nonzero means that we have found an instruction which has
242 the effect of adding or or'ing the imm13 field to rs1. */
243 int imm_added_to_rs1 = 0;
244
245 /* Nonzero means that we have found a plus sign in the args
246 field of the opcode table. */
247 int found_plus = 0;
248
249 /* Nonzero means we have an annulled branch. */
250 int is_annulled = 0;
251
252 /* Do we have an `add' or `or' instruction where rs1 is the same
253 as rsd, and which has the i bit set? */
254 if ((opcode->match == 0x80102000 || opcode->match == 0x80002000)
255 /* (or) (add) */
256 && X_RS1 (insn) == X_RD (insn))
257 imm_added_to_rs1 = 1;
258
259 if (X_RS1 (insn) != X_RD (insn)
260 && strchr (opcode->args, 'r') != 0)
261 /* Can't do simple format if source and dest are different. */
262 continue;
263
264 (*info->fprintf_func) (stream, opcode->name);
265
266 {
267 register CONST char *s;
268
269 if (opcode->args[0] != ',')
270 (*info->fprintf_func) (stream, " ");
271 for (s = opcode->args; *s != '\0'; ++s)
272 {
273 while (*s == ',')
274 {
275 (*info->fprintf_func) (stream, ",");
276 ++s;
277 switch (*s) {
278 case 'a':
279 (*info->fprintf_func) (stream, "a");
280 is_annulled = 1;
281 ++s;
282 continue;
283 case 'N':
284 (*info->fprintf_func) (stream, "pn");
285 ++s;
286 continue;
287
288 case 'T':
289 (*info->fprintf_func) (stream, "pt");
290 ++s;
291 continue;
292
293 default:
294 break;
295 } /* switch on arg */
296 } /* while there are comma started args */
297
298 (*info->fprintf_func) (stream, " ");
299
300 switch (*s)
301 {
302 case '+':
303 found_plus = 1;
304
305 /* note fall-through */
306 default:
307 (*info->fprintf_func) (stream, "%c", *s);
308 break;
309
310 case '#':
311 (*info->fprintf_func) (stream, "0");
312 break;
313
314 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
315 case '1':
316 case 'r':
317 reg (X_RS1 (insn));
318 break;
319
320 case '2':
321 reg (X_RS2 (insn));
322 break;
323
324 case 'd':
325 reg (X_RD (insn));
326 break;
327 #undef reg
328
329 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
330 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
331 case 'e':
332 freg (X_RS1 (insn));
333 break;
334 case 'v': /* double/even */
335 case 'V': /* quad/multiple of 4 */
336 fregx (X_RS1 (insn));
337 break;
338
339 case 'f':
340 freg (X_RS2 (insn));
341 break;
342 case 'B': /* double/even */
343 case 'R': /* quad/multiple of 4 */
344 fregx (X_RS2 (insn));
345 break;
346
347 case 'g':
348 freg (X_RD (insn));
349 break;
350 case 'H': /* double/even */
351 case 'J': /* quad/multiple of 4 */
352 fregx (X_RD (insn));
353 break;
354 #undef freg
355 #undef fregx
356
357 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
358 case 'b':
359 creg (X_RS1 (insn));
360 break;
361
362 case 'c':
363 creg (X_RS2 (insn));
364 break;
365
366 case 'D':
367 creg (X_RD (insn));
368 break;
369 #undef creg
370
371 case 'h':
372 (*info->fprintf_func) (stream, "%%hi(%#x)",
373 (0xFFFFFFFF
374 & ((int) X_IMM22 (insn) << 10)));
375 break;
376
377 case 'i':
378 {
379 int imm = SEX (X_IMM13 (insn), 13);
380
381 /* Check to see whether we have a 1+i, and take
382 note of that fact.
383
384 Note: because of the way we sort the table,
385 we will be matching 1+i rather than i+1,
386 so it is OK to assume that i is after +,
387 not before it. */
388 if (found_plus)
389 imm_added_to_rs1 = 1;
390
391 if (imm <= 9)
392 (*info->fprintf_func) (stream, "%d", imm);
393 else
394 (*info->fprintf_func) (stream, "%#x", imm);
395 }
396 break;
397
398 case 'I': /* 11 bit immediate. */
399 case 'j': /* 10 bit immediate. */
400 {
401 int imm;
402
403 if (*s == 'I')
404 imm = SEX (X_IMM13 (insn), 11);
405 else
406 imm = SEX (X_IMM13 (insn), 10);
407
408 /* Check to see whether we have a 1+i, and take
409 note of that fact.
410
411 Note: because of the way we sort the table,
412 we will be matching 1+i rather than i+1,
413 so it is OK to assume that i is after +,
414 not before it. */
415 if (found_plus)
416 imm_added_to_rs1 = 1;
417
418 if (imm <= 9)
419 (info->fprintf_func) (stream, "%d", imm);
420 else
421 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
422 }
423 break;
424
425 case 'K':
426 {
427 int mask = X_MEMBAR (insn);
428 int bit = 0x40, printed_one = 0;
429 char *name;
430
431 if (mask == 0)
432 (info->fprintf_func) (stream, "0");
433 else
434 while (bit)
435 {
436 if (mask & bit)
437 {
438 if (printed_one)
439 (info->fprintf_func) (stream, "|");
440 name = sparc_decode_membar (bit);
441 (info->fprintf_func) (stream, "%s", name);
442 printed_one = 1;
443 }
444 bit >>= 1;
445 }
446 break;
447 }
448
449 case 'k':
450 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
451 (*info->print_address_func) (info->target, info);
452 break;
453
454 case 'G':
455 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
456 (*info->print_address_func) (info->target, info);
457 break;
458
459 case '6':
460 case '7':
461 case '8':
462 case '9':
463 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
464 break;
465
466 case 'z':
467 (*info->fprintf_func) (stream, "%%icc");
468 break;
469
470 case 'Z':
471 (*info->fprintf_func) (stream, "%%xcc");
472 break;
473
474 case 'E':
475 (*info->fprintf_func) (stream, "%%ccr");
476 break;
477
478 case 's':
479 (*info->fprintf_func) (stream, "%%fprs");
480 break;
481
482 case 'o':
483 (*info->fprintf_func) (stream, "%%asi");
484 break;
485
486 case 'W':
487 (*info->fprintf_func) (stream, "%%tick");
488 break;
489
490 case 'P':
491 (*info->fprintf_func) (stream, "%%pc");
492 break;
493
494 case '?':
495 if (X_RS1 (insn) == 31)
496 (*info->fprintf_func) (stream, "%%ver");
497 else if ((unsigned) X_RS1 (insn) < 16)
498 (*info->fprintf_func) (stream, "%%%s",
499 v9_priv_reg_names[X_RS1 (insn)]);
500 else
501 (*info->fprintf_func) (stream, "%%reserved");
502 break;
503
504 case '!':
505 if ((unsigned) X_RD (insn) < 15)
506 (*info->fprintf_func) (stream, "%%%s",
507 v9_priv_reg_names[X_RD (insn)]);
508 else
509 (*info->fprintf_func) (stream, "%%reserved");
510 break;
511
512 case '*':
513 {
514 char *name = sparc_decode_prefetch (X_RD (insn));
515
516 if (name)
517 (*info->fprintf_func) (stream, "%s", name);
518 else
519 (*info->fprintf_func) (stream, "%d", X_RD (insn));
520 break;
521 }
522
523 case 'M':
524 (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
525 break;
526
527 case 'm':
528 (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
529 break;
530
531 case 'L':
532 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
533 (*info->print_address_func) (info->target, info);
534 break;
535
536 case 'n':
537 (*info->fprintf_func)
538 (stream, "%#x", SEX (X_DISP22 (insn), 22));
539 break;
540
541 case 'l':
542 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
543 (*info->print_address_func) (info->target, info);
544 break;
545
546 case 'A':
547 {
548 char *name = sparc_decode_asi (X_ASI (insn));
549
550 if (name)
551 (*info->fprintf_func) (stream, "%s", name);
552 else
553 (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
554 break;
555 }
556
557 case 'C':
558 (*info->fprintf_func) (stream, "%%csr");
559 break;
560
561 case 'F':
562 (*info->fprintf_func) (stream, "%%fsr");
563 break;
564
565 case 'p':
566 (*info->fprintf_func) (stream, "%%psr");
567 break;
568
569 case 'q':
570 (*info->fprintf_func) (stream, "%%fq");
571 break;
572
573 case 'Q':
574 (*info->fprintf_func) (stream, "%%cq");
575 break;
576
577 case 't':
578 (*info->fprintf_func) (stream, "%%tbr");
579 break;
580
581 case 'w':
582 (*info->fprintf_func) (stream, "%%wim");
583 break;
584
585 case 'x':
586 (*info->fprintf_func) (stream, "%d",
587 ((X_LDST_I (insn) << 8)
588 + X_ASI (insn)));
589 break;
590
591 case 'y':
592 (*info->fprintf_func) (stream, "%%y");
593 break;
594 }
595 }
596 }
597
598 /* If we are adding or or'ing something to rs1, then
599 check to see whether the previous instruction was
600 a sethi to the same register as in the sethi.
601 If so, attempt to print the result of the add or
602 or (in this context add and or do the same thing)
603 and its symbolic value. */
604 if (imm_added_to_rs1)
605 {
606 unsigned long prev_insn;
607 int errcode;
608
609 errcode =
610 (*info->read_memory_func)
611 (memaddr - 4, buffer, sizeof (buffer), info);
612 prev_insn = bfd_getb32 (buffer);
613
614 if (errcode == 0)
615 {
616 /* If it is a delayed branch, we need to look at the
617 instruction before the delayed branch. This handles
618 sequences such as
619
620 sethi %o1, %hi(_foo), %o1
621 call _printf
622 or %o1, %lo(_foo), %o1
623 */
624
625 if (is_delayed_branch (prev_insn))
626 {
627 errcode = (*info->read_memory_func)
628 (memaddr - 8, buffer, sizeof (buffer), info);
629 prev_insn = bfd_getb32 (buffer);
630 }
631 }
632
633 /* If there was a problem reading memory, then assume
634 the previous instruction was not sethi. */
635 if (errcode == 0)
636 {
637 /* Is it sethi to the same register? */
638 if ((prev_insn & 0xc1c00000) == 0x01000000
639 && X_RD (prev_insn) == X_RS1 (insn))
640 {
641 (*info->fprintf_func) (stream, "\t! ");
642 info->target =
643 (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10)
644 | SEX (X_IMM13 (insn), 13);
645 (*info->print_address_func) (info->target, info);
646 info->insn_type = dis_dref;
647 info->data_size = 4; /* FIXME!!! */
648 }
649 }
650 }
651
652 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
653 {
654 /* FIXME -- check is_annulled flag */
655 if (opcode->flags & F_UNBR)
656 info->insn_type = dis_branch;
657 if (opcode->flags & F_CONDBR)
658 info->insn_type = dis_condbranch;
659 if (opcode->flags & F_JSR)
660 info->insn_type = dis_jsr;
661 if (opcode->flags & F_DELAYED)
662 info->branch_delay_insns = 1;
663 }
664
665 return sizeof (buffer);
666 }
667 }
668
669 info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
670 (*info->fprintf_func) (stream, "%#8x", insn);
671 return sizeof (buffer);
672 }
673
674 /* Compare opcodes A and B. */
675
676 static int
677 compare_opcodes (a, b)
678 char *a, *b;
679 {
680 struct sparc_opcode *op0 = (struct sparc_opcode *) a;
681 struct sparc_opcode *op1 = (struct sparc_opcode *) b;
682 unsigned long int match0 = op0->match, match1 = op1->match;
683 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
684 register unsigned int i;
685
686 /* If a bit is set in both match and lose, there is something
687 wrong with the opcode table. */
688 if (match0 & lose0)
689 {
690 fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
691 op0->name, match0, lose0);
692 op0->lose &= ~op0->match;
693 lose0 = op0->lose;
694 }
695
696 if (match1 & lose1)
697 {
698 fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
699 op1->name, match1, lose1);
700 op1->lose &= ~op1->match;
701 lose1 = op1->lose;
702 }
703
704 /* Because the bits that are variable in one opcode are constant in
705 another, it is important to order the opcodes in the right order. */
706 for (i = 0; i < 32; ++i)
707 {
708 unsigned long int x = 1 << i;
709 int x0 = (match0 & x) != 0;
710 int x1 = (match1 & x) != 0;
711
712 if (x0 != x1)
713 return x1 - x0;
714 }
715
716 for (i = 0; i < 32; ++i)
717 {
718 unsigned long int x = 1 << i;
719 int x0 = (lose0 & x) != 0;
720 int x1 = (lose1 & x) != 0;
721
722 if (x0 != x1)
723 return x1 - x0;
724 }
725
726 /* Put non-sparc64 insns ahead of sparc64 ones. */
727 if ((op0->architecture >= v9) != (op1->architecture >= v9))
728 return (op0->architecture >= v9) - (op1->architecture >= v9);
729
730 /* They are functionally equal. So as long as the opcode table is
731 valid, we can put whichever one first we want, on aesthetic grounds. */
732
733 /* Our first aesthetic ground is that aliases defer to real insns. */
734 {
735 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
736 if (alias_diff != 0)
737 /* Put the one that isn't an alias first. */
738 return alias_diff;
739 }
740
741 /* Except for aliases, two "identical" instructions had
742 better have the same opcode. This is a sanity check on the table. */
743 i = strcmp (op0->name, op1->name);
744 if (i)
745 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
746 return i;
747 else
748 fprintf (stderr,
749 "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
750 op0->name, op1->name);
751
752 /* Fewer arguments are preferred. */
753 {
754 int length_diff = strlen (op0->args) - strlen (op1->args);
755 if (length_diff != 0)
756 /* Put the one with fewer arguments first. */
757 return length_diff;
758 }
759
760 /* Put 1+i before i+1. */
761 {
762 char *p0 = (char *) strchr(op0->args, '+');
763 char *p1 = (char *) strchr(op1->args, '+');
764
765 if (p0 && p1)
766 {
767 /* There is a plus in both operands. Note that a plus
768 sign cannot be the first character in args,
769 so the following [-1]'s are valid. */
770 if (p0[-1] == 'i' && p1[1] == 'i')
771 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
772 return 1;
773 if (p0[1] == 'i' && p1[-1] == 'i')
774 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
775 return -1;
776 }
777 }
778
779 /* Put 1,i before i,1. */
780 {
781 int i0 = strncmp (op0->args, "i,1", 3) == 0;
782 int i1 = strncmp (op1->args, "i,1", 3) == 0;
783
784 if (i0 ^ i1)
785 return i0 - i1;
786 }
787
788 /* They are, as far as we can tell, identical.
789 Since qsort may have rearranged the table partially, there is
790 no way to tell which one was first in the opcode table as
791 written, so just say there are equal. */
792 return 0;
793 }
794
795 /* Build a hash table from the opcode table. */
796
797 static void
798 build_hash_table (table, hash_table, num_opcodes)
799 struct sparc_opcode *table;
800 struct opcode_hash **hash_table;
801 int num_opcodes;
802 {
803 register int i;
804 int hash_count[HASH_SIZE];
805 static struct opcode_hash *hash_buf = NULL;
806
807 /* Start at the end of the table and work backwards so that each
808 chain is sorted. */
809
810 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
811 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
812 if (hash_buf != NULL)
813 free (hash_buf);
814 hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes);
815 for (i = num_opcodes - 1; i >= 0; --i)
816 {
817 register int hash = HASH_INSN (sparc_opcodes[i].match);
818 register struct opcode_hash *h = &hash_buf[i];
819 h->next = hash_table[hash];
820 h->opcode = &sparc_opcodes[i];
821 hash_table[hash] = h;
822 ++hash_count[hash];
823 }
824
825 #if 0 /* for debugging */
826 {
827 int min_count = num_opcodes, max_count = 0;
828 int total;
829
830 for (i = 0; i < HASH_SIZE; ++i)
831 {
832 if (hash_count[i] < min_count)
833 min_count = hash_count[i];
834 if (hash_count[i] > max_count)
835 max_count = hash_count[i];
836 total += hash_count[i];
837 }
838
839 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
840 min_count, max_count, (double) total / HASH_SIZE);
841 }
842 #endif
843 }