opcodes/tic80-opc.c

   1 /* Opcode table for TI TMS320C80 (MVP).
   2    Copyright 1996 Free Software Foundation, Inc.
   3
   4 This file is part of GDB, GAS, and the GNU binutils.
   5
   6 GDB, GAS, and the GNU binutils are free software; you can redistribute
   7 them and/or modify them under the terms of the GNU General Public
   8 License as published by the Free Software Foundation; either version
   9 1, or (at your option) any later version.
  10
  11 GDB, GAS, and the GNU binutils are distributed in the hope that they
  12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  14 the GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this file; see the file COPYING.  If not, write to the Free
  18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include <stdio.h>
  21 #include "ansidecl.h"
  22 #include "opcode/tic80.h"
  23
  24 /* This file holds various tables for the TMS320C80 (MVP).
  25
  26    The opcode table is strictly constant data, so the compiler should
  27    be able to put it in the .text section.
  28
  29    This file also holds the operand table.  All knowledge about
  30    inserting operands into instructions and vice-versa is kept in this
  31    file.
  32
  33    The predefined register table maps from register names to register
  34    values.  */
  35
  36 \f
  37 /* Table of predefined symbol names, such as general purpose registers,
  38    floating point registers, condition codes, control registers, and bit
  39    numbers.
  40
  41    The table is sorted case independently by name so that it is suitable for
  42    searching via a binary search using a case independent comparison
  43    function.
  44
  45    Note that the type of the symbol is stored in the upper bits of the value
  46    field, which allows the value and type to be passed around as a unit in a
  47    single int.  The types have to be masked off before using the numeric
  48    value as a number.
  49 */
  50
  51 const struct predefined_symbol tic80_predefined_symbols[] =
  52 {
  53   { "a0",       TIC80_OPERAND_FPA | 0 },
  54   { "a1",       TIC80_OPERAND_FPA | 1 },
  55   { "alw.b",    TIC80_OPERAND_CC | 7 },
  56   { "alw.h",    TIC80_OPERAND_CC | 15 },
  57   { "alw.w",    TIC80_OPERAND_CC | 23 },
  58   { "ANASTAT",  TIC80_OPERAND_CR | 0x34 },
  59   { "BRK1",     TIC80_OPERAND_CR | 0x39 },
  60   { "BRK2",     TIC80_OPERAND_CR | 0x3A },
  61   { "CONFIG",   TIC80_OPERAND_CR | 2 },
  62   { "DLRU",     TIC80_OPERAND_CR | 0x500 },
  63   { "DTAG0",    TIC80_OPERAND_CR | 0x400 },
  64   { "DTAG1",    TIC80_OPERAND_CR | 0x401 },
  65   { "DTAG10",   TIC80_OPERAND_CR | 0x40A },
  66   { "DTAG11",   TIC80_OPERAND_CR | 0x40B },
  67   { "DTAG12",   TIC80_OPERAND_CR | 0x40C },
  68   { "DTAG13",   TIC80_OPERAND_CR | 0x40D },
  69   { "DTAG14",   TIC80_OPERAND_CR | 0x40E },
  70   { "DTAG15",   TIC80_OPERAND_CR | 0x40F },
  71   { "DTAG2",    TIC80_OPERAND_CR | 0x402 },
  72   { "DTAG3",    TIC80_OPERAND_CR | 0x403 },
  73   { "DTAG4",    TIC80_OPERAND_CR | 0x404 },
  74   { "DTAG5",    TIC80_OPERAND_CR | 0x405 },
  75   { "DTAG6",    TIC80_OPERAND_CR | 0x406 },
  76   { "DTAG7",    TIC80_OPERAND_CR | 0x407 },
  77   { "DTAG8",    TIC80_OPERAND_CR | 0x408 },
  78   { "DTAG9",    TIC80_OPERAND_CR | 0x409 },
  79   { "ECOMCNTL", TIC80_OPERAND_CR | 0x33 },
  80   { "EIP",      TIC80_OPERAND_CR | 1 },
  81   { "EPC",      TIC80_OPERAND_CR | 0 },
  82   { "eq.b",     TIC80_OPERAND_BITNUM  | 0 },
  83   { "eq.h",     TIC80_OPERAND_BITNUM  | 10 },
  84   { "eq.w",     TIC80_OPERAND_BITNUM  | 20 },
  85   { "eq0.b",    TIC80_OPERAND_CC | 2 },
  86   { "eq0.h",    TIC80_OPERAND_CC | 10 },
  87   { "eq0.w",    TIC80_OPERAND_CC | 18 },
  88   { "FLTADR",   TIC80_OPERAND_CR | 0x11 },
  89   { "FLTDTH",   TIC80_OPERAND_CR | 0x14 },
  90   { "FLTDTL",   TIC80_OPERAND_CR | 0x13 },
  91   { "FLTOP",    TIC80_OPERAND_CR | 0x10 },
  92   { "FLTTAG",   TIC80_OPERAND_CR | 0x12 },
  93   { "FPST",     TIC80_OPERAND_CR | 8 },
  94   { "ge.b",     TIC80_OPERAND_BITNUM  | 5 },
  95   { "ge.h",     TIC80_OPERAND_BITNUM  | 15 },
  96   { "ge.w",     TIC80_OPERAND_BITNUM  | 25 },
  97   { "ge0.b",    TIC80_OPERAND_CC | 3 },
  98   { "ge0.h",    TIC80_OPERAND_CC | 11 },
  99   { "ge0.w",    TIC80_OPERAND_CC | 19 },
 100   { "gt.b",     TIC80_OPERAND_BITNUM  | 2 },
 101   { "gt.h",     TIC80_OPERAND_BITNUM  | 12 },
 102   { "gt.w",     TIC80_OPERAND_BITNUM  | 22 },
 103   { "gt0.b",    TIC80_OPERAND_CC | 1 },
 104   { "gt0.h",    TIC80_OPERAND_CC | 9 },
 105   { "gt0.w",    TIC80_OPERAND_CC | 17 },
 106   { "hi.b",     TIC80_OPERAND_BITNUM  | 6 },
 107   { "hi.h",     TIC80_OPERAND_BITNUM  | 16 },
 108   { "hi.w",     TIC80_OPERAND_BITNUM  | 26 },
 109   { "hs.b",     TIC80_OPERAND_BITNUM  | 9 },
 110   { "hs.h",     TIC80_OPERAND_BITNUM  | 19 },
 111   { "hs.w",     TIC80_OPERAND_BITNUM  | 29 },
 112   { "IE",       TIC80_OPERAND_CR | 6 },
 113   { "ILRU",     TIC80_OPERAND_CR | 0x300 },
 114   { "IN0P",     TIC80_OPERAND_CR | 0x4000 },
 115   { "IN1P",     TIC80_OPERAND_CR | 0x4001 },
 116   { "INTPEN",   TIC80_OPERAND_CR | 4 },
 117   { "ITAG0",    TIC80_OPERAND_CR | 0x200 },
 118   { "ITAG1",    TIC80_OPERAND_CR | 0x201 },
 119   { "ITAG10",   TIC80_OPERAND_CR | 0x20A },
 120   { "ITAG11",   TIC80_OPERAND_CR | 0x20B },
 121   { "ITAG12",   TIC80_OPERAND_CR | 0x20C },
 122   { "ITAG13",   TIC80_OPERAND_CR | 0x20D },
 123   { "ITAG14",   TIC80_OPERAND_CR | 0x20E },
 124   { "ITAG15",   TIC80_OPERAND_CR | 0x20F },
 125   { "ITAG2",    TIC80_OPERAND_CR | 0x202 },
 126   { "ITAG3",    TIC80_OPERAND_CR | 0x203 },
 127   { "ITAG4",    TIC80_OPERAND_CR | 0x204 },
 128   { "ITAG5",    TIC80_OPERAND_CR | 0x205 },
 129   { "ITAG6",    TIC80_OPERAND_CR | 0x206 },
 130   { "ITAG7",    TIC80_OPERAND_CR | 0x207 },
 131   { "ITAG8",    TIC80_OPERAND_CR | 0x208 },
 132   { "ITAG9",    TIC80_OPERAND_CR | 0x209 },
 133   { "le.b",     TIC80_OPERAND_BITNUM  | 3 },
 134   { "le.h",     TIC80_OPERAND_BITNUM  | 13 },
 135   { "le.w",     TIC80_OPERAND_BITNUM  | 23 },
 136   { "le0.b",    TIC80_OPERAND_CC | 6 },
 137   { "le0.h",    TIC80_OPERAND_CC | 14 },
 138   { "le0.w",    TIC80_OPERAND_CC | 22 },
 139   { "lo.b",     TIC80_OPERAND_BITNUM  | 8 },
 140   { "lo.h",     TIC80_OPERAND_BITNUM  | 18 },
 141   { "lo.w",     TIC80_OPERAND_BITNUM  | 28 },
 142   { "ls.b",     TIC80_OPERAND_BITNUM  | 7 },
 143   { "ls.h",     TIC80_OPERAND_BITNUM  | 17 },
 144   { "ls.w",     TIC80_OPERAND_BITNUM  | 27 },
 145   { "lt.b",     TIC80_OPERAND_BITNUM  | 4 },
 146   { "lt.h",     TIC80_OPERAND_BITNUM  | 14 },
 147   { "lt.w",     TIC80_OPERAND_BITNUM  | 24 },
 148   { "lt0.b",    TIC80_OPERAND_CC | 4 },
 149   { "lt0.h",    TIC80_OPERAND_CC | 12 },
 150   { "lt0.w",    TIC80_OPERAND_CC | 20 },
 151   { "MIP",      TIC80_OPERAND_CR | 0x31 },
 152   { "MPC",      TIC80_OPERAND_CR | 0x30 },
 153   { "ne.b",     TIC80_OPERAND_BITNUM  | 1 },
 154   { "ne.h",     TIC80_OPERAND_BITNUM  | 11 },
 155   { "ne.w",     TIC80_OPERAND_BITNUM  | 21 },
 156   { "ne0.b",    TIC80_OPERAND_CC | 5 },
 157   { "ne0.h",    TIC80_OPERAND_CC | 13 },
 158   { "ne0.w",    TIC80_OPERAND_CC | 21 },
 159   { "nev.b",    TIC80_OPERAND_CC | 0 },
 160   { "nev.h",    TIC80_OPERAND_CC | 8 },
 161   { "nev.w",    TIC80_OPERAND_CC | 16 },
 162   { "OUTP",     TIC80_OPERAND_CR | 0x4002 },
 163   { "PKTREQ",   TIC80_OPERAND_CR | 0xD },
 164   { "PPERROR",  TIC80_OPERAND_CR | 0xA },
 165   { "r0",       TIC80_OPERAND_GPR | 0 },
 166   { "r1",       TIC80_OPERAND_GPR | 1 },
 167   { "r10",      TIC80_OPERAND_GPR | 10 },
 168   { "r11",      TIC80_OPERAND_GPR | 11 },
 169   { "r12",      TIC80_OPERAND_GPR | 12 },
 170   { "r13",      TIC80_OPERAND_GPR | 13 },
 171   { "r14",      TIC80_OPERAND_GPR | 14 },
 172   { "r15",      TIC80_OPERAND_GPR | 15 },
 173   { "r16",      TIC80_OPERAND_GPR | 16 },
 174   { "r17",      TIC80_OPERAND_GPR | 17 },
 175   { "r18",      TIC80_OPERAND_GPR | 18 },
 176   { "r19",      TIC80_OPERAND_GPR | 19 },
 177   { "r2",       TIC80_OPERAND_GPR | 2 },
 178   { "r20",      TIC80_OPERAND_GPR | 20 },
 179   { "r21",      TIC80_OPERAND_GPR | 21 },
 180   { "r22",      TIC80_OPERAND_GPR | 22 },
 181   { "r23",      TIC80_OPERAND_GPR | 23 },
 182   { "r24",      TIC80_OPERAND_GPR | 24 },
 183   { "r24",      TIC80_OPERAND_GPR | 24 },
 184   { "r26",      TIC80_OPERAND_GPR | 26 },
 185   { "r27",      TIC80_OPERAND_GPR | 27 },
 186   { "r28",      TIC80_OPERAND_GPR | 28 },
 187   { "r29",      TIC80_OPERAND_GPR | 29 },
 188   { "r3",       TIC80_OPERAND_GPR | 3 },
 189   { "r30",      TIC80_OPERAND_GPR | 30 },
 190   { "r31",      TIC80_OPERAND_GPR | 31 },
 191   { "r4",       TIC80_OPERAND_GPR | 4 },
 192   { "r5",       TIC80_OPERAND_GPR | 5 },
 193   { "r6",       TIC80_OPERAND_GPR | 6 },
 194   { "r7",       TIC80_OPERAND_GPR | 7 },
 195   { "r8",       TIC80_OPERAND_GPR | 8 },
 196   { "r9",       TIC80_OPERAND_GPR | 9 },
 197   { "SYSSTK",   TIC80_OPERAND_CR | 0x20 },
 198   { "SYSTMP",   TIC80_OPERAND_CR | 0x21 },
 199   { "TCOUNT",   TIC80_OPERAND_CR | 0xE },
 200   { "TSCALE",   TIC80_OPERAND_CR | 0xF },
 201 };
 202
 203 const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol);
 204
 205 /* This function takes a predefined symbol name in NAME and translates
 206    it to a numeric value, which it returns.  If no translation is
 207    possible, it returns -1, a value not used by any predefined
 208    symbol. Note that the predefined symbol array is presorted case
 209    independently by name. */
 210
 211 int
 212 tic80_symbol_to_value (name)
 213      char *name;
 214 {
 215   int low = 0;
 216   int middle;
 217   int high = tic80_num_predefined_symbols - 1;
 218   int cmp;
 219   int rtnval = -1;
 220
 221   while (low <= high)
 222     {
 223       middle = (low + high) / 2;
 224       cmp = strcasecmp (name, tic80_predefined_symbols[middle].name);
 225       if (cmp < 0)
 226         {
 227           high = middle - 1;
 228         }
 229       else if (cmp > 0)
 230         {
 231           low = middle + 1;
 232         }
 233       else
 234         {
 235           rtnval = tic80_predefined_symbols[middle].value;
 236           break;
 237         }
 238     }
 239   return (rtnval);
 240 }
 241
 242 /* This function takes a value VAL and finds a matching predefined
 243    symbol that is in the operand class specified by CLASS.  If CLASS
 244    is zero, the first matching symbol is returned. */
 245
 246 const char *
 247 tic80_value_to_symbol (val, class)
 248      int val;
 249      int class;
 250 {
 251   const struct predefined_symbol *pdsp;
 252   int ival;
 253   char *name;
 254
 255   name = NULL;
 256   for (pdsp = tic80_predefined_symbols;
 257        pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols;
 258        pdsp++)
 259     {
 260       ival = pdsp -> value & ~TIC80_OPERAND_MASK;
 261       if (ival == val)
 262         {
 263           if ((class == 0) || (class & pdsp -> value))
 264             {
 265               /* Found the desired match */
 266               name = pdsp -> name;
 267               break;
 268             }
 269         }
 270     }
 271   return (name);
 272 }
 273
 274 \f
 275 /* The operands table.  The fields are:
 276
 277         bits, shift, insertion function, extraction function, flags
 278  */
 279
 280 const struct tic80_operand tic80_operands[] =
 281 {
 282
 283   /* The zero index is used to indicate the end of the list of operands.  */
 284
 285 #define UNUSED (0)
 286   { 0, 0, 0, 0, 0 },
 287
 288   /* Short signed immediate value in bits 14-0. */
 289
 290 #define SSI (UNUSED + 1)
 291   { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
 292
 293   /* Short unsigned immediate value in bits 14-0 */
 294
 295 #define SUI (SSI + 1)
 296   { 15, 0, NULL, NULL, 0 },
 297
 298   /* Short unsigned bitfield in bits 14-0.  We distinguish this
 299      from a regular unsigned immediate value only for the convenience
 300      of the disassembler and the user. */
 301
 302 #define SUBF (SUI + 1)
 303   { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
 304
 305   /* Long signed immediate in following 32 bit word */
 306
 307 #define LSI (SUBF + 1)
 308   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
 309
 310   /* Long unsigned immediate in following 32 bit word */
 311
 312 #define LUI (LSI + 1)
 313   { 32, 0, NULL, NULL, 0 },
 314
 315   /* Long unsigned bitfield in following 32 bit word.  We distinguish
 316      this from a regular unsigned immediate value only for the
 317      convenience of the disassembler and the user. */
 318
 319 #define LUBF (LUI + 1)
 320   { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
 321
 322   /* Single precision floating point immediate in following 32 bit
 323      word. */
 324
 325 #define SPFI (LUBF + 1)
 326   { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
 327
 328   /* Register in bits 4-0 */
 329
 330 #define REG_0 (SPFI + 1)
 331   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
 332
 333   /* Register in bits 26-22 */
 334
 335 #define REG_22 (REG_0 + 1)
 336   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
 337
 338   /* Register in bits 31-27 */
 339
 340 #define REG_DEST (REG_22 + 1)
 341   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
 342
 343   /* Short signed PC word offset in bits 14-0 */
 344
 345 #define OFF_SS_PC (REG_DEST + 1)
 346   { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
 347
 348   /* Long signed PC word offset in following 32 bit word */
 349
 350 #define OFF_SL_PC (OFF_SS_PC + 1)
 351   {32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
 352
 353   /* Short signed base relative byte offset in bits 14-0 */
 354
 355 #define OFF_SS_BR (OFF_SL_PC + 1)
 356   { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
 357
 358   /* Long signed base relative byte offset in following 32 bit word */
 359
 360 #define OFF_SL_BR (OFF_SS_BR + 1)
 361   {32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
 362
 363   /* BITNUM in bits 31-27 */
 364
 365 #define BITNUM (OFF_SL_BR + 1)
 366   { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
 367
 368   /* Condition code in bits 31-27 */
 369
 370 #define CC (BITNUM + 1)
 371   { 5, 27, NULL, NULL, TIC80_OPERAND_CC },
 372
 373   /* Control register number in bits 14-0 */
 374
 375 #define CR_SI (CC + 1)
 376   { 15, 0, NULL, NULL, TIC80_OPERAND_CR },
 377
 378   /* Control register number in next 32 bit word */
 379
 380 #define CR_LI (CR_SI + 1)
 381   { 32, 0, NULL, NULL, TIC80_OPERAND_CR },
 382
 383   /* A base register in bits 26-22, enclosed in parens */
 384
 385 #define REG_BASE (CR_LI + 1)
 386   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS },
 387
 388   /* A base register in bits 26-22, enclosed in parens, with optional ":m"
 389      flag in bit 17 (short immediate instructions only) */
 390
 391 #define REG_BASE_M_SI (REG_BASE + 1)
 392   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
 393
 394   /* A base register in bits 26-22, enclosed in parens, with optional ":m"
 395    flag in bit 15 (long immediate and register instructions only) */
 396
 397 #define REG_BASE_M_LI (REG_BASE_M_SI + 1)
 398   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
 399
 400   /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */
 401
 402 #define REG_SCALED (REG_BASE_M_LI + 1)
 403   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
 404
 405   /* Long signed immediate in following 32 bit word, with optional ":s" modifier
 406      flag in bit 11 */
 407
 408 #define LSI_SCALED (REG_SCALED + 1)
 409   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
 410
 411   /* Unsigned immediate in bits 4-0, used only for shift instructions */
 412
 413 #define ROTATE (LSI_SCALED + 1)
 414   { 5, 0, NULL, NULL, 0 },
 415
 416   /* Unsigned immediate in bits 9-5, used only for shift instructions */
 417 #define ENDMASK (ROTATE + 1)
 418   { 5, 5, NULL, NULL, 0 },
 419
 420 };
 421
 422 const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
 423
 424 \f
 425 /* Macros used to generate entries for the opcodes table. */
 426
 427 #define FIXME 0
 428
 429 /* Short-Immediate Format Instructions - basic opcode */
 430 #define OP_SI(x)        (((x) & 0x7F) << 15)
 431 #define MASK_SI         OP_SI(0x7F)
 432
 433 /* Long-Immediate Format Instructions - basic opcode */
 434 #define OP_LI(x)        (((x) & 0x3FF) << 12)
 435 #define MASK_LI         OP_LI(0x3FF)
 436
 437 /* Register Format Instructions - basic opcode */
 438 #define OP_REG(x)       OP_LI(x)        /* For readability */
 439 #define MASK_REG        MASK_LI         /* For readability */
 440
 441 /* The 'n' bit at bit 10 */
 442 #define n(x)            ((x) << 10)
 443
 444 /* The 'i' bit at bit 11 */
 445 #define i(x)            ((x) << 11)
 446
 447 /* The 'F' bit at bit 27 */
 448 #define F(x)            ((x) << 27)
 449
 450 /* The 'E' bit at bit 27 */
 451 #define E(x)            ((x) << 27)
 452
 453 /* The 'M' bit at bit 15 in register and long immediate opcodes */
 454 #define M_REG(x)        ((x) << 15)
 455 #define M_LI(x)         ((x) << 15)
 456
 457 /* The 'M' bit at bit 17 in short immediate opcodes */
 458 #define M_SI(x)         ((x) << 17)
 459
 460 /* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
 461 #define SZ_REG(x)       ((x) << 13)
 462 #define SZ_LI(x)        ((x) << 13)
 463
 464 /* The 'SZ' field at bits 16-15 in short immediate opcodes */
 465 #define SZ_SI(x)        ((x) << 15)
 466
 467 /* The 'D' (direct external memory access) bit at bit 10 in long immediate
 468    and register opcodes. */
 469 #define D(x)            ((x) << 10)
 470
 471 /* The 'S' (scale offset by data size) bit at bit 11 in long immediate
 472    and register opcodes. */
 473 #define S(x)            ((x) << 11)
 474
 475 /* The 'PD' field at bits 10-9 in floating point instructions */
 476 #define PD(x)           ((x) << 9)
 477
 478 /* The 'P2' field at bits 8-7 in floating point instructions */
 479 #define P2(x)           ((x) << 7)
 480
 481 /* The 'P1' field at bits 6-5 in floating point instructions */
 482 #define P1(x)           ((x) << 5)
 483
 484 /* The 'a' field at bit 16 in vector instructions */
 485 #define V_a1(x)         ((x) << 16)
 486
 487 /* The 'a' field at bit 11 in vector instructions */
 488 #define V_a0(x)         ((x) << 11)
 489
 490 /* The 'm' field at bit 10 in vector instructions */
 491 #define V_m(x)          ((x) << 10)
 492
 493 /* The 'S' field at bit 9 in vector instructions */
 494 #define V_S(x)          ((x) << 9)
 495
 496 /* The 'Z' field at bit 8 in vector instructions */
 497 #define V_Z(x)          ((x) << 8)
 498
 499 /* The 'p' field at bit 6 in vector instructions */
 500 #define V_p(x)          ((x) << 6)
 501
 502 /* The opcode field at bits 21-17 for vector instructions */
 503 #define OP_V(x)         ((x) << 17)
 504 #define MASK_V          OP_V(0x1F)
 505
 506 \f
 507 /* The opcode table.  Formatted for better readability on a wide screen.  Also, all
 508  entries with the same mnemonic are sorted so that they are adjacent in the table,
 509  allowing the use of a hash table to locate the first of a sequence of opcodes that have
 510  a particular name. */
 511
 512 const struct tic80_opcode tic80_opcodes[] = {
 513
 514   /* The "nop" instruction is really "rdcr 0,r0".  We put it first so that this
 515      specific bit pattern will get disassembled as a nop rather than an rdcr. The
 516      mask of all ones ensures that this will happen. */
 517
 518   {"nop",       OP_SI(0x4),     ~0,             0,              {0}                     },
 519
 520   /* The "br" instruction is really "bbz target,r0,31".  We put it first so that
 521      this specific bit pattern will get disassembled as a br rather than bbz. */
 522
 523   {"br",        OP_LI(0x391),   0xFFFFF000,     0,      {OFF_SL_PC}     },
 524   {"br",        OP_REG(0x390),  0xFFFFF000,     0,      {REG_0}         },
 525   {"br",        OP_SI(0x48),    0xFFFF8000,     0,      {OFF_SS_PC}     },
 526   {"br.a",      OP_LI(0x393),   0xFFFFF000,     0,      {OFF_SL_PC}     },
 527   {"br.a",      OP_REG(0x392),  0xFFFFF000,     0,      {REG_0}         },
 528   {"br.a",      OP_SI(0x49),    0xFFFF8000,     0,      {OFF_SS_PC}     },
 529
 530   /* Signed integer ADD */
 531
 532   {"add",       OP_LI(0x3B1),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
 533   {"add",       OP_REG(0x3B0),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 534   {"add",       OP_SI(0x58),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
 535
 536   /* Unsigned integer ADD */
 537
 538   {"addu",      OP_LI(0x3B3),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
 539   {"addu",      OP_REG(0x3B2),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 540   {"addu",      OP_SI(0x59),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
 541
 542   /* Bitwise AND */
 543
 544   {"and",       OP_LI(0x323),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 545   {"and",       OP_REG(0x322),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 546   {"and",       OP_SI(0x11),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 547   {"and.tt",    OP_LI(0x323),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 548   {"and.tt",    OP_REG(0x322),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 549   {"and.tt",    OP_SI(0x11),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 550
 551   /* Bitwise AND with ones complement of both sources */
 552
 553   {"and.ff",    OP_LI(0x331),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 554   {"and.ff",    OP_REG(0x330),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 555   {"and.ff",    OP_SI(0x18),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 556
 557   /* Bitwise AND with ones complement of source 1 */
 558
 559   {"and.ft",    OP_LI(0x329),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 560   {"and.ft",    OP_REG(0x328),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 561   {"and.ft",    OP_SI(0x14),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 562
 563   /* Bitwise AND with ones complement of source 2 */
 564
 565   {"and.tf",    OP_LI(0x325),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST}        },
 566   {"and.tf",    OP_REG(0x324),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 567   {"and.tf",    OP_SI(0x12),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST}        },
 568
 569   /* Branch Bit One - nonannulled */
 570
 571   {"bbo",       OP_LI(0x395),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 572   {"bbo",       OP_REG(0x394),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 573   {"bbo",       OP_SI(0x4A),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 574
 575   /* Branch Bit One - annulled */
 576
 577   {"bbo.a",     OP_LI(0x397),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 578   {"bbo.a",     OP_REG(0x396),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 579   {"bbo.a",     OP_SI(0x4B),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 580
 581   /* Branch Bit Zero - nonannulled */
 582
 583   {"bbz",       OP_LI(0x391),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 584   {"bbz",       OP_REG(0x390),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 585   {"bbz",       OP_SI(0x48),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 586
 587   /* Branch Bit Zero - annulled */
 588
 589   {"bbz.a",     OP_LI(0x393),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
 590   {"bbz.a",     OP_REG(0x392),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 591   {"bbz.a",     OP_SI(0x49),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },
 592
 593   /* Branch Conditional - nonannulled */
 594
 595   {"bcnd",      OP_LI(0x399),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
 596   {"bcnd",      OP_REG(0x398),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 597   {"bcnd",      OP_SI(0x4C),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },
 598
 599   /* Branch Conditional - annulled */
 600
 601   {"bcnd.a",    OP_LI(0x39B),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
 602   {"bcnd.a",    OP_REG(0x39A),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 603   {"bcnd.a",    OP_SI(0x4D),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },
 604
 605   /* Branch Control Register */
 606
 607   {"brcr",      OP_LI(0x30D),   MASK_LI,        0,      {CR_LI} },
 608   {"brcr",      OP_REG(0x30C),  MASK_REG,       0,      {REG_0} },
 609   {"brcr",      OP_SI(0x6),     MASK_SI,        0,      {CR_SI} },
 610
 611   /* Branch and save return - nonannulled */
 612
 613   {"bsr",       OP_LI(0x381),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
 614   {"bsr",       OP_REG(0x380),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 615   {"bsr",       OP_SI(0x40),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },
 616
 617   /* Branch and save return - annulled */
 618
 619   {"bsr.a",     OP_LI(0x383),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
 620   {"bsr.a",     OP_REG(0x382),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 621   {"bsr.a",     OP_SI(0x41),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },
 622
 623   /* Send command */
 624
 625   {"cmnd",      OP_LI(0x305),   MASK_LI,        0,      {LUI}   },
 626   {"cmnd",      OP_REG(0x304),  MASK_REG,       0,      {REG_0} },
 627   {"cmnd",      OP_SI(0x2),     MASK_SI,        0,      {SUI}   },
 628
 629   /* Integer compare */
 630
 631   {"cmp",       OP_LI(0x3A1),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
 632   {"cmp",       OP_REG(0x3A0),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 633   {"cmp",       OP_SI(0x50),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
 634
 635   /* Flush data cache subblock - don't clear subblock preset flag */
 636
 637   {"dcachec",   OP_LI(0x371),   F(1) | (MASK_LI  & ~M_LI(1))  | S(1) | D(1),    0, {LSI, REG_BASE_M_LI}         },
 638   {"dcachec",   OP_REG(0x370),  F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),    0, {REG_0, REG_BASE_M_LI}       },
 639   {"dcachec",   OP_SI(0x38),    F(1) | (MASK_SI  & ~M_SI(1)),                   0, {SSI, REG_BASE_M_SI}         },
 640
 641   /* Flush data cache subblock - clear subblock preset flag */
 642
 643   {"dcachef",   OP_LI(0x371)  | F(1),   F(1) | (MASK_LI  & ~M_LI(1))   | S(1) | D(1),   0, {LSI, REG_BASE_M_LI}         },
 644   {"dcachef",   OP_REG(0x370) | F(1),   F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),    0, {REG_0, REG_BASE_M_LI}       },
 645   {"dcachef",   OP_SI(0x38)   | F(1),   F(1) | (MASK_SI  & ~M_SI(1)),                   0, {SSI, REG_BASE_M_SI}         },
 646
 647   /* Direct load signed data into register */
 648
 649   {"dld",       OP_LI(0x345)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 650   {"dld",       OP_REG(0x344) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 651   {"dld.b",     OP_LI(0x341)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 652   {"dld.b",     OP_REG(0x340) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 653   {"dld.d",     OP_LI(0x347)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 654   {"dld.d",     OP_REG(0x346) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 655   {"dld.h",     OP_LI(0x343)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 656   {"dld.h",     OP_REG(0x342) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 657
 658   /* Direct load unsigned data into register */
 659
 660   {"dld.ub",    OP_LI(0x351)  | D(1),   (MASK_LI  &  ~M_REG(1)) | D(1), 0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 661   {"dld.ub",    OP_REG(0x350) | D(1),   (MASK_REG & ~M_REG(1))  | D(1), 0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 662   {"dld.uh",    OP_LI(0x353)  | D(1),   (MASK_LI  &  ~M_REG(1)) | D(1), 0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 663   {"dld.uh",    OP_REG(0x352) | D(1),   (MASK_REG & ~M_REG(1))  | D(1), 0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 664
 665   /* Direct store data into memory */
 666
 667   {"dst",       OP_LI(0x365)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 668   {"dst",       OP_REG(0x364) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 669   {"dst.b",     OP_LI(0x361)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 670   {"dst.b",     OP_REG(0x360) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 671   {"dst.d",     OP_LI(0x367)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 672   {"dst.d",     OP_REG(0x366) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 673   {"dst.h",     OP_LI(0x363)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 674   {"dst.h",     OP_REG(0x362) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 675
 676   /* Emulation stop */
 677
 678   {"estop",     OP_LI(0x3FC),   MASK_LI,        0,              {0}     },
 679
 680   /* Emulation trap */
 681
 682   {"etrap",     OP_LI(0x303)  | E(1),   MASK_LI  | E(1),        0,      {LUI}   },
 683   {"etrap",     OP_REG(0x302) | E(1),   MASK_REG | E(1),        0,      {REG_0} },
 684   {"etrap",     OP_SI(0x1)    | E(1),   MASK_SI  | E(1),        0,      {SUI}   },
 685
 686   /* Floating-point addition */
 687
 688   {"fadd.ddd",  OP_REG(0x3E0) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 689   {"fadd.dsd",  OP_REG(0x3E0) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 690   {"fadd.sdd",  OP_LI(0x3E1)  | PD(1) | P2(1) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 691   {"fadd.sdd",  OP_REG(0x3E0) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 692   {"fadd.ssd",  OP_LI(0x3E1)  | PD(1) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 693   {"fadd.ssd",  OP_REG(0x3E0) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 694   {"fadd.sss",  OP_LI(0x3E1)  | PD(0) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 695   {"fadd.sss",  OP_REG(0x3E0) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 696
 697   /* Floating point compare */
 698
 699   {"fcmp.dd",   OP_REG(0x3EA) | PD(0) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 700   {"fcmp.ds",   OP_REG(0x3EA) | PD(0) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 701   {"fcmp.sd",   OP_LI(0x3EB)  | PD(0) | P2(1) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3),  0,    {SPFI, REG_22, REG_DEST}       },
 702   {"fcmp.sd",   OP_REG(0x3EA) | PD(0) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 703   {"fcmp.ss",   OP_LI(0x3EB)  | PD(0) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3),  0,    {SPFI, REG_22, REG_DEST}       },
 704   {"fcmp.ss",   OP_REG(0x3EA) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3),  0,    {REG_0, REG_22, REG_DEST}      },
 705
 706   /* Floating point divide */
 707
 708   {"fdiv.ddd",  OP_REG(0x3E6) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 709   {"fdiv.dsd",  OP_REG(0x3E6) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 710   {"fdiv.sdd",  OP_LI(0x3E7)  | PD(1) | P2(1) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 711   {"fdiv.sdd",  OP_REG(0x3E6) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 712   {"fdiv.ssd",  OP_LI(0x3E7)  | PD(1) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 713   {"fdiv.ssd",  OP_REG(0x3E6) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 714   {"fdiv.sss",  OP_LI(0x3E7)  | PD(0) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 715   {"fdiv.sss",  OP_REG(0x3E6) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 716
 717   /* Floating point multiply */
 718
 719   {"fmpy.ddd",  OP_REG(0x3E4) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 720   {"fmpy.dsd",  OP_REG(0x3E4) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 721   {"fmpy.iii",  OP_LI(0x3E5)  | PD(2) | P2(2) | P1(2),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_22, REG_DEST}        },
 722   {"fmpy.iii",  OP_REG(0x3E4) | PD(2) | P2(2) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 723   {"fmpy.sdd",  OP_LI(0x3E5)  | PD(1) | P2(1) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 724   {"fmpy.sdd",  OP_REG(0x3E4) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 725   {"fmpy.ssd",  OP_LI(0x3E5)  | PD(1) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 726   {"fmpy.ssd",  OP_REG(0x3E4) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 727   {"fmpy.sss",  OP_LI(0x3E5)  | PD(0) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 728   {"fmpy.sss",  OP_REG(0x3E4) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 729   {"fmpy.uuu",  OP_LI(0x3E5)  | PD(3) | P2(3) | P1(3),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LUI, REG_22, REG_DEST}        },
 730   {"fmpy.uuu",  OP_REG(0x3E4) | PD(3) | P2(3) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 731
 732   /* Convert/Round to Minus Infinity */
 733
 734   {"frndm.dd",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 735   {"frndm.di",  OP_REG(0x3E8) | PD(2) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 736   {"frndm.ds",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 737   {"frndm.du",  OP_REG(0x3E8) | PD(3) | P2(3) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 738   {"frndm.id",  OP_LI(0x3E9)  | PD(1) | P2(3) | P1(2),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 739   {"frndm.id",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 740   {"frndm.is",  OP_LI(0x3E9)  | PD(0) | P2(3) | P1(2),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 741   {"frndm.is",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 742   {"frndm.sd",  OP_LI(0x3E9)  | PD(1) | P2(3) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 743   {"frndm.sd",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 744   {"frndm.si",  OP_LI(0x3E9)  | PD(2) | P2(3) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 745   {"frndm.si",  OP_REG(0x3E8) | PD(2) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 746   {"frndm.ss",  OP_LI(0x3E9)  | PD(0) | P2(3) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 747   {"frndm.ss",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 748   {"frndm.su",  OP_LI(0x3E9)  | PD(3) | P2(3) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 749   {"frndm.su",  OP_REG(0x3E8) | PD(3) | P2(3) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 750   {"frndm.ud",  OP_LI(0x3E9)  | PD(1) | P2(3) | P1(3),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 751   {"frndm.ud",  OP_REG(0x3E8) | PD(1) | P2(3) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 752   {"frndm.us",  OP_LI(0x3E9)  | PD(0) | P2(3) | P1(3),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 753   {"frndm.us",  OP_REG(0x3E8) | PD(0) | P2(3) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 754
 755   /* Convert/Round to Nearest */
 756
 757   {"frndn.dd",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 758   {"frndn.di",  OP_REG(0x3E8) | PD(2) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 759   {"frndn.ds",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 760   {"frndn.du",  OP_REG(0x3E8) | PD(3) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 761   {"frndn.id",  OP_LI(0x3E9)  | PD(1) | P2(0) | P1(2),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 762   {"frndn.id",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 763   {"frndn.is",  OP_LI(0x3E9)  | PD(0) | P2(0) | P1(2),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 764   {"frndn.is",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 765   {"frndn.sd",  OP_LI(0x3E9)  | PD(1) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 766   {"frndn.sd",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 767   {"frndn.si",  OP_LI(0x3E9)  | PD(2) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 768   {"frndn.si",  OP_REG(0x3E8) | PD(2) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 769   {"frndn.ss",  OP_LI(0x3E9)  | PD(0) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 770   {"frndn.ss",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 771   {"frndn.su",  OP_LI(0x3E9)  | PD(3) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 772   {"frndn.su",  OP_REG(0x3E8) | PD(3) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 773   {"frndn.ud",  OP_LI(0x3E9)  | PD(1) | P2(0) | P1(3),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 774   {"frndn.ud",  OP_REG(0x3E8) | PD(1) | P2(0) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 775   {"frndn.us",  OP_LI(0x3E9)  | PD(0) | P2(0) | P1(3),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 776   {"frndn.us",  OP_REG(0x3E8) | PD(0) | P2(0) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 777
 778   /* Convert/Round to Positive Infinity */
 779
 780   {"frndp.dd",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 781   {"frndp.di",  OP_REG(0x3E8) | PD(2) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 782   {"frndp.ds",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 783   {"frndp.du",  OP_REG(0x3E8) | PD(3) | P2(2) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 784   {"frndp.id",  OP_LI(0x3E9)  | PD(1) | P2(2) | P1(2),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 785   {"frndp.id",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 786   {"frndp.is",  OP_LI(0x3E9)  | PD(0) | P2(2) | P1(2),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 787   {"frndp.is",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 788   {"frndp.sd",  OP_LI(0x3E9)  | PD(1) | P2(2) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 789   {"frndp.sd",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 790   {"frndp.si",  OP_LI(0x3E9)  | PD(2) | P2(2) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 791   {"frndp.si",  OP_REG(0x3E8) | PD(2) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 792   {"frndp.ss",  OP_LI(0x3E9)  | PD(0) | P2(2) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 793   {"frndp.ss",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 794   {"frndp.su",  OP_LI(0x3E9)  | PD(3) | P2(2) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 795   {"frndp.su",  OP_REG(0x3E8) | PD(3) | P2(2) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 796   {"frndp.ud",  OP_LI(0x3E9)  | PD(1) | P2(2) | P1(3),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 797   {"frndp.ud",  OP_REG(0x3E8) | PD(1) | P2(2) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 798   {"frndp.us",  OP_LI(0x3E9)  | PD(0) | P2(2) | P1(3),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 799   {"frndp.us",  OP_REG(0x3E8) | PD(0) | P2(2) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 800
 801   /* Convert/Round to Zero */
 802
 803   {"frndz.dd",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 804   {"frndz.di",  OP_REG(0x3E8) | PD(2) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 805   {"frndz.ds",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 806   {"frndz.du",  OP_REG(0x3E8) | PD(3) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 807   {"frndz.id",  OP_LI(0x3E9)  | PD(1) | P2(1) | P1(2),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 808   {"frndz.id",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 809   {"frndz.is",  OP_LI(0x3E9)  | PD(0) | P2(1) | P1(2),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 810   {"frndz.is",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(2),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 811   {"frndz.sd",  OP_LI(0x3E9)  | PD(1) | P2(1) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 812   {"frndz.sd",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 813   {"frndz.si",  OP_LI(0x3E9)  | PD(2) | P2(1) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 814   {"frndz.si",  OP_REG(0x3E8) | PD(2) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 815   {"frndz.ss",  OP_LI(0x3E9)  | PD(0) | P2(1) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 816   {"frndz.ss",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 817   {"frndz.su",  OP_LI(0x3E9)  | PD(3) | P2(1) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 818   {"frndz.su",  OP_REG(0x3E8) | PD(3) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 819   {"frndz.ud",  OP_LI(0x3E9)  | PD(1) | P2(1) | P1(3),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 820   {"frndz.ud",  OP_REG(0x3E8) | PD(1) | P2(1) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 821   {"frndz.us",  OP_LI(0x3E9)  | PD(0) | P2(1) | P1(3),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {LSI, REG_DEST}        },
 822   {"frndz.us",  OP_REG(0x3E8) | PD(0) | P2(1) | P1(3),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 823
 824   /* Floating point square root */
 825
 826   {"fsqrt.dd",  OP_REG(0x3EE) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 827   {"fsqrt.sd",  OP_LI(0x3EF)  | PD(1) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 828   {"fsqrt.sd",  OP_REG(0x3EE) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 829   {"fsqrt.ss",  OP_LI(0x3EF)  | PD(0) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_DEST}       },
 830   {"fsqrt.ss",  OP_REG(0x3EE) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_DEST}      },
 831
 832   /* Floating point subtraction */
 833
 834   { "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 835   { "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 836   { "fsub.sdd", OP_LI(0x3E3)  | PD(1) | P2(1) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 837   { "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 838   { "fsub.ssd", OP_LI(0x3E3)  | PD(1) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 839   { "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 840   { "fsub.sss", OP_LI(0x3E3)  | PD(0) | P2(0) | P1(0),  MASK_LI  | PD(3) | P2(3) | P1(3), 0,     {SPFI, REG_22, REG_DEST}       },
 841   { "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0),  MASK_REG | PD(3) | P2(3) | P1(3), 0,     {REG_0, REG_22, REG_DEST}      },
 842
 843   /* Illegal instructions */
 844
 845   {"illop0",    OP_SI(0x0),     MASK_SI,        0,      {0}     },
 846   {"illopF",    0x1FF << 13,    0x1FF << 13,    0,      {0}     },
 847
 848   /* Jump and save return */
 849
 850   {"jsr",       OP_LI(0x389),   MASK_LI,        0,      {OFF_SL_BR, REG_BASE, REG_DEST} },
 851   {"jsr",       OP_REG(0x388),  MASK_REG,       0,      {REG_0, REG_BASE, REG_DEST}     },
 852   {"jsr",       OP_SI(0x44),    MASK_SI,        0,      {OFF_SS_BR, REG_BASE, REG_DEST} },
 853   {"jsr.a",     OP_LI(0x38B),   MASK_LI,        0,      {OFF_SL_BR, REG_BASE, REG_DEST} },
 854   {"jsr.a",     OP_REG(0x38A),  MASK_REG,       0,      {REG_0, REG_BASE, REG_DEST}     },
 855   {"jsr.a",     OP_SI(0x45),    MASK_SI,        0,      {OFF_SS_BR, REG_BASE, REG_DEST} },
 856
 857   /* Load Signed Data Into Register */
 858
 859   {"ld",        OP_LI(0x345)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 860   {"ld",        OP_REG(0x344) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 861   {"ld",        OP_SI(0x22),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 862   {"ld.b",      OP_LI(0x341)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 863   {"ld.b",      OP_REG(0x340) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 864   {"ld.b",      OP_SI(0x20),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 865   {"ld.d",      OP_LI(0x347)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 866   {"ld.d",      OP_REG(0x346) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 867   {"ld.d",      OP_SI(0x23),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 868   {"ld.h",      OP_LI(0x343)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 869   {"ld.h",      OP_REG(0x342) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 870   {"ld.h",      OP_SI(0x21),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 871
 872   /* Load Unsigned Data Into Register */
 873
 874   {"ld.ub",     OP_LI(0x351)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 875   {"ld.ub",     OP_REG(0x350) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 876   {"ld.ub",     OP_SI(0x28),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 877   {"ld.uh",     OP_LI(0x353)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
 878   {"ld.uh",     OP_REG(0x352) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
 879   {"ld.uh",     OP_SI(0x29),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
 880
 881   /* Leftmost one */
 882
 883   {"lmo",       OP_LI(0x3F0),   MASK_LI,        0,      {REG_22, REG_DEST}      },
 884
 885   /* Bitwise logical OR */
 886
 887   {"or.ff",     OP_LI(0x33D),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 888   {"or.ff",     OP_REG(0x33C),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 889   {"or.ff",     OP_SI(0x1E),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 890   {"or.ft",     OP_LI(0x33B),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 891   {"or.ft",     OP_REG(0x33A),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 892   {"or.ft",     OP_SI(0x1D),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 893   {"or.tf",     OP_LI(0x337),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 894   {"or.tf",     OP_REG(0x336),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 895   {"or.tf",     OP_SI(0x1B),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 896   {"or.tt",     OP_LI(0x32F),   MASK_LI,        0,      {LUI, REG_22, REG_DEST}         },
 897   {"or.tt",     OP_REG(0x32E),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
 898   {"or.tt",     OP_SI(0x17),    MASK_SI,        0,      {SUI, REG_22, REG_DEST}         },
 899
 900   /* Read Control Register */
 901
 902   {"rdcr",      OP_LI(0x309),   MASK_LI  | (0x1F << 22),        0,      {CR_LI, REG_DEST}       },
 903   {"rdcr",      OP_REG(0x308),  MASK_REG | (0x1F << 22),        0,      {REG_0, REG_DEST}       },
 904   {"rdcr",      OP_SI(0x4),     MASK_SI  | (0x1F << 22),        0,      {CR_SI, REG_DEST}       },
 905
 906   /* Rightmost one */
 907
 908   {"rmo",       OP_LI(0x3F2),   MASK_LI,        0,              {REG_22, REG_DEST}      },
 909
 910   /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions.
 911      They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */
 912
 913
 914   {"ins",       OP_REG(0x31E) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 915   {"ins",       OP_SI(0xF)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 916   {"rotl",      OP_REG(0x310) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 917   {"rotl",      OP_SI(0x8)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 918   {"shl",       OP_REG(0x31C) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 919   {"shl",       OP_SI(0xE)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 920   {"sl.dm",     OP_REG(0x312) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 921   {"sl.dm",     OP_SI(0x9)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 922   {"sl.ds",     OP_REG(0x314) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 923   {"sl.ds",     OP_SI(0xA)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 924   {"sl.dz",     OP_REG(0x310) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 925   {"sl.dz",     OP_SI(0x8)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 926   {"sl.em",     OP_REG(0x318) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 927   {"sl.em",     OP_SI(0xC)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 928   {"sl.es",     OP_REG(0x31A) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 929   {"sl.es",     OP_SI(0xD)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 930   {"sl.ez",     OP_REG(0x316) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 931   {"sl.ez",     OP_SI(0xB)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 932   {"sl.im",     OP_REG(0x31E) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 933   {"sl.im",     OP_SI(0xF)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 934   {"sl.iz",     OP_REG(0x31C) | i(0) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 935   {"sl.iz",     OP_SI(0xE)    | i(0) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 936
 937   /* Shift Register Left With Inverted Endmask */
 938
 939   {"sli.dm",    OP_REG(0x312) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 940   {"sli.dm",    OP_SI(0x9)    | i(1) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 941   {"sli.ds",    OP_REG(0x314) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 942   {"sli.ds",    OP_SI(0xA)    | i(1) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 943   {"sli.dz",    OP_REG(0x310) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 944   {"sli.dz",    OP_SI(0x8)    | i(1) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 945   {"sli.em",    OP_REG(0x318) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 946   {"sli.em",    OP_SI(0xC)    | i(1) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 947   {"sli.es",    OP_REG(0x31A) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 948   {"sli.es",    OP_SI(0xD)    | i(1) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 949   {"sli.ez",    OP_REG(0x316) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 950   {"sli.ez",    OP_SI(0xB)    | i(1) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 951   {"sli.im",    OP_REG(0x31E) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 952   {"sli.im",    OP_SI(0xF)    | i(1) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 953   {"sli.iz",    OP_REG(0x31C) | i(1) | n(0),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 954   {"sli.iz",    OP_SI(0xE)    | i(1) | n(0),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 955
 956   /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions.
 957      They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */
 958
 959   {"exts",      OP_REG(0x314) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 960   {"exts",      OP_SI(0xA)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 961   {"extu",      OP_REG(0x310) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 962   {"extu",      OP_SI(0x8)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 963   {"rotr",      OP_REG(0x310) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 964   {"rotr",      OP_SI(0x8)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 965   {"sra",       OP_REG(0x31A) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 966   {"sra",       OP_SI(0xD)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 967   {"srl",       OP_REG(0x316) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 968   {"srl",       OP_SI(0xB)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 969   {"sr.dm",     OP_REG(0x312) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 970   {"sr.dm",     OP_SI(0x9)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 971   {"sr.ds",     OP_REG(0x314) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 972   {"sr.ds",     OP_SI(0xA)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 973   {"sr.dz",     OP_REG(0x310) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 974   {"sr.dz",     OP_SI(0x8)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 975   {"sr.em",     OP_REG(0x318) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 976   {"sr.em",     OP_SI(0xC)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 977   {"sr.es",     OP_REG(0x31A) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 978   {"sr.es",     OP_SI(0xD)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 979   {"sr.ez",     OP_REG(0x316) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 980   {"sr.ez",     OP_SI(0xB)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 981   {"sr.im",     OP_REG(0x31E) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 982   {"sr.im",     OP_SI(0xF)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 983   {"sr.iz",     OP_REG(0x31C) | i(0) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 984   {"sr.iz",     OP_SI(0xE)    | i(0) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 985
 986   /* Shift Register Right With Inverted Endmask */
 987
 988   {"sri.dm",    OP_REG(0x312) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 989   {"sri.dm",    OP_SI(0x9)    | i(1) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 990   {"sri.ds",    OP_REG(0x314) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 991   {"sri.ds",    OP_SI(0xA)    | i(1) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 992   {"sri.dz",    OP_REG(0x310) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 993   {"sri.dz",    OP_SI(0x8)    | i(1) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 994   {"sri.em",    OP_REG(0x318) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 995   {"sri.em",    OP_SI(0xC)    | i(1) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 996   {"sri.es",    OP_REG(0x31A) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 997   {"sri.es",    OP_SI(0xD)    | i(1) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
 998   {"sri.ez",    OP_REG(0x316) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
 999   {"sri.ez",    OP_SI(0xB)    | i(1) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
1000   {"sri.im",    OP_REG(0x31E) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
1001   {"sri.im",    OP_SI(0xF)    | i(1) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
1002   {"sri.iz",    OP_REG(0x31C) | i(1) | n(1),    MASK_REG | i(1) | n(1), 0,      {REG_0, ENDMASK, REG_22, REG_DEST}      },
1003   {"sri.iz",    OP_SI(0xE)    | i(1) | n(1),    MASK_SI  | i(1) | n(1), 0,      {ROTATE, ENDMASK, REG_22, REG_DEST}     },
1004
1005   /* Store Data into Memory */
1006
1007   {"st",        OP_LI(0x365)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
1008   {"st",        OP_REG(0x364) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
1009   {"st",        OP_SI(0x32),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}},
1010   {"st.b",      OP_LI(0x361)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
1011   {"st.b",      OP_REG(0x360) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
1012   {"st.b",      OP_SI(0x30),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}},
1013   {"st.d",      OP_LI(0x367)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
1014   {"st.d",      OP_REG(0x366) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
1015   {"st.d",      OP_SI(0x33),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}},
1016   {"st.h",      OP_LI(0x363)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
1017   {"st.h",      OP_REG(0x362) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
1018   {"st.h",      OP_SI(0x31),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}},
1019
1020   /* Signed Integer Subtract */
1021
1022   {"sub",       OP_LI(0x3B5),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
1023   {"sub",       OP_REG(0x3B4),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
1024   {"sub",       OP_SI(0x5A),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
1025
1026   /* Unsigned Integer Subtract */
1027
1028   {"subu",      OP_LI(0x3B7),   MASK_LI,        0,      {LSI, REG_22, REG_DEST}         },
1029   {"subu",      OP_REG(0x3B6),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
1030   {"subu",      OP_SI(0x5B),    MASK_SI,        0,      {SSI, REG_22, REG_DEST}         },
1031
1032   /* Write Control Register
1033      Is a special form of the "swcr" instruction so comes before it in the table. */
1034
1035   {"wrcr",      OP_LI(0x30B),   MASK_LI | (0x1F << 27),         0,      {CR_LI, REG_22} },
1036   {"wrcr",      OP_REG(0x30A),  MASK_REG | (0x1F << 27),        0,      {REG_0, REG_22} },
1037   {"wrcr",      OP_SI(0x5),     MASK_SI | (0x1F << 27),         0,      {CR_SI, REG_22} },
1038
1039   /* Swap Control Register */
1040
1041   {"swcr",      OP_LI(0x30B),   MASK_LI,        0,      {CR_LI, REG_22, REG_DEST}       },
1042   {"swcr",      OP_REG(0x30A),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST}       },
1043   {"swcr",      OP_SI(0x5),     MASK_SI,        0,      {CR_SI, REG_22, REG_DEST}       },
1044
1045   /* Trap */
1046
1047   {"trap",      OP_LI(0x303)  | E(0),   MASK_LI  | E(1),        0,      {LUI}   },
1048   {"trap",      OP_REG(0x302) | E(0),   MASK_REG | E(1),        0,      {REG_0} },
1049   {"trap",      OP_SI(0x1)    | E(0),   MASK_SI  | E(1),        0,      {SUI}   },
1050
1051   /* Vector Floating-Point Add */
1052
1053   {"vadd.dd",   OP_REG(0x3C0) | P2(1) | P1(1),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
1054   {"vadd.sd",   OP_LI(0x3C1)  | P2(1) | P1(0),  MASK_LI  | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {SPFI, REG_22, REG_22}  },
1055   {"vadd.sd",   OP_REG(0x3C0) | P2(1) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
1056   {"vadd.ss",   OP_LI(0x3C1)  | P2(0) | P1(0),  MASK_LI  | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {SPFI, REG_22, REG_22}  },
1057   {"vadd.ss",   OP_REG(0x3C0) | P2(0) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
1058
1059   /* Vector Floating-Point Multiply and Add to Accumulator
1060    FIXME! This is not yet implemented.  From the documentation there appears to be no way to
1061    tell the difference between the opcodes for instructions that have register destinations
1062    and instructions that have accumulator destinations.  Further investigation is necessary.
1063    Since this isn't critical to getting a TIC80 toolchain up and running, it is defered
1064    until later. */
1065
1066   /* Vector Floating-Point Multiply
1067    Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */
1068
1069   {"vmpy.dd",   OP_REG(0x3C4) | P2(1) | P1(1),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
1070   {"vmpy.sd",   OP_LI(0x3C5)  | P2(1) | P1(0),  MASK_LI  | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} },
1071   {"vmpy.sd",   OP_REG(0x3C4) | P2(1) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
1072   {"vmpy.ss",   OP_LI(0x3C5)  | P2(0) | P1(0),  MASK_LI  | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} },
1073   {"vmpy.ss",   OP_REG(0x3C4) | P2(0) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
1074
1075   /* Vector Floating-Point Multiply and Subtract from Accumulator
1076      FIXME: See note above for vmac instruction */
1077
1078   /* Vector Floating-Point Subtract Accumulator From Source
1079      FIXME: See note above for vmac instruction */
1080
1081   /* Vector Round With Floating-Point Input
1082      FIXME: See note above for vmac instruction */
1083
1084   /* Vector Round with Integer Input */
1085
1086   {"vrnd.id",   OP_LI (0x3CB)  | P2(1) | P1(0), MASK_LI  | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {LSI, REG_22}},
1087   {"vrnd.id",   OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {REG_0, REG_22}},
1088   {"vrnd.is",   OP_LI (0x3CB)  | P2(0) | P1(0), MASK_LI  | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {LSI, REG_22}},
1089   {"vrnd.is",   OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {REG_0, REG_22}},
1090   {"vrnd.ud",   OP_LI (0x3CB)  | P2(1) | P1(1), MASK_LI  | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {LUI, REG_22}},
1091   {"vrnd.ud",   OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {REG_0, REG_22}},
1092   {"vrnd.us",   OP_LI (0x3CB)  | P2(0) | P1(1), MASK_LI  | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {LUI, REG_22}},
1093   {"vrnd.us",   OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),    TIC80_VECTOR, {REG_0, REG_22}},
1094
1095   /* Vector Floating-Point Subtract */
1096
1097   {"vsub.dd",   OP_REG(0x3C2) | P2(1) | P1(1),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
1098   {"vsub.sd",   OP_LI(0x3C3)  | P2(1) | P1(0),  MASK_LI  | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {SPFI, REG_22, REG_22}  },
1099   {"vsub.sd",   OP_REG(0x3C2) | P2(1) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
1100   {"vsub.ss",   OP_LI(0x3C3)  | P2(0) | P1(0),  MASK_LI  | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {SPFI, REG_22, REG_22}  },
1101   {"vsub.ss",   OP_REG(0x3C2) | P2(0) | P1(0),  MASK_REG | V_a1(1) | P2(1) | P1(1),     TIC80_VECTOR,   {REG_0, REG_22, REG_22} },
1102
1103   /* Vector Load Data Into Register - Note that the vector load/store instructions come after the other
1104    vector instructions so that the disassembler will always print the load/store instruction second for
1105    vector instructions that have two instructions in the same opcode. */
1106
1107   {"vld0.d",    OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
1108   {"vld0.s",    OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
1109   {"vld1.d",    OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
1110   {"vld1.s",    OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
1111
1112   /* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other
1113    vector instructions so that the disassembler will always print the load/store instruction second for
1114    vector instructions that have two instructions in the same opcode. */
1115
1116   {"vst.d",     OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
1117   {"vst.s",     OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1),  MASK_V | V_m(1) | V_S(1) | V_p(1),      TIC80_VECTOR, {REG_DEST} },
1118
1119   {"xnor",      OP_LI(0x333),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST} },
1120   {"xnor",      OP_REG(0x332),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST} },
1121   {"xnor",      OP_SI(0x19),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST} },
1122
1123   {"xor",       OP_LI(0x32D),   MASK_LI,        0,      {LUBF, REG_22, REG_DEST} },
1124   {"xor",       OP_REG(0x32C),  MASK_REG,       0,      {REG_0, REG_22, REG_DEST} },
1125   {"xor",       OP_SI(0x16),    MASK_SI,        0,      {SUBF, REG_22, REG_DEST} },
1126
1127 };
1128
1129 const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);