add store and ldq
[libreriscv.git] / openpower / isa / branch.mdwn
1 # Branch
2
3 b target_addr (AA=0 LK=0)
4
5 ba target_addr (AA=1 LK=0)
6
7 bl target_addr (AA=0 LK=1)
8
9 bla target_addr (AA=1 LK=1)
10
11 if AA then NIA <-iea EXTS(LI || 0b00)
12 else NIA <-iea CIA + EXTS(LI || 0b00)
13 if LK then LR <-iea CIA + 4
14
15 # Branch Conditional
16
17 bc BO,BI,target_addr (AA=0 LK=0)
18
19 bca BO,BI,target_addr (AA=1 LK=0)
20
21 bcl BO,BI,target_addr (AA=0 LK=1)
22
23 bcla BO,BI,target_addr (AA=1 LK=1)
24
25 if (64-bit mode)
26 then M <- 0
27 else M <- 32
28 if ¬BO[2] then CTR <- CTR - 1
29 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
30 cond_ok <- BO[0] | (CRBI+32 => BO[1])
31 if ctr_ok & cond_ok then
32 if AA then NIA <-iea EXTS(BD || 0b00)
33 else NIA <-iea CIA + EXTS(BD || 0b00)
34 if LK then LR <-iea CIA + 4
35
36 # Branch Conditional to Link Register
37
38 bclr BO,BI,BH (LK=0)
39
40 bclrl BO,BI,BH (LK=1)
41
42 if (64-bit mode)
43 then M <- 0
44 else M <- 32
45 if ¬BO[2] then CTR <- CTR - 1
46 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]
47 cond_ok <- BO[0] | (CR[BI+32] => BO[1])
48 if ctr_ok & cond_ok then NIA <- iea LR[0:61] || 0b00
49 if LK then LR <-iea CIA + 4
50
51 # Branch Conditional to Count Register
52
53 bcctr BO,BI,BH (LK=0)
54
55 bcctrl BO,BI,BH (LK=1)
56
57 cond_ok <- BO[0] | (CR[BI+32] => BO[1])
58 if cond_ok then NIA <-iea CTR[0:61] || 0b00
59 if LK then LR <- iea CIA + 4
60
61
62 # Branch Conditional to Branch Target Address Register
63
64 bctar BO,BI,BH (LK=0)
65
66 bctarl BO,BI,BH (LK=1)
67
68 if (64-bit mode)
69 then M <- 0
70 else M <- 32
71 if ¬BO[2] then CTR <- CTR - 1
72 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]
73 cond_ok <- BO[0] | (CR[BI+32] => BO[1])
74 if ctr_ok & cond_ok then NIA <-iea TAR[0:61] || 0b00
75 if LK then LR <-iea CIA + 4
76