5 * b target_addr (AA=0 LK=0)
6 * ba target_addr (AA=1 LK=0)
7 * bl target_addr (AA=0 LK=1)
8 * bla target_addr (AA=1 LK=1)
10 if AA then NIA <-iea EXTS(LI || 0b00)
11 else NIA <-iea CIA + EXTS(LI || 0b00)
12 if LK then LR <-iea CIA + 4
14 Special Registers Altered:
22 * bc BO,BI,target_addr (AA=0 LK=0)
23 * bca BO,BI,target_addr (AA=1 LK=0)
24 * bcl BO,BI,target_addr (AA=0 LK=1)
25 * bcla BO,BI,target_addr (AA=1 LK=1)
27 if (mode_is_64bit) then M <- 0
29 if ¬BO[2] then CTR <- CTR - 1
30 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
31 cond_ok <- BO[0] | ¬(CRBI+32 ^ BO[1])
32 if ctr_ok & cond_ok then
33 if AA then NIA <-iea EXTS(BD || 0b00)
34 else NIA <-iea CIA + EXTS(BD || 0b00)
35 if LK then LR <-iea CIA + 4
37 Special Registers Altered:
42 # Branch Conditional to Link Register
46 * bclr BO,BI,BH (LK=0)
47 * bclrl BO,BI,BH (LK=1)
49 if (mode_is_64bit) then M <- 0
51 if ¬BO[2] then CTR <- CTR - 1
52 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
53 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
54 if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
55 if LK then LR <-iea CIA + 4
57 Special Registers Altered:
62 # Branch Conditional to Count Register
66 * bcctr BO,BI,BH (LK=0)
67 * bcctrl BO,BI,BH (LK=1)
69 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
70 if cond_ok then NIA <-iea CTR[0:61] || 0b00
71 if LK then LR <-iea CIA + 4
73 Special Registers Altered:
77 # Branch Conditional to Branch Target Address Register
81 * bctar BO,BI,BH (LK=0)
82 * bctarl BO,BI,BH (LK=1)
84 if (mode_is_64bit) then M <- 0
86 if ¬BO[2] then CTR <- CTR - 1
87 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
88 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
89 if ctr_ok & cond_ok then NIA <-iea TAR[0:61] || 0b00
90 if LK then LR <-iea CIA + 4
92 Special Registers Altered: