5 * b target_addr (AA=0 LK=0)
6 * ba target_addr (AA=1 LK=0)
7 * bl target_addr (AA=0 LK=1)
8 * bla target_addr (AA=1 LK=1)
12 if AA then NIA <-iea EXTS(LI || 0b00)
13 else NIA <-iea CIA + EXTS(LI || 0b00)
14 if LK then LR <-iea CIA + 4
16 Special Registers Altered:
24 * bc BO,BI,target_addr (AA=0 LK=0)
25 * bca BO,BI,target_addr (AA=1 LK=0)
26 * bcl BO,BI,target_addr (AA=0 LK=1)
27 * bcla BO,BI,target_addr (AA=1 LK=1)
31 if (mode_is_64bit) then M <- 0
33 if ¬BO[2] then CTR <- CTR - 1
34 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
35 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
36 if ctr_ok & cond_ok then
37 if AA then NIA <-iea EXTS(BD || 0b00)
38 else NIA <-iea CIA + EXTS(BD || 0b00)
39 if LK then LR <-iea CIA + 4
41 Special Registers Altered:
46 # Branch Conditional to Link Register
50 * bclr BO,BI,BH (LK=0)
51 * bclrl BO,BI,BH (LK=1)
55 if (mode_is_64bit) then M <- 0
57 if ¬BO[2] then CTR <- CTR - 1
58 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
59 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
60 if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
61 if LK then LR <-iea CIA + 4
63 Special Registers Altered:
68 # Branch Conditional to Count Register
72 * bcctr BO,BI,BH (LK=0)
73 * bcctrl BO,BI,BH (LK=1)
77 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
78 if cond_ok then NIA <-iea CTR[0:61] || 0b00
79 if LK then LR <-iea CIA + 4
81 Special Registers Altered:
85 # Branch Conditional to Branch Target Address Register
89 * bctar BO,BI,BH (LK=0)
90 * bctarl BO,BI,BH (LK=1)
94 if (mode_is_64bit) then M <- 0
96 if ¬BO[2] then CTR <- CTR - 1
97 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
98 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
99 if ctr_ok & cond_ok then NIA <-iea TAR[0:61] || 0b00
100 if LK then LR <-iea CIA + 4
102 Special Registers Altered: