add branch pseudocode page
[libreriscv.git] / openpower / isa / branch.mdwn
1 # Branch
2
3 b
4 ba
5 bl
6 bla
7
8 target_addr
9 target_addr
10 target_addr
11 target_addr
12
13 (AA=0 LK=0)
14 (AA=1 LK=0)
15 (AA=0 LK=1)
16 (AA=1 LK=1)
17
18 if AA then NIA <-iea EXTS(LI || 0b00)
19 else NIA <-iea CIA + EXTS(LI || 0b00)
20 if LK then LR <-iea CIA + 4
21
22 # Branch Conditional
23
24 bc
25 bca
26 bcl
27 bcla
28
29 BO,BI,target_addr
30 BO,BI,target_addr
31 BO,BI,target_addr
32 BO,BI,target_addr
33
34 (AA=0 LK=0)
35 (AA=1 LK=0)
36 (AA=0 LK=1)
37 (AA=1 LK=1)
38
39 if (64-bit mode)
40 then M <- 0
41 else M <- 32
42 if ¬BO[2] then CTR <- CTR - 1
43 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
44 cond_ok <- BO[0] | (CRBI+32 => BO[1])
45 if ctr_ok & cond_ok then
46 if AA then NIA <-iea EXTS(BD || 0b00)
47 else NIA <-iea CIA + EXTS(BD || 0b00)
48 if LK then LR <-iea CIA + 4
49
50 # Branch Conditional to Link Register
51
52 XL-form
53
54 bclr
55 bclrl
56
57 BO,BI,BH
58 BO,BI,BH
59
60 (LK=0)
61 (LK=1)
62
63 if (64-bit mode)
64 then M <- 0
65 else M <- 32
66 if ¬BO[2] then CTR <- CTR - 1
67 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]
68 cond_ok <- BO[0] | (CR[BI+32] => BO[1])
69 if ctr_ok & cond_ok then NIA <- iea LR[0:61] || 0b00
70 if LK then LR <-iea CIA + 4
71
72 # Branch Conditional to Count Register
73
74 bcctr
75 bcctrl
76
77 BO,BI,BH
78 BO,BI,BH
79
80 (LK=0)
81 (LK=1)
82
83 cond_ok <- BO[0] | (CR[BI+32] => BO[1])
84 if cond_ok then NIA <-iea CTR[0:61] || 0b00
85 if LK then LR <- iea CIA + 4
86
87
88 # Branch Conditional to Branch Target Address Register
89
90 bctar
91 bctarl
92
93 BO,BI,BH
94 BO,BI,BH
95
96 (LK=0)
97 (LK=1)
98
99 if (64-bit mode)
100 then M <- 0
101 else M <- 32
102 if ¬BO[2] then CTR <- CTR - 1
103 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]
104 cond_ok <- BO[0] | (CR[BI+32] => BO[1])
105 if ctr_ok & cond_ok then NIA <-iea TAR[0:61] || 0b00
106 if LK then LR <-iea CIA + 4
107