openpower/isa/comparefixed.mdwn

   1 # Compare Immediate
   2
   3 D-Form
   4
   5 * cmpi BF,L,RA,SI
   6
   7 Pseudo-code:
   8
   9     if L = 0 then a <-  EXTS((RA)[32:63])
  10     else a <-  (RA)
  11     if      a < EXTS(SI) then c <- 0b100
  12     else if a > EXTS(SI) then c <- 0b010
  13     else                      c <- 0b001
  14     CR[4*BF+32:4*BF+35] <- c || XER[SO]
  15
  16 Special Registers Altered:
  17
  18     CR field BF
  19
  20 # Compare
  21 # Compare
  22
  23 X-Form
  24
  25 * cmp BF,L,RA,RB
  26
  27 Pseudo-code:
  28
  29     if L = 0 then
  30         a <-  EXTS((RA)[32:63] )
  31         b <- EXTS((RB)[32:63])
  32     else
  33         a <- (RA)
  34         b <- (RB)
  35     if      a < b then c <-  0b100
  36     else if a > b then c <-  0b010
  37     else               c <-  0b001
  38     CR[4*BF+32:4*BF+35] <-  c || XER[SO]
  39
  40 Special Registers Altered:
  41
  42     CR field BF
  43
  44 # Compare Logical Immediate
  45 # Compare Logical Immediate
  46
  47 D-Form
  48
  49 * cmpli BF,L,RA,UI
  50
  51 Pseudo-code:
  52
  53     if L = 0 then a <- [0]*32 || (RA)[32:63]
  54     else a <- (RA)
  55     if      a <u ( [0]*48 || UI) then c <- 0b100
  56     else if a >u ( [0]*48 || UI) then c <- 0b010
  57     else                         c <- 0b001
  58     CR[4*BF+32:4*BF+35] <- c || XER[SO]
  59
  60 Special Registers Altered:
  61
  62     CR field BF
  63
  64 # Compare Logical
  65 # Compare Logical
  66
  67 X-Form
  68
  69 * cmpl BF,L,RA,RB
  70
  71 Pseudo-code:
  72
  73     if L = 0 then
  74         a <- [0]*32 || (RA)[32:63]
  75         b <- [0]*32 || (RB)[32:63]
  76     else
  77         a <-  (RA)
  78         b <-  (RB)
  79     if      a <u b then c <- 0b100
  80     else if a >u b then c <- 0b010
  81     else                c <-  0b001
  82     CR[4*BF+32:4*BF+35] <- c || XER[SO]
  83
  84 Special Registers Altered:
  85
  86     CR field BF
  87
  88 # Compare Ranged Byte
  89 # Compare Ranged Byte
  90
  91 X-Form
  92
  93 * cmprb BF,L,RA,RB
  94
  95 Pseudo-code:
  96
  97     src1    <- EXTZ((RA)[56:63])
  98     src21hi <- EXTZ((RB)[32:39])
  99     src21lo <- EXTZ((RB)[40:47])
 100     src22hi <- EXTZ((RB)[48:55])
 101     src22lo <- EXTZ((RB)[56:63])
 102     if L=0 then
 103        in_range <-  (src22lo  <= src1) & (src1 <=  src22hi)
 104     else
 105        in_range <- (((src21lo  <= src1) & (src1 <=  src21hi)) |
 106                     ((src22lo  <= src1) & (src1 <=  src22hi)))
 107     CR[4*BF+32] <- 0b0
 108     CR[4*BF+33] <- in_range
 109     CR[4*BF+34] <- 0b0
 110     CR[4*BF+35] <- 0b0
 111
 112 Special Registers Altered:
 113
 114     CR field BF
 115
 116 # Compare Equal Byte
 117 # Compare Equal Byte
 118
 119 X-Form
 120
 121 * cmpeqb BF,RA,RB
 122
 123 Pseudo-code:
 124
 125     src1 <- GPR[RA]
 126     src1 <- src1[56:63]
 127     match <- ((src1 = (RB)[00:07]) |
 128               (src1 = (RB)[08:15]) |
 129               (src1 = (RB)[16:23]) |
 130               (src1 = (RB)[24:31]) |
 131               (src1 = (RB)[32:39]) |
 132               (src1 = (RB)[40:47]) |
 133               (src1 = (RB)[48:55]) |
 134               (src1 = (RB)[56:63]))
 135     CR[4*BF+32] <- 0b0
 136     CR[4*BF+33] <- match
 137     CR[4*BF+34] <- 0b0
 138     CR[4*BF+35] <- 0b0
 139
 140 Special Registers Altered:
 141
 142     CR field BF
 143