openpower/isa/fixedarith.mdwn

   1 # Add Immediate
   2
   3 D-Form
   4
   5 * addi RT,RA,SI
   6
   7 Pseudo-code:
   8
   9     RT <- (RA|0) + EXTS(SI)
  10
  11 Special Registers Altered:
  12
  13     None
  14
  15 # Add Immediate Shifted
  16
  17 D-Form
  18
  19 * addis RT,RA,SI
  20
  21 Pseudo-code:
  22
  23     RT <- (RA|0) + EXTS(SI || [0]*16)
  24
  25 Special Registers Altered:
  26
  27     None
  28
  29 # Add PC Immediate Shifted
  30
  31 DX-Form
  32
  33 * addpcis RT,D
  34
  35 Pseudo-code:
  36
  37     D <- d0||d1||d2
  38     RT <- NIA + EXTS(D || [0]*16)
  39
  40 Special Registers Altered:
  41
  42     None
  43
  44 # Add
  45
  46 XO-Form
  47
  48 * add RT,RA,RB (OE=0 Rc=0)
  49 * add.  RT,RA,RB (OE=0 Rc=1)
  50 * addo RT,RA,RB (OE=1 Rc=0)
  51 * addo.  RT,RA,RB (OE=1 Rc=1)
  52
  53 Pseudo-code:
  54
  55     RT <- (RA) + (RB)
  56
  57 Special Registers Altered:
  58
  59     CR0                     (if Rc=1)
  60     SO OV OV32             (if OE=1)
  61
  62 # Subtract From
  63
  64 XO-Form
  65
  66 * subf RT,RA,RB (OE=0 Rc=0)
  67 * subf.  RT,RA,RB (OE=0 Rc=1)
  68 * subfo RT,RA,RB (OE=1 Rc=0)
  69 * subfo.  RT,RA,RB (OE=1 Rc=1)
  70
  71 Pseudo-code:
  72
  73     RT <- ¬(RA) + (RB) + 1
  74
  75 Special Registers Altered:
  76
  77     CR0                     (if Rc=1)
  78     SO OV OV32             (if OE=1)
  79
  80 # Add Immediate Carrying
  81
  82 D-Form
  83
  84 * addic RT,RA,SI
  85
  86 Pseudo-code:
  87
  88     RT <- (RA) + EXTS(SI)
  89
  90 Special Registers Altered:
  91
  92     CA CA32
  93
  94 # Add Immediate Carrying and Record
  95
  96 D-Form
  97
  98 * addic. RT,RA,SI
  99
 100 Pseudo-code:
 101
 102     RT <- (RA) + EXTS(SI)
 103
 104 Special Registers Altered:
 105
 106     CR0 CA CA32
 107
 108 # Subtract From Immediate Carrying
 109
 110 D-Form
 111
 112 * subfic RT,RA,SI
 113
 114 Pseudo-code:
 115
 116     RT <- ¬(RA) + EXTS(SI) + 1
 117
 118 Special Registers Altered:
 119
 120     CA CA32
 121
 122 # Add Carrying
 123
 124 XO-Form
 125
 126 * addc RT,RA,RB (OE=0 Rc=0)
 127 * addc.  RT,RA,RB (OE=0 Rc=1)
 128 * addco RT,RA,RB (OE=1 Rc=0)
 129 * addco.  RT,RA,RB (OE=1 Rc=1)
 130
 131 Pseudo-code:
 132
 133     RT <- (RA) + (RB)
 134
 135 Special Registers Altered:
 136
 137     CA CA32
 138     CR0                     (if Rc=1)
 139     SO OV OV32             (if OE=1)
 140
 141 # Subtract From Carrying
 142
 143 XO-Form
 144
 145 * subfc RT,RA,RB (OE=0 Rc=0)
 146 * subfc.  RT,RA,RB (OE=0 Rc=1)
 147 * subfco RT,RA,RB (OE=1 Rc=0)
 148 * subfco.  RT,RA,RB (OE=1 Rc=1)
 149
 150 Pseudo-code:
 151
 152     RT <- ¬(RA) + (RB) + 1
 153
 154 Special Registers Altered:
 155
 156     CA CA32
 157     CR0                     (if Rc=1)
 158     SO OV OV32             (if OE=1)
 159
 160 # Add Extended
 161
 162 XO-Form
 163
 164 * adde RT,RA,RB (OE=0 Rc=0)
 165 * adde.  RT,RA,RB (OE=0 Rc=1)
 166 * addeo RT,RA,RB (OE=1 Rc=0)
 167 * addeo.  RT,RA,RB (OE=1 Rc=1)
 168
 169 Pseudo-code:
 170
 171     RT <- (RA) + (RB) + CA
 172
 173 Special Registers Altered:
 174
 175     CA CA32
 176     CR0                     (if Rc=1)
 177     SO OV OV32             (if OE=1)
 178
 179 # Subtract From Extended
 180
 181 XO-Form
 182
 183 * subfe RT,RA,RB (OE=0 Rc=0)
 184 * subfe.  RT,RA,RB (OE=0 Rc=1)
 185 * subfeo RT,RA,RB (OE=1 Rc=0)
 186 * subfeo.  RT,RA,RB (OE=1 Rc=1)
 187
 188 Pseudo-code:
 189
 190     RT <- ¬(RA) + (RB) + CA
 191
 192 Special Registers Altered:
 193
 194     CA CA32
 195     CR0                     (if Rc=1)
 196     SO OV OV32             (if OE=1)
 197
 198 # Add to Minus One Extended
 199
 200 XO-Form
 201
 202 * addme RT,RA (OE=0 Rc=0)
 203 * addme.  RT,RA (OE=0 Rc=1)
 204 * addmeo RT,RA (OE=1 Rc=0)
 205 * addmeo.  RT,RA (OE=1 Rc=1)
 206
 207 Pseudo-code:
 208
 209     RT <- (RA) + CA - 1
 210
 211 Special Registers Altered:
 212
 213     CA CA32
 214     CR0                     (if Rc=1)
 215     SO OV OV32             (if OE=1)
 216
 217 # Subtract From Minus One Extended
 218
 219 XO-Form
 220
 221 * subfme RT,RA (OE=0 Rc=0)
 222 * subfme.  RT,RA (OE=0 Rc=1)
 223 * subfmeo RT,RA (OE=1 Rc=0)
 224 * subfmeo.  RT,RA (OE=1 Rc=1)
 225
 226 Pseudo-code:
 227
 228     RT <- ¬(RA) + CA - 1
 229
 230 Special Registers Altered:
 231
 232     CA CA32
 233     CR0                     (if Rc=1)
 234     SO OV OV32             (if OE=1)
 235
 236 # Add Extended using alternate carry bit
 237
 238 Z23-Form
 239
 240 * addex RT,RA,RB,CY
 241
 242 Pseudo-code:
 243
 244     if CY=0 then RT <- (RA) + (RB) + OV
 245
 246 Special Registers Altered:
 247
 248     OV OV32                (if CY=0 )
 249
 250 # Subtract From Zero Extended
 251
 252 XO-Form
 253
 254 * subfze RT,RA (OE=0 Rc=0)
 255 * subfze.  RT,RA (OE=0 Rc=1)
 256 * subfzeo RT,RA (OE=1 Rc=0)
 257 * subfzeo.  RT,RA (OE=1 Rc=1)
 258
 259 Pseudo-code:
 260
 261     RT <- ¬(RA) + CA
 262
 263 Special Registers Altered:
 264
 265     CA CA32
 266     CR0                     (if Rc=1)
 267     SO OV OV32             (if OE=1)
 268
 269 # Add to Zero Extended
 270
 271 XO-Form
 272
 273 * addze RT,RA (OE=0 Rc=0)
 274 * addze.  RT,RA (OE=0 Rc=1)
 275 * addzeo RT,RA (OE=1 Rc=0)
 276 * addzeo.  RT,RA (OE=1 Rc=1)
 277
 278 Pseudo-code:
 279
 280     RT <- (RA) + CA
 281
 282 Special Registers Altered:
 283
 284     CA CA32
 285     CR0                     (if Rc=1)
 286     SO OV OV32             (if OE=1)
 287
 288 # Negate
 289
 290 XO-Form
 291
 292 * neg RT,RA (OE=0 Rc=0)
 293 * neg.  RT,RA (OE=0 Rc=1)
 294 * nego RT,RA (OE=1 Rc=0)
 295 * nego.  RT,RA (OE=1 Rc=1)
 296
 297 Pseudo-code:
 298
 299     RT <- ¬(RA) + 1
 300
 301 Special Registers Altered:
 302
 303     CR0                     (if Rc=1)
 304     SO OV OV32             (if OE=1)
 305
 306 # Multiply Low Immediate
 307
 308 D-Form
 309
 310 * mulli RT,RA,SI
 311
 312 Pseudo-code:
 313
 314     prod[0:127] <- MULS((RA), EXTS(SI))
 315     RT <- prod[64:127]
 316
 317 Special Registers Altered:
 318
 319     None
 320
 321 # Multiply High Word
 322
 323 XO-Form
 324
 325 * mulhw RT,RA,RB (Rc=0)
 326 * mulhw.  RT,RA,RB (Rc=1)
 327
 328 Pseudo-code:
 329
 330     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
 331     RT[32:63] <- prod[0:31]
 332     RT[0:31] <- prod[0:31]
 333
 334 Special Registers Altered:
 335
 336     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 337
 338 # Multiply Low Word
 339
 340 XO-Form
 341
 342 * mullw RT,RA,RB (OE=0 Rc=0)
 343 * mullw.  RT,RA,RB (OE=0 Rc=1)
 344 * mullwo RT,RA,RB (OE=1 Rc=0)
 345 * mullwo.  RT,RA,RB (OE=1 Rc=1)
 346
 347 Pseudo-code:
 348
 349     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
 350     RT <- prod
 351     overflow <- ((prod[0:32] != [0]*33) &
 352                  (prod[0:32] != [1]*33))
 353
 354 Special Registers Altered:
 355
 356     CR0                     (if Rc=1)
 357     SO OV OV32             (if OE=1)
 358
 359 # Multiply High Word Unsigned
 360
 361 XO-Form
 362
 363 * mulhwu RT,RA,RB (Rc=0)
 364 * mulhwu.  RT,RA,RB (Rc=1)
 365
 366 Pseudo-code:
 367
 368     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 369     RT[32:63] <- prod[0:31]
 370     RT[0:31] <- prod[0:31]
 371
 372 Special Registers Altered:
 373
 374     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 375
 376 # Divide Word
 377
 378 XO-Form
 379
 380 * divw RT,RA,RB (OE=0 Rc=0)
 381 * divw.  RT,RA,RB (OE=0 Rc=1)
 382 * divwo RT,RA,RB (OE=1 Rc=0)
 383 * divwo.  RT,RA,RB (OE=1 Rc=1)
 384
 385 Pseudo-code:
 386
 387     dividend[0:31] <-  (RA)[32:63]
 388     divisor[0:31] <- (RB) [32:63]
 389     if (((dividend = ([0]*31 || [1])) &
 390          (divisor = [1]*32)) |
 391          (divisor = [0]*32)) then
 392         RT[0:63] <- undefined([0]*64)
 393         overflow <- 1
 394     else
 395         RT[32:63] <- DIVS(dividend, divisor)
 396         RT[0:31] <- undefined([0]*32)
 397         overflow <- 0
 398
 399 Special Registers Altered:
 400
 401     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 402     SO OV OV32                              (if OE=1)
 403
 404 # Divide Word Unsigned
 405
 406 XO-Form
 407
 408 * divwu RT,RA,RB (OE=0 Rc=0)
 409 * divwu.  RT,RA,RB (OE=0 Rc=1)
 410 * divwuo RT,RA,RB (OE=1 Rc=0)
 411 * divwuo.  RT,RA,RB (OE=1 Rc=1)
 412
 413 Pseudo-code:
 414
 415     dividend[0:31] <- (RA)[32:63]
 416     divisor[0:31] <- (RB)[32:63]
 417     if divisor != 0 then
 418         RT[32:63] <-  dividend / divisor
 419         RT[0:31] <- undefined([0]*32)
 420         overflow <- 0
 421     else
 422         RT[0:63] <- undefined([0]*64)
 423         overflow <- 1
 424
 425 Special Registers Altered:
 426
 427     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 428     SO OV OV32                              (if OE=1)
 429
 430 # Divide Word Extended
 431
 432 XO-Form
 433
 434 * divwe RT,RA,RB (OE=0 Rc=0)
 435 * divwe.  RT,RA,RB (OE=0 Rc=1)
 436 * divweo RT,RA,RB (OE=1 Rc=0)
 437 * divweo.  RT,RA,RB (OE=1 Rc=1)
 438
 439 Pseudo-code:
 440
 441     dividend[0:63] <- (RA)[32:63] || [0]*32
 442     divisor[0:63] <- EXTS64((RB)[32:63])
 443     if (((dividend = 0x8000_0000_0000_0000) &
 444          (divisor = 0xffff_ffff_ffff_ffff)) |
 445          (divisor = 0x0000_0000_0000_0000)) then
 446         overflow <- 1
 447     else
 448         result <- DIVS(dividend, divisor)
 449         result32[0:63] <- EXTS64(result[32:63])
 450         if (result32 = result) then
 451             RT[32:63] <- result[32:63]
 452             RT[0:31] <- undefined([0]*32)
 453             overflow <- 0
 454         else
 455             overflow <- 1
 456     if overflow = 1 then
 457         RT[0:63] <- undefined([0]*64)
 458
 459 Special Registers Altered:
 460
 461     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 462     SO OV OV32                              (if OE=1)
 463
 464 # Divide Word Extended Unsigned
 465
 466 XO-Form
 467
 468 * divweu RT,RA,RB (OE=0 Rc=0)
 469 * divweu.  RT,RA,RB (OE=0 Rc=1)
 470 * divweuo RT,RA,RB (OE=1 Rc=0)
 471 * divweuo.  RT,RA,RB (OE=1 Rc=1)
 472
 473 Pseudo-code:
 474
 475     dividend[0:63] <- (RA)[32:63] || [0]*32
 476     divisor[0:63] <- [0]*32 || (RB)[32:63]
 477     if (divisor = 0x0000_0000_0000_0000) then
 478         overflow <- 1
 479     else
 480         result <- dividend / divisor
 481         if RA[32:63] <u RB[32:63] then
 482             RT[32:63] <- result[32:63]
 483             RT[0:31] <- undefined([0]*32)
 484             overflow <- 0
 485         else
 486             overflow <- 1
 487     if overflow = 1 then
 488         RT[0:63] <- undefined([0]*64)
 489
 490 Special Registers Altered:
 491
 492     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 493     SO OV OV32                              (if OE=1)
 494
 495 # Modulo Signed Word
 496
 497 X-Form
 498
 499 * modsw RT,RA,RB
 500
 501 Pseudo-code:
 502
 503     dividend[0:31] <- (RA)[32:63]
 504     divisor[0:31] <- (RB)[32:63]
 505     if (((dividend = 0x8000_0000) &
 506          (divisor = 0xffff_ffff)) |
 507          (divisor = 0x0000_0000)) then
 508         RT[0:63] <- undefined([0]*64)
 509         overflow <- 1
 510     else
 511         RT[0:63] <- EXTS64(MODS(dividend, divisor))
 512         RT[0:31] <- undefined(RT[0:31])
 513         overflow <- 0
 514
 515 Special Registers Altered:
 516
 517     None
 518
 519 # Modulo Unsigned Word
 520
 521 X-Form
 522
 523 * moduw RT,RA,RB
 524
 525 Pseudo-code:
 526
 527     dividend[0:31] <- (RA) [32:63]
 528     divisor [0:31] <- (RB) [32:63]
 529     if divisor = 0x0000_0000 then
 530         RT[0:63] <- undefined([0]*64)
 531         overflow <- 1
 532     else
 533         RT[32:63] <- dividend % divisor
 534         RT[0:31] <- undefined([0]*32)
 535         overflow <- 0
 536
 537 Special Registers Altered:
 538
 539     None
 540
 541 # Deliver A Random Number
 542
 543 X-Form
 544
 545 * darn RT,L3
 546
 547 Pseudo-code:
 548
 549     RT <- random(L3)
 550
 551 Special Registers Altered:
 552
 553     none
 554
 555 # Multiply Low Doubleword
 556
 557 XO-Form
 558
 559 * mulld RT,RA,RB (OE=0 Rc=0)
 560 * mulld.  RT,RA,RB (OE=0 Rc=1)
 561 * mulldo RT,RA,RB (OE=1 Rc=0)
 562 * mulldo.  RT,RA,RB (OE=1 Rc=1)
 563
 564 Pseudo-code:
 565
 566     prod[0:127] <- MULS((RA), (RB))
 567     RT <- prod[64:127]
 568     overflow <- ((prod[0:64] != [0]*65) &
 569                  (prod[0:64] != [1]*65))
 570
 571 Special Registers Altered:
 572
 573     CR0                     (if Rc=1)
 574     SO OV OV32             (if OE=1)
 575
 576 # Multiply High Doubleword
 577
 578 XO-Form
 579
 580 * mulhd RT,RA,RB (Rc=0)
 581 * mulhd.  RT,RA,RB (Rc=1)
 582
 583 Pseudo-code:
 584
 585     prod[0:127] <- MULS((RA), (RB))
 586     RT <- prod[0:63]
 587
 588 Special Registers Altered:
 589
 590     CR0                     (if Rc=1)
 591
 592 # Multiply High Doubleword Unsigned
 593
 594 XO-Form
 595
 596 * mulhdu RT,RA,RB (Rc=0)
 597 * mulhdu.  RT,RA,RB (Rc=1)
 598
 599 Pseudo-code:
 600
 601     prod[0:127] <- (RA) *  (RB)
 602     RT <- prod[0:63]
 603
 604 Special Registers Altered:
 605
 606     CR0                    (if Rc=1)
 607
 608 # Multiply-Add High Doubleword VA-Form
 609
 610 VA-Form
 611
 612 * maddhd RT,RA.RB,RC
 613
 614 Pseudo-code:
 615
 616     prod[0:127] <- MULS((RA), (RB))
 617     sum[0:127] <- prod + EXTS(RC)
 618     RT <- sum[0:63]
 619
 620 Special Registers Altered:
 621
 622     None
 623
 624 # Multiply-Add High Doubleword Unsigned
 625
 626 VA-Form
 627
 628 * maddhdu RT,RA.RB,RC
 629
 630 Pseudo-code:
 631
 632     prod[0:127] <- (RA) * (RB)
 633     sum[0:127] <- prod + EXTZ(RC)
 634     RT <- sum[0:63]
 635
 636 Special Registers Altered:
 637
 638     None
 639
 640 # Multiply-Add Low Doubleword
 641
 642 VA-Form
 643
 644 * maddld RT,RA.RB,RC
 645
 646 Pseudo-code:
 647
 648     prod[0:127] <- MULS((RA), (RB))
 649     sum[0:127] <- prod + EXTS(RC)
 650     RT <- sum[64:127]
 651
 652 Special Registers Altered:
 653
 654     None
 655
 656 # Divide Doubleword
 657
 658 XO-Form
 659
 660 * divd RT,RA,RB (OE=0 Rc=0)
 661 * divd.  RT,RA,RB (OE=0 Rc=1)
 662 * divdo RT,RA,RB (OE=1 Rc=0)
 663 * divdo.  RT,RA,RB (OE=1 Rc=1)
 664
 665 Pseudo-code:
 666
 667     dividend[0:63] <- (RA)
 668     divisor[0:63] <- (RB)
 669     if (((dividend = 0x8000_0000_0000_0000) &
 670          (divisor = 0xffff_ffff_ffff_ffff)) |
 671          (divisor = 0x0000_0000_0000_0000)) then
 672         RT[0:63] <- undefined([0]*64)
 673         overflow <- 1
 674     else
 675         RT <- DIVS(dividend, divisor)
 676         overflow <- 0
 677
 678 Special Registers Altered:
 679
 680     CR0                     (if Rc=1)
 681     SO OV OV32             (if OE=1)
 682
 683 # Divide Doubleword Unsigned
 684
 685 XO-Form
 686
 687 * divdu RT,RA,RB (OE=0 Rc=0)
 688 * divdu.  RT,RA,RB (OE=0 Rc=1)
 689 * divduo RT,RA,RB (OE=1 Rc=0)
 690 * divduo.  RT,RA,RB (OE=1 Rc=1)
 691
 692 Pseudo-code:
 693
 694     dividend[0:63] <- (RA)
 695     divisor[0:63] <- (RB)
 696     if (divisor = 0x0000_0000_0000_0000) then
 697         RT[0:63] <- undefined([0]*64)
 698         overflow <- 1
 699     else
 700         RT <- dividend / divisor
 701         overflow <- 0
 702
 703 Special Registers Altered:
 704
 705     CR0                     (if Rc=1)
 706     SO OV OV32             (if OE=1)
 707
 708 # Divide Doubleword Extended
 709
 710 XO-Form
 711
 712 * divde RT,RA,RB (OE=0 Rc=0)
 713 * divde.  RT,RA,RB (OE=0 Rc=1)
 714 * divdeo RT,RA,RB (OE=1 Rc=0)
 715 * divdeo.  RT,RA,RB (OE=1 Rc=1)
 716
 717 Pseudo-code:
 718
 719     dividend[0:127] <- (RA) || [0]*64
 720     divisor[0:127] <- EXTS128((RB))
 721     if (((dividend = 0x8000_0000_0000_0000_0000_0000_0000_0000) &
 722          (divisor = 0xffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff)) |
 723          (divisor = 0x0000_0000_0000_0000_0000_0000_0000_0000)) then
 724         overflow <- 1
 725     else
 726         result <- DIVS(dividend, divisor)
 727         result64[0:127] <- EXTS128(result[64:127])
 728         if (result64 = result) then
 729             RT <- result[64:127]
 730             overflow <- 0
 731         else
 732             overflow <- 1
 733     if overflow = 1 then
 734         RT[0:63] <- undefined([0]*64)
 735
 736 Special Registers Altered:
 737
 738     CR0                     (if Rc=1)
 739     SO OV OV32             (if OE=1)
 740
 741 # Divide Doubleword Extended Unsigned
 742
 743 XO-Form
 744
 745 * divdeu RT,RA,RB (OE=0 Rc=0)
 746 * divdeu.  RT,RA,RB (OE=0 Rc=1)
 747 * divdeuo RT,RA,RB (OE=1 Rc=0)
 748 * divdeuo.  RT,RA,RB (OE=1 Rc=1)
 749
 750 Pseudo-code:
 751
 752     dividend[0:127] <-  (RA) || [0]*64
 753     divisor[0:127] <- [0]*64 || (RB)
 754     if divisor = [0]*128 then
 755         overflow <- 1
 756     else
 757         result <- dividend / divisor
 758         if (RA) <u (RB) then
 759             RT <- result[64:127]
 760             overflow <- 0
 761         else
 762             overflow <- 1
 763     if overflow = 1 then
 764         RT[0:63] <- undefined([0]*64)
 765
 766 Special Registers Altered:
 767
 768     CR0                     (if Rc=1)
 769     SO OV OV32             (if OE=1)
 770
 771 # Modulo Signed Doubleword
 772
 773 X-Form
 774
 775 * modsd RT,RA,RB
 776
 777 Pseudo-code:
 778
 779     dividend <- (RA)
 780     divisor  <- (RB)
 781     if (((dividend = 0x8000_0000_0000_0000) &
 782          (divisor = 0xffff_ffff_ffff_ffff)) |
 783          (divisor = 0x0000_0000_0000_0000)) then
 784         RT[0:63] <- undefined([0]*64)
 785         overflow <- 1
 786     else
 787         RT       <- MODS(dividend, divisor)
 788         overflow <- 0
 789
 790 Special Registers Altered:
 791
 792     None
 793
 794 # Modulo Unsigned Doubleword
 795
 796 X-Form
 797
 798 * modud RT,RA,RB
 799
 800 Pseudo-code:
 801
 802     dividend <- (RA)
 803     divisor  <- (RB)
 804     if (divisor = 0x0000_0000_0000_0000) then
 805         RT[0:63] <- undefined([0]*64)
 806         overflow <- 1
 807     else
 808         RT       <- dividend % divisor
 809         overflow <- 0
 810
 811 Special Registers Altered:
 812
 813     None
 814