openpower/isa/fixedarith.mdwn

   1 # Add Immediate
   2
   3 D-Form
   4
   5 * addi RT,RA,SI
   6
   7 Pseudo-code:
   8
   9     if RA = 0 then RT <- EXTS(SI)
  10     else           RT <- (RA) + EXTS(SI)
  11
  12 Special Registers Altered:
  13
  14     None
  15
  16 # Add Immediate Shifted
  17
  18 D-Form
  19
  20 * addis RT,RA,SI
  21
  22 Pseudo-code:
  23
  24     if RA = 0 then RT <- EXTS(SI || [0]*16)
  25     else           RT <- (RA) + EXTS(SI || [0]*16)
  26
  27 Special Registers Altered:
  28
  29     None
  30
  31 # Add PC Immediate Shifted
  32
  33 DX-Form
  34
  35 * addpcis RT,D
  36
  37 Pseudo-code:
  38
  39     D <- d0||d1||d2
  40     RT <- NIA + EXTS(D || [0]*16)
  41
  42 Special Registers Altered:
  43
  44     None
  45
  46 # Add
  47
  48 XO-Form
  49
  50 * add RT,RA,RB (OE=0 Rc=0)
  51 * add.  RT,RA,RB (OE=0 Rc=1)
  52 * addo RT,RA,RB (OE=1 Rc=0)
  53 * addo.  RT,RA,RB (OE=1 Rc=1)
  54
  55 Pseudo-code:
  56
  57     RT <- (RA) + (RB)
  58
  59 Special Registers Altered:
  60
  61     CR0                     (if Rc=1)
  62     SO OV OV32             (if OE=1)
  63
  64 # Subtract From
  65
  66 XO-Form
  67
  68 * subf RT,RA,RB (OE=0 Rc=0)
  69 * subf.  RT,RA,RB (OE=0 Rc=1)
  70 * subfo RT,RA,RB (OE=1 Rc=0)
  71 * subfo.  RT,RA,RB (OE=1 Rc=1)
  72
  73 Pseudo-code:
  74
  75     RT <- ¬(RA) + (RB) + 1
  76
  77 Special Registers Altered:
  78
  79     CR0                     (if Rc=1)
  80     SO OV OV32             (if OE=1)
  81
  82 # Add Immediate Carrying
  83
  84 D-Form
  85
  86 * addic RT,RA,SI
  87
  88 Pseudo-code:
  89
  90     RT <- (RA) + EXTS(SI)
  91
  92 Special Registers Altered:
  93
  94     CA CA32
  95
  96 # Add Immediate Carrying and Record
  97
  98 D-Form
  99
 100 * addic. RT,RA,SI
 101
 102 Pseudo-code:
 103
 104     RT <- (RA) + EXTS(SI)
 105
 106 Special Registers Altered:
 107
 108     CR0 CA CA32
 109
 110 # Subtract From Immediate Carrying
 111
 112 D-Form
 113
 114 * subfic RT,RA,SI
 115
 116 Pseudo-code:
 117
 118     RT <- ¬(RA) + EXTS(SI) + 1
 119
 120 Special Registers Altered:
 121
 122     CA CA32
 123
 124 # Add Carrying
 125
 126 XO-Form
 127
 128 * addc RT,RA,RB (OE=0 Rc=0)
 129 * addc.  RT,RA,RB (OE=0 Rc=1)
 130 * addco RT,RA,RB (OE=1 Rc=0)
 131 * addco.  RT,RA,RB (OE=1 Rc=1)
 132
 133 Pseudo-code:
 134
 135     RT <- (RA) + (RB)
 136
 137 Special Registers Altered:
 138
 139     CA CA32
 140     CR0                     (if Rc=1)
 141     SO OV OV32             (if OE=1)
 142
 143 # Subtract From Carrying
 144
 145 XO-Form
 146
 147 * subfc RT,RA,RB (OE=0 Rc=0)
 148 * subfc.  RT,RA,RB (OE=0 Rc=1)
 149 * subfco RT,RA,RB (OE=1 Rc=0)
 150 * subfco.  RT,RA,RB (OE=1 Rc=1)
 151
 152 Pseudo-code:
 153
 154     RT <- ¬(RA) + (RB) + 1
 155
 156 Special Registers Altered:
 157
 158     CA CA32
 159     CR0                     (if Rc=1)
 160     SO OV OV32             (if OE=1)
 161
 162 # Add Extended
 163
 164 XO-Form
 165
 166 * adde RT,RA,RB (OE=0 Rc=0)
 167 * adde.  RT,RA,RB (OE=0 Rc=1)
 168 * addeo RT,RA,RB (OE=1 Rc=0)
 169 * addeo.  RT,RA,RB (OE=1 Rc=1)
 170
 171 Pseudo-code:
 172
 173     RT <- (RA) + (RB) + CA
 174
 175 Special Registers Altered:
 176
 177     CA CA32
 178     CR0                     (if Rc=1)
 179     SO OV OV32             (if OE=1)
 180
 181 # Subtract From Extended
 182
 183 XO-Form
 184
 185 * subfe RT,RA,RB (OE=0 Rc=0)
 186 * subfe.  RT,RA,RB (OE=0 Rc=1)
 187 * subfeo RT,RA,RB (OE=1 Rc=0)
 188 * subfeo.  RT,RA,RB (OE=1 Rc=1)
 189
 190 Pseudo-code:
 191
 192     RT <- ¬(RA) + (RB) + CA
 193
 194 Special Registers Altered:
 195
 196     CA CA32
 197     CR0                     (if Rc=1)
 198     SO OV OV32             (if OE=1)
 199
 200 # Add to Minus One Extended
 201
 202 XO-Form
 203
 204 * addme RT,RA (OE=0 Rc=0)
 205 * addme.  RT,RA (OE=0 Rc=1)
 206 * addmeo RT,RA (OE=1 Rc=0)
 207 * addmeo.  RT,RA (OE=1 Rc=1)
 208
 209 Pseudo-code:
 210
 211     RT <- (RA) + CA - 1
 212
 213 Special Registers Altered:
 214
 215     CA CA32
 216     CR0                     (if Rc=1)
 217     SO OV OV32             (if OE=1)
 218
 219 # Subtract From Minus One Extended
 220
 221 XO-Form
 222
 223 * subfme RT,RA (OE=0 Rc=0)
 224 * subfme.  RT,RA (OE=0 Rc=1)
 225 * subfmeo RT,RA (OE=1 Rc=0)
 226 * subfmeo.  RT,RA (OE=1 Rc=1)
 227
 228 Pseudo-code:
 229
 230     RT <- ¬(RA) + CA - 1
 231
 232 Special Registers Altered:
 233
 234     CA CA32
 235     CR0                     (if Rc=1)
 236     SO OV OV32             (if OE=1)
 237
 238 # Add Extended using alternate carry bit
 239
 240 Z23-Form
 241
 242 * addex RT,RA,RB,CY
 243
 244 Pseudo-code:
 245
 246     if CY=0 then RT <- (RA) + (RB) + OV
 247
 248 Special Registers Altered:
 249
 250     OV OV32                (if CY=0 )
 251
 252 # Subtract From Zero Extended
 253
 254 XO-Form
 255
 256 * subfze RT,RA (OE=0 Rc=0)
 257 * subfze.  RT,RA (OE=0 Rc=1)
 258 * subfzeo RT,RA (OE=1 Rc=0)
 259 * subfzeo.  RT,RA (OE=1 Rc=1)
 260
 261 Pseudo-code:
 262
 263     RT <- ¬(RA) + CA
 264
 265 Special Registers Altered:
 266
 267     CA CA32
 268     CR0                     (if Rc=1)
 269     SO OV OV32             (if OE=1)
 270
 271 # Add to Zero Extended
 272
 273 XO-Form
 274
 275 * addze RT,RA (OE=0 Rc=0)
 276 * addze.  RT,RA (OE=0 Rc=1)
 277 * addzeo RT,RA (OE=1 Rc=0)
 278 * addzeo.  RT,RA (OE=1 Rc=1)
 279
 280 Pseudo-code:
 281
 282     RT <- (RA) + CA
 283
 284 Special Registers Altered:
 285
 286     CA CA32
 287     CR0                     (if Rc=1)
 288     SO OV OV32             (if OE=1)
 289
 290 # Negate
 291
 292 XO-Form
 293
 294 * neg RT,RA (OE=0 Rc=0)
 295 * neg.  RT,RA (OE=0 Rc=1)
 296 * nego RT,RA (OE=1 Rc=0)
 297 * nego.  RT,RA (OE=1 Rc=1)
 298
 299 Pseudo-code:
 300
 301     RT <- ¬(RA) + 1
 302
 303 Special Registers Altered:
 304
 305     CR0                     (if Rc=1)
 306     SO OV OV32             (if OE=1)
 307
 308 # Multiply Low Immediate
 309
 310 D-Form
 311
 312 * mulli RT,RA,SI
 313
 314 Pseudo-code:
 315
 316     prod[0:127] <- (RA) * EXTS(SI)
 317     RT <- prod[64:127]
 318
 319 Special Registers Altered:
 320
 321     None
 322
 323 # Multiply High Word
 324
 325 XO-Form
 326
 327 * mulhw RT,RA,RB (Rc=0)
 328 * mulhw.  RT,RA,RB (Rc=1)
 329
 330 Pseudo-code:
 331
 332     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 333     RT[32:63] <- prod[0:31]
 334     RT[0:31] <- undefined[0:31]
 335
 336 Special Registers Altered:
 337
 338     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 339
 340 # Multiply Low Word
 341
 342 XO-Form
 343
 344 * mullw RT,RA,RB (OE=0 Rc=0)
 345 * mullw.  RT,RA,RB (OE=0 Rc=1)
 346 * mullwo RT,RA,RB (OE=1 Rc=0)
 347 * mullwo.  RT,RA,RB (OE=1 Rc=1)
 348
 349 Pseudo-code:
 350
 351     prod[0:63] <- (RA)[32:63] * (RB)[32:63]
 352     RT <- prod
 353
 354 Special Registers Altered:
 355
 356     CR0                     (if Rc=1)
 357     SO OV OV32             (if OE=1)
 358
 359 # Multiply High Word Unsigned
 360
 361 XO-Form
 362
 363 * mulhwu RT,RA,RB (Rc=0)
 364 * mulhwu.  RT,RA,RB (Rc=1)
 365
 366 Pseudo-code:
 367
 368     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 369     RT[32:63] <- prod[0:31]
 370     RT[0:31] <- undefined[0:31]
 371
 372 Special Registers Altered:
 373
 374     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 375
 376 # Divide Word
 377
 378 XO-Form
 379
 380 * divw RT,RA,RB (OE=0 Rc=0)
 381 * divw.  RT,RA,RB (OE=0 Rc=1)
 382 * divwo RT,RA,RB (OE=1 Rc=0)
 383 * divwo.  RT,RA,RB (OE=1 Rc=1)
 384
 385 Pseudo-code:
 386
 387     dividend[0:31] <-  (RA)[32:63]
 388     divisor[0:31] <- (RB) [32:63]
 389     if (((dividend = 0x8000_0000) &
 390          (divisor = 0xffff_ffff)) |
 391          (divisor = 0x0000_0000)) then
 392         RT[0:63] <- undefined[0:63]
 393         overflow <- 1
 394     else
 395         RT[32:63] <- dividend / divisor
 396         RT[0:31] <- undefined[0:31]
 397         overflow <- 0
 398
 399 Special Registers Altered:
 400
 401     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 402     SO OV OV32                              (if OE=1)
 403
 404 # Divide Word Unsigned
 405
 406 XO-Form
 407
 408 * divwu RT,RA,RB (OE=0 Rc=0)
 409 * divwu.  RT,RA,RB (OE=0 Rc=1)
 410 * divwuo RT,RA,RB (OE=1 Rc=0)
 411 * divwuo.  RT,RA,RB (OE=1 Rc=1)
 412
 413 Pseudo-code:
 414
 415     dividend[0:31] <- (RA)[32:63]
 416     divisor[0:31] <- (RB)[32:63]
 417     if divisor != 0 then
 418         RT[32:63] <-  dividend / divisor
 419         RT[0:31] <- undefined[0:31]
 420         overflow <- 0
 421     else
 422         RT[0:63] <- undefined[0:63]
 423         overflow <- 1
 424
 425 Special Registers Altered:
 426
 427     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 428     SO OV OV32                              (if OE=1)
 429
 430 # Divide Word Extended
 431
 432 XO-Form
 433
 434 * divwe RT,RA,RB (OE=0 Rc=0)
 435 * divwe.  RT,RA,RB (OE=0 Rc=1)
 436 * divweo RT,RA,RB (OE=1 Rc=0)
 437 * divweo.  RT,RA,RB (OE=1 Rc=1)
 438
 439 Pseudo-code:
 440
 441     dividend[0:63] <- (RA)[32:63] || [0]*32
 442     divisor[0:63] <- [0]*32 || (RB)[32:63]
 443     if (divisor = 0x0000_0000_0000_0000) then
 444         overflow <- 1
 445     else
 446         result <- dividend /  divisor
 447         if (result[32:63] = 0) then
 448             RT[32:63] <- result[0:31]
 449             RT[0:31] <- undefined[0:31]
 450             overflow <- 0
 451         else
 452             overflow <- 1
 453     if overflow = 1 then
 454         RT[0:63] <- undefined[0:63]
 455
 456 Special Registers Altered:
 457
 458     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 459     SO OV OV32                              (if OE=1)
 460
 461 # Divide Word Extended Unsigned
 462
 463 XO-Form
 464
 465 * divweu RT,RA,RB (OE=0 Rc=0)
 466 * divweu.  RT,RA,RB (OE=0 Rc=1)
 467 * divweuo RT,RA,RB (OE=1 Rc=0)
 468 * divweuo.  RT,RA,RB (OE=1 Rc=1)
 469
 470 Pseudo-code:
 471
 472     dividend[0:63] <- (RA)[32:63] || [0]*32
 473     divisor[0:63] <- [0]*32 || (RB)[32:63]
 474     if (divisor = 0x0000_0000_0000_0000) then
 475         overflow <- 1
 476     else
 477         result <- dividend /  divisor
 478         if (RA) < (RB) then
 479             RT[32:63] <- result[0:31]
 480             RT[0:31] <- undefined[0:31]
 481             overflow <- 0
 482         else
 483             overflow <- 1
 484     if overflow = 1 then
 485         RT[0:63] <- undefined[0:63]
 486
 487 Special Registers Altered:
 488
 489     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 490     SO OV OV32                              (if OE=1)
 491
 492 # Modulo Signed Word
 493
 494 X-Form
 495
 496 * modsw RT,RA,RB
 497
 498 Pseudo-code:
 499
 500     dividend[0:31] <- (RA)[32:63]
 501     divisor [0:31] <- (RB)[32:63]
 502     if (((dividend = 0x8000_0000) &
 503          (divisor = 0xffff_ffff)) |
 504          (divisor = 0x0000_0000)) then
 505         RT[0:63] <- undefined[0:63]
 506         overflow <- 1
 507     else
 508         RT[32:63] <- dividend % divisor
 509         RT[0:31] <- undefined[0:31]
 510         overflow <- 0
 511
 512 Special Registers Altered:
 513
 514     None
 515
 516 # Modulo Unsigned Word
 517
 518 X-Form
 519
 520 * moduw RT,RA,RB
 521
 522 Pseudo-code:
 523
 524     dividend[0:31] <- (RA) [32:63]
 525     divisor [0:31] <- (RB) [32:63]
 526     if divisor = 0x0000_0000 then
 527         RT[0:63] <- undefined[0:63]
 528         overflow <- 1
 529     else
 530         RT[32:63] <- dividend % divisor
 531         RT[0:31] <- undefined[0:31]
 532         overflow <- 0
 533
 534 Special Registers Altered:
 535
 536     None
 537
 538 # Deliver A Random Number
 539
 540 X-Form
 541
 542 * darn RT,L
 543
 544 Pseudo-code:
 545
 546     RT <- random(L)
 547
 548 Special Registers Altered:
 549
 550     none
 551
 552 # Multiply Low Doubleword
 553
 554 XO-Form
 555
 556 * mulld RT,RA,RB (OE=0 Rc=0)
 557 * mulld.  RT,RA,RB (OE=0 Rc=1)
 558 * mulldo RT,RA,RB (OE=1 Rc=0)
 559 * mulldo.  RT,RA,RB (OE=1 Rc=1)
 560
 561 Pseudo-code:
 562
 563     prod[0:127] <- (RA) * (RB)
 564     RT <- prod[64:127]
 565
 566 Special Registers Altered:
 567
 568     CR0                     (if Rc=1)
 569     SO OV OV32             (if OE=1)
 570
 571 # Multiply High Doubleword
 572
 573 XO-Form
 574
 575 * mulhd RT,RA,RB (Rc=0)
 576 * mulhd.  RT,RA,RB (Rc=1)
 577
 578 Pseudo-code:
 579
 580     prod[0:127] <- (RA) *  (RB)
 581     RT <- prod[0:63]
 582
 583 Special Registers Altered:
 584
 585     CR0                     (if Rc=1)
 586
 587 # Multiply High Doubleword Unsigned
 588
 589 XO-Form
 590
 591 * mulhdu RT,RA,RB (Rc=0)
 592 * mulhdu.  RT,RA,RB (Rc=1)
 593
 594 Pseudo-code:
 595
 596     prod[0:127] <- (RA) *  (RB)
 597     RT <- prod[0:63]
 598
 599 Special Registers Altered:
 600
 601     CR0                    (if Rc=1)
 602
 603 # Multiply-Add High Doubleword VA-Form
 604
 605 VA-Form
 606
 607 * maddhd RT,RA.RB,RC
 608
 609 Pseudo-code:
 610
 611     prod[0:127] <- (RA) * (RB)
 612     sum[0:127] <- prod + EXTS(RC)
 613     RT <- sum[0:63]
 614
 615 Special Registers Altered:
 616
 617     None
 618
 619 # Multiply-Add High Doubleword Unsigned
 620
 621 VA-Form
 622
 623 * maddhdu RT,RA.RB,RC
 624
 625 Pseudo-code:
 626
 627     prod[0:127] <- (RA) * (RB)
 628     sum[0:127] <- prod + EXTZ(RC)
 629     RT <- sum[0:63]
 630
 631 Special Registers Altered:
 632
 633     None
 634
 635 # Multiply-Add Low Doubleword
 636
 637 VA-Form
 638
 639 * maddld RT,RA.RB,RC
 640
 641 Pseudo-code:
 642
 643     prod[0:127] <- (RA) * (RB)
 644     sum[0:127] <- prod + EXTS(RC)
 645     RT <- sum[64:127]
 646
 647 Special Registers Altered:
 648
 649     None
 650
 651 # Divide Doubleword
 652
 653 XO-Form
 654
 655 * divd RT,RA,RB (OE=0 Rc=0)
 656 * divd.  RT,RA,RB (OE=0 Rc=1)
 657 * divdo RT,RA,RB (OE=1 Rc=0)
 658 * divdo.  RT,RA,RB (OE=1 Rc=1)
 659
 660 Pseudo-code:
 661
 662     dividend[0:63] <- (RA)
 663     divisor[0:63] <- (RB)
 664     if (((dividend = 0x8000_0000_0000_0000) &
 665          (divisor = 0xffff_ffff_ffff_ffff)) |
 666          (divisor = 0x0000_0000_0000_0000)) then
 667         RT[0:63] <- undefined[0:63]
 668         overflow <- 1
 669     else
 670         RT <- dividend / divisor
 671         overflow <- 0
 672
 673 Special Registers Altered:
 674
 675     CR0                     (if Rc=1)
 676     SO OV OV32             (if OE=1)
 677
 678 # Divide Doubleword Unsigned
 679
 680 XO-Form
 681
 682 * divdu RT,RA,RB (OE=0 Rc=0)
 683 * divdu.  RT,RA,RB (OE=0 Rc=1)
 684 * divduo RT,RA,RB (OE=1 Rc=0)
 685 * divduo.  RT,RA,RB (OE=1 Rc=1)
 686
 687 Pseudo-code:
 688
 689     dividend[0:63] <- (RA)
 690     divisor[0:63] <- (RB)
 691     if (divisor = 0x0000_0000_0000_0000) then
 692         RT[0:63] <- undefined[0:63]
 693         overflow <- 1
 694     else
 695         RT <- dividend / divisor
 696         overflow <- 0
 697
 698 Special Registers Altered:
 699
 700     CR0                     (if Rc=1)
 701     SO OV OV32             (if OE=1)
 702
 703 # Divide Doubleword Extended
 704
 705 XO-Form
 706
 707 * divde RT,RA,RB (OE=0 Rc=0)
 708 * divde.  RT,RA,RB (OE=0 Rc=1)
 709 * divdeo RT,RA,RB (OE=1 Rc=0)
 710 * divdeo.  RT,RA,RB (OE=1 Rc=1)
 711
 712 Pseudo-code:
 713
 714     dividend[0:127] <-  (RA) || [0]*64
 715     divisor[0:127] <- [0*64] || (RB)
 716     if divisor = [0]*128 then
 717         overflow <- 1
 718     else
 719         result <- dividend /  divisor
 720         if result[64:127] = 0x0000_0000_0000_0000 then
 721             RT <- result[63:127]
 722             overflow <- 0
 723         else
 724             overflow <- 1
 725     if overflow = 1 then
 726         RT[0:63] <- undefined[0:63]
 727
 728 Special Registers Altered:
 729
 730     CR0                     (if Rc=1)
 731     SO OV OV32             (if OE=1)
 732
 733 # Divide Doubleword Extended Unsigned
 734
 735 XO-Form
 736
 737 * divdeu RT,RA,RB (OE=0 Rc=0)
 738 * divdeu.  RT,RA,RB (OE=0 Rc=1)
 739 * divdeuo RT,RA,RB (OE=1 Rc=0)
 740 * divdeuo.  RT,RA,RB (OE=1 Rc=1)
 741
 742 Pseudo-code:
 743
 744     dividend[0:127] <-  (RA) || [0]*64
 745     divisor[0:127] <- [0*64] || (RB)
 746     if divisor = [0]*128 then
 747         overflow <- 1
 748     else
 749         result <- dividend /  divisor
 750         if (RA) < (RB) then
 751             RT <- result[63:127]
 752             overflow <- 0
 753         else
 754             overflow <- 1
 755     if overflow = 1 then
 756         RT[0:63] <- undefined[0:63]
 757
 758 Special Registers Altered:
 759
 760     CR0                     (if Rc=1)
 761     SO OV OV32             (if OE=1)
 762
 763 # Modulo Signed Doubleword
 764
 765 X-Form
 766
 767 * modsd RT,RA,RB
 768
 769 Pseudo-code:
 770
 771     dividend <- (RA)
 772     divisor  <- (RB)
 773     if (((dividend = 0x8000_0000_0000_0000) &
 774          (divisor = 0xffff_ffff_ffff_ffff)) |
 775          (divisor = 0x0000_0000_0000_0000)) then
 776         RT[0:63] <- undefined[0:63]
 777         overflow <- 1
 778     else
 779         RT       <- dividend % divisor
 780         overflow <- 0
 781
 782 Special Registers Altered:
 783
 784     None
 785
 786 # Modulo Unsigned Doubleword
 787
 788 X-Form
 789
 790 * modud RT,RA,RB
 791
 792 Pseudo-code:
 793
 794     dividend <- (RA)
 795     divisor  <- (RB)
 796     if (divisor = 0x0000_0000_0000_0000) then
 797         RT[0:63] <- undefined[0:63]
 798         overflow <- 1
 799     else
 800         RT       <- dividend % divisor
 801         overflow <- 0
 802
 803 Special Registers Altered:
 804
 805     None
 806