openpower/isa/fixedarith.mdwn

   1 # Add Immediate
   2
   3 D-Form
   4
   5 * addi RT,RA,SI
   6
   7     if RA = 0 then RT <- EXTS(SI)
   8     else           RT <- (RA) + EXTS(SI)
   9
  10 Special Registers Altered:
  11
  12     None
  13
  14 # Add Immediate Shifted
  15
  16 D-Form
  17
  18 * addis RT,RA,SI
  19
  20     if RA = 0 then RT <- EXTS(SI || [0]*16)
  21     else           RT <- (RA) + EXTS(SI || [0]*16)
  22
  23 Special Registers Altered:
  24
  25     None
  26
  27 # Add PC Immediate Shifted
  28
  29 DX-Form
  30
  31 * addpcis RT,D
  32
  33     D <- d0||d1||d2
  34     RT <- NIA + EXTS(D || [0]*16)
  35
  36 Special Registers Altered:
  37
  38     None
  39
  40 # Add
  41
  42 XO-Form
  43
  44 * add RT,RA,RB (OE=0 Rc=0)
  45 * add.  RT,RA,RB (OE=0 Rc=1)
  46 * addo RT,RA,RB (OE=1 Rc=0)
  47 * addo.  RT,RA,RB (OE=1 Rc=1)
  48
  49     RT <- (RA) + (RB)
  50
  51 Special Registers Altered:
  52
  53     CR0                     (if Rc=1)
  54     SO OV OV32             (if OE=1)
  55
  56 # Subtract From
  57
  58 XO-Form
  59
  60 * subf RT,RA,RB (OE=0 Rc=0)
  61 * subf.  RT,RA,RB (OE=0 Rc=1)
  62 * subfo RT,RA,RB (OE=1 Rc=0)
  63 * subfo.  RT,RA,RB (OE=1 Rc=1)
  64
  65     RT <- ¬(RA) + (RB) + 1
  66
  67 Special Registers Altered:
  68
  69     CR0                     (if Rc=1)
  70     SO OV OV32             (if OE=1)
  71
  72 # Add Immediate Carrying
  73
  74 D-Form
  75
  76 * addic RT,RA,SI
  77
  78     RT <- (RA) + EXTS(SI)
  79
  80 Special Registers Altered:
  81
  82     CA CA32
  83
  84 # Add Immediate Carrying and Record
  85
  86 D-Form
  87
  88 * addic. RT,RA,SI
  89
  90     RT <- (RA) + EXTS(SI)
  91
  92 Special Registers Altered:
  93
  94     CR0 CA CA32
  95
  96 # Subtract From Immediate Carrying
  97
  98 D-Form
  99
 100 * subfic RT,RA,SI
 101
 102     RT <- ¬(RA) + EXTS(SI) + 1
 103
 104 Special Registers Altered:
 105
 106     CA CA32
 107
 108 # Add Carrying
 109
 110 XO-Form
 111
 112 * addc RT,RA,RB (OE=0 Rc=0)
 113 * addc.  RT,RA,RB (OE=0 Rc=1)
 114 * addco RT,RA,RB (OE=1 Rc=0)
 115 * addco.  RT,RA,RB (OE=1 Rc=1)
 116
 117     RT <- (RA) + (RB)
 118
 119 Special Registers Altered:
 120
 121     CA CA32
 122     CR0                     (if Rc=1)
 123     SO OV OV32             (if OE=1)
 124
 125 # Subtract From Carrying
 126
 127 XO-Form
 128
 129 * subfc RT,RA,RB (OE=0 Rc=0)
 130 * subfc.  RT,RA,RB (OE=0 Rc=1)
 131 * subfco RT,RA,RB (OE=1 Rc=0)
 132 * subfco.  RT,RA,RB (OE=1 Rc=1)
 133
 134     RT <- ¬(RA) + (RB) + 1
 135
 136 Special Registers Altered:
 137
 138     CA CA32
 139     CR0                     (if Rc=1)
 140     SO OV OV32             (if OE=1)
 141
 142 # Add Extended
 143
 144 XO-Form
 145
 146 * adde RT,RA,RB (OE=0 Rc=0)
 147 * adde.  RT,RA,RB (OE=0 Rc=1)
 148 * addeo RT,RA,RB (OE=1 Rc=0)
 149 * addeo.  RT,RA,RB (OE=1 Rc=1)
 150
 151     RT <- (RA) + (RB) + CA
 152
 153 Special Registers Altered:
 154
 155     CA CA32
 156     CR0                     (if Rc=1)
 157     SO OV OV32             (if OE=1)
 158
 159 # Subtract From Extended
 160
 161 XO-Form
 162
 163 * subfe RT,RA,RB (OE=0 Rc=0)
 164 * subfe.  RT,RA,RB (OE=0 Rc=1)
 165 * subfeo RT,RA,RB (OE=1 Rc=0)
 166 * subfeo.  RT,RA,RB (OE=1 Rc=1)
 167
 168     RT <- ¬(RA) + (RB) + CA
 169
 170 Special Registers Altered:
 171
 172     CA CA32
 173     CR0                     (if Rc=1)
 174     SO OV OV32             (if OE=1)
 175
 176 # Add to Minus One Extended
 177
 178 XO-Form
 179
 180 * addme RT,RA (OE=0 Rc=0)
 181 * addme.  RT,RA (OE=0 Rc=1)
 182 * addmeo RT,RA (OE=1 Rc=0)
 183 * addmeo.  RT,RA (OE=1 Rc=1)
 184
 185     RT <- (RA) + CA - 1
 186
 187 Special Registers Altered:
 188
 189     CA CA32
 190     CR0                     (if Rc=1)
 191     SO OV OV32             (if OE=1)
 192
 193 # Subtract From Minus One Extended
 194
 195 XO-Form
 196
 197 * subfme RT,RA (OE=0 Rc=0)
 198 * subfme.  RT,RA (OE=0 Rc=1)
 199 * subfmeo RT,RA (OE=1 Rc=0)
 200 * subfmeo.  RT,RA (OE=1 Rc=1)
 201
 202     RT <- ¬(RA) + CA - 1
 203
 204 Special Registers Altered:
 205
 206     CA CA32
 207     CR0                     (if Rc=1)
 208     SO OV OV32             (if OE=1)
 209
 210 # Add Extended using alternate carry bit
 211
 212 Z23-Form
 213
 214 * addex RT,RA,RB,CY
 215
 216     if CY=0 then RT <- (RA) + (RB) + OV
 217
 218 Special Registers Altered:
 219
 220     OV OV32                (if CY=0 )
 221
 222 # Subtract From Zero Extended
 223
 224 XO-Form
 225
 226 * subfze RT,RA (OE=0 Rc=0)
 227 * subfze.  RT,RA (OE=0 Rc=1)
 228 * subfzeo RT,RA (OE=1 Rc=0)
 229 * subfzeo.  RT,RA (OE=1 Rc=1)
 230
 231     RT <- ¬(RA) + CA
 232
 233 Special Registers Altered:
 234
 235     CA CA32
 236     CR0                     (if Rc=1)
 237     SO OV OV32             (if OE=1)
 238
 239 # Add to Zero Extended
 240
 241 XO-Form
 242
 243 * addze RT,RA (OE=0 Rc=0)
 244 * addze.  RT,RA (OE=0 Rc=1)
 245 * addzeo RT,RA (OE=1 Rc=0)
 246 * addzeo.  RT,RA (OE=1 Rc=1)
 247
 248     RT <- (RA) + CA
 249
 250 Special Registers Altered:
 251
 252     CA CA32
 253     CR0                     (if Rc=1)
 254     SO OV OV32             (if OE=1)
 255
 256 # Negate
 257
 258 XO-Form
 259
 260 * neg RT,RA (OE=0 Rc=0)
 261 * neg.  RT,RA (OE=0 Rc=1)
 262 * nego RT,RA (OE=1 Rc=0)
 263 * nego.  RT,RA (OE=1 Rc=1)
 264
 265     RT <- ¬(RA) + 1
 266
 267 Special Registers Altered:
 268
 269     CR0                     (if Rc=1)
 270     SO OV OV32             (if OE=1)
 271
 272 # Multiply Low Immediate
 273
 274 D-Form
 275
 276 * mulli RT,RA,SI
 277
 278     prod[0:127] <- (RA) * EXTS(SI)
 279     RT <- prod[64:127]
 280
 281 Special Registers Altered:
 282
 283     None
 284
 285 # Multiply High Word
 286
 287 XO-Form
 288
 289 * mulhw RT,RA,RB (Rc=0)
 290 * mulhw.  RT,RA,RB (Rc=1)
 291
 292     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 293     RT[32:63] <- prod[0:31]
 294     RT[0:31] <- undefined
 295
 296 Special Registers Altered:
 297
 298     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 299
 300 # Multiply Low Word
 301
 302 XO-Form
 303
 304 * mullw RT,RA,RB (OE=0 Rc=0)
 305 * mullw.  RT,RA,RB (OE=0 Rc=1)
 306 * mullwo RT,RA,RB (OE=1 Rc=0)
 307 * mullwo.  RT,RA,RB (OE=1 Rc=1)
 308
 309     RT <- (RA)[32:63] * (RB)[32:63]
 310
 311 Special Registers Altered:
 312
 313     CR0                     (if Rc=1)
 314     SO OV OV32             (if OE=1)
 315
 316 # Multiply High Word Unsigned
 317
 318 XO-Form
 319
 320 * mulhwu RT,RA,RB (Rc=0)
 321 * mulhwu.  RT,RA,RB (Rc=1)
 322
 323     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 324     RT[32:63] <- prod[0:31]
 325     RT[0:31] <- undefined
 326
 327 Special Registers Altered:
 328
 329     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 330
 331 # Divide Word
 332
 333 XO-Form
 334
 335 * divw RT,RA,RB (OE=0 Rc=0)
 336 * divw.  RT,RA,RB (OE=0 Rc=1)
 337 * divwo RT,RA,RB (OE=1 Rc=0)
 338 * divwo.  RT,RA,RB (OE=1 Rc=1)
 339
 340     dividend[0:31] <-  (RA)[32:63]
 341     divisor[0:31] <- (RB) [32:63]
 342     RT[32:63] <- dividend / divisor
 343     RT[0:31] <- undefined
 344
 345 Special Registers Altered:
 346
 347     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 348     SO OV OV32                              (if OE=1)
 349
 350 # Divide Word Unsigned
 351
 352 XO-Form
 353
 354 * divwu RT,RA,RB (OE=0 Rc=0)
 355 * divwu.  RT,RA,RB (OE=0 Rc=1)
 356 * divwuo RT,RA,RB (OE=1 Rc=0)
 357 * divwuo.  RT,RA,RB (OE=1 Rc=1)
 358
 359     dividend[0:31] <- (RA)[32:63]
 360     divisor[0:31] <- (RB)[32:63]
 361     RT[32:63] <-  dividend / divisor
 362     RT[0:31] <- undefined
 363
 364 Special Registers Altered:
 365
 366     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 367     SO OV OV32                              (if OE=1)
 368
 369 # Divide Word Extended
 370
 371 XO-Form
 372
 373 * divwe RT,RA,RB (OE=0 Rc=0)
 374 * divwe.  RT,RA,RB (OE=0 Rc=1)
 375 * divweo RT,RA,RB (OE=1 Rc=0)
 376 * divweo.  RT,RA,RB (OE=1 Rc=1)
 377
 378     dividend[0:63] <- (RA)[32:63] || [0]*32
 379     divisor[0:31] <- (RB)[32:63]
 380     RT[32:63] <- dividend /  divisor
 381     RT[0:31] <- undefined
 382
 383 Special Registers Altered:
 384
 385     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 386     SO OV OV32                              (if OE=1)
 387
 388 # Divide Word Extended Unsigned
 389
 390 XO-Form
 391
 392 * divweu RT,RA,RB (OE=0 Rc=0)
 393 * divweu.  RT,RA,RB (OE=0 Rc=1)
 394 * divweuo RT,RA,RB (OE=1 Rc=0)
 395 * divweuo.  RT,RA,RB (OE=1 Rc=1)
 396
 397     dividend[0:63] <- (RA)[32:63] || [0]*32
 398     divisor[0:31] <- (RB)[32:63]
 399     RT[32:63] <- dividend / divisor
 400     RT[0:31] <- undefined
 401
 402 Special Registers Altered:
 403
 404     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 405     SO OV OV32                              (if OE=1)
 406
 407 # Modulo Signed Word
 408
 409 X-Form
 410
 411 * modsw RT,RA,RB
 412
 413     dividend[0:31] <- (RA)[32:63]
 414     divisor [0:31] <- (RB)[32:63]-
 415     RT[32:63] <- dividend % divisor
 416     RT[0:31 ] <- undefined
 417
 418 Special Registers Altered:
 419
 420     None
 421
 422 # Modulo Unsigned Word
 423
 424 X-Form
 425
 426 * moduw RT,RA,RB
 427
 428     dividend[0:31] <- (RA) [32:63]
 429     divisor [0:31] <- (RB) [32:63]
 430     RT[32:63] <- dividend % divisor
 431     RT[0:31 ] <- undefined
 432
 433 Special Registers Altered:
 434
 435     None
 436
 437 # Deliver A Random Number
 438
 439 X-Form
 440
 441 * darn RT,L
 442
 443     RT <- random(L)
 444
 445 Special Registers Altered:
 446
 447     none
 448
 449 # Multiply Low Doubleword
 450
 451 XO-Form
 452
 453 * mulld RT,RA,RB (OE=0 Rc=0)
 454 * mulld.  RT,RA,RB (OE=0 Rc=1)
 455 * mulldo RT,RA,RB (OE=1 Rc=0)
 456 * mulldo.  RT,RA,RB (OE=1 Rc=1)
 457
 458     prod[0:127] <- (RA) * (RB)
 459     RT <- prod[64:127]
 460
 461 Special Registers Altered:
 462
 463     CR0                     (if Rc=1)
 464     SO OV OV32             (if OE=1)
 465
 466 # Multiply High Doubleword
 467
 468 XO-Form
 469
 470 * mulhd RT,RA,RB (Rc=0)
 471 * mulhd.  RT,RA,RB (Rc=1)
 472
 473     prod[0:127] <- (RA) *  (RB)
 474     RT <- prod[0:63]
 475
 476 Special Registers Altered:
 477
 478     CR0                     (if Rc=1)
 479
 480 # Multiply High Doubleword Unsigned
 481
 482 XO-Form
 483
 484 * mulhdu RT,RA,RB (Rc=0)
 485 * mulhdu.  RT,RA,RB (Rc=1)
 486
 487     prod[0:127] <- (RA) *  (RB)
 488     RT <- prod[0:63]
 489
 490 Special Registers Altered:
 491
 492     CR0                    (if Rc=1)
 493
 494 # Multiply-Add High Doubleword VA-Form
 495
 496 VA-Form
 497
 498 * maddhd RT,RA.RB,RC
 499
 500     prod[0:127] <- (RA) * (RB)
 501     sum[0:127] <- prod + EXTS(RC)
 502     RT <- sum[0:63]
 503
 504 Special Registers Altered:
 505
 506     None
 507
 508 # Multiply-Add High Doubleword Unsigned
 509
 510 VA-Form
 511
 512 * maddhdu RT,RA.RB,RC
 513
 514     prod[0:127] <- (RA) * (RB)
 515     sum[0:127] <- prod + EXTZ(RC)
 516     RT <- sum[0:63]
 517
 518 Special Registers Altered:
 519
 520     None
 521
 522 # Multiply-Add Low Doubleword
 523
 524 VA-Form
 525
 526 * maddld RT,RA.RB,RC
 527
 528     prod[0:127] <- (RA) * (RB)
 529     sum[0:127] <- prod + EXTS(RC)
 530     RT <- sum[64:127]
 531
 532 Special Registers Altered:
 533
 534     None
 535
 536 # Divide Doubleword
 537
 538 XO-Form
 539
 540 * divd RT,RA,RB (OE=0 Rc=0)
 541 * divd.  RT,RA,RB (OE=0 Rc=1)
 542 * divdo RT,RA,RB (OE=1 Rc=0)
 543 * divdo.  RT,RA,RB (OE=1 Rc=1)
 544
 545     dividend[0:63] <- (RA)
 546     divisor[0:63] <- (RB)
 547     RT <- dividend / divisor
 548
 549 Special Registers Altered:
 550
 551     CR0                     (if Rc=1)
 552     SO OV OV32             (if OE=1)
 553
 554 # Divide Doubleword Unsigned
 555
 556 XO-Form
 557
 558 * divdu RT,RA,RB (OE=0 Rc=0)
 559 * divdu.  RT,RA,RB (OE=0 Rc=1)
 560 * divduo RT,RA,RB (OE=1 Rc=0)
 561 * divduo.  RT,RA,RB (OE=1 Rc=1)
 562
 563     dividend[0:63] <- (RA)
 564     divisor[0:63] <- (RB)
 565     RT <- dividend / divisor
 566
 567 Special Registers Altered:
 568
 569     CR0                     (if Rc=1)
 570     SO OV OV32             (if OE=1)
 571
 572 # Divide Doubleword Extended
 573
 574 XO-Form
 575
 576 * divde RT,RA,RB (OE=0 Rc=0)
 577 * divde.  RT,RA,RB (OE=0 Rc=1)
 578 * divdeo RT,RA,RB (OE=1 Rc=0)
 579 * divdeo.  RT,RA,RB (OE=1 Rc=1)
 580
 581     dividend[0:127] <-  (RA) || [0]*64
 582     divisor[0:63] <- (RB)
 583     RT <- dividend / divisor
 584
 585 Special Registers Altered:
 586
 587     CR0                     (if Rc=1)
 588     SO OV OV32             (if OE=1)
 589
 590 # Divide Doubleword Extended Unsigned
 591
 592 XO-Form
 593
 594 * divdeu RT,RA,RB (OE=0 Rc=0)
 595 * divdeu.  RT,RA,RB (OE=0 Rc=1)
 596 * divdeuo RT,RA,RB (OE=1 Rc=0)
 597 * divdeuo.  RT,RA,RB (OE=1 Rc=1)
 598
 599     dividend[0:127] <-  (RA) || [0]*64
 600     divisor[0:63] <- (RB)
 601     RT <- dividend / divisor
 602
 603 Special Registers Altered:
 604
 605     CR0                     (if Rc=1)
 606     SO OV OV32             (if OE=1)
 607
 608 # Modulo Signed Doubleword
 609
 610 X-Form
 611
 612 * modsd RT,RA,RB
 613
 614     dividend <- (RA)
 615     divisor  <- (RB)
 616     RT       <- dividend % divisor
 617
 618 Special Registers Altered:
 619
 620     None
 621
 622 # Modulo Unsigned Doubleword
 623
 624 X-Form
 625
 626 * modud RT,RA,RB
 627
 628     dividend <- (RA)
 629     divisor  <- (RB)
 630     RT       <- dividend % divisor
 631
 632 Special Registers Altered:
 633
 634     None
 635