openpower/isa/fixedarith.mdwn

   1 # Add Immediate
   2
   3 D-Form
   4
   5 * addi RT,RA,SI
   6
   7 Pseudo-code:
   8
   9     if RA = 0 then RT <- EXTS(SI)
  10     else           RT <- (RA) + EXTS(SI)
  11
  12 Special Registers Altered:
  13
  14     None
  15
  16 # Add Immediate Shifted
  17
  18 D-Form
  19
  20 * addis RT,RA,SI
  21
  22 Pseudo-code:
  23
  24     if RA = 0 then RT <- EXTS(SI || [0]*16)
  25     else           RT <- (RA) + EXTS(SI || [0]*16)
  26
  27 Special Registers Altered:
  28
  29     None
  30
  31 # Add PC Immediate Shifted
  32
  33 DX-Form
  34
  35 * addpcis RT,D
  36
  37 Pseudo-code:
  38
  39     D <- d0||d1||d2
  40     RT <- NIA + EXTS(D || [0]*16)
  41
  42 Special Registers Altered:
  43
  44     None
  45
  46 # Add
  47
  48 XO-Form
  49
  50 * add RT,RA,RB (OE=0 Rc=0)
  51 * add.  RT,RA,RB (OE=0 Rc=1)
  52 * addo RT,RA,RB (OE=1 Rc=0)
  53 * addo.  RT,RA,RB (OE=1 Rc=1)
  54
  55 Pseudo-code:
  56
  57     RT <- (RA) + (RB)
  58
  59 Special Registers Altered:
  60
  61     CR0                     (if Rc=1)
  62     SO OV OV32             (if OE=1)
  63
  64 # Subtract From
  65
  66 XO-Form
  67
  68 * subf RT,RA,RB (OE=0 Rc=0)
  69 * subf.  RT,RA,RB (OE=0 Rc=1)
  70 * subfo RT,RA,RB (OE=1 Rc=0)
  71 * subfo.  RT,RA,RB (OE=1 Rc=1)
  72
  73 Pseudo-code:
  74
  75     RT <- ¬(RA) + (RB) + 1
  76
  77 Special Registers Altered:
  78
  79     CR0                     (if Rc=1)
  80     SO OV OV32             (if OE=1)
  81
  82 # Add Immediate Carrying
  83
  84 D-Form
  85
  86 * addic RT,RA,SI
  87
  88 Pseudo-code:
  89
  90     RT <- (RA) + EXTS(SI)
  91
  92 Special Registers Altered:
  93
  94     CA CA32
  95
  96 # Add Immediate Carrying and Record
  97
  98 D-Form
  99
 100 * addic. RT,RA,SI
 101
 102 Pseudo-code:
 103
 104     RT <- (RA) + EXTS(SI)
 105
 106 Special Registers Altered:
 107
 108     CR0 CA CA32
 109
 110 # Subtract From Immediate Carrying
 111
 112 D-Form
 113
 114 * subfic RT,RA,SI
 115
 116 Pseudo-code:
 117
 118     RT <- ¬(RA) + EXTS(SI) + 1
 119
 120 Special Registers Altered:
 121
 122     CA CA32
 123
 124 # Add Carrying
 125
 126 XO-Form
 127
 128 * addc RT,RA,RB (OE=0 Rc=0)
 129 * addc.  RT,RA,RB (OE=0 Rc=1)
 130 * addco RT,RA,RB (OE=1 Rc=0)
 131 * addco.  RT,RA,RB (OE=1 Rc=1)
 132
 133 Pseudo-code:
 134
 135     RT <- (RA) + (RB)
 136
 137 Special Registers Altered:
 138
 139     CA CA32
 140     CR0                     (if Rc=1)
 141     SO OV OV32             (if OE=1)
 142
 143 # Subtract From Carrying
 144
 145 XO-Form
 146
 147 * subfc RT,RA,RB (OE=0 Rc=0)
 148 * subfc.  RT,RA,RB (OE=0 Rc=1)
 149 * subfco RT,RA,RB (OE=1 Rc=0)
 150 * subfco.  RT,RA,RB (OE=1 Rc=1)
 151
 152 Pseudo-code:
 153
 154     RT <- ¬(RA) + (RB) + 1
 155
 156 Special Registers Altered:
 157
 158     CA CA32
 159     CR0                     (if Rc=1)
 160     SO OV OV32             (if OE=1)
 161
 162 # Add Extended
 163
 164 XO-Form
 165
 166 * adde RT,RA,RB (OE=0 Rc=0)
 167 * adde.  RT,RA,RB (OE=0 Rc=1)
 168 * addeo RT,RA,RB (OE=1 Rc=0)
 169 * addeo.  RT,RA,RB (OE=1 Rc=1)
 170
 171 Pseudo-code:
 172
 173     RT <- (RA) + (RB) + CA
 174
 175 Special Registers Altered:
 176
 177     CA CA32
 178     CR0                     (if Rc=1)
 179     SO OV OV32             (if OE=1)
 180
 181 # Subtract From Extended
 182
 183 XO-Form
 184
 185 * subfe RT,RA,RB (OE=0 Rc=0)
 186 * subfe.  RT,RA,RB (OE=0 Rc=1)
 187 * subfeo RT,RA,RB (OE=1 Rc=0)
 188 * subfeo.  RT,RA,RB (OE=1 Rc=1)
 189
 190 Pseudo-code:
 191
 192     RT <- ¬(RA) + (RB) + CA
 193
 194 Special Registers Altered:
 195
 196     CA CA32
 197     CR0                     (if Rc=1)
 198     SO OV OV32             (if OE=1)
 199
 200 # Add to Minus One Extended
 201
 202 XO-Form
 203
 204 * addme RT,RA (OE=0 Rc=0)
 205 * addme.  RT,RA (OE=0 Rc=1)
 206 * addmeo RT,RA (OE=1 Rc=0)
 207 * addmeo.  RT,RA (OE=1 Rc=1)
 208
 209 Pseudo-code:
 210
 211     RT <- (RA) + CA - 1
 212
 213 Special Registers Altered:
 214
 215     CA CA32
 216     CR0                     (if Rc=1)
 217     SO OV OV32             (if OE=1)
 218
 219 # Subtract From Minus One Extended
 220
 221 XO-Form
 222
 223 * subfme RT,RA (OE=0 Rc=0)
 224 * subfme.  RT,RA (OE=0 Rc=1)
 225 * subfmeo RT,RA (OE=1 Rc=0)
 226 * subfmeo.  RT,RA (OE=1 Rc=1)
 227
 228 Pseudo-code:
 229
 230     RT <- ¬(RA) + CA - 1
 231
 232 Special Registers Altered:
 233
 234     CA CA32
 235     CR0                     (if Rc=1)
 236     SO OV OV32             (if OE=1)
 237
 238 # Add Extended using alternate carry bit
 239
 240 Z23-Form
 241
 242 * addex RT,RA,RB,CY
 243
 244 Pseudo-code:
 245
 246     if CY=0 then RT <- (RA) + (RB) + OV
 247
 248 Special Registers Altered:
 249
 250     OV OV32                (if CY=0 )
 251
 252 # Subtract From Zero Extended
 253
 254 XO-Form
 255
 256 * subfze RT,RA (OE=0 Rc=0)
 257 * subfze.  RT,RA (OE=0 Rc=1)
 258 * subfzeo RT,RA (OE=1 Rc=0)
 259 * subfzeo.  RT,RA (OE=1 Rc=1)
 260
 261 Pseudo-code:
 262
 263     RT <- ¬(RA) + CA
 264
 265 Special Registers Altered:
 266
 267     CA CA32
 268     CR0                     (if Rc=1)
 269     SO OV OV32             (if OE=1)
 270
 271 # Add to Zero Extended
 272
 273 XO-Form
 274
 275 * addze RT,RA (OE=0 Rc=0)
 276 * addze.  RT,RA (OE=0 Rc=1)
 277 * addzeo RT,RA (OE=1 Rc=0)
 278 * addzeo.  RT,RA (OE=1 Rc=1)
 279
 280 Pseudo-code:
 281
 282     RT <- (RA) + CA
 283
 284 Special Registers Altered:
 285
 286     CA CA32
 287     CR0                     (if Rc=1)
 288     SO OV OV32             (if OE=1)
 289
 290 # Negate
 291
 292 XO-Form
 293
 294 * neg RT,RA (OE=0 Rc=0)
 295 * neg.  RT,RA (OE=0 Rc=1)
 296 * nego RT,RA (OE=1 Rc=0)
 297 * nego.  RT,RA (OE=1 Rc=1)
 298
 299 Pseudo-code:
 300
 301     RT <- ¬(RA) + 1
 302
 303 Special Registers Altered:
 304
 305     CR0                     (if Rc=1)
 306     SO OV OV32             (if OE=1)
 307
 308 # Multiply Low Immediate
 309
 310 D-Form
 311
 312 * mulli RT,RA,SI
 313
 314 Pseudo-code:
 315
 316     prod[0:127] <- MULS((RA), EXTS(SI))
 317     RT <- prod[64:127]
 318
 319 Special Registers Altered:
 320
 321     None
 322
 323 # Multiply High Word
 324
 325 XO-Form
 326
 327 * mulhw RT,RA,RB (Rc=0)
 328 * mulhw.  RT,RA,RB (Rc=1)
 329
 330 Pseudo-code:
 331
 332     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
 333     RT[32:63] <- prod[0:31]
 334     RT[0:31] <- prod[0:31]
 335
 336 Special Registers Altered:
 337
 338     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 339
 340 # Multiply Low Word
 341
 342 XO-Form
 343
 344 * mullw RT,RA,RB (OE=0 Rc=0)
 345 * mullw.  RT,RA,RB (OE=0 Rc=1)
 346 * mullwo RT,RA,RB (OE=1 Rc=0)
 347 * mullwo.  RT,RA,RB (OE=1 Rc=1)
 348
 349 Pseudo-code:
 350
 351     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
 352     RT <- prod
 353     overflow <- ((prod[32:64] != 0x0000_0000) &
 354                  (prod[32:64] != 0xffff_ffff))
 355
 356 Special Registers Altered:
 357
 358     CR0                     (if Rc=1)
 359     SO OV OV32             (if OE=1)
 360
 361 # Multiply High Word Unsigned
 362
 363 XO-Form
 364
 365 * mulhwu RT,RA,RB (Rc=0)
 366 * mulhwu.  RT,RA,RB (Rc=1)
 367
 368 Pseudo-code:
 369
 370     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 371     RT[32:63] <- prod[0:31]
 372     RT[0:31] <- prod[0:31]
 373
 374 Special Registers Altered:
 375
 376     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 377
 378 # Divide Word
 379
 380 XO-Form
 381
 382 * divw RT,RA,RB (OE=0 Rc=0)
 383 * divw.  RT,RA,RB (OE=0 Rc=1)
 384 * divwo RT,RA,RB (OE=1 Rc=0)
 385 * divwo.  RT,RA,RB (OE=1 Rc=1)
 386
 387 Pseudo-code:
 388
 389     dividend[0:31] <-  (RA)[32:63]
 390     divisor[0:31] <- (RB) [32:63]
 391     if (((dividend = 0x8000_0000) &
 392          (divisor = 0xffff_ffff)) |
 393          (divisor = 0x0000_0000)) then
 394         RT[0:63] <- undefined[0:63]
 395         overflow <- 1
 396     else
 397         RT[32:63] <- DIVS(dividend, divisor)
 398         RT[0:31] <- undefined[0:31]
 399         overflow <- 0
 400
 401 Special Registers Altered:
 402
 403     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 404     SO OV OV32                              (if OE=1)
 405
 406 # Divide Word Unsigned
 407
 408 XO-Form
 409
 410 * divwu RT,RA,RB (OE=0 Rc=0)
 411 * divwu.  RT,RA,RB (OE=0 Rc=1)
 412 * divwuo RT,RA,RB (OE=1 Rc=0)
 413 * divwuo.  RT,RA,RB (OE=1 Rc=1)
 414
 415 Pseudo-code:
 416
 417     dividend[0:31] <- (RA)[32:63]
 418     divisor[0:31] <- (RB)[32:63]
 419     if divisor != 0 then
 420         RT[32:63] <-  dividend / divisor
 421         RT[0:31] <- undefined[0:31]
 422         overflow <- 0
 423     else
 424         RT[0:63] <- undefined[0:63]
 425         overflow <- 1
 426
 427 Special Registers Altered:
 428
 429     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 430     SO OV OV32                              (if OE=1)
 431
 432 # Divide Word Extended
 433
 434 XO-Form
 435
 436 * divwe RT,RA,RB (OE=0 Rc=0)
 437 * divwe.  RT,RA,RB (OE=0 Rc=1)
 438 * divweo RT,RA,RB (OE=1 Rc=0)
 439 * divweo.  RT,RA,RB (OE=1 Rc=1)
 440
 441 Pseudo-code:
 442
 443     dividend[0:63] <- (RA)[32:63] || [0]*32
 444     divisor[0:63] <- [0]*32 || (RB)[32:63]
 445     if (divisor = 0x0000_0000_0000_0000) then
 446         overflow <- 1
 447     else
 448         result <- DIVS(dividend, divisor)
 449         if (result[32:63] = 0) then
 450             RT[32:63] <- result[0:31]
 451             RT[0:31] <- undefined[0:31]
 452             overflow <- 0
 453         else
 454             overflow <- 1
 455     if overflow = 1 then
 456         RT[0:63] <- undefined[0:63]
 457
 458 Special Registers Altered:
 459
 460     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 461     SO OV OV32                              (if OE=1)
 462
 463 # Divide Word Extended Unsigned
 464
 465 XO-Form
 466
 467 * divweu RT,RA,RB (OE=0 Rc=0)
 468 * divweu.  RT,RA,RB (OE=0 Rc=1)
 469 * divweuo RT,RA,RB (OE=1 Rc=0)
 470 * divweuo.  RT,RA,RB (OE=1 Rc=1)
 471
 472 Pseudo-code:
 473
 474     dividend[0:63] <- (RA)[32:63] || [0]*32
 475     divisor[0:63] <- [0]*32 || (RB)[32:63]
 476     if (divisor = 0x0000_0000_0000_0000) then
 477         overflow <- 1
 478     else
 479         result <- dividend /  divisor
 480         if (RA) < (RB) then
 481             RT[32:63] <- result[0:31]
 482             RT[0:31] <- undefined[0:31]
 483             overflow <- 0
 484         else
 485             overflow <- 1
 486     if overflow = 1 then
 487         RT[0:63] <- undefined[0:63]
 488
 489 Special Registers Altered:
 490
 491     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 492     SO OV OV32                              (if OE=1)
 493
 494 # Modulo Signed Word
 495
 496 X-Form
 497
 498 * modsw RT,RA,RB
 499
 500 Pseudo-code:
 501
 502     dividend[0:31] <- (RA)[32:63]
 503     divisor [0:31] <- (RB)[32:63]
 504     if (((dividend = 0x8000_0000) &
 505          (divisor = 0xffff_ffff)) |
 506          (divisor = 0x0000_0000)) then
 507         RT[0:63] <- undefined[0:63]
 508         overflow <- 1
 509     else
 510         RT[32:63] <- MODS(dividend, divisor)
 511         RT[0:31] <- undefined[0:31]
 512         overflow <- 0
 513
 514 Special Registers Altered:
 515
 516     None
 517
 518 # Modulo Unsigned Word
 519
 520 X-Form
 521
 522 * moduw RT,RA,RB
 523
 524 Pseudo-code:
 525
 526     dividend[0:31] <- (RA) [32:63]
 527     divisor [0:31] <- (RB) [32:63]
 528     if divisor = 0x0000_0000 then
 529         RT[0:63] <- undefined[0:63]
 530         overflow <- 1
 531     else
 532         RT[32:63] <- MODS(dividend, divisor)
 533         RT[0:31] <- undefined[0:31]
 534         overflow <- 0
 535
 536 Special Registers Altered:
 537
 538     None
 539
 540 # Deliver A Random Number
 541
 542 X-Form
 543
 544 * darn RT,L
 545
 546 Pseudo-code:
 547
 548     RT <- random(L)
 549
 550 Special Registers Altered:
 551
 552     none
 553
 554 # Multiply Low Doubleword
 555
 556 XO-Form
 557
 558 * mulld RT,RA,RB (OE=0 Rc=0)
 559 * mulld.  RT,RA,RB (OE=0 Rc=1)
 560 * mulldo RT,RA,RB (OE=1 Rc=0)
 561 * mulldo.  RT,RA,RB (OE=1 Rc=1)
 562
 563 Pseudo-code:
 564
 565     prod[0:127] <- MULS((RA), (RB))
 566     RT <- prod[64:127]
 567
 568 Special Registers Altered:
 569
 570     CR0                     (if Rc=1)
 571     SO OV OV32             (if OE=1)
 572
 573 # Multiply High Doubleword
 574
 575 XO-Form
 576
 577 * mulhd RT,RA,RB (Rc=0)
 578 * mulhd.  RT,RA,RB (Rc=1)
 579
 580 Pseudo-code:
 581
 582     prod[0:127] <- MULS((RA), (RB))
 583     RT <- prod[0:63]
 584
 585 Special Registers Altered:
 586
 587     CR0                     (if Rc=1)
 588
 589 # Multiply High Doubleword Unsigned
 590
 591 XO-Form
 592
 593 * mulhdu RT,RA,RB (Rc=0)
 594 * mulhdu.  RT,RA,RB (Rc=1)
 595
 596 Pseudo-code:
 597
 598     prod[0:127] <- (RA) *  (RB)
 599     RT <- prod[0:63]
 600
 601 Special Registers Altered:
 602
 603     CR0                    (if Rc=1)
 604
 605 # Multiply-Add High Doubleword VA-Form
 606
 607 VA-Form
 608
 609 * maddhd RT,RA.RB,RC
 610
 611 Pseudo-code:
 612
 613     prod[0:127] <- MULS((RA), (RB))
 614     sum[0:127] <- prod + EXTS(RC)
 615     RT <- sum[0:63]
 616
 617 Special Registers Altered:
 618
 619     None
 620
 621 # Multiply-Add High Doubleword Unsigned
 622
 623 VA-Form
 624
 625 * maddhdu RT,RA.RB,RC
 626
 627 Pseudo-code:
 628
 629     prod[0:127] <- (RA) * (RB)
 630     sum[0:127] <- prod + EXTZ(RC)
 631     RT <- sum[0:63]
 632
 633 Special Registers Altered:
 634
 635     None
 636
 637 # Multiply-Add Low Doubleword
 638
 639 VA-Form
 640
 641 * maddld RT,RA.RB,RC
 642
 643 Pseudo-code:
 644
 645     prod[0:127] <- MULS((RA), (RB))
 646     sum[0:127] <- prod + EXTS(RC)
 647     RT <- sum[64:127]
 648
 649 Special Registers Altered:
 650
 651     None
 652
 653 # Divide Doubleword
 654
 655 XO-Form
 656
 657 * divd RT,RA,RB (OE=0 Rc=0)
 658 * divd.  RT,RA,RB (OE=0 Rc=1)
 659 * divdo RT,RA,RB (OE=1 Rc=0)
 660 * divdo.  RT,RA,RB (OE=1 Rc=1)
 661
 662 Pseudo-code:
 663
 664     dividend[0:63] <- (RA)
 665     divisor[0:63] <- (RB)
 666     if (((dividend = 0x8000_0000_0000_0000) &
 667          (divisor = 0xffff_ffff_ffff_ffff)) |
 668          (divisor = 0x0000_0000_0000_0000)) then
 669         RT[0:63] <- undefined[0:63]
 670         overflow <- 1
 671     else
 672         RT <- DIVS(dividend, divisor)
 673         overflow <- 0
 674
 675 Special Registers Altered:
 676
 677     CR0                     (if Rc=1)
 678     SO OV OV32             (if OE=1)
 679
 680 # Divide Doubleword Unsigned
 681
 682 XO-Form
 683
 684 * divdu RT,RA,RB (OE=0 Rc=0)
 685 * divdu.  RT,RA,RB (OE=0 Rc=1)
 686 * divduo RT,RA,RB (OE=1 Rc=0)
 687 * divduo.  RT,RA,RB (OE=1 Rc=1)
 688
 689 Pseudo-code:
 690
 691     dividend[0:63] <- (RA)
 692     divisor[0:63] <- (RB)
 693     if (divisor = 0x0000_0000_0000_0000) then
 694         RT[0:63] <- undefined[0:63]
 695         overflow <- 1
 696     else
 697         RT <- dividend / divisor
 698         overflow <- 0
 699
 700 Special Registers Altered:
 701
 702     CR0                     (if Rc=1)
 703     SO OV OV32             (if OE=1)
 704
 705 # Divide Doubleword Extended
 706
 707 XO-Form
 708
 709 * divde RT,RA,RB (OE=0 Rc=0)
 710 * divde.  RT,RA,RB (OE=0 Rc=1)
 711 * divdeo RT,RA,RB (OE=1 Rc=0)
 712 * divdeo.  RT,RA,RB (OE=1 Rc=1)
 713
 714 Pseudo-code:
 715
 716     dividend[0:127] <-  (RA) || [0]*64
 717     divisor[0:127] <- [0*64] || (RB)
 718     if divisor = [0]*128 then
 719         overflow <- 1
 720     else
 721         result <- DIVS(dividend, divisor)
 722         if result[64:127] = 0x0000_0000_0000_0000 then
 723             RT <- result[63:127]
 724             overflow <- 0
 725         else
 726             overflow <- 1
 727     if overflow = 1 then
 728         RT[0:63] <- undefined[0:63]
 729
 730 Special Registers Altered:
 731
 732     CR0                     (if Rc=1)
 733     SO OV OV32             (if OE=1)
 734
 735 # Divide Doubleword Extended Unsigned
 736
 737 XO-Form
 738
 739 * divdeu RT,RA,RB (OE=0 Rc=0)
 740 * divdeu.  RT,RA,RB (OE=0 Rc=1)
 741 * divdeuo RT,RA,RB (OE=1 Rc=0)
 742 * divdeuo.  RT,RA,RB (OE=1 Rc=1)
 743
 744 Pseudo-code:
 745
 746     dividend[0:127] <-  (RA) || [0]*64
 747     divisor[0:127] <- [0*64] || (RB)
 748     if divisor = [0]*128 then
 749         overflow <- 1
 750     else
 751         result <- dividend /  divisor
 752         if (RA) < (RB) then
 753             RT <- result[63:127]
 754             overflow <- 0
 755         else
 756             overflow <- 1
 757     if overflow = 1 then
 758         RT[0:63] <- undefined[0:63]
 759
 760 Special Registers Altered:
 761
 762     CR0                     (if Rc=1)
 763     SO OV OV32             (if OE=1)
 764
 765 # Modulo Signed Doubleword
 766
 767 X-Form
 768
 769 * modsd RT,RA,RB
 770
 771 Pseudo-code:
 772
 773     dividend <- (RA)
 774     divisor  <- (RB)
 775     if (((dividend = 0x8000_0000_0000_0000) &
 776          (divisor = 0xffff_ffff_ffff_ffff)) |
 777          (divisor = 0x0000_0000_0000_0000)) then
 778         RT[0:63] <- undefined[0:63]
 779         overflow <- 1
 780     else
 781         RT       <- MODS(dividend, divisor)
 782         overflow <- 0
 783
 784 Special Registers Altered:
 785
 786     None
 787
 788 # Modulo Unsigned Doubleword
 789
 790 X-Form
 791
 792 * modud RT,RA,RB
 793
 794 Pseudo-code:
 795
 796     dividend <- (RA)
 797     divisor  <- (RB)
 798     if (divisor = 0x0000_0000_0000_0000) then
 799         RT[0:63] <- undefined[0:63]
 800         overflow <- 1
 801     else
 802         RT       <- dividend % divisor
 803         overflow <- 0
 804
 805 Special Registers Altered:
 806
 807     None
 808