9 RT <- (RA|0) + EXTS(SI)
11 Special Registers Altered:
15 # Add Immediate Shifted
23 RT <- (RA|0) + EXTS(SI || [0]*16)
25 Special Registers Altered:
29 # Add PC Immediate Shifted
38 RT <- NIA + EXTS(D || [0]*16)
40 Special Registers Altered:
48 * add RT,RA,RB (OE=0 Rc=0)
49 * add. RT,RA,RB (OE=0 Rc=1)
50 * addo RT,RA,RB (OE=1 Rc=0)
51 * addo. RT,RA,RB (OE=1 Rc=1)
57 Special Registers Altered:
66 * subf RT,RA,RB (OE=0 Rc=0)
67 * subf. RT,RA,RB (OE=0 Rc=1)
68 * subfo RT,RA,RB (OE=1 Rc=0)
69 * subfo. RT,RA,RB (OE=1 Rc=1)
73 RT <- ¬(RA) + (RB) + 1
75 Special Registers Altered:
80 # Add Immediate Carrying
90 Special Registers Altered:
94 # Add Immediate Carrying and Record
102 RT <- (RA) + EXTS(SI)
104 Special Registers Altered:
108 # Subtract From Immediate Carrying
116 RT <- ¬(RA) + EXTS(SI) + 1
118 Special Registers Altered:
126 * addc RT,RA,RB (OE=0 Rc=0)
127 * addc. RT,RA,RB (OE=0 Rc=1)
128 * addco RT,RA,RB (OE=1 Rc=0)
129 * addco. RT,RA,RB (OE=1 Rc=1)
135 Special Registers Altered:
141 # Subtract From Carrying
145 * subfc RT,RA,RB (OE=0 Rc=0)
146 * subfc. RT,RA,RB (OE=0 Rc=1)
147 * subfco RT,RA,RB (OE=1 Rc=0)
148 * subfco. RT,RA,RB (OE=1 Rc=1)
152 RT <- ¬(RA) + (RB) + 1
154 Special Registers Altered:
164 * adde RT,RA,RB (OE=0 Rc=0)
165 * adde. RT,RA,RB (OE=0 Rc=1)
166 * addeo RT,RA,RB (OE=1 Rc=0)
167 * addeo. RT,RA,RB (OE=1 Rc=1)
171 RT <- (RA) + (RB) + CA
173 Special Registers Altered:
179 # Subtract From Extended
183 * subfe RT,RA,RB (OE=0 Rc=0)
184 * subfe. RT,RA,RB (OE=0 Rc=1)
185 * subfeo RT,RA,RB (OE=1 Rc=0)
186 * subfeo. RT,RA,RB (OE=1 Rc=1)
190 RT <- ¬(RA) + (RB) + CA
192 Special Registers Altered:
198 # Add to Minus One Extended
202 * addme RT,RA (OE=0 Rc=0)
203 * addme. RT,RA (OE=0 Rc=1)
204 * addmeo RT,RA (OE=1 Rc=0)
205 * addmeo. RT,RA (OE=1 Rc=1)
211 Special Registers Altered:
217 # Subtract From Minus One Extended
221 * subfme RT,RA (OE=0 Rc=0)
222 * subfme. RT,RA (OE=0 Rc=1)
223 * subfmeo RT,RA (OE=1 Rc=0)
224 * subfmeo. RT,RA (OE=1 Rc=1)
230 Special Registers Altered:
236 # Add Extended using alternate carry bit
244 if CY=0 then RT <- (RA) + (RB) + OV
246 Special Registers Altered:
250 # Subtract From Zero Extended
254 * subfze RT,RA (OE=0 Rc=0)
255 * subfze. RT,RA (OE=0 Rc=1)
256 * subfzeo RT,RA (OE=1 Rc=0)
257 * subfzeo. RT,RA (OE=1 Rc=1)
263 Special Registers Altered:
269 # Add to Zero Extended
273 * addze RT,RA (OE=0 Rc=0)
274 * addze. RT,RA (OE=0 Rc=1)
275 * addzeo RT,RA (OE=1 Rc=0)
276 * addzeo. RT,RA (OE=1 Rc=1)
282 Special Registers Altered:
292 * neg RT,RA (OE=0 Rc=0)
293 * neg. RT,RA (OE=0 Rc=1)
294 * nego RT,RA (OE=1 Rc=0)
295 * nego. RT,RA (OE=1 Rc=1)
301 Special Registers Altered:
306 # Multiply Low Immediate
314 prod[0:127] <- MULS((RA), EXTS(SI))
317 Special Registers Altered:
325 * mulhw RT,RA,RB (Rc=0)
326 * mulhw. RT,RA,RB (Rc=1)
330 prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
331 RT[32:63] <- prod[0:31]
332 RT[0:31] <- prod[0:31]
334 Special Registers Altered:
336 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
342 * mullw RT,RA,RB (OE=0 Rc=0)
343 * mullw. RT,RA,RB (OE=0 Rc=1)
344 * mullwo RT,RA,RB (OE=1 Rc=0)
345 * mullwo. RT,RA,RB (OE=1 Rc=1)
349 prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
351 overflow <- ((prod[0:32] != [0]*33) &
352 (prod[0:32] != [1]*33))
354 Special Registers Altered:
359 # Multiply High Word Unsigned
363 * mulhwu RT,RA,RB (Rc=0)
364 * mulhwu. RT,RA,RB (Rc=1)
368 prod[0:63] <- (RA)[32:63] * (RB)[32:63]
369 RT[32:63] <- prod[0:31]
370 RT[0:31] <- prod[0:31]
372 Special Registers Altered:
374 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
380 * divw RT,RA,RB (OE=0 Rc=0)
381 * divw. RT,RA,RB (OE=0 Rc=1)
382 * divwo RT,RA,RB (OE=1 Rc=0)
383 * divwo. RT,RA,RB (OE=1 Rc=1)
387 dividend[0:31] <- (RA)[32:63]
388 divisor[0:31] <- (RB) [32:63]
389 if (((dividend = 0x8000_0000) &
390 (divisor = 0xffff_ffff)) |
391 (divisor = 0x0000_0000)) then
392 RT[0:63] <- undefined[0:63]
395 RT[32:63] <- DIVS(dividend, divisor)
396 RT[0:31] <- undefined[0:31]
399 Special Registers Altered:
401 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
404 # Divide Word Unsigned
408 * divwu RT,RA,RB (OE=0 Rc=0)
409 * divwu. RT,RA,RB (OE=0 Rc=1)
410 * divwuo RT,RA,RB (OE=1 Rc=0)
411 * divwuo. RT,RA,RB (OE=1 Rc=1)
415 dividend[0:31] <- (RA)[32:63]
416 divisor[0:31] <- (RB)[32:63]
418 RT[32:63] <- dividend / divisor
419 RT[0:31] <- undefined[0:31]
422 RT[0:63] <- undefined[0:63]
425 Special Registers Altered:
427 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
430 # Divide Word Extended
434 * divwe RT,RA,RB (OE=0 Rc=0)
435 * divwe. RT,RA,RB (OE=0 Rc=1)
436 * divweo RT,RA,RB (OE=1 Rc=0)
437 * divweo. RT,RA,RB (OE=1 Rc=1)
441 dividend[0:63] <- (RA)[32:63] || [0]*32
442 divisor[0:63] <- [0]*32 || (RB)[32:63]
443 if (divisor = 0x0000_0000_0000_0000) then
446 result <- DIVS(dividend, divisor)
447 if (result[32:63] = 0) then
448 RT[32:63] <- result[0:31]
449 RT[0:31] <- undefined[0:31]
454 RT[0:63] <- undefined[0:63]
456 Special Registers Altered:
458 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
461 # Divide Word Extended Unsigned
465 * divweu RT,RA,RB (OE=0 Rc=0)
466 * divweu. RT,RA,RB (OE=0 Rc=1)
467 * divweuo RT,RA,RB (OE=1 Rc=0)
468 * divweuo. RT,RA,RB (OE=1 Rc=1)
472 dividend[0:63] <- (RA)[32:63] || [0]*32
473 divisor[0:63] <- [0]*32 || (RB)[32:63]
474 if (divisor = 0x0000_0000_0000_0000) then
477 result <- dividend / divisor
479 RT[32:63] <- result[0:31]
480 RT[0:31] <- undefined[0:31]
485 RT[0:63] <- undefined[0:63]
487 Special Registers Altered:
489 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
500 dividend[0:31] <- (RA)[32:63]
501 divisor [0:31] <- (RB)[32:63]
502 if (((dividend = 0x8000_0000) &
503 (divisor = 0xffff_ffff)) |
504 (divisor = 0x0000_0000)) then
505 RT[0:63] <- undefined[0:63]
508 RT[32:63] <- MODS(dividend, divisor)
509 RT[0:31] <- undefined[0:31]
512 Special Registers Altered:
516 # Modulo Unsigned Word
524 dividend[0:31] <- (RA) [32:63]
525 divisor [0:31] <- (RB) [32:63]
526 if divisor = 0x0000_0000 then
527 RT[0:63] <- undefined[0:63]
530 RT[32:63] <- MODS(dividend, divisor)
531 RT[0:31] <- undefined[0:31]
534 Special Registers Altered:
538 # Deliver A Random Number
548 Special Registers Altered:
552 # Multiply Low Doubleword
556 * mulld RT,RA,RB (OE=0 Rc=0)
557 * mulld. RT,RA,RB (OE=0 Rc=1)
558 * mulldo RT,RA,RB (OE=1 Rc=0)
559 * mulldo. RT,RA,RB (OE=1 Rc=1)
563 prod[0:127] <- MULS((RA), (RB))
565 overflow <- ((prod[0:64] != [0]*65) &
566 (prod[0:64] != [1]*65))
568 Special Registers Altered:
573 # Multiply High Doubleword
577 * mulhd RT,RA,RB (Rc=0)
578 * mulhd. RT,RA,RB (Rc=1)
582 prod[0:127] <- MULS((RA), (RB))
585 Special Registers Altered:
589 # Multiply High Doubleword Unsigned
593 * mulhdu RT,RA,RB (Rc=0)
594 * mulhdu. RT,RA,RB (Rc=1)
598 prod[0:127] <- (RA) * (RB)
601 Special Registers Altered:
605 # Multiply-Add High Doubleword VA-Form
613 prod[0:127] <- MULS((RA), (RB))
614 sum[0:127] <- prod + EXTS(RC)
617 Special Registers Altered:
621 # Multiply-Add High Doubleword Unsigned
625 * maddhdu RT,RA.RB,RC
629 prod[0:127] <- (RA) * (RB)
630 sum[0:127] <- prod + EXTZ(RC)
633 Special Registers Altered:
637 # Multiply-Add Low Doubleword
645 prod[0:127] <- MULS((RA), (RB))
646 sum[0:127] <- prod + EXTS(RC)
649 Special Registers Altered:
657 * divd RT,RA,RB (OE=0 Rc=0)
658 * divd. RT,RA,RB (OE=0 Rc=1)
659 * divdo RT,RA,RB (OE=1 Rc=0)
660 * divdo. RT,RA,RB (OE=1 Rc=1)
664 dividend[0:63] <- (RA)
665 divisor[0:63] <- (RB)
666 if (((dividend = 0x8000_0000_0000_0000) &
667 (divisor = 0xffff_ffff_ffff_ffff)) |
668 (divisor = 0x0000_0000_0000_0000)) then
669 RT[0:63] <- undefined[0:63]
672 RT <- DIVS(dividend, divisor)
675 Special Registers Altered:
680 # Divide Doubleword Unsigned
684 * divdu RT,RA,RB (OE=0 Rc=0)
685 * divdu. RT,RA,RB (OE=0 Rc=1)
686 * divduo RT,RA,RB (OE=1 Rc=0)
687 * divduo. RT,RA,RB (OE=1 Rc=1)
691 dividend[0:63] <- (RA)
692 divisor[0:63] <- (RB)
693 if (divisor = 0x0000_0000_0000_0000) then
694 RT[0:63] <- undefined[0:63]
697 RT <- dividend / divisor
700 Special Registers Altered:
705 # Divide Doubleword Extended
709 * divde RT,RA,RB (OE=0 Rc=0)
710 * divde. RT,RA,RB (OE=0 Rc=1)
711 * divdeo RT,RA,RB (OE=1 Rc=0)
712 * divdeo. RT,RA,RB (OE=1 Rc=1)
716 dividend[0:127] <- (RA) || [0]*64
717 divisor[0:127] <- [0]*64 || (RB)
718 if divisor = [0]*128 then
721 result <- DIVS(dividend, divisor)
722 if result[64:127] = 0x0000_0000_0000_0000 then
728 RT[0:63] <- undefined[0:63]
730 Special Registers Altered:
735 # Divide Doubleword Extended Unsigned
739 * divdeu RT,RA,RB (OE=0 Rc=0)
740 * divdeu. RT,RA,RB (OE=0 Rc=1)
741 * divdeuo RT,RA,RB (OE=1 Rc=0)
742 * divdeuo. RT,RA,RB (OE=1 Rc=1)
746 dividend[0:127] <- (RA) || [0]*64
747 divisor[0:127] <- [0]*64 || (RB)
748 if divisor = [0]*128 then
751 result <- dividend / divisor
758 RT[0:63] <- undefined[0:63]
760 Special Registers Altered:
765 # Modulo Signed Doubleword
775 if (((dividend = 0x8000_0000_0000_0000) &
776 (divisor = 0xffff_ffff_ffff_ffff)) |
777 (divisor = 0x0000_0000_0000_0000)) then
778 RT[0:63] <- undefined[0:63]
781 RT <- MODS(dividend, divisor)
784 Special Registers Altered:
788 # Modulo Unsigned Doubleword
798 if (divisor = 0x0000_0000_0000_0000) then
799 RT[0:63] <- undefined[0:63]
802 RT <- dividend % divisor
805 Special Registers Altered: