9 if RA = 0 then RT <- EXTS(SI)
10 else RT <- (RA) + EXTS(SI)
12 Special Registers Altered:
16 # Add Immediate Shifted
24 if RA = 0 then RT <- EXTS(SI || [0]*16)
25 else RT <- (RA) + EXTS(SI || [0]*16)
27 Special Registers Altered:
31 # Add PC Immediate Shifted
40 RT <- NIA + EXTS(D || [0]*16)
42 Special Registers Altered:
50 * add RT,RA,RB (OE=0 Rc=0)
51 * add. RT,RA,RB (OE=0 Rc=1)
52 * addo RT,RA,RB (OE=1 Rc=0)
53 * addo. RT,RA,RB (OE=1 Rc=1)
59 Special Registers Altered:
68 * subf RT,RA,RB (OE=0 Rc=0)
69 * subf. RT,RA,RB (OE=0 Rc=1)
70 * subfo RT,RA,RB (OE=1 Rc=0)
71 * subfo. RT,RA,RB (OE=1 Rc=1)
75 RT <- ¬(RA) + (RB) + 1
77 Special Registers Altered:
82 # Add Immediate Carrying
92 Special Registers Altered:
96 # Add Immediate Carrying and Record
104 RT <- (RA) + EXTS(SI)
106 Special Registers Altered:
110 # Subtract From Immediate Carrying
118 RT <- ¬(RA) + EXTS(SI) + 1
120 Special Registers Altered:
128 * addc RT,RA,RB (OE=0 Rc=0)
129 * addc. RT,RA,RB (OE=0 Rc=1)
130 * addco RT,RA,RB (OE=1 Rc=0)
131 * addco. RT,RA,RB (OE=1 Rc=1)
137 Special Registers Altered:
143 # Subtract From Carrying
147 * subfc RT,RA,RB (OE=0 Rc=0)
148 * subfc. RT,RA,RB (OE=0 Rc=1)
149 * subfco RT,RA,RB (OE=1 Rc=0)
150 * subfco. RT,RA,RB (OE=1 Rc=1)
154 RT <- ¬(RA) + (RB) + 1
156 Special Registers Altered:
166 * adde RT,RA,RB (OE=0 Rc=0)
167 * adde. RT,RA,RB (OE=0 Rc=1)
168 * addeo RT,RA,RB (OE=1 Rc=0)
169 * addeo. RT,RA,RB (OE=1 Rc=1)
173 RT <- (RA) + (RB) + CA
175 Special Registers Altered:
181 # Subtract From Extended
185 * subfe RT,RA,RB (OE=0 Rc=0)
186 * subfe. RT,RA,RB (OE=0 Rc=1)
187 * subfeo RT,RA,RB (OE=1 Rc=0)
188 * subfeo. RT,RA,RB (OE=1 Rc=1)
192 RT <- ¬(RA) + (RB) + CA
194 Special Registers Altered:
200 # Add to Minus One Extended
204 * addme RT,RA (OE=0 Rc=0)
205 * addme. RT,RA (OE=0 Rc=1)
206 * addmeo RT,RA (OE=1 Rc=0)
207 * addmeo. RT,RA (OE=1 Rc=1)
213 Special Registers Altered:
219 # Subtract From Minus One Extended
223 * subfme RT,RA (OE=0 Rc=0)
224 * subfme. RT,RA (OE=0 Rc=1)
225 * subfmeo RT,RA (OE=1 Rc=0)
226 * subfmeo. RT,RA (OE=1 Rc=1)
232 Special Registers Altered:
238 # Add Extended using alternate carry bit
246 if CY=0 then RT <- (RA) + (RB) + OV
248 Special Registers Altered:
252 # Subtract From Zero Extended
256 * subfze RT,RA (OE=0 Rc=0)
257 * subfze. RT,RA (OE=0 Rc=1)
258 * subfzeo RT,RA (OE=1 Rc=0)
259 * subfzeo. RT,RA (OE=1 Rc=1)
265 Special Registers Altered:
271 # Add to Zero Extended
275 * addze RT,RA (OE=0 Rc=0)
276 * addze. RT,RA (OE=0 Rc=1)
277 * addzeo RT,RA (OE=1 Rc=0)
278 * addzeo. RT,RA (OE=1 Rc=1)
284 Special Registers Altered:
294 * neg RT,RA (OE=0 Rc=0)
295 * neg. RT,RA (OE=0 Rc=1)
296 * nego RT,RA (OE=1 Rc=0)
297 * nego. RT,RA (OE=1 Rc=1)
303 Special Registers Altered:
308 # Multiply Low Immediate
316 prod[0:127] <- MULS((RA), EXTS(SI))
319 Special Registers Altered:
327 * mulhw RT,RA,RB (Rc=0)
328 * mulhw. RT,RA,RB (Rc=1)
332 prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
333 RT[32:63] <- prod[0:31]
334 RT[0:31] <- prod[0:31]
336 Special Registers Altered:
338 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
344 * mullw RT,RA,RB (OE=0 Rc=0)
345 * mullw. RT,RA,RB (OE=0 Rc=1)
346 * mullwo RT,RA,RB (OE=1 Rc=0)
347 * mullwo. RT,RA,RB (OE=1 Rc=1)
351 prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
354 Special Registers Altered:
359 # Multiply High Word Unsigned
363 * mulhwu RT,RA,RB (Rc=0)
364 * mulhwu. RT,RA,RB (Rc=1)
368 prod[0:63] <- (RA)[32:63] * (RB)[32:63]
369 RT[32:63] <- prod[0:31]
370 RT[0:31] <- prod[0:31]
372 Special Registers Altered:
374 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
380 * divw RT,RA,RB (OE=0 Rc=0)
381 * divw. RT,RA,RB (OE=0 Rc=1)
382 * divwo RT,RA,RB (OE=1 Rc=0)
383 * divwo. RT,RA,RB (OE=1 Rc=1)
387 dividend[0:31] <- (RA)[32:63]
388 divisor[0:31] <- (RB) [32:63]
389 if (((dividend = 0x8000_0000) &
390 (divisor = 0xffff_ffff)) |
391 (divisor = 0x0000_0000)) then
392 RT[0:63] <- undefined[0:63]
395 RT[32:63] <- DIVS(dividend, divisor)
396 RT[0:31] <- undefined[0:31]
399 Special Registers Altered:
401 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
404 # Divide Word Unsigned
408 * divwu RT,RA,RB (OE=0 Rc=0)
409 * divwu. RT,RA,RB (OE=0 Rc=1)
410 * divwuo RT,RA,RB (OE=1 Rc=0)
411 * divwuo. RT,RA,RB (OE=1 Rc=1)
415 dividend[0:31] <- (RA)[32:63]
416 divisor[0:31] <- (RB)[32:63]
418 RT[32:63] <- dividend / divisor
419 RT[0:31] <- undefined[0:31]
422 RT[0:63] <- undefined[0:63]
425 Special Registers Altered:
427 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
430 # Divide Word Extended
434 * divwe RT,RA,RB (OE=0 Rc=0)
435 * divwe. RT,RA,RB (OE=0 Rc=1)
436 * divweo RT,RA,RB (OE=1 Rc=0)
437 * divweo. RT,RA,RB (OE=1 Rc=1)
441 dividend[0:63] <- (RA)[32:63] || [0]*32
442 divisor[0:63] <- [0]*32 || (RB)[32:63]
443 if (divisor = 0x0000_0000_0000_0000) then
446 result <- DIVS(dividend, divisor)
447 if (result[32:63] = 0) then
448 RT[32:63] <- result[0:31]
449 RT[0:31] <- undefined[0:31]
454 RT[0:63] <- undefined[0:63]
456 Special Registers Altered:
458 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
461 # Divide Word Extended Unsigned
465 * divweu RT,RA,RB (OE=0 Rc=0)
466 * divweu. RT,RA,RB (OE=0 Rc=1)
467 * divweuo RT,RA,RB (OE=1 Rc=0)
468 * divweuo. RT,RA,RB (OE=1 Rc=1)
472 dividend[0:63] <- (RA)[32:63] || [0]*32
473 divisor[0:63] <- [0]*32 || (RB)[32:63]
474 if (divisor = 0x0000_0000_0000_0000) then
477 result <- dividend / divisor
479 RT[32:63] <- result[0:31]
480 RT[0:31] <- undefined[0:31]
485 RT[0:63] <- undefined[0:63]
487 Special Registers Altered:
489 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
500 dividend[0:31] <- (RA)[32:63]
501 divisor [0:31] <- (RB)[32:63]
502 if (((dividend = 0x8000_0000) &
503 (divisor = 0xffff_ffff)) |
504 (divisor = 0x0000_0000)) then
505 RT[0:63] <- undefined[0:63]
508 RT[32:63] <- MODS(dividend, divisor)
509 RT[0:31] <- undefined[0:31]
512 Special Registers Altered:
516 # Modulo Unsigned Word
524 dividend[0:31] <- (RA) [32:63]
525 divisor [0:31] <- (RB) [32:63]
526 if divisor = 0x0000_0000 then
527 RT[0:63] <- undefined[0:63]
530 RT[32:63] <- MODS(dividend, divisor)
531 RT[0:31] <- undefined[0:31]
534 Special Registers Altered:
538 # Deliver A Random Number
548 Special Registers Altered:
552 # Multiply Low Doubleword
556 * mulld RT,RA,RB (OE=0 Rc=0)
557 * mulld. RT,RA,RB (OE=0 Rc=1)
558 * mulldo RT,RA,RB (OE=1 Rc=0)
559 * mulldo. RT,RA,RB (OE=1 Rc=1)
563 prod[0:127] <- MULS((RA), (RB))
566 Special Registers Altered:
571 # Multiply High Doubleword
575 * mulhd RT,RA,RB (Rc=0)
576 * mulhd. RT,RA,RB (Rc=1)
580 prod[0:127] <- MULS((RA), (RB))
583 Special Registers Altered:
587 # Multiply High Doubleword Unsigned
591 * mulhdu RT,RA,RB (Rc=0)
592 * mulhdu. RT,RA,RB (Rc=1)
596 prod[0:127] <- (RA) * (RB)
599 Special Registers Altered:
603 # Multiply-Add High Doubleword VA-Form
611 prod[0:127] <- MULS((RA), (RB))
612 sum[0:127] <- prod + EXTS(RC)
615 Special Registers Altered:
619 # Multiply-Add High Doubleword Unsigned
623 * maddhdu RT,RA.RB,RC
627 prod[0:127] <- (RA) * (RB)
628 sum[0:127] <- prod + EXTZ(RC)
631 Special Registers Altered:
635 # Multiply-Add Low Doubleword
643 prod[0:127] <- MULS((RA), (RB))
644 sum[0:127] <- prod + EXTS(RC)
647 Special Registers Altered:
655 * divd RT,RA,RB (OE=0 Rc=0)
656 * divd. RT,RA,RB (OE=0 Rc=1)
657 * divdo RT,RA,RB (OE=1 Rc=0)
658 * divdo. RT,RA,RB (OE=1 Rc=1)
662 dividend[0:63] <- (RA)
663 divisor[0:63] <- (RB)
664 if (((dividend = 0x8000_0000_0000_0000) &
665 (divisor = 0xffff_ffff_ffff_ffff)) |
666 (divisor = 0x0000_0000_0000_0000)) then
667 RT[0:63] <- undefined[0:63]
670 RT <- DIVS(dividend, divisor)
673 Special Registers Altered:
678 # Divide Doubleword Unsigned
682 * divdu RT,RA,RB (OE=0 Rc=0)
683 * divdu. RT,RA,RB (OE=0 Rc=1)
684 * divduo RT,RA,RB (OE=1 Rc=0)
685 * divduo. RT,RA,RB (OE=1 Rc=1)
689 dividend[0:63] <- (RA)
690 divisor[0:63] <- (RB)
691 if (divisor = 0x0000_0000_0000_0000) then
692 RT[0:63] <- undefined[0:63]
695 RT <- dividend / divisor
698 Special Registers Altered:
703 # Divide Doubleword Extended
707 * divde RT,RA,RB (OE=0 Rc=0)
708 * divde. RT,RA,RB (OE=0 Rc=1)
709 * divdeo RT,RA,RB (OE=1 Rc=0)
710 * divdeo. RT,RA,RB (OE=1 Rc=1)
714 dividend[0:127] <- (RA) || [0]*64
715 divisor[0:127] <- [0*64] || (RB)
716 if divisor = [0]*128 then
719 result <- DIVS(dividend, divisor)
720 if result[64:127] = 0x0000_0000_0000_0000 then
726 RT[0:63] <- undefined[0:63]
728 Special Registers Altered:
733 # Divide Doubleword Extended Unsigned
737 * divdeu RT,RA,RB (OE=0 Rc=0)
738 * divdeu. RT,RA,RB (OE=0 Rc=1)
739 * divdeuo RT,RA,RB (OE=1 Rc=0)
740 * divdeuo. RT,RA,RB (OE=1 Rc=1)
744 dividend[0:127] <- (RA) || [0]*64
745 divisor[0:127] <- [0*64] || (RB)
746 if divisor = [0]*128 then
749 result <- dividend / divisor
756 RT[0:63] <- undefined[0:63]
758 Special Registers Altered:
763 # Modulo Signed Doubleword
773 if (((dividend = 0x8000_0000_0000_0000) &
774 (divisor = 0xffff_ffff_ffff_ffff)) |
775 (divisor = 0x0000_0000_0000_0000)) then
776 RT[0:63] <- undefined[0:63]
779 RT <- MODS(dividend, divisor)
782 Special Registers Altered:
786 # Modulo Unsigned Doubleword
796 if (divisor = 0x0000_0000_0000_0000) then
797 RT[0:63] <- undefined[0:63]
800 RT <- dividend % divisor
803 Special Registers Altered: