openpower/isa/fixedarith.mdwn

   1 # Add Immediate
   2
   3 D-Form
   4
   5 * addi RT,RA,SI
   6
   7 Pseudo-code:
   8
   9     RT <- (RA|0) + EXTS(SI)
  10
  11 Special Registers Altered:
  12
  13     None
  14
  15 # Add Immediate Shifted
  16
  17 D-Form
  18
  19 * addis RT,RA,SI
  20
  21 Pseudo-code:
  22
  23     RT <- (RA|0) + EXTS(SI || [0]*16)
  24
  25 Special Registers Altered:
  26
  27     None
  28
  29 # Add PC Immediate Shifted
  30
  31 DX-Form
  32
  33 * addpcis RT,D
  34
  35 Pseudo-code:
  36
  37     D <- d0||d1||d2
  38     RT <- NIA + EXTS(D || [0]*16)
  39
  40 Special Registers Altered:
  41
  42     None
  43
  44 # Add
  45
  46 XO-Form
  47
  48 * add RT,RA,RB (OE=0 Rc=0)
  49 * add.  RT,RA,RB (OE=0 Rc=1)
  50 * addo RT,RA,RB (OE=1 Rc=0)
  51 * addo.  RT,RA,RB (OE=1 Rc=1)
  52
  53 Pseudo-code:
  54
  55     RT <- (RA) + (RB)
  56
  57 Special Registers Altered:
  58
  59     CR0                     (if Rc=1)
  60     SO OV OV32             (if OE=1)
  61
  62 # Subtract From
  63
  64 XO-Form
  65
  66 * subf RT,RA,RB (OE=0 Rc=0)
  67 * subf.  RT,RA,RB (OE=0 Rc=1)
  68 * subfo RT,RA,RB (OE=1 Rc=0)
  69 * subfo.  RT,RA,RB (OE=1 Rc=1)
  70
  71 Pseudo-code:
  72
  73     RT <- ¬(RA) + (RB) + 1
  74
  75 Special Registers Altered:
  76
  77     CR0                     (if Rc=1)
  78     SO OV OV32             (if OE=1)
  79
  80 # Add Immediate Carrying
  81
  82 D-Form
  83
  84 * addic RT,RA,SI
  85
  86 Pseudo-code:
  87
  88     RT <- (RA) + EXTS(SI)
  89
  90 Special Registers Altered:
  91
  92     CA CA32
  93
  94 # Add Immediate Carrying and Record
  95
  96 D-Form
  97
  98 * addic. RT,RA,SI
  99
 100 Pseudo-code:
 101
 102     RT <- (RA) + EXTS(SI)
 103
 104 Special Registers Altered:
 105
 106     CR0 CA CA32
 107
 108 # Subtract From Immediate Carrying
 109
 110 D-Form
 111
 112 * subfic RT,RA,SI
 113
 114 Pseudo-code:
 115
 116     RT <- ¬(RA) + EXTS(SI) + 1
 117
 118 Special Registers Altered:
 119
 120     CA CA32
 121
 122 # Add Carrying
 123
 124 XO-Form
 125
 126 * addc RT,RA,RB (OE=0 Rc=0)
 127 * addc.  RT,RA,RB (OE=0 Rc=1)
 128 * addco RT,RA,RB (OE=1 Rc=0)
 129 * addco.  RT,RA,RB (OE=1 Rc=1)
 130
 131 Pseudo-code:
 132
 133     RT <- (RA) + (RB)
 134
 135 Special Registers Altered:
 136
 137     CA CA32
 138     CR0                     (if Rc=1)
 139     SO OV OV32             (if OE=1)
 140
 141 # Subtract From Carrying
 142
 143 XO-Form
 144
 145 * subfc RT,RA,RB (OE=0 Rc=0)
 146 * subfc.  RT,RA,RB (OE=0 Rc=1)
 147 * subfco RT,RA,RB (OE=1 Rc=0)
 148 * subfco.  RT,RA,RB (OE=1 Rc=1)
 149
 150 Pseudo-code:
 151
 152     RT <- ¬(RA) + (RB) + 1
 153
 154 Special Registers Altered:
 155
 156     CA CA32
 157     CR0                     (if Rc=1)
 158     SO OV OV32             (if OE=1)
 159
 160 # Add Extended
 161
 162 XO-Form
 163
 164 * adde RT,RA,RB (OE=0 Rc=0)
 165 * adde.  RT,RA,RB (OE=0 Rc=1)
 166 * addeo RT,RA,RB (OE=1 Rc=0)
 167 * addeo.  RT,RA,RB (OE=1 Rc=1)
 168
 169 Pseudo-code:
 170
 171     RT <- (RA) + (RB) + CA
 172
 173 Special Registers Altered:
 174
 175     CA CA32
 176     CR0                     (if Rc=1)
 177     SO OV OV32             (if OE=1)
 178
 179 # Subtract From Extended
 180
 181 XO-Form
 182
 183 * subfe RT,RA,RB (OE=0 Rc=0)
 184 * subfe.  RT,RA,RB (OE=0 Rc=1)
 185 * subfeo RT,RA,RB (OE=1 Rc=0)
 186 * subfeo.  RT,RA,RB (OE=1 Rc=1)
 187
 188 Pseudo-code:
 189
 190     RT <- ¬(RA) + (RB) + CA
 191
 192 Special Registers Altered:
 193
 194     CA CA32
 195     CR0                     (if Rc=1)
 196     SO OV OV32             (if OE=1)
 197
 198 # Add to Minus One Extended
 199
 200 XO-Form
 201
 202 * addme RT,RA (OE=0 Rc=0)
 203 * addme.  RT,RA (OE=0 Rc=1)
 204 * addmeo RT,RA (OE=1 Rc=0)
 205 * addmeo.  RT,RA (OE=1 Rc=1)
 206
 207 Pseudo-code:
 208
 209     RT <- (RA) + CA - 1
 210
 211 Special Registers Altered:
 212
 213     CA CA32
 214     CR0                     (if Rc=1)
 215     SO OV OV32             (if OE=1)
 216
 217 # Subtract From Minus One Extended
 218
 219 XO-Form
 220
 221 * subfme RT,RA (OE=0 Rc=0)
 222 * subfme.  RT,RA (OE=0 Rc=1)
 223 * subfmeo RT,RA (OE=1 Rc=0)
 224 * subfmeo.  RT,RA (OE=1 Rc=1)
 225
 226 Pseudo-code:
 227
 228     RT <- ¬(RA) + CA - 1
 229
 230 Special Registers Altered:
 231
 232     CA CA32
 233     CR0                     (if Rc=1)
 234     SO OV OV32             (if OE=1)
 235
 236 # Add Extended using alternate carry bit
 237
 238 Z23-Form
 239
 240 * addex RT,RA,RB,CY
 241
 242 Pseudo-code:
 243
 244     if CY=0 then RT <- (RA) + (RB) + OV
 245
 246 Special Registers Altered:
 247
 248     OV OV32                (if CY=0 )
 249
 250 # Subtract From Zero Extended
 251
 252 XO-Form
 253
 254 * subfze RT,RA (OE=0 Rc=0)
 255 * subfze.  RT,RA (OE=0 Rc=1)
 256 * subfzeo RT,RA (OE=1 Rc=0)
 257 * subfzeo.  RT,RA (OE=1 Rc=1)
 258
 259 Pseudo-code:
 260
 261     RT <- ¬(RA) + CA
 262
 263 Special Registers Altered:
 264
 265     CA CA32
 266     CR0                     (if Rc=1)
 267     SO OV OV32             (if OE=1)
 268
 269 # Add to Zero Extended
 270
 271 XO-Form
 272
 273 * addze RT,RA (OE=0 Rc=0)
 274 * addze.  RT,RA (OE=0 Rc=1)
 275 * addzeo RT,RA (OE=1 Rc=0)
 276 * addzeo.  RT,RA (OE=1 Rc=1)
 277
 278 Pseudo-code:
 279
 280     RT <- (RA) + CA
 281
 282 Special Registers Altered:
 283
 284     CA CA32
 285     CR0                     (if Rc=1)
 286     SO OV OV32             (if OE=1)
 287
 288 # Negate
 289
 290 XO-Form
 291
 292 * neg RT,RA (OE=0 Rc=0)
 293 * neg.  RT,RA (OE=0 Rc=1)
 294 * nego RT,RA (OE=1 Rc=0)
 295 * nego.  RT,RA (OE=1 Rc=1)
 296
 297 Pseudo-code:
 298
 299     RT <- ¬(RA) + 1
 300
 301 Special Registers Altered:
 302
 303     CR0                     (if Rc=1)
 304     SO OV OV32             (if OE=1)
 305
 306 # Multiply Low Immediate
 307
 308 D-Form
 309
 310 * mulli RT,RA,SI
 311
 312 Pseudo-code:
 313
 314     prod[0:127] <- MULS((RA), EXTS(SI))
 315     RT <- prod[64:127]
 316
 317 Special Registers Altered:
 318
 319     None
 320
 321 # Multiply High Word
 322
 323 XO-Form
 324
 325 * mulhw RT,RA,RB (Rc=0)
 326 * mulhw.  RT,RA,RB (Rc=1)
 327
 328 Pseudo-code:
 329
 330     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
 331     RT[32:63] <- prod[0:31]
 332     RT[0:31] <- prod[0:31]
 333
 334 Special Registers Altered:
 335
 336     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 337
 338 # Multiply Low Word
 339
 340 XO-Form
 341
 342 * mullw RT,RA,RB (OE=0 Rc=0)
 343 * mullw.  RT,RA,RB (OE=0 Rc=1)
 344 * mullwo RT,RA,RB (OE=1 Rc=0)
 345 * mullwo.  RT,RA,RB (OE=1 Rc=1)
 346
 347 Pseudo-code:
 348
 349     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
 350     RT <- prod
 351     overflow <- ((prod[0:32] != [0]*33) &
 352                  (prod[0:32] != [1]*33))
 353
 354 Special Registers Altered:
 355
 356     CR0                     (if Rc=1)
 357     SO OV OV32             (if OE=1)
 358
 359 # Multiply High Word Unsigned
 360
 361 XO-Form
 362
 363 * mulhwu RT,RA,RB (Rc=0)
 364 * mulhwu.  RT,RA,RB (Rc=1)
 365
 366 Pseudo-code:
 367
 368     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 369     RT[32:63] <- prod[0:31]
 370     RT[0:31] <- prod[0:31]
 371
 372 Special Registers Altered:
 373
 374     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 375
 376 # Divide Word
 377
 378 XO-Form
 379
 380 * divw RT,RA,RB (OE=0 Rc=0)
 381 * divw.  RT,RA,RB (OE=0 Rc=1)
 382 * divwo RT,RA,RB (OE=1 Rc=0)
 383 * divwo.  RT,RA,RB (OE=1 Rc=1)
 384
 385 Pseudo-code:
 386
 387     dividend[0:31] <-  (RA)[32:63]
 388     divisor[0:31] <- (RB) [32:63]
 389     if (((dividend = 0x8000_0000) &
 390          (divisor = 0xffff_ffff)) |
 391          (divisor = 0x0000_0000)) then
 392         RT[0:63] <- undefined[0:63]
 393         overflow <- 1
 394     else
 395         RT[32:63] <- DIVS(dividend, divisor)
 396         RT[0:31] <- undefined[0:31]
 397         overflow <- 0
 398
 399 Special Registers Altered:
 400
 401     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 402     SO OV OV32                              (if OE=1)
 403
 404 # Divide Word Unsigned
 405
 406 XO-Form
 407
 408 * divwu RT,RA,RB (OE=0 Rc=0)
 409 * divwu.  RT,RA,RB (OE=0 Rc=1)
 410 * divwuo RT,RA,RB (OE=1 Rc=0)
 411 * divwuo.  RT,RA,RB (OE=1 Rc=1)
 412
 413 Pseudo-code:
 414
 415     dividend[0:31] <- (RA)[32:63]
 416     divisor[0:31] <- (RB)[32:63]
 417     if divisor != 0 then
 418         RT[32:63] <-  dividend / divisor
 419         RT[0:31] <- undefined[0:31]
 420         overflow <- 0
 421     else
 422         RT[0:63] <- undefined[0:63]
 423         overflow <- 1
 424
 425 Special Registers Altered:
 426
 427     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 428     SO OV OV32                              (if OE=1)
 429
 430 # Divide Word Extended
 431
 432 XO-Form
 433
 434 * divwe RT,RA,RB (OE=0 Rc=0)
 435 * divwe.  RT,RA,RB (OE=0 Rc=1)
 436 * divweo RT,RA,RB (OE=1 Rc=0)
 437 * divweo.  RT,RA,RB (OE=1 Rc=1)
 438
 439 Pseudo-code:
 440
 441     dividend[0:63] <- (RA)[32:63] || [0]*32
 442     divisor[0:63] <- EXTS64((RB)[32:63])
 443     if (divisor = 0x0000_0000_0000_0000) then
 444         overflow <- 1
 445     else
 446         result <- DIVS(dividend, divisor)
 447         result32[0:63] <- EXTS64(result[32:63])
 448         if (result32 = result) then
 449             RT[32:63] <- result[32:63]
 450             RT[0:31] <- undefined[0:31]
 451             overflow <- 0
 452         else
 453             overflow <- 1
 454     if overflow = 1 then
 455         RT[0:63] <- undefined[0:63]
 456
 457 Special Registers Altered:
 458
 459     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 460     SO OV OV32                              (if OE=1)
 461
 462 # Divide Word Extended Unsigned
 463
 464 XO-Form
 465
 466 * divweu RT,RA,RB (OE=0 Rc=0)
 467 * divweu.  RT,RA,RB (OE=0 Rc=1)
 468 * divweuo RT,RA,RB (OE=1 Rc=0)
 469 * divweuo.  RT,RA,RB (OE=1 Rc=1)
 470
 471 Pseudo-code:
 472
 473     dividend[0:63] <- (RA)[32:63] || [0]*32
 474     divisor[0:63] <- [0]*32 || (RB)[32:63]
 475     if (divisor = 0x0000_0000_0000_0000) then
 476         overflow <- 1
 477     else
 478         result <- dividend /  divisor
 479         if (RA) < (RB) then
 480             RT[32:63] <- result[32:63]
 481             RT[0:31] <- undefined[0:31]
 482             overflow <- 0
 483         else
 484             overflow <- 1
 485     if overflow = 1 then
 486         RT[0:63] <- undefined[0:63]
 487
 488 Special Registers Altered:
 489
 490     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 491     SO OV OV32                              (if OE=1)
 492
 493 # Modulo Signed Word
 494
 495 X-Form
 496
 497 * modsw RT,RA,RB
 498
 499 Pseudo-code:
 500
 501     dividend[0:31] <- (RA)[32:63]
 502     divisor [0:31] <- (RB)[32:63]
 503     if (((dividend = 0x8000_0000) &
 504          (divisor = 0xffff_ffff)) |
 505          (divisor = 0x0000_0000)) then
 506         RT[0:63] <- undefined[0:63]
 507         overflow <- 1
 508     else
 509         RT[32:63] <- MODS(dividend, divisor)
 510         RT[0:31] <- undefined[0:31]
 511         overflow <- 0
 512
 513 Special Registers Altered:
 514
 515     None
 516
 517 # Modulo Unsigned Word
 518
 519 X-Form
 520
 521 * moduw RT,RA,RB
 522
 523 Pseudo-code:
 524
 525     dividend[0:31] <- (RA) [32:63]
 526     divisor [0:31] <- (RB) [32:63]
 527     if divisor = 0x0000_0000 then
 528         RT[0:63] <- undefined[0:63]
 529         overflow <- 1
 530     else
 531         RT[32:63] <- MODS(dividend, divisor)
 532         RT[0:31] <- undefined[0:31]
 533         overflow <- 0
 534
 535 Special Registers Altered:
 536
 537     None
 538
 539 # Deliver A Random Number
 540
 541 X-Form
 542
 543 * darn RT,L3
 544
 545 Pseudo-code:
 546
 547     RT <- random(L3)
 548
 549 Special Registers Altered:
 550
 551     none
 552
 553 # Multiply Low Doubleword
 554
 555 XO-Form
 556
 557 * mulld RT,RA,RB (OE=0 Rc=0)
 558 * mulld.  RT,RA,RB (OE=0 Rc=1)
 559 * mulldo RT,RA,RB (OE=1 Rc=0)
 560 * mulldo.  RT,RA,RB (OE=1 Rc=1)
 561
 562 Pseudo-code:
 563
 564     prod[0:127] <- MULS((RA), (RB))
 565     RT <- prod[64:127]
 566     overflow <- ((prod[0:64] != [0]*65) &
 567                  (prod[0:64] != [1]*65))
 568
 569 Special Registers Altered:
 570
 571     CR0                     (if Rc=1)
 572     SO OV OV32             (if OE=1)
 573
 574 # Multiply High Doubleword
 575
 576 XO-Form
 577
 578 * mulhd RT,RA,RB (Rc=0)
 579 * mulhd.  RT,RA,RB (Rc=1)
 580
 581 Pseudo-code:
 582
 583     prod[0:127] <- MULS((RA), (RB))
 584     RT <- prod[0:63]
 585
 586 Special Registers Altered:
 587
 588     CR0                     (if Rc=1)
 589
 590 # Multiply High Doubleword Unsigned
 591
 592 XO-Form
 593
 594 * mulhdu RT,RA,RB (Rc=0)
 595 * mulhdu.  RT,RA,RB (Rc=1)
 596
 597 Pseudo-code:
 598
 599     prod[0:127] <- (RA) *  (RB)
 600     RT <- prod[0:63]
 601
 602 Special Registers Altered:
 603
 604     CR0                    (if Rc=1)
 605
 606 # Multiply-Add High Doubleword VA-Form
 607
 608 VA-Form
 609
 610 * maddhd RT,RA.RB,RC
 611
 612 Pseudo-code:
 613
 614     prod[0:127] <- MULS((RA), (RB))
 615     sum[0:127] <- prod + EXTS(RC)
 616     RT <- sum[0:63]
 617
 618 Special Registers Altered:
 619
 620     None
 621
 622 # Multiply-Add High Doubleword Unsigned
 623
 624 VA-Form
 625
 626 * maddhdu RT,RA.RB,RC
 627
 628 Pseudo-code:
 629
 630     prod[0:127] <- (RA) * (RB)
 631     sum[0:127] <- prod + EXTZ(RC)
 632     RT <- sum[0:63]
 633
 634 Special Registers Altered:
 635
 636     None
 637
 638 # Multiply-Add Low Doubleword
 639
 640 VA-Form
 641
 642 * maddld RT,RA.RB,RC
 643
 644 Pseudo-code:
 645
 646     prod[0:127] <- MULS((RA), (RB))
 647     sum[0:127] <- prod + EXTS(RC)
 648     RT <- sum[64:127]
 649
 650 Special Registers Altered:
 651
 652     None
 653
 654 # Divide Doubleword
 655
 656 XO-Form
 657
 658 * divd RT,RA,RB (OE=0 Rc=0)
 659 * divd.  RT,RA,RB (OE=0 Rc=1)
 660 * divdo RT,RA,RB (OE=1 Rc=0)
 661 * divdo.  RT,RA,RB (OE=1 Rc=1)
 662
 663 Pseudo-code:
 664
 665     dividend[0:63] <- (RA)
 666     divisor[0:63] <- (RB)
 667     if (((dividend = 0x8000_0000_0000_0000) &
 668          (divisor = 0xffff_ffff_ffff_ffff)) |
 669          (divisor = 0x0000_0000_0000_0000)) then
 670         RT[0:63] <- undefined[0:63]
 671         overflow <- 1
 672     else
 673         RT <- DIVS(dividend, divisor)
 674         overflow <- 0
 675
 676 Special Registers Altered:
 677
 678     CR0                     (if Rc=1)
 679     SO OV OV32             (if OE=1)
 680
 681 # Divide Doubleword Unsigned
 682
 683 XO-Form
 684
 685 * divdu RT,RA,RB (OE=0 Rc=0)
 686 * divdu.  RT,RA,RB (OE=0 Rc=1)
 687 * divduo RT,RA,RB (OE=1 Rc=0)
 688 * divduo.  RT,RA,RB (OE=1 Rc=1)
 689
 690 Pseudo-code:
 691
 692     dividend[0:63] <- (RA)
 693     divisor[0:63] <- (RB)
 694     if (divisor = 0x0000_0000_0000_0000) then
 695         RT[0:63] <- undefined[0:63]
 696         overflow <- 1
 697     else
 698         RT <- dividend / divisor
 699         overflow <- 0
 700
 701 Special Registers Altered:
 702
 703     CR0                     (if Rc=1)
 704     SO OV OV32             (if OE=1)
 705
 706 # Divide Doubleword Extended
 707
 708 XO-Form
 709
 710 * divde RT,RA,RB (OE=0 Rc=0)
 711 * divde.  RT,RA,RB (OE=0 Rc=1)
 712 * divdeo RT,RA,RB (OE=1 Rc=0)
 713 * divdeo.  RT,RA,RB (OE=1 Rc=1)
 714
 715 Pseudo-code:
 716
 717     dividend[0:127] <-  (RA) || [0]*64
 718     divisor[0:127] <- [0]*64 || (RB)
 719     if divisor = [0]*128 then
 720         overflow <- 1
 721     else
 722         result <- DIVS(dividend, divisor)
 723         if result[0:64] = 0x0000_0000_0000_0000 then
 724             RT <- result[0:63]
 725             overflow <- 0
 726         else
 727             overflow <- 1
 728     if overflow = 1 then
 729         RT[0:63] <- undefined[0:63]
 730
 731 Special Registers Altered:
 732
 733     CR0                     (if Rc=1)
 734     SO OV OV32             (if OE=1)
 735
 736 # Divide Doubleword Extended Unsigned
 737
 738 XO-Form
 739
 740 * divdeu RT,RA,RB (OE=0 Rc=0)
 741 * divdeu.  RT,RA,RB (OE=0 Rc=1)
 742 * divdeuo RT,RA,RB (OE=1 Rc=0)
 743 * divdeuo.  RT,RA,RB (OE=1 Rc=1)
 744
 745 Pseudo-code:
 746
 747     dividend[0:127] <-  (RA) || [0]*64
 748     divisor[0:127] <- [0]*64 || (RB)
 749     if divisor = [0]*128 then
 750         overflow <- 1
 751     else
 752         result <- dividend /  divisor
 753         if (RA) < (RB) then
 754             RT <- result[0:63]
 755             overflow <- 0
 756         else
 757             overflow <- 1
 758     if overflow = 1 then
 759         RT[0:63] <- undefined[0:63]
 760
 761 Special Registers Altered:
 762
 763     CR0                     (if Rc=1)
 764     SO OV OV32             (if OE=1)
 765
 766 # Modulo Signed Doubleword
 767
 768 X-Form
 769
 770 * modsd RT,RA,RB
 771
 772 Pseudo-code:
 773
 774     dividend <- (RA)
 775     divisor  <- (RB)
 776     if (((dividend = 0x8000_0000_0000_0000) &
 777          (divisor = 0xffff_ffff_ffff_ffff)) |
 778          (divisor = 0x0000_0000_0000_0000)) then
 779         RT[0:63] <- undefined[0:63]
 780         overflow <- 1
 781     else
 782         RT       <- MODS(dividend, divisor)
 783         overflow <- 0
 784
 785 Special Registers Altered:
 786
 787     None
 788
 789 # Modulo Unsigned Doubleword
 790
 791 X-Form
 792
 793 * modud RT,RA,RB
 794
 795 Pseudo-code:
 796
 797     dividend <- (RA)
 798     divisor  <- (RB)
 799     if (divisor = 0x0000_0000_0000_0000) then
 800         RT[0:63] <- undefined[0:63]
 801         overflow <- 1
 802     else
 803         RT       <- dividend % divisor
 804         overflow <- 0
 805
 806 Special Registers Altered:
 807
 808     None
 809