openpower/isa/fixedarith.mdwn

   1 # Add Immediate
   2
   3 D-Form
   4
   5 * addi RT,RA,SI
   6
   7 Pseudo-code:
   8
   9     if RA = 0 then RT <- EXTS(SI)
  10     else           RT <- (RA) + EXTS(SI)
  11
  12 Special Registers Altered:
  13
  14     None
  15
  16 # Add Immediate Shifted
  17
  18 D-Form
  19
  20 * addis RT,RA,SI
  21
  22 Pseudo-code:
  23
  24     if RA = 0 then RT <- EXTS(SI || [0]*16)
  25     else           RT <- (RA) + EXTS(SI || [0]*16)
  26
  27 Special Registers Altered:
  28
  29     None
  30
  31 # Add PC Immediate Shifted
  32
  33 DX-Form
  34
  35 * addpcis RT,D
  36
  37 Pseudo-code:
  38
  39     D <- d0||d1||d2
  40     RT <- NIA + EXTS(D || [0]*16)
  41
  42 Special Registers Altered:
  43
  44     None
  45
  46 # Add
  47
  48 XO-Form
  49
  50 * add RT,RA,RB (OE=0 Rc=0)
  51 * add.  RT,RA,RB (OE=0 Rc=1)
  52 * addo RT,RA,RB (OE=1 Rc=0)
  53 * addo.  RT,RA,RB (OE=1 Rc=1)
  54
  55 Pseudo-code:
  56
  57     RT <- (RA) + (RB)
  58
  59 Special Registers Altered:
  60
  61     CR0                     (if Rc=1)
  62     SO OV OV32             (if OE=1)
  63
  64 # Subtract From
  65
  66 XO-Form
  67
  68 * subf RT,RA,RB (OE=0 Rc=0)
  69 * subf.  RT,RA,RB (OE=0 Rc=1)
  70 * subfo RT,RA,RB (OE=1 Rc=0)
  71 * subfo.  RT,RA,RB (OE=1 Rc=1)
  72
  73 Pseudo-code:
  74
  75     RT <- ¬(RA) + (RB) + 1
  76
  77 Special Registers Altered:
  78
  79     CR0                     (if Rc=1)
  80     SO OV OV32             (if OE=1)
  81
  82 # Add Immediate Carrying
  83
  84 D-Form
  85
  86 * addic RT,RA,SI
  87
  88 Pseudo-code:
  89
  90     RT <- (RA) + EXTS(SI)
  91
  92 Special Registers Altered:
  93
  94     CA CA32
  95
  96 # Add Immediate Carrying and Record
  97
  98 D-Form
  99
 100 * addic. RT,RA,SI
 101
 102 Pseudo-code:
 103
 104     RT <- (RA) + EXTS(SI)
 105
 106 Special Registers Altered:
 107
 108     CR0 CA CA32
 109
 110 # Subtract From Immediate Carrying
 111
 112 D-Form
 113
 114 * subfic RT,RA,SI
 115
 116 Pseudo-code:
 117
 118     RT <- ¬(RA) + EXTS(SI) + 1
 119
 120 Special Registers Altered:
 121
 122     CA CA32
 123
 124 # Add Carrying
 125
 126 XO-Form
 127
 128 * addc RT,RA,RB (OE=0 Rc=0)
 129 * addc.  RT,RA,RB (OE=0 Rc=1)
 130 * addco RT,RA,RB (OE=1 Rc=0)
 131 * addco.  RT,RA,RB (OE=1 Rc=1)
 132
 133 Pseudo-code:
 134
 135     RT <- (RA) + (RB)
 136
 137 Special Registers Altered:
 138
 139     CA CA32
 140     CR0                     (if Rc=1)
 141     SO OV OV32             (if OE=1)
 142
 143 # Subtract From Carrying
 144
 145 XO-Form
 146
 147 * subfc RT,RA,RB (OE=0 Rc=0)
 148 * subfc.  RT,RA,RB (OE=0 Rc=1)
 149 * subfco RT,RA,RB (OE=1 Rc=0)
 150 * subfco.  RT,RA,RB (OE=1 Rc=1)
 151
 152 Pseudo-code:
 153
 154     RT <- ¬(RA) + (RB) + 1
 155
 156 Special Registers Altered:
 157
 158     CA CA32
 159     CR0                     (if Rc=1)
 160     SO OV OV32             (if OE=1)
 161
 162 # Add Extended
 163
 164 XO-Form
 165
 166 * adde RT,RA,RB (OE=0 Rc=0)
 167 * adde.  RT,RA,RB (OE=0 Rc=1)
 168 * addeo RT,RA,RB (OE=1 Rc=0)
 169 * addeo.  RT,RA,RB (OE=1 Rc=1)
 170
 171 Pseudo-code:
 172
 173     RT <- (RA) + (RB) + CA
 174
 175 Special Registers Altered:
 176
 177     CA CA32
 178     CR0                     (if Rc=1)
 179     SO OV OV32             (if OE=1)
 180
 181 # Subtract From Extended
 182
 183 XO-Form
 184
 185 * subfe RT,RA,RB (OE=0 Rc=0)
 186 * subfe.  RT,RA,RB (OE=0 Rc=1)
 187 * subfeo RT,RA,RB (OE=1 Rc=0)
 188 * subfeo.  RT,RA,RB (OE=1 Rc=1)
 189
 190 Pseudo-code:
 191
 192     RT <- ¬(RA) + (RB) + CA
 193
 194 Special Registers Altered:
 195
 196     CA CA32
 197     CR0                     (if Rc=1)
 198     SO OV OV32             (if OE=1)
 199
 200 # Add to Minus One Extended
 201
 202 XO-Form
 203
 204 * addme RT,RA (OE=0 Rc=0)
 205 * addme.  RT,RA (OE=0 Rc=1)
 206 * addmeo RT,RA (OE=1 Rc=0)
 207 * addmeo.  RT,RA (OE=1 Rc=1)
 208
 209 Pseudo-code:
 210
 211     RT <- (RA) + CA - 1
 212
 213 Special Registers Altered:
 214
 215     CA CA32
 216     CR0                     (if Rc=1)
 217     SO OV OV32             (if OE=1)
 218
 219 # Subtract From Minus One Extended
 220
 221 XO-Form
 222
 223 * subfme RT,RA (OE=0 Rc=0)
 224 * subfme.  RT,RA (OE=0 Rc=1)
 225 * subfmeo RT,RA (OE=1 Rc=0)
 226 * subfmeo.  RT,RA (OE=1 Rc=1)
 227
 228 Pseudo-code:
 229
 230     RT <- ¬(RA) + CA - 1
 231
 232 Special Registers Altered:
 233
 234     CA CA32
 235     CR0                     (if Rc=1)
 236     SO OV OV32             (if OE=1)
 237
 238 # Add Extended using alternate carry bit
 239
 240 Z23-Form
 241
 242 * addex RT,RA,RB,CY
 243
 244 Pseudo-code:
 245
 246     if CY=0 then RT <- (RA) + (RB) + OV
 247
 248 Special Registers Altered:
 249
 250     OV OV32                (if CY=0 )
 251
 252 # Subtract From Zero Extended
 253
 254 XO-Form
 255
 256 * subfze RT,RA (OE=0 Rc=0)
 257 * subfze.  RT,RA (OE=0 Rc=1)
 258 * subfzeo RT,RA (OE=1 Rc=0)
 259 * subfzeo.  RT,RA (OE=1 Rc=1)
 260
 261 Pseudo-code:
 262
 263     RT <- ¬(RA) + CA
 264
 265 Special Registers Altered:
 266
 267     CA CA32
 268     CR0                     (if Rc=1)
 269     SO OV OV32             (if OE=1)
 270
 271 # Add to Zero Extended
 272
 273 XO-Form
 274
 275 * addze RT,RA (OE=0 Rc=0)
 276 * addze.  RT,RA (OE=0 Rc=1)
 277 * addzeo RT,RA (OE=1 Rc=0)
 278 * addzeo.  RT,RA (OE=1 Rc=1)
 279
 280 Pseudo-code:
 281
 282     RT <- (RA) + CA
 283
 284 Special Registers Altered:
 285
 286     CA CA32
 287     CR0                     (if Rc=1)
 288     SO OV OV32             (if OE=1)
 289
 290 # Negate
 291
 292 XO-Form
 293
 294 * neg RT,RA (OE=0 Rc=0)
 295 * neg.  RT,RA (OE=0 Rc=1)
 296 * nego RT,RA (OE=1 Rc=0)
 297 * nego.  RT,RA (OE=1 Rc=1)
 298
 299 Pseudo-code:
 300
 301     RT <- ¬(RA) + 1
 302
 303 Special Registers Altered:
 304
 305     CR0                     (if Rc=1)
 306     SO OV OV32             (if OE=1)
 307
 308 # Multiply Low Immediate
 309
 310 D-Form
 311
 312 * mulli RT,RA,SI
 313
 314 Pseudo-code:
 315
 316     prod[0:127] <- MULS((RA), EXTS(SI))
 317     RT <- prod[64:127]
 318
 319 Special Registers Altered:
 320
 321     None
 322
 323 # Multiply High Word
 324
 325 XO-Form
 326
 327 * mulhw RT,RA,RB (Rc=0)
 328 * mulhw.  RT,RA,RB (Rc=1)
 329
 330 Pseudo-code:
 331
 332     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
 333     RT[32:63] <- prod[0:31]
 334     RT[0:31] <- prod[0:31]
 335
 336 Special Registers Altered:
 337
 338     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 339
 340 # Multiply Low Word
 341
 342 XO-Form
 343
 344 * mullw RT,RA,RB (OE=0 Rc=0)
 345 * mullw.  RT,RA,RB (OE=0 Rc=1)
 346 * mullwo RT,RA,RB (OE=1 Rc=0)
 347 * mullwo.  RT,RA,RB (OE=1 Rc=1)
 348
 349 Pseudo-code:
 350
 351     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
 352     RT <- prod
 353     if ((prod[32:64] != 0x0000_0000) &
 354         (prod[32:64] != 0xffff_ffff)) then
 355         overflow <- 1
 356     else
 357         overflow <- 0
 358
 359 Special Registers Altered:
 360
 361     CR0                     (if Rc=1)
 362     SO OV OV32             (if OE=1)
 363
 364 # Multiply High Word Unsigned
 365
 366 XO-Form
 367
 368 * mulhwu RT,RA,RB (Rc=0)
 369 * mulhwu.  RT,RA,RB (Rc=1)
 370
 371 Pseudo-code:
 372
 373     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 374     RT[32:63] <- prod[0:31]
 375     RT[0:31] <- prod[0:31]
 376
 377 Special Registers Altered:
 378
 379     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 380
 381 # Divide Word
 382
 383 XO-Form
 384
 385 * divw RT,RA,RB (OE=0 Rc=0)
 386 * divw.  RT,RA,RB (OE=0 Rc=1)
 387 * divwo RT,RA,RB (OE=1 Rc=0)
 388 * divwo.  RT,RA,RB (OE=1 Rc=1)
 389
 390 Pseudo-code:
 391
 392     dividend[0:31] <-  (RA)[32:63]
 393     divisor[0:31] <- (RB) [32:63]
 394     if (((dividend = 0x8000_0000) &
 395          (divisor = 0xffff_ffff)) |
 396          (divisor = 0x0000_0000)) then
 397         RT[0:63] <- undefined[0:63]
 398         overflow <- 1
 399     else
 400         RT[32:63] <- DIVS(dividend, divisor)
 401         RT[0:31] <- undefined[0:31]
 402         overflow <- 0
 403
 404 Special Registers Altered:
 405
 406     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 407     SO OV OV32                              (if OE=1)
 408
 409 # Divide Word Unsigned
 410
 411 XO-Form
 412
 413 * divwu RT,RA,RB (OE=0 Rc=0)
 414 * divwu.  RT,RA,RB (OE=0 Rc=1)
 415 * divwuo RT,RA,RB (OE=1 Rc=0)
 416 * divwuo.  RT,RA,RB (OE=1 Rc=1)
 417
 418 Pseudo-code:
 419
 420     dividend[0:31] <- (RA)[32:63]
 421     divisor[0:31] <- (RB)[32:63]
 422     if divisor != 0 then
 423         RT[32:63] <-  dividend / divisor
 424         RT[0:31] <- undefined[0:31]
 425         overflow <- 0
 426     else
 427         RT[0:63] <- undefined[0:63]
 428         overflow <- 1
 429
 430 Special Registers Altered:
 431
 432     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 433     SO OV OV32                              (if OE=1)
 434
 435 # Divide Word Extended
 436
 437 XO-Form
 438
 439 * divwe RT,RA,RB (OE=0 Rc=0)
 440 * divwe.  RT,RA,RB (OE=0 Rc=1)
 441 * divweo RT,RA,RB (OE=1 Rc=0)
 442 * divweo.  RT,RA,RB (OE=1 Rc=1)
 443
 444 Pseudo-code:
 445
 446     dividend[0:63] <- (RA)[32:63] || [0]*32
 447     divisor[0:63] <- [0]*32 || (RB)[32:63]
 448     if (divisor = 0x0000_0000_0000_0000) then
 449         overflow <- 1
 450     else
 451         result <- DIVS(dividend, divisor)
 452         if (result[32:63] = 0) then
 453             RT[32:63] <- result[0:31]
 454             RT[0:31] <- undefined[0:31]
 455             overflow <- 0
 456         else
 457             overflow <- 1
 458     if overflow = 1 then
 459         RT[0:63] <- undefined[0:63]
 460
 461 Special Registers Altered:
 462
 463     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 464     SO OV OV32                              (if OE=1)
 465
 466 # Divide Word Extended Unsigned
 467
 468 XO-Form
 469
 470 * divweu RT,RA,RB (OE=0 Rc=0)
 471 * divweu.  RT,RA,RB (OE=0 Rc=1)
 472 * divweuo RT,RA,RB (OE=1 Rc=0)
 473 * divweuo.  RT,RA,RB (OE=1 Rc=1)
 474
 475 Pseudo-code:
 476
 477     dividend[0:63] <- (RA)[32:63] || [0]*32
 478     divisor[0:63] <- [0]*32 || (RB)[32:63]
 479     if (divisor = 0x0000_0000_0000_0000) then
 480         overflow <- 1
 481     else
 482         result <- dividend /  divisor
 483         if (RA) < (RB) then
 484             RT[32:63] <- result[0:31]
 485             RT[0:31] <- undefined[0:31]
 486             overflow <- 0
 487         else
 488             overflow <- 1
 489     if overflow = 1 then
 490         RT[0:63] <- undefined[0:63]
 491
 492 Special Registers Altered:
 493
 494     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 495     SO OV OV32                              (if OE=1)
 496
 497 # Modulo Signed Word
 498
 499 X-Form
 500
 501 * modsw RT,RA,RB
 502
 503 Pseudo-code:
 504
 505     dividend[0:31] <- (RA)[32:63]
 506     divisor [0:31] <- (RB)[32:63]
 507     if (((dividend = 0x8000_0000) &
 508          (divisor = 0xffff_ffff)) |
 509          (divisor = 0x0000_0000)) then
 510         RT[0:63] <- undefined[0:63]
 511         overflow <- 1
 512     else
 513         RT[32:63] <- MODS(dividend, divisor)
 514         RT[0:31] <- undefined[0:31]
 515         overflow <- 0
 516
 517 Special Registers Altered:
 518
 519     None
 520
 521 # Modulo Unsigned Word
 522
 523 X-Form
 524
 525 * moduw RT,RA,RB
 526
 527 Pseudo-code:
 528
 529     dividend[0:31] <- (RA) [32:63]
 530     divisor [0:31] <- (RB) [32:63]
 531     if divisor = 0x0000_0000 then
 532         RT[0:63] <- undefined[0:63]
 533         overflow <- 1
 534     else
 535         RT[32:63] <- MODS(dividend, divisor)
 536         RT[0:31] <- undefined[0:31]
 537         overflow <- 0
 538
 539 Special Registers Altered:
 540
 541     None
 542
 543 # Deliver A Random Number
 544
 545 X-Form
 546
 547 * darn RT,L
 548
 549 Pseudo-code:
 550
 551     RT <- random(L)
 552
 553 Special Registers Altered:
 554
 555     none
 556
 557 # Multiply Low Doubleword
 558
 559 XO-Form
 560
 561 * mulld RT,RA,RB (OE=0 Rc=0)
 562 * mulld.  RT,RA,RB (OE=0 Rc=1)
 563 * mulldo RT,RA,RB (OE=1 Rc=0)
 564 * mulldo.  RT,RA,RB (OE=1 Rc=1)
 565
 566 Pseudo-code:
 567
 568     prod[0:127] <- MULS((RA), (RB))
 569     RT <- prod[64:127]
 570
 571 Special Registers Altered:
 572
 573     CR0                     (if Rc=1)
 574     SO OV OV32             (if OE=1)
 575
 576 # Multiply High Doubleword
 577
 578 XO-Form
 579
 580 * mulhd RT,RA,RB (Rc=0)
 581 * mulhd.  RT,RA,RB (Rc=1)
 582
 583 Pseudo-code:
 584
 585     prod[0:127] <- MULS((RA), (RB))
 586     RT <- prod[0:63]
 587
 588 Special Registers Altered:
 589
 590     CR0                     (if Rc=1)
 591
 592 # Multiply High Doubleword Unsigned
 593
 594 XO-Form
 595
 596 * mulhdu RT,RA,RB (Rc=0)
 597 * mulhdu.  RT,RA,RB (Rc=1)
 598
 599 Pseudo-code:
 600
 601     prod[0:127] <- (RA) *  (RB)
 602     RT <- prod[0:63]
 603
 604 Special Registers Altered:
 605
 606     CR0                    (if Rc=1)
 607
 608 # Multiply-Add High Doubleword VA-Form
 609
 610 VA-Form
 611
 612 * maddhd RT,RA.RB,RC
 613
 614 Pseudo-code:
 615
 616     prod[0:127] <- MULS((RA), (RB))
 617     sum[0:127] <- prod + EXTS(RC)
 618     RT <- sum[0:63]
 619
 620 Special Registers Altered:
 621
 622     None
 623
 624 # Multiply-Add High Doubleword Unsigned
 625
 626 VA-Form
 627
 628 * maddhdu RT,RA.RB,RC
 629
 630 Pseudo-code:
 631
 632     prod[0:127] <- (RA) * (RB)
 633     sum[0:127] <- prod + EXTZ(RC)
 634     RT <- sum[0:63]
 635
 636 Special Registers Altered:
 637
 638     None
 639
 640 # Multiply-Add Low Doubleword
 641
 642 VA-Form
 643
 644 * maddld RT,RA.RB,RC
 645
 646 Pseudo-code:
 647
 648     prod[0:127] <- MULS((RA), (RB))
 649     sum[0:127] <- prod + EXTS(RC)
 650     RT <- sum[64:127]
 651
 652 Special Registers Altered:
 653
 654     None
 655
 656 # Divide Doubleword
 657
 658 XO-Form
 659
 660 * divd RT,RA,RB (OE=0 Rc=0)
 661 * divd.  RT,RA,RB (OE=0 Rc=1)
 662 * divdo RT,RA,RB (OE=1 Rc=0)
 663 * divdo.  RT,RA,RB (OE=1 Rc=1)
 664
 665 Pseudo-code:
 666
 667     dividend[0:63] <- (RA)
 668     divisor[0:63] <- (RB)
 669     if (((dividend = 0x8000_0000_0000_0000) &
 670          (divisor = 0xffff_ffff_ffff_ffff)) |
 671          (divisor = 0x0000_0000_0000_0000)) then
 672         RT[0:63] <- undefined[0:63]
 673         overflow <- 1
 674     else
 675         RT <- DIVS(dividend, divisor)
 676         overflow <- 0
 677
 678 Special Registers Altered:
 679
 680     CR0                     (if Rc=1)
 681     SO OV OV32             (if OE=1)
 682
 683 # Divide Doubleword Unsigned
 684
 685 XO-Form
 686
 687 * divdu RT,RA,RB (OE=0 Rc=0)
 688 * divdu.  RT,RA,RB (OE=0 Rc=1)
 689 * divduo RT,RA,RB (OE=1 Rc=0)
 690 * divduo.  RT,RA,RB (OE=1 Rc=1)
 691
 692 Pseudo-code:
 693
 694     dividend[0:63] <- (RA)
 695     divisor[0:63] <- (RB)
 696     if (divisor = 0x0000_0000_0000_0000) then
 697         RT[0:63] <- undefined[0:63]
 698         overflow <- 1
 699     else
 700         RT <- dividend / divisor
 701         overflow <- 0
 702
 703 Special Registers Altered:
 704
 705     CR0                     (if Rc=1)
 706     SO OV OV32             (if OE=1)
 707
 708 # Divide Doubleword Extended
 709
 710 XO-Form
 711
 712 * divde RT,RA,RB (OE=0 Rc=0)
 713 * divde.  RT,RA,RB (OE=0 Rc=1)
 714 * divdeo RT,RA,RB (OE=1 Rc=0)
 715 * divdeo.  RT,RA,RB (OE=1 Rc=1)
 716
 717 Pseudo-code:
 718
 719     dividend[0:127] <-  (RA) || [0]*64
 720     divisor[0:127] <- [0*64] || (RB)
 721     if divisor = [0]*128 then
 722         overflow <- 1
 723     else
 724         result <- DIVS(dividend, divisor)
 725         if result[64:127] = 0x0000_0000_0000_0000 then
 726             RT <- result[63:127]
 727             overflow <- 0
 728         else
 729             overflow <- 1
 730     if overflow = 1 then
 731         RT[0:63] <- undefined[0:63]
 732
 733 Special Registers Altered:
 734
 735     CR0                     (if Rc=1)
 736     SO OV OV32             (if OE=1)
 737
 738 # Divide Doubleword Extended Unsigned
 739
 740 XO-Form
 741
 742 * divdeu RT,RA,RB (OE=0 Rc=0)
 743 * divdeu.  RT,RA,RB (OE=0 Rc=1)
 744 * divdeuo RT,RA,RB (OE=1 Rc=0)
 745 * divdeuo.  RT,RA,RB (OE=1 Rc=1)
 746
 747 Pseudo-code:
 748
 749     dividend[0:127] <-  (RA) || [0]*64
 750     divisor[0:127] <- [0*64] || (RB)
 751     if divisor = [0]*128 then
 752         overflow <- 1
 753     else
 754         result <- dividend /  divisor
 755         if (RA) < (RB) then
 756             RT <- result[63:127]
 757             overflow <- 0
 758         else
 759             overflow <- 1
 760     if overflow = 1 then
 761         RT[0:63] <- undefined[0:63]
 762
 763 Special Registers Altered:
 764
 765     CR0                     (if Rc=1)
 766     SO OV OV32             (if OE=1)
 767
 768 # Modulo Signed Doubleword
 769
 770 X-Form
 771
 772 * modsd RT,RA,RB
 773
 774 Pseudo-code:
 775
 776     dividend <- (RA)
 777     divisor  <- (RB)
 778     if (((dividend = 0x8000_0000_0000_0000) &
 779          (divisor = 0xffff_ffff_ffff_ffff)) |
 780          (divisor = 0x0000_0000_0000_0000)) then
 781         RT[0:63] <- undefined[0:63]
 782         overflow <- 1
 783     else
 784         RT       <- MODS(dividend, divisor)
 785         overflow <- 0
 786
 787 Special Registers Altered:
 788
 789     None
 790
 791 # Modulo Unsigned Doubleword
 792
 793 X-Form
 794
 795 * modud RT,RA,RB
 796
 797 Pseudo-code:
 798
 799     dividend <- (RA)
 800     divisor  <- (RB)
 801     if (divisor = 0x0000_0000_0000_0000) then
 802         RT[0:63] <- undefined[0:63]
 803         overflow <- 1
 804     else
 805         RT       <- dividend % divisor
 806         overflow <- 0
 807
 808 Special Registers Altered:
 809
 810     None
 811