openpower/isa/fixedarith.mdwn

   1 # Add Immediate
   2
   3 D-Form
   4
   5 * addi RT,RA,SI
   6
   7     if RA = 0 then RT <- EXTS(SI)
   8     else           RT <- (RA) + EXTS(SI)
   9
  10 Special Registers Altered:
  11
  12     None
  13
  14 # Add Immediate Shifted
  15
  16 D-Form
  17
  18 * addis RT,RA,SI
  19
  20     if RA = 0 then RT <- EXTS(SI || [0]*16)
  21     else           RT <- (RA) + EXTS(SI || [0]*16)
  22
  23 Special Registers Altered:
  24
  25     None
  26
  27 # Add PC Immediate Shifted
  28
  29 DX-Form
  30
  31 * addpcis RT,D
  32
  33     D <- d0||d1||d2
  34     RT <- NIA + EXTS(D || [0]*16)
  35
  36 Special Registers Altered:
  37
  38     None
  39
  40 # Add
  41
  42 XO-Form
  43
  44 * add RT,RA,RB (OE=0 Rc=0)
  45 * add.  RT,RA,RB (OE=0 Rc=1)
  46 * addo RT,RA,RB (OE=1 Rc=0)
  47 * addo.  RT,RA,RB (OE=1 Rc=1)
  48
  49     RT <- (RA) + (RB)
  50
  51 Special Registers Altered:
  52
  53     CR0                     (if Rc=1)
  54     SO OV OV32             (if OE=1)
  55
  56 # Subtract From
  57
  58 XO-Form
  59
  60 * subf RT,RA,RB (OE=0 Rc=0)
  61 * subf.  RT,RA,RB (OE=0 Rc=1)
  62 * subfo RT,RA,RB (OE=1 Rc=0)
  63 * subfo.  RT,RA,RB (OE=1 Rc=1)
  64
  65     RT <- ¬(RA) + (RB) + 1
  66
  67 Special Registers Altered:
  68
  69     CR0                     (if Rc=1)
  70     SO OV OV32             (if OE=1)
  71
  72 # Add Immediate Carrying
  73
  74 D-Form
  75
  76 * addic RT,RA,SI
  77
  78     RT <- (RA) + EXTS(SI)
  79
  80 Special Registers Altered:
  81
  82     CA CA32
  83
  84 # Add Immediate Carrying and Record
  85
  86 D-Form
  87
  88 * addic. RT,RA,SI
  89
  90     RT <- (RA) + EXTS(SI)
  91
  92 Special Registers Altered:
  93
  94     CR0 CA CA32
  95
  96 # Subtract From Immediate Carrying
  97
  98 D-Form
  99
 100 * subfic RT,RA,SI
 101
 102     RT <- ¬(RA) + EXTS(SI) + 1
 103
 104 Special Registers Altered:
 105
 106     CA CA32
 107
 108 # Add Carrying
 109
 110 XO-Form
 111
 112 * addc RT,RA,RB (OE=0 Rc=0)
 113 * addc.  RT,RA,RB (OE=0 Rc=1)
 114 * addco RT,RA,RB (OE=1 Rc=0)
 115 * addco.  RT,RA,RB (OE=1 Rc=1)
 116
 117     RT <- (RA) + (RB)
 118
 119 Special Registers Altered:
 120
 121     CA CA32
 122     CR0                     (if Rc=1)
 123     SO OV OV32             (if OE=1)
 124
 125 # Subtract From Carrying
 126
 127 XO-Form
 128
 129 * subfc RT,RA,RB (OE=0 Rc=0)
 130 * subfc.  RT,RA,RB (OE=0 Rc=1)
 131 * subfco RT,RA,RB (OE=1 Rc=0)
 132 * subfco.  RT,RA,RB (OE=1 Rc=1)
 133
 134     RT <- ¬(RA) + (RB) + 1
 135
 136 Special Registers Altered:
 137
 138     CA CA32
 139     CR0                     (if Rc=1)
 140     SO OV OV32             (if OE=1)
 141
 142 # Add Extended
 143
 144 XO-Form
 145
 146 * adde RT,RA,RB (OE=0 Rc=0)
 147 * adde.  RT,RA,RB (OE=0 Rc=1)
 148 * addeo RT,RA,RB (OE=1 Rc=0)
 149 * addeo.  RT,RA,RB (OE=1 Rc=1)
 150
 151     RT <- (RA) + (RB) + CA
 152
 153 Special Registers Altered:
 154
 155     CA CA32
 156     CR0                     (if Rc=1)
 157     SO OV OV32             (if OE=1)
 158
 159 # Subtract From Extended
 160
 161 XO-Form
 162
 163 * subfe RT,RA,RB (OE=0 Rc=0)
 164 * subfe.  RT,RA,RB (OE=0 Rc=1)
 165 * subfeo RT,RA,RB (OE=1 Rc=0)
 166 * subfeo.  RT,RA,RB (OE=1 Rc=1)
 167
 168     RT <- ¬(RA) + (RB) + CA
 169
 170 Special Registers Altered:
 171
 172     CA CA32
 173     CR0                     (if Rc=1)
 174     SO OV OV32             (if OE=1)
 175
 176 # Add to Minus One Extended
 177
 178 XO-Form
 179
 180 * addme RT,RA (OE=0 Rc=0)
 181 * addme.  RT,RA (OE=0 Rc=1)
 182 * addmeo RT,RA (OE=1 Rc=0)
 183 * addmeo.  RT,RA (OE=1 Rc=1)
 184
 185     RT <- (RA) + CA - 1
 186
 187 Special Registers Altered:
 188
 189     CA CA32
 190     CR0                     (if Rc=1)
 191     SO OV OV32             (if OE=1)
 192
 193 # Subtract From Minus One Extended
 194
 195 XO-Form
 196
 197 * subfme RT,RA (OE=0 Rc=0)
 198 * subfme.  RT,RA (OE=0 Rc=1)
 199 * subfmeo RT,RA (OE=1 Rc=0)
 200 * subfmeo.  RT,RA (OE=1 Rc=1)
 201
 202     RT <- ¬(RA) + CA - 1
 203
 204 Special Registers Altered:
 205
 206     CA CA32
 207     CR0                     (if Rc=1)
 208     SO OV OV32             (if OE=1)
 209
 210 # Add Extended using alternate carry bit
 211
 212 Z23-Form
 213
 214 * addex RT,RA,RB,CY
 215
 216     if CY=0 then RT <- (RA) + (RB) + OV
 217
 218 Special Registers Altered:
 219
 220     OV OV32                (if CY=0 )
 221
 222 # Subtract From Zero Extended
 223
 224 XO-Form
 225
 226 * subfze RT,RA (OE=0 Rc=0)
 227 * subfze.  RT,RA (OE=0 Rc=1)
 228 * subfzeo RT,RA (OE=1 Rc=0)
 229 * subfzeo.  RT,RA (OE=1 Rc=1)
 230
 231     RT <- ¬(RA) + CA
 232
 233 Special Registers Altered:
 234
 235     CA CA32
 236     CR0                     (if Rc=1)
 237     SO OV OV32             (if OE=1)
 238
 239 # Add to Zero Extended
 240
 241 XO-Form
 242
 243 * addze RT,RA (OE=0 Rc=0)
 244 * addze.  RT,RA (OE=0 Rc=1)
 245 * addzeo RT,RA (OE=1 Rc=0)
 246 * addzeo.  RT,RA (OE=1 Rc=1)
 247
 248     RT <- (RA) + CA
 249
 250 Special Registers Altered:
 251
 252     CA CA32
 253     CR0                     (if Rc=1)
 254     SO OV OV32             (if OE=1)
 255
 256 # Negate
 257
 258 XO-Form
 259
 260 * neg RT,RA (OE=0 Rc=0)
 261 * neg.  RT,RA (OE=0 Rc=1)
 262 * nego RT,RA (OE=1 Rc=0)
 263 * nego.  RT,RA (OE=1 Rc=1)
 264
 265     RT <- ¬(RA) + 1
 266
 267 Special Registers Altered:
 268
 269     CR0                     (if Rc=1)
 270     SO OV OV32             (if OE=1)
 271
 272 # Multiply Low Immediate
 273
 274 D-Form
 275
 276 * mulli RT,RA,SI
 277
 278     prod[0:127] <- (RA) * EXTS(SI)
 279     RT <- prod[64:127]
 280
 281 Special Registers Altered:
 282
 283     None
 284
 285 # Multiply High Word
 286
 287 XO-Form
 288
 289 * mulhw RT,RA,RB (Rc=0)
 290 * mulhw.  RT,RA,RB (Rc=1)
 291
 292     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 293     RT[32:63] <- prod[0:31]
 294     RT[0:31] <- undefined[0:31]
 295
 296 Special Registers Altered:
 297
 298     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 299
 300 # Multiply Low Word
 301
 302 XO-Form
 303
 304 * mullw RT,RA,RB (OE=0 Rc=0)
 305 * mullw.  RT,RA,RB (OE=0 Rc=1)
 306 * mullwo RT,RA,RB (OE=1 Rc=0)
 307 * mullwo.  RT,RA,RB (OE=1 Rc=1)
 308
 309     RT <- (RA)[32:63] * (RB)[32:63]
 310
 311 Special Registers Altered:
 312
 313     CR0                     (if Rc=1)
 314     SO OV OV32             (if OE=1)
 315
 316 # Multiply High Word Unsigned
 317
 318 XO-Form
 319
 320 * mulhwu RT,RA,RB (Rc=0)
 321 * mulhwu.  RT,RA,RB (Rc=1)
 322
 323     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
 324     RT[32:63] <- prod[0:31]
 325     RT[0:31] <- undefined[0:31]
 326
 327 Special Registers Altered:
 328
 329     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 330
 331 # Divide Word
 332
 333 XO-Form
 334
 335 * divw RT,RA,RB (OE=0 Rc=0)
 336 * divw.  RT,RA,RB (OE=0 Rc=1)
 337 * divwo RT,RA,RB (OE=1 Rc=0)
 338 * divwo.  RT,RA,RB (OE=1 Rc=1)
 339
 340     dividend[0:31] <-  (RA)[32:63]
 341     divisor[0:31] <- (RB) [32:63]
 342     if (((dividend = 0x8000_0000) &
 343          (divisor = 0xffff_ffff)) |
 344          (divisor = 0x0000_0000)) then
 345         RT[0:63] <- undefined[0:63]
 346         overflow <- 1
 347     else
 348         RT[32:63] <- dividend / divisor
 349         RT[0:31] <- undefined[0:31]
 350         overflow <- 0
 351
 352 Special Registers Altered:
 353
 354     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 355     SO OV OV32                              (if OE=1)
 356
 357 # Divide Word Unsigned
 358
 359 XO-Form
 360
 361 * divwu RT,RA,RB (OE=0 Rc=0)
 362 * divwu.  RT,RA,RB (OE=0 Rc=1)
 363 * divwuo RT,RA,RB (OE=1 Rc=0)
 364 * divwuo.  RT,RA,RB (OE=1 Rc=1)
 365
 366     dividend[0:31] <- (RA)[32:63]
 367     divisor[0:31] <- (RB)[32:63]
 368     if divisor != 0 then
 369         RT[32:63] <-  dividend / divisor
 370         RT[0:31] <- undefined[0:31]
 371         overflow <- 0
 372     else
 373         RT[0:63] <- undefined[0:63]
 374         overflow <- 1
 375
 376 Special Registers Altered:
 377
 378     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 379     SO OV OV32                              (if OE=1)
 380
 381 # Divide Word Extended
 382
 383 XO-Form
 384
 385 * divwe RT,RA,RB (OE=0 Rc=0)
 386 * divwe.  RT,RA,RB (OE=0 Rc=1)
 387 * divweo RT,RA,RB (OE=1 Rc=0)
 388 * divweo.  RT,RA,RB (OE=1 Rc=1)
 389
 390     dividend[0:63] <- (RA)[32:63] || [0]*32
 391     divisor[0:63] <- (RB)[32:63] || [0]*32
 392     if (divisor = 0x0000_0000_0000_0000) then
 393         overflow <- 1
 394     else
 395         result <- dividend /  divisor
 396         if (result[32:63] = 0) then
 397             RT[32:63] <- result[0:31]
 398             RT[0:31] <- undefined[0:31]
 399             overflow <- 0
 400         else
 401             overflow <- 1
 402     if overflow = 1 then
 403         RT[0:63] <- undefined[0:63]
 404
 405 Special Registers Altered:
 406
 407     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 408     SO OV OV32                              (if OE=1)
 409
 410 # Divide Word Extended Unsigned
 411
 412 XO-Form
 413
 414 * divweu RT,RA,RB (OE=0 Rc=0)
 415 * divweu.  RT,RA,RB (OE=0 Rc=1)
 416 * divweuo RT,RA,RB (OE=1 Rc=0)
 417 * divweuo.  RT,RA,RB (OE=1 Rc=1)
 418
 419     dividend[0:63] <- (RA)[32:63] || [0]*32
 420     divisor[0:63] <- (RB)[32:63] || [0]*32
 421     if (divisor = 0x0000_0000_0000_0000) then
 422         overflow <- 1
 423     else
 424         result <- dividend /  divisor
 425         if (RA) < (RB) then
 426             RT[32:63] <- result[0:31]
 427             RT[0:31] <- undefined[0:31]
 428             overflow <- 0
 429         else
 430             overflow <- 1
 431     if overflow = 1 then
 432         RT[0:63] <- undefined[0:63]
 433
 434 Special Registers Altered:
 435
 436     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 437     SO OV OV32                              (if OE=1)
 438
 439 # Modulo Signed Word
 440
 441 X-Form
 442
 443 * modsw RT,RA,RB
 444
 445     dividend[0:31] <- (RA)[32:63]
 446     divisor [0:31] <- (RB)[32:63]
 447     if (((dividend = 0x8000_0000) &
 448          (divisor = 0xffff_ffff)) |
 449          (divisor = 0x0000_0000)) then
 450         RT[0:63] <- undefined[0:63]
 451         overflow <- 1
 452     else
 453         RT[32:63] <- dividend % divisor
 454         RT[0:31] <- undefined[0:31]
 455         overflow <- 0
 456
 457 Special Registers Altered:
 458
 459     None
 460
 461 # Modulo Unsigned Word
 462
 463 X-Form
 464
 465 * moduw RT,RA,RB
 466
 467     dividend[0:31] <- (RA) [32:63]
 468     divisor [0:31] <- (RB) [32:63]
 469     if divisor = 0x0000_0000 then
 470         RT[0:63] <- undefined[0:63]
 471         overflow <- 1
 472     else
 473         RT[32:63] <- dividend % divisor
 474         RT[0:31] <- undefined[0:31]
 475         overflow <- 0
 476
 477 Special Registers Altered:
 478
 479     None
 480
 481 # Deliver A Random Number
 482
 483 X-Form
 484
 485 * darn RT,L
 486
 487     RT <- random(L)
 488
 489 Special Registers Altered:
 490
 491     none
 492
 493 # Multiply Low Doubleword
 494
 495 XO-Form
 496
 497 * mulld RT,RA,RB (OE=0 Rc=0)
 498 * mulld.  RT,RA,RB (OE=0 Rc=1)
 499 * mulldo RT,RA,RB (OE=1 Rc=0)
 500 * mulldo.  RT,RA,RB (OE=1 Rc=1)
 501
 502     prod[0:127] <- (RA) * (RB)
 503     RT <- prod[64:127]
 504
 505 Special Registers Altered:
 506
 507     CR0                     (if Rc=1)
 508     SO OV OV32             (if OE=1)
 509
 510 # Multiply High Doubleword
 511
 512 XO-Form
 513
 514 * mulhd RT,RA,RB (Rc=0)
 515 * mulhd.  RT,RA,RB (Rc=1)
 516
 517     prod[0:127] <- (RA) *  (RB)
 518     RT <- prod[0:63]
 519
 520 Special Registers Altered:
 521
 522     CR0                     (if Rc=1)
 523
 524 # Multiply High Doubleword Unsigned
 525
 526 XO-Form
 527
 528 * mulhdu RT,RA,RB (Rc=0)
 529 * mulhdu.  RT,RA,RB (Rc=1)
 530
 531     prod[0:127] <- (RA) *  (RB)
 532     RT <- prod[0:63]
 533
 534 Special Registers Altered:
 535
 536     CR0                    (if Rc=1)
 537
 538 # Multiply-Add High Doubleword VA-Form
 539
 540 VA-Form
 541
 542 * maddhd RT,RA.RB,RC
 543
 544     prod[0:127] <- (RA) * (RB)
 545     sum[0:127] <- prod + EXTS(RC)
 546     RT <- sum[0:63]
 547
 548 Special Registers Altered:
 549
 550     None
 551
 552 # Multiply-Add High Doubleword Unsigned
 553
 554 VA-Form
 555
 556 * maddhdu RT,RA.RB,RC
 557
 558     prod[0:127] <- (RA) * (RB)
 559     sum[0:127] <- prod + EXTZ(RC)
 560     RT <- sum[0:63]
 561
 562 Special Registers Altered:
 563
 564     None
 565
 566 # Multiply-Add Low Doubleword
 567
 568 VA-Form
 569
 570 * maddld RT,RA.RB,RC
 571
 572     prod[0:127] <- (RA) * (RB)
 573     sum[0:127] <- prod + EXTS(RC)
 574     RT <- sum[64:127]
 575
 576 Special Registers Altered:
 577
 578     None
 579
 580 # Divide Doubleword
 581
 582 XO-Form
 583
 584 * divd RT,RA,RB (OE=0 Rc=0)
 585 * divd.  RT,RA,RB (OE=0 Rc=1)
 586 * divdo RT,RA,RB (OE=1 Rc=0)
 587 * divdo.  RT,RA,RB (OE=1 Rc=1)
 588
 589     dividend[0:63] <- (RA)
 590     divisor[0:63] <- (RB)
 591     if (((dividend = 0x8000_0000_0000_0000) &
 592          (divisor = 0xffff_ffff_ffff_ffff)) |
 593          (divisor = 0x0000_0000_0000_0000)) then
 594         RT[0:63] <- undefined[0:63]
 595         overflow <- 1
 596     else
 597         RT <- dividend / divisor
 598         overflow <- 0
 599
 600 Special Registers Altered:
 601
 602     CR0                     (if Rc=1)
 603     SO OV OV32             (if OE=1)
 604
 605 # Divide Doubleword Unsigned
 606
 607 XO-Form
 608
 609 * divdu RT,RA,RB (OE=0 Rc=0)
 610 * divdu.  RT,RA,RB (OE=0 Rc=1)
 611 * divduo RT,RA,RB (OE=1 Rc=0)
 612 * divduo.  RT,RA,RB (OE=1 Rc=1)
 613
 614     dividend[0:63] <- (RA)
 615     divisor[0:63] <- (RB)
 616     if (divisor = 0x0000_0000_0000_0000) then
 617         RT[0:63] <- undefined[0:63]
 618         overflow <- 1
 619     else
 620         RT <- dividend / divisor
 621         overflow <- 0
 622
 623 Special Registers Altered:
 624
 625     CR0                     (if Rc=1)
 626     SO OV OV32             (if OE=1)
 627
 628 # Divide Doubleword Extended
 629
 630 XO-Form
 631
 632 * divde RT,RA,RB (OE=0 Rc=0)
 633 * divde.  RT,RA,RB (OE=0 Rc=1)
 634 * divdeo RT,RA,RB (OE=1 Rc=0)
 635 * divdeo.  RT,RA,RB (OE=1 Rc=1)
 636
 637     dividend[0:127] <-  (RA) || [0]*64
 638     divisor[0:127] <- (RB) || [0*64]
 639     if divisor = [0]*128 then
 640         overflow <- 1
 641     else
 642         result <- dividend /  divisor
 643         if result[64:127] = 0x0000_0000_0000_0000 then
 644             RT <- result[63:127]
 645             overflow <- 0
 646         else
 647             overflow <- 1
 648     if overflow = 1 then
 649         RT[0:63] <- undefined[0:63]
 650
 651 Special Registers Altered:
 652
 653     CR0                     (if Rc=1)
 654     SO OV OV32             (if OE=1)
 655
 656 # Divide Doubleword Extended Unsigned
 657
 658 XO-Form
 659
 660 * divdeu RT,RA,RB (OE=0 Rc=0)
 661 * divdeu.  RT,RA,RB (OE=0 Rc=1)
 662 * divdeuo RT,RA,RB (OE=1 Rc=0)
 663 * divdeuo.  RT,RA,RB (OE=1 Rc=1)
 664
 665     dividend[0:127] <-  (RA) || [0]*64
 666     divisor[0:127] <- (RB) || [0*64]
 667     if divisor = [0]*128 then
 668         overflow <- 1
 669     else
 670         result <- dividend /  divisor
 671         if (RA) < (RB) then
 672             RT <- result[63:127]
 673             overflow <- 0
 674         else
 675             overflow <- 1
 676     if overflow = 1 then
 677         RT[0:63] <- undefined[0:63]
 678
 679 Special Registers Altered:
 680
 681     CR0                     (if Rc=1)
 682     SO OV OV32             (if OE=1)
 683
 684 # Modulo Signed Doubleword
 685
 686 X-Form
 687
 688 * modsd RT,RA,RB
 689
 690     dividend <- (RA)
 691     divisor  <- (RB)
 692     if (((dividend = 0x8000_0000_0000_0000) &
 693          (divisor = 0xffff_ffff_ffff_ffff)) |
 694          (divisor = 0x0000_0000_0000_0000)) then
 695         RT[0:63] <- undefined[0:63]
 696         overflow <- 1
 697     else
 698         RT       <- dividend % divisor
 699         overflow <- 0
 700
 701 Special Registers Altered:
 702
 703     None
 704
 705 # Modulo Unsigned Doubleword
 706
 707 X-Form
 708
 709 * modud RT,RA,RB
 710
 711     dividend <- (RA)
 712     divisor  <- (RB)
 713     if (divisor = 0x0000_0000_0000_0000) then
 714         RT[0:63] <- undefined[0:63]
 715         overflow <- 1
 716     else
 717         RT       <- dividend % divisor
 718         overflow <- 0
 719
 720 Special Registers Altered:
 721
 722     None
 723