9 if RA = 0 then RT <- EXTS(SI)
10 else RT <- (RA) + EXTS(SI)
12 Special Registers Altered:
16 # Add Immediate Shifted
24 if RA = 0 then RT <- EXTS(SI || [0]*16)
25 else RT <- (RA) + EXTS(SI || [0]*16)
27 Special Registers Altered:
31 # Add PC Immediate Shifted
40 RT <- NIA + EXTS(D || [0]*16)
42 Special Registers Altered:
50 * add RT,RA,RB (OE=0 Rc=0)
51 * add. RT,RA,RB (OE=0 Rc=1)
52 * addo RT,RA,RB (OE=1 Rc=0)
53 * addo. RT,RA,RB (OE=1 Rc=1)
59 Special Registers Altered:
68 * subf RT,RA,RB (OE=0 Rc=0)
69 * subf. RT,RA,RB (OE=0 Rc=1)
70 * subfo RT,RA,RB (OE=1 Rc=0)
71 * subfo. RT,RA,RB (OE=1 Rc=1)
75 RT <- ¬(RA) + (RB) + 1
77 Special Registers Altered:
82 # Add Immediate Carrying
92 Special Registers Altered:
96 # Add Immediate Carrying and Record
104 RT <- (RA) + EXTS(SI)
106 Special Registers Altered:
110 # Subtract From Immediate Carrying
118 RT <- ¬(RA) + EXTS(SI) + 1
120 Special Registers Altered:
128 * addc RT,RA,RB (OE=0 Rc=0)
129 * addc. RT,RA,RB (OE=0 Rc=1)
130 * addco RT,RA,RB (OE=1 Rc=0)
131 * addco. RT,RA,RB (OE=1 Rc=1)
137 Special Registers Altered:
143 # Subtract From Carrying
147 * subfc RT,RA,RB (OE=0 Rc=0)
148 * subfc. RT,RA,RB (OE=0 Rc=1)
149 * subfco RT,RA,RB (OE=1 Rc=0)
150 * subfco. RT,RA,RB (OE=1 Rc=1)
154 RT <- ¬(RA) + (RB) + 1
156 Special Registers Altered:
166 * adde RT,RA,RB (OE=0 Rc=0)
167 * adde. RT,RA,RB (OE=0 Rc=1)
168 * addeo RT,RA,RB (OE=1 Rc=0)
169 * addeo. RT,RA,RB (OE=1 Rc=1)
173 RT <- (RA) + (RB) + CA
175 Special Registers Altered:
181 # Subtract From Extended
185 * subfe RT,RA,RB (OE=0 Rc=0)
186 * subfe. RT,RA,RB (OE=0 Rc=1)
187 * subfeo RT,RA,RB (OE=1 Rc=0)
188 * subfeo. RT,RA,RB (OE=1 Rc=1)
192 RT <- ¬(RA) + (RB) + CA
194 Special Registers Altered:
200 # Add to Minus One Extended
204 * addme RT,RA (OE=0 Rc=0)
205 * addme. RT,RA (OE=0 Rc=1)
206 * addmeo RT,RA (OE=1 Rc=0)
207 * addmeo. RT,RA (OE=1 Rc=1)
213 Special Registers Altered:
219 # Subtract From Minus One Extended
223 * subfme RT,RA (OE=0 Rc=0)
224 * subfme. RT,RA (OE=0 Rc=1)
225 * subfmeo RT,RA (OE=1 Rc=0)
226 * subfmeo. RT,RA (OE=1 Rc=1)
232 Special Registers Altered:
238 # Add Extended using alternate carry bit
246 if CY=0 then RT <- (RA) + (RB) + OV
248 Special Registers Altered:
252 # Subtract From Zero Extended
256 * subfze RT,RA (OE=0 Rc=0)
257 * subfze. RT,RA (OE=0 Rc=1)
258 * subfzeo RT,RA (OE=1 Rc=0)
259 * subfzeo. RT,RA (OE=1 Rc=1)
265 Special Registers Altered:
271 # Add to Zero Extended
275 * addze RT,RA (OE=0 Rc=0)
276 * addze. RT,RA (OE=0 Rc=1)
277 * addzeo RT,RA (OE=1 Rc=0)
278 * addzeo. RT,RA (OE=1 Rc=1)
284 Special Registers Altered:
294 * neg RT,RA (OE=0 Rc=0)
295 * neg. RT,RA (OE=0 Rc=1)
296 * nego RT,RA (OE=1 Rc=0)
297 * nego. RT,RA (OE=1 Rc=1)
303 Special Registers Altered:
308 # Multiply Low Immediate
316 prod[0:127] <- MULS((RA), EXTS(SI))
319 Special Registers Altered:
327 * mulhw RT,RA,RB (Rc=0)
328 * mulhw. RT,RA,RB (Rc=1)
332 prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
333 RT[32:63] <- prod[0:31]
334 RT[0:31] <- prod[0:31]
336 Special Registers Altered:
338 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
344 * mullw RT,RA,RB (OE=0 Rc=0)
345 * mullw. RT,RA,RB (OE=0 Rc=1)
346 * mullwo RT,RA,RB (OE=1 Rc=0)
347 * mullwo. RT,RA,RB (OE=1 Rc=1)
351 prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
353 overflow <- ((prod[0:32] != 0x0_0000_0000) &
354 (prod[0:32] != 0x1_ffff_ffff))
356 Special Registers Altered:
361 # Multiply High Word Unsigned
365 * mulhwu RT,RA,RB (Rc=0)
366 * mulhwu. RT,RA,RB (Rc=1)
370 prod[0:63] <- (RA)[32:63] * (RB)[32:63]
371 RT[32:63] <- prod[0:31]
372 RT[0:31] <- prod[0:31]
374 Special Registers Altered:
376 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
382 * divw RT,RA,RB (OE=0 Rc=0)
383 * divw. RT,RA,RB (OE=0 Rc=1)
384 * divwo RT,RA,RB (OE=1 Rc=0)
385 * divwo. RT,RA,RB (OE=1 Rc=1)
389 dividend[0:31] <- (RA)[32:63]
390 divisor[0:31] <- (RB) [32:63]
391 if (((dividend = 0x8000_0000) &
392 (divisor = 0xffff_ffff)) |
393 (divisor = 0x0000_0000)) then
394 RT[0:63] <- undefined[0:63]
397 RT[32:63] <- DIVS(dividend, divisor)
398 RT[0:31] <- undefined[0:31]
401 Special Registers Altered:
403 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
406 # Divide Word Unsigned
410 * divwu RT,RA,RB (OE=0 Rc=0)
411 * divwu. RT,RA,RB (OE=0 Rc=1)
412 * divwuo RT,RA,RB (OE=1 Rc=0)
413 * divwuo. RT,RA,RB (OE=1 Rc=1)
417 dividend[0:31] <- (RA)[32:63]
418 divisor[0:31] <- (RB)[32:63]
420 RT[32:63] <- dividend / divisor
421 RT[0:31] <- undefined[0:31]
424 RT[0:63] <- undefined[0:63]
427 Special Registers Altered:
429 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
432 # Divide Word Extended
436 * divwe RT,RA,RB (OE=0 Rc=0)
437 * divwe. RT,RA,RB (OE=0 Rc=1)
438 * divweo RT,RA,RB (OE=1 Rc=0)
439 * divweo. RT,RA,RB (OE=1 Rc=1)
443 dividend[0:63] <- (RA)[32:63] || [0]*32
444 divisor[0:63] <- [0]*32 || (RB)[32:63]
445 if (divisor = 0x0000_0000_0000_0000) then
448 result <- DIVS(dividend, divisor)
449 if (result[32:63] = 0) then
450 RT[32:63] <- result[0:31]
451 RT[0:31] <- undefined[0:31]
456 RT[0:63] <- undefined[0:63]
458 Special Registers Altered:
460 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
463 # Divide Word Extended Unsigned
467 * divweu RT,RA,RB (OE=0 Rc=0)
468 * divweu. RT,RA,RB (OE=0 Rc=1)
469 * divweuo RT,RA,RB (OE=1 Rc=0)
470 * divweuo. RT,RA,RB (OE=1 Rc=1)
474 dividend[0:63] <- (RA)[32:63] || [0]*32
475 divisor[0:63] <- [0]*32 || (RB)[32:63]
476 if (divisor = 0x0000_0000_0000_0000) then
479 result <- dividend / divisor
481 RT[32:63] <- result[0:31]
482 RT[0:31] <- undefined[0:31]
487 RT[0:63] <- undefined[0:63]
489 Special Registers Altered:
491 CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
502 dividend[0:31] <- (RA)[32:63]
503 divisor [0:31] <- (RB)[32:63]
504 if (((dividend = 0x8000_0000) &
505 (divisor = 0xffff_ffff)) |
506 (divisor = 0x0000_0000)) then
507 RT[0:63] <- undefined[0:63]
510 RT[32:63] <- MODS(dividend, divisor)
511 RT[0:31] <- undefined[0:31]
514 Special Registers Altered:
518 # Modulo Unsigned Word
526 dividend[0:31] <- (RA) [32:63]
527 divisor [0:31] <- (RB) [32:63]
528 if divisor = 0x0000_0000 then
529 RT[0:63] <- undefined[0:63]
532 RT[32:63] <- MODS(dividend, divisor)
533 RT[0:31] <- undefined[0:31]
536 Special Registers Altered:
540 # Deliver A Random Number
550 Special Registers Altered:
554 # Multiply Low Doubleword
558 * mulld RT,RA,RB (OE=0 Rc=0)
559 * mulld. RT,RA,RB (OE=0 Rc=1)
560 * mulldo RT,RA,RB (OE=1 Rc=0)
561 * mulldo. RT,RA,RB (OE=1 Rc=1)
565 prod[0:127] <- MULS((RA), (RB))
567 overflow <- ((prod[0:64] != 0x0_0000_0000_0000_0000) &
568 (prod[0:64] != 0x1_ffff_ffff_ffff_ffff))
570 Special Registers Altered:
575 # Multiply High Doubleword
579 * mulhd RT,RA,RB (Rc=0)
580 * mulhd. RT,RA,RB (Rc=1)
584 prod[0:127] <- MULS((RA), (RB))
587 Special Registers Altered:
591 # Multiply High Doubleword Unsigned
595 * mulhdu RT,RA,RB (Rc=0)
596 * mulhdu. RT,RA,RB (Rc=1)
600 prod[0:127] <- (RA) * (RB)
603 Special Registers Altered:
607 # Multiply-Add High Doubleword VA-Form
615 prod[0:127] <- MULS((RA), (RB))
616 sum[0:127] <- prod + EXTS(RC)
619 Special Registers Altered:
623 # Multiply-Add High Doubleword Unsigned
627 * maddhdu RT,RA.RB,RC
631 prod[0:127] <- (RA) * (RB)
632 sum[0:127] <- prod + EXTZ(RC)
635 Special Registers Altered:
639 # Multiply-Add Low Doubleword
647 prod[0:127] <- MULS((RA), (RB))
648 sum[0:127] <- prod + EXTS(RC)
651 Special Registers Altered:
659 * divd RT,RA,RB (OE=0 Rc=0)
660 * divd. RT,RA,RB (OE=0 Rc=1)
661 * divdo RT,RA,RB (OE=1 Rc=0)
662 * divdo. RT,RA,RB (OE=1 Rc=1)
666 dividend[0:63] <- (RA)
667 divisor[0:63] <- (RB)
668 if (((dividend = 0x8000_0000_0000_0000) &
669 (divisor = 0xffff_ffff_ffff_ffff)) |
670 (divisor = 0x0000_0000_0000_0000)) then
671 RT[0:63] <- undefined[0:63]
674 RT <- DIVS(dividend, divisor)
677 Special Registers Altered:
682 # Divide Doubleword Unsigned
686 * divdu RT,RA,RB (OE=0 Rc=0)
687 * divdu. RT,RA,RB (OE=0 Rc=1)
688 * divduo RT,RA,RB (OE=1 Rc=0)
689 * divduo. RT,RA,RB (OE=1 Rc=1)
693 dividend[0:63] <- (RA)
694 divisor[0:63] <- (RB)
695 if (divisor = 0x0000_0000_0000_0000) then
696 RT[0:63] <- undefined[0:63]
699 RT <- dividend / divisor
702 Special Registers Altered:
707 # Divide Doubleword Extended
711 * divde RT,RA,RB (OE=0 Rc=0)
712 * divde. RT,RA,RB (OE=0 Rc=1)
713 * divdeo RT,RA,RB (OE=1 Rc=0)
714 * divdeo. RT,RA,RB (OE=1 Rc=1)
718 dividend[0:127] <- (RA) || [0]*64
719 divisor[0:127] <- [0]*64 || (RB)
720 if divisor = [0]*128 then
723 result <- DIVS(dividend, divisor)
724 if result[64:127] = 0x0000_0000_0000_0000 then
730 RT[0:63] <- undefined[0:63]
732 Special Registers Altered:
737 # Divide Doubleword Extended Unsigned
741 * divdeu RT,RA,RB (OE=0 Rc=0)
742 * divdeu. RT,RA,RB (OE=0 Rc=1)
743 * divdeuo RT,RA,RB (OE=1 Rc=0)
744 * divdeuo. RT,RA,RB (OE=1 Rc=1)
748 dividend[0:127] <- (RA) || [0]*64
749 divisor[0:127] <- [0]*64 || (RB)
750 if divisor = [0]*128 then
753 result <- dividend / divisor
760 RT[0:63] <- undefined[0:63]
762 Special Registers Altered:
767 # Modulo Signed Doubleword
777 if (((dividend = 0x8000_0000_0000_0000) &
778 (divisor = 0xffff_ffff_ffff_ffff)) |
779 (divisor = 0x0000_0000_0000_0000)) then
780 RT[0:63] <- undefined[0:63]
783 RT <- MODS(dividend, divisor)
786 Special Registers Altered:
790 # Modulo Unsigned Doubleword
800 if (divisor = 0x0000_0000_0000_0000) then
801 RT[0:63] <- undefined[0:63]
804 RT <- dividend % divisor
807 Special Registers Altered: