openpower/isa/fixedldstcache.mdwn

   1 # Load Byte and Zero Caching Inhibited Indexed
   2
   3 X-Form
   4
   5 * lbzcix RT,RA,RB
   6
   7 Pseudo-code:
   8
   9     b <- (RA|0)
  10     EA <- b + (RB)
  11     RT <- [0] * 56 || MEM(EA, 1)
  12
  13 Special Registers Altered:
  14
  15     None
  16
  17 # Load Halfword and Zero Caching Inhibited Indexed
  18
  19 X-Form
  20
  21 * lhzcix RT,RA,RB
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + (RB)
  27     RT <- [0] * 48 || MEM(EA, 2)
  28
  29 Special Registers Altered:
  30
  31     None
  32
  33 # Load Word and Zero Caching Inhibited Indexed
  34
  35 X-Form
  36
  37 * lwzcix RT,RA,RB
  38
  39 Pseudo-code:
  40
  41     b <- (RA|0)
  42     EA <- b + (RB)
  43     RT <- [0] * 32 || MEM(EA, 4)
  44
  45 Special Registers Altered:
  46
  47     None
  48
  49 # Load Doubleword Caching Inhibited Indexed
  50
  51 X-Form
  52
  53 * ldcix RT,RA,RB
  54
  55 Pseudo-code:
  56
  57     b <- (RA|0)
  58     EA <- b + (RB)
  59     RT <- MEM(EA, 8)
  60
  61 Special Registers Altered:
  62
  63     None
  64
  65 # Store Byte Caching Inhibited Indexed
  66
  67 X-Form
  68
  69 * stbcix RS,RA,RB
  70
  71 Pseudo-code:
  72
  73     b <- (RA|0)
  74     EA <- b + (RB)
  75     MEM(EA, 1) <- (RS)[56:63]
  76
  77 Special Registers Altered:
  78
  79     None
  80
  81 # Store Halfword Caching Inhibited Indexed
  82
  83 X-Form
  84
  85 * sthcix RS,RA,RB
  86
  87 Pseudo-code:
  88
  89     b <- (RA|0)
  90     EA <- b + (RB)
  91     MEM(EA, 2) <- (RS)[48:63]
  92
  93 Special Registers Altered:
  94
  95     None
  96
  97 # Store Word Caching Inhibited Indexed
  98
  99 X-Form
 100
 101 * stwcix RS,RA,RB
 102
 103 Pseudo-code:
 104
 105     b <- (RA|0)
 106     EA <- b + (RB)
 107     MEM(EA, 4) <- (RS)[32:63]
 108
 109 Special Registers Altered:
 110
 111     None
 112
 113 # Store Doubleword Caching Inhibited Indexed
 114
 115 X-Form
 116
 117 * stdcix RS,RA,RB
 118
 119 Pseudo-code:
 120
 121     b <- (RA|0)
 122     EA <- b + (RB)
 123     MEM(EA, 8) <- (RS)
 124
 125 Special Registers Altered:
 126
 127     None
 128