openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43 Let the effective address (EA) be the sum (RA|0)+ D.
  44 The byte in storage addressed by EA is loaded into
  45 RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Load Byte and Zero with Update
  68
  69 D-Form
  70
  71 * lbzu RT,D(RA)
  72
  73 Pseudo-code:
  74
  75     EA <- (RA) + EXTS(D)
  76     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  77     RA <- EA
  78
  79 Description:Let the effective address (EA) be the sum (RA)+ D. The
  80 byte in storage addressed by EA is loaded into RT 56:63.
  81 RT0:55 are set to 0.
  82 EA is placed into register RA.
  83 If RA=0 or RA=RT, the instruction form is invalid.
  84
  85 Special Registers Altered:
  86
  87     None
  88
  89 # Load Byte and Zero with Update Indexed
  90
  91 X-Form
  92
  93 * lbzux RT,RA,RB
  94
  95 Pseudo-code:
  96
  97     EA <- (RA) + (RB)
  98     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  99     RA <- EA
 100
 101 Description:Let the effective address (EA) be the sum (RA)+ (RB).
 102 The byte in storage addressed by EA is loaded into
 103 RT56:63. RT0:55 are set to 0.
 104 EA is placed into register RA.
 105 If RA=0 or RA=RT, the instruction form is invalid.
 106
 107 Special Registers Altered:
 108
 109     None
 110
 111 # Load Halfword and Zero
 112
 113 D-Form
 114
 115 * lhz RT,D(RA)
 116
 117 Pseudo-code:
 118
 119     b <- (RA|0)
 120     EA <- b + EXTS(D)
 121     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 122
 123 Special Registers Altered:
 124
 125     None
 126
 127 # Load Halfword and Zero Indexed
 128
 129 X-Form
 130
 131 * lhzx RT,RA,RB
 132
 133 Pseudo-code:
 134
 135     b <- (RA|0)
 136     EA <- b + (RB)
 137     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 138
 139 Special Registers Altered:
 140
 141     None
 142
 143 # Load Halfword and Zero with Update
 144
 145 D-Form
 146
 147 * lhzu RT,D(RA)
 148
 149 Pseudo-code:
 150
 151     EA <- (RA) + EXTS(D)
 152     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 153     RA <- EA
 154
 155 Description:Let the effective address (EA) be the sum
 156 (RA|0)+ (RB). The halfword in storage addressed by
 157 EA is loaded into RT 48:63. RT 0:47 are set to 0.
 158
 159 Special Registers Altered:
 160
 161     None
 162
 163 # Load Halfword and Zero with Update Indexed
 164
 165 X-Form
 166
 167 * lhzux RT,RA,RB
 168
 169 Pseudo-code:
 170
 171     EA <- (RA) + (RB)
 172     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 173     RA <- EA
 174
 175 Special Registers Altered:
 176
 177     None
 178
 179 # Load Halfword Algebraic
 180
 181 D-Form
 182
 183 * lha RT,D(RA)
 184
 185 Pseudo-code:
 186
 187     b <- (RA|0)
 188     EA <- b + EXTS(D)
 189     RT <- EXTS(MEM(EA, 2))
 190
 191 Special Registers Altered:
 192
 193     None
 194
 195 # Load Halfword Algebraic Indexed
 196
 197 X-Form
 198
 199 * lhax RT,RA,RB
 200
 201 Pseudo-code:
 202
 203     b <- (RA|0)
 204     EA <- b + (RB)
 205     RT <- EXTS(MEM(EA, 2))
 206
 207 Special Registers Altered:
 208
 209     None
 210
 211 # Load Halfword Algebraic with Update
 212
 213 D-Form
 214
 215 * lhau RT,D(RA)
 216
 217 Pseudo-code:
 218
 219     EA <- (RA) + EXTS(D)
 220     RT <- EXTS(MEM(EA, 2))
 221     RA <- EA
 222
 223 Special Registers Altered:
 224
 225     None
 226
 227 # Load Halfword Algebraic with Update Indexed
 228
 229 X-Form
 230
 231 * lhaux RT,RA,RB
 232
 233 Pseudo-code:
 234
 235     EA <- (RA) + (RB)
 236     RT <- EXTS(MEM(EA, 2))
 237     RA <- EA
 238
 239 Special Registers Altered:
 240
 241     None
 242
 243 # Load Word and Zero
 244
 245 D-Form
 246
 247 * lwz RT,D(RA)
 248
 249 Pseudo-code:
 250
 251     b <- (RA|0)
 252     EA <- b + EXTS(D)
 253     RT <- [0] * 32 || MEM(EA, 4)
 254
 255 Special Registers Altered:
 256
 257     None
 258
 259 # Load Word and Zero Indexed
 260
 261 X-Form
 262
 263 * lwzx RT,RA,RB
 264
 265 Pseudo-code:
 266
 267     b <- (RA|0)
 268     EA <- b + (RB)
 269     RT <- [0] * 32 || MEM(EA, 4)
 270
 271 Special Registers Altered:
 272
 273     None
 274
 275 # Load Word and Zero with Update
 276
 277 D-Form
 278
 279 * lwzu RT,D(RA)
 280
 281 Pseudo-code:
 282
 283     EA <- (RA) + EXTS(D)
 284     RT <- [0]*32 || MEM(EA, 4)
 285     RA <- EA
 286
 287 Special Registers Altered:
 288
 289     None
 290
 291 # Load Word and Zero with Update Indexed
 292
 293 X-Form
 294
 295 * lwzux RT,RA,RB
 296
 297 Pseudo-code:
 298
 299     EA <- (RA) + (RB)
 300     RT <- [0] * 32 || MEM(EA, 4)
 301     RA <- EA
 302
 303 Special Registers Altered:
 304
 305     None
 306
 307 # Load Word Algebraic
 308
 309 DS-Form
 310
 311 * lwa RT,DS(RA)
 312
 313 Pseudo-code:
 314
 315     b <- (RA|0)
 316     EA <- b + EXTS(DS || 0b00)
 317     RT <- EXTS(MEM(EA, 4))
 318
 319 Special Registers Altered:
 320
 321     None
 322
 323 # Load Word Algebraic Indexed
 324
 325 X-Form
 326
 327 * lwax RT,RA,RB
 328
 329 Pseudo-code:
 330
 331     b <- (RA|0)
 332     EA <- b + (RB)
 333     RT <- EXTS(MEM(EA, 4))
 334
 335 Special Registers Altered:
 336
 337     None
 338
 339 # Load Word Algebraic with Update Indexed
 340
 341 X-Form
 342
 343 * lwaux RT,RA,RB
 344
 345 Pseudo-code:
 346
 347     EA <- (RA) + (RB)
 348     RT <- EXTS(MEM(EA, 4))
 349     RA <- EA
 350
 351 Special Registers Altered:
 352
 353     None
 354
 355 # Load Doubleword
 356
 357 DS-Form
 358
 359 * ld RT,DS(RA)
 360
 361 Pseudo-code:
 362
 363     b <- (RA|0)
 364     EA <- b + EXTS(DS || 0b00)
 365     RT <- MEM(EA, 8)
 366
 367 Special Registers Altered:
 368
 369     None
 370
 371 # Load Doubleword Indexed
 372
 373 X-Form
 374
 375 * ldx RT,RA,RB
 376
 377 Pseudo-code:
 378
 379     b <- (RA|0)
 380     EA <- b + (RB)
 381     RT <- MEM(EA, 8)
 382
 383 Special Registers Altered:
 384
 385     None
 386
 387 # Load Doubleword with Update Indexed
 388
 389 DS-Form
 390
 391 * ldu RT,DS(RA)
 392
 393 Pseudo-code:
 394
 395     EA <- (RA) + EXTS(DS || 0b00)
 396     RT <- MEM(EA, 8)
 397     RA <- EA
 398
 399 Special Registers Altered:
 400
 401     None
 402
 403 # Load Doubleword with Update Indexed
 404
 405 X-Form
 406
 407 * ldux RT,RA,RB
 408
 409 Pseudo-code:
 410
 411     EA <- (RA) + (RB)
 412     RT <- MEM(EA, 8)
 413     RA <- EA
 414
 415 Special Registers Altered:
 416
 417     None
 418
 419 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 420
 421 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 422 <!-- doubleword in storage addressed by EA. -->
 423
 424 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 425 <!-- updated with the effective address. For these forms, the following rules apply. -->
 426
 427 <!-- If RA!=0, the effective address is placed into register RA. -->
 428
 429 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 430 <!-- and then EA is placed into RA (RS). -->
 431
 432 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 433
 434 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 435
 436 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 437 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 438 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 439 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 440 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 441 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 442 <!-- by EA. -->
 443
 444 # Load Quadword
 445
 446 DQ-Form
 447
 448 * lq RTp,DQ(RA)
 449
 450 Pseudo-code:
 451
 452     b <- (RA|0)
 453     EA <- b + EXTS(DQ || 0b0000)
 454     RTp <- MEM(EA, 16)
 455
 456 Special Registers Altered:
 457
 458     None
 459
 460 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 461
 462 # Load Halfword Byte-Reverse Indexed
 463
 464 X-Form
 465
 466 * lhbrx RT,RA,RB
 467
 468 Pseudo-code:
 469
 470     b <- (RA|0)
 471     EA <- b + (RB)
 472     load_data <- MEM(EA, 2)
 473     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 474
 475 Special Registers Altered:
 476
 477     None
 478
 479 # Load Word Byte-Reverse Indexed
 480
 481 X-Form
 482
 483 * lwbrx RT,RA,RB
 484
 485 Pseudo-code:
 486
 487     b <- (RA|0)
 488     EA <- b + (RB)
 489     load_data <- MEM(EA, 4)
 490     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 491                     || load_data[8:15]  || load_data[0:7])
 492
 493 Special Registers Altered:
 494
 495     None
 496
 497
 498 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 499
 500 # Load Doubleword Byte-Reverse Indexed
 501
 502 X-Form
 503
 504 * ldbrx RT,RA,RB
 505
 506 Pseudo-code:
 507
 508     b <- (RA|0)
 509     EA <- b + (RB)
 510     load_data <- MEM(EA, 8)
 511     RT <- (load_data[56:63] || load_data[48:55]
 512         || load_data[40:47] || load_data[32:39]
 513         || load_data[24:31] || load_data[16:23]
 514         || load_data[8:15]  || load_data[0:7])
 515
 516 Special Registers Altered:
 517
 518     None
 519
 520 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 521
 522 # Load Multiple Word
 523
 524 DQ-Form
 525
 526 * lmw RT,D(RA)
 527
 528 Pseudo-code:
 529
 530     b <- (RA|0)
 531     EA <- b + EXTS(D)
 532     r <- RT[0:63]
 533     do while r <=  31
 534         GPR(r) <- [0]*32 || MEM(EA, 4)
 535         r <- r + 1
 536         EA <- EA + 4
 537
 538 Special Registers Altered:
 539
 540     None
 541