openpower/isa/fixedload.mdwn

   1 # Load Byte and Zero
   2
   3 D-Form
   4
   5 * lbz RT,D(RA)
   6
   7 Pseudo-code:
   8
   9     b <- (RA|0)
  10     EA <- b + EXTS(D)
  11     RT <- [0]*56 || MEM(EA, 1)
  12
  13 Special Registers Altered:
  14
  15     None
  16
  17 # Load Byte and Zero Indexed
  18
  19 X-Form
  20
  21 * lbzx RT,RA,RB
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + (RB)
  27     RT <- [0] * 56 || MEM(EA, 1)
  28
  29 Special Registers Altered:
  30
  31     None
  32
  33 # Load Byte and Zero with Update
  34
  35 D-Form
  36
  37 * lbzu RT,D(RA)
  38
  39 Pseudo-code:
  40
  41     EA <- (RA) + EXTS(D)
  42     RT <- [0] * 56 || MEM(EA, 1)
  43     RA <- EA
  44
  45 Special Registers Altered:
  46
  47     None
  48
  49 # Load Byte and Zero with Update Indexed
  50
  51 X-Form
  52
  53 * lbzux RT,RA,RB
  54
  55 Pseudo-code:
  56
  57     EA <- (RA) + (RB)
  58     RT <- [0] * 56 || MEM(EA, 1)
  59     RA <- EA
  60
  61 Special Registers Altered:
  62
  63     None
  64
  65 # Load Halfword and Zero
  66
  67 D-Form
  68
  69 * lhz RT,D(RA)
  70
  71 Pseudo-code:
  72
  73     b <- (RA|0)
  74     EA <- b + EXTS(D)
  75     RT <- [0] * 48 || MEM(EA, 2)
  76
  77 Special Registers Altered:
  78
  79     None
  80
  81 # Load Halfword and Zero Indexed
  82
  83 X-Form
  84
  85 * lhzx RT,RA,RB
  86
  87 Pseudo-code:
  88
  89     b <- (RA|0)
  90     EA <- b + (RB)
  91     RT <- [0] * 48 || MEM(EA, 2)
  92
  93 Special Registers Altered:
  94
  95     None
  96
  97 # Load Halfword and Zero with Update
  98
  99 D-Form
 100
 101 * lhzu RT,D(RA)
 102
 103 Pseudo-code:
 104
 105     EA <- (RA) + EXTS(D)
 106     RT <- [0] * 48 || MEM(EA, 2)
 107     RA <- EA
 108
 109 Special Registers Altered:
 110
 111     None
 112
 113 # Load Halfword and Zero with Update Indexed
 114
 115 X-Form
 116
 117 * lhzux RT,RA,RB
 118
 119 Pseudo-code:
 120
 121     EA <- (RA) + (RB)
 122     RT <- [0] * 48 || MEM(EA, 2)
 123     RA <- EA
 124
 125 Special Registers Altered:
 126
 127     None
 128
 129 # Load Halfword Algebraic
 130
 131 D-Form
 132
 133 * lha RT,D(RA)
 134
 135 Pseudo-code:
 136
 137     b <- (RA|0)
 138     EA <- b + EXTS(D)
 139     RT <- EXTS(MEM(EA, 2))
 140
 141 Special Registers Altered:
 142
 143     None
 144
 145 # Load Halfword Algebraic Indexed
 146
 147 X-Form
 148
 149 * lhax RT,RA,RB
 150
 151 Pseudo-code:
 152
 153     b <- (RA|0)
 154     EA <- b + (RB)
 155     RT <- EXTS(MEM(EA, 2))
 156
 157 Special Registers Altered:
 158
 159     None
 160
 161 # Load Halfword Algebraic with Update
 162
 163 D-Form
 164
 165 * lhau RT,D(RA)
 166
 167 Pseudo-code:
 168
 169     EA <- (RA) + EXTS(D)
 170     RT <- EXTS(MEM(EA, 2))
 171     RA <- EA
 172
 173 Special Registers Altered:
 174
 175     None
 176
 177 # Load Halfword Algebraic with Update Indexed
 178
 179 X-Form
 180
 181 * lhaux RT,RA,RB
 182
 183 Pseudo-code:
 184
 185     EA <- (RA) + (RB)
 186     RT <- EXTS(MEM(EA, 2))
 187     RA <- EA
 188
 189 Special Registers Altered:
 190
 191     None
 192
 193 # Load Word and Zero
 194
 195 D-Form
 196
 197 * lwz RT,D(RA)
 198
 199 Pseudo-code:
 200
 201     b <- (RA|0)
 202     EA <- b + EXTS(D)
 203     RT <- [0] * 32 || MEM(EA, 4)
 204
 205 Special Registers Altered:
 206
 207     None
 208
 209 # Load Word and Zero Indexed
 210
 211 X-Form
 212
 213 * lwzx RT,RA,RB
 214
 215 Pseudo-code:
 216
 217     b <- (RA|0)
 218     EA <- b + (RB)
 219     RT <- [0] * 32 || MEM(EA, 4)
 220
 221 Special Registers Altered:
 222
 223     None
 224
 225 # Load Word and Zero with Update
 226
 227 D-Form
 228
 229 * lwzu RT,D(RA)
 230
 231 Pseudo-code:
 232
 233     EA <- (RA) + EXTS(D)
 234     RT <- [0]*32 || MEM(EA, 4)
 235     RA <- EA
 236
 237 Special Registers Altered:
 238
 239     None
 240
 241 # Load Word and Zero with Update Indexed
 242
 243 X-Form
 244
 245 * lwzux RT,RA,RB
 246
 247 Pseudo-code:
 248
 249     EA <- (RA) + (RB)
 250     RT <- [0] * 32 || MEM(EA, 4)
 251     RA <- EA
 252
 253 Special Registers Altered:
 254
 255     None
 256
 257 # Load Word Algebraic
 258
 259 DS-Form
 260
 261 * lwa RT,DS(RA)
 262
 263 Pseudo-code:
 264
 265     b <- (RA|0)
 266     EA <- b + EXTS(DS || 0b00)
 267     RT <- EXTS(MEM(EA, 4))
 268
 269 Special Registers Altered:
 270
 271     None
 272
 273 # Load Word Algebraic Indexed
 274
 275 X-Form
 276
 277 * lwax RT,RA,RB
 278
 279 Pseudo-code:
 280
 281     b <- (RA|0)
 282     EA <- b + (RB)
 283     RT <- EXTS(MEM(EA, 4))
 284
 285 Special Registers Altered:
 286
 287     None
 288
 289 # Load Word Algebraic with Update Indexed
 290
 291 X-Form
 292
 293 * lwaux RT,RA,RB
 294
 295 Pseudo-code:
 296
 297     EA <- (RA) + (RB)
 298     RT <- EXTS(MEM(EA, 4))
 299     RA <- EA
 300
 301 Special Registers Altered:
 302
 303     None
 304
 305 # Load Doubleword
 306
 307 DS-Form
 308
 309 * ld RT,DS(RA)
 310
 311 Pseudo-code:
 312
 313     b <- (RA|0)
 314     EA <- b + EXTS(DS || 0b00)
 315     RT <- MEM(EA, 8)
 316
 317 Special Registers Altered:
 318
 319     None
 320
 321 # Load Doubleword Indexed
 322
 323 X-Form
 324
 325 * ldx RT,RA,RB
 326
 327 Pseudo-code:
 328
 329     b <- (RA|0)
 330     EA <- b + (RB)
 331     RT <- MEM(EA, 8)
 332
 333 Special Registers Altered:
 334
 335     None
 336
 337 # Load Doubleword with Update Indexed
 338
 339 DS-Form
 340
 341 * ldu RT,DS(RA)
 342
 343 Pseudo-code:
 344
 345     EA <- (RA) + EXTS(DS || 0b00)
 346     RT <- MEM(EA, 8)
 347     RA <- EA
 348
 349 Special Registers Altered:
 350
 351     None
 352
 353 # Load Doubleword with Update Indexed
 354
 355 X-Form
 356
 357 * ldux RT,RA,RB
 358
 359 Pseudo-code:
 360
 361     EA <- (RA) + (RB)
 362     RT <- MEM(EA, 8)
 363     RA <- EA
 364
 365 Special Registers Altered:
 366
 367     None
 368
 369 # Load Quadword
 370
 371 DQ-Form
 372
 373 * lq RTp,DQ(RA)
 374
 375 Pseudo-code:
 376
 377     b <- (RA|0)
 378     EA <- b + EXTS(DQ || 0b0000)
 379     RTp <- MEM(EA, 16)
 380
 381 Special Registers Altered:
 382
 383     None
 384
 385 # Load Halfword Byte-Reverse Indexed
 386
 387 X-Form
 388
 389 * lhbrx RT,RA,RB
 390
 391 Pseudo-code:
 392
 393     b <- (RA|0)
 394     EA <- b + (RB)
 395     load_data <- MEM(EA, 2)
 396     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 397
 398 Special Registers Altered:
 399
 400     None
 401
 402 # Load Word Byte-Reverse Indexed
 403
 404 X-Form
 405
 406 * lwbrx RT,RA,RB
 407
 408 Pseudo-code:
 409
 410     b <- (RA|0)
 411     EA <- b + (RB)
 412     load_data <- MEM(EA, 4)
 413     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 414                     || load_data[8:15]  || load_data[0:7])
 415
 416 Special Registers Altered:
 417
 418     None
 419
 420 # Load Doubleword Byte-Reverse Indexed
 421
 422 X-Form
 423
 424 * ldbrx RT,RA,RB
 425
 426 Pseudo-code:
 427
 428     b <- (RA|0)
 429     EA <- b + (RB)
 430     load_data <- MEM(EA, 8)
 431     RT <- (load_data[56:63] || load_data[48:55]
 432         || load_data[40:47] || load_data[32:39]
 433         || load_data[24:31] || load_data[16:23]
 434         || load_data[8:15]  || load_data[0:7])
 435
 436 Special Registers Altered:
 437
 438     None
 439
 440 # Load Multiple Word
 441
 442 DQ-Form
 443
 444 * lmw RT,D(RA)
 445
 446 Pseudo-code:
 447
 448     b <- (RA|0)
 449     EA <- b + EXTS(D)
 450     r <- RT
 451     do while r <=  31
 452         GPR(r) <- [0]*32 || MEM(EA, 4)
 453         r <- r + 1
 454         EA <- EA + 4
 455
 456 Special Registers Altered:
 457
 458     None