openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44     The byte in storage addressed by EA is loaded into
  45     RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Description:
  64
  65     Let the effective address (EA) be the sum
  66     (RA|0)+ (RB). The byte in storage addressed by EA is
  67     loaded into RT[56:63] . RT[0:55] are set to 0.
  68
  69 Special Registers Altered:
  70
  71     None
  72
  73 # Load Byte and Zero with Update
  74
  75 D-Form
  76
  77 * lbzu RT,D(RA)
  78
  79 Pseudo-code:
  80
  81     EA <- (RA) + EXTS(D)
  82     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  83     RA <- EA
  84
  85 Description:
  86
  87     Let the effective address (EA) be the sum (RA)+ D. The
  88     byte in storage addressed by EA is loaded into RT[56:63].
  89     RT[0:55] are set to 0.
  90
  91     EA is placed into register RA.
  92
  93     If RA=0 or RA=RT, the instruction form is invalid.
  94
  95 Special Registers Altered:
  96
  97     None
  98
  99 # Load Byte and Zero with Update Indexed
 100
 101 X-Form
 102
 103 * lbzux RT,RA,RB
 104
 105 Pseudo-code:
 106
 107     EA <- (RA) + (RB)
 108     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 109     RA <- EA
 110
 111 Description:
 112
 113     Let the effective address (EA) be the sum (RA)+ (RB).
 114     The byte in storage addressed by EA is loaded into
 115     RT[56:63]. RT[0:55] are set to 0.
 116
 117     EA is placed into register RA.
 118
 119     If RA=0 or RA=RT, the instruction form is invalid.
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Load Halfword and Zero
 126
 127 D-Form
 128
 129 * lhz RT,D(RA)
 130
 131 Pseudo-code:
 132
 133     b <- (RA|0)
 134     EA <- b + EXTS(D)
 135     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 136
 137 Description:
 138
 139     Let the effective address (EA) be the sum (RA|0)+ D.
 140     The halfword in storage addressed by EA is loaded into
 141     RT[48:63]. RT[0:47] are set to 0.
 142
 143 Special Registers Altered:
 144
 145     None
 146
 147 # Load Halfword and Zero Indexed
 148
 149 X-Form
 150
 151 * lhzx RT,RA,RB
 152
 153 Pseudo-code:
 154
 155     b <- (RA|0)
 156     EA <- b + (RB)
 157     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 158
 159 Description:
 160
 161     Let the effective address (EA) be the sum
 162     (RA|0)+ (RB). The halfword in storage addressed by
 163     EA is loaded into RT 48:63. RT 0:47 are set to 0.
 164
 165 Special Registers Altered:
 166
 167     None
 168
 169 # Load Halfword and Zero with Update
 170
 171 D-Form
 172
 173 * lhzu RT,D(RA)
 174
 175 Pseudo-code:
 176
 177     EA <- (RA) + EXTS(D)
 178     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 179     RA <- EA
 180
 181 Description:
 182
 183     Let the effective address (EA) be the sum (RA)+ D. The
 184     halfword in storage addressed by EA is loaded into
 185     RT[48:63]. RT[0:47] are set to 0.
 186
 187     EA is placed into register RA.
 188
 189     If RA=0 or RA=RT, the instruction form is invalid.
 190
 191 Special Registers Altered:
 192
 193     None
 194
 195 # Load Halfword and Zero with Update Indexed
 196
 197 X-Form
 198
 199 * lhzux RT,RA,RB
 200
 201 Pseudo-code:
 202
 203     EA <- (RA) + (RB)
 204     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 205     RA <- EA
 206
 207 Description:
 208
 209     Let the effective address (EA) be the sum (RA)+ (RB).
 210     The halfword in storage addressed by EA is loaded into
 211     RT[48:63]. RT[0:47] are set to 0.
 212
 213     EA is placed into register RA.
 214
 215     If RA=0 or RA=RT, the instruction form is invalid.
 216
 217 Special Registers Altered:
 218
 219     None
 220
 221 # Load Halfword Algebraic
 222
 223 D-Form
 224
 225 * lha RT,D(RA)
 226
 227 Pseudo-code:
 228
 229     b <- (RA|0)
 230     EA <- b + EXTS(D)
 231     RT <- EXTS(MEM(EA, 2))
 232
 233 Special Registers Altered:
 234
 235     None
 236
 237 # Load Halfword Algebraic Indexed
 238
 239 X-Form
 240
 241 * lhax RT,RA,RB
 242
 243 Pseudo-code:
 244
 245     b <- (RA|0)
 246     EA <- b + (RB)
 247     RT <- EXTS(MEM(EA, 2))
 248
 249 Special Registers Altered:
 250
 251     None
 252
 253 # Load Halfword Algebraic with Update
 254
 255 D-Form
 256
 257 * lhau RT,D(RA)
 258
 259 Pseudo-code:
 260
 261     EA <- (RA) + EXTS(D)
 262     RT <- EXTS(MEM(EA, 2))
 263     RA <- EA
 264
 265 Description:
 266
 267     Let the effective address (EA) be the sum (RA)+ D. The
 268     halfword in storage addressed by EA is loaded into
 269     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 270     loaded halfword.
 271
 272     EA is placed into register RA.
 273
 274     If RA=0 or RA=RT, the instruction form is invalid.
 275
 276 Special Registers Altered:
 277
 278     None
 279
 280 # Load Halfword Algebraic with Update Indexed
 281
 282 X-Form
 283
 284 * lhaux RT,RA,RB
 285
 286 Pseudo-code:
 287
 288     EA <- (RA) + (RB)
 289     RT <- EXTS(MEM(EA, 2))
 290     RA <- EA
 291
 292 Description:
 293
 294     Let the effective address (EA) be the sum (RA)+ (RB).
 295     The halfword in storage addressed by EA is loaded into
 296     RT48:63. RT 0:47 are filled with a copy of bit 0 of the
 297     loaded halfword.
 298
 299     EA is placed into register RA.
 300
 301     If RA=0 or RA=RT, the instruction form is invalid.
 302
 303 Special Registers Altered:
 304
 305     None
 306
 307 # Load Word and Zero
 308
 309 D-Form
 310
 311 * lwz RT,D(RA)
 312
 313 Pseudo-code:
 314
 315     b <- (RA|0)
 316     EA <- b + EXTS(D)
 317     RT <- [0] * 32 || MEM(EA, 4)
 318
 319 Special Registers Altered:
 320
 321     None
 322
 323 # Load Word and Zero Indexed
 324
 325 X-Form
 326
 327 * lwzx RT,RA,RB
 328
 329 Pseudo-code:
 330
 331     b <- (RA|0)
 332     EA <- b + (RB)
 333     RT <- [0] * 32 || MEM(EA, 4)
 334
 335 Special Registers Altered:
 336
 337     None
 338
 339 # Load Word and Zero with Update
 340
 341 D-Form
 342
 343 * lwzu RT,D(RA)
 344
 345 Pseudo-code:
 346
 347     EA <- (RA) + EXTS(D)
 348     RT <- [0]*32 || MEM(EA, 4)
 349     RA <- EA
 350
 351 Special Registers Altered:
 352
 353     None
 354
 355 # Load Word and Zero with Update Indexed
 356
 357 X-Form
 358
 359 * lwzux RT,RA,RB
 360
 361 Pseudo-code:
 362
 363     EA <- (RA) + (RB)
 364     RT <- [0] * 32 || MEM(EA, 4)
 365     RA <- EA
 366
 367 Special Registers Altered:
 368
 369     None
 370
 371 # Load Word Algebraic
 372
 373 DS-Form
 374
 375 * lwa RT,DS(RA)
 376
 377 Pseudo-code:
 378
 379     b <- (RA|0)
 380     EA <- b + EXTS(DS || 0b00)
 381     RT <- EXTS(MEM(EA, 4))
 382
 383 Special Registers Altered:
 384
 385     None
 386
 387 # Load Word Algebraic Indexed
 388
 389 X-Form
 390
 391 * lwax RT,RA,RB
 392
 393 Pseudo-code:
 394
 395     b <- (RA|0)
 396     EA <- b + (RB)
 397     RT <- EXTS(MEM(EA, 4))
 398
 399 Special Registers Altered:
 400
 401     None
 402
 403 # Load Word Algebraic with Update Indexed
 404
 405 X-Form
 406
 407 * lwaux RT,RA,RB
 408
 409 Pseudo-code:
 410
 411     EA <- (RA) + (RB)
 412     RT <- EXTS(MEM(EA, 4))
 413     RA <- EA
 414
 415 Special Registers Altered:
 416
 417     None
 418
 419 # Load Doubleword
 420
 421 DS-Form
 422
 423 * ld RT,DS(RA)
 424
 425 Pseudo-code:
 426
 427     b <- (RA|0)
 428     EA <- b + EXTS(DS || 0b00)
 429     RT <- MEM(EA, 8)
 430
 431 Special Registers Altered:
 432
 433     None
 434
 435 # Load Doubleword Indexed
 436
 437 X-Form
 438
 439 * ldx RT,RA,RB
 440
 441 Pseudo-code:
 442
 443     b <- (RA|0)
 444     EA <- b + (RB)
 445     RT <- MEM(EA, 8)
 446
 447 Special Registers Altered:
 448
 449     None
 450
 451 # Load Doubleword with Update Indexed
 452
 453 DS-Form
 454
 455 * ldu RT,DS(RA)
 456
 457 Pseudo-code:
 458
 459     EA <- (RA) + EXTS(DS || 0b00)
 460     RT <- MEM(EA, 8)
 461     RA <- EA
 462
 463 Special Registers Altered:
 464
 465     None
 466
 467 # Load Doubleword with Update Indexed
 468
 469 X-Form
 470
 471 * ldux RT,RA,RB
 472
 473 Pseudo-code:
 474
 475     EA <- (RA) + (RB)
 476     RT <- MEM(EA, 8)
 477     RA <- EA
 478
 479 Special Registers Altered:
 480
 481     None
 482
 483 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 484
 485 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 486 <!-- doubleword in storage addressed by EA. -->
 487
 488 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 489 <!-- updated with the effective address. For these forms, the following rules apply. -->
 490
 491 <!-- If RA!=0, the effective address is placed into register RA. -->
 492
 493 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 494 <!-- and then EA is placed into RA (RS). -->
 495
 496 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 497
 498 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 499
 500 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 501 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 502 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 503 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 504 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 505 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 506 <!-- by EA. -->
 507
 508 # Load Quadword
 509
 510 DQ-Form
 511
 512 * lq RTp,DQ(RA)
 513
 514 Pseudo-code:
 515
 516     b <- (RA|0)
 517     EA <- b + EXTS(DQ || 0b0000)
 518     RTp <- MEM(EA, 16)
 519
 520 Special Registers Altered:
 521
 522     None
 523
 524 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 525
 526 # Load Halfword Byte-Reverse Indexed
 527
 528 X-Form
 529
 530 * lhbrx RT,RA,RB
 531
 532 Pseudo-code:
 533
 534     b <- (RA|0)
 535     EA <- b + (RB)
 536     load_data <- MEM(EA, 2)
 537     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 538
 539 Special Registers Altered:
 540
 541     None
 542
 543 # Load Word Byte-Reverse Indexed
 544
 545 X-Form
 546
 547 * lwbrx RT,RA,RB
 548
 549 Pseudo-code:
 550
 551     b <- (RA|0)
 552     EA <- b + (RB)
 553     load_data <- MEM(EA, 4)
 554     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 555                     || load_data[8:15]  || load_data[0:7])
 556
 557 Special Registers Altered:
 558
 559     None
 560
 561
 562 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 563
 564 # Load Doubleword Byte-Reverse Indexed
 565
 566 X-Form
 567
 568 * ldbrx RT,RA,RB
 569
 570 Pseudo-code:
 571
 572     b <- (RA|0)
 573     EA <- b + (RB)
 574     load_data <- MEM(EA, 8)
 575     RT <- (load_data[56:63] || load_data[48:55]
 576         || load_data[40:47] || load_data[32:39]
 577         || load_data[24:31] || load_data[16:23]
 578         || load_data[8:15]  || load_data[0:7])
 579
 580 Special Registers Altered:
 581
 582     None
 583
 584 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 585
 586 # Load Multiple Word
 587
 588 DQ-Form
 589
 590 * lmw RT,D(RA)
 591
 592 Pseudo-code:
 593
 594     b <- (RA|0)
 595     EA <- b + EXTS(D)
 596     r <- RT[0:63]
 597     do while r <=  31
 598         GPR(r) <- [0]*32 || MEM(EA, 4)
 599         r <- r + 1
 600         EA <- EA + 4
 601
 602 Special Registers Altered:
 603
 604     None
 605