1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
43 Let the effective address (EA) be the sum (RA|0)+ D.
44 The byte in storage addressed by EA is loaded into
45 RT[56:63]. RT[0:55] are set to 0.
47 Special Registers Altered:
51 # Load Byte and Zero Indexed
61 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
63 Special Registers Altered:
67 # Load Byte and Zero with Update
76 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
79 Special Registers Altered:
83 # Load Byte and Zero with Update Indexed
92 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
95 Special Registers Altered:
99 # Load Halfword and Zero
109 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
111 Special Registers Altered:
115 # Load Halfword and Zero Indexed
125 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
127 Special Registers Altered:
131 # Load Halfword and Zero with Update
140 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
143 Special Registers Altered:
147 # Load Halfword and Zero with Update Indexed
156 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
159 Special Registers Altered:
163 # Load Halfword Algebraic
173 RT <- EXTS(MEM(EA, 2))
175 Special Registers Altered:
179 # Load Halfword Algebraic Indexed
189 RT <- EXTS(MEM(EA, 2))
191 Special Registers Altered:
195 # Load Halfword Algebraic with Update
204 RT <- EXTS(MEM(EA, 2))
207 Special Registers Altered:
211 # Load Halfword Algebraic with Update Indexed
220 RT <- EXTS(MEM(EA, 2))
223 Special Registers Altered:
237 RT <- [0] * 32 || MEM(EA, 4)
239 Special Registers Altered:
243 # Load Word and Zero Indexed
253 RT <- [0] * 32 || MEM(EA, 4)
255 Special Registers Altered:
259 # Load Word and Zero with Update
268 RT <- [0]*32 || MEM(EA, 4)
271 Special Registers Altered:
275 # Load Word and Zero with Update Indexed
284 RT <- [0] * 32 || MEM(EA, 4)
287 Special Registers Altered:
291 # Load Word Algebraic
300 EA <- b + EXTS(DS || 0b00)
301 RT <- EXTS(MEM(EA, 4))
303 Special Registers Altered:
307 # Load Word Algebraic Indexed
317 RT <- EXTS(MEM(EA, 4))
319 Special Registers Altered:
323 # Load Word Algebraic with Update Indexed
332 RT <- EXTS(MEM(EA, 4))
335 Special Registers Altered:
348 EA <- b + EXTS(DS || 0b00)
351 Special Registers Altered:
355 # Load Doubleword Indexed
367 Special Registers Altered:
371 # Load Doubleword with Update Indexed
379 EA <- (RA) + EXTS(DS || 0b00)
383 Special Registers Altered:
387 # Load Doubleword with Update Indexed
399 Special Registers Altered:
403 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
405 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
406 <!-- doubleword in storage addressed by EA. -->
408 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
409 <!-- updated with the effective address. For these forms, the following rules apply. -->
411 <!-- If RA!=0, the effective address is placed into register RA. -->
413 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
414 <!-- and then EA is placed into RA (RS). -->
416 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
418 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
420 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
421 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
422 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
423 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
424 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
425 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
437 EA <- b + EXTS(DQ || 0b0000)
440 Special Registers Altered:
444 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
446 # Load Halfword Byte-Reverse Indexed
456 load_data <- MEM(EA, 2)
457 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
459 Special Registers Altered:
463 # Load Word Byte-Reverse Indexed
473 load_data <- MEM(EA, 4)
474 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
475 || load_data[8:15] || load_data[0:7])
477 Special Registers Altered:
482 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
484 # Load Doubleword Byte-Reverse Indexed
494 load_data <- MEM(EA, 8)
495 RT <- (load_data[56:63] || load_data[48:55]
496 || load_data[40:47] || load_data[32:39]
497 || load_data[24:31] || load_data[16:23]
498 || load_data[8:15] || load_data[0:7])
500 Special Registers Altered:
504 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
518 GPR(r) <- [0]*32 || MEM(EA, 4)
522 Special Registers Altered: