1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
43 Let the effective address (EA) be the sum (RA|0)+ D.
44 The byte in storage addressed by EA is loaded into
45 RT[56:63]. RT[0:55] are set to 0.
47 Special Registers Altered:
51 # Load Byte and Zero Indexed
61 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
63 Special Registers Altered:
67 # Load Byte and Zero with Update
76 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
81 Let the effective address (EA) be the sum (RA)+ D. The
82 byte in storage addressed by EA is loaded into RT[56:63].
83 RT[0:55] are set to 0.
85 EA is placed into register RA.
87 If RA=0 or RA=RT, the instruction form is invalid.
89 Special Registers Altered:
93 # Load Byte and Zero with Update Indexed
102 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
107 Let the effective address (EA) be the sum (RA)+ (RB).
108 The byte in storage addressed by EA is loaded into
109 RT[56:63]. RT[0:55] are set to 0.
111 EA is placed into register RA.
113 If RA=0 or RA=RT, the instruction form is invalid.
115 Special Registers Altered:
119 # Load Halfword and Zero
129 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
131 Special Registers Altered:
135 # Load Halfword and Zero Indexed
145 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
147 Special Registers Altered:
151 # Load Halfword and Zero with Update
160 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
163 Description:Let the effective address (EA) be the sum (RA)+ D. The
164 halfword in storage addressed by EA is loaded into
165 RT48:63. RT 0:47 are set to 0.
166 EA is placed into register RA.
167 If RA=0 or RA=RT, the instruction form is invalid.
169 Special Registers Altered:
173 # Load Halfword and Zero with Update Indexed
182 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
185 Special Registers Altered:
189 # Load Halfword Algebraic
199 RT <- EXTS(MEM(EA, 2))
201 Special Registers Altered:
205 # Load Halfword Algebraic Indexed
215 RT <- EXTS(MEM(EA, 2))
217 Special Registers Altered:
221 # Load Halfword Algebraic with Update
230 RT <- EXTS(MEM(EA, 2))
233 Special Registers Altered:
237 # Load Halfword Algebraic with Update Indexed
246 RT <- EXTS(MEM(EA, 2))
249 Special Registers Altered:
263 RT <- [0] * 32 || MEM(EA, 4)
265 Special Registers Altered:
269 # Load Word and Zero Indexed
279 RT <- [0] * 32 || MEM(EA, 4)
281 Special Registers Altered:
285 # Load Word and Zero with Update
294 RT <- [0]*32 || MEM(EA, 4)
297 Special Registers Altered:
301 # Load Word and Zero with Update Indexed
310 RT <- [0] * 32 || MEM(EA, 4)
313 Special Registers Altered:
317 # Load Word Algebraic
326 EA <- b + EXTS(DS || 0b00)
327 RT <- EXTS(MEM(EA, 4))
329 Special Registers Altered:
333 # Load Word Algebraic Indexed
343 RT <- EXTS(MEM(EA, 4))
345 Special Registers Altered:
349 # Load Word Algebraic with Update Indexed
358 RT <- EXTS(MEM(EA, 4))
361 Special Registers Altered:
374 EA <- b + EXTS(DS || 0b00)
377 Special Registers Altered:
381 # Load Doubleword Indexed
393 Special Registers Altered:
397 # Load Doubleword with Update Indexed
405 EA <- (RA) + EXTS(DS || 0b00)
409 Special Registers Altered:
413 # Load Doubleword with Update Indexed
425 Special Registers Altered:
429 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
431 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
432 <!-- doubleword in storage addressed by EA. -->
434 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
435 <!-- updated with the effective address. For these forms, the following rules apply. -->
437 <!-- If RA!=0, the effective address is placed into register RA. -->
439 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
440 <!-- and then EA is placed into RA (RS). -->
442 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
444 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
446 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
447 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
448 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
449 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
450 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
451 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
463 EA <- b + EXTS(DQ || 0b0000)
466 Special Registers Altered:
470 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
472 # Load Halfword Byte-Reverse Indexed
482 load_data <- MEM(EA, 2)
483 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
485 Special Registers Altered:
489 # Load Word Byte-Reverse Indexed
499 load_data <- MEM(EA, 4)
500 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
501 || load_data[8:15] || load_data[0:7])
503 Special Registers Altered:
508 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
510 # Load Doubleword Byte-Reverse Indexed
520 load_data <- MEM(EA, 8)
521 RT <- (load_data[56:63] || load_data[48:55]
522 || load_data[40:47] || load_data[32:39]
523 || load_data[24:31] || load_data[16:23]
524 || load_data[8:15] || load_data[0:7])
526 Special Registers Altered:
530 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
544 GPR(r) <- [0]*32 || MEM(EA, 4)
548 Special Registers Altered: