openpower/isa/fixedstore.mdwn

   1 # Store Byte
   2
   3 D-Form
   4
   5 * stb RS,D(RA)
   6
   7 Pseudo-code:
   8
   9     b <- (RA|0)
  10     EA <- b + EXTS(D)
  11     MEM(EA, 1) <- (RS)[56:63]
  12
  13 Special Registers Altered:
  14
  15     None
  16
  17 # Store Byte Indexed
  18
  19 X-Form
  20
  21 * stbx RS,RA,RB
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + (RB)
  27     MEM(EA, 1) <- (RS)[56:63]
  28
  29 Special Registers Altered:
  30
  31     None
  32
  33 # Store Byte with Update
  34
  35 D-Form
  36
  37 * stbu RS,D(RA)
  38
  39 Pseudo-code:
  40
  41     EA <- (RA) + EXTS(D)
  42     MEM(EA, 1) <- (RS)[56:63]
  43     RA <- EA
  44
  45 Special Registers Altered:
  46
  47     None
  48
  49 # Store Byte with Update Indexed
  50
  51 X-Form
  52
  53 * stbux RS,RA,RB
  54
  55 Pseudo-code:
  56
  57     EA <- (RA) + (RB)
  58     MEM(EA, 1) <- (RS)[56:63]
  59     RA <- EA
  60
  61 Special Registers Altered:
  62
  63     None
  64
  65 # Store Halfword
  66
  67 D-Form
  68
  69 * sth RS,D(RA)
  70
  71 Pseudo-code:
  72
  73     b <- (RA|0)
  74     EA <- b + EXTS(D)
  75     MEM(EA, 2) <- (RS)[48:63]
  76
  77 Special Registers Altered:
  78
  79     None
  80
  81 # Store Halfword Indexed
  82
  83 X-Form
  84
  85 * sthx RS,RA,RB
  86
  87 Pseudo-code:
  88
  89     b <- (RA|0)
  90     EA <- b + (RB)
  91     MEM(EA, 2) <- (RS)[48:63]
  92
  93 Special Registers Altered:
  94
  95     None
  96
  97 # Store Halfword with Update
  98
  99 D-Form
 100
 101 * sthu RS,D(RA)
 102
 103 Pseudo-code:
 104
 105     EA <- (RA) + EXTS(D)
 106     MEM(EA, 2) <- (RS)[48:63]
 107     RA <- EA
 108
 109 Special Registers Altered:
 110
 111     None
 112
 113 # Store Halfword with Update Indexed
 114
 115 X-Form
 116
 117 * sthux RS,RA,RB
 118
 119 Pseudo-code:
 120
 121     EA <- (RA) + (RB)
 122     MEM(EA, 2) <- (RS)[48:63]
 123     RA <- EA
 124
 125 Special Registers Altered:
 126
 127     None
 128
 129 # Store Word
 130
 131 D-Form
 132
 133 * stw RS,D(RA)
 134
 135 Pseudo-code:
 136
 137     b <- (RA|0)
 138     EA <- b + EXTS(D)
 139     MEM(EA, 4) <- (RS)[32:63]
 140
 141 Special Registers Altered:
 142
 143     None
 144
 145 # Store Word Indexed
 146
 147 X-Form
 148
 149 * stwx RS,RA,RB
 150
 151 Pseudo-code:
 152
 153     b <- (RA|0)
 154     EA <- b + (RB)
 155     MEM(EA, 4) <- (RS)[32:63]
 156
 157 Special Registers Altered:
 158
 159     None
 160
 161 # Store Word with Update
 162
 163 D-Form
 164
 165 * stwu RS,D(RA)
 166
 167 Pseudo-code:
 168
 169     EA <- (RA) + EXTS(D)
 170     MEM(EA, 4) <- (RS)[32:63]
 171     RA <- EA
 172
 173 Special Registers Altered:
 174
 175     None
 176
 177 # Store Word with Update Indexed
 178
 179 X-Form
 180
 181 * stwux RS,RA,RB
 182
 183 Pseudo-code:
 184
 185     EA <- (RA) + (RB)
 186     MEM(EA, 4) <- (RS)[32:63]
 187     RA <- EA
 188
 189 Special Registers Altered:
 190
 191     None
 192
 193 # Store Doubleword
 194
 195 DS-Form
 196
 197 * std RS,DS(RA)
 198
 199 Pseudo-code:
 200
 201     b <- (RA|0)
 202     EA <- b + EXTS(DS || 0b00)
 203     MEM(EA, 8) <- (RS)
 204
 205 Special Registers Altered:
 206
 207     None
 208
 209 # Store Doubleword Indexed
 210
 211 X-Form
 212
 213 * stdx RS,RA,RB
 214
 215 Pseudo-code:
 216
 217     b <- (RA|0)
 218     EA <- b + (RB)
 219     MEM(EA, 8) <- (RS)
 220
 221 Special Registers Altered:
 222
 223     None
 224
 225 # Store Doubleword with Update
 226
 227 DS-Form
 228
 229 * stdu RS,DS(RA)
 230
 231 Pseudo-code:
 232
 233     EA <- (RA) + EXTS(DS || 0b00)
 234     MEM(EA, 8) <- (RS)
 235     RA <- EA
 236
 237 Special Registers Altered:
 238
 239     None
 240
 241 # Store Doubleword with Update Indexed
 242
 243 X-Form
 244
 245 * stdux RS,RA,RB
 246
 247 Pseudo-code:
 248
 249     EA <- (RA) + (RB)
 250     MEM(EA, 8) <- (RS)
 251     RA <- EA
 252
 253 Special Registers Altered:
 254
 255     None
 256
 257 # Store Quadword
 258
 259 DS-Form
 260
 261 * stq RSp,DS(RA)
 262
 263 Pseudo-code:
 264
 265     b <- (RA|0)
 266     EA <- b + EXTS(DS || 0b00)
 267     MEM(EA, 16) <- RSp
 268
 269 Special Registers Altered:
 270
 271     None
 272
 273 # Store Halfword Byte-Reverse Indexed
 274
 275 X-Form
 276
 277 * sthbrx RS,RA,RB
 278
 279 Pseudo-code:
 280
 281     b <- (RA|0)
 282     EA <- b + (RB)
 283     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 284
 285 Special Registers Altered:
 286
 287     None
 288
 289 # Store Word Byte-Reverse Indexed
 290
 291 X-Form
 292
 293 * stwbrx RS,RA,RB
 294
 295 Pseudo-code:
 296
 297     b <- (RA|0)
 298     EA <- b + (RB)
 299     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 300                    ||(RS)[32:39])
 301
 302 Special Registers Altered:
 303
 304     None
 305
 306 # Store Doubleword Byte-Reverse Indexed
 307
 308 X-Form
 309
 310 * stdbrx RS,RA,RB
 311
 312 Pseudo-code:
 313
 314     b <- (RA|0)
 315     EA <- b + (RB)
 316     MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
 317                     || (RS)[40:47] || (RS)[32:39]
 318                     || (RS)[24:31] || (RS)[16:23]
 319                     || (RS)[8:15]  || (RS)[0:7])
 320
 321 Special Registers Altered:
 322
 323     None
 324
 325 # Store Multiple Word
 326
 327 D-Form
 328
 329 * stmw RS,D(RA)
 330
 331 Pseudo-code:
 332
 333     b <- (RA|0)
 334     EA <- b + EXTS(D)
 335     r <- RS
 336     do while r <= 31
 337         MEM(EA, 4) <- GPR(r)[32:63]
 338         r <-  r + 1
 339         EA <-  EA + 4
 340
 341 Special Registers Altered:
 342
 343     None
 344