missing info
[libreriscv.git] / openpower / isa / fixedstore.mdwn
1 # Store Byte
2
3 D-Form
4
5 * stb RS,D(RA)
6
7 if RA = 0 then b <- 0
8 else b <- (RA)
9 EA <- b + EXTS(D)
10 MEM(EA, 1) <- (RS)[56:63]
11
12 # Store Byte Indexed
13
14 X-Form
15
16 * stbx RS,RA,RB
17
18 if RA = 0 then b <- 0
19 else b <- (RA)
20 EA <- b + (RB)
21 MEM(EA, 1) <- (RS)[56:63]
22
23 # Store Byte with Update
24
25 D-Form
26
27 * stbu RS,D(RA)
28
29 EA <- (RA) + EXTS(D)
30 MEM(EA, 1) <- (RS)[56:63]
31 RA <- EA
32
33 # Store Byte with Update Indexed
34
35 X-Form
36
37 * stbux RS,RA,RB
38
39 EA <- (RA) + (RB)
40 MEM(EA, 1) <- (RS)[56:63]
41 RA <- EA
42 # Store Halfword
43
44 D-Form
45
46 * sth RS,D(RA)
47
48 if RA = 0 then b <- 0
49 else b <- (RA)
50 EA <- b + EXTS(D)
51 MEM(EA, 2) <- (RS)[48:63]
52
53 # Store Halfword Indexed
54
55 X-Form
56
57 * sthx RS,RA,RB
58
59 if RA = 0 then b <- 0
60 else b <- (RA)
61 EA <- b + (RB)
62 MEM(EA, 2) <- (RS)[48:63]
63
64 # Store Halfword with Update
65
66 D-Form
67
68 * sthu RS,D(RA)
69
70 EA <- (RA) + EXTS(D)
71 MEM(EA, 2) <- (RS)[48:63]
72 RA <- EA
73
74 # Store Halfword with Update Indexed
75
76 X-Form
77
78 * sthux RS,RA,RB
79
80 EA <- (RA) + (RB)
81 MEM(EA, 2) <- (RS)[48:63]
82 RA <- EA
83
84 # Store Word
85
86 D-Form
87
88 * stw RS,D(RA)
89
90 if RA = 0 then b <- 0
91 else b <- (RA)
92 EA <- b + EXTS(D)
93 MEM(EA, 4) <- (RS)[32:63]
94
95 # Store Word Indexed
96
97 X-Form
98
99 * stwx RS,RA,RB
100
101 if RA = 0 then b <- 0
102 else b <- (RA)
103 EA <- b + (RB)
104 MEM(EA, 4) <- (RS)[32:63]
105
106 # Store Word with Update
107
108 D-Form
109
110 * stwu RS,D(RA)
111
112 EA <- (RA) + EXTS(D)
113 MEM(EA, 4) <- (RS) 32:63
114 RA <- EA
115
116 # Store Word with Update Indexed
117
118 X-Form
119
120 * stwux RS,RA,RB
121
122 EA <- (RA) + (RB)
123 MEM(EA, 4) <- (RS) 32:63
124 RA <- EA
125
126 # Store Doubleword
127
128 DS-Form
129
130 * std RS,DS(RA)
131
132 if RA = 0 then b <- 0
133 else b <- (RA)
134 EA <- b + EXTS(DS || 0b00)
135 MEM(EA, 8) <- (RS)
136
137 # Store Doubleword Indexed
138
139 X-Form
140
141 * stdx RS,RA,RB
142
143 if RA = 0 then b <- 0
144 else b <- (RA)
145 EA <- b + (RB)
146 MEM(EA, 8) <- (RS)
147
148 # Store Doubleword with Update
149
150 DS-Form
151
152 * stdu RS,DS(RA)
153
154 EA <- (RA) + EXTS(DS || 0b00)
155 MEM(EA, 8) <- (RS)
156 RA <- EA
157
158 # Store Doubleword with Update Indexed
159
160 X-Form
161
162 * stdux RS,RA,RB
163
164 EA <- (RA) + (RB)
165 MEM(EA, 8) <- (RS)
166 RA <- EA
167
168 # Store Quadword
169
170 DS-Form
171
172 * stq RSp,DS(RA)
173
174 if RA = 0 then b <- 0
175 else b <- (RA)
176 EA <- b + EXTS(DS || 0b00)
177 MEM(EA, 16) <- RSp
178
179 # Store Halfword Byte-Reverse Indexed
180
181 X-Form
182
183 * sthbrx RS,RA,RB
184
185 if RA = 0 then b <- 0
186 else b <- (RA)
187 EA <- b + (RB)
188 MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
189
190 # Store Word Byte-Reverse Indexed
191
192 X-Form
193
194 * stwbrx RS,RA,RB
195
196 if RA = 0 then b <- 0
197 else b <- (RA)
198 EA <- b + (RB)
199 MEM(EA, 4) <- (RS)[56:63] || (RS)[48:55] || (RS)[40:47]
200 ||(RS)[32:39]
201
202 # Store Doubleword Byte-Reverse Indexed
203
204 X-Form
205
206 * stdbrx RS,RA,RB
207
208 if RA = 0 then b <- 0
209 else b <- (RA)
210 EA <- b + (RB)
211 MEM(EA, 8) <- (RS) [56:63] || (RS)48:55]
212 || (RS)[40:47] || (RS)[32:39]
213 || (RS)[24:31] || (RS)[16:23]
214 || (RS)[8:15] || (RS)[0:7]
215
216 # Store Multiple Word
217
218 D-Form
219
220 * stmw RS,D(RA)
221
222 if RA = 0 then b <- 0
223 else b <- (RA)
224 EA <- b + EXTS(D)
225 r <- RS
226 do while r <= 31
227 MEM(EA, 4) <- GPR(r)[32:63]
228 r <- r + 1
229 EA <- EA + 4
230
231