openpower/isa/fixedstore.mdwn

   1 # Store Byte
   2
   3 D-Form
   4
   5 * stb RS,D(RA)
   6
   7     if RA = 0 then b <-  0
   8     else           b <-  (RA)
   9     EA <- b + EXTS(D)
  10     MEM(EA, 1) <- (RS)[56:63]
  11
  12 Special Registers Altered:
  13
  14     None
  15
  16 # Store Byte Indexed
  17
  18 X-Form
  19
  20 * stbx RS,RA,RB
  21
  22     if RA = 0 then b <- 0
  23     else           b <- (RA)
  24     EA <- b + (RB)
  25     MEM(EA, 1) <- (RS)[56:63]
  26
  27 Special Registers Altered:
  28
  29     None
  30
  31 # Store Byte with Update
  32
  33 D-Form
  34
  35 * stbu RS,D(RA)
  36
  37     EA <- (RA) + EXTS(D)
  38     MEM(EA, 1) <- (RS)[56:63]
  39     RA <- EA
  40
  41 Special Registers Altered:
  42
  43     None
  44
  45 # Store Byte with Update Indexed
  46
  47 X-Form
  48
  49 * stbux RS,RA,RB
  50
  51     EA <- (RA) + (RB)
  52     MEM(EA, 1) <- (RS)[56:63]
  53     RA <- EA
  54
  55 Special Registers Altered:
  56
  57     None
  58
  59 # Store Halfword
  60
  61 D-Form
  62
  63 * sth RS,D(RA)
  64
  65     if RA = 0 then b <-  0
  66     else           b <-  (RA)
  67     EA <- b + EXTS(D)
  68     MEM(EA, 2) <- (RS)[48:63]
  69
  70 Special Registers Altered:
  71
  72     None
  73
  74 # Store Halfword Indexed
  75
  76 X-Form
  77
  78 * sthx RS,RA,RB
  79
  80     if RA = 0 then b <- 0
  81     else           b <- (RA)
  82     EA <- b + (RB)
  83     MEM(EA, 2) <- (RS)[48:63]
  84
  85 Special Registers Altered:
  86
  87     None
  88
  89 # Store Halfword with Update
  90
  91 D-Form
  92
  93 * sthu RS,D(RA)
  94
  95     EA <- (RA) + EXTS(D)
  96     MEM(EA, 2) <- (RS)[48:63]
  97     RA <- EA
  98
  99 Special Registers Altered:
 100
 101     None
 102
 103 # Store Halfword with Update Indexed
 104
 105 X-Form
 106
 107 * sthux RS,RA,RB
 108
 109     EA <- (RA) + (RB)
 110     MEM(EA, 2) <- (RS)[48:63]
 111     RA <- EA
 112
 113 Special Registers Altered:
 114
 115     None
 116
 117 # Store Word
 118
 119 D-Form
 120
 121 * stw RS,D(RA)
 122
 123     if RA = 0 then b <-  0
 124     else           b <-  (RA)
 125     EA <- b + EXTS(D)
 126     MEM(EA, 4) <- (RS)[32:63]
 127
 128 Special Registers Altered:
 129
 130     None
 131
 132 # Store Word Indexed
 133
 134 X-Form
 135
 136 * stwx RS,RA,RB
 137
 138     if RA = 0 then b <- 0
 139     else           b <- (RA)
 140     EA <- b + (RB)
 141     MEM(EA, 4) <- (RS)[32:63]
 142
 143 Special Registers Altered:
 144
 145     None
 146
 147 # Store Word with Update
 148
 149 D-Form
 150
 151 * stwu RS,D(RA)
 152
 153     EA <- (RA) + EXTS(D)
 154     MEM(EA, 4) <- (RS) 32:63
 155     RA <- EA
 156
 157 Special Registers Altered:
 158
 159     None
 160
 161 # Store Word with Update Indexed
 162
 163 X-Form
 164
 165 * stwux RS,RA,RB
 166
 167     EA <- (RA) + (RB)
 168     MEM(EA, 4) <- (RS) 32:63
 169     RA <- EA
 170
 171 Special Registers Altered:
 172
 173     None
 174
 175 # Store Doubleword
 176
 177 DS-Form
 178
 179 * std RS,DS(RA)
 180
 181     if RA = 0 then b <-  0
 182     else           b <-  (RA)
 183     EA <- b + EXTS(DS || 0b00)
 184     MEM(EA, 8) <- (RS)
 185
 186 Special Registers Altered:
 187
 188     None
 189
 190 # Store Doubleword Indexed
 191
 192 X-Form
 193
 194 * stdx RS,RA,RB
 195
 196     if RA = 0 then b <- 0
 197     else           b <- (RA)
 198     EA <- b + (RB)
 199     MEM(EA, 8) <- (RS)
 200
 201 Special Registers Altered:
 202
 203     None
 204
 205 # Store Doubleword with Update
 206
 207 DS-Form
 208
 209 * stdu RS,DS(RA)
 210
 211     EA <- (RA) + EXTS(DS || 0b00)
 212     MEM(EA, 8) <- (RS)
 213     RA <- EA
 214
 215 Special Registers Altered:
 216
 217     None
 218
 219 # Store Doubleword with Update Indexed
 220
 221 X-Form
 222
 223 * stdux RS,RA,RB
 224
 225     EA <- (RA) + (RB)
 226     MEM(EA, 8) <- (RS)
 227     RA <- EA
 228
 229 Special Registers Altered:
 230
 231     None
 232
 233 # Store Quadword
 234
 235 DS-Form
 236
 237 * stq RSp,DS(RA)
 238
 239     if RA = 0 then b <-  0
 240     else           b <-  (RA)
 241     EA <- b + EXTS(DS || 0b00)
 242     MEM(EA, 16) <- RSp
 243
 244 Special Registers Altered:
 245
 246     None
 247
 248 # Store Halfword Byte-Reverse Indexed
 249
 250 X-Form
 251
 252 * sthbrx RS,RA,RB
 253
 254     if RA = 0 then b <- 0
 255     else           b <- (RA)
 256     EA <- b + (RB)
 257     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 258
 259 Special Registers Altered:
 260
 261     None
 262
 263 # Store Word Byte-Reverse Indexed
 264
 265 X-Form
 266
 267 * stwbrx RS,RA,RB
 268
 269     if RA = 0 then b <- 0
 270     else           b <- (RA)
 271     EA <- b + (RB)
 272     MEM(EA, 4) <- (RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 273                    ||(RS)[32:39]
 274
 275 Special Registers Altered:
 276
 277     None
 278
 279 # Store Doubleword Byte-Reverse Indexed
 280
 281 X-Form
 282
 283 * stdbrx RS,RA,RB
 284
 285     if RA = 0 then b <- 0
 286     else           b <- (RA)
 287     EA <- b + (RB)
 288     MEM(EA, 8) <- (RS) [56:63] || (RS)48:55]
 289     || (RS)[40:47] || (RS)[32:39]
 290     || (RS)[24:31] || (RS)[16:23]
 291     || (RS)[8:15]  || (RS)[0:7]
 292
 293 Special Registers Altered:
 294
 295     None
 296
 297 # Store Multiple Word
 298
 299 D-Form
 300
 301 * stmw RS,D(RA)
 302
 303     if RA = 0 then b <- 0
 304     else           b <- (RA)
 305     EA <- b + EXTS(D)
 306     r <- RS
 307     do while r <= 31
 308         MEM(EA, 4) <- GPR(r)[32:63]
 309         r <-  r + 1
 310         EA <-  EA + 4
 311
 312 Special Registers Altered:
 313
 314     None
 315